xref: /openbmc/linux/drivers/net/ethernet/ti/cpsw.c (revision a2cce7a9)
1 /*
2  * Texas Instruments Ethernet Switch Driver
3  *
4  * Copyright (C) 2012 Texas Instruments
5  *
6  * This program is free software; you can redistribute it and/or
7  * modify it under the terms of the GNU General Public License as
8  * published by the Free Software Foundation version 2.
9  *
10  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
11  * kind, whether express or implied; without even the implied warranty
12  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13  * GNU General Public License for more details.
14  */
15 
16 #include <linux/kernel.h>
17 #include <linux/io.h>
18 #include <linux/clk.h>
19 #include <linux/timer.h>
20 #include <linux/module.h>
21 #include <linux/platform_device.h>
22 #include <linux/irqreturn.h>
23 #include <linux/interrupt.h>
24 #include <linux/if_ether.h>
25 #include <linux/etherdevice.h>
26 #include <linux/netdevice.h>
27 #include <linux/net_tstamp.h>
28 #include <linux/phy.h>
29 #include <linux/workqueue.h>
30 #include <linux/delay.h>
31 #include <linux/pm_runtime.h>
32 #include <linux/of.h>
33 #include <linux/of_net.h>
34 #include <linux/of_device.h>
35 #include <linux/if_vlan.h>
36 
37 #include <linux/pinctrl/consumer.h>
38 
39 #include "cpsw.h"
40 #include "cpsw_ale.h"
41 #include "cpts.h"
42 #include "davinci_cpdma.h"
43 
44 #define CPSW_DEBUG	(NETIF_MSG_HW		| NETIF_MSG_WOL		| \
45 			 NETIF_MSG_DRV		| NETIF_MSG_LINK	| \
46 			 NETIF_MSG_IFUP		| NETIF_MSG_INTR	| \
47 			 NETIF_MSG_PROBE	| NETIF_MSG_TIMER	| \
48 			 NETIF_MSG_IFDOWN	| NETIF_MSG_RX_ERR	| \
49 			 NETIF_MSG_TX_ERR	| NETIF_MSG_TX_DONE	| \
50 			 NETIF_MSG_PKTDATA	| NETIF_MSG_TX_QUEUED	| \
51 			 NETIF_MSG_RX_STATUS)
52 
53 #define cpsw_info(priv, type, format, ...)		\
54 do {								\
55 	if (netif_msg_##type(priv) && net_ratelimit())		\
56 		dev_info(priv->dev, format, ## __VA_ARGS__);	\
57 } while (0)
58 
59 #define cpsw_err(priv, type, format, ...)		\
60 do {								\
61 	if (netif_msg_##type(priv) && net_ratelimit())		\
62 		dev_err(priv->dev, format, ## __VA_ARGS__);	\
63 } while (0)
64 
65 #define cpsw_dbg(priv, type, format, ...)		\
66 do {								\
67 	if (netif_msg_##type(priv) && net_ratelimit())		\
68 		dev_dbg(priv->dev, format, ## __VA_ARGS__);	\
69 } while (0)
70 
71 #define cpsw_notice(priv, type, format, ...)		\
72 do {								\
73 	if (netif_msg_##type(priv) && net_ratelimit())		\
74 		dev_notice(priv->dev, format, ## __VA_ARGS__);	\
75 } while (0)
76 
77 #define ALE_ALL_PORTS		0x7
78 
79 #define CPSW_MAJOR_VERSION(reg)		(reg >> 8 & 0x7)
80 #define CPSW_MINOR_VERSION(reg)		(reg & 0xff)
81 #define CPSW_RTL_VERSION(reg)		((reg >> 11) & 0x1f)
82 
83 #define CPSW_VERSION_1		0x19010a
84 #define CPSW_VERSION_2		0x19010c
85 #define CPSW_VERSION_3		0x19010f
86 #define CPSW_VERSION_4		0x190112
87 
88 #define HOST_PORT_NUM		0
89 #define SLIVER_SIZE		0x40
90 
91 #define CPSW1_HOST_PORT_OFFSET	0x028
92 #define CPSW1_SLAVE_OFFSET	0x050
93 #define CPSW1_SLAVE_SIZE	0x040
94 #define CPSW1_CPDMA_OFFSET	0x100
95 #define CPSW1_STATERAM_OFFSET	0x200
96 #define CPSW1_HW_STATS		0x400
97 #define CPSW1_CPTS_OFFSET	0x500
98 #define CPSW1_ALE_OFFSET	0x600
99 #define CPSW1_SLIVER_OFFSET	0x700
100 
101 #define CPSW2_HOST_PORT_OFFSET	0x108
102 #define CPSW2_SLAVE_OFFSET	0x200
103 #define CPSW2_SLAVE_SIZE	0x100
104 #define CPSW2_CPDMA_OFFSET	0x800
105 #define CPSW2_HW_STATS		0x900
106 #define CPSW2_STATERAM_OFFSET	0xa00
107 #define CPSW2_CPTS_OFFSET	0xc00
108 #define CPSW2_ALE_OFFSET	0xd00
109 #define CPSW2_SLIVER_OFFSET	0xd80
110 #define CPSW2_BD_OFFSET		0x2000
111 
112 #define CPDMA_RXTHRESH		0x0c0
113 #define CPDMA_RXFREE		0x0e0
114 #define CPDMA_TXHDP		0x00
115 #define CPDMA_RXHDP		0x20
116 #define CPDMA_TXCP		0x40
117 #define CPDMA_RXCP		0x60
118 
119 #define CPSW_POLL_WEIGHT	64
120 #define CPSW_MIN_PACKET_SIZE	60
121 #define CPSW_MAX_PACKET_SIZE	(1500 + 14 + 4 + 4)
122 
123 #define RX_PRIORITY_MAPPING	0x76543210
124 #define TX_PRIORITY_MAPPING	0x33221100
125 #define CPDMA_TX_PRIORITY_MAP	0x76543210
126 
127 #define CPSW_VLAN_AWARE		BIT(1)
128 #define CPSW_ALE_VLAN_AWARE	1
129 
130 #define CPSW_FIFO_NORMAL_MODE		(0 << 16)
131 #define CPSW_FIFO_DUAL_MAC_MODE		(1 << 16)
132 #define CPSW_FIFO_RATE_LIMIT_MODE	(2 << 16)
133 
134 #define CPSW_INTPACEEN		(0x3f << 16)
135 #define CPSW_INTPRESCALE_MASK	(0x7FF << 0)
136 #define CPSW_CMINTMAX_CNT	63
137 #define CPSW_CMINTMIN_CNT	2
138 #define CPSW_CMINTMAX_INTVL	(1000 / CPSW_CMINTMIN_CNT)
139 #define CPSW_CMINTMIN_INTVL	((1000 / CPSW_CMINTMAX_CNT) + 1)
140 
141 #define cpsw_slave_index(priv)				\
142 		((priv->data.dual_emac) ? priv->emac_port :	\
143 		priv->data.active_slave)
144 
145 static int debug_level;
146 module_param(debug_level, int, 0);
147 MODULE_PARM_DESC(debug_level, "cpsw debug level (NETIF_MSG bits)");
148 
149 static int ale_ageout = 10;
150 module_param(ale_ageout, int, 0);
151 MODULE_PARM_DESC(ale_ageout, "cpsw ale ageout interval (seconds)");
152 
153 static int rx_packet_max = CPSW_MAX_PACKET_SIZE;
154 module_param(rx_packet_max, int, 0);
155 MODULE_PARM_DESC(rx_packet_max, "maximum receive packet size (bytes)");
156 
157 struct cpsw_wr_regs {
158 	u32	id_ver;
159 	u32	soft_reset;
160 	u32	control;
161 	u32	int_control;
162 	u32	rx_thresh_en;
163 	u32	rx_en;
164 	u32	tx_en;
165 	u32	misc_en;
166 	u32	mem_allign1[8];
167 	u32	rx_thresh_stat;
168 	u32	rx_stat;
169 	u32	tx_stat;
170 	u32	misc_stat;
171 	u32	mem_allign2[8];
172 	u32	rx_imax;
173 	u32	tx_imax;
174 
175 };
176 
177 struct cpsw_ss_regs {
178 	u32	id_ver;
179 	u32	control;
180 	u32	soft_reset;
181 	u32	stat_port_en;
182 	u32	ptype;
183 	u32	soft_idle;
184 	u32	thru_rate;
185 	u32	gap_thresh;
186 	u32	tx_start_wds;
187 	u32	flow_control;
188 	u32	vlan_ltype;
189 	u32	ts_ltype;
190 	u32	dlr_ltype;
191 };
192 
193 /* CPSW_PORT_V1 */
194 #define CPSW1_MAX_BLKS      0x00 /* Maximum FIFO Blocks */
195 #define CPSW1_BLK_CNT       0x04 /* FIFO Block Usage Count (Read Only) */
196 #define CPSW1_TX_IN_CTL     0x08 /* Transmit FIFO Control */
197 #define CPSW1_PORT_VLAN     0x0c /* VLAN Register */
198 #define CPSW1_TX_PRI_MAP    0x10 /* Tx Header Priority to Switch Pri Mapping */
199 #define CPSW1_TS_CTL        0x14 /* Time Sync Control */
200 #define CPSW1_TS_SEQ_LTYPE  0x18 /* Time Sync Sequence ID Offset and Msg Type */
201 #define CPSW1_TS_VLAN       0x1c /* Time Sync VLAN1 and VLAN2 */
202 
203 /* CPSW_PORT_V2 */
204 #define CPSW2_CONTROL       0x00 /* Control Register */
205 #define CPSW2_MAX_BLKS      0x08 /* Maximum FIFO Blocks */
206 #define CPSW2_BLK_CNT       0x0c /* FIFO Block Usage Count (Read Only) */
207 #define CPSW2_TX_IN_CTL     0x10 /* Transmit FIFO Control */
208 #define CPSW2_PORT_VLAN     0x14 /* VLAN Register */
209 #define CPSW2_TX_PRI_MAP    0x18 /* Tx Header Priority to Switch Pri Mapping */
210 #define CPSW2_TS_SEQ_MTYPE  0x1c /* Time Sync Sequence ID Offset and Msg Type */
211 
212 /* CPSW_PORT_V1 and V2 */
213 #define SA_LO               0x20 /* CPGMAC_SL Source Address Low */
214 #define SA_HI               0x24 /* CPGMAC_SL Source Address High */
215 #define SEND_PERCENT        0x28 /* Transmit Queue Send Percentages */
216 
217 /* CPSW_PORT_V2 only */
218 #define RX_DSCP_PRI_MAP0    0x30 /* Rx DSCP Priority to Rx Packet Mapping */
219 #define RX_DSCP_PRI_MAP1    0x34 /* Rx DSCP Priority to Rx Packet Mapping */
220 #define RX_DSCP_PRI_MAP2    0x38 /* Rx DSCP Priority to Rx Packet Mapping */
221 #define RX_DSCP_PRI_MAP3    0x3c /* Rx DSCP Priority to Rx Packet Mapping */
222 #define RX_DSCP_PRI_MAP4    0x40 /* Rx DSCP Priority to Rx Packet Mapping */
223 #define RX_DSCP_PRI_MAP5    0x44 /* Rx DSCP Priority to Rx Packet Mapping */
224 #define RX_DSCP_PRI_MAP6    0x48 /* Rx DSCP Priority to Rx Packet Mapping */
225 #define RX_DSCP_PRI_MAP7    0x4c /* Rx DSCP Priority to Rx Packet Mapping */
226 
227 /* Bit definitions for the CPSW2_CONTROL register */
228 #define PASS_PRI_TAGGED     (1<<24) /* Pass Priority Tagged */
229 #define VLAN_LTYPE2_EN      (1<<21) /* VLAN LTYPE 2 enable */
230 #define VLAN_LTYPE1_EN      (1<<20) /* VLAN LTYPE 1 enable */
231 #define DSCP_PRI_EN         (1<<16) /* DSCP Priority Enable */
232 #define TS_320              (1<<14) /* Time Sync Dest Port 320 enable */
233 #define TS_319              (1<<13) /* Time Sync Dest Port 319 enable */
234 #define TS_132              (1<<12) /* Time Sync Dest IP Addr 132 enable */
235 #define TS_131              (1<<11) /* Time Sync Dest IP Addr 131 enable */
236 #define TS_130              (1<<10) /* Time Sync Dest IP Addr 130 enable */
237 #define TS_129              (1<<9)  /* Time Sync Dest IP Addr 129 enable */
238 #define TS_TTL_NONZERO      (1<<8)  /* Time Sync Time To Live Non-zero enable */
239 #define TS_ANNEX_F_EN       (1<<6)  /* Time Sync Annex F enable */
240 #define TS_ANNEX_D_EN       (1<<4)  /* Time Sync Annex D enable */
241 #define TS_LTYPE2_EN        (1<<3)  /* Time Sync LTYPE 2 enable */
242 #define TS_LTYPE1_EN        (1<<2)  /* Time Sync LTYPE 1 enable */
243 #define TS_TX_EN            (1<<1)  /* Time Sync Transmit Enable */
244 #define TS_RX_EN            (1<<0)  /* Time Sync Receive Enable */
245 
246 #define CTRL_V2_TS_BITS \
247 	(TS_320 | TS_319 | TS_132 | TS_131 | TS_130 | TS_129 |\
248 	 TS_TTL_NONZERO  | TS_ANNEX_D_EN | TS_LTYPE1_EN)
249 
250 #define CTRL_V2_ALL_TS_MASK (CTRL_V2_TS_BITS | TS_TX_EN | TS_RX_EN)
251 #define CTRL_V2_TX_TS_BITS  (CTRL_V2_TS_BITS | TS_TX_EN)
252 #define CTRL_V2_RX_TS_BITS  (CTRL_V2_TS_BITS | TS_RX_EN)
253 
254 
255 #define CTRL_V3_TS_BITS \
256 	(TS_320 | TS_319 | TS_132 | TS_131 | TS_130 | TS_129 |\
257 	 TS_TTL_NONZERO | TS_ANNEX_F_EN | TS_ANNEX_D_EN |\
258 	 TS_LTYPE1_EN)
259 
260 #define CTRL_V3_ALL_TS_MASK (CTRL_V3_TS_BITS | TS_TX_EN | TS_RX_EN)
261 #define CTRL_V3_TX_TS_BITS  (CTRL_V3_TS_BITS | TS_TX_EN)
262 #define CTRL_V3_RX_TS_BITS  (CTRL_V3_TS_BITS | TS_RX_EN)
263 
264 /* Bit definitions for the CPSW2_TS_SEQ_MTYPE register */
265 #define TS_SEQ_ID_OFFSET_SHIFT   (16)    /* Time Sync Sequence ID Offset */
266 #define TS_SEQ_ID_OFFSET_MASK    (0x3f)
267 #define TS_MSG_TYPE_EN_SHIFT     (0)     /* Time Sync Message Type Enable */
268 #define TS_MSG_TYPE_EN_MASK      (0xffff)
269 
270 /* The PTP event messages - Sync, Delay_Req, Pdelay_Req, and Pdelay_Resp. */
271 #define EVENT_MSG_BITS ((1<<0) | (1<<1) | (1<<2) | (1<<3))
272 
273 /* Bit definitions for the CPSW1_TS_CTL register */
274 #define CPSW_V1_TS_RX_EN		BIT(0)
275 #define CPSW_V1_TS_TX_EN		BIT(4)
276 #define CPSW_V1_MSG_TYPE_OFS		16
277 
278 /* Bit definitions for the CPSW1_TS_SEQ_LTYPE register */
279 #define CPSW_V1_SEQ_ID_OFS_SHIFT	16
280 
281 struct cpsw_host_regs {
282 	u32	max_blks;
283 	u32	blk_cnt;
284 	u32	tx_in_ctl;
285 	u32	port_vlan;
286 	u32	tx_pri_map;
287 	u32	cpdma_tx_pri_map;
288 	u32	cpdma_rx_chan_map;
289 };
290 
291 struct cpsw_sliver_regs {
292 	u32	id_ver;
293 	u32	mac_control;
294 	u32	mac_status;
295 	u32	soft_reset;
296 	u32	rx_maxlen;
297 	u32	__reserved_0;
298 	u32	rx_pause;
299 	u32	tx_pause;
300 	u32	__reserved_1;
301 	u32	rx_pri_map;
302 };
303 
304 struct cpsw_hw_stats {
305 	u32	rxgoodframes;
306 	u32	rxbroadcastframes;
307 	u32	rxmulticastframes;
308 	u32	rxpauseframes;
309 	u32	rxcrcerrors;
310 	u32	rxaligncodeerrors;
311 	u32	rxoversizedframes;
312 	u32	rxjabberframes;
313 	u32	rxundersizedframes;
314 	u32	rxfragments;
315 	u32	__pad_0[2];
316 	u32	rxoctets;
317 	u32	txgoodframes;
318 	u32	txbroadcastframes;
319 	u32	txmulticastframes;
320 	u32	txpauseframes;
321 	u32	txdeferredframes;
322 	u32	txcollisionframes;
323 	u32	txsinglecollframes;
324 	u32	txmultcollframes;
325 	u32	txexcessivecollisions;
326 	u32	txlatecollisions;
327 	u32	txunderrun;
328 	u32	txcarriersenseerrors;
329 	u32	txoctets;
330 	u32	octetframes64;
331 	u32	octetframes65t127;
332 	u32	octetframes128t255;
333 	u32	octetframes256t511;
334 	u32	octetframes512t1023;
335 	u32	octetframes1024tup;
336 	u32	netoctets;
337 	u32	rxsofoverruns;
338 	u32	rxmofoverruns;
339 	u32	rxdmaoverruns;
340 };
341 
342 struct cpsw_slave {
343 	void __iomem			*regs;
344 	struct cpsw_sliver_regs __iomem	*sliver;
345 	int				slave_num;
346 	u32				mac_control;
347 	struct cpsw_slave_data		*data;
348 	struct phy_device		*phy;
349 	struct net_device		*ndev;
350 	u32				port_vlan;
351 	u32				open_stat;
352 };
353 
354 static inline u32 slave_read(struct cpsw_slave *slave, u32 offset)
355 {
356 	return __raw_readl(slave->regs + offset);
357 }
358 
359 static inline void slave_write(struct cpsw_slave *slave, u32 val, u32 offset)
360 {
361 	__raw_writel(val, slave->regs + offset);
362 }
363 
364 struct cpsw_priv {
365 	spinlock_t			lock;
366 	struct platform_device		*pdev;
367 	struct net_device		*ndev;
368 	struct napi_struct		napi_rx;
369 	struct napi_struct		napi_tx;
370 	struct device			*dev;
371 	struct cpsw_platform_data	data;
372 	struct cpsw_ss_regs __iomem	*regs;
373 	struct cpsw_wr_regs __iomem	*wr_regs;
374 	u8 __iomem			*hw_stats;
375 	struct cpsw_host_regs __iomem	*host_port_regs;
376 	u32				msg_enable;
377 	u32				version;
378 	u32				coal_intvl;
379 	u32				bus_freq_mhz;
380 	int				rx_packet_max;
381 	int				host_port;
382 	struct clk			*clk;
383 	u8				mac_addr[ETH_ALEN];
384 	struct cpsw_slave		*slaves;
385 	struct cpdma_ctlr		*dma;
386 	struct cpdma_chan		*txch, *rxch;
387 	struct cpsw_ale			*ale;
388 	bool				rx_pause;
389 	bool				tx_pause;
390 	bool				quirk_irq;
391 	bool				rx_irq_disabled;
392 	bool				tx_irq_disabled;
393 	/* snapshot of IRQ numbers */
394 	u32 irqs_table[4];
395 	u32 num_irqs;
396 	struct cpts *cpts;
397 	u32 emac_port;
398 };
399 
400 struct cpsw_stats {
401 	char stat_string[ETH_GSTRING_LEN];
402 	int type;
403 	int sizeof_stat;
404 	int stat_offset;
405 };
406 
407 enum {
408 	CPSW_STATS,
409 	CPDMA_RX_STATS,
410 	CPDMA_TX_STATS,
411 };
412 
413 #define CPSW_STAT(m)		CPSW_STATS,				\
414 				sizeof(((struct cpsw_hw_stats *)0)->m), \
415 				offsetof(struct cpsw_hw_stats, m)
416 #define CPDMA_RX_STAT(m)	CPDMA_RX_STATS,				   \
417 				sizeof(((struct cpdma_chan_stats *)0)->m), \
418 				offsetof(struct cpdma_chan_stats, m)
419 #define CPDMA_TX_STAT(m)	CPDMA_TX_STATS,				   \
420 				sizeof(((struct cpdma_chan_stats *)0)->m), \
421 				offsetof(struct cpdma_chan_stats, m)
422 
423 static const struct cpsw_stats cpsw_gstrings_stats[] = {
424 	{ "Good Rx Frames", CPSW_STAT(rxgoodframes) },
425 	{ "Broadcast Rx Frames", CPSW_STAT(rxbroadcastframes) },
426 	{ "Multicast Rx Frames", CPSW_STAT(rxmulticastframes) },
427 	{ "Pause Rx Frames", CPSW_STAT(rxpauseframes) },
428 	{ "Rx CRC Errors", CPSW_STAT(rxcrcerrors) },
429 	{ "Rx Align/Code Errors", CPSW_STAT(rxaligncodeerrors) },
430 	{ "Oversize Rx Frames", CPSW_STAT(rxoversizedframes) },
431 	{ "Rx Jabbers", CPSW_STAT(rxjabberframes) },
432 	{ "Undersize (Short) Rx Frames", CPSW_STAT(rxundersizedframes) },
433 	{ "Rx Fragments", CPSW_STAT(rxfragments) },
434 	{ "Rx Octets", CPSW_STAT(rxoctets) },
435 	{ "Good Tx Frames", CPSW_STAT(txgoodframes) },
436 	{ "Broadcast Tx Frames", CPSW_STAT(txbroadcastframes) },
437 	{ "Multicast Tx Frames", CPSW_STAT(txmulticastframes) },
438 	{ "Pause Tx Frames", CPSW_STAT(txpauseframes) },
439 	{ "Deferred Tx Frames", CPSW_STAT(txdeferredframes) },
440 	{ "Collisions", CPSW_STAT(txcollisionframes) },
441 	{ "Single Collision Tx Frames", CPSW_STAT(txsinglecollframes) },
442 	{ "Multiple Collision Tx Frames", CPSW_STAT(txmultcollframes) },
443 	{ "Excessive Collisions", CPSW_STAT(txexcessivecollisions) },
444 	{ "Late Collisions", CPSW_STAT(txlatecollisions) },
445 	{ "Tx Underrun", CPSW_STAT(txunderrun) },
446 	{ "Carrier Sense Errors", CPSW_STAT(txcarriersenseerrors) },
447 	{ "Tx Octets", CPSW_STAT(txoctets) },
448 	{ "Rx + Tx 64 Octet Frames", CPSW_STAT(octetframes64) },
449 	{ "Rx + Tx 65-127 Octet Frames", CPSW_STAT(octetframes65t127) },
450 	{ "Rx + Tx 128-255 Octet Frames", CPSW_STAT(octetframes128t255) },
451 	{ "Rx + Tx 256-511 Octet Frames", CPSW_STAT(octetframes256t511) },
452 	{ "Rx + Tx 512-1023 Octet Frames", CPSW_STAT(octetframes512t1023) },
453 	{ "Rx + Tx 1024-Up Octet Frames", CPSW_STAT(octetframes1024tup) },
454 	{ "Net Octets", CPSW_STAT(netoctets) },
455 	{ "Rx Start of Frame Overruns", CPSW_STAT(rxsofoverruns) },
456 	{ "Rx Middle of Frame Overruns", CPSW_STAT(rxmofoverruns) },
457 	{ "Rx DMA Overruns", CPSW_STAT(rxdmaoverruns) },
458 	{ "Rx DMA chan: head_enqueue", CPDMA_RX_STAT(head_enqueue) },
459 	{ "Rx DMA chan: tail_enqueue", CPDMA_RX_STAT(tail_enqueue) },
460 	{ "Rx DMA chan: pad_enqueue", CPDMA_RX_STAT(pad_enqueue) },
461 	{ "Rx DMA chan: misqueued", CPDMA_RX_STAT(misqueued) },
462 	{ "Rx DMA chan: desc_alloc_fail", CPDMA_RX_STAT(desc_alloc_fail) },
463 	{ "Rx DMA chan: pad_alloc_fail", CPDMA_RX_STAT(pad_alloc_fail) },
464 	{ "Rx DMA chan: runt_receive_buf", CPDMA_RX_STAT(runt_receive_buff) },
465 	{ "Rx DMA chan: runt_transmit_buf", CPDMA_RX_STAT(runt_transmit_buff) },
466 	{ "Rx DMA chan: empty_dequeue", CPDMA_RX_STAT(empty_dequeue) },
467 	{ "Rx DMA chan: busy_dequeue", CPDMA_RX_STAT(busy_dequeue) },
468 	{ "Rx DMA chan: good_dequeue", CPDMA_RX_STAT(good_dequeue) },
469 	{ "Rx DMA chan: requeue", CPDMA_RX_STAT(requeue) },
470 	{ "Rx DMA chan: teardown_dequeue", CPDMA_RX_STAT(teardown_dequeue) },
471 	{ "Tx DMA chan: head_enqueue", CPDMA_TX_STAT(head_enqueue) },
472 	{ "Tx DMA chan: tail_enqueue", CPDMA_TX_STAT(tail_enqueue) },
473 	{ "Tx DMA chan: pad_enqueue", CPDMA_TX_STAT(pad_enqueue) },
474 	{ "Tx DMA chan: misqueued", CPDMA_TX_STAT(misqueued) },
475 	{ "Tx DMA chan: desc_alloc_fail", CPDMA_TX_STAT(desc_alloc_fail) },
476 	{ "Tx DMA chan: pad_alloc_fail", CPDMA_TX_STAT(pad_alloc_fail) },
477 	{ "Tx DMA chan: runt_receive_buf", CPDMA_TX_STAT(runt_receive_buff) },
478 	{ "Tx DMA chan: runt_transmit_buf", CPDMA_TX_STAT(runt_transmit_buff) },
479 	{ "Tx DMA chan: empty_dequeue", CPDMA_TX_STAT(empty_dequeue) },
480 	{ "Tx DMA chan: busy_dequeue", CPDMA_TX_STAT(busy_dequeue) },
481 	{ "Tx DMA chan: good_dequeue", CPDMA_TX_STAT(good_dequeue) },
482 	{ "Tx DMA chan: requeue", CPDMA_TX_STAT(requeue) },
483 	{ "Tx DMA chan: teardown_dequeue", CPDMA_TX_STAT(teardown_dequeue) },
484 };
485 
486 #define CPSW_STATS_LEN	ARRAY_SIZE(cpsw_gstrings_stats)
487 
488 #define napi_to_priv(napi)	container_of(napi, struct cpsw_priv, napi)
489 #define for_each_slave(priv, func, arg...)				\
490 	do {								\
491 		struct cpsw_slave *slave;				\
492 		int n;							\
493 		if (priv->data.dual_emac)				\
494 			(func)((priv)->slaves + priv->emac_port, ##arg);\
495 		else							\
496 			for (n = (priv)->data.slaves,			\
497 					slave = (priv)->slaves;		\
498 					n; n--)				\
499 				(func)(slave++, ##arg);			\
500 	} while (0)
501 #define cpsw_get_slave_ndev(priv, __slave_no__)				\
502 	((__slave_no__ < priv->data.slaves) ?				\
503 		priv->slaves[__slave_no__].ndev : NULL)
504 #define cpsw_get_slave_priv(priv, __slave_no__)				\
505 	(((__slave_no__ < priv->data.slaves) &&				\
506 		(priv->slaves[__slave_no__].ndev)) ?			\
507 		netdev_priv(priv->slaves[__slave_no__].ndev) : NULL)	\
508 
509 #define cpsw_dual_emac_src_port_detect(status, priv, ndev, skb)		\
510 	do {								\
511 		if (!priv->data.dual_emac)				\
512 			break;						\
513 		if (CPDMA_RX_SOURCE_PORT(status) == 1) {		\
514 			ndev = cpsw_get_slave_ndev(priv, 0);		\
515 			priv = netdev_priv(ndev);			\
516 			skb->dev = ndev;				\
517 		} else if (CPDMA_RX_SOURCE_PORT(status) == 2) {		\
518 			ndev = cpsw_get_slave_ndev(priv, 1);		\
519 			priv = netdev_priv(ndev);			\
520 			skb->dev = ndev;				\
521 		}							\
522 	} while (0)
523 #define cpsw_add_mcast(priv, addr)					\
524 	do {								\
525 		if (priv->data.dual_emac) {				\
526 			struct cpsw_slave *slave = priv->slaves +	\
527 						priv->emac_port;	\
528 			int slave_port = cpsw_get_slave_port(priv,	\
529 						slave->slave_num);	\
530 			cpsw_ale_add_mcast(priv->ale, addr,		\
531 				1 << slave_port | 1 << priv->host_port,	\
532 				ALE_VLAN, slave->port_vlan, 0);		\
533 		} else {						\
534 			cpsw_ale_add_mcast(priv->ale, addr,		\
535 				ALE_ALL_PORTS << priv->host_port,	\
536 				0, 0, 0);				\
537 		}							\
538 	} while (0)
539 
540 static inline int cpsw_get_slave_port(struct cpsw_priv *priv, u32 slave_num)
541 {
542 	if (priv->host_port == 0)
543 		return slave_num + 1;
544 	else
545 		return slave_num;
546 }
547 
548 static void cpsw_set_promiscious(struct net_device *ndev, bool enable)
549 {
550 	struct cpsw_priv *priv = netdev_priv(ndev);
551 	struct cpsw_ale *ale = priv->ale;
552 	int i;
553 
554 	if (priv->data.dual_emac) {
555 		bool flag = false;
556 
557 		/* Enabling promiscuous mode for one interface will be
558 		 * common for both the interface as the interface shares
559 		 * the same hardware resource.
560 		 */
561 		for (i = 0; i < priv->data.slaves; i++)
562 			if (priv->slaves[i].ndev->flags & IFF_PROMISC)
563 				flag = true;
564 
565 		if (!enable && flag) {
566 			enable = true;
567 			dev_err(&ndev->dev, "promiscuity not disabled as the other interface is still in promiscuity mode\n");
568 		}
569 
570 		if (enable) {
571 			/* Enable Bypass */
572 			cpsw_ale_control_set(ale, 0, ALE_BYPASS, 1);
573 
574 			dev_dbg(&ndev->dev, "promiscuity enabled\n");
575 		} else {
576 			/* Disable Bypass */
577 			cpsw_ale_control_set(ale, 0, ALE_BYPASS, 0);
578 			dev_dbg(&ndev->dev, "promiscuity disabled\n");
579 		}
580 	} else {
581 		if (enable) {
582 			unsigned long timeout = jiffies + HZ;
583 
584 			/* Disable Learn for all ports (host is port 0 and slaves are port 1 and up */
585 			for (i = 0; i <= priv->data.slaves; i++) {
586 				cpsw_ale_control_set(ale, i,
587 						     ALE_PORT_NOLEARN, 1);
588 				cpsw_ale_control_set(ale, i,
589 						     ALE_PORT_NO_SA_UPDATE, 1);
590 			}
591 
592 			/* Clear All Untouched entries */
593 			cpsw_ale_control_set(ale, 0, ALE_AGEOUT, 1);
594 			do {
595 				cpu_relax();
596 				if (cpsw_ale_control_get(ale, 0, ALE_AGEOUT))
597 					break;
598 			} while (time_after(timeout, jiffies));
599 			cpsw_ale_control_set(ale, 0, ALE_AGEOUT, 1);
600 
601 			/* Clear all mcast from ALE */
602 			cpsw_ale_flush_multicast(ale, ALE_ALL_PORTS <<
603 						 priv->host_port, -1);
604 
605 			/* Flood All Unicast Packets to Host port */
606 			cpsw_ale_control_set(ale, 0, ALE_P0_UNI_FLOOD, 1);
607 			dev_dbg(&ndev->dev, "promiscuity enabled\n");
608 		} else {
609 			/* Don't Flood All Unicast Packets to Host port */
610 			cpsw_ale_control_set(ale, 0, ALE_P0_UNI_FLOOD, 0);
611 
612 			/* Enable Learn for all ports (host is port 0 and slaves are port 1 and up */
613 			for (i = 0; i <= priv->data.slaves; i++) {
614 				cpsw_ale_control_set(ale, i,
615 						     ALE_PORT_NOLEARN, 0);
616 				cpsw_ale_control_set(ale, i,
617 						     ALE_PORT_NO_SA_UPDATE, 0);
618 			}
619 			dev_dbg(&ndev->dev, "promiscuity disabled\n");
620 		}
621 	}
622 }
623 
624 static void cpsw_ndo_set_rx_mode(struct net_device *ndev)
625 {
626 	struct cpsw_priv *priv = netdev_priv(ndev);
627 	int vid;
628 
629 	if (priv->data.dual_emac)
630 		vid = priv->slaves[priv->emac_port].port_vlan;
631 	else
632 		vid = priv->data.default_vlan;
633 
634 	if (ndev->flags & IFF_PROMISC) {
635 		/* Enable promiscuous mode */
636 		cpsw_set_promiscious(ndev, true);
637 		cpsw_ale_set_allmulti(priv->ale, IFF_ALLMULTI);
638 		return;
639 	} else {
640 		/* Disable promiscuous mode */
641 		cpsw_set_promiscious(ndev, false);
642 	}
643 
644 	/* Restore allmulti on vlans if necessary */
645 	cpsw_ale_set_allmulti(priv->ale, priv->ndev->flags & IFF_ALLMULTI);
646 
647 	/* Clear all mcast from ALE */
648 	cpsw_ale_flush_multicast(priv->ale, ALE_ALL_PORTS << priv->host_port,
649 				 vid);
650 
651 	if (!netdev_mc_empty(ndev)) {
652 		struct netdev_hw_addr *ha;
653 
654 		/* program multicast address list into ALE register */
655 		netdev_for_each_mc_addr(ha, ndev) {
656 			cpsw_add_mcast(priv, (u8 *)ha->addr);
657 		}
658 	}
659 }
660 
661 static void cpsw_intr_enable(struct cpsw_priv *priv)
662 {
663 	__raw_writel(0xFF, &priv->wr_regs->tx_en);
664 	__raw_writel(0xFF, &priv->wr_regs->rx_en);
665 
666 	cpdma_ctlr_int_ctrl(priv->dma, true);
667 	return;
668 }
669 
670 static void cpsw_intr_disable(struct cpsw_priv *priv)
671 {
672 	__raw_writel(0, &priv->wr_regs->tx_en);
673 	__raw_writel(0, &priv->wr_regs->rx_en);
674 
675 	cpdma_ctlr_int_ctrl(priv->dma, false);
676 	return;
677 }
678 
679 static void cpsw_tx_handler(void *token, int len, int status)
680 {
681 	struct sk_buff		*skb = token;
682 	struct net_device	*ndev = skb->dev;
683 	struct cpsw_priv	*priv = netdev_priv(ndev);
684 
685 	/* Check whether the queue is stopped due to stalled tx dma, if the
686 	 * queue is stopped then start the queue as we have free desc for tx
687 	 */
688 	if (unlikely(netif_queue_stopped(ndev)))
689 		netif_wake_queue(ndev);
690 	cpts_tx_timestamp(priv->cpts, skb);
691 	ndev->stats.tx_packets++;
692 	ndev->stats.tx_bytes += len;
693 	dev_kfree_skb_any(skb);
694 }
695 
696 static void cpsw_rx_handler(void *token, int len, int status)
697 {
698 	struct sk_buff		*skb = token;
699 	struct sk_buff		*new_skb;
700 	struct net_device	*ndev = skb->dev;
701 	struct cpsw_priv	*priv = netdev_priv(ndev);
702 	int			ret = 0;
703 
704 	cpsw_dual_emac_src_port_detect(status, priv, ndev, skb);
705 
706 	if (unlikely(status < 0) || unlikely(!netif_running(ndev))) {
707 		bool ndev_status = false;
708 		struct cpsw_slave *slave = priv->slaves;
709 		int n;
710 
711 		if (priv->data.dual_emac) {
712 			/* In dual emac mode check for all interfaces */
713 			for (n = priv->data.slaves; n; n--, slave++)
714 				if (netif_running(slave->ndev))
715 					ndev_status = true;
716 		}
717 
718 		if (ndev_status && (status >= 0)) {
719 			/* The packet received is for the interface which
720 			 * is already down and the other interface is up
721 			 * and running, instead of freeing which results
722 			 * in reducing of the number of rx descriptor in
723 			 * DMA engine, requeue skb back to cpdma.
724 			 */
725 			new_skb = skb;
726 			goto requeue;
727 		}
728 
729 		/* the interface is going down, skbs are purged */
730 		dev_kfree_skb_any(skb);
731 		return;
732 	}
733 
734 	new_skb = netdev_alloc_skb_ip_align(ndev, priv->rx_packet_max);
735 	if (new_skb) {
736 		skb_put(skb, len);
737 		cpts_rx_timestamp(priv->cpts, skb);
738 		skb->protocol = eth_type_trans(skb, ndev);
739 		netif_receive_skb(skb);
740 		ndev->stats.rx_bytes += len;
741 		ndev->stats.rx_packets++;
742 	} else {
743 		ndev->stats.rx_dropped++;
744 		new_skb = skb;
745 	}
746 
747 requeue:
748 	ret = cpdma_chan_submit(priv->rxch, new_skb, new_skb->data,
749 			skb_tailroom(new_skb), 0);
750 	if (WARN_ON(ret < 0))
751 		dev_kfree_skb_any(new_skb);
752 }
753 
754 static irqreturn_t cpsw_tx_interrupt(int irq, void *dev_id)
755 {
756 	struct cpsw_priv *priv = dev_id;
757 
758 	writel(0, &priv->wr_regs->tx_en);
759 	cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_TX);
760 
761 	if (priv->quirk_irq) {
762 		disable_irq_nosync(priv->irqs_table[1]);
763 		priv->tx_irq_disabled = true;
764 	}
765 
766 	napi_schedule(&priv->napi_tx);
767 	return IRQ_HANDLED;
768 }
769 
770 static irqreturn_t cpsw_rx_interrupt(int irq, void *dev_id)
771 {
772 	struct cpsw_priv *priv = dev_id;
773 
774 	cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_RX);
775 	writel(0, &priv->wr_regs->rx_en);
776 
777 	if (priv->quirk_irq) {
778 		disable_irq_nosync(priv->irqs_table[0]);
779 		priv->rx_irq_disabled = true;
780 	}
781 
782 	napi_schedule(&priv->napi_rx);
783 	return IRQ_HANDLED;
784 }
785 
786 static int cpsw_tx_poll(struct napi_struct *napi_tx, int budget)
787 {
788 	struct cpsw_priv	*priv = napi_to_priv(napi_tx);
789 	int			num_tx;
790 
791 	num_tx = cpdma_chan_process(priv->txch, budget);
792 	if (num_tx < budget) {
793 		napi_complete(napi_tx);
794 		writel(0xff, &priv->wr_regs->tx_en);
795 		if (priv->quirk_irq && priv->tx_irq_disabled) {
796 			priv->tx_irq_disabled = false;
797 			enable_irq(priv->irqs_table[1]);
798 		}
799 	}
800 
801 	if (num_tx)
802 		cpsw_dbg(priv, intr, "poll %d tx pkts\n", num_tx);
803 
804 	return num_tx;
805 }
806 
807 static int cpsw_rx_poll(struct napi_struct *napi_rx, int budget)
808 {
809 	struct cpsw_priv	*priv = napi_to_priv(napi_rx);
810 	int			num_rx;
811 
812 	num_rx = cpdma_chan_process(priv->rxch, budget);
813 	if (num_rx < budget) {
814 		napi_complete(napi_rx);
815 		writel(0xff, &priv->wr_regs->rx_en);
816 		if (priv->quirk_irq && priv->rx_irq_disabled) {
817 			priv->rx_irq_disabled = false;
818 			enable_irq(priv->irqs_table[0]);
819 		}
820 	}
821 
822 	if (num_rx)
823 		cpsw_dbg(priv, intr, "poll %d rx pkts\n", num_rx);
824 
825 	return num_rx;
826 }
827 
828 static inline void soft_reset(const char *module, void __iomem *reg)
829 {
830 	unsigned long timeout = jiffies + HZ;
831 
832 	__raw_writel(1, reg);
833 	do {
834 		cpu_relax();
835 	} while ((__raw_readl(reg) & 1) && time_after(timeout, jiffies));
836 
837 	WARN(__raw_readl(reg) & 1, "failed to soft-reset %s\n", module);
838 }
839 
840 #define mac_hi(mac)	(((mac)[0] << 0) | ((mac)[1] << 8) |	\
841 			 ((mac)[2] << 16) | ((mac)[3] << 24))
842 #define mac_lo(mac)	(((mac)[4] << 0) | ((mac)[5] << 8))
843 
844 static void cpsw_set_slave_mac(struct cpsw_slave *slave,
845 			       struct cpsw_priv *priv)
846 {
847 	slave_write(slave, mac_hi(priv->mac_addr), SA_HI);
848 	slave_write(slave, mac_lo(priv->mac_addr), SA_LO);
849 }
850 
851 static void _cpsw_adjust_link(struct cpsw_slave *slave,
852 			      struct cpsw_priv *priv, bool *link)
853 {
854 	struct phy_device	*phy = slave->phy;
855 	u32			mac_control = 0;
856 	u32			slave_port;
857 
858 	if (!phy)
859 		return;
860 
861 	slave_port = cpsw_get_slave_port(priv, slave->slave_num);
862 
863 	if (phy->link) {
864 		mac_control = priv->data.mac_control;
865 
866 		/* enable forwarding */
867 		cpsw_ale_control_set(priv->ale, slave_port,
868 				     ALE_PORT_STATE, ALE_PORT_STATE_FORWARD);
869 
870 		if (phy->speed == 1000)
871 			mac_control |= BIT(7);	/* GIGABITEN	*/
872 		if (phy->duplex)
873 			mac_control |= BIT(0);	/* FULLDUPLEXEN	*/
874 
875 		/* set speed_in input in case RMII mode is used in 100Mbps */
876 		if (phy->speed == 100)
877 			mac_control |= BIT(15);
878 		else if (phy->speed == 10)
879 			mac_control |= BIT(18); /* In Band mode */
880 
881 		if (priv->rx_pause)
882 			mac_control |= BIT(3);
883 
884 		if (priv->tx_pause)
885 			mac_control |= BIT(4);
886 
887 		*link = true;
888 	} else {
889 		mac_control = 0;
890 		/* disable forwarding */
891 		cpsw_ale_control_set(priv->ale, slave_port,
892 				     ALE_PORT_STATE, ALE_PORT_STATE_DISABLE);
893 	}
894 
895 	if (mac_control != slave->mac_control) {
896 		phy_print_status(phy);
897 		__raw_writel(mac_control, &slave->sliver->mac_control);
898 	}
899 
900 	slave->mac_control = mac_control;
901 }
902 
903 static void cpsw_adjust_link(struct net_device *ndev)
904 {
905 	struct cpsw_priv	*priv = netdev_priv(ndev);
906 	bool			link = false;
907 
908 	for_each_slave(priv, _cpsw_adjust_link, priv, &link);
909 
910 	if (link) {
911 		netif_carrier_on(ndev);
912 		if (netif_running(ndev))
913 			netif_wake_queue(ndev);
914 	} else {
915 		netif_carrier_off(ndev);
916 		netif_stop_queue(ndev);
917 	}
918 }
919 
920 static int cpsw_get_coalesce(struct net_device *ndev,
921 				struct ethtool_coalesce *coal)
922 {
923 	struct cpsw_priv *priv = netdev_priv(ndev);
924 
925 	coal->rx_coalesce_usecs = priv->coal_intvl;
926 	return 0;
927 }
928 
929 static int cpsw_set_coalesce(struct net_device *ndev,
930 				struct ethtool_coalesce *coal)
931 {
932 	struct cpsw_priv *priv = netdev_priv(ndev);
933 	u32 int_ctrl;
934 	u32 num_interrupts = 0;
935 	u32 prescale = 0;
936 	u32 addnl_dvdr = 1;
937 	u32 coal_intvl = 0;
938 
939 	coal_intvl = coal->rx_coalesce_usecs;
940 
941 	int_ctrl =  readl(&priv->wr_regs->int_control);
942 	prescale = priv->bus_freq_mhz * 4;
943 
944 	if (!coal->rx_coalesce_usecs) {
945 		int_ctrl &= ~(CPSW_INTPRESCALE_MASK | CPSW_INTPACEEN);
946 		goto update_return;
947 	}
948 
949 	if (coal_intvl < CPSW_CMINTMIN_INTVL)
950 		coal_intvl = CPSW_CMINTMIN_INTVL;
951 
952 	if (coal_intvl > CPSW_CMINTMAX_INTVL) {
953 		/* Interrupt pacer works with 4us Pulse, we can
954 		 * throttle further by dilating the 4us pulse.
955 		 */
956 		addnl_dvdr = CPSW_INTPRESCALE_MASK / prescale;
957 
958 		if (addnl_dvdr > 1) {
959 			prescale *= addnl_dvdr;
960 			if (coal_intvl > (CPSW_CMINTMAX_INTVL * addnl_dvdr))
961 				coal_intvl = (CPSW_CMINTMAX_INTVL
962 						* addnl_dvdr);
963 		} else {
964 			addnl_dvdr = 1;
965 			coal_intvl = CPSW_CMINTMAX_INTVL;
966 		}
967 	}
968 
969 	num_interrupts = (1000 * addnl_dvdr) / coal_intvl;
970 	writel(num_interrupts, &priv->wr_regs->rx_imax);
971 	writel(num_interrupts, &priv->wr_regs->tx_imax);
972 
973 	int_ctrl |= CPSW_INTPACEEN;
974 	int_ctrl &= (~CPSW_INTPRESCALE_MASK);
975 	int_ctrl |= (prescale & CPSW_INTPRESCALE_MASK);
976 
977 update_return:
978 	writel(int_ctrl, &priv->wr_regs->int_control);
979 
980 	cpsw_notice(priv, timer, "Set coalesce to %d usecs.\n", coal_intvl);
981 	if (priv->data.dual_emac) {
982 		int i;
983 
984 		for (i = 0; i < priv->data.slaves; i++) {
985 			priv = netdev_priv(priv->slaves[i].ndev);
986 			priv->coal_intvl = coal_intvl;
987 		}
988 	} else {
989 		priv->coal_intvl = coal_intvl;
990 	}
991 
992 	return 0;
993 }
994 
995 static int cpsw_get_sset_count(struct net_device *ndev, int sset)
996 {
997 	switch (sset) {
998 	case ETH_SS_STATS:
999 		return CPSW_STATS_LEN;
1000 	default:
1001 		return -EOPNOTSUPP;
1002 	}
1003 }
1004 
1005 static void cpsw_get_strings(struct net_device *ndev, u32 stringset, u8 *data)
1006 {
1007 	u8 *p = data;
1008 	int i;
1009 
1010 	switch (stringset) {
1011 	case ETH_SS_STATS:
1012 		for (i = 0; i < CPSW_STATS_LEN; i++) {
1013 			memcpy(p, cpsw_gstrings_stats[i].stat_string,
1014 			       ETH_GSTRING_LEN);
1015 			p += ETH_GSTRING_LEN;
1016 		}
1017 		break;
1018 	}
1019 }
1020 
1021 static void cpsw_get_ethtool_stats(struct net_device *ndev,
1022 				    struct ethtool_stats *stats, u64 *data)
1023 {
1024 	struct cpsw_priv *priv = netdev_priv(ndev);
1025 	struct cpdma_chan_stats rx_stats;
1026 	struct cpdma_chan_stats tx_stats;
1027 	u32 val;
1028 	u8 *p;
1029 	int i;
1030 
1031 	/* Collect Davinci CPDMA stats for Rx and Tx Channel */
1032 	cpdma_chan_get_stats(priv->rxch, &rx_stats);
1033 	cpdma_chan_get_stats(priv->txch, &tx_stats);
1034 
1035 	for (i = 0; i < CPSW_STATS_LEN; i++) {
1036 		switch (cpsw_gstrings_stats[i].type) {
1037 		case CPSW_STATS:
1038 			val = readl(priv->hw_stats +
1039 				    cpsw_gstrings_stats[i].stat_offset);
1040 			data[i] = val;
1041 			break;
1042 
1043 		case CPDMA_RX_STATS:
1044 			p = (u8 *)&rx_stats +
1045 				cpsw_gstrings_stats[i].stat_offset;
1046 			data[i] = *(u32 *)p;
1047 			break;
1048 
1049 		case CPDMA_TX_STATS:
1050 			p = (u8 *)&tx_stats +
1051 				cpsw_gstrings_stats[i].stat_offset;
1052 			data[i] = *(u32 *)p;
1053 			break;
1054 		}
1055 	}
1056 }
1057 
1058 static int cpsw_common_res_usage_state(struct cpsw_priv *priv)
1059 {
1060 	u32 i;
1061 	u32 usage_count = 0;
1062 
1063 	if (!priv->data.dual_emac)
1064 		return 0;
1065 
1066 	for (i = 0; i < priv->data.slaves; i++)
1067 		if (priv->slaves[i].open_stat)
1068 			usage_count++;
1069 
1070 	return usage_count;
1071 }
1072 
1073 static inline int cpsw_tx_packet_submit(struct net_device *ndev,
1074 			struct cpsw_priv *priv, struct sk_buff *skb)
1075 {
1076 	if (!priv->data.dual_emac)
1077 		return cpdma_chan_submit(priv->txch, skb, skb->data,
1078 				  skb->len, 0);
1079 
1080 	if (ndev == cpsw_get_slave_ndev(priv, 0))
1081 		return cpdma_chan_submit(priv->txch, skb, skb->data,
1082 				  skb->len, 1);
1083 	else
1084 		return cpdma_chan_submit(priv->txch, skb, skb->data,
1085 				  skb->len, 2);
1086 }
1087 
1088 static inline void cpsw_add_dual_emac_def_ale_entries(
1089 		struct cpsw_priv *priv, struct cpsw_slave *slave,
1090 		u32 slave_port)
1091 {
1092 	u32 port_mask = 1 << slave_port | 1 << priv->host_port;
1093 
1094 	if (priv->version == CPSW_VERSION_1)
1095 		slave_write(slave, slave->port_vlan, CPSW1_PORT_VLAN);
1096 	else
1097 		slave_write(slave, slave->port_vlan, CPSW2_PORT_VLAN);
1098 	cpsw_ale_add_vlan(priv->ale, slave->port_vlan, port_mask,
1099 			  port_mask, port_mask, 0);
1100 	cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast,
1101 			   port_mask, ALE_VLAN, slave->port_vlan, 0);
1102 	cpsw_ale_add_ucast(priv->ale, priv->mac_addr,
1103 		priv->host_port, ALE_VLAN | ALE_SECURE, slave->port_vlan);
1104 }
1105 
1106 static void soft_reset_slave(struct cpsw_slave *slave)
1107 {
1108 	char name[32];
1109 
1110 	snprintf(name, sizeof(name), "slave-%d", slave->slave_num);
1111 	soft_reset(name, &slave->sliver->soft_reset);
1112 }
1113 
1114 static void cpsw_slave_open(struct cpsw_slave *slave, struct cpsw_priv *priv)
1115 {
1116 	u32 slave_port;
1117 
1118 	soft_reset_slave(slave);
1119 
1120 	/* setup priority mapping */
1121 	__raw_writel(RX_PRIORITY_MAPPING, &slave->sliver->rx_pri_map);
1122 
1123 	switch (priv->version) {
1124 	case CPSW_VERSION_1:
1125 		slave_write(slave, TX_PRIORITY_MAPPING, CPSW1_TX_PRI_MAP);
1126 		break;
1127 	case CPSW_VERSION_2:
1128 	case CPSW_VERSION_3:
1129 	case CPSW_VERSION_4:
1130 		slave_write(slave, TX_PRIORITY_MAPPING, CPSW2_TX_PRI_MAP);
1131 		break;
1132 	}
1133 
1134 	/* setup max packet size, and mac address */
1135 	__raw_writel(priv->rx_packet_max, &slave->sliver->rx_maxlen);
1136 	cpsw_set_slave_mac(slave, priv);
1137 
1138 	slave->mac_control = 0;	/* no link yet */
1139 
1140 	slave_port = cpsw_get_slave_port(priv, slave->slave_num);
1141 
1142 	if (priv->data.dual_emac)
1143 		cpsw_add_dual_emac_def_ale_entries(priv, slave, slave_port);
1144 	else
1145 		cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast,
1146 				   1 << slave_port, 0, 0, ALE_MCAST_FWD_2);
1147 
1148 	slave->phy = phy_connect(priv->ndev, slave->data->phy_id,
1149 				 &cpsw_adjust_link, slave->data->phy_if);
1150 	if (IS_ERR(slave->phy)) {
1151 		dev_err(priv->dev, "phy %s not found on slave %d\n",
1152 			slave->data->phy_id, slave->slave_num);
1153 		slave->phy = NULL;
1154 	} else {
1155 		dev_info(priv->dev, "phy found : id is : 0x%x\n",
1156 			 slave->phy->phy_id);
1157 		phy_start(slave->phy);
1158 
1159 		/* Configure GMII_SEL register */
1160 		cpsw_phy_sel(&priv->pdev->dev, slave->phy->interface,
1161 			     slave->slave_num);
1162 	}
1163 }
1164 
1165 static inline void cpsw_add_default_vlan(struct cpsw_priv *priv)
1166 {
1167 	const int vlan = priv->data.default_vlan;
1168 	const int port = priv->host_port;
1169 	u32 reg;
1170 	int i;
1171 	int unreg_mcast_mask;
1172 
1173 	reg = (priv->version == CPSW_VERSION_1) ? CPSW1_PORT_VLAN :
1174 	       CPSW2_PORT_VLAN;
1175 
1176 	writel(vlan, &priv->host_port_regs->port_vlan);
1177 
1178 	for (i = 0; i < priv->data.slaves; i++)
1179 		slave_write(priv->slaves + i, vlan, reg);
1180 
1181 	if (priv->ndev->flags & IFF_ALLMULTI)
1182 		unreg_mcast_mask = ALE_ALL_PORTS;
1183 	else
1184 		unreg_mcast_mask = ALE_PORT_1 | ALE_PORT_2;
1185 
1186 	cpsw_ale_add_vlan(priv->ale, vlan, ALE_ALL_PORTS << port,
1187 			  ALE_ALL_PORTS << port, ALE_ALL_PORTS << port,
1188 			  unreg_mcast_mask << port);
1189 }
1190 
1191 static void cpsw_init_host_port(struct cpsw_priv *priv)
1192 {
1193 	u32 control_reg;
1194 	u32 fifo_mode;
1195 
1196 	/* soft reset the controller and initialize ale */
1197 	soft_reset("cpsw", &priv->regs->soft_reset);
1198 	cpsw_ale_start(priv->ale);
1199 
1200 	/* switch to vlan unaware mode */
1201 	cpsw_ale_control_set(priv->ale, priv->host_port, ALE_VLAN_AWARE,
1202 			     CPSW_ALE_VLAN_AWARE);
1203 	control_reg = readl(&priv->regs->control);
1204 	control_reg |= CPSW_VLAN_AWARE;
1205 	writel(control_reg, &priv->regs->control);
1206 	fifo_mode = (priv->data.dual_emac) ? CPSW_FIFO_DUAL_MAC_MODE :
1207 		     CPSW_FIFO_NORMAL_MODE;
1208 	writel(fifo_mode, &priv->host_port_regs->tx_in_ctl);
1209 
1210 	/* setup host port priority mapping */
1211 	__raw_writel(CPDMA_TX_PRIORITY_MAP,
1212 		     &priv->host_port_regs->cpdma_tx_pri_map);
1213 	__raw_writel(0, &priv->host_port_regs->cpdma_rx_chan_map);
1214 
1215 	cpsw_ale_control_set(priv->ale, priv->host_port,
1216 			     ALE_PORT_STATE, ALE_PORT_STATE_FORWARD);
1217 
1218 	if (!priv->data.dual_emac) {
1219 		cpsw_ale_add_ucast(priv->ale, priv->mac_addr, priv->host_port,
1220 				   0, 0);
1221 		cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast,
1222 				   1 << priv->host_port, 0, 0, ALE_MCAST_FWD_2);
1223 	}
1224 }
1225 
1226 static void cpsw_slave_stop(struct cpsw_slave *slave, struct cpsw_priv *priv)
1227 {
1228 	u32 slave_port;
1229 
1230 	slave_port = cpsw_get_slave_port(priv, slave->slave_num);
1231 
1232 	if (!slave->phy)
1233 		return;
1234 	phy_stop(slave->phy);
1235 	phy_disconnect(slave->phy);
1236 	slave->phy = NULL;
1237 	cpsw_ale_control_set(priv->ale, slave_port,
1238 			     ALE_PORT_STATE, ALE_PORT_STATE_DISABLE);
1239 }
1240 
1241 static int cpsw_ndo_open(struct net_device *ndev)
1242 {
1243 	struct cpsw_priv *priv = netdev_priv(ndev);
1244 	int i, ret;
1245 	u32 reg;
1246 
1247 	if (!cpsw_common_res_usage_state(priv))
1248 		cpsw_intr_disable(priv);
1249 	netif_carrier_off(ndev);
1250 
1251 	pm_runtime_get_sync(&priv->pdev->dev);
1252 
1253 	reg = priv->version;
1254 
1255 	dev_info(priv->dev, "initializing cpsw version %d.%d (%d)\n",
1256 		 CPSW_MAJOR_VERSION(reg), CPSW_MINOR_VERSION(reg),
1257 		 CPSW_RTL_VERSION(reg));
1258 
1259 	/* initialize host and slave ports */
1260 	if (!cpsw_common_res_usage_state(priv))
1261 		cpsw_init_host_port(priv);
1262 	for_each_slave(priv, cpsw_slave_open, priv);
1263 
1264 	/* Add default VLAN */
1265 	if (!priv->data.dual_emac)
1266 		cpsw_add_default_vlan(priv);
1267 	else
1268 		cpsw_ale_add_vlan(priv->ale, priv->data.default_vlan,
1269 				  ALE_ALL_PORTS << priv->host_port,
1270 				  ALE_ALL_PORTS << priv->host_port, 0, 0);
1271 
1272 	if (!cpsw_common_res_usage_state(priv)) {
1273 		struct cpsw_priv *priv_sl0 = cpsw_get_slave_priv(priv, 0);
1274 
1275 		/* setup tx dma to fixed prio and zero offset */
1276 		cpdma_control_set(priv->dma, CPDMA_TX_PRIO_FIXED, 1);
1277 		cpdma_control_set(priv->dma, CPDMA_RX_BUFFER_OFFSET, 0);
1278 
1279 		/* disable priority elevation */
1280 		__raw_writel(0, &priv->regs->ptype);
1281 
1282 		/* enable statistics collection only on all ports */
1283 		__raw_writel(0x7, &priv->regs->stat_port_en);
1284 
1285 		/* Enable internal fifo flow control */
1286 		writel(0x7, &priv->regs->flow_control);
1287 
1288 		napi_enable(&priv_sl0->napi_rx);
1289 		napi_enable(&priv_sl0->napi_tx);
1290 
1291 		if (priv_sl0->tx_irq_disabled) {
1292 			priv_sl0->tx_irq_disabled = false;
1293 			enable_irq(priv->irqs_table[1]);
1294 		}
1295 
1296 		if (priv_sl0->rx_irq_disabled) {
1297 			priv_sl0->rx_irq_disabled = false;
1298 			enable_irq(priv->irqs_table[0]);
1299 		}
1300 
1301 		if (WARN_ON(!priv->data.rx_descs))
1302 			priv->data.rx_descs = 128;
1303 
1304 		for (i = 0; i < priv->data.rx_descs; i++) {
1305 			struct sk_buff *skb;
1306 
1307 			ret = -ENOMEM;
1308 			skb = __netdev_alloc_skb_ip_align(priv->ndev,
1309 					priv->rx_packet_max, GFP_KERNEL);
1310 			if (!skb)
1311 				goto err_cleanup;
1312 			ret = cpdma_chan_submit(priv->rxch, skb, skb->data,
1313 					skb_tailroom(skb), 0);
1314 			if (ret < 0) {
1315 				kfree_skb(skb);
1316 				goto err_cleanup;
1317 			}
1318 		}
1319 		/* continue even if we didn't manage to submit all
1320 		 * receive descs
1321 		 */
1322 		cpsw_info(priv, ifup, "submitted %d rx descriptors\n", i);
1323 
1324 		if (cpts_register(&priv->pdev->dev, priv->cpts,
1325 				  priv->data.cpts_clock_mult,
1326 				  priv->data.cpts_clock_shift))
1327 			dev_err(priv->dev, "error registering cpts device\n");
1328 
1329 	}
1330 
1331 	/* Enable Interrupt pacing if configured */
1332 	if (priv->coal_intvl != 0) {
1333 		struct ethtool_coalesce coal;
1334 
1335 		coal.rx_coalesce_usecs = (priv->coal_intvl << 4);
1336 		cpsw_set_coalesce(ndev, &coal);
1337 	}
1338 
1339 	cpdma_ctlr_start(priv->dma);
1340 	cpsw_intr_enable(priv);
1341 
1342 	if (priv->data.dual_emac)
1343 		priv->slaves[priv->emac_port].open_stat = true;
1344 	return 0;
1345 
1346 err_cleanup:
1347 	cpdma_ctlr_stop(priv->dma);
1348 	for_each_slave(priv, cpsw_slave_stop, priv);
1349 	pm_runtime_put_sync(&priv->pdev->dev);
1350 	netif_carrier_off(priv->ndev);
1351 	return ret;
1352 }
1353 
1354 static int cpsw_ndo_stop(struct net_device *ndev)
1355 {
1356 	struct cpsw_priv *priv = netdev_priv(ndev);
1357 
1358 	cpsw_info(priv, ifdown, "shutting down cpsw device\n");
1359 	netif_stop_queue(priv->ndev);
1360 	netif_carrier_off(priv->ndev);
1361 
1362 	if (cpsw_common_res_usage_state(priv) <= 1) {
1363 		struct cpsw_priv *priv_sl0 = cpsw_get_slave_priv(priv, 0);
1364 
1365 		napi_disable(&priv_sl0->napi_rx);
1366 		napi_disable(&priv_sl0->napi_tx);
1367 		cpts_unregister(priv->cpts);
1368 		cpsw_intr_disable(priv);
1369 		cpdma_ctlr_stop(priv->dma);
1370 		cpsw_ale_stop(priv->ale);
1371 	}
1372 	for_each_slave(priv, cpsw_slave_stop, priv);
1373 	pm_runtime_put_sync(&priv->pdev->dev);
1374 	if (priv->data.dual_emac)
1375 		priv->slaves[priv->emac_port].open_stat = false;
1376 	return 0;
1377 }
1378 
1379 static netdev_tx_t cpsw_ndo_start_xmit(struct sk_buff *skb,
1380 				       struct net_device *ndev)
1381 {
1382 	struct cpsw_priv *priv = netdev_priv(ndev);
1383 	int ret;
1384 
1385 	ndev->trans_start = jiffies;
1386 
1387 	if (skb_padto(skb, CPSW_MIN_PACKET_SIZE)) {
1388 		cpsw_err(priv, tx_err, "packet pad failed\n");
1389 		ndev->stats.tx_dropped++;
1390 		return NETDEV_TX_OK;
1391 	}
1392 
1393 	if (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP &&
1394 				priv->cpts->tx_enable)
1395 		skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
1396 
1397 	skb_tx_timestamp(skb);
1398 
1399 	ret = cpsw_tx_packet_submit(ndev, priv, skb);
1400 	if (unlikely(ret != 0)) {
1401 		cpsw_err(priv, tx_err, "desc submit failed\n");
1402 		goto fail;
1403 	}
1404 
1405 	/* If there is no more tx desc left free then we need to
1406 	 * tell the kernel to stop sending us tx frames.
1407 	 */
1408 	if (unlikely(!cpdma_check_free_tx_desc(priv->txch)))
1409 		netif_stop_queue(ndev);
1410 
1411 	return NETDEV_TX_OK;
1412 fail:
1413 	ndev->stats.tx_dropped++;
1414 	netif_stop_queue(ndev);
1415 	return NETDEV_TX_BUSY;
1416 }
1417 
1418 #ifdef CONFIG_TI_CPTS
1419 
1420 static void cpsw_hwtstamp_v1(struct cpsw_priv *priv)
1421 {
1422 	struct cpsw_slave *slave = &priv->slaves[priv->data.active_slave];
1423 	u32 ts_en, seq_id;
1424 
1425 	if (!priv->cpts->tx_enable && !priv->cpts->rx_enable) {
1426 		slave_write(slave, 0, CPSW1_TS_CTL);
1427 		return;
1428 	}
1429 
1430 	seq_id = (30 << CPSW_V1_SEQ_ID_OFS_SHIFT) | ETH_P_1588;
1431 	ts_en = EVENT_MSG_BITS << CPSW_V1_MSG_TYPE_OFS;
1432 
1433 	if (priv->cpts->tx_enable)
1434 		ts_en |= CPSW_V1_TS_TX_EN;
1435 
1436 	if (priv->cpts->rx_enable)
1437 		ts_en |= CPSW_V1_TS_RX_EN;
1438 
1439 	slave_write(slave, ts_en, CPSW1_TS_CTL);
1440 	slave_write(slave, seq_id, CPSW1_TS_SEQ_LTYPE);
1441 }
1442 
1443 static void cpsw_hwtstamp_v2(struct cpsw_priv *priv)
1444 {
1445 	struct cpsw_slave *slave;
1446 	u32 ctrl, mtype;
1447 
1448 	if (priv->data.dual_emac)
1449 		slave = &priv->slaves[priv->emac_port];
1450 	else
1451 		slave = &priv->slaves[priv->data.active_slave];
1452 
1453 	ctrl = slave_read(slave, CPSW2_CONTROL);
1454 	switch (priv->version) {
1455 	case CPSW_VERSION_2:
1456 		ctrl &= ~CTRL_V2_ALL_TS_MASK;
1457 
1458 		if (priv->cpts->tx_enable)
1459 			ctrl |= CTRL_V2_TX_TS_BITS;
1460 
1461 		if (priv->cpts->rx_enable)
1462 			ctrl |= CTRL_V2_RX_TS_BITS;
1463 		break;
1464 	case CPSW_VERSION_3:
1465 	default:
1466 		ctrl &= ~CTRL_V3_ALL_TS_MASK;
1467 
1468 		if (priv->cpts->tx_enable)
1469 			ctrl |= CTRL_V3_TX_TS_BITS;
1470 
1471 		if (priv->cpts->rx_enable)
1472 			ctrl |= CTRL_V3_RX_TS_BITS;
1473 		break;
1474 	}
1475 
1476 	mtype = (30 << TS_SEQ_ID_OFFSET_SHIFT) | EVENT_MSG_BITS;
1477 
1478 	slave_write(slave, mtype, CPSW2_TS_SEQ_MTYPE);
1479 	slave_write(slave, ctrl, CPSW2_CONTROL);
1480 	__raw_writel(ETH_P_1588, &priv->regs->ts_ltype);
1481 }
1482 
1483 static int cpsw_hwtstamp_set(struct net_device *dev, struct ifreq *ifr)
1484 {
1485 	struct cpsw_priv *priv = netdev_priv(dev);
1486 	struct cpts *cpts = priv->cpts;
1487 	struct hwtstamp_config cfg;
1488 
1489 	if (priv->version != CPSW_VERSION_1 &&
1490 	    priv->version != CPSW_VERSION_2 &&
1491 	    priv->version != CPSW_VERSION_3)
1492 		return -EOPNOTSUPP;
1493 
1494 	if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg)))
1495 		return -EFAULT;
1496 
1497 	/* reserved for future extensions */
1498 	if (cfg.flags)
1499 		return -EINVAL;
1500 
1501 	if (cfg.tx_type != HWTSTAMP_TX_OFF && cfg.tx_type != HWTSTAMP_TX_ON)
1502 		return -ERANGE;
1503 
1504 	switch (cfg.rx_filter) {
1505 	case HWTSTAMP_FILTER_NONE:
1506 		cpts->rx_enable = 0;
1507 		break;
1508 	case HWTSTAMP_FILTER_ALL:
1509 	case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
1510 	case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
1511 	case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
1512 		return -ERANGE;
1513 	case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
1514 	case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
1515 	case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
1516 	case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
1517 	case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
1518 	case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
1519 	case HWTSTAMP_FILTER_PTP_V2_EVENT:
1520 	case HWTSTAMP_FILTER_PTP_V2_SYNC:
1521 	case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
1522 		cpts->rx_enable = 1;
1523 		cfg.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
1524 		break;
1525 	default:
1526 		return -ERANGE;
1527 	}
1528 
1529 	cpts->tx_enable = cfg.tx_type == HWTSTAMP_TX_ON;
1530 
1531 	switch (priv->version) {
1532 	case CPSW_VERSION_1:
1533 		cpsw_hwtstamp_v1(priv);
1534 		break;
1535 	case CPSW_VERSION_2:
1536 	case CPSW_VERSION_3:
1537 		cpsw_hwtstamp_v2(priv);
1538 		break;
1539 	default:
1540 		WARN_ON(1);
1541 	}
1542 
1543 	return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0;
1544 }
1545 
1546 static int cpsw_hwtstamp_get(struct net_device *dev, struct ifreq *ifr)
1547 {
1548 	struct cpsw_priv *priv = netdev_priv(dev);
1549 	struct cpts *cpts = priv->cpts;
1550 	struct hwtstamp_config cfg;
1551 
1552 	if (priv->version != CPSW_VERSION_1 &&
1553 	    priv->version != CPSW_VERSION_2 &&
1554 	    priv->version != CPSW_VERSION_3)
1555 		return -EOPNOTSUPP;
1556 
1557 	cfg.flags = 0;
1558 	cfg.tx_type = cpts->tx_enable ? HWTSTAMP_TX_ON : HWTSTAMP_TX_OFF;
1559 	cfg.rx_filter = (cpts->rx_enable ?
1560 			 HWTSTAMP_FILTER_PTP_V2_EVENT : HWTSTAMP_FILTER_NONE);
1561 
1562 	return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0;
1563 }
1564 
1565 #endif /*CONFIG_TI_CPTS*/
1566 
1567 static int cpsw_ndo_ioctl(struct net_device *dev, struct ifreq *req, int cmd)
1568 {
1569 	struct cpsw_priv *priv = netdev_priv(dev);
1570 	int slave_no = cpsw_slave_index(priv);
1571 
1572 	if (!netif_running(dev))
1573 		return -EINVAL;
1574 
1575 	switch (cmd) {
1576 #ifdef CONFIG_TI_CPTS
1577 	case SIOCSHWTSTAMP:
1578 		return cpsw_hwtstamp_set(dev, req);
1579 	case SIOCGHWTSTAMP:
1580 		return cpsw_hwtstamp_get(dev, req);
1581 #endif
1582 	}
1583 
1584 	if (!priv->slaves[slave_no].phy)
1585 		return -EOPNOTSUPP;
1586 	return phy_mii_ioctl(priv->slaves[slave_no].phy, req, cmd);
1587 }
1588 
1589 static void cpsw_ndo_tx_timeout(struct net_device *ndev)
1590 {
1591 	struct cpsw_priv *priv = netdev_priv(ndev);
1592 
1593 	cpsw_err(priv, tx_err, "transmit timeout, restarting dma\n");
1594 	ndev->stats.tx_errors++;
1595 	cpsw_intr_disable(priv);
1596 	cpdma_chan_stop(priv->txch);
1597 	cpdma_chan_start(priv->txch);
1598 	cpsw_intr_enable(priv);
1599 }
1600 
1601 static int cpsw_ndo_set_mac_address(struct net_device *ndev, void *p)
1602 {
1603 	struct cpsw_priv *priv = netdev_priv(ndev);
1604 	struct sockaddr *addr = (struct sockaddr *)p;
1605 	int flags = 0;
1606 	u16 vid = 0;
1607 
1608 	if (!is_valid_ether_addr(addr->sa_data))
1609 		return -EADDRNOTAVAIL;
1610 
1611 	if (priv->data.dual_emac) {
1612 		vid = priv->slaves[priv->emac_port].port_vlan;
1613 		flags = ALE_VLAN;
1614 	}
1615 
1616 	cpsw_ale_del_ucast(priv->ale, priv->mac_addr, priv->host_port,
1617 			   flags, vid);
1618 	cpsw_ale_add_ucast(priv->ale, addr->sa_data, priv->host_port,
1619 			   flags, vid);
1620 
1621 	memcpy(priv->mac_addr, addr->sa_data, ETH_ALEN);
1622 	memcpy(ndev->dev_addr, priv->mac_addr, ETH_ALEN);
1623 	for_each_slave(priv, cpsw_set_slave_mac, priv);
1624 
1625 	return 0;
1626 }
1627 
1628 #ifdef CONFIG_NET_POLL_CONTROLLER
1629 static void cpsw_ndo_poll_controller(struct net_device *ndev)
1630 {
1631 	struct cpsw_priv *priv = netdev_priv(ndev);
1632 
1633 	cpsw_intr_disable(priv);
1634 	cpsw_rx_interrupt(priv->irqs_table[0], priv);
1635 	cpsw_tx_interrupt(priv->irqs_table[1], priv);
1636 	cpsw_intr_enable(priv);
1637 }
1638 #endif
1639 
1640 static inline int cpsw_add_vlan_ale_entry(struct cpsw_priv *priv,
1641 				unsigned short vid)
1642 {
1643 	int ret;
1644 	int unreg_mcast_mask = 0;
1645 	u32 port_mask;
1646 
1647 	if (priv->data.dual_emac) {
1648 		port_mask = (1 << (priv->emac_port + 1)) | ALE_PORT_HOST;
1649 
1650 		if (priv->ndev->flags & IFF_ALLMULTI)
1651 			unreg_mcast_mask = port_mask;
1652 	} else {
1653 		port_mask = ALE_ALL_PORTS;
1654 
1655 		if (priv->ndev->flags & IFF_ALLMULTI)
1656 			unreg_mcast_mask = ALE_ALL_PORTS;
1657 		else
1658 			unreg_mcast_mask = ALE_PORT_1 | ALE_PORT_2;
1659 	}
1660 
1661 	ret = cpsw_ale_add_vlan(priv->ale, vid, port_mask, 0, port_mask,
1662 				unreg_mcast_mask << priv->host_port);
1663 	if (ret != 0)
1664 		return ret;
1665 
1666 	ret = cpsw_ale_add_ucast(priv->ale, priv->mac_addr,
1667 				 priv->host_port, ALE_VLAN, vid);
1668 	if (ret != 0)
1669 		goto clean_vid;
1670 
1671 	ret = cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast,
1672 				 port_mask, ALE_VLAN, vid, 0);
1673 	if (ret != 0)
1674 		goto clean_vlan_ucast;
1675 	return 0;
1676 
1677 clean_vlan_ucast:
1678 	cpsw_ale_del_ucast(priv->ale, priv->mac_addr,
1679 			    priv->host_port, ALE_VLAN, vid);
1680 clean_vid:
1681 	cpsw_ale_del_vlan(priv->ale, vid, 0);
1682 	return ret;
1683 }
1684 
1685 static int cpsw_ndo_vlan_rx_add_vid(struct net_device *ndev,
1686 				    __be16 proto, u16 vid)
1687 {
1688 	struct cpsw_priv *priv = netdev_priv(ndev);
1689 
1690 	if (vid == priv->data.default_vlan)
1691 		return 0;
1692 
1693 	if (priv->data.dual_emac) {
1694 		/* In dual EMAC, reserved VLAN id should not be used for
1695 		 * creating VLAN interfaces as this can break the dual
1696 		 * EMAC port separation
1697 		 */
1698 		int i;
1699 
1700 		for (i = 0; i < priv->data.slaves; i++) {
1701 			if (vid == priv->slaves[i].port_vlan)
1702 				return -EINVAL;
1703 		}
1704 	}
1705 
1706 	dev_info(priv->dev, "Adding vlanid %d to vlan filter\n", vid);
1707 	return cpsw_add_vlan_ale_entry(priv, vid);
1708 }
1709 
1710 static int cpsw_ndo_vlan_rx_kill_vid(struct net_device *ndev,
1711 				     __be16 proto, u16 vid)
1712 {
1713 	struct cpsw_priv *priv = netdev_priv(ndev);
1714 	int ret;
1715 
1716 	if (vid == priv->data.default_vlan)
1717 		return 0;
1718 
1719 	if (priv->data.dual_emac) {
1720 		int i;
1721 
1722 		for (i = 0; i < priv->data.slaves; i++) {
1723 			if (vid == priv->slaves[i].port_vlan)
1724 				return -EINVAL;
1725 		}
1726 	}
1727 
1728 	dev_info(priv->dev, "removing vlanid %d from vlan filter\n", vid);
1729 	ret = cpsw_ale_del_vlan(priv->ale, vid, 0);
1730 	if (ret != 0)
1731 		return ret;
1732 
1733 	ret = cpsw_ale_del_ucast(priv->ale, priv->mac_addr,
1734 				 priv->host_port, ALE_VLAN, vid);
1735 	if (ret != 0)
1736 		return ret;
1737 
1738 	return cpsw_ale_del_mcast(priv->ale, priv->ndev->broadcast,
1739 				  0, ALE_VLAN, vid);
1740 }
1741 
1742 static const struct net_device_ops cpsw_netdev_ops = {
1743 	.ndo_open		= cpsw_ndo_open,
1744 	.ndo_stop		= cpsw_ndo_stop,
1745 	.ndo_start_xmit		= cpsw_ndo_start_xmit,
1746 	.ndo_set_mac_address	= cpsw_ndo_set_mac_address,
1747 	.ndo_do_ioctl		= cpsw_ndo_ioctl,
1748 	.ndo_validate_addr	= eth_validate_addr,
1749 	.ndo_change_mtu		= eth_change_mtu,
1750 	.ndo_tx_timeout		= cpsw_ndo_tx_timeout,
1751 	.ndo_set_rx_mode	= cpsw_ndo_set_rx_mode,
1752 #ifdef CONFIG_NET_POLL_CONTROLLER
1753 	.ndo_poll_controller	= cpsw_ndo_poll_controller,
1754 #endif
1755 	.ndo_vlan_rx_add_vid	= cpsw_ndo_vlan_rx_add_vid,
1756 	.ndo_vlan_rx_kill_vid	= cpsw_ndo_vlan_rx_kill_vid,
1757 };
1758 
1759 static int cpsw_get_regs_len(struct net_device *ndev)
1760 {
1761 	struct cpsw_priv *priv = netdev_priv(ndev);
1762 
1763 	return priv->data.ale_entries * ALE_ENTRY_WORDS * sizeof(u32);
1764 }
1765 
1766 static void cpsw_get_regs(struct net_device *ndev,
1767 			  struct ethtool_regs *regs, void *p)
1768 {
1769 	struct cpsw_priv *priv = netdev_priv(ndev);
1770 	u32 *reg = p;
1771 
1772 	/* update CPSW IP version */
1773 	regs->version = priv->version;
1774 
1775 	cpsw_ale_dump(priv->ale, reg);
1776 }
1777 
1778 static void cpsw_get_drvinfo(struct net_device *ndev,
1779 			     struct ethtool_drvinfo *info)
1780 {
1781 	struct cpsw_priv *priv = netdev_priv(ndev);
1782 
1783 	strlcpy(info->driver, "cpsw", sizeof(info->driver));
1784 	strlcpy(info->version, "1.0", sizeof(info->version));
1785 	strlcpy(info->bus_info, priv->pdev->name, sizeof(info->bus_info));
1786 	info->regdump_len = cpsw_get_regs_len(ndev);
1787 }
1788 
1789 static u32 cpsw_get_msglevel(struct net_device *ndev)
1790 {
1791 	struct cpsw_priv *priv = netdev_priv(ndev);
1792 	return priv->msg_enable;
1793 }
1794 
1795 static void cpsw_set_msglevel(struct net_device *ndev, u32 value)
1796 {
1797 	struct cpsw_priv *priv = netdev_priv(ndev);
1798 	priv->msg_enable = value;
1799 }
1800 
1801 static int cpsw_get_ts_info(struct net_device *ndev,
1802 			    struct ethtool_ts_info *info)
1803 {
1804 #ifdef CONFIG_TI_CPTS
1805 	struct cpsw_priv *priv = netdev_priv(ndev);
1806 
1807 	info->so_timestamping =
1808 		SOF_TIMESTAMPING_TX_HARDWARE |
1809 		SOF_TIMESTAMPING_TX_SOFTWARE |
1810 		SOF_TIMESTAMPING_RX_HARDWARE |
1811 		SOF_TIMESTAMPING_RX_SOFTWARE |
1812 		SOF_TIMESTAMPING_SOFTWARE |
1813 		SOF_TIMESTAMPING_RAW_HARDWARE;
1814 	info->phc_index = priv->cpts->phc_index;
1815 	info->tx_types =
1816 		(1 << HWTSTAMP_TX_OFF) |
1817 		(1 << HWTSTAMP_TX_ON);
1818 	info->rx_filters =
1819 		(1 << HWTSTAMP_FILTER_NONE) |
1820 		(1 << HWTSTAMP_FILTER_PTP_V2_EVENT);
1821 #else
1822 	info->so_timestamping =
1823 		SOF_TIMESTAMPING_TX_SOFTWARE |
1824 		SOF_TIMESTAMPING_RX_SOFTWARE |
1825 		SOF_TIMESTAMPING_SOFTWARE;
1826 	info->phc_index = -1;
1827 	info->tx_types = 0;
1828 	info->rx_filters = 0;
1829 #endif
1830 	return 0;
1831 }
1832 
1833 static int cpsw_get_settings(struct net_device *ndev,
1834 			     struct ethtool_cmd *ecmd)
1835 {
1836 	struct cpsw_priv *priv = netdev_priv(ndev);
1837 	int slave_no = cpsw_slave_index(priv);
1838 
1839 	if (priv->slaves[slave_no].phy)
1840 		return phy_ethtool_gset(priv->slaves[slave_no].phy, ecmd);
1841 	else
1842 		return -EOPNOTSUPP;
1843 }
1844 
1845 static int cpsw_set_settings(struct net_device *ndev, struct ethtool_cmd *ecmd)
1846 {
1847 	struct cpsw_priv *priv = netdev_priv(ndev);
1848 	int slave_no = cpsw_slave_index(priv);
1849 
1850 	if (priv->slaves[slave_no].phy)
1851 		return phy_ethtool_sset(priv->slaves[slave_no].phy, ecmd);
1852 	else
1853 		return -EOPNOTSUPP;
1854 }
1855 
1856 static void cpsw_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
1857 {
1858 	struct cpsw_priv *priv = netdev_priv(ndev);
1859 	int slave_no = cpsw_slave_index(priv);
1860 
1861 	wol->supported = 0;
1862 	wol->wolopts = 0;
1863 
1864 	if (priv->slaves[slave_no].phy)
1865 		phy_ethtool_get_wol(priv->slaves[slave_no].phy, wol);
1866 }
1867 
1868 static int cpsw_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
1869 {
1870 	struct cpsw_priv *priv = netdev_priv(ndev);
1871 	int slave_no = cpsw_slave_index(priv);
1872 
1873 	if (priv->slaves[slave_no].phy)
1874 		return phy_ethtool_set_wol(priv->slaves[slave_no].phy, wol);
1875 	else
1876 		return -EOPNOTSUPP;
1877 }
1878 
1879 static void cpsw_get_pauseparam(struct net_device *ndev,
1880 				struct ethtool_pauseparam *pause)
1881 {
1882 	struct cpsw_priv *priv = netdev_priv(ndev);
1883 
1884 	pause->autoneg = AUTONEG_DISABLE;
1885 	pause->rx_pause = priv->rx_pause ? true : false;
1886 	pause->tx_pause = priv->tx_pause ? true : false;
1887 }
1888 
1889 static int cpsw_set_pauseparam(struct net_device *ndev,
1890 			       struct ethtool_pauseparam *pause)
1891 {
1892 	struct cpsw_priv *priv = netdev_priv(ndev);
1893 	bool link;
1894 
1895 	priv->rx_pause = pause->rx_pause ? true : false;
1896 	priv->tx_pause = pause->tx_pause ? true : false;
1897 
1898 	for_each_slave(priv, _cpsw_adjust_link, priv, &link);
1899 
1900 	return 0;
1901 }
1902 
1903 static const struct ethtool_ops cpsw_ethtool_ops = {
1904 	.get_drvinfo	= cpsw_get_drvinfo,
1905 	.get_msglevel	= cpsw_get_msglevel,
1906 	.set_msglevel	= cpsw_set_msglevel,
1907 	.get_link	= ethtool_op_get_link,
1908 	.get_ts_info	= cpsw_get_ts_info,
1909 	.get_settings	= cpsw_get_settings,
1910 	.set_settings	= cpsw_set_settings,
1911 	.get_coalesce	= cpsw_get_coalesce,
1912 	.set_coalesce	= cpsw_set_coalesce,
1913 	.get_sset_count		= cpsw_get_sset_count,
1914 	.get_strings		= cpsw_get_strings,
1915 	.get_ethtool_stats	= cpsw_get_ethtool_stats,
1916 	.get_pauseparam		= cpsw_get_pauseparam,
1917 	.set_pauseparam		= cpsw_set_pauseparam,
1918 	.get_wol	= cpsw_get_wol,
1919 	.set_wol	= cpsw_set_wol,
1920 	.get_regs_len	= cpsw_get_regs_len,
1921 	.get_regs	= cpsw_get_regs,
1922 };
1923 
1924 static void cpsw_slave_init(struct cpsw_slave *slave, struct cpsw_priv *priv,
1925 			    u32 slave_reg_ofs, u32 sliver_reg_ofs)
1926 {
1927 	void __iomem		*regs = priv->regs;
1928 	int			slave_num = slave->slave_num;
1929 	struct cpsw_slave_data	*data = priv->data.slave_data + slave_num;
1930 
1931 	slave->data	= data;
1932 	slave->regs	= regs + slave_reg_ofs;
1933 	slave->sliver	= regs + sliver_reg_ofs;
1934 	slave->port_vlan = data->dual_emac_res_vlan;
1935 }
1936 
1937 static int cpsw_probe_dt(struct cpsw_platform_data *data,
1938 			 struct platform_device *pdev)
1939 {
1940 	struct device_node *node = pdev->dev.of_node;
1941 	struct device_node *slave_node;
1942 	int i = 0, ret;
1943 	u32 prop;
1944 
1945 	if (!node)
1946 		return -EINVAL;
1947 
1948 	if (of_property_read_u32(node, "slaves", &prop)) {
1949 		dev_err(&pdev->dev, "Missing slaves property in the DT.\n");
1950 		return -EINVAL;
1951 	}
1952 	data->slaves = prop;
1953 
1954 	if (of_property_read_u32(node, "active_slave", &prop)) {
1955 		dev_err(&pdev->dev, "Missing active_slave property in the DT.\n");
1956 		return -EINVAL;
1957 	}
1958 	data->active_slave = prop;
1959 
1960 	if (of_property_read_u32(node, "cpts_clock_mult", &prop)) {
1961 		dev_err(&pdev->dev, "Missing cpts_clock_mult property in the DT.\n");
1962 		return -EINVAL;
1963 	}
1964 	data->cpts_clock_mult = prop;
1965 
1966 	if (of_property_read_u32(node, "cpts_clock_shift", &prop)) {
1967 		dev_err(&pdev->dev, "Missing cpts_clock_shift property in the DT.\n");
1968 		return -EINVAL;
1969 	}
1970 	data->cpts_clock_shift = prop;
1971 
1972 	data->slave_data = devm_kzalloc(&pdev->dev, data->slaves
1973 					* sizeof(struct cpsw_slave_data),
1974 					GFP_KERNEL);
1975 	if (!data->slave_data)
1976 		return -ENOMEM;
1977 
1978 	if (of_property_read_u32(node, "cpdma_channels", &prop)) {
1979 		dev_err(&pdev->dev, "Missing cpdma_channels property in the DT.\n");
1980 		return -EINVAL;
1981 	}
1982 	data->channels = prop;
1983 
1984 	if (of_property_read_u32(node, "ale_entries", &prop)) {
1985 		dev_err(&pdev->dev, "Missing ale_entries property in the DT.\n");
1986 		return -EINVAL;
1987 	}
1988 	data->ale_entries = prop;
1989 
1990 	if (of_property_read_u32(node, "bd_ram_size", &prop)) {
1991 		dev_err(&pdev->dev, "Missing bd_ram_size property in the DT.\n");
1992 		return -EINVAL;
1993 	}
1994 	data->bd_ram_size = prop;
1995 
1996 	if (of_property_read_u32(node, "rx_descs", &prop)) {
1997 		dev_err(&pdev->dev, "Missing rx_descs property in the DT.\n");
1998 		return -EINVAL;
1999 	}
2000 	data->rx_descs = prop;
2001 
2002 	if (of_property_read_u32(node, "mac_control", &prop)) {
2003 		dev_err(&pdev->dev, "Missing mac_control property in the DT.\n");
2004 		return -EINVAL;
2005 	}
2006 	data->mac_control = prop;
2007 
2008 	if (of_property_read_bool(node, "dual_emac"))
2009 		data->dual_emac = 1;
2010 
2011 	/*
2012 	 * Populate all the child nodes here...
2013 	 */
2014 	ret = of_platform_populate(node, NULL, NULL, &pdev->dev);
2015 	/* We do not want to force this, as in some cases may not have child */
2016 	if (ret)
2017 		dev_warn(&pdev->dev, "Doesn't have any child node\n");
2018 
2019 	for_each_child_of_node(node, slave_node) {
2020 		struct cpsw_slave_data *slave_data = data->slave_data + i;
2021 		const void *mac_addr = NULL;
2022 		u32 phyid;
2023 		int lenp;
2024 		const __be32 *parp;
2025 		struct device_node *mdio_node;
2026 		struct platform_device *mdio;
2027 
2028 		/* This is no slave child node, continue */
2029 		if (strcmp(slave_node->name, "slave"))
2030 			continue;
2031 
2032 		parp = of_get_property(slave_node, "phy_id", &lenp);
2033 		if ((parp == NULL) || (lenp != (sizeof(void *) * 2))) {
2034 			dev_err(&pdev->dev, "Missing slave[%d] phy_id property\n", i);
2035 			goto no_phy_slave;
2036 		}
2037 		mdio_node = of_find_node_by_phandle(be32_to_cpup(parp));
2038 		phyid = be32_to_cpup(parp+1);
2039 		mdio = of_find_device_by_node(mdio_node);
2040 		of_node_put(mdio_node);
2041 		if (!mdio) {
2042 			dev_err(&pdev->dev, "Missing mdio platform device\n");
2043 			return -EINVAL;
2044 		}
2045 		snprintf(slave_data->phy_id, sizeof(slave_data->phy_id),
2046 			 PHY_ID_FMT, mdio->name, phyid);
2047 
2048 		slave_data->phy_if = of_get_phy_mode(slave_node);
2049 		if (slave_data->phy_if < 0) {
2050 			dev_err(&pdev->dev, "Missing or malformed slave[%d] phy-mode property\n",
2051 				i);
2052 			return slave_data->phy_if;
2053 		}
2054 
2055 no_phy_slave:
2056 		mac_addr = of_get_mac_address(slave_node);
2057 		if (mac_addr) {
2058 			memcpy(slave_data->mac_addr, mac_addr, ETH_ALEN);
2059 		} else {
2060 			if (of_machine_is_compatible("ti,am33xx")) {
2061 				ret = cpsw_am33xx_cm_get_macid(&pdev->dev,
2062 							0x630, i,
2063 							slave_data->mac_addr);
2064 				if (ret)
2065 					return ret;
2066 			}
2067 		}
2068 		if (data->dual_emac) {
2069 			if (of_property_read_u32(slave_node, "dual_emac_res_vlan",
2070 						 &prop)) {
2071 				dev_err(&pdev->dev, "Missing dual_emac_res_vlan in DT.\n");
2072 				slave_data->dual_emac_res_vlan = i+1;
2073 				dev_err(&pdev->dev, "Using %d as Reserved VLAN for %d slave\n",
2074 					slave_data->dual_emac_res_vlan, i);
2075 			} else {
2076 				slave_data->dual_emac_res_vlan = prop;
2077 			}
2078 		}
2079 
2080 		i++;
2081 		if (i == data->slaves)
2082 			break;
2083 	}
2084 
2085 	return 0;
2086 }
2087 
2088 static int cpsw_probe_dual_emac(struct platform_device *pdev,
2089 				struct cpsw_priv *priv)
2090 {
2091 	struct cpsw_platform_data	*data = &priv->data;
2092 	struct net_device		*ndev;
2093 	struct cpsw_priv		*priv_sl2;
2094 	int ret = 0, i;
2095 
2096 	ndev = alloc_etherdev(sizeof(struct cpsw_priv));
2097 	if (!ndev) {
2098 		dev_err(&pdev->dev, "cpsw: error allocating net_device\n");
2099 		return -ENOMEM;
2100 	}
2101 
2102 	priv_sl2 = netdev_priv(ndev);
2103 	spin_lock_init(&priv_sl2->lock);
2104 	priv_sl2->data = *data;
2105 	priv_sl2->pdev = pdev;
2106 	priv_sl2->ndev = ndev;
2107 	priv_sl2->dev  = &ndev->dev;
2108 	priv_sl2->msg_enable = netif_msg_init(debug_level, CPSW_DEBUG);
2109 	priv_sl2->rx_packet_max = max(rx_packet_max, 128);
2110 
2111 	if (is_valid_ether_addr(data->slave_data[1].mac_addr)) {
2112 		memcpy(priv_sl2->mac_addr, data->slave_data[1].mac_addr,
2113 			ETH_ALEN);
2114 		dev_info(&pdev->dev, "cpsw: Detected MACID = %pM\n", priv_sl2->mac_addr);
2115 	} else {
2116 		random_ether_addr(priv_sl2->mac_addr);
2117 		dev_info(&pdev->dev, "cpsw: Random MACID = %pM\n", priv_sl2->mac_addr);
2118 	}
2119 	memcpy(ndev->dev_addr, priv_sl2->mac_addr, ETH_ALEN);
2120 
2121 	priv_sl2->slaves = priv->slaves;
2122 	priv_sl2->clk = priv->clk;
2123 
2124 	priv_sl2->coal_intvl = 0;
2125 	priv_sl2->bus_freq_mhz = priv->bus_freq_mhz;
2126 
2127 	priv_sl2->regs = priv->regs;
2128 	priv_sl2->host_port = priv->host_port;
2129 	priv_sl2->host_port_regs = priv->host_port_regs;
2130 	priv_sl2->wr_regs = priv->wr_regs;
2131 	priv_sl2->hw_stats = priv->hw_stats;
2132 	priv_sl2->dma = priv->dma;
2133 	priv_sl2->txch = priv->txch;
2134 	priv_sl2->rxch = priv->rxch;
2135 	priv_sl2->ale = priv->ale;
2136 	priv_sl2->emac_port = 1;
2137 	priv->slaves[1].ndev = ndev;
2138 	priv_sl2->cpts = priv->cpts;
2139 	priv_sl2->version = priv->version;
2140 
2141 	for (i = 0; i < priv->num_irqs; i++) {
2142 		priv_sl2->irqs_table[i] = priv->irqs_table[i];
2143 		priv_sl2->num_irqs = priv->num_irqs;
2144 	}
2145 	ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
2146 
2147 	ndev->netdev_ops = &cpsw_netdev_ops;
2148 	ndev->ethtool_ops = &cpsw_ethtool_ops;
2149 
2150 	/* register the network device */
2151 	SET_NETDEV_DEV(ndev, &pdev->dev);
2152 	ret = register_netdev(ndev);
2153 	if (ret) {
2154 		dev_err(&pdev->dev, "cpsw: error registering net device\n");
2155 		free_netdev(ndev);
2156 		ret = -ENODEV;
2157 	}
2158 
2159 	return ret;
2160 }
2161 
2162 #define CPSW_QUIRK_IRQ		BIT(0)
2163 
2164 static struct platform_device_id cpsw_devtype[] = {
2165 	{
2166 		/* keep it for existing comaptibles */
2167 		.name = "cpsw",
2168 		.driver_data = CPSW_QUIRK_IRQ,
2169 	}, {
2170 		.name = "am335x-cpsw",
2171 		.driver_data = CPSW_QUIRK_IRQ,
2172 	}, {
2173 		.name = "am4372-cpsw",
2174 		.driver_data = 0,
2175 	}, {
2176 		.name = "dra7-cpsw",
2177 		.driver_data = 0,
2178 	}, {
2179 		/* sentinel */
2180 	}
2181 };
2182 MODULE_DEVICE_TABLE(platform, cpsw_devtype);
2183 
2184 enum ti_cpsw_type {
2185 	CPSW = 0,
2186 	AM335X_CPSW,
2187 	AM4372_CPSW,
2188 	DRA7_CPSW,
2189 };
2190 
2191 static const struct of_device_id cpsw_of_mtable[] = {
2192 	{ .compatible = "ti,cpsw", .data = &cpsw_devtype[CPSW], },
2193 	{ .compatible = "ti,am335x-cpsw", .data = &cpsw_devtype[AM335X_CPSW], },
2194 	{ .compatible = "ti,am4372-cpsw", .data = &cpsw_devtype[AM4372_CPSW], },
2195 	{ .compatible = "ti,dra7-cpsw", .data = &cpsw_devtype[DRA7_CPSW], },
2196 	{ /* sentinel */ },
2197 };
2198 MODULE_DEVICE_TABLE(of, cpsw_of_mtable);
2199 
2200 static int cpsw_probe(struct platform_device *pdev)
2201 {
2202 	struct cpsw_platform_data	*data;
2203 	struct net_device		*ndev;
2204 	struct cpsw_priv		*priv;
2205 	struct cpdma_params		dma_params;
2206 	struct cpsw_ale_params		ale_params;
2207 	void __iomem			*ss_regs;
2208 	struct resource			*res, *ss_res;
2209 	const struct of_device_id	*of_id;
2210 	u32 slave_offset, sliver_offset, slave_size;
2211 	int ret = 0, i;
2212 	int irq;
2213 
2214 	ndev = alloc_etherdev(sizeof(struct cpsw_priv));
2215 	if (!ndev) {
2216 		dev_err(&pdev->dev, "error allocating net_device\n");
2217 		return -ENOMEM;
2218 	}
2219 
2220 	platform_set_drvdata(pdev, ndev);
2221 	priv = netdev_priv(ndev);
2222 	spin_lock_init(&priv->lock);
2223 	priv->pdev = pdev;
2224 	priv->ndev = ndev;
2225 	priv->dev  = &ndev->dev;
2226 	priv->msg_enable = netif_msg_init(debug_level, CPSW_DEBUG);
2227 	priv->rx_packet_max = max(rx_packet_max, 128);
2228 	priv->cpts = devm_kzalloc(&pdev->dev, sizeof(struct cpts), GFP_KERNEL);
2229 	if (!priv->cpts) {
2230 		dev_err(&pdev->dev, "error allocating cpts\n");
2231 		ret = -ENOMEM;
2232 		goto clean_ndev_ret;
2233 	}
2234 
2235 	/*
2236 	 * This may be required here for child devices.
2237 	 */
2238 	pm_runtime_enable(&pdev->dev);
2239 
2240 	/* Select default pin state */
2241 	pinctrl_pm_select_default_state(&pdev->dev);
2242 
2243 	if (cpsw_probe_dt(&priv->data, pdev)) {
2244 		dev_err(&pdev->dev, "cpsw: platform data missing\n");
2245 		ret = -ENODEV;
2246 		goto clean_runtime_disable_ret;
2247 	}
2248 	data = &priv->data;
2249 
2250 	if (is_valid_ether_addr(data->slave_data[0].mac_addr)) {
2251 		memcpy(priv->mac_addr, data->slave_data[0].mac_addr, ETH_ALEN);
2252 		dev_info(&pdev->dev, "Detected MACID = %pM\n", priv->mac_addr);
2253 	} else {
2254 		eth_random_addr(priv->mac_addr);
2255 		dev_info(&pdev->dev, "Random MACID = %pM\n", priv->mac_addr);
2256 	}
2257 
2258 	memcpy(ndev->dev_addr, priv->mac_addr, ETH_ALEN);
2259 
2260 	priv->slaves = devm_kzalloc(&pdev->dev,
2261 				    sizeof(struct cpsw_slave) * data->slaves,
2262 				    GFP_KERNEL);
2263 	if (!priv->slaves) {
2264 		ret = -ENOMEM;
2265 		goto clean_runtime_disable_ret;
2266 	}
2267 	for (i = 0; i < data->slaves; i++)
2268 		priv->slaves[i].slave_num = i;
2269 
2270 	priv->slaves[0].ndev = ndev;
2271 	priv->emac_port = 0;
2272 
2273 	priv->clk = devm_clk_get(&pdev->dev, "fck");
2274 	if (IS_ERR(priv->clk)) {
2275 		dev_err(priv->dev, "fck is not found\n");
2276 		ret = -ENODEV;
2277 		goto clean_runtime_disable_ret;
2278 	}
2279 	priv->coal_intvl = 0;
2280 	priv->bus_freq_mhz = clk_get_rate(priv->clk) / 1000000;
2281 
2282 	ss_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2283 	ss_regs = devm_ioremap_resource(&pdev->dev, ss_res);
2284 	if (IS_ERR(ss_regs)) {
2285 		ret = PTR_ERR(ss_regs);
2286 		goto clean_runtime_disable_ret;
2287 	}
2288 	priv->regs = ss_regs;
2289 	priv->host_port = HOST_PORT_NUM;
2290 
2291 	/* Need to enable clocks with runtime PM api to access module
2292 	 * registers
2293 	 */
2294 	pm_runtime_get_sync(&pdev->dev);
2295 	priv->version = readl(&priv->regs->id_ver);
2296 	pm_runtime_put_sync(&pdev->dev);
2297 
2298 	res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
2299 	priv->wr_regs = devm_ioremap_resource(&pdev->dev, res);
2300 	if (IS_ERR(priv->wr_regs)) {
2301 		ret = PTR_ERR(priv->wr_regs);
2302 		goto clean_runtime_disable_ret;
2303 	}
2304 
2305 	memset(&dma_params, 0, sizeof(dma_params));
2306 	memset(&ale_params, 0, sizeof(ale_params));
2307 
2308 	switch (priv->version) {
2309 	case CPSW_VERSION_1:
2310 		priv->host_port_regs = ss_regs + CPSW1_HOST_PORT_OFFSET;
2311 		priv->cpts->reg      = ss_regs + CPSW1_CPTS_OFFSET;
2312 		priv->hw_stats	     = ss_regs + CPSW1_HW_STATS;
2313 		dma_params.dmaregs   = ss_regs + CPSW1_CPDMA_OFFSET;
2314 		dma_params.txhdp     = ss_regs + CPSW1_STATERAM_OFFSET;
2315 		ale_params.ale_regs  = ss_regs + CPSW1_ALE_OFFSET;
2316 		slave_offset         = CPSW1_SLAVE_OFFSET;
2317 		slave_size           = CPSW1_SLAVE_SIZE;
2318 		sliver_offset        = CPSW1_SLIVER_OFFSET;
2319 		dma_params.desc_mem_phys = 0;
2320 		break;
2321 	case CPSW_VERSION_2:
2322 	case CPSW_VERSION_3:
2323 	case CPSW_VERSION_4:
2324 		priv->host_port_regs = ss_regs + CPSW2_HOST_PORT_OFFSET;
2325 		priv->cpts->reg      = ss_regs + CPSW2_CPTS_OFFSET;
2326 		priv->hw_stats	     = ss_regs + CPSW2_HW_STATS;
2327 		dma_params.dmaregs   = ss_regs + CPSW2_CPDMA_OFFSET;
2328 		dma_params.txhdp     = ss_regs + CPSW2_STATERAM_OFFSET;
2329 		ale_params.ale_regs  = ss_regs + CPSW2_ALE_OFFSET;
2330 		slave_offset         = CPSW2_SLAVE_OFFSET;
2331 		slave_size           = CPSW2_SLAVE_SIZE;
2332 		sliver_offset        = CPSW2_SLIVER_OFFSET;
2333 		dma_params.desc_mem_phys =
2334 			(u32 __force) ss_res->start + CPSW2_BD_OFFSET;
2335 		break;
2336 	default:
2337 		dev_err(priv->dev, "unknown version 0x%08x\n", priv->version);
2338 		ret = -ENODEV;
2339 		goto clean_runtime_disable_ret;
2340 	}
2341 	for (i = 0; i < priv->data.slaves; i++) {
2342 		struct cpsw_slave *slave = &priv->slaves[i];
2343 		cpsw_slave_init(slave, priv, slave_offset, sliver_offset);
2344 		slave_offset  += slave_size;
2345 		sliver_offset += SLIVER_SIZE;
2346 	}
2347 
2348 	dma_params.dev		= &pdev->dev;
2349 	dma_params.rxthresh	= dma_params.dmaregs + CPDMA_RXTHRESH;
2350 	dma_params.rxfree	= dma_params.dmaregs + CPDMA_RXFREE;
2351 	dma_params.rxhdp	= dma_params.txhdp + CPDMA_RXHDP;
2352 	dma_params.txcp		= dma_params.txhdp + CPDMA_TXCP;
2353 	dma_params.rxcp		= dma_params.txhdp + CPDMA_RXCP;
2354 
2355 	dma_params.num_chan		= data->channels;
2356 	dma_params.has_soft_reset	= true;
2357 	dma_params.min_packet_size	= CPSW_MIN_PACKET_SIZE;
2358 	dma_params.desc_mem_size	= data->bd_ram_size;
2359 	dma_params.desc_align		= 16;
2360 	dma_params.has_ext_regs		= true;
2361 	dma_params.desc_hw_addr         = dma_params.desc_mem_phys;
2362 
2363 	priv->dma = cpdma_ctlr_create(&dma_params);
2364 	if (!priv->dma) {
2365 		dev_err(priv->dev, "error initializing dma\n");
2366 		ret = -ENOMEM;
2367 		goto clean_runtime_disable_ret;
2368 	}
2369 
2370 	priv->txch = cpdma_chan_create(priv->dma, tx_chan_num(0),
2371 				       cpsw_tx_handler);
2372 	priv->rxch = cpdma_chan_create(priv->dma, rx_chan_num(0),
2373 				       cpsw_rx_handler);
2374 
2375 	if (WARN_ON(!priv->txch || !priv->rxch)) {
2376 		dev_err(priv->dev, "error initializing dma channels\n");
2377 		ret = -ENOMEM;
2378 		goto clean_dma_ret;
2379 	}
2380 
2381 	ale_params.dev			= &ndev->dev;
2382 	ale_params.ale_ageout		= ale_ageout;
2383 	ale_params.ale_entries		= data->ale_entries;
2384 	ale_params.ale_ports		= data->slaves;
2385 
2386 	priv->ale = cpsw_ale_create(&ale_params);
2387 	if (!priv->ale) {
2388 		dev_err(priv->dev, "error initializing ale engine\n");
2389 		ret = -ENODEV;
2390 		goto clean_dma_ret;
2391 	}
2392 
2393 	ndev->irq = platform_get_irq(pdev, 1);
2394 	if (ndev->irq < 0) {
2395 		dev_err(priv->dev, "error getting irq resource\n");
2396 		ret = -ENOENT;
2397 		goto clean_ale_ret;
2398 	}
2399 
2400 	of_id = of_match_device(cpsw_of_mtable, &pdev->dev);
2401 	if (of_id) {
2402 		pdev->id_entry = of_id->data;
2403 		if (pdev->id_entry->driver_data)
2404 			priv->quirk_irq = true;
2405 	}
2406 
2407 	/* Grab RX and TX IRQs. Note that we also have RX_THRESHOLD and
2408 	 * MISC IRQs which are always kept disabled with this driver so
2409 	 * we will not request them.
2410 	 *
2411 	 * If anyone wants to implement support for those, make sure to
2412 	 * first request and append them to irqs_table array.
2413 	 */
2414 
2415 	/* RX IRQ */
2416 	irq = platform_get_irq(pdev, 1);
2417 	if (irq < 0)
2418 		goto clean_ale_ret;
2419 
2420 	priv->irqs_table[0] = irq;
2421 	ret = devm_request_irq(&pdev->dev, irq, cpsw_rx_interrupt,
2422 			       0, dev_name(&pdev->dev), priv);
2423 	if (ret < 0) {
2424 		dev_err(priv->dev, "error attaching irq (%d)\n", ret);
2425 		goto clean_ale_ret;
2426 	}
2427 
2428 	/* TX IRQ */
2429 	irq = platform_get_irq(pdev, 2);
2430 	if (irq < 0)
2431 		goto clean_ale_ret;
2432 
2433 	priv->irqs_table[1] = irq;
2434 	ret = devm_request_irq(&pdev->dev, irq, cpsw_tx_interrupt,
2435 			       0, dev_name(&pdev->dev), priv);
2436 	if (ret < 0) {
2437 		dev_err(priv->dev, "error attaching irq (%d)\n", ret);
2438 		goto clean_ale_ret;
2439 	}
2440 	priv->num_irqs = 2;
2441 
2442 	ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
2443 
2444 	ndev->netdev_ops = &cpsw_netdev_ops;
2445 	ndev->ethtool_ops = &cpsw_ethtool_ops;
2446 	netif_napi_add(ndev, &priv->napi_rx, cpsw_rx_poll, CPSW_POLL_WEIGHT);
2447 	netif_napi_add(ndev, &priv->napi_tx, cpsw_tx_poll, CPSW_POLL_WEIGHT);
2448 
2449 	/* register the network device */
2450 	SET_NETDEV_DEV(ndev, &pdev->dev);
2451 	ret = register_netdev(ndev);
2452 	if (ret) {
2453 		dev_err(priv->dev, "error registering net device\n");
2454 		ret = -ENODEV;
2455 		goto clean_ale_ret;
2456 	}
2457 
2458 	cpsw_notice(priv, probe, "initialized device (regs %pa, irq %d)\n",
2459 		    &ss_res->start, ndev->irq);
2460 
2461 	if (priv->data.dual_emac) {
2462 		ret = cpsw_probe_dual_emac(pdev, priv);
2463 		if (ret) {
2464 			cpsw_err(priv, probe, "error probe slave 2 emac interface\n");
2465 			goto clean_ale_ret;
2466 		}
2467 	}
2468 
2469 	return 0;
2470 
2471 clean_ale_ret:
2472 	cpsw_ale_destroy(priv->ale);
2473 clean_dma_ret:
2474 	cpdma_chan_destroy(priv->txch);
2475 	cpdma_chan_destroy(priv->rxch);
2476 	cpdma_ctlr_destroy(priv->dma);
2477 clean_runtime_disable_ret:
2478 	pm_runtime_disable(&pdev->dev);
2479 clean_ndev_ret:
2480 	free_netdev(priv->ndev);
2481 	return ret;
2482 }
2483 
2484 static int cpsw_remove_child_device(struct device *dev, void *c)
2485 {
2486 	struct platform_device *pdev = to_platform_device(dev);
2487 
2488 	of_device_unregister(pdev);
2489 
2490 	return 0;
2491 }
2492 
2493 static int cpsw_remove(struct platform_device *pdev)
2494 {
2495 	struct net_device *ndev = platform_get_drvdata(pdev);
2496 	struct cpsw_priv *priv = netdev_priv(ndev);
2497 
2498 	if (priv->data.dual_emac)
2499 		unregister_netdev(cpsw_get_slave_ndev(priv, 1));
2500 	unregister_netdev(ndev);
2501 
2502 	cpsw_ale_destroy(priv->ale);
2503 	cpdma_chan_destroy(priv->txch);
2504 	cpdma_chan_destroy(priv->rxch);
2505 	cpdma_ctlr_destroy(priv->dma);
2506 	pm_runtime_disable(&pdev->dev);
2507 	device_for_each_child(&pdev->dev, NULL, cpsw_remove_child_device);
2508 	if (priv->data.dual_emac)
2509 		free_netdev(cpsw_get_slave_ndev(priv, 1));
2510 	free_netdev(ndev);
2511 	return 0;
2512 }
2513 
2514 #ifdef CONFIG_PM_SLEEP
2515 static int cpsw_suspend(struct device *dev)
2516 {
2517 	struct platform_device	*pdev = to_platform_device(dev);
2518 	struct net_device	*ndev = platform_get_drvdata(pdev);
2519 	struct cpsw_priv	*priv = netdev_priv(ndev);
2520 
2521 	if (priv->data.dual_emac) {
2522 		int i;
2523 
2524 		for (i = 0; i < priv->data.slaves; i++) {
2525 			if (netif_running(priv->slaves[i].ndev))
2526 				cpsw_ndo_stop(priv->slaves[i].ndev);
2527 			soft_reset_slave(priv->slaves + i);
2528 		}
2529 	} else {
2530 		if (netif_running(ndev))
2531 			cpsw_ndo_stop(ndev);
2532 		for_each_slave(priv, soft_reset_slave);
2533 	}
2534 
2535 	pm_runtime_put_sync(&pdev->dev);
2536 
2537 	/* Select sleep pin state */
2538 	pinctrl_pm_select_sleep_state(&pdev->dev);
2539 
2540 	return 0;
2541 }
2542 
2543 static int cpsw_resume(struct device *dev)
2544 {
2545 	struct platform_device	*pdev = to_platform_device(dev);
2546 	struct net_device	*ndev = platform_get_drvdata(pdev);
2547 	struct cpsw_priv	*priv = netdev_priv(ndev);
2548 
2549 	pm_runtime_get_sync(&pdev->dev);
2550 
2551 	/* Select default pin state */
2552 	pinctrl_pm_select_default_state(&pdev->dev);
2553 
2554 	if (priv->data.dual_emac) {
2555 		int i;
2556 
2557 		for (i = 0; i < priv->data.slaves; i++) {
2558 			if (netif_running(priv->slaves[i].ndev))
2559 				cpsw_ndo_open(priv->slaves[i].ndev);
2560 		}
2561 	} else {
2562 		if (netif_running(ndev))
2563 			cpsw_ndo_open(ndev);
2564 	}
2565 	return 0;
2566 }
2567 #endif
2568 
2569 static SIMPLE_DEV_PM_OPS(cpsw_pm_ops, cpsw_suspend, cpsw_resume);
2570 
2571 static struct platform_driver cpsw_driver = {
2572 	.driver = {
2573 		.name	 = "cpsw",
2574 		.pm	 = &cpsw_pm_ops,
2575 		.of_match_table = cpsw_of_mtable,
2576 	},
2577 	.probe = cpsw_probe,
2578 	.remove = cpsw_remove,
2579 };
2580 
2581 static int __init cpsw_init(void)
2582 {
2583 	return platform_driver_register(&cpsw_driver);
2584 }
2585 late_initcall(cpsw_init);
2586 
2587 static void __exit cpsw_exit(void)
2588 {
2589 	platform_driver_unregister(&cpsw_driver);
2590 }
2591 module_exit(cpsw_exit);
2592 
2593 MODULE_LICENSE("GPL");
2594 MODULE_AUTHOR("Cyril Chemparathy <cyril@ti.com>");
2595 MODULE_AUTHOR("Mugunthan V N <mugunthanvnm@ti.com>");
2596 MODULE_DESCRIPTION("TI CPSW Ethernet driver");
2597