1 /* 2 * Texas Instruments Ethernet Switch Driver 3 * 4 * Copyright (C) 2012 Texas Instruments 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License as 8 * published by the Free Software Foundation version 2. 9 * 10 * This program is distributed "as is" WITHOUT ANY WARRANTY of any 11 * kind, whether express or implied; without even the implied warranty 12 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 */ 15 16 #include <linux/kernel.h> 17 #include <linux/io.h> 18 #include <linux/clk.h> 19 #include <linux/timer.h> 20 #include <linux/module.h> 21 #include <linux/platform_device.h> 22 #include <linux/irqreturn.h> 23 #include <linux/interrupt.h> 24 #include <linux/if_ether.h> 25 #include <linux/etherdevice.h> 26 #include <linux/netdevice.h> 27 #include <linux/net_tstamp.h> 28 #include <linux/phy.h> 29 #include <linux/workqueue.h> 30 #include <linux/delay.h> 31 #include <linux/pm_runtime.h> 32 #include <linux/of.h> 33 #include <linux/of_net.h> 34 #include <linux/of_device.h> 35 #include <linux/if_vlan.h> 36 37 #include <linux/pinctrl/consumer.h> 38 39 #include "cpsw.h" 40 #include "cpsw_ale.h" 41 #include "cpts.h" 42 #include "davinci_cpdma.h" 43 44 #define CPSW_DEBUG (NETIF_MSG_HW | NETIF_MSG_WOL | \ 45 NETIF_MSG_DRV | NETIF_MSG_LINK | \ 46 NETIF_MSG_IFUP | NETIF_MSG_INTR | \ 47 NETIF_MSG_PROBE | NETIF_MSG_TIMER | \ 48 NETIF_MSG_IFDOWN | NETIF_MSG_RX_ERR | \ 49 NETIF_MSG_TX_ERR | NETIF_MSG_TX_DONE | \ 50 NETIF_MSG_PKTDATA | NETIF_MSG_TX_QUEUED | \ 51 NETIF_MSG_RX_STATUS) 52 53 #define cpsw_info(priv, type, format, ...) \ 54 do { \ 55 if (netif_msg_##type(priv) && net_ratelimit()) \ 56 dev_info(priv->dev, format, ## __VA_ARGS__); \ 57 } while (0) 58 59 #define cpsw_err(priv, type, format, ...) \ 60 do { \ 61 if (netif_msg_##type(priv) && net_ratelimit()) \ 62 dev_err(priv->dev, format, ## __VA_ARGS__); \ 63 } while (0) 64 65 #define cpsw_dbg(priv, type, format, ...) \ 66 do { \ 67 if (netif_msg_##type(priv) && net_ratelimit()) \ 68 dev_dbg(priv->dev, format, ## __VA_ARGS__); \ 69 } while (0) 70 71 #define cpsw_notice(priv, type, format, ...) \ 72 do { \ 73 if (netif_msg_##type(priv) && net_ratelimit()) \ 74 dev_notice(priv->dev, format, ## __VA_ARGS__); \ 75 } while (0) 76 77 #define ALE_ALL_PORTS 0x7 78 79 #define CPSW_MAJOR_VERSION(reg) (reg >> 8 & 0x7) 80 #define CPSW_MINOR_VERSION(reg) (reg & 0xff) 81 #define CPSW_RTL_VERSION(reg) ((reg >> 11) & 0x1f) 82 83 #define CPSW_VERSION_1 0x19010a 84 #define CPSW_VERSION_2 0x19010c 85 #define CPSW_VERSION_3 0x19010f 86 #define CPSW_VERSION_4 0x190112 87 88 #define HOST_PORT_NUM 0 89 #define SLIVER_SIZE 0x40 90 91 #define CPSW1_HOST_PORT_OFFSET 0x028 92 #define CPSW1_SLAVE_OFFSET 0x050 93 #define CPSW1_SLAVE_SIZE 0x040 94 #define CPSW1_CPDMA_OFFSET 0x100 95 #define CPSW1_STATERAM_OFFSET 0x200 96 #define CPSW1_HW_STATS 0x400 97 #define CPSW1_CPTS_OFFSET 0x500 98 #define CPSW1_ALE_OFFSET 0x600 99 #define CPSW1_SLIVER_OFFSET 0x700 100 101 #define CPSW2_HOST_PORT_OFFSET 0x108 102 #define CPSW2_SLAVE_OFFSET 0x200 103 #define CPSW2_SLAVE_SIZE 0x100 104 #define CPSW2_CPDMA_OFFSET 0x800 105 #define CPSW2_HW_STATS 0x900 106 #define CPSW2_STATERAM_OFFSET 0xa00 107 #define CPSW2_CPTS_OFFSET 0xc00 108 #define CPSW2_ALE_OFFSET 0xd00 109 #define CPSW2_SLIVER_OFFSET 0xd80 110 #define CPSW2_BD_OFFSET 0x2000 111 112 #define CPDMA_RXTHRESH 0x0c0 113 #define CPDMA_RXFREE 0x0e0 114 #define CPDMA_TXHDP 0x00 115 #define CPDMA_RXHDP 0x20 116 #define CPDMA_TXCP 0x40 117 #define CPDMA_RXCP 0x60 118 119 #define CPSW_POLL_WEIGHT 64 120 #define CPSW_MIN_PACKET_SIZE 60 121 #define CPSW_MAX_PACKET_SIZE (1500 + 14 + 4 + 4) 122 123 #define RX_PRIORITY_MAPPING 0x76543210 124 #define TX_PRIORITY_MAPPING 0x33221100 125 #define CPDMA_TX_PRIORITY_MAP 0x76543210 126 127 #define CPSW_VLAN_AWARE BIT(1) 128 #define CPSW_ALE_VLAN_AWARE 1 129 130 #define CPSW_FIFO_NORMAL_MODE (0 << 15) 131 #define CPSW_FIFO_DUAL_MAC_MODE (1 << 15) 132 #define CPSW_FIFO_RATE_LIMIT_MODE (2 << 15) 133 134 #define CPSW_INTPACEEN (0x3f << 16) 135 #define CPSW_INTPRESCALE_MASK (0x7FF << 0) 136 #define CPSW_CMINTMAX_CNT 63 137 #define CPSW_CMINTMIN_CNT 2 138 #define CPSW_CMINTMAX_INTVL (1000 / CPSW_CMINTMIN_CNT) 139 #define CPSW_CMINTMIN_INTVL ((1000 / CPSW_CMINTMAX_CNT) + 1) 140 141 #define cpsw_enable_irq(priv) \ 142 do { \ 143 u32 i; \ 144 for (i = 0; i < priv->num_irqs; i++) \ 145 enable_irq(priv->irqs_table[i]); \ 146 } while (0); 147 #define cpsw_disable_irq(priv) \ 148 do { \ 149 u32 i; \ 150 for (i = 0; i < priv->num_irqs; i++) \ 151 disable_irq_nosync(priv->irqs_table[i]); \ 152 } while (0); 153 154 #define cpsw_slave_index(priv) \ 155 ((priv->data.dual_emac) ? priv->emac_port : \ 156 priv->data.active_slave) 157 158 static int debug_level; 159 module_param(debug_level, int, 0); 160 MODULE_PARM_DESC(debug_level, "cpsw debug level (NETIF_MSG bits)"); 161 162 static int ale_ageout = 10; 163 module_param(ale_ageout, int, 0); 164 MODULE_PARM_DESC(ale_ageout, "cpsw ale ageout interval (seconds)"); 165 166 static int rx_packet_max = CPSW_MAX_PACKET_SIZE; 167 module_param(rx_packet_max, int, 0); 168 MODULE_PARM_DESC(rx_packet_max, "maximum receive packet size (bytes)"); 169 170 struct cpsw_wr_regs { 171 u32 id_ver; 172 u32 soft_reset; 173 u32 control; 174 u32 int_control; 175 u32 rx_thresh_en; 176 u32 rx_en; 177 u32 tx_en; 178 u32 misc_en; 179 u32 mem_allign1[8]; 180 u32 rx_thresh_stat; 181 u32 rx_stat; 182 u32 tx_stat; 183 u32 misc_stat; 184 u32 mem_allign2[8]; 185 u32 rx_imax; 186 u32 tx_imax; 187 188 }; 189 190 struct cpsw_ss_regs { 191 u32 id_ver; 192 u32 control; 193 u32 soft_reset; 194 u32 stat_port_en; 195 u32 ptype; 196 u32 soft_idle; 197 u32 thru_rate; 198 u32 gap_thresh; 199 u32 tx_start_wds; 200 u32 flow_control; 201 u32 vlan_ltype; 202 u32 ts_ltype; 203 u32 dlr_ltype; 204 }; 205 206 /* CPSW_PORT_V1 */ 207 #define CPSW1_MAX_BLKS 0x00 /* Maximum FIFO Blocks */ 208 #define CPSW1_BLK_CNT 0x04 /* FIFO Block Usage Count (Read Only) */ 209 #define CPSW1_TX_IN_CTL 0x08 /* Transmit FIFO Control */ 210 #define CPSW1_PORT_VLAN 0x0c /* VLAN Register */ 211 #define CPSW1_TX_PRI_MAP 0x10 /* Tx Header Priority to Switch Pri Mapping */ 212 #define CPSW1_TS_CTL 0x14 /* Time Sync Control */ 213 #define CPSW1_TS_SEQ_LTYPE 0x18 /* Time Sync Sequence ID Offset and Msg Type */ 214 #define CPSW1_TS_VLAN 0x1c /* Time Sync VLAN1 and VLAN2 */ 215 216 /* CPSW_PORT_V2 */ 217 #define CPSW2_CONTROL 0x00 /* Control Register */ 218 #define CPSW2_MAX_BLKS 0x08 /* Maximum FIFO Blocks */ 219 #define CPSW2_BLK_CNT 0x0c /* FIFO Block Usage Count (Read Only) */ 220 #define CPSW2_TX_IN_CTL 0x10 /* Transmit FIFO Control */ 221 #define CPSW2_PORT_VLAN 0x14 /* VLAN Register */ 222 #define CPSW2_TX_PRI_MAP 0x18 /* Tx Header Priority to Switch Pri Mapping */ 223 #define CPSW2_TS_SEQ_MTYPE 0x1c /* Time Sync Sequence ID Offset and Msg Type */ 224 225 /* CPSW_PORT_V1 and V2 */ 226 #define SA_LO 0x20 /* CPGMAC_SL Source Address Low */ 227 #define SA_HI 0x24 /* CPGMAC_SL Source Address High */ 228 #define SEND_PERCENT 0x28 /* Transmit Queue Send Percentages */ 229 230 /* CPSW_PORT_V2 only */ 231 #define RX_DSCP_PRI_MAP0 0x30 /* Rx DSCP Priority to Rx Packet Mapping */ 232 #define RX_DSCP_PRI_MAP1 0x34 /* Rx DSCP Priority to Rx Packet Mapping */ 233 #define RX_DSCP_PRI_MAP2 0x38 /* Rx DSCP Priority to Rx Packet Mapping */ 234 #define RX_DSCP_PRI_MAP3 0x3c /* Rx DSCP Priority to Rx Packet Mapping */ 235 #define RX_DSCP_PRI_MAP4 0x40 /* Rx DSCP Priority to Rx Packet Mapping */ 236 #define RX_DSCP_PRI_MAP5 0x44 /* Rx DSCP Priority to Rx Packet Mapping */ 237 #define RX_DSCP_PRI_MAP6 0x48 /* Rx DSCP Priority to Rx Packet Mapping */ 238 #define RX_DSCP_PRI_MAP7 0x4c /* Rx DSCP Priority to Rx Packet Mapping */ 239 240 /* Bit definitions for the CPSW2_CONTROL register */ 241 #define PASS_PRI_TAGGED (1<<24) /* Pass Priority Tagged */ 242 #define VLAN_LTYPE2_EN (1<<21) /* VLAN LTYPE 2 enable */ 243 #define VLAN_LTYPE1_EN (1<<20) /* VLAN LTYPE 1 enable */ 244 #define DSCP_PRI_EN (1<<16) /* DSCP Priority Enable */ 245 #define TS_320 (1<<14) /* Time Sync Dest Port 320 enable */ 246 #define TS_319 (1<<13) /* Time Sync Dest Port 319 enable */ 247 #define TS_132 (1<<12) /* Time Sync Dest IP Addr 132 enable */ 248 #define TS_131 (1<<11) /* Time Sync Dest IP Addr 131 enable */ 249 #define TS_130 (1<<10) /* Time Sync Dest IP Addr 130 enable */ 250 #define TS_129 (1<<9) /* Time Sync Dest IP Addr 129 enable */ 251 #define TS_BIT8 (1<<8) /* ts_ttl_nonzero? */ 252 #define TS_ANNEX_D_EN (1<<4) /* Time Sync Annex D enable */ 253 #define TS_LTYPE2_EN (1<<3) /* Time Sync LTYPE 2 enable */ 254 #define TS_LTYPE1_EN (1<<2) /* Time Sync LTYPE 1 enable */ 255 #define TS_TX_EN (1<<1) /* Time Sync Transmit Enable */ 256 #define TS_RX_EN (1<<0) /* Time Sync Receive Enable */ 257 258 #define CTRL_TS_BITS \ 259 (TS_320 | TS_319 | TS_132 | TS_131 | TS_130 | TS_129 | TS_BIT8 | \ 260 TS_ANNEX_D_EN | TS_LTYPE1_EN) 261 262 #define CTRL_ALL_TS_MASK (CTRL_TS_BITS | TS_TX_EN | TS_RX_EN) 263 #define CTRL_TX_TS_BITS (CTRL_TS_BITS | TS_TX_EN) 264 #define CTRL_RX_TS_BITS (CTRL_TS_BITS | TS_RX_EN) 265 266 /* Bit definitions for the CPSW2_TS_SEQ_MTYPE register */ 267 #define TS_SEQ_ID_OFFSET_SHIFT (16) /* Time Sync Sequence ID Offset */ 268 #define TS_SEQ_ID_OFFSET_MASK (0x3f) 269 #define TS_MSG_TYPE_EN_SHIFT (0) /* Time Sync Message Type Enable */ 270 #define TS_MSG_TYPE_EN_MASK (0xffff) 271 272 /* The PTP event messages - Sync, Delay_Req, Pdelay_Req, and Pdelay_Resp. */ 273 #define EVENT_MSG_BITS ((1<<0) | (1<<1) | (1<<2) | (1<<3)) 274 275 /* Bit definitions for the CPSW1_TS_CTL register */ 276 #define CPSW_V1_TS_RX_EN BIT(0) 277 #define CPSW_V1_TS_TX_EN BIT(4) 278 #define CPSW_V1_MSG_TYPE_OFS 16 279 280 /* Bit definitions for the CPSW1_TS_SEQ_LTYPE register */ 281 #define CPSW_V1_SEQ_ID_OFS_SHIFT 16 282 283 struct cpsw_host_regs { 284 u32 max_blks; 285 u32 blk_cnt; 286 u32 tx_in_ctl; 287 u32 port_vlan; 288 u32 tx_pri_map; 289 u32 cpdma_tx_pri_map; 290 u32 cpdma_rx_chan_map; 291 }; 292 293 struct cpsw_sliver_regs { 294 u32 id_ver; 295 u32 mac_control; 296 u32 mac_status; 297 u32 soft_reset; 298 u32 rx_maxlen; 299 u32 __reserved_0; 300 u32 rx_pause; 301 u32 tx_pause; 302 u32 __reserved_1; 303 u32 rx_pri_map; 304 }; 305 306 struct cpsw_hw_stats { 307 u32 rxgoodframes; 308 u32 rxbroadcastframes; 309 u32 rxmulticastframes; 310 u32 rxpauseframes; 311 u32 rxcrcerrors; 312 u32 rxaligncodeerrors; 313 u32 rxoversizedframes; 314 u32 rxjabberframes; 315 u32 rxundersizedframes; 316 u32 rxfragments; 317 u32 __pad_0[2]; 318 u32 rxoctets; 319 u32 txgoodframes; 320 u32 txbroadcastframes; 321 u32 txmulticastframes; 322 u32 txpauseframes; 323 u32 txdeferredframes; 324 u32 txcollisionframes; 325 u32 txsinglecollframes; 326 u32 txmultcollframes; 327 u32 txexcessivecollisions; 328 u32 txlatecollisions; 329 u32 txunderrun; 330 u32 txcarriersenseerrors; 331 u32 txoctets; 332 u32 octetframes64; 333 u32 octetframes65t127; 334 u32 octetframes128t255; 335 u32 octetframes256t511; 336 u32 octetframes512t1023; 337 u32 octetframes1024tup; 338 u32 netoctets; 339 u32 rxsofoverruns; 340 u32 rxmofoverruns; 341 u32 rxdmaoverruns; 342 }; 343 344 struct cpsw_slave { 345 void __iomem *regs; 346 struct cpsw_sliver_regs __iomem *sliver; 347 int slave_num; 348 u32 mac_control; 349 struct cpsw_slave_data *data; 350 struct phy_device *phy; 351 struct net_device *ndev; 352 u32 port_vlan; 353 u32 open_stat; 354 }; 355 356 static inline u32 slave_read(struct cpsw_slave *slave, u32 offset) 357 { 358 return __raw_readl(slave->regs + offset); 359 } 360 361 static inline void slave_write(struct cpsw_slave *slave, u32 val, u32 offset) 362 { 363 __raw_writel(val, slave->regs + offset); 364 } 365 366 struct cpsw_priv { 367 spinlock_t lock; 368 struct platform_device *pdev; 369 struct net_device *ndev; 370 struct napi_struct napi; 371 struct device *dev; 372 struct cpsw_platform_data data; 373 struct cpsw_ss_regs __iomem *regs; 374 struct cpsw_wr_regs __iomem *wr_regs; 375 u8 __iomem *hw_stats; 376 struct cpsw_host_regs __iomem *host_port_regs; 377 u32 msg_enable; 378 u32 version; 379 u32 coal_intvl; 380 u32 bus_freq_mhz; 381 struct net_device_stats stats; 382 int rx_packet_max; 383 int host_port; 384 struct clk *clk; 385 u8 mac_addr[ETH_ALEN]; 386 struct cpsw_slave *slaves; 387 struct cpdma_ctlr *dma; 388 struct cpdma_chan *txch, *rxch; 389 struct cpsw_ale *ale; 390 /* snapshot of IRQ numbers */ 391 u32 irqs_table[4]; 392 u32 num_irqs; 393 bool irq_enabled; 394 struct cpts *cpts; 395 u32 emac_port; 396 }; 397 398 struct cpsw_stats { 399 char stat_string[ETH_GSTRING_LEN]; 400 int type; 401 int sizeof_stat; 402 int stat_offset; 403 }; 404 405 enum { 406 CPSW_STATS, 407 CPDMA_RX_STATS, 408 CPDMA_TX_STATS, 409 }; 410 411 #define CPSW_STAT(m) CPSW_STATS, \ 412 sizeof(((struct cpsw_hw_stats *)0)->m), \ 413 offsetof(struct cpsw_hw_stats, m) 414 #define CPDMA_RX_STAT(m) CPDMA_RX_STATS, \ 415 sizeof(((struct cpdma_chan_stats *)0)->m), \ 416 offsetof(struct cpdma_chan_stats, m) 417 #define CPDMA_TX_STAT(m) CPDMA_TX_STATS, \ 418 sizeof(((struct cpdma_chan_stats *)0)->m), \ 419 offsetof(struct cpdma_chan_stats, m) 420 421 static const struct cpsw_stats cpsw_gstrings_stats[] = { 422 { "Good Rx Frames", CPSW_STAT(rxgoodframes) }, 423 { "Broadcast Rx Frames", CPSW_STAT(rxbroadcastframes) }, 424 { "Multicast Rx Frames", CPSW_STAT(rxmulticastframes) }, 425 { "Pause Rx Frames", CPSW_STAT(rxpauseframes) }, 426 { "Rx CRC Errors", CPSW_STAT(rxcrcerrors) }, 427 { "Rx Align/Code Errors", CPSW_STAT(rxaligncodeerrors) }, 428 { "Oversize Rx Frames", CPSW_STAT(rxoversizedframes) }, 429 { "Rx Jabbers", CPSW_STAT(rxjabberframes) }, 430 { "Undersize (Short) Rx Frames", CPSW_STAT(rxundersizedframes) }, 431 { "Rx Fragments", CPSW_STAT(rxfragments) }, 432 { "Rx Octets", CPSW_STAT(rxoctets) }, 433 { "Good Tx Frames", CPSW_STAT(txgoodframes) }, 434 { "Broadcast Tx Frames", CPSW_STAT(txbroadcastframes) }, 435 { "Multicast Tx Frames", CPSW_STAT(txmulticastframes) }, 436 { "Pause Tx Frames", CPSW_STAT(txpauseframes) }, 437 { "Deferred Tx Frames", CPSW_STAT(txdeferredframes) }, 438 { "Collisions", CPSW_STAT(txcollisionframes) }, 439 { "Single Collision Tx Frames", CPSW_STAT(txsinglecollframes) }, 440 { "Multiple Collision Tx Frames", CPSW_STAT(txmultcollframes) }, 441 { "Excessive Collisions", CPSW_STAT(txexcessivecollisions) }, 442 { "Late Collisions", CPSW_STAT(txlatecollisions) }, 443 { "Tx Underrun", CPSW_STAT(txunderrun) }, 444 { "Carrier Sense Errors", CPSW_STAT(txcarriersenseerrors) }, 445 { "Tx Octets", CPSW_STAT(txoctets) }, 446 { "Rx + Tx 64 Octet Frames", CPSW_STAT(octetframes64) }, 447 { "Rx + Tx 65-127 Octet Frames", CPSW_STAT(octetframes65t127) }, 448 { "Rx + Tx 128-255 Octet Frames", CPSW_STAT(octetframes128t255) }, 449 { "Rx + Tx 256-511 Octet Frames", CPSW_STAT(octetframes256t511) }, 450 { "Rx + Tx 512-1023 Octet Frames", CPSW_STAT(octetframes512t1023) }, 451 { "Rx + Tx 1024-Up Octet Frames", CPSW_STAT(octetframes1024tup) }, 452 { "Net Octets", CPSW_STAT(netoctets) }, 453 { "Rx Start of Frame Overruns", CPSW_STAT(rxsofoverruns) }, 454 { "Rx Middle of Frame Overruns", CPSW_STAT(rxmofoverruns) }, 455 { "Rx DMA Overruns", CPSW_STAT(rxdmaoverruns) }, 456 { "Rx DMA chan: head_enqueue", CPDMA_RX_STAT(head_enqueue) }, 457 { "Rx DMA chan: tail_enqueue", CPDMA_RX_STAT(tail_enqueue) }, 458 { "Rx DMA chan: pad_enqueue", CPDMA_RX_STAT(pad_enqueue) }, 459 { "Rx DMA chan: misqueued", CPDMA_RX_STAT(misqueued) }, 460 { "Rx DMA chan: desc_alloc_fail", CPDMA_RX_STAT(desc_alloc_fail) }, 461 { "Rx DMA chan: pad_alloc_fail", CPDMA_RX_STAT(pad_alloc_fail) }, 462 { "Rx DMA chan: runt_receive_buf", CPDMA_RX_STAT(runt_receive_buff) }, 463 { "Rx DMA chan: runt_transmit_buf", CPDMA_RX_STAT(runt_transmit_buff) }, 464 { "Rx DMA chan: empty_dequeue", CPDMA_RX_STAT(empty_dequeue) }, 465 { "Rx DMA chan: busy_dequeue", CPDMA_RX_STAT(busy_dequeue) }, 466 { "Rx DMA chan: good_dequeue", CPDMA_RX_STAT(good_dequeue) }, 467 { "Rx DMA chan: requeue", CPDMA_RX_STAT(requeue) }, 468 { "Rx DMA chan: teardown_dequeue", CPDMA_RX_STAT(teardown_dequeue) }, 469 { "Tx DMA chan: head_enqueue", CPDMA_TX_STAT(head_enqueue) }, 470 { "Tx DMA chan: tail_enqueue", CPDMA_TX_STAT(tail_enqueue) }, 471 { "Tx DMA chan: pad_enqueue", CPDMA_TX_STAT(pad_enqueue) }, 472 { "Tx DMA chan: misqueued", CPDMA_TX_STAT(misqueued) }, 473 { "Tx DMA chan: desc_alloc_fail", CPDMA_TX_STAT(desc_alloc_fail) }, 474 { "Tx DMA chan: pad_alloc_fail", CPDMA_TX_STAT(pad_alloc_fail) }, 475 { "Tx DMA chan: runt_receive_buf", CPDMA_TX_STAT(runt_receive_buff) }, 476 { "Tx DMA chan: runt_transmit_buf", CPDMA_TX_STAT(runt_transmit_buff) }, 477 { "Tx DMA chan: empty_dequeue", CPDMA_TX_STAT(empty_dequeue) }, 478 { "Tx DMA chan: busy_dequeue", CPDMA_TX_STAT(busy_dequeue) }, 479 { "Tx DMA chan: good_dequeue", CPDMA_TX_STAT(good_dequeue) }, 480 { "Tx DMA chan: requeue", CPDMA_TX_STAT(requeue) }, 481 { "Tx DMA chan: teardown_dequeue", CPDMA_TX_STAT(teardown_dequeue) }, 482 }; 483 484 #define CPSW_STATS_LEN ARRAY_SIZE(cpsw_gstrings_stats) 485 486 #define napi_to_priv(napi) container_of(napi, struct cpsw_priv, napi) 487 #define for_each_slave(priv, func, arg...) \ 488 do { \ 489 struct cpsw_slave *slave; \ 490 int n; \ 491 if (priv->data.dual_emac) \ 492 (func)((priv)->slaves + priv->emac_port, ##arg);\ 493 else \ 494 for (n = (priv)->data.slaves, \ 495 slave = (priv)->slaves; \ 496 n; n--) \ 497 (func)(slave++, ##arg); \ 498 } while (0) 499 #define cpsw_get_slave_ndev(priv, __slave_no__) \ 500 (priv->slaves[__slave_no__].ndev) 501 #define cpsw_get_slave_priv(priv, __slave_no__) \ 502 ((priv->slaves[__slave_no__].ndev) ? \ 503 netdev_priv(priv->slaves[__slave_no__].ndev) : NULL) \ 504 505 #define cpsw_dual_emac_src_port_detect(status, priv, ndev, skb) \ 506 do { \ 507 if (!priv->data.dual_emac) \ 508 break; \ 509 if (CPDMA_RX_SOURCE_PORT(status) == 1) { \ 510 ndev = cpsw_get_slave_ndev(priv, 0); \ 511 priv = netdev_priv(ndev); \ 512 skb->dev = ndev; \ 513 } else if (CPDMA_RX_SOURCE_PORT(status) == 2) { \ 514 ndev = cpsw_get_slave_ndev(priv, 1); \ 515 priv = netdev_priv(ndev); \ 516 skb->dev = ndev; \ 517 } \ 518 } while (0) 519 #define cpsw_add_mcast(priv, addr) \ 520 do { \ 521 if (priv->data.dual_emac) { \ 522 struct cpsw_slave *slave = priv->slaves + \ 523 priv->emac_port; \ 524 int slave_port = cpsw_get_slave_port(priv, \ 525 slave->slave_num); \ 526 cpsw_ale_add_mcast(priv->ale, addr, \ 527 1 << slave_port | 1 << priv->host_port, \ 528 ALE_VLAN, slave->port_vlan, 0); \ 529 } else { \ 530 cpsw_ale_add_mcast(priv->ale, addr, \ 531 ALE_ALL_PORTS << priv->host_port, \ 532 0, 0, 0); \ 533 } \ 534 } while (0) 535 536 static inline int cpsw_get_slave_port(struct cpsw_priv *priv, u32 slave_num) 537 { 538 if (priv->host_port == 0) 539 return slave_num + 1; 540 else 541 return slave_num; 542 } 543 544 static void cpsw_ndo_set_rx_mode(struct net_device *ndev) 545 { 546 struct cpsw_priv *priv = netdev_priv(ndev); 547 548 if (ndev->flags & IFF_PROMISC) { 549 /* Enable promiscuous mode */ 550 dev_err(priv->dev, "Ignoring Promiscuous mode\n"); 551 return; 552 } 553 554 /* Clear all mcast from ALE */ 555 cpsw_ale_flush_multicast(priv->ale, ALE_ALL_PORTS << priv->host_port); 556 557 if (!netdev_mc_empty(ndev)) { 558 struct netdev_hw_addr *ha; 559 560 /* program multicast address list into ALE register */ 561 netdev_for_each_mc_addr(ha, ndev) { 562 cpsw_add_mcast(priv, (u8 *)ha->addr); 563 } 564 } 565 } 566 567 static void cpsw_intr_enable(struct cpsw_priv *priv) 568 { 569 __raw_writel(0xFF, &priv->wr_regs->tx_en); 570 __raw_writel(0xFF, &priv->wr_regs->rx_en); 571 572 cpdma_ctlr_int_ctrl(priv->dma, true); 573 return; 574 } 575 576 static void cpsw_intr_disable(struct cpsw_priv *priv) 577 { 578 __raw_writel(0, &priv->wr_regs->tx_en); 579 __raw_writel(0, &priv->wr_regs->rx_en); 580 581 cpdma_ctlr_int_ctrl(priv->dma, false); 582 return; 583 } 584 585 void cpsw_tx_handler(void *token, int len, int status) 586 { 587 struct sk_buff *skb = token; 588 struct net_device *ndev = skb->dev; 589 struct cpsw_priv *priv = netdev_priv(ndev); 590 591 /* Check whether the queue is stopped due to stalled tx dma, if the 592 * queue is stopped then start the queue as we have free desc for tx 593 */ 594 if (unlikely(netif_queue_stopped(ndev))) 595 netif_wake_queue(ndev); 596 cpts_tx_timestamp(priv->cpts, skb); 597 priv->stats.tx_packets++; 598 priv->stats.tx_bytes += len; 599 dev_kfree_skb_any(skb); 600 } 601 602 void cpsw_rx_handler(void *token, int len, int status) 603 { 604 struct sk_buff *skb = token; 605 struct sk_buff *new_skb; 606 struct net_device *ndev = skb->dev; 607 struct cpsw_priv *priv = netdev_priv(ndev); 608 int ret = 0; 609 610 cpsw_dual_emac_src_port_detect(status, priv, ndev, skb); 611 612 if (unlikely(status < 0)) { 613 /* the interface is going down, skbs are purged */ 614 dev_kfree_skb_any(skb); 615 return; 616 } 617 618 new_skb = netdev_alloc_skb_ip_align(ndev, priv->rx_packet_max); 619 if (new_skb) { 620 skb_put(skb, len); 621 cpts_rx_timestamp(priv->cpts, skb); 622 skb->protocol = eth_type_trans(skb, ndev); 623 netif_receive_skb(skb); 624 priv->stats.rx_bytes += len; 625 priv->stats.rx_packets++; 626 } else { 627 priv->stats.rx_dropped++; 628 new_skb = skb; 629 } 630 631 ret = cpdma_chan_submit(priv->rxch, new_skb, new_skb->data, 632 skb_tailroom(new_skb), 0); 633 if (WARN_ON(ret < 0)) 634 dev_kfree_skb_any(new_skb); 635 } 636 637 static irqreturn_t cpsw_interrupt(int irq, void *dev_id) 638 { 639 struct cpsw_priv *priv = dev_id; 640 641 cpsw_intr_disable(priv); 642 if (priv->irq_enabled == true) { 643 cpsw_disable_irq(priv); 644 priv->irq_enabled = false; 645 } 646 647 if (netif_running(priv->ndev)) { 648 napi_schedule(&priv->napi); 649 return IRQ_HANDLED; 650 } 651 652 priv = cpsw_get_slave_priv(priv, 1); 653 if (!priv) 654 return IRQ_NONE; 655 656 if (netif_running(priv->ndev)) { 657 napi_schedule(&priv->napi); 658 return IRQ_HANDLED; 659 } 660 return IRQ_NONE; 661 } 662 663 static int cpsw_poll(struct napi_struct *napi, int budget) 664 { 665 struct cpsw_priv *priv = napi_to_priv(napi); 666 int num_tx, num_rx; 667 668 num_tx = cpdma_chan_process(priv->txch, 128); 669 if (num_tx) 670 cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_TX); 671 672 num_rx = cpdma_chan_process(priv->rxch, budget); 673 if (num_rx < budget) { 674 struct cpsw_priv *prim_cpsw; 675 676 napi_complete(napi); 677 cpsw_intr_enable(priv); 678 cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_RX); 679 prim_cpsw = cpsw_get_slave_priv(priv, 0); 680 if (prim_cpsw->irq_enabled == false) { 681 prim_cpsw->irq_enabled = true; 682 cpsw_enable_irq(priv); 683 } 684 } 685 686 if (num_rx || num_tx) 687 cpsw_dbg(priv, intr, "poll %d rx, %d tx pkts\n", 688 num_rx, num_tx); 689 690 return num_rx; 691 } 692 693 static inline void soft_reset(const char *module, void __iomem *reg) 694 { 695 unsigned long timeout = jiffies + HZ; 696 697 __raw_writel(1, reg); 698 do { 699 cpu_relax(); 700 } while ((__raw_readl(reg) & 1) && time_after(timeout, jiffies)); 701 702 WARN(__raw_readl(reg) & 1, "failed to soft-reset %s\n", module); 703 } 704 705 #define mac_hi(mac) (((mac)[0] << 0) | ((mac)[1] << 8) | \ 706 ((mac)[2] << 16) | ((mac)[3] << 24)) 707 #define mac_lo(mac) (((mac)[4] << 0) | ((mac)[5] << 8)) 708 709 static void cpsw_set_slave_mac(struct cpsw_slave *slave, 710 struct cpsw_priv *priv) 711 { 712 slave_write(slave, mac_hi(priv->mac_addr), SA_HI); 713 slave_write(slave, mac_lo(priv->mac_addr), SA_LO); 714 } 715 716 static void _cpsw_adjust_link(struct cpsw_slave *slave, 717 struct cpsw_priv *priv, bool *link) 718 { 719 struct phy_device *phy = slave->phy; 720 u32 mac_control = 0; 721 u32 slave_port; 722 723 if (!phy) 724 return; 725 726 slave_port = cpsw_get_slave_port(priv, slave->slave_num); 727 728 if (phy->link) { 729 mac_control = priv->data.mac_control; 730 731 /* enable forwarding */ 732 cpsw_ale_control_set(priv->ale, slave_port, 733 ALE_PORT_STATE, ALE_PORT_STATE_FORWARD); 734 735 if (phy->speed == 1000) 736 mac_control |= BIT(7); /* GIGABITEN */ 737 if (phy->duplex) 738 mac_control |= BIT(0); /* FULLDUPLEXEN */ 739 740 /* set speed_in input in case RMII mode is used in 100Mbps */ 741 if (phy->speed == 100) 742 mac_control |= BIT(15); 743 744 *link = true; 745 } else { 746 mac_control = 0; 747 /* disable forwarding */ 748 cpsw_ale_control_set(priv->ale, slave_port, 749 ALE_PORT_STATE, ALE_PORT_STATE_DISABLE); 750 } 751 752 if (mac_control != slave->mac_control) { 753 phy_print_status(phy); 754 __raw_writel(mac_control, &slave->sliver->mac_control); 755 } 756 757 slave->mac_control = mac_control; 758 } 759 760 static void cpsw_adjust_link(struct net_device *ndev) 761 { 762 struct cpsw_priv *priv = netdev_priv(ndev); 763 bool link = false; 764 765 for_each_slave(priv, _cpsw_adjust_link, priv, &link); 766 767 if (link) { 768 netif_carrier_on(ndev); 769 if (netif_running(ndev)) 770 netif_wake_queue(ndev); 771 } else { 772 netif_carrier_off(ndev); 773 netif_stop_queue(ndev); 774 } 775 } 776 777 static int cpsw_get_coalesce(struct net_device *ndev, 778 struct ethtool_coalesce *coal) 779 { 780 struct cpsw_priv *priv = netdev_priv(ndev); 781 782 coal->rx_coalesce_usecs = priv->coal_intvl; 783 return 0; 784 } 785 786 static int cpsw_set_coalesce(struct net_device *ndev, 787 struct ethtool_coalesce *coal) 788 { 789 struct cpsw_priv *priv = netdev_priv(ndev); 790 u32 int_ctrl; 791 u32 num_interrupts = 0; 792 u32 prescale = 0; 793 u32 addnl_dvdr = 1; 794 u32 coal_intvl = 0; 795 796 if (!coal->rx_coalesce_usecs) 797 return -EINVAL; 798 799 coal_intvl = coal->rx_coalesce_usecs; 800 801 int_ctrl = readl(&priv->wr_regs->int_control); 802 prescale = priv->bus_freq_mhz * 4; 803 804 if (coal_intvl < CPSW_CMINTMIN_INTVL) 805 coal_intvl = CPSW_CMINTMIN_INTVL; 806 807 if (coal_intvl > CPSW_CMINTMAX_INTVL) { 808 /* Interrupt pacer works with 4us Pulse, we can 809 * throttle further by dilating the 4us pulse. 810 */ 811 addnl_dvdr = CPSW_INTPRESCALE_MASK / prescale; 812 813 if (addnl_dvdr > 1) { 814 prescale *= addnl_dvdr; 815 if (coal_intvl > (CPSW_CMINTMAX_INTVL * addnl_dvdr)) 816 coal_intvl = (CPSW_CMINTMAX_INTVL 817 * addnl_dvdr); 818 } else { 819 addnl_dvdr = 1; 820 coal_intvl = CPSW_CMINTMAX_INTVL; 821 } 822 } 823 824 num_interrupts = (1000 * addnl_dvdr) / coal_intvl; 825 writel(num_interrupts, &priv->wr_regs->rx_imax); 826 writel(num_interrupts, &priv->wr_regs->tx_imax); 827 828 int_ctrl |= CPSW_INTPACEEN; 829 int_ctrl &= (~CPSW_INTPRESCALE_MASK); 830 int_ctrl |= (prescale & CPSW_INTPRESCALE_MASK); 831 writel(int_ctrl, &priv->wr_regs->int_control); 832 833 cpsw_notice(priv, timer, "Set coalesce to %d usecs.\n", coal_intvl); 834 if (priv->data.dual_emac) { 835 int i; 836 837 for (i = 0; i < priv->data.slaves; i++) { 838 priv = netdev_priv(priv->slaves[i].ndev); 839 priv->coal_intvl = coal_intvl; 840 } 841 } else { 842 priv->coal_intvl = coal_intvl; 843 } 844 845 return 0; 846 } 847 848 static int cpsw_get_sset_count(struct net_device *ndev, int sset) 849 { 850 switch (sset) { 851 case ETH_SS_STATS: 852 return CPSW_STATS_LEN; 853 default: 854 return -EOPNOTSUPP; 855 } 856 } 857 858 static void cpsw_get_strings(struct net_device *ndev, u32 stringset, u8 *data) 859 { 860 u8 *p = data; 861 int i; 862 863 switch (stringset) { 864 case ETH_SS_STATS: 865 for (i = 0; i < CPSW_STATS_LEN; i++) { 866 memcpy(p, cpsw_gstrings_stats[i].stat_string, 867 ETH_GSTRING_LEN); 868 p += ETH_GSTRING_LEN; 869 } 870 break; 871 } 872 } 873 874 static void cpsw_get_ethtool_stats(struct net_device *ndev, 875 struct ethtool_stats *stats, u64 *data) 876 { 877 struct cpsw_priv *priv = netdev_priv(ndev); 878 struct cpdma_chan_stats rx_stats; 879 struct cpdma_chan_stats tx_stats; 880 u32 val; 881 u8 *p; 882 int i; 883 884 /* Collect Davinci CPDMA stats for Rx and Tx Channel */ 885 cpdma_chan_get_stats(priv->rxch, &rx_stats); 886 cpdma_chan_get_stats(priv->txch, &tx_stats); 887 888 for (i = 0; i < CPSW_STATS_LEN; i++) { 889 switch (cpsw_gstrings_stats[i].type) { 890 case CPSW_STATS: 891 val = readl(priv->hw_stats + 892 cpsw_gstrings_stats[i].stat_offset); 893 data[i] = val; 894 break; 895 896 case CPDMA_RX_STATS: 897 p = (u8 *)&rx_stats + 898 cpsw_gstrings_stats[i].stat_offset; 899 data[i] = *(u32 *)p; 900 break; 901 902 case CPDMA_TX_STATS: 903 p = (u8 *)&tx_stats + 904 cpsw_gstrings_stats[i].stat_offset; 905 data[i] = *(u32 *)p; 906 break; 907 } 908 } 909 } 910 911 static inline int __show_stat(char *buf, int maxlen, const char *name, u32 val) 912 { 913 static char *leader = "........................................"; 914 915 if (!val) 916 return 0; 917 else 918 return snprintf(buf, maxlen, "%s %s %10d\n", name, 919 leader + strlen(name), val); 920 } 921 922 static int cpsw_common_res_usage_state(struct cpsw_priv *priv) 923 { 924 u32 i; 925 u32 usage_count = 0; 926 927 if (!priv->data.dual_emac) 928 return 0; 929 930 for (i = 0; i < priv->data.slaves; i++) 931 if (priv->slaves[i].open_stat) 932 usage_count++; 933 934 return usage_count; 935 } 936 937 static inline int cpsw_tx_packet_submit(struct net_device *ndev, 938 struct cpsw_priv *priv, struct sk_buff *skb) 939 { 940 if (!priv->data.dual_emac) 941 return cpdma_chan_submit(priv->txch, skb, skb->data, 942 skb->len, 0); 943 944 if (ndev == cpsw_get_slave_ndev(priv, 0)) 945 return cpdma_chan_submit(priv->txch, skb, skb->data, 946 skb->len, 1); 947 else 948 return cpdma_chan_submit(priv->txch, skb, skb->data, 949 skb->len, 2); 950 } 951 952 static inline void cpsw_add_dual_emac_def_ale_entries( 953 struct cpsw_priv *priv, struct cpsw_slave *slave, 954 u32 slave_port) 955 { 956 u32 port_mask = 1 << slave_port | 1 << priv->host_port; 957 958 if (priv->version == CPSW_VERSION_1) 959 slave_write(slave, slave->port_vlan, CPSW1_PORT_VLAN); 960 else 961 slave_write(slave, slave->port_vlan, CPSW2_PORT_VLAN); 962 cpsw_ale_add_vlan(priv->ale, slave->port_vlan, port_mask, 963 port_mask, port_mask, 0); 964 cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast, 965 port_mask, ALE_VLAN, slave->port_vlan, 0); 966 cpsw_ale_add_ucast(priv->ale, priv->mac_addr, 967 priv->host_port, ALE_VLAN, slave->port_vlan); 968 } 969 970 static void soft_reset_slave(struct cpsw_slave *slave) 971 { 972 char name[32]; 973 974 snprintf(name, sizeof(name), "slave-%d", slave->slave_num); 975 soft_reset(name, &slave->sliver->soft_reset); 976 } 977 978 static void cpsw_slave_open(struct cpsw_slave *slave, struct cpsw_priv *priv) 979 { 980 u32 slave_port; 981 982 soft_reset_slave(slave); 983 984 /* setup priority mapping */ 985 __raw_writel(RX_PRIORITY_MAPPING, &slave->sliver->rx_pri_map); 986 987 switch (priv->version) { 988 case CPSW_VERSION_1: 989 slave_write(slave, TX_PRIORITY_MAPPING, CPSW1_TX_PRI_MAP); 990 break; 991 case CPSW_VERSION_2: 992 case CPSW_VERSION_3: 993 case CPSW_VERSION_4: 994 slave_write(slave, TX_PRIORITY_MAPPING, CPSW2_TX_PRI_MAP); 995 break; 996 } 997 998 /* setup max packet size, and mac address */ 999 __raw_writel(priv->rx_packet_max, &slave->sliver->rx_maxlen); 1000 cpsw_set_slave_mac(slave, priv); 1001 1002 slave->mac_control = 0; /* no link yet */ 1003 1004 slave_port = cpsw_get_slave_port(priv, slave->slave_num); 1005 1006 if (priv->data.dual_emac) 1007 cpsw_add_dual_emac_def_ale_entries(priv, slave, slave_port); 1008 else 1009 cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast, 1010 1 << slave_port, 0, 0, ALE_MCAST_FWD_2); 1011 1012 slave->phy = phy_connect(priv->ndev, slave->data->phy_id, 1013 &cpsw_adjust_link, slave->data->phy_if); 1014 if (IS_ERR(slave->phy)) { 1015 dev_err(priv->dev, "phy %s not found on slave %d\n", 1016 slave->data->phy_id, slave->slave_num); 1017 slave->phy = NULL; 1018 } else { 1019 dev_info(priv->dev, "phy found : id is : 0x%x\n", 1020 slave->phy->phy_id); 1021 phy_start(slave->phy); 1022 1023 /* Configure GMII_SEL register */ 1024 cpsw_phy_sel(&priv->pdev->dev, slave->phy->interface, 1025 slave->slave_num); 1026 } 1027 } 1028 1029 static inline void cpsw_add_default_vlan(struct cpsw_priv *priv) 1030 { 1031 const int vlan = priv->data.default_vlan; 1032 const int port = priv->host_port; 1033 u32 reg; 1034 int i; 1035 1036 reg = (priv->version == CPSW_VERSION_1) ? CPSW1_PORT_VLAN : 1037 CPSW2_PORT_VLAN; 1038 1039 writel(vlan, &priv->host_port_regs->port_vlan); 1040 1041 for (i = 0; i < priv->data.slaves; i++) 1042 slave_write(priv->slaves + i, vlan, reg); 1043 1044 cpsw_ale_add_vlan(priv->ale, vlan, ALE_ALL_PORTS << port, 1045 ALE_ALL_PORTS << port, ALE_ALL_PORTS << port, 1046 (ALE_PORT_1 | ALE_PORT_2) << port); 1047 } 1048 1049 static void cpsw_init_host_port(struct cpsw_priv *priv) 1050 { 1051 u32 control_reg; 1052 u32 fifo_mode; 1053 1054 /* soft reset the controller and initialize ale */ 1055 soft_reset("cpsw", &priv->regs->soft_reset); 1056 cpsw_ale_start(priv->ale); 1057 1058 /* switch to vlan unaware mode */ 1059 cpsw_ale_control_set(priv->ale, priv->host_port, ALE_VLAN_AWARE, 1060 CPSW_ALE_VLAN_AWARE); 1061 control_reg = readl(&priv->regs->control); 1062 control_reg |= CPSW_VLAN_AWARE; 1063 writel(control_reg, &priv->regs->control); 1064 fifo_mode = (priv->data.dual_emac) ? CPSW_FIFO_DUAL_MAC_MODE : 1065 CPSW_FIFO_NORMAL_MODE; 1066 writel(fifo_mode, &priv->host_port_regs->tx_in_ctl); 1067 1068 /* setup host port priority mapping */ 1069 __raw_writel(CPDMA_TX_PRIORITY_MAP, 1070 &priv->host_port_regs->cpdma_tx_pri_map); 1071 __raw_writel(0, &priv->host_port_regs->cpdma_rx_chan_map); 1072 1073 cpsw_ale_control_set(priv->ale, priv->host_port, 1074 ALE_PORT_STATE, ALE_PORT_STATE_FORWARD); 1075 1076 if (!priv->data.dual_emac) { 1077 cpsw_ale_add_ucast(priv->ale, priv->mac_addr, priv->host_port, 1078 0, 0); 1079 cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast, 1080 1 << priv->host_port, 0, 0, ALE_MCAST_FWD_2); 1081 } 1082 } 1083 1084 static void cpsw_slave_stop(struct cpsw_slave *slave, struct cpsw_priv *priv) 1085 { 1086 if (!slave->phy) 1087 return; 1088 phy_stop(slave->phy); 1089 phy_disconnect(slave->phy); 1090 slave->phy = NULL; 1091 } 1092 1093 static int cpsw_ndo_open(struct net_device *ndev) 1094 { 1095 struct cpsw_priv *priv = netdev_priv(ndev); 1096 struct cpsw_priv *prim_cpsw; 1097 int i, ret; 1098 u32 reg; 1099 1100 if (!cpsw_common_res_usage_state(priv)) 1101 cpsw_intr_disable(priv); 1102 netif_carrier_off(ndev); 1103 1104 pm_runtime_get_sync(&priv->pdev->dev); 1105 1106 reg = priv->version; 1107 1108 dev_info(priv->dev, "initializing cpsw version %d.%d (%d)\n", 1109 CPSW_MAJOR_VERSION(reg), CPSW_MINOR_VERSION(reg), 1110 CPSW_RTL_VERSION(reg)); 1111 1112 /* initialize host and slave ports */ 1113 if (!cpsw_common_res_usage_state(priv)) 1114 cpsw_init_host_port(priv); 1115 for_each_slave(priv, cpsw_slave_open, priv); 1116 1117 /* Add default VLAN */ 1118 if (!priv->data.dual_emac) 1119 cpsw_add_default_vlan(priv); 1120 1121 if (!cpsw_common_res_usage_state(priv)) { 1122 /* setup tx dma to fixed prio and zero offset */ 1123 cpdma_control_set(priv->dma, CPDMA_TX_PRIO_FIXED, 1); 1124 cpdma_control_set(priv->dma, CPDMA_RX_BUFFER_OFFSET, 0); 1125 1126 /* disable priority elevation */ 1127 __raw_writel(0, &priv->regs->ptype); 1128 1129 /* enable statistics collection only on all ports */ 1130 __raw_writel(0x7, &priv->regs->stat_port_en); 1131 1132 if (WARN_ON(!priv->data.rx_descs)) 1133 priv->data.rx_descs = 128; 1134 1135 for (i = 0; i < priv->data.rx_descs; i++) { 1136 struct sk_buff *skb; 1137 1138 ret = -ENOMEM; 1139 skb = __netdev_alloc_skb_ip_align(priv->ndev, 1140 priv->rx_packet_max, GFP_KERNEL); 1141 if (!skb) 1142 goto err_cleanup; 1143 ret = cpdma_chan_submit(priv->rxch, skb, skb->data, 1144 skb_tailroom(skb), 0); 1145 if (ret < 0) { 1146 kfree_skb(skb); 1147 goto err_cleanup; 1148 } 1149 } 1150 /* continue even if we didn't manage to submit all 1151 * receive descs 1152 */ 1153 cpsw_info(priv, ifup, "submitted %d rx descriptors\n", i); 1154 } 1155 1156 /* Enable Interrupt pacing if configured */ 1157 if (priv->coal_intvl != 0) { 1158 struct ethtool_coalesce coal; 1159 1160 coal.rx_coalesce_usecs = (priv->coal_intvl << 4); 1161 cpsw_set_coalesce(ndev, &coal); 1162 } 1163 1164 prim_cpsw = cpsw_get_slave_priv(priv, 0); 1165 if (prim_cpsw->irq_enabled == false) { 1166 if ((priv == prim_cpsw) || !netif_running(prim_cpsw->ndev)) { 1167 prim_cpsw->irq_enabled = true; 1168 cpsw_enable_irq(prim_cpsw); 1169 } 1170 } 1171 1172 napi_enable(&priv->napi); 1173 cpdma_ctlr_start(priv->dma); 1174 cpsw_intr_enable(priv); 1175 cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_RX); 1176 cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_TX); 1177 1178 if (priv->data.dual_emac) 1179 priv->slaves[priv->emac_port].open_stat = true; 1180 return 0; 1181 1182 err_cleanup: 1183 cpdma_ctlr_stop(priv->dma); 1184 for_each_slave(priv, cpsw_slave_stop, priv); 1185 pm_runtime_put_sync(&priv->pdev->dev); 1186 netif_carrier_off(priv->ndev); 1187 return ret; 1188 } 1189 1190 static int cpsw_ndo_stop(struct net_device *ndev) 1191 { 1192 struct cpsw_priv *priv = netdev_priv(ndev); 1193 1194 cpsw_info(priv, ifdown, "shutting down cpsw device\n"); 1195 netif_stop_queue(priv->ndev); 1196 napi_disable(&priv->napi); 1197 netif_carrier_off(priv->ndev); 1198 1199 if (cpsw_common_res_usage_state(priv) <= 1) { 1200 cpsw_intr_disable(priv); 1201 cpdma_ctlr_int_ctrl(priv->dma, false); 1202 cpdma_ctlr_stop(priv->dma); 1203 cpsw_ale_stop(priv->ale); 1204 } 1205 for_each_slave(priv, cpsw_slave_stop, priv); 1206 pm_runtime_put_sync(&priv->pdev->dev); 1207 if (priv->data.dual_emac) 1208 priv->slaves[priv->emac_port].open_stat = false; 1209 return 0; 1210 } 1211 1212 static netdev_tx_t cpsw_ndo_start_xmit(struct sk_buff *skb, 1213 struct net_device *ndev) 1214 { 1215 struct cpsw_priv *priv = netdev_priv(ndev); 1216 int ret; 1217 1218 ndev->trans_start = jiffies; 1219 1220 if (skb_padto(skb, CPSW_MIN_PACKET_SIZE)) { 1221 cpsw_err(priv, tx_err, "packet pad failed\n"); 1222 priv->stats.tx_dropped++; 1223 return NETDEV_TX_OK; 1224 } 1225 1226 if (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP && 1227 priv->cpts->tx_enable) 1228 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 1229 1230 skb_tx_timestamp(skb); 1231 1232 ret = cpsw_tx_packet_submit(ndev, priv, skb); 1233 if (unlikely(ret != 0)) { 1234 cpsw_err(priv, tx_err, "desc submit failed\n"); 1235 goto fail; 1236 } 1237 1238 /* If there is no more tx desc left free then we need to 1239 * tell the kernel to stop sending us tx frames. 1240 */ 1241 if (unlikely(!cpdma_check_free_tx_desc(priv->txch))) 1242 netif_stop_queue(ndev); 1243 1244 return NETDEV_TX_OK; 1245 fail: 1246 priv->stats.tx_dropped++; 1247 netif_stop_queue(ndev); 1248 return NETDEV_TX_BUSY; 1249 } 1250 1251 static void cpsw_ndo_change_rx_flags(struct net_device *ndev, int flags) 1252 { 1253 /* 1254 * The switch cannot operate in promiscuous mode without substantial 1255 * headache. For promiscuous mode to work, we would need to put the 1256 * ALE in bypass mode and route all traffic to the host port. 1257 * Subsequently, the host will need to operate as a "bridge", learn, 1258 * and flood as needed. For now, we simply complain here and 1259 * do nothing about it :-) 1260 */ 1261 if ((flags & IFF_PROMISC) && (ndev->flags & IFF_PROMISC)) 1262 dev_err(&ndev->dev, "promiscuity ignored!\n"); 1263 1264 /* 1265 * The switch cannot filter multicast traffic unless it is configured 1266 * in "VLAN Aware" mode. Unfortunately, VLAN awareness requires a 1267 * whole bunch of additional logic that this driver does not implement 1268 * at present. 1269 */ 1270 if ((flags & IFF_ALLMULTI) && !(ndev->flags & IFF_ALLMULTI)) 1271 dev_err(&ndev->dev, "multicast traffic cannot be filtered!\n"); 1272 } 1273 1274 #ifdef CONFIG_TI_CPTS 1275 1276 static void cpsw_hwtstamp_v1(struct cpsw_priv *priv) 1277 { 1278 struct cpsw_slave *slave = &priv->slaves[priv->data.active_slave]; 1279 u32 ts_en, seq_id; 1280 1281 if (!priv->cpts->tx_enable && !priv->cpts->rx_enable) { 1282 slave_write(slave, 0, CPSW1_TS_CTL); 1283 return; 1284 } 1285 1286 seq_id = (30 << CPSW_V1_SEQ_ID_OFS_SHIFT) | ETH_P_1588; 1287 ts_en = EVENT_MSG_BITS << CPSW_V1_MSG_TYPE_OFS; 1288 1289 if (priv->cpts->tx_enable) 1290 ts_en |= CPSW_V1_TS_TX_EN; 1291 1292 if (priv->cpts->rx_enable) 1293 ts_en |= CPSW_V1_TS_RX_EN; 1294 1295 slave_write(slave, ts_en, CPSW1_TS_CTL); 1296 slave_write(slave, seq_id, CPSW1_TS_SEQ_LTYPE); 1297 } 1298 1299 static void cpsw_hwtstamp_v2(struct cpsw_priv *priv) 1300 { 1301 struct cpsw_slave *slave; 1302 u32 ctrl, mtype; 1303 1304 if (priv->data.dual_emac) 1305 slave = &priv->slaves[priv->emac_port]; 1306 else 1307 slave = &priv->slaves[priv->data.active_slave]; 1308 1309 ctrl = slave_read(slave, CPSW2_CONTROL); 1310 ctrl &= ~CTRL_ALL_TS_MASK; 1311 1312 if (priv->cpts->tx_enable) 1313 ctrl |= CTRL_TX_TS_BITS; 1314 1315 if (priv->cpts->rx_enable) 1316 ctrl |= CTRL_RX_TS_BITS; 1317 1318 mtype = (30 << TS_SEQ_ID_OFFSET_SHIFT) | EVENT_MSG_BITS; 1319 1320 slave_write(slave, mtype, CPSW2_TS_SEQ_MTYPE); 1321 slave_write(slave, ctrl, CPSW2_CONTROL); 1322 __raw_writel(ETH_P_1588, &priv->regs->ts_ltype); 1323 } 1324 1325 static int cpsw_hwtstamp_ioctl(struct net_device *dev, struct ifreq *ifr) 1326 { 1327 struct cpsw_priv *priv = netdev_priv(dev); 1328 struct cpts *cpts = priv->cpts; 1329 struct hwtstamp_config cfg; 1330 1331 if (priv->version != CPSW_VERSION_1 && 1332 priv->version != CPSW_VERSION_2) 1333 return -EOPNOTSUPP; 1334 1335 if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg))) 1336 return -EFAULT; 1337 1338 /* reserved for future extensions */ 1339 if (cfg.flags) 1340 return -EINVAL; 1341 1342 if (cfg.tx_type != HWTSTAMP_TX_OFF && cfg.tx_type != HWTSTAMP_TX_ON) 1343 return -ERANGE; 1344 1345 switch (cfg.rx_filter) { 1346 case HWTSTAMP_FILTER_NONE: 1347 cpts->rx_enable = 0; 1348 break; 1349 case HWTSTAMP_FILTER_ALL: 1350 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: 1351 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: 1352 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: 1353 return -ERANGE; 1354 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: 1355 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 1356 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 1357 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: 1358 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: 1359 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: 1360 case HWTSTAMP_FILTER_PTP_V2_EVENT: 1361 case HWTSTAMP_FILTER_PTP_V2_SYNC: 1362 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 1363 cpts->rx_enable = 1; 1364 cfg.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT; 1365 break; 1366 default: 1367 return -ERANGE; 1368 } 1369 1370 cpts->tx_enable = cfg.tx_type == HWTSTAMP_TX_ON; 1371 1372 switch (priv->version) { 1373 case CPSW_VERSION_1: 1374 cpsw_hwtstamp_v1(priv); 1375 break; 1376 case CPSW_VERSION_2: 1377 cpsw_hwtstamp_v2(priv); 1378 break; 1379 default: 1380 WARN_ON(1); 1381 } 1382 1383 return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0; 1384 } 1385 1386 #endif /*CONFIG_TI_CPTS*/ 1387 1388 static int cpsw_ndo_ioctl(struct net_device *dev, struct ifreq *req, int cmd) 1389 { 1390 struct cpsw_priv *priv = netdev_priv(dev); 1391 struct mii_ioctl_data *data = if_mii(req); 1392 int slave_no = cpsw_slave_index(priv); 1393 1394 if (!netif_running(dev)) 1395 return -EINVAL; 1396 1397 switch (cmd) { 1398 #ifdef CONFIG_TI_CPTS 1399 case SIOCSHWTSTAMP: 1400 return cpsw_hwtstamp_ioctl(dev, req); 1401 #endif 1402 case SIOCGMIIPHY: 1403 data->phy_id = priv->slaves[slave_no].phy->addr; 1404 break; 1405 default: 1406 return -ENOTSUPP; 1407 } 1408 1409 return 0; 1410 } 1411 1412 static void cpsw_ndo_tx_timeout(struct net_device *ndev) 1413 { 1414 struct cpsw_priv *priv = netdev_priv(ndev); 1415 1416 cpsw_err(priv, tx_err, "transmit timeout, restarting dma\n"); 1417 priv->stats.tx_errors++; 1418 cpsw_intr_disable(priv); 1419 cpdma_ctlr_int_ctrl(priv->dma, false); 1420 cpdma_chan_stop(priv->txch); 1421 cpdma_chan_start(priv->txch); 1422 cpdma_ctlr_int_ctrl(priv->dma, true); 1423 cpsw_intr_enable(priv); 1424 cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_RX); 1425 cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_TX); 1426 1427 } 1428 1429 static int cpsw_ndo_set_mac_address(struct net_device *ndev, void *p) 1430 { 1431 struct cpsw_priv *priv = netdev_priv(ndev); 1432 struct sockaddr *addr = (struct sockaddr *)p; 1433 int flags = 0; 1434 u16 vid = 0; 1435 1436 if (!is_valid_ether_addr(addr->sa_data)) 1437 return -EADDRNOTAVAIL; 1438 1439 if (priv->data.dual_emac) { 1440 vid = priv->slaves[priv->emac_port].port_vlan; 1441 flags = ALE_VLAN; 1442 } 1443 1444 cpsw_ale_del_ucast(priv->ale, priv->mac_addr, priv->host_port, 1445 flags, vid); 1446 cpsw_ale_add_ucast(priv->ale, addr->sa_data, priv->host_port, 1447 flags, vid); 1448 1449 memcpy(priv->mac_addr, addr->sa_data, ETH_ALEN); 1450 memcpy(ndev->dev_addr, priv->mac_addr, ETH_ALEN); 1451 for_each_slave(priv, cpsw_set_slave_mac, priv); 1452 1453 return 0; 1454 } 1455 1456 static struct net_device_stats *cpsw_ndo_get_stats(struct net_device *ndev) 1457 { 1458 struct cpsw_priv *priv = netdev_priv(ndev); 1459 return &priv->stats; 1460 } 1461 1462 #ifdef CONFIG_NET_POLL_CONTROLLER 1463 static void cpsw_ndo_poll_controller(struct net_device *ndev) 1464 { 1465 struct cpsw_priv *priv = netdev_priv(ndev); 1466 1467 cpsw_intr_disable(priv); 1468 cpdma_ctlr_int_ctrl(priv->dma, false); 1469 cpsw_interrupt(ndev->irq, priv); 1470 cpdma_ctlr_int_ctrl(priv->dma, true); 1471 cpsw_intr_enable(priv); 1472 cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_RX); 1473 cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_TX); 1474 1475 } 1476 #endif 1477 1478 static inline int cpsw_add_vlan_ale_entry(struct cpsw_priv *priv, 1479 unsigned short vid) 1480 { 1481 int ret; 1482 1483 ret = cpsw_ale_add_vlan(priv->ale, vid, 1484 ALE_ALL_PORTS << priv->host_port, 1485 0, ALE_ALL_PORTS << priv->host_port, 1486 (ALE_PORT_1 | ALE_PORT_2) << priv->host_port); 1487 if (ret != 0) 1488 return ret; 1489 1490 ret = cpsw_ale_add_ucast(priv->ale, priv->mac_addr, 1491 priv->host_port, ALE_VLAN, vid); 1492 if (ret != 0) 1493 goto clean_vid; 1494 1495 ret = cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast, 1496 ALE_ALL_PORTS << priv->host_port, 1497 ALE_VLAN, vid, 0); 1498 if (ret != 0) 1499 goto clean_vlan_ucast; 1500 return 0; 1501 1502 clean_vlan_ucast: 1503 cpsw_ale_del_ucast(priv->ale, priv->mac_addr, 1504 priv->host_port, ALE_VLAN, vid); 1505 clean_vid: 1506 cpsw_ale_del_vlan(priv->ale, vid, 0); 1507 return ret; 1508 } 1509 1510 static int cpsw_ndo_vlan_rx_add_vid(struct net_device *ndev, 1511 __be16 proto, u16 vid) 1512 { 1513 struct cpsw_priv *priv = netdev_priv(ndev); 1514 1515 if (vid == priv->data.default_vlan) 1516 return 0; 1517 1518 dev_info(priv->dev, "Adding vlanid %d to vlan filter\n", vid); 1519 return cpsw_add_vlan_ale_entry(priv, vid); 1520 } 1521 1522 static int cpsw_ndo_vlan_rx_kill_vid(struct net_device *ndev, 1523 __be16 proto, u16 vid) 1524 { 1525 struct cpsw_priv *priv = netdev_priv(ndev); 1526 int ret; 1527 1528 if (vid == priv->data.default_vlan) 1529 return 0; 1530 1531 dev_info(priv->dev, "removing vlanid %d from vlan filter\n", vid); 1532 ret = cpsw_ale_del_vlan(priv->ale, vid, 0); 1533 if (ret != 0) 1534 return ret; 1535 1536 ret = cpsw_ale_del_ucast(priv->ale, priv->mac_addr, 1537 priv->host_port, ALE_VLAN, vid); 1538 if (ret != 0) 1539 return ret; 1540 1541 return cpsw_ale_del_mcast(priv->ale, priv->ndev->broadcast, 1542 0, ALE_VLAN, vid); 1543 } 1544 1545 static const struct net_device_ops cpsw_netdev_ops = { 1546 .ndo_open = cpsw_ndo_open, 1547 .ndo_stop = cpsw_ndo_stop, 1548 .ndo_start_xmit = cpsw_ndo_start_xmit, 1549 .ndo_change_rx_flags = cpsw_ndo_change_rx_flags, 1550 .ndo_set_mac_address = cpsw_ndo_set_mac_address, 1551 .ndo_do_ioctl = cpsw_ndo_ioctl, 1552 .ndo_validate_addr = eth_validate_addr, 1553 .ndo_change_mtu = eth_change_mtu, 1554 .ndo_tx_timeout = cpsw_ndo_tx_timeout, 1555 .ndo_get_stats = cpsw_ndo_get_stats, 1556 .ndo_set_rx_mode = cpsw_ndo_set_rx_mode, 1557 #ifdef CONFIG_NET_POLL_CONTROLLER 1558 .ndo_poll_controller = cpsw_ndo_poll_controller, 1559 #endif 1560 .ndo_vlan_rx_add_vid = cpsw_ndo_vlan_rx_add_vid, 1561 .ndo_vlan_rx_kill_vid = cpsw_ndo_vlan_rx_kill_vid, 1562 }; 1563 1564 static void cpsw_get_drvinfo(struct net_device *ndev, 1565 struct ethtool_drvinfo *info) 1566 { 1567 struct cpsw_priv *priv = netdev_priv(ndev); 1568 1569 strlcpy(info->driver, "TI CPSW Driver v1.0", sizeof(info->driver)); 1570 strlcpy(info->version, "1.0", sizeof(info->version)); 1571 strlcpy(info->bus_info, priv->pdev->name, sizeof(info->bus_info)); 1572 } 1573 1574 static u32 cpsw_get_msglevel(struct net_device *ndev) 1575 { 1576 struct cpsw_priv *priv = netdev_priv(ndev); 1577 return priv->msg_enable; 1578 } 1579 1580 static void cpsw_set_msglevel(struct net_device *ndev, u32 value) 1581 { 1582 struct cpsw_priv *priv = netdev_priv(ndev); 1583 priv->msg_enable = value; 1584 } 1585 1586 static int cpsw_get_ts_info(struct net_device *ndev, 1587 struct ethtool_ts_info *info) 1588 { 1589 #ifdef CONFIG_TI_CPTS 1590 struct cpsw_priv *priv = netdev_priv(ndev); 1591 1592 info->so_timestamping = 1593 SOF_TIMESTAMPING_TX_HARDWARE | 1594 SOF_TIMESTAMPING_TX_SOFTWARE | 1595 SOF_TIMESTAMPING_RX_HARDWARE | 1596 SOF_TIMESTAMPING_RX_SOFTWARE | 1597 SOF_TIMESTAMPING_SOFTWARE | 1598 SOF_TIMESTAMPING_RAW_HARDWARE; 1599 info->phc_index = priv->cpts->phc_index; 1600 info->tx_types = 1601 (1 << HWTSTAMP_TX_OFF) | 1602 (1 << HWTSTAMP_TX_ON); 1603 info->rx_filters = 1604 (1 << HWTSTAMP_FILTER_NONE) | 1605 (1 << HWTSTAMP_FILTER_PTP_V2_EVENT); 1606 #else 1607 info->so_timestamping = 1608 SOF_TIMESTAMPING_TX_SOFTWARE | 1609 SOF_TIMESTAMPING_RX_SOFTWARE | 1610 SOF_TIMESTAMPING_SOFTWARE; 1611 info->phc_index = -1; 1612 info->tx_types = 0; 1613 info->rx_filters = 0; 1614 #endif 1615 return 0; 1616 } 1617 1618 static int cpsw_get_settings(struct net_device *ndev, 1619 struct ethtool_cmd *ecmd) 1620 { 1621 struct cpsw_priv *priv = netdev_priv(ndev); 1622 int slave_no = cpsw_slave_index(priv); 1623 1624 if (priv->slaves[slave_no].phy) 1625 return phy_ethtool_gset(priv->slaves[slave_no].phy, ecmd); 1626 else 1627 return -EOPNOTSUPP; 1628 } 1629 1630 static int cpsw_set_settings(struct net_device *ndev, struct ethtool_cmd *ecmd) 1631 { 1632 struct cpsw_priv *priv = netdev_priv(ndev); 1633 int slave_no = cpsw_slave_index(priv); 1634 1635 if (priv->slaves[slave_no].phy) 1636 return phy_ethtool_sset(priv->slaves[slave_no].phy, ecmd); 1637 else 1638 return -EOPNOTSUPP; 1639 } 1640 1641 static void cpsw_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol) 1642 { 1643 struct cpsw_priv *priv = netdev_priv(ndev); 1644 int slave_no = cpsw_slave_index(priv); 1645 1646 wol->supported = 0; 1647 wol->wolopts = 0; 1648 1649 if (priv->slaves[slave_no].phy) 1650 phy_ethtool_get_wol(priv->slaves[slave_no].phy, wol); 1651 } 1652 1653 static int cpsw_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol) 1654 { 1655 struct cpsw_priv *priv = netdev_priv(ndev); 1656 int slave_no = cpsw_slave_index(priv); 1657 1658 if (priv->slaves[slave_no].phy) 1659 return phy_ethtool_set_wol(priv->slaves[slave_no].phy, wol); 1660 else 1661 return -EOPNOTSUPP; 1662 } 1663 1664 static const struct ethtool_ops cpsw_ethtool_ops = { 1665 .get_drvinfo = cpsw_get_drvinfo, 1666 .get_msglevel = cpsw_get_msglevel, 1667 .set_msglevel = cpsw_set_msglevel, 1668 .get_link = ethtool_op_get_link, 1669 .get_ts_info = cpsw_get_ts_info, 1670 .get_settings = cpsw_get_settings, 1671 .set_settings = cpsw_set_settings, 1672 .get_coalesce = cpsw_get_coalesce, 1673 .set_coalesce = cpsw_set_coalesce, 1674 .get_sset_count = cpsw_get_sset_count, 1675 .get_strings = cpsw_get_strings, 1676 .get_ethtool_stats = cpsw_get_ethtool_stats, 1677 .get_wol = cpsw_get_wol, 1678 .set_wol = cpsw_set_wol, 1679 }; 1680 1681 static void cpsw_slave_init(struct cpsw_slave *slave, struct cpsw_priv *priv, 1682 u32 slave_reg_ofs, u32 sliver_reg_ofs) 1683 { 1684 void __iomem *regs = priv->regs; 1685 int slave_num = slave->slave_num; 1686 struct cpsw_slave_data *data = priv->data.slave_data + slave_num; 1687 1688 slave->data = data; 1689 slave->regs = regs + slave_reg_ofs; 1690 slave->sliver = regs + sliver_reg_ofs; 1691 slave->port_vlan = data->dual_emac_res_vlan; 1692 } 1693 1694 static int cpsw_probe_dt(struct cpsw_platform_data *data, 1695 struct platform_device *pdev) 1696 { 1697 struct device_node *node = pdev->dev.of_node; 1698 struct device_node *slave_node; 1699 int i = 0, ret; 1700 u32 prop; 1701 1702 if (!node) 1703 return -EINVAL; 1704 1705 if (of_property_read_u32(node, "slaves", &prop)) { 1706 pr_err("Missing slaves property in the DT.\n"); 1707 return -EINVAL; 1708 } 1709 data->slaves = prop; 1710 1711 if (of_property_read_u32(node, "active_slave", &prop)) { 1712 pr_err("Missing active_slave property in the DT.\n"); 1713 return -EINVAL; 1714 } 1715 data->active_slave = prop; 1716 1717 if (of_property_read_u32(node, "cpts_clock_mult", &prop)) { 1718 pr_err("Missing cpts_clock_mult property in the DT.\n"); 1719 return -EINVAL; 1720 } 1721 data->cpts_clock_mult = prop; 1722 1723 if (of_property_read_u32(node, "cpts_clock_shift", &prop)) { 1724 pr_err("Missing cpts_clock_shift property in the DT.\n"); 1725 return -EINVAL; 1726 } 1727 data->cpts_clock_shift = prop; 1728 1729 data->slave_data = devm_kzalloc(&pdev->dev, data->slaves 1730 * sizeof(struct cpsw_slave_data), 1731 GFP_KERNEL); 1732 if (!data->slave_data) 1733 return -ENOMEM; 1734 1735 if (of_property_read_u32(node, "cpdma_channels", &prop)) { 1736 pr_err("Missing cpdma_channels property in the DT.\n"); 1737 return -EINVAL; 1738 } 1739 data->channels = prop; 1740 1741 if (of_property_read_u32(node, "ale_entries", &prop)) { 1742 pr_err("Missing ale_entries property in the DT.\n"); 1743 return -EINVAL; 1744 } 1745 data->ale_entries = prop; 1746 1747 if (of_property_read_u32(node, "bd_ram_size", &prop)) { 1748 pr_err("Missing bd_ram_size property in the DT.\n"); 1749 return -EINVAL; 1750 } 1751 data->bd_ram_size = prop; 1752 1753 if (of_property_read_u32(node, "rx_descs", &prop)) { 1754 pr_err("Missing rx_descs property in the DT.\n"); 1755 return -EINVAL; 1756 } 1757 data->rx_descs = prop; 1758 1759 if (of_property_read_u32(node, "mac_control", &prop)) { 1760 pr_err("Missing mac_control property in the DT.\n"); 1761 return -EINVAL; 1762 } 1763 data->mac_control = prop; 1764 1765 if (of_property_read_bool(node, "dual_emac")) 1766 data->dual_emac = 1; 1767 1768 /* 1769 * Populate all the child nodes here... 1770 */ 1771 ret = of_platform_populate(node, NULL, NULL, &pdev->dev); 1772 /* We do not want to force this, as in some cases may not have child */ 1773 if (ret) 1774 pr_warn("Doesn't have any child node\n"); 1775 1776 for_each_child_of_node(node, slave_node) { 1777 struct cpsw_slave_data *slave_data = data->slave_data + i; 1778 const void *mac_addr = NULL; 1779 u32 phyid; 1780 int lenp; 1781 const __be32 *parp; 1782 struct device_node *mdio_node; 1783 struct platform_device *mdio; 1784 1785 /* This is no slave child node, continue */ 1786 if (strcmp(slave_node->name, "slave")) 1787 continue; 1788 1789 parp = of_get_property(slave_node, "phy_id", &lenp); 1790 if ((parp == NULL) || (lenp != (sizeof(void *) * 2))) { 1791 pr_err("Missing slave[%d] phy_id property\n", i); 1792 return -EINVAL; 1793 } 1794 mdio_node = of_find_node_by_phandle(be32_to_cpup(parp)); 1795 phyid = be32_to_cpup(parp+1); 1796 mdio = of_find_device_by_node(mdio_node); 1797 snprintf(slave_data->phy_id, sizeof(slave_data->phy_id), 1798 PHY_ID_FMT, mdio->name, phyid); 1799 1800 mac_addr = of_get_mac_address(slave_node); 1801 if (mac_addr) 1802 memcpy(slave_data->mac_addr, mac_addr, ETH_ALEN); 1803 1804 slave_data->phy_if = of_get_phy_mode(slave_node); 1805 1806 if (data->dual_emac) { 1807 if (of_property_read_u32(slave_node, "dual_emac_res_vlan", 1808 &prop)) { 1809 pr_err("Missing dual_emac_res_vlan in DT.\n"); 1810 slave_data->dual_emac_res_vlan = i+1; 1811 pr_err("Using %d as Reserved VLAN for %d slave\n", 1812 slave_data->dual_emac_res_vlan, i); 1813 } else { 1814 slave_data->dual_emac_res_vlan = prop; 1815 } 1816 } 1817 1818 i++; 1819 } 1820 1821 return 0; 1822 } 1823 1824 static int cpsw_probe_dual_emac(struct platform_device *pdev, 1825 struct cpsw_priv *priv) 1826 { 1827 struct cpsw_platform_data *data = &priv->data; 1828 struct net_device *ndev; 1829 struct cpsw_priv *priv_sl2; 1830 int ret = 0, i; 1831 1832 ndev = alloc_etherdev(sizeof(struct cpsw_priv)); 1833 if (!ndev) { 1834 pr_err("cpsw: error allocating net_device\n"); 1835 return -ENOMEM; 1836 } 1837 1838 priv_sl2 = netdev_priv(ndev); 1839 spin_lock_init(&priv_sl2->lock); 1840 priv_sl2->data = *data; 1841 priv_sl2->pdev = pdev; 1842 priv_sl2->ndev = ndev; 1843 priv_sl2->dev = &ndev->dev; 1844 priv_sl2->msg_enable = netif_msg_init(debug_level, CPSW_DEBUG); 1845 priv_sl2->rx_packet_max = max(rx_packet_max, 128); 1846 1847 if (is_valid_ether_addr(data->slave_data[1].mac_addr)) { 1848 memcpy(priv_sl2->mac_addr, data->slave_data[1].mac_addr, 1849 ETH_ALEN); 1850 pr_info("cpsw: Detected MACID = %pM\n", priv_sl2->mac_addr); 1851 } else { 1852 random_ether_addr(priv_sl2->mac_addr); 1853 pr_info("cpsw: Random MACID = %pM\n", priv_sl2->mac_addr); 1854 } 1855 memcpy(ndev->dev_addr, priv_sl2->mac_addr, ETH_ALEN); 1856 1857 priv_sl2->slaves = priv->slaves; 1858 priv_sl2->clk = priv->clk; 1859 1860 priv_sl2->coal_intvl = 0; 1861 priv_sl2->bus_freq_mhz = priv->bus_freq_mhz; 1862 1863 priv_sl2->regs = priv->regs; 1864 priv_sl2->host_port = priv->host_port; 1865 priv_sl2->host_port_regs = priv->host_port_regs; 1866 priv_sl2->wr_regs = priv->wr_regs; 1867 priv_sl2->hw_stats = priv->hw_stats; 1868 priv_sl2->dma = priv->dma; 1869 priv_sl2->txch = priv->txch; 1870 priv_sl2->rxch = priv->rxch; 1871 priv_sl2->ale = priv->ale; 1872 priv_sl2->emac_port = 1; 1873 priv->slaves[1].ndev = ndev; 1874 priv_sl2->cpts = priv->cpts; 1875 priv_sl2->version = priv->version; 1876 1877 for (i = 0; i < priv->num_irqs; i++) { 1878 priv_sl2->irqs_table[i] = priv->irqs_table[i]; 1879 priv_sl2->num_irqs = priv->num_irqs; 1880 } 1881 ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER; 1882 1883 ndev->netdev_ops = &cpsw_netdev_ops; 1884 SET_ETHTOOL_OPS(ndev, &cpsw_ethtool_ops); 1885 netif_napi_add(ndev, &priv_sl2->napi, cpsw_poll, CPSW_POLL_WEIGHT); 1886 1887 /* register the network device */ 1888 SET_NETDEV_DEV(ndev, &pdev->dev); 1889 ret = register_netdev(ndev); 1890 if (ret) { 1891 pr_err("cpsw: error registering net device\n"); 1892 free_netdev(ndev); 1893 ret = -ENODEV; 1894 } 1895 1896 return ret; 1897 } 1898 1899 static int cpsw_probe(struct platform_device *pdev) 1900 { 1901 struct cpsw_platform_data *data; 1902 struct net_device *ndev; 1903 struct cpsw_priv *priv; 1904 struct cpdma_params dma_params; 1905 struct cpsw_ale_params ale_params; 1906 void __iomem *ss_regs; 1907 struct resource *res, *ss_res; 1908 u32 slave_offset, sliver_offset, slave_size; 1909 int ret = 0, i, k = 0; 1910 1911 ndev = alloc_etherdev(sizeof(struct cpsw_priv)); 1912 if (!ndev) { 1913 pr_err("error allocating net_device\n"); 1914 return -ENOMEM; 1915 } 1916 1917 platform_set_drvdata(pdev, ndev); 1918 priv = netdev_priv(ndev); 1919 spin_lock_init(&priv->lock); 1920 priv->pdev = pdev; 1921 priv->ndev = ndev; 1922 priv->dev = &ndev->dev; 1923 priv->msg_enable = netif_msg_init(debug_level, CPSW_DEBUG); 1924 priv->rx_packet_max = max(rx_packet_max, 128); 1925 priv->cpts = devm_kzalloc(&pdev->dev, sizeof(struct cpts), GFP_KERNEL); 1926 priv->irq_enabled = true; 1927 if (!priv->cpts) { 1928 pr_err("error allocating cpts\n"); 1929 goto clean_ndev_ret; 1930 } 1931 1932 /* 1933 * This may be required here for child devices. 1934 */ 1935 pm_runtime_enable(&pdev->dev); 1936 1937 /* Select default pin state */ 1938 pinctrl_pm_select_default_state(&pdev->dev); 1939 1940 if (cpsw_probe_dt(&priv->data, pdev)) { 1941 pr_err("cpsw: platform data missing\n"); 1942 ret = -ENODEV; 1943 goto clean_runtime_disable_ret; 1944 } 1945 data = &priv->data; 1946 1947 if (is_valid_ether_addr(data->slave_data[0].mac_addr)) { 1948 memcpy(priv->mac_addr, data->slave_data[0].mac_addr, ETH_ALEN); 1949 pr_info("Detected MACID = %pM\n", priv->mac_addr); 1950 } else { 1951 eth_random_addr(priv->mac_addr); 1952 pr_info("Random MACID = %pM\n", priv->mac_addr); 1953 } 1954 1955 memcpy(ndev->dev_addr, priv->mac_addr, ETH_ALEN); 1956 1957 priv->slaves = devm_kzalloc(&pdev->dev, 1958 sizeof(struct cpsw_slave) * data->slaves, 1959 GFP_KERNEL); 1960 if (!priv->slaves) { 1961 ret = -ENOMEM; 1962 goto clean_runtime_disable_ret; 1963 } 1964 for (i = 0; i < data->slaves; i++) 1965 priv->slaves[i].slave_num = i; 1966 1967 priv->slaves[0].ndev = ndev; 1968 priv->emac_port = 0; 1969 1970 priv->clk = devm_clk_get(&pdev->dev, "fck"); 1971 if (IS_ERR(priv->clk)) { 1972 dev_err(priv->dev, "fck is not found\n"); 1973 ret = -ENODEV; 1974 goto clean_runtime_disable_ret; 1975 } 1976 priv->coal_intvl = 0; 1977 priv->bus_freq_mhz = clk_get_rate(priv->clk) / 1000000; 1978 1979 ss_res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1980 ss_regs = devm_ioremap_resource(&pdev->dev, ss_res); 1981 if (IS_ERR(ss_regs)) { 1982 ret = PTR_ERR(ss_regs); 1983 goto clean_runtime_disable_ret; 1984 } 1985 priv->regs = ss_regs; 1986 priv->version = __raw_readl(&priv->regs->id_ver); 1987 priv->host_port = HOST_PORT_NUM; 1988 1989 res = platform_get_resource(pdev, IORESOURCE_MEM, 1); 1990 priv->wr_regs = devm_ioremap_resource(&pdev->dev, res); 1991 if (IS_ERR(priv->wr_regs)) { 1992 ret = PTR_ERR(priv->wr_regs); 1993 goto clean_runtime_disable_ret; 1994 } 1995 1996 memset(&dma_params, 0, sizeof(dma_params)); 1997 memset(&ale_params, 0, sizeof(ale_params)); 1998 1999 switch (priv->version) { 2000 case CPSW_VERSION_1: 2001 priv->host_port_regs = ss_regs + CPSW1_HOST_PORT_OFFSET; 2002 priv->cpts->reg = ss_regs + CPSW1_CPTS_OFFSET; 2003 priv->hw_stats = ss_regs + CPSW1_HW_STATS; 2004 dma_params.dmaregs = ss_regs + CPSW1_CPDMA_OFFSET; 2005 dma_params.txhdp = ss_regs + CPSW1_STATERAM_OFFSET; 2006 ale_params.ale_regs = ss_regs + CPSW1_ALE_OFFSET; 2007 slave_offset = CPSW1_SLAVE_OFFSET; 2008 slave_size = CPSW1_SLAVE_SIZE; 2009 sliver_offset = CPSW1_SLIVER_OFFSET; 2010 dma_params.desc_mem_phys = 0; 2011 break; 2012 case CPSW_VERSION_2: 2013 case CPSW_VERSION_3: 2014 case CPSW_VERSION_4: 2015 priv->host_port_regs = ss_regs + CPSW2_HOST_PORT_OFFSET; 2016 priv->cpts->reg = ss_regs + CPSW2_CPTS_OFFSET; 2017 priv->hw_stats = ss_regs + CPSW2_HW_STATS; 2018 dma_params.dmaregs = ss_regs + CPSW2_CPDMA_OFFSET; 2019 dma_params.txhdp = ss_regs + CPSW2_STATERAM_OFFSET; 2020 ale_params.ale_regs = ss_regs + CPSW2_ALE_OFFSET; 2021 slave_offset = CPSW2_SLAVE_OFFSET; 2022 slave_size = CPSW2_SLAVE_SIZE; 2023 sliver_offset = CPSW2_SLIVER_OFFSET; 2024 dma_params.desc_mem_phys = 2025 (u32 __force) ss_res->start + CPSW2_BD_OFFSET; 2026 break; 2027 default: 2028 dev_err(priv->dev, "unknown version 0x%08x\n", priv->version); 2029 ret = -ENODEV; 2030 goto clean_runtime_disable_ret; 2031 } 2032 for (i = 0; i < priv->data.slaves; i++) { 2033 struct cpsw_slave *slave = &priv->slaves[i]; 2034 cpsw_slave_init(slave, priv, slave_offset, sliver_offset); 2035 slave_offset += slave_size; 2036 sliver_offset += SLIVER_SIZE; 2037 } 2038 2039 dma_params.dev = &pdev->dev; 2040 dma_params.rxthresh = dma_params.dmaregs + CPDMA_RXTHRESH; 2041 dma_params.rxfree = dma_params.dmaregs + CPDMA_RXFREE; 2042 dma_params.rxhdp = dma_params.txhdp + CPDMA_RXHDP; 2043 dma_params.txcp = dma_params.txhdp + CPDMA_TXCP; 2044 dma_params.rxcp = dma_params.txhdp + CPDMA_RXCP; 2045 2046 dma_params.num_chan = data->channels; 2047 dma_params.has_soft_reset = true; 2048 dma_params.min_packet_size = CPSW_MIN_PACKET_SIZE; 2049 dma_params.desc_mem_size = data->bd_ram_size; 2050 dma_params.desc_align = 16; 2051 dma_params.has_ext_regs = true; 2052 dma_params.desc_hw_addr = dma_params.desc_mem_phys; 2053 2054 priv->dma = cpdma_ctlr_create(&dma_params); 2055 if (!priv->dma) { 2056 dev_err(priv->dev, "error initializing dma\n"); 2057 ret = -ENOMEM; 2058 goto clean_runtime_disable_ret; 2059 } 2060 2061 priv->txch = cpdma_chan_create(priv->dma, tx_chan_num(0), 2062 cpsw_tx_handler); 2063 priv->rxch = cpdma_chan_create(priv->dma, rx_chan_num(0), 2064 cpsw_rx_handler); 2065 2066 if (WARN_ON(!priv->txch || !priv->rxch)) { 2067 dev_err(priv->dev, "error initializing dma channels\n"); 2068 ret = -ENOMEM; 2069 goto clean_dma_ret; 2070 } 2071 2072 ale_params.dev = &ndev->dev; 2073 ale_params.ale_ageout = ale_ageout; 2074 ale_params.ale_entries = data->ale_entries; 2075 ale_params.ale_ports = data->slaves; 2076 2077 priv->ale = cpsw_ale_create(&ale_params); 2078 if (!priv->ale) { 2079 dev_err(priv->dev, "error initializing ale engine\n"); 2080 ret = -ENODEV; 2081 goto clean_dma_ret; 2082 } 2083 2084 ndev->irq = platform_get_irq(pdev, 0); 2085 if (ndev->irq < 0) { 2086 dev_err(priv->dev, "error getting irq resource\n"); 2087 ret = -ENOENT; 2088 goto clean_ale_ret; 2089 } 2090 2091 while ((res = platform_get_resource(priv->pdev, IORESOURCE_IRQ, k))) { 2092 for (i = res->start; i <= res->end; i++) { 2093 if (devm_request_irq(&pdev->dev, i, cpsw_interrupt, 0, 2094 dev_name(priv->dev), priv)) { 2095 dev_err(priv->dev, "error attaching irq\n"); 2096 goto clean_ale_ret; 2097 } 2098 priv->irqs_table[k] = i; 2099 priv->num_irqs = k + 1; 2100 } 2101 k++; 2102 } 2103 2104 ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER; 2105 2106 ndev->netdev_ops = &cpsw_netdev_ops; 2107 SET_ETHTOOL_OPS(ndev, &cpsw_ethtool_ops); 2108 netif_napi_add(ndev, &priv->napi, cpsw_poll, CPSW_POLL_WEIGHT); 2109 2110 /* register the network device */ 2111 SET_NETDEV_DEV(ndev, &pdev->dev); 2112 ret = register_netdev(ndev); 2113 if (ret) { 2114 dev_err(priv->dev, "error registering net device\n"); 2115 ret = -ENODEV; 2116 goto clean_ale_ret; 2117 } 2118 2119 if (cpts_register(&pdev->dev, priv->cpts, 2120 data->cpts_clock_mult, data->cpts_clock_shift)) 2121 dev_err(priv->dev, "error registering cpts device\n"); 2122 2123 cpsw_notice(priv, probe, "initialized device (regs %x, irq %d)\n", 2124 ss_res->start, ndev->irq); 2125 2126 if (priv->data.dual_emac) { 2127 ret = cpsw_probe_dual_emac(pdev, priv); 2128 if (ret) { 2129 cpsw_err(priv, probe, "error probe slave 2 emac interface\n"); 2130 goto clean_ale_ret; 2131 } 2132 } 2133 2134 return 0; 2135 2136 clean_ale_ret: 2137 cpsw_ale_destroy(priv->ale); 2138 clean_dma_ret: 2139 cpdma_chan_destroy(priv->txch); 2140 cpdma_chan_destroy(priv->rxch); 2141 cpdma_ctlr_destroy(priv->dma); 2142 clean_runtime_disable_ret: 2143 pm_runtime_disable(&pdev->dev); 2144 clean_ndev_ret: 2145 free_netdev(priv->ndev); 2146 return ret; 2147 } 2148 2149 static int cpsw_remove(struct platform_device *pdev) 2150 { 2151 struct net_device *ndev = platform_get_drvdata(pdev); 2152 struct cpsw_priv *priv = netdev_priv(ndev); 2153 2154 if (priv->data.dual_emac) 2155 unregister_netdev(cpsw_get_slave_ndev(priv, 1)); 2156 unregister_netdev(ndev); 2157 2158 cpts_unregister(priv->cpts); 2159 2160 cpsw_ale_destroy(priv->ale); 2161 cpdma_chan_destroy(priv->txch); 2162 cpdma_chan_destroy(priv->rxch); 2163 cpdma_ctlr_destroy(priv->dma); 2164 pm_runtime_disable(&pdev->dev); 2165 if (priv->data.dual_emac) 2166 free_netdev(cpsw_get_slave_ndev(priv, 1)); 2167 free_netdev(ndev); 2168 return 0; 2169 } 2170 2171 static int cpsw_suspend(struct device *dev) 2172 { 2173 struct platform_device *pdev = to_platform_device(dev); 2174 struct net_device *ndev = platform_get_drvdata(pdev); 2175 struct cpsw_priv *priv = netdev_priv(ndev); 2176 2177 if (netif_running(ndev)) 2178 cpsw_ndo_stop(ndev); 2179 2180 for_each_slave(priv, soft_reset_slave); 2181 2182 pm_runtime_put_sync(&pdev->dev); 2183 2184 /* Select sleep pin state */ 2185 pinctrl_pm_select_sleep_state(&pdev->dev); 2186 2187 return 0; 2188 } 2189 2190 static int cpsw_resume(struct device *dev) 2191 { 2192 struct platform_device *pdev = to_platform_device(dev); 2193 struct net_device *ndev = platform_get_drvdata(pdev); 2194 2195 pm_runtime_get_sync(&pdev->dev); 2196 2197 /* Select default pin state */ 2198 pinctrl_pm_select_default_state(&pdev->dev); 2199 2200 if (netif_running(ndev)) 2201 cpsw_ndo_open(ndev); 2202 return 0; 2203 } 2204 2205 static const struct dev_pm_ops cpsw_pm_ops = { 2206 .suspend = cpsw_suspend, 2207 .resume = cpsw_resume, 2208 }; 2209 2210 static const struct of_device_id cpsw_of_mtable[] = { 2211 { .compatible = "ti,cpsw", }, 2212 { /* sentinel */ }, 2213 }; 2214 MODULE_DEVICE_TABLE(of, cpsw_of_mtable); 2215 2216 static struct platform_driver cpsw_driver = { 2217 .driver = { 2218 .name = "cpsw", 2219 .owner = THIS_MODULE, 2220 .pm = &cpsw_pm_ops, 2221 .of_match_table = cpsw_of_mtable, 2222 }, 2223 .probe = cpsw_probe, 2224 .remove = cpsw_remove, 2225 }; 2226 2227 static int __init cpsw_init(void) 2228 { 2229 return platform_driver_register(&cpsw_driver); 2230 } 2231 late_initcall(cpsw_init); 2232 2233 static void __exit cpsw_exit(void) 2234 { 2235 platform_driver_unregister(&cpsw_driver); 2236 } 2237 module_exit(cpsw_exit); 2238 2239 MODULE_LICENSE("GPL"); 2240 MODULE_AUTHOR("Cyril Chemparathy <cyril@ti.com>"); 2241 MODULE_AUTHOR("Mugunthan V N <mugunthanvnm@ti.com>"); 2242 MODULE_DESCRIPTION("TI CPSW Ethernet driver"); 2243