1 /* 2 * Texas Instruments Ethernet Switch Driver 3 * 4 * Copyright (C) 2012 Texas Instruments 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License as 8 * published by the Free Software Foundation version 2. 9 * 10 * This program is distributed "as is" WITHOUT ANY WARRANTY of any 11 * kind, whether express or implied; without even the implied warranty 12 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 */ 15 16 #include <linux/kernel.h> 17 #include <linux/io.h> 18 #include <linux/clk.h> 19 #include <linux/timer.h> 20 #include <linux/module.h> 21 #include <linux/platform_device.h> 22 #include <linux/irqreturn.h> 23 #include <linux/interrupt.h> 24 #include <linux/if_ether.h> 25 #include <linux/etherdevice.h> 26 #include <linux/netdevice.h> 27 #include <linux/net_tstamp.h> 28 #include <linux/phy.h> 29 #include <linux/workqueue.h> 30 #include <linux/delay.h> 31 #include <linux/pm_runtime.h> 32 #include <linux/of.h> 33 #include <linux/of_net.h> 34 #include <linux/of_device.h> 35 #include <linux/if_vlan.h> 36 37 #include <linux/pinctrl/consumer.h> 38 39 #include "cpsw.h" 40 #include "cpsw_ale.h" 41 #include "cpts.h" 42 #include "davinci_cpdma.h" 43 44 #define CPSW_DEBUG (NETIF_MSG_HW | NETIF_MSG_WOL | \ 45 NETIF_MSG_DRV | NETIF_MSG_LINK | \ 46 NETIF_MSG_IFUP | NETIF_MSG_INTR | \ 47 NETIF_MSG_PROBE | NETIF_MSG_TIMER | \ 48 NETIF_MSG_IFDOWN | NETIF_MSG_RX_ERR | \ 49 NETIF_MSG_TX_ERR | NETIF_MSG_TX_DONE | \ 50 NETIF_MSG_PKTDATA | NETIF_MSG_TX_QUEUED | \ 51 NETIF_MSG_RX_STATUS) 52 53 #define cpsw_info(priv, type, format, ...) \ 54 do { \ 55 if (netif_msg_##type(priv) && net_ratelimit()) \ 56 dev_info(priv->dev, format, ## __VA_ARGS__); \ 57 } while (0) 58 59 #define cpsw_err(priv, type, format, ...) \ 60 do { \ 61 if (netif_msg_##type(priv) && net_ratelimit()) \ 62 dev_err(priv->dev, format, ## __VA_ARGS__); \ 63 } while (0) 64 65 #define cpsw_dbg(priv, type, format, ...) \ 66 do { \ 67 if (netif_msg_##type(priv) && net_ratelimit()) \ 68 dev_dbg(priv->dev, format, ## __VA_ARGS__); \ 69 } while (0) 70 71 #define cpsw_notice(priv, type, format, ...) \ 72 do { \ 73 if (netif_msg_##type(priv) && net_ratelimit()) \ 74 dev_notice(priv->dev, format, ## __VA_ARGS__); \ 75 } while (0) 76 77 #define ALE_ALL_PORTS 0x7 78 79 #define CPSW_MAJOR_VERSION(reg) (reg >> 8 & 0x7) 80 #define CPSW_MINOR_VERSION(reg) (reg & 0xff) 81 #define CPSW_RTL_VERSION(reg) ((reg >> 11) & 0x1f) 82 83 #define CPSW_VERSION_1 0x19010a 84 #define CPSW_VERSION_2 0x19010c 85 #define CPSW_VERSION_3 0x19010f 86 #define CPSW_VERSION_4 0x190112 87 88 #define HOST_PORT_NUM 0 89 #define SLIVER_SIZE 0x40 90 91 #define CPSW1_HOST_PORT_OFFSET 0x028 92 #define CPSW1_SLAVE_OFFSET 0x050 93 #define CPSW1_SLAVE_SIZE 0x040 94 #define CPSW1_CPDMA_OFFSET 0x100 95 #define CPSW1_STATERAM_OFFSET 0x200 96 #define CPSW1_HW_STATS 0x400 97 #define CPSW1_CPTS_OFFSET 0x500 98 #define CPSW1_ALE_OFFSET 0x600 99 #define CPSW1_SLIVER_OFFSET 0x700 100 101 #define CPSW2_HOST_PORT_OFFSET 0x108 102 #define CPSW2_SLAVE_OFFSET 0x200 103 #define CPSW2_SLAVE_SIZE 0x100 104 #define CPSW2_CPDMA_OFFSET 0x800 105 #define CPSW2_HW_STATS 0x900 106 #define CPSW2_STATERAM_OFFSET 0xa00 107 #define CPSW2_CPTS_OFFSET 0xc00 108 #define CPSW2_ALE_OFFSET 0xd00 109 #define CPSW2_SLIVER_OFFSET 0xd80 110 #define CPSW2_BD_OFFSET 0x2000 111 112 #define CPDMA_RXTHRESH 0x0c0 113 #define CPDMA_RXFREE 0x0e0 114 #define CPDMA_TXHDP 0x00 115 #define CPDMA_RXHDP 0x20 116 #define CPDMA_TXCP 0x40 117 #define CPDMA_RXCP 0x60 118 119 #define CPSW_POLL_WEIGHT 64 120 #define CPSW_MIN_PACKET_SIZE 60 121 #define CPSW_MAX_PACKET_SIZE (1500 + 14 + 4 + 4) 122 123 #define RX_PRIORITY_MAPPING 0x76543210 124 #define TX_PRIORITY_MAPPING 0x33221100 125 #define CPDMA_TX_PRIORITY_MAP 0x76543210 126 127 #define CPSW_VLAN_AWARE BIT(1) 128 #define CPSW_ALE_VLAN_AWARE 1 129 130 #define CPSW_FIFO_NORMAL_MODE (0 << 15) 131 #define CPSW_FIFO_DUAL_MAC_MODE (1 << 15) 132 #define CPSW_FIFO_RATE_LIMIT_MODE (2 << 15) 133 134 #define CPSW_INTPACEEN (0x3f << 16) 135 #define CPSW_INTPRESCALE_MASK (0x7FF << 0) 136 #define CPSW_CMINTMAX_CNT 63 137 #define CPSW_CMINTMIN_CNT 2 138 #define CPSW_CMINTMAX_INTVL (1000 / CPSW_CMINTMIN_CNT) 139 #define CPSW_CMINTMIN_INTVL ((1000 / CPSW_CMINTMAX_CNT) + 1) 140 141 #define cpsw_enable_irq(priv) \ 142 do { \ 143 u32 i; \ 144 for (i = 0; i < priv->num_irqs; i++) \ 145 enable_irq(priv->irqs_table[i]); \ 146 } while (0); 147 #define cpsw_disable_irq(priv) \ 148 do { \ 149 u32 i; \ 150 for (i = 0; i < priv->num_irqs; i++) \ 151 disable_irq_nosync(priv->irqs_table[i]); \ 152 } while (0); 153 154 #define cpsw_slave_index(priv) \ 155 ((priv->data.dual_emac) ? priv->emac_port : \ 156 priv->data.active_slave) 157 158 static int debug_level; 159 module_param(debug_level, int, 0); 160 MODULE_PARM_DESC(debug_level, "cpsw debug level (NETIF_MSG bits)"); 161 162 static int ale_ageout = 10; 163 module_param(ale_ageout, int, 0); 164 MODULE_PARM_DESC(ale_ageout, "cpsw ale ageout interval (seconds)"); 165 166 static int rx_packet_max = CPSW_MAX_PACKET_SIZE; 167 module_param(rx_packet_max, int, 0); 168 MODULE_PARM_DESC(rx_packet_max, "maximum receive packet size (bytes)"); 169 170 struct cpsw_wr_regs { 171 u32 id_ver; 172 u32 soft_reset; 173 u32 control; 174 u32 int_control; 175 u32 rx_thresh_en; 176 u32 rx_en; 177 u32 tx_en; 178 u32 misc_en; 179 u32 mem_allign1[8]; 180 u32 rx_thresh_stat; 181 u32 rx_stat; 182 u32 tx_stat; 183 u32 misc_stat; 184 u32 mem_allign2[8]; 185 u32 rx_imax; 186 u32 tx_imax; 187 188 }; 189 190 struct cpsw_ss_regs { 191 u32 id_ver; 192 u32 control; 193 u32 soft_reset; 194 u32 stat_port_en; 195 u32 ptype; 196 u32 soft_idle; 197 u32 thru_rate; 198 u32 gap_thresh; 199 u32 tx_start_wds; 200 u32 flow_control; 201 u32 vlan_ltype; 202 u32 ts_ltype; 203 u32 dlr_ltype; 204 }; 205 206 /* CPSW_PORT_V1 */ 207 #define CPSW1_MAX_BLKS 0x00 /* Maximum FIFO Blocks */ 208 #define CPSW1_BLK_CNT 0x04 /* FIFO Block Usage Count (Read Only) */ 209 #define CPSW1_TX_IN_CTL 0x08 /* Transmit FIFO Control */ 210 #define CPSW1_PORT_VLAN 0x0c /* VLAN Register */ 211 #define CPSW1_TX_PRI_MAP 0x10 /* Tx Header Priority to Switch Pri Mapping */ 212 #define CPSW1_TS_CTL 0x14 /* Time Sync Control */ 213 #define CPSW1_TS_SEQ_LTYPE 0x18 /* Time Sync Sequence ID Offset and Msg Type */ 214 #define CPSW1_TS_VLAN 0x1c /* Time Sync VLAN1 and VLAN2 */ 215 216 /* CPSW_PORT_V2 */ 217 #define CPSW2_CONTROL 0x00 /* Control Register */ 218 #define CPSW2_MAX_BLKS 0x08 /* Maximum FIFO Blocks */ 219 #define CPSW2_BLK_CNT 0x0c /* FIFO Block Usage Count (Read Only) */ 220 #define CPSW2_TX_IN_CTL 0x10 /* Transmit FIFO Control */ 221 #define CPSW2_PORT_VLAN 0x14 /* VLAN Register */ 222 #define CPSW2_TX_PRI_MAP 0x18 /* Tx Header Priority to Switch Pri Mapping */ 223 #define CPSW2_TS_SEQ_MTYPE 0x1c /* Time Sync Sequence ID Offset and Msg Type */ 224 225 /* CPSW_PORT_V1 and V2 */ 226 #define SA_LO 0x20 /* CPGMAC_SL Source Address Low */ 227 #define SA_HI 0x24 /* CPGMAC_SL Source Address High */ 228 #define SEND_PERCENT 0x28 /* Transmit Queue Send Percentages */ 229 230 /* CPSW_PORT_V2 only */ 231 #define RX_DSCP_PRI_MAP0 0x30 /* Rx DSCP Priority to Rx Packet Mapping */ 232 #define RX_DSCP_PRI_MAP1 0x34 /* Rx DSCP Priority to Rx Packet Mapping */ 233 #define RX_DSCP_PRI_MAP2 0x38 /* Rx DSCP Priority to Rx Packet Mapping */ 234 #define RX_DSCP_PRI_MAP3 0x3c /* Rx DSCP Priority to Rx Packet Mapping */ 235 #define RX_DSCP_PRI_MAP4 0x40 /* Rx DSCP Priority to Rx Packet Mapping */ 236 #define RX_DSCP_PRI_MAP5 0x44 /* Rx DSCP Priority to Rx Packet Mapping */ 237 #define RX_DSCP_PRI_MAP6 0x48 /* Rx DSCP Priority to Rx Packet Mapping */ 238 #define RX_DSCP_PRI_MAP7 0x4c /* Rx DSCP Priority to Rx Packet Mapping */ 239 240 /* Bit definitions for the CPSW2_CONTROL register */ 241 #define PASS_PRI_TAGGED (1<<24) /* Pass Priority Tagged */ 242 #define VLAN_LTYPE2_EN (1<<21) /* VLAN LTYPE 2 enable */ 243 #define VLAN_LTYPE1_EN (1<<20) /* VLAN LTYPE 1 enable */ 244 #define DSCP_PRI_EN (1<<16) /* DSCP Priority Enable */ 245 #define TS_320 (1<<14) /* Time Sync Dest Port 320 enable */ 246 #define TS_319 (1<<13) /* Time Sync Dest Port 319 enable */ 247 #define TS_132 (1<<12) /* Time Sync Dest IP Addr 132 enable */ 248 #define TS_131 (1<<11) /* Time Sync Dest IP Addr 131 enable */ 249 #define TS_130 (1<<10) /* Time Sync Dest IP Addr 130 enable */ 250 #define TS_129 (1<<9) /* Time Sync Dest IP Addr 129 enable */ 251 #define TS_BIT8 (1<<8) /* ts_ttl_nonzero? */ 252 #define TS_ANNEX_D_EN (1<<4) /* Time Sync Annex D enable */ 253 #define TS_LTYPE2_EN (1<<3) /* Time Sync LTYPE 2 enable */ 254 #define TS_LTYPE1_EN (1<<2) /* Time Sync LTYPE 1 enable */ 255 #define TS_TX_EN (1<<1) /* Time Sync Transmit Enable */ 256 #define TS_RX_EN (1<<0) /* Time Sync Receive Enable */ 257 258 #define CTRL_TS_BITS \ 259 (TS_320 | TS_319 | TS_132 | TS_131 | TS_130 | TS_129 | TS_BIT8 | \ 260 TS_ANNEX_D_EN | TS_LTYPE1_EN) 261 262 #define CTRL_ALL_TS_MASK (CTRL_TS_BITS | TS_TX_EN | TS_RX_EN) 263 #define CTRL_TX_TS_BITS (CTRL_TS_BITS | TS_TX_EN) 264 #define CTRL_RX_TS_BITS (CTRL_TS_BITS | TS_RX_EN) 265 266 /* Bit definitions for the CPSW2_TS_SEQ_MTYPE register */ 267 #define TS_SEQ_ID_OFFSET_SHIFT (16) /* Time Sync Sequence ID Offset */ 268 #define TS_SEQ_ID_OFFSET_MASK (0x3f) 269 #define TS_MSG_TYPE_EN_SHIFT (0) /* Time Sync Message Type Enable */ 270 #define TS_MSG_TYPE_EN_MASK (0xffff) 271 272 /* The PTP event messages - Sync, Delay_Req, Pdelay_Req, and Pdelay_Resp. */ 273 #define EVENT_MSG_BITS ((1<<0) | (1<<1) | (1<<2) | (1<<3)) 274 275 /* Bit definitions for the CPSW1_TS_CTL register */ 276 #define CPSW_V1_TS_RX_EN BIT(0) 277 #define CPSW_V1_TS_TX_EN BIT(4) 278 #define CPSW_V1_MSG_TYPE_OFS 16 279 280 /* Bit definitions for the CPSW1_TS_SEQ_LTYPE register */ 281 #define CPSW_V1_SEQ_ID_OFS_SHIFT 16 282 283 struct cpsw_host_regs { 284 u32 max_blks; 285 u32 blk_cnt; 286 u32 tx_in_ctl; 287 u32 port_vlan; 288 u32 tx_pri_map; 289 u32 cpdma_tx_pri_map; 290 u32 cpdma_rx_chan_map; 291 }; 292 293 struct cpsw_sliver_regs { 294 u32 id_ver; 295 u32 mac_control; 296 u32 mac_status; 297 u32 soft_reset; 298 u32 rx_maxlen; 299 u32 __reserved_0; 300 u32 rx_pause; 301 u32 tx_pause; 302 u32 __reserved_1; 303 u32 rx_pri_map; 304 }; 305 306 struct cpsw_hw_stats { 307 u32 rxgoodframes; 308 u32 rxbroadcastframes; 309 u32 rxmulticastframes; 310 u32 rxpauseframes; 311 u32 rxcrcerrors; 312 u32 rxaligncodeerrors; 313 u32 rxoversizedframes; 314 u32 rxjabberframes; 315 u32 rxundersizedframes; 316 u32 rxfragments; 317 u32 __pad_0[2]; 318 u32 rxoctets; 319 u32 txgoodframes; 320 u32 txbroadcastframes; 321 u32 txmulticastframes; 322 u32 txpauseframes; 323 u32 txdeferredframes; 324 u32 txcollisionframes; 325 u32 txsinglecollframes; 326 u32 txmultcollframes; 327 u32 txexcessivecollisions; 328 u32 txlatecollisions; 329 u32 txunderrun; 330 u32 txcarriersenseerrors; 331 u32 txoctets; 332 u32 octetframes64; 333 u32 octetframes65t127; 334 u32 octetframes128t255; 335 u32 octetframes256t511; 336 u32 octetframes512t1023; 337 u32 octetframes1024tup; 338 u32 netoctets; 339 u32 rxsofoverruns; 340 u32 rxmofoverruns; 341 u32 rxdmaoverruns; 342 }; 343 344 struct cpsw_slave { 345 void __iomem *regs; 346 struct cpsw_sliver_regs __iomem *sliver; 347 int slave_num; 348 u32 mac_control; 349 struct cpsw_slave_data *data; 350 struct phy_device *phy; 351 struct net_device *ndev; 352 u32 port_vlan; 353 u32 open_stat; 354 }; 355 356 static inline u32 slave_read(struct cpsw_slave *slave, u32 offset) 357 { 358 return __raw_readl(slave->regs + offset); 359 } 360 361 static inline void slave_write(struct cpsw_slave *slave, u32 val, u32 offset) 362 { 363 __raw_writel(val, slave->regs + offset); 364 } 365 366 struct cpsw_priv { 367 spinlock_t lock; 368 struct platform_device *pdev; 369 struct net_device *ndev; 370 struct resource *cpsw_res; 371 struct resource *cpsw_wr_res; 372 struct napi_struct napi; 373 struct device *dev; 374 struct cpsw_platform_data data; 375 struct cpsw_ss_regs __iomem *regs; 376 struct cpsw_wr_regs __iomem *wr_regs; 377 u8 __iomem *hw_stats; 378 struct cpsw_host_regs __iomem *host_port_regs; 379 u32 msg_enable; 380 u32 version; 381 u32 coal_intvl; 382 u32 bus_freq_mhz; 383 struct net_device_stats stats; 384 int rx_packet_max; 385 int host_port; 386 struct clk *clk; 387 u8 mac_addr[ETH_ALEN]; 388 struct cpsw_slave *slaves; 389 struct cpdma_ctlr *dma; 390 struct cpdma_chan *txch, *rxch; 391 struct cpsw_ale *ale; 392 /* snapshot of IRQ numbers */ 393 u32 irqs_table[4]; 394 u32 num_irqs; 395 bool irq_enabled; 396 struct cpts *cpts; 397 u32 emac_port; 398 }; 399 400 struct cpsw_stats { 401 char stat_string[ETH_GSTRING_LEN]; 402 int type; 403 int sizeof_stat; 404 int stat_offset; 405 }; 406 407 enum { 408 CPSW_STATS, 409 CPDMA_RX_STATS, 410 CPDMA_TX_STATS, 411 }; 412 413 #define CPSW_STAT(m) CPSW_STATS, \ 414 sizeof(((struct cpsw_hw_stats *)0)->m), \ 415 offsetof(struct cpsw_hw_stats, m) 416 #define CPDMA_RX_STAT(m) CPDMA_RX_STATS, \ 417 sizeof(((struct cpdma_chan_stats *)0)->m), \ 418 offsetof(struct cpdma_chan_stats, m) 419 #define CPDMA_TX_STAT(m) CPDMA_TX_STATS, \ 420 sizeof(((struct cpdma_chan_stats *)0)->m), \ 421 offsetof(struct cpdma_chan_stats, m) 422 423 static const struct cpsw_stats cpsw_gstrings_stats[] = { 424 { "Good Rx Frames", CPSW_STAT(rxgoodframes) }, 425 { "Broadcast Rx Frames", CPSW_STAT(rxbroadcastframes) }, 426 { "Multicast Rx Frames", CPSW_STAT(rxmulticastframes) }, 427 { "Pause Rx Frames", CPSW_STAT(rxpauseframes) }, 428 { "Rx CRC Errors", CPSW_STAT(rxcrcerrors) }, 429 { "Rx Align/Code Errors", CPSW_STAT(rxaligncodeerrors) }, 430 { "Oversize Rx Frames", CPSW_STAT(rxoversizedframes) }, 431 { "Rx Jabbers", CPSW_STAT(rxjabberframes) }, 432 { "Undersize (Short) Rx Frames", CPSW_STAT(rxundersizedframes) }, 433 { "Rx Fragments", CPSW_STAT(rxfragments) }, 434 { "Rx Octets", CPSW_STAT(rxoctets) }, 435 { "Good Tx Frames", CPSW_STAT(txgoodframes) }, 436 { "Broadcast Tx Frames", CPSW_STAT(txbroadcastframes) }, 437 { "Multicast Tx Frames", CPSW_STAT(txmulticastframes) }, 438 { "Pause Tx Frames", CPSW_STAT(txpauseframes) }, 439 { "Deferred Tx Frames", CPSW_STAT(txdeferredframes) }, 440 { "Collisions", CPSW_STAT(txcollisionframes) }, 441 { "Single Collision Tx Frames", CPSW_STAT(txsinglecollframes) }, 442 { "Multiple Collision Tx Frames", CPSW_STAT(txmultcollframes) }, 443 { "Excessive Collisions", CPSW_STAT(txexcessivecollisions) }, 444 { "Late Collisions", CPSW_STAT(txlatecollisions) }, 445 { "Tx Underrun", CPSW_STAT(txunderrun) }, 446 { "Carrier Sense Errors", CPSW_STAT(txcarriersenseerrors) }, 447 { "Tx Octets", CPSW_STAT(txoctets) }, 448 { "Rx + Tx 64 Octet Frames", CPSW_STAT(octetframes64) }, 449 { "Rx + Tx 65-127 Octet Frames", CPSW_STAT(octetframes65t127) }, 450 { "Rx + Tx 128-255 Octet Frames", CPSW_STAT(octetframes128t255) }, 451 { "Rx + Tx 256-511 Octet Frames", CPSW_STAT(octetframes256t511) }, 452 { "Rx + Tx 512-1023 Octet Frames", CPSW_STAT(octetframes512t1023) }, 453 { "Rx + Tx 1024-Up Octet Frames", CPSW_STAT(octetframes1024tup) }, 454 { "Net Octets", CPSW_STAT(netoctets) }, 455 { "Rx Start of Frame Overruns", CPSW_STAT(rxsofoverruns) }, 456 { "Rx Middle of Frame Overruns", CPSW_STAT(rxmofoverruns) }, 457 { "Rx DMA Overruns", CPSW_STAT(rxdmaoverruns) }, 458 { "Rx DMA chan: head_enqueue", CPDMA_RX_STAT(head_enqueue) }, 459 { "Rx DMA chan: tail_enqueue", CPDMA_RX_STAT(tail_enqueue) }, 460 { "Rx DMA chan: pad_enqueue", CPDMA_RX_STAT(pad_enqueue) }, 461 { "Rx DMA chan: misqueued", CPDMA_RX_STAT(misqueued) }, 462 { "Rx DMA chan: desc_alloc_fail", CPDMA_RX_STAT(desc_alloc_fail) }, 463 { "Rx DMA chan: pad_alloc_fail", CPDMA_RX_STAT(pad_alloc_fail) }, 464 { "Rx DMA chan: runt_receive_buf", CPDMA_RX_STAT(runt_receive_buff) }, 465 { "Rx DMA chan: runt_transmit_buf", CPDMA_RX_STAT(runt_transmit_buff) }, 466 { "Rx DMA chan: empty_dequeue", CPDMA_RX_STAT(empty_dequeue) }, 467 { "Rx DMA chan: busy_dequeue", CPDMA_RX_STAT(busy_dequeue) }, 468 { "Rx DMA chan: good_dequeue", CPDMA_RX_STAT(good_dequeue) }, 469 { "Rx DMA chan: requeue", CPDMA_RX_STAT(requeue) }, 470 { "Rx DMA chan: teardown_dequeue", CPDMA_RX_STAT(teardown_dequeue) }, 471 { "Tx DMA chan: head_enqueue", CPDMA_TX_STAT(head_enqueue) }, 472 { "Tx DMA chan: tail_enqueue", CPDMA_TX_STAT(tail_enqueue) }, 473 { "Tx DMA chan: pad_enqueue", CPDMA_TX_STAT(pad_enqueue) }, 474 { "Tx DMA chan: misqueued", CPDMA_TX_STAT(misqueued) }, 475 { "Tx DMA chan: desc_alloc_fail", CPDMA_TX_STAT(desc_alloc_fail) }, 476 { "Tx DMA chan: pad_alloc_fail", CPDMA_TX_STAT(pad_alloc_fail) }, 477 { "Tx DMA chan: runt_receive_buf", CPDMA_TX_STAT(runt_receive_buff) }, 478 { "Tx DMA chan: runt_transmit_buf", CPDMA_TX_STAT(runt_transmit_buff) }, 479 { "Tx DMA chan: empty_dequeue", CPDMA_TX_STAT(empty_dequeue) }, 480 { "Tx DMA chan: busy_dequeue", CPDMA_TX_STAT(busy_dequeue) }, 481 { "Tx DMA chan: good_dequeue", CPDMA_TX_STAT(good_dequeue) }, 482 { "Tx DMA chan: requeue", CPDMA_TX_STAT(requeue) }, 483 { "Tx DMA chan: teardown_dequeue", CPDMA_TX_STAT(teardown_dequeue) }, 484 }; 485 486 #define CPSW_STATS_LEN ARRAY_SIZE(cpsw_gstrings_stats) 487 488 #define napi_to_priv(napi) container_of(napi, struct cpsw_priv, napi) 489 #define for_each_slave(priv, func, arg...) \ 490 do { \ 491 struct cpsw_slave *slave; \ 492 int n; \ 493 if (priv->data.dual_emac) \ 494 (func)((priv)->slaves + priv->emac_port, ##arg);\ 495 else \ 496 for (n = (priv)->data.slaves, \ 497 slave = (priv)->slaves; \ 498 n; n--) \ 499 (func)(slave++, ##arg); \ 500 } while (0) 501 #define cpsw_get_slave_ndev(priv, __slave_no__) \ 502 (priv->slaves[__slave_no__].ndev) 503 #define cpsw_get_slave_priv(priv, __slave_no__) \ 504 ((priv->slaves[__slave_no__].ndev) ? \ 505 netdev_priv(priv->slaves[__slave_no__].ndev) : NULL) \ 506 507 #define cpsw_dual_emac_src_port_detect(status, priv, ndev, skb) \ 508 do { \ 509 if (!priv->data.dual_emac) \ 510 break; \ 511 if (CPDMA_RX_SOURCE_PORT(status) == 1) { \ 512 ndev = cpsw_get_slave_ndev(priv, 0); \ 513 priv = netdev_priv(ndev); \ 514 skb->dev = ndev; \ 515 } else if (CPDMA_RX_SOURCE_PORT(status) == 2) { \ 516 ndev = cpsw_get_slave_ndev(priv, 1); \ 517 priv = netdev_priv(ndev); \ 518 skb->dev = ndev; \ 519 } \ 520 } while (0) 521 #define cpsw_add_mcast(priv, addr) \ 522 do { \ 523 if (priv->data.dual_emac) { \ 524 struct cpsw_slave *slave = priv->slaves + \ 525 priv->emac_port; \ 526 int slave_port = cpsw_get_slave_port(priv, \ 527 slave->slave_num); \ 528 cpsw_ale_add_mcast(priv->ale, addr, \ 529 1 << slave_port | 1 << priv->host_port, \ 530 ALE_VLAN, slave->port_vlan, 0); \ 531 } else { \ 532 cpsw_ale_add_mcast(priv->ale, addr, \ 533 ALE_ALL_PORTS << priv->host_port, \ 534 0, 0, 0); \ 535 } \ 536 } while (0) 537 538 static inline int cpsw_get_slave_port(struct cpsw_priv *priv, u32 slave_num) 539 { 540 if (priv->host_port == 0) 541 return slave_num + 1; 542 else 543 return slave_num; 544 } 545 546 static void cpsw_ndo_set_rx_mode(struct net_device *ndev) 547 { 548 struct cpsw_priv *priv = netdev_priv(ndev); 549 550 if (ndev->flags & IFF_PROMISC) { 551 /* Enable promiscuous mode */ 552 dev_err(priv->dev, "Ignoring Promiscuous mode\n"); 553 return; 554 } 555 556 /* Clear all mcast from ALE */ 557 cpsw_ale_flush_multicast(priv->ale, ALE_ALL_PORTS << priv->host_port); 558 559 if (!netdev_mc_empty(ndev)) { 560 struct netdev_hw_addr *ha; 561 562 /* program multicast address list into ALE register */ 563 netdev_for_each_mc_addr(ha, ndev) { 564 cpsw_add_mcast(priv, (u8 *)ha->addr); 565 } 566 } 567 } 568 569 static void cpsw_intr_enable(struct cpsw_priv *priv) 570 { 571 __raw_writel(0xFF, &priv->wr_regs->tx_en); 572 __raw_writel(0xFF, &priv->wr_regs->rx_en); 573 574 cpdma_ctlr_int_ctrl(priv->dma, true); 575 return; 576 } 577 578 static void cpsw_intr_disable(struct cpsw_priv *priv) 579 { 580 __raw_writel(0, &priv->wr_regs->tx_en); 581 __raw_writel(0, &priv->wr_regs->rx_en); 582 583 cpdma_ctlr_int_ctrl(priv->dma, false); 584 return; 585 } 586 587 void cpsw_tx_handler(void *token, int len, int status) 588 { 589 struct sk_buff *skb = token; 590 struct net_device *ndev = skb->dev; 591 struct cpsw_priv *priv = netdev_priv(ndev); 592 593 /* Check whether the queue is stopped due to stalled tx dma, if the 594 * queue is stopped then start the queue as we have free desc for tx 595 */ 596 if (unlikely(netif_queue_stopped(ndev))) 597 netif_wake_queue(ndev); 598 cpts_tx_timestamp(priv->cpts, skb); 599 priv->stats.tx_packets++; 600 priv->stats.tx_bytes += len; 601 dev_kfree_skb_any(skb); 602 } 603 604 void cpsw_rx_handler(void *token, int len, int status) 605 { 606 struct sk_buff *skb = token; 607 struct sk_buff *new_skb; 608 struct net_device *ndev = skb->dev; 609 struct cpsw_priv *priv = netdev_priv(ndev); 610 int ret = 0; 611 612 cpsw_dual_emac_src_port_detect(status, priv, ndev, skb); 613 614 if (unlikely(status < 0)) { 615 /* the interface is going down, skbs are purged */ 616 dev_kfree_skb_any(skb); 617 return; 618 } 619 620 new_skb = netdev_alloc_skb_ip_align(ndev, priv->rx_packet_max); 621 if (new_skb) { 622 skb_put(skb, len); 623 cpts_rx_timestamp(priv->cpts, skb); 624 skb->protocol = eth_type_trans(skb, ndev); 625 netif_receive_skb(skb); 626 priv->stats.rx_bytes += len; 627 priv->stats.rx_packets++; 628 } else { 629 priv->stats.rx_dropped++; 630 new_skb = skb; 631 } 632 633 ret = cpdma_chan_submit(priv->rxch, new_skb, new_skb->data, 634 skb_tailroom(new_skb), 0); 635 if (WARN_ON(ret < 0)) 636 dev_kfree_skb_any(new_skb); 637 } 638 639 static irqreturn_t cpsw_interrupt(int irq, void *dev_id) 640 { 641 struct cpsw_priv *priv = dev_id; 642 643 cpsw_intr_disable(priv); 644 if (priv->irq_enabled == true) { 645 cpsw_disable_irq(priv); 646 priv->irq_enabled = false; 647 } 648 649 if (netif_running(priv->ndev)) { 650 napi_schedule(&priv->napi); 651 return IRQ_HANDLED; 652 } 653 654 priv = cpsw_get_slave_priv(priv, 1); 655 if (!priv) 656 return IRQ_NONE; 657 658 if (netif_running(priv->ndev)) { 659 napi_schedule(&priv->napi); 660 return IRQ_HANDLED; 661 } 662 return IRQ_NONE; 663 } 664 665 static int cpsw_poll(struct napi_struct *napi, int budget) 666 { 667 struct cpsw_priv *priv = napi_to_priv(napi); 668 int num_tx, num_rx; 669 670 num_tx = cpdma_chan_process(priv->txch, 128); 671 if (num_tx) 672 cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_TX); 673 674 num_rx = cpdma_chan_process(priv->rxch, budget); 675 if (num_rx < budget) { 676 struct cpsw_priv *prim_cpsw; 677 678 napi_complete(napi); 679 cpsw_intr_enable(priv); 680 cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_RX); 681 prim_cpsw = cpsw_get_slave_priv(priv, 0); 682 if (prim_cpsw->irq_enabled == false) { 683 prim_cpsw->irq_enabled = true; 684 cpsw_enable_irq(priv); 685 } 686 } 687 688 if (num_rx || num_tx) 689 cpsw_dbg(priv, intr, "poll %d rx, %d tx pkts\n", 690 num_rx, num_tx); 691 692 return num_rx; 693 } 694 695 static inline void soft_reset(const char *module, void __iomem *reg) 696 { 697 unsigned long timeout = jiffies + HZ; 698 699 __raw_writel(1, reg); 700 do { 701 cpu_relax(); 702 } while ((__raw_readl(reg) & 1) && time_after(timeout, jiffies)); 703 704 WARN(__raw_readl(reg) & 1, "failed to soft-reset %s\n", module); 705 } 706 707 #define mac_hi(mac) (((mac)[0] << 0) | ((mac)[1] << 8) | \ 708 ((mac)[2] << 16) | ((mac)[3] << 24)) 709 #define mac_lo(mac) (((mac)[4] << 0) | ((mac)[5] << 8)) 710 711 static void cpsw_set_slave_mac(struct cpsw_slave *slave, 712 struct cpsw_priv *priv) 713 { 714 slave_write(slave, mac_hi(priv->mac_addr), SA_HI); 715 slave_write(slave, mac_lo(priv->mac_addr), SA_LO); 716 } 717 718 static void _cpsw_adjust_link(struct cpsw_slave *slave, 719 struct cpsw_priv *priv, bool *link) 720 { 721 struct phy_device *phy = slave->phy; 722 u32 mac_control = 0; 723 u32 slave_port; 724 725 if (!phy) 726 return; 727 728 slave_port = cpsw_get_slave_port(priv, slave->slave_num); 729 730 if (phy->link) { 731 mac_control = priv->data.mac_control; 732 733 /* enable forwarding */ 734 cpsw_ale_control_set(priv->ale, slave_port, 735 ALE_PORT_STATE, ALE_PORT_STATE_FORWARD); 736 737 if (phy->speed == 1000) 738 mac_control |= BIT(7); /* GIGABITEN */ 739 if (phy->duplex) 740 mac_control |= BIT(0); /* FULLDUPLEXEN */ 741 742 /* set speed_in input in case RMII mode is used in 100Mbps */ 743 if (phy->speed == 100) 744 mac_control |= BIT(15); 745 746 *link = true; 747 } else { 748 mac_control = 0; 749 /* disable forwarding */ 750 cpsw_ale_control_set(priv->ale, slave_port, 751 ALE_PORT_STATE, ALE_PORT_STATE_DISABLE); 752 } 753 754 if (mac_control != slave->mac_control) { 755 phy_print_status(phy); 756 __raw_writel(mac_control, &slave->sliver->mac_control); 757 } 758 759 slave->mac_control = mac_control; 760 } 761 762 static void cpsw_adjust_link(struct net_device *ndev) 763 { 764 struct cpsw_priv *priv = netdev_priv(ndev); 765 bool link = false; 766 767 for_each_slave(priv, _cpsw_adjust_link, priv, &link); 768 769 if (link) { 770 netif_carrier_on(ndev); 771 if (netif_running(ndev)) 772 netif_wake_queue(ndev); 773 } else { 774 netif_carrier_off(ndev); 775 netif_stop_queue(ndev); 776 } 777 } 778 779 static int cpsw_get_coalesce(struct net_device *ndev, 780 struct ethtool_coalesce *coal) 781 { 782 struct cpsw_priv *priv = netdev_priv(ndev); 783 784 coal->rx_coalesce_usecs = priv->coal_intvl; 785 return 0; 786 } 787 788 static int cpsw_set_coalesce(struct net_device *ndev, 789 struct ethtool_coalesce *coal) 790 { 791 struct cpsw_priv *priv = netdev_priv(ndev); 792 u32 int_ctrl; 793 u32 num_interrupts = 0; 794 u32 prescale = 0; 795 u32 addnl_dvdr = 1; 796 u32 coal_intvl = 0; 797 798 if (!coal->rx_coalesce_usecs) 799 return -EINVAL; 800 801 coal_intvl = coal->rx_coalesce_usecs; 802 803 int_ctrl = readl(&priv->wr_regs->int_control); 804 prescale = priv->bus_freq_mhz * 4; 805 806 if (coal_intvl < CPSW_CMINTMIN_INTVL) 807 coal_intvl = CPSW_CMINTMIN_INTVL; 808 809 if (coal_intvl > CPSW_CMINTMAX_INTVL) { 810 /* Interrupt pacer works with 4us Pulse, we can 811 * throttle further by dilating the 4us pulse. 812 */ 813 addnl_dvdr = CPSW_INTPRESCALE_MASK / prescale; 814 815 if (addnl_dvdr > 1) { 816 prescale *= addnl_dvdr; 817 if (coal_intvl > (CPSW_CMINTMAX_INTVL * addnl_dvdr)) 818 coal_intvl = (CPSW_CMINTMAX_INTVL 819 * addnl_dvdr); 820 } else { 821 addnl_dvdr = 1; 822 coal_intvl = CPSW_CMINTMAX_INTVL; 823 } 824 } 825 826 num_interrupts = (1000 * addnl_dvdr) / coal_intvl; 827 writel(num_interrupts, &priv->wr_regs->rx_imax); 828 writel(num_interrupts, &priv->wr_regs->tx_imax); 829 830 int_ctrl |= CPSW_INTPACEEN; 831 int_ctrl &= (~CPSW_INTPRESCALE_MASK); 832 int_ctrl |= (prescale & CPSW_INTPRESCALE_MASK); 833 writel(int_ctrl, &priv->wr_regs->int_control); 834 835 cpsw_notice(priv, timer, "Set coalesce to %d usecs.\n", coal_intvl); 836 if (priv->data.dual_emac) { 837 int i; 838 839 for (i = 0; i < priv->data.slaves; i++) { 840 priv = netdev_priv(priv->slaves[i].ndev); 841 priv->coal_intvl = coal_intvl; 842 } 843 } else { 844 priv->coal_intvl = coal_intvl; 845 } 846 847 return 0; 848 } 849 850 static int cpsw_get_sset_count(struct net_device *ndev, int sset) 851 { 852 switch (sset) { 853 case ETH_SS_STATS: 854 return CPSW_STATS_LEN; 855 default: 856 return -EOPNOTSUPP; 857 } 858 } 859 860 static void cpsw_get_strings(struct net_device *ndev, u32 stringset, u8 *data) 861 { 862 u8 *p = data; 863 int i; 864 865 switch (stringset) { 866 case ETH_SS_STATS: 867 for (i = 0; i < CPSW_STATS_LEN; i++) { 868 memcpy(p, cpsw_gstrings_stats[i].stat_string, 869 ETH_GSTRING_LEN); 870 p += ETH_GSTRING_LEN; 871 } 872 break; 873 } 874 } 875 876 static void cpsw_get_ethtool_stats(struct net_device *ndev, 877 struct ethtool_stats *stats, u64 *data) 878 { 879 struct cpsw_priv *priv = netdev_priv(ndev); 880 struct cpdma_chan_stats rx_stats; 881 struct cpdma_chan_stats tx_stats; 882 u32 val; 883 u8 *p; 884 int i; 885 886 /* Collect Davinci CPDMA stats for Rx and Tx Channel */ 887 cpdma_chan_get_stats(priv->rxch, &rx_stats); 888 cpdma_chan_get_stats(priv->txch, &tx_stats); 889 890 for (i = 0; i < CPSW_STATS_LEN; i++) { 891 switch (cpsw_gstrings_stats[i].type) { 892 case CPSW_STATS: 893 val = readl(priv->hw_stats + 894 cpsw_gstrings_stats[i].stat_offset); 895 data[i] = val; 896 break; 897 898 case CPDMA_RX_STATS: 899 p = (u8 *)&rx_stats + 900 cpsw_gstrings_stats[i].stat_offset; 901 data[i] = *(u32 *)p; 902 break; 903 904 case CPDMA_TX_STATS: 905 p = (u8 *)&tx_stats + 906 cpsw_gstrings_stats[i].stat_offset; 907 data[i] = *(u32 *)p; 908 break; 909 } 910 } 911 } 912 913 static inline int __show_stat(char *buf, int maxlen, const char *name, u32 val) 914 { 915 static char *leader = "........................................"; 916 917 if (!val) 918 return 0; 919 else 920 return snprintf(buf, maxlen, "%s %s %10d\n", name, 921 leader + strlen(name), val); 922 } 923 924 static int cpsw_common_res_usage_state(struct cpsw_priv *priv) 925 { 926 u32 i; 927 u32 usage_count = 0; 928 929 if (!priv->data.dual_emac) 930 return 0; 931 932 for (i = 0; i < priv->data.slaves; i++) 933 if (priv->slaves[i].open_stat) 934 usage_count++; 935 936 return usage_count; 937 } 938 939 static inline int cpsw_tx_packet_submit(struct net_device *ndev, 940 struct cpsw_priv *priv, struct sk_buff *skb) 941 { 942 if (!priv->data.dual_emac) 943 return cpdma_chan_submit(priv->txch, skb, skb->data, 944 skb->len, 0); 945 946 if (ndev == cpsw_get_slave_ndev(priv, 0)) 947 return cpdma_chan_submit(priv->txch, skb, skb->data, 948 skb->len, 1); 949 else 950 return cpdma_chan_submit(priv->txch, skb, skb->data, 951 skb->len, 2); 952 } 953 954 static inline void cpsw_add_dual_emac_def_ale_entries( 955 struct cpsw_priv *priv, struct cpsw_slave *slave, 956 u32 slave_port) 957 { 958 u32 port_mask = 1 << slave_port | 1 << priv->host_port; 959 960 if (priv->version == CPSW_VERSION_1) 961 slave_write(slave, slave->port_vlan, CPSW1_PORT_VLAN); 962 else 963 slave_write(slave, slave->port_vlan, CPSW2_PORT_VLAN); 964 cpsw_ale_add_vlan(priv->ale, slave->port_vlan, port_mask, 965 port_mask, port_mask, 0); 966 cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast, 967 port_mask, ALE_VLAN, slave->port_vlan, 0); 968 cpsw_ale_add_ucast(priv->ale, priv->mac_addr, 969 priv->host_port, ALE_VLAN, slave->port_vlan); 970 } 971 972 static void cpsw_slave_open(struct cpsw_slave *slave, struct cpsw_priv *priv) 973 { 974 char name[32]; 975 u32 slave_port; 976 977 sprintf(name, "slave-%d", slave->slave_num); 978 979 soft_reset(name, &slave->sliver->soft_reset); 980 981 /* setup priority mapping */ 982 __raw_writel(RX_PRIORITY_MAPPING, &slave->sliver->rx_pri_map); 983 984 switch (priv->version) { 985 case CPSW_VERSION_1: 986 slave_write(slave, TX_PRIORITY_MAPPING, CPSW1_TX_PRI_MAP); 987 break; 988 case CPSW_VERSION_2: 989 case CPSW_VERSION_3: 990 case CPSW_VERSION_4: 991 slave_write(slave, TX_PRIORITY_MAPPING, CPSW2_TX_PRI_MAP); 992 break; 993 } 994 995 /* setup max packet size, and mac address */ 996 __raw_writel(priv->rx_packet_max, &slave->sliver->rx_maxlen); 997 cpsw_set_slave_mac(slave, priv); 998 999 slave->mac_control = 0; /* no link yet */ 1000 1001 slave_port = cpsw_get_slave_port(priv, slave->slave_num); 1002 1003 if (priv->data.dual_emac) 1004 cpsw_add_dual_emac_def_ale_entries(priv, slave, slave_port); 1005 else 1006 cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast, 1007 1 << slave_port, 0, 0, ALE_MCAST_FWD_2); 1008 1009 slave->phy = phy_connect(priv->ndev, slave->data->phy_id, 1010 &cpsw_adjust_link, slave->data->phy_if); 1011 if (IS_ERR(slave->phy)) { 1012 dev_err(priv->dev, "phy %s not found on slave %d\n", 1013 slave->data->phy_id, slave->slave_num); 1014 slave->phy = NULL; 1015 } else { 1016 dev_info(priv->dev, "phy found : id is : 0x%x\n", 1017 slave->phy->phy_id); 1018 phy_start(slave->phy); 1019 } 1020 } 1021 1022 static inline void cpsw_add_default_vlan(struct cpsw_priv *priv) 1023 { 1024 const int vlan = priv->data.default_vlan; 1025 const int port = priv->host_port; 1026 u32 reg; 1027 int i; 1028 1029 reg = (priv->version == CPSW_VERSION_1) ? CPSW1_PORT_VLAN : 1030 CPSW2_PORT_VLAN; 1031 1032 writel(vlan, &priv->host_port_regs->port_vlan); 1033 1034 for (i = 0; i < priv->data.slaves; i++) 1035 slave_write(priv->slaves + i, vlan, reg); 1036 1037 cpsw_ale_add_vlan(priv->ale, vlan, ALE_ALL_PORTS << port, 1038 ALE_ALL_PORTS << port, ALE_ALL_PORTS << port, 1039 (ALE_PORT_1 | ALE_PORT_2) << port); 1040 } 1041 1042 static void cpsw_init_host_port(struct cpsw_priv *priv) 1043 { 1044 u32 control_reg; 1045 u32 fifo_mode; 1046 1047 /* soft reset the controller and initialize ale */ 1048 soft_reset("cpsw", &priv->regs->soft_reset); 1049 cpsw_ale_start(priv->ale); 1050 1051 /* switch to vlan unaware mode */ 1052 cpsw_ale_control_set(priv->ale, priv->host_port, ALE_VLAN_AWARE, 1053 CPSW_ALE_VLAN_AWARE); 1054 control_reg = readl(&priv->regs->control); 1055 control_reg |= CPSW_VLAN_AWARE; 1056 writel(control_reg, &priv->regs->control); 1057 fifo_mode = (priv->data.dual_emac) ? CPSW_FIFO_DUAL_MAC_MODE : 1058 CPSW_FIFO_NORMAL_MODE; 1059 writel(fifo_mode, &priv->host_port_regs->tx_in_ctl); 1060 1061 /* setup host port priority mapping */ 1062 __raw_writel(CPDMA_TX_PRIORITY_MAP, 1063 &priv->host_port_regs->cpdma_tx_pri_map); 1064 __raw_writel(0, &priv->host_port_regs->cpdma_rx_chan_map); 1065 1066 cpsw_ale_control_set(priv->ale, priv->host_port, 1067 ALE_PORT_STATE, ALE_PORT_STATE_FORWARD); 1068 1069 if (!priv->data.dual_emac) { 1070 cpsw_ale_add_ucast(priv->ale, priv->mac_addr, priv->host_port, 1071 0, 0); 1072 cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast, 1073 1 << priv->host_port, 0, 0, ALE_MCAST_FWD_2); 1074 } 1075 } 1076 1077 static void cpsw_slave_stop(struct cpsw_slave *slave, struct cpsw_priv *priv) 1078 { 1079 if (!slave->phy) 1080 return; 1081 phy_stop(slave->phy); 1082 phy_disconnect(slave->phy); 1083 slave->phy = NULL; 1084 } 1085 1086 static int cpsw_ndo_open(struct net_device *ndev) 1087 { 1088 struct cpsw_priv *priv = netdev_priv(ndev); 1089 struct cpsw_priv *prim_cpsw; 1090 int i, ret; 1091 u32 reg; 1092 1093 if (!cpsw_common_res_usage_state(priv)) 1094 cpsw_intr_disable(priv); 1095 netif_carrier_off(ndev); 1096 1097 pm_runtime_get_sync(&priv->pdev->dev); 1098 1099 reg = priv->version; 1100 1101 dev_info(priv->dev, "initializing cpsw version %d.%d (%d)\n", 1102 CPSW_MAJOR_VERSION(reg), CPSW_MINOR_VERSION(reg), 1103 CPSW_RTL_VERSION(reg)); 1104 1105 /* initialize host and slave ports */ 1106 if (!cpsw_common_res_usage_state(priv)) 1107 cpsw_init_host_port(priv); 1108 for_each_slave(priv, cpsw_slave_open, priv); 1109 1110 /* Add default VLAN */ 1111 if (!priv->data.dual_emac) 1112 cpsw_add_default_vlan(priv); 1113 1114 if (!cpsw_common_res_usage_state(priv)) { 1115 /* setup tx dma to fixed prio and zero offset */ 1116 cpdma_control_set(priv->dma, CPDMA_TX_PRIO_FIXED, 1); 1117 cpdma_control_set(priv->dma, CPDMA_RX_BUFFER_OFFSET, 0); 1118 1119 /* disable priority elevation */ 1120 __raw_writel(0, &priv->regs->ptype); 1121 1122 /* enable statistics collection only on all ports */ 1123 __raw_writel(0x7, &priv->regs->stat_port_en); 1124 1125 if (WARN_ON(!priv->data.rx_descs)) 1126 priv->data.rx_descs = 128; 1127 1128 for (i = 0; i < priv->data.rx_descs; i++) { 1129 struct sk_buff *skb; 1130 1131 ret = -ENOMEM; 1132 skb = __netdev_alloc_skb_ip_align(priv->ndev, 1133 priv->rx_packet_max, GFP_KERNEL); 1134 if (!skb) 1135 goto err_cleanup; 1136 ret = cpdma_chan_submit(priv->rxch, skb, skb->data, 1137 skb_tailroom(skb), 0); 1138 if (ret < 0) { 1139 kfree_skb(skb); 1140 goto err_cleanup; 1141 } 1142 } 1143 /* continue even if we didn't manage to submit all 1144 * receive descs 1145 */ 1146 cpsw_info(priv, ifup, "submitted %d rx descriptors\n", i); 1147 } 1148 1149 /* Enable Interrupt pacing if configured */ 1150 if (priv->coal_intvl != 0) { 1151 struct ethtool_coalesce coal; 1152 1153 coal.rx_coalesce_usecs = (priv->coal_intvl << 4); 1154 cpsw_set_coalesce(ndev, &coal); 1155 } 1156 1157 prim_cpsw = cpsw_get_slave_priv(priv, 0); 1158 if (prim_cpsw->irq_enabled == false) { 1159 if ((priv == prim_cpsw) || !netif_running(prim_cpsw->ndev)) { 1160 prim_cpsw->irq_enabled = true; 1161 cpsw_enable_irq(prim_cpsw); 1162 } 1163 } 1164 1165 napi_enable(&priv->napi); 1166 cpdma_ctlr_start(priv->dma); 1167 cpsw_intr_enable(priv); 1168 cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_RX); 1169 cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_TX); 1170 1171 if (priv->data.dual_emac) 1172 priv->slaves[priv->emac_port].open_stat = true; 1173 return 0; 1174 1175 err_cleanup: 1176 cpdma_ctlr_stop(priv->dma); 1177 for_each_slave(priv, cpsw_slave_stop, priv); 1178 pm_runtime_put_sync(&priv->pdev->dev); 1179 netif_carrier_off(priv->ndev); 1180 return ret; 1181 } 1182 1183 static int cpsw_ndo_stop(struct net_device *ndev) 1184 { 1185 struct cpsw_priv *priv = netdev_priv(ndev); 1186 1187 cpsw_info(priv, ifdown, "shutting down cpsw device\n"); 1188 netif_stop_queue(priv->ndev); 1189 napi_disable(&priv->napi); 1190 netif_carrier_off(priv->ndev); 1191 1192 if (cpsw_common_res_usage_state(priv) <= 1) { 1193 cpsw_intr_disable(priv); 1194 cpdma_ctlr_int_ctrl(priv->dma, false); 1195 cpdma_ctlr_stop(priv->dma); 1196 cpsw_ale_stop(priv->ale); 1197 } 1198 for_each_slave(priv, cpsw_slave_stop, priv); 1199 pm_runtime_put_sync(&priv->pdev->dev); 1200 if (priv->data.dual_emac) 1201 priv->slaves[priv->emac_port].open_stat = false; 1202 return 0; 1203 } 1204 1205 static netdev_tx_t cpsw_ndo_start_xmit(struct sk_buff *skb, 1206 struct net_device *ndev) 1207 { 1208 struct cpsw_priv *priv = netdev_priv(ndev); 1209 int ret; 1210 1211 ndev->trans_start = jiffies; 1212 1213 if (skb_padto(skb, CPSW_MIN_PACKET_SIZE)) { 1214 cpsw_err(priv, tx_err, "packet pad failed\n"); 1215 priv->stats.tx_dropped++; 1216 return NETDEV_TX_OK; 1217 } 1218 1219 if (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP && 1220 priv->cpts->tx_enable) 1221 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 1222 1223 skb_tx_timestamp(skb); 1224 1225 ret = cpsw_tx_packet_submit(ndev, priv, skb); 1226 if (unlikely(ret != 0)) { 1227 cpsw_err(priv, tx_err, "desc submit failed\n"); 1228 goto fail; 1229 } 1230 1231 /* If there is no more tx desc left free then we need to 1232 * tell the kernel to stop sending us tx frames. 1233 */ 1234 if (unlikely(!cpdma_check_free_tx_desc(priv->txch))) 1235 netif_stop_queue(ndev); 1236 1237 return NETDEV_TX_OK; 1238 fail: 1239 priv->stats.tx_dropped++; 1240 netif_stop_queue(ndev); 1241 return NETDEV_TX_BUSY; 1242 } 1243 1244 static void cpsw_ndo_change_rx_flags(struct net_device *ndev, int flags) 1245 { 1246 /* 1247 * The switch cannot operate in promiscuous mode without substantial 1248 * headache. For promiscuous mode to work, we would need to put the 1249 * ALE in bypass mode and route all traffic to the host port. 1250 * Subsequently, the host will need to operate as a "bridge", learn, 1251 * and flood as needed. For now, we simply complain here and 1252 * do nothing about it :-) 1253 */ 1254 if ((flags & IFF_PROMISC) && (ndev->flags & IFF_PROMISC)) 1255 dev_err(&ndev->dev, "promiscuity ignored!\n"); 1256 1257 /* 1258 * The switch cannot filter multicast traffic unless it is configured 1259 * in "VLAN Aware" mode. Unfortunately, VLAN awareness requires a 1260 * whole bunch of additional logic that this driver does not implement 1261 * at present. 1262 */ 1263 if ((flags & IFF_ALLMULTI) && !(ndev->flags & IFF_ALLMULTI)) 1264 dev_err(&ndev->dev, "multicast traffic cannot be filtered!\n"); 1265 } 1266 1267 #ifdef CONFIG_TI_CPTS 1268 1269 static void cpsw_hwtstamp_v1(struct cpsw_priv *priv) 1270 { 1271 struct cpsw_slave *slave = &priv->slaves[priv->data.active_slave]; 1272 u32 ts_en, seq_id; 1273 1274 if (!priv->cpts->tx_enable && !priv->cpts->rx_enable) { 1275 slave_write(slave, 0, CPSW1_TS_CTL); 1276 return; 1277 } 1278 1279 seq_id = (30 << CPSW_V1_SEQ_ID_OFS_SHIFT) | ETH_P_1588; 1280 ts_en = EVENT_MSG_BITS << CPSW_V1_MSG_TYPE_OFS; 1281 1282 if (priv->cpts->tx_enable) 1283 ts_en |= CPSW_V1_TS_TX_EN; 1284 1285 if (priv->cpts->rx_enable) 1286 ts_en |= CPSW_V1_TS_RX_EN; 1287 1288 slave_write(slave, ts_en, CPSW1_TS_CTL); 1289 slave_write(slave, seq_id, CPSW1_TS_SEQ_LTYPE); 1290 } 1291 1292 static void cpsw_hwtstamp_v2(struct cpsw_priv *priv) 1293 { 1294 struct cpsw_slave *slave; 1295 u32 ctrl, mtype; 1296 1297 if (priv->data.dual_emac) 1298 slave = &priv->slaves[priv->emac_port]; 1299 else 1300 slave = &priv->slaves[priv->data.active_slave]; 1301 1302 ctrl = slave_read(slave, CPSW2_CONTROL); 1303 ctrl &= ~CTRL_ALL_TS_MASK; 1304 1305 if (priv->cpts->tx_enable) 1306 ctrl |= CTRL_TX_TS_BITS; 1307 1308 if (priv->cpts->rx_enable) 1309 ctrl |= CTRL_RX_TS_BITS; 1310 1311 mtype = (30 << TS_SEQ_ID_OFFSET_SHIFT) | EVENT_MSG_BITS; 1312 1313 slave_write(slave, mtype, CPSW2_TS_SEQ_MTYPE); 1314 slave_write(slave, ctrl, CPSW2_CONTROL); 1315 __raw_writel(ETH_P_1588, &priv->regs->ts_ltype); 1316 } 1317 1318 static int cpsw_hwtstamp_ioctl(struct net_device *dev, struct ifreq *ifr) 1319 { 1320 struct cpsw_priv *priv = netdev_priv(dev); 1321 struct cpts *cpts = priv->cpts; 1322 struct hwtstamp_config cfg; 1323 1324 if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg))) 1325 return -EFAULT; 1326 1327 /* reserved for future extensions */ 1328 if (cfg.flags) 1329 return -EINVAL; 1330 1331 switch (cfg.tx_type) { 1332 case HWTSTAMP_TX_OFF: 1333 cpts->tx_enable = 0; 1334 break; 1335 case HWTSTAMP_TX_ON: 1336 cpts->tx_enable = 1; 1337 break; 1338 default: 1339 return -ERANGE; 1340 } 1341 1342 switch (cfg.rx_filter) { 1343 case HWTSTAMP_FILTER_NONE: 1344 cpts->rx_enable = 0; 1345 break; 1346 case HWTSTAMP_FILTER_ALL: 1347 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: 1348 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: 1349 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: 1350 return -ERANGE; 1351 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: 1352 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 1353 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 1354 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: 1355 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: 1356 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: 1357 case HWTSTAMP_FILTER_PTP_V2_EVENT: 1358 case HWTSTAMP_FILTER_PTP_V2_SYNC: 1359 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 1360 cpts->rx_enable = 1; 1361 cfg.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT; 1362 break; 1363 default: 1364 return -ERANGE; 1365 } 1366 1367 switch (priv->version) { 1368 case CPSW_VERSION_1: 1369 cpsw_hwtstamp_v1(priv); 1370 break; 1371 case CPSW_VERSION_2: 1372 cpsw_hwtstamp_v2(priv); 1373 break; 1374 default: 1375 return -ENOTSUPP; 1376 } 1377 1378 return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0; 1379 } 1380 1381 #endif /*CONFIG_TI_CPTS*/ 1382 1383 static int cpsw_ndo_ioctl(struct net_device *dev, struct ifreq *req, int cmd) 1384 { 1385 struct cpsw_priv *priv = netdev_priv(dev); 1386 struct mii_ioctl_data *data = if_mii(req); 1387 int slave_no = cpsw_slave_index(priv); 1388 1389 if (!netif_running(dev)) 1390 return -EINVAL; 1391 1392 switch (cmd) { 1393 #ifdef CONFIG_TI_CPTS 1394 case SIOCSHWTSTAMP: 1395 return cpsw_hwtstamp_ioctl(dev, req); 1396 #endif 1397 case SIOCGMIIPHY: 1398 data->phy_id = priv->slaves[slave_no].phy->addr; 1399 break; 1400 default: 1401 return -ENOTSUPP; 1402 } 1403 1404 return 0; 1405 } 1406 1407 static void cpsw_ndo_tx_timeout(struct net_device *ndev) 1408 { 1409 struct cpsw_priv *priv = netdev_priv(ndev); 1410 1411 cpsw_err(priv, tx_err, "transmit timeout, restarting dma\n"); 1412 priv->stats.tx_errors++; 1413 cpsw_intr_disable(priv); 1414 cpdma_ctlr_int_ctrl(priv->dma, false); 1415 cpdma_chan_stop(priv->txch); 1416 cpdma_chan_start(priv->txch); 1417 cpdma_ctlr_int_ctrl(priv->dma, true); 1418 cpsw_intr_enable(priv); 1419 cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_RX); 1420 cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_TX); 1421 1422 } 1423 1424 static int cpsw_ndo_set_mac_address(struct net_device *ndev, void *p) 1425 { 1426 struct cpsw_priv *priv = netdev_priv(ndev); 1427 struct sockaddr *addr = (struct sockaddr *)p; 1428 int flags = 0; 1429 u16 vid = 0; 1430 1431 if (!is_valid_ether_addr(addr->sa_data)) 1432 return -EADDRNOTAVAIL; 1433 1434 if (priv->data.dual_emac) { 1435 vid = priv->slaves[priv->emac_port].port_vlan; 1436 flags = ALE_VLAN; 1437 } 1438 1439 cpsw_ale_del_ucast(priv->ale, priv->mac_addr, priv->host_port, 1440 flags, vid); 1441 cpsw_ale_add_ucast(priv->ale, addr->sa_data, priv->host_port, 1442 flags, vid); 1443 1444 memcpy(priv->mac_addr, addr->sa_data, ETH_ALEN); 1445 memcpy(ndev->dev_addr, priv->mac_addr, ETH_ALEN); 1446 for_each_slave(priv, cpsw_set_slave_mac, priv); 1447 1448 return 0; 1449 } 1450 1451 static struct net_device_stats *cpsw_ndo_get_stats(struct net_device *ndev) 1452 { 1453 struct cpsw_priv *priv = netdev_priv(ndev); 1454 return &priv->stats; 1455 } 1456 1457 #ifdef CONFIG_NET_POLL_CONTROLLER 1458 static void cpsw_ndo_poll_controller(struct net_device *ndev) 1459 { 1460 struct cpsw_priv *priv = netdev_priv(ndev); 1461 1462 cpsw_intr_disable(priv); 1463 cpdma_ctlr_int_ctrl(priv->dma, false); 1464 cpsw_interrupt(ndev->irq, priv); 1465 cpdma_ctlr_int_ctrl(priv->dma, true); 1466 cpsw_intr_enable(priv); 1467 cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_RX); 1468 cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_TX); 1469 1470 } 1471 #endif 1472 1473 static inline int cpsw_add_vlan_ale_entry(struct cpsw_priv *priv, 1474 unsigned short vid) 1475 { 1476 int ret; 1477 1478 ret = cpsw_ale_add_vlan(priv->ale, vid, 1479 ALE_ALL_PORTS << priv->host_port, 1480 0, ALE_ALL_PORTS << priv->host_port, 1481 (ALE_PORT_1 | ALE_PORT_2) << priv->host_port); 1482 if (ret != 0) 1483 return ret; 1484 1485 ret = cpsw_ale_add_ucast(priv->ale, priv->mac_addr, 1486 priv->host_port, ALE_VLAN, vid); 1487 if (ret != 0) 1488 goto clean_vid; 1489 1490 ret = cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast, 1491 ALE_ALL_PORTS << priv->host_port, 1492 ALE_VLAN, vid, 0); 1493 if (ret != 0) 1494 goto clean_vlan_ucast; 1495 return 0; 1496 1497 clean_vlan_ucast: 1498 cpsw_ale_del_ucast(priv->ale, priv->mac_addr, 1499 priv->host_port, ALE_VLAN, vid); 1500 clean_vid: 1501 cpsw_ale_del_vlan(priv->ale, vid, 0); 1502 return ret; 1503 } 1504 1505 static int cpsw_ndo_vlan_rx_add_vid(struct net_device *ndev, 1506 __be16 proto, u16 vid) 1507 { 1508 struct cpsw_priv *priv = netdev_priv(ndev); 1509 1510 if (vid == priv->data.default_vlan) 1511 return 0; 1512 1513 dev_info(priv->dev, "Adding vlanid %d to vlan filter\n", vid); 1514 return cpsw_add_vlan_ale_entry(priv, vid); 1515 } 1516 1517 static int cpsw_ndo_vlan_rx_kill_vid(struct net_device *ndev, 1518 __be16 proto, u16 vid) 1519 { 1520 struct cpsw_priv *priv = netdev_priv(ndev); 1521 int ret; 1522 1523 if (vid == priv->data.default_vlan) 1524 return 0; 1525 1526 dev_info(priv->dev, "removing vlanid %d from vlan filter\n", vid); 1527 ret = cpsw_ale_del_vlan(priv->ale, vid, 0); 1528 if (ret != 0) 1529 return ret; 1530 1531 ret = cpsw_ale_del_ucast(priv->ale, priv->mac_addr, 1532 priv->host_port, ALE_VLAN, vid); 1533 if (ret != 0) 1534 return ret; 1535 1536 return cpsw_ale_del_mcast(priv->ale, priv->ndev->broadcast, 1537 0, ALE_VLAN, vid); 1538 } 1539 1540 static const struct net_device_ops cpsw_netdev_ops = { 1541 .ndo_open = cpsw_ndo_open, 1542 .ndo_stop = cpsw_ndo_stop, 1543 .ndo_start_xmit = cpsw_ndo_start_xmit, 1544 .ndo_change_rx_flags = cpsw_ndo_change_rx_flags, 1545 .ndo_set_mac_address = cpsw_ndo_set_mac_address, 1546 .ndo_do_ioctl = cpsw_ndo_ioctl, 1547 .ndo_validate_addr = eth_validate_addr, 1548 .ndo_change_mtu = eth_change_mtu, 1549 .ndo_tx_timeout = cpsw_ndo_tx_timeout, 1550 .ndo_get_stats = cpsw_ndo_get_stats, 1551 .ndo_set_rx_mode = cpsw_ndo_set_rx_mode, 1552 #ifdef CONFIG_NET_POLL_CONTROLLER 1553 .ndo_poll_controller = cpsw_ndo_poll_controller, 1554 #endif 1555 .ndo_vlan_rx_add_vid = cpsw_ndo_vlan_rx_add_vid, 1556 .ndo_vlan_rx_kill_vid = cpsw_ndo_vlan_rx_kill_vid, 1557 }; 1558 1559 static void cpsw_get_drvinfo(struct net_device *ndev, 1560 struct ethtool_drvinfo *info) 1561 { 1562 struct cpsw_priv *priv = netdev_priv(ndev); 1563 1564 strlcpy(info->driver, "TI CPSW Driver v1.0", sizeof(info->driver)); 1565 strlcpy(info->version, "1.0", sizeof(info->version)); 1566 strlcpy(info->bus_info, priv->pdev->name, sizeof(info->bus_info)); 1567 } 1568 1569 static u32 cpsw_get_msglevel(struct net_device *ndev) 1570 { 1571 struct cpsw_priv *priv = netdev_priv(ndev); 1572 return priv->msg_enable; 1573 } 1574 1575 static void cpsw_set_msglevel(struct net_device *ndev, u32 value) 1576 { 1577 struct cpsw_priv *priv = netdev_priv(ndev); 1578 priv->msg_enable = value; 1579 } 1580 1581 static int cpsw_get_ts_info(struct net_device *ndev, 1582 struct ethtool_ts_info *info) 1583 { 1584 #ifdef CONFIG_TI_CPTS 1585 struct cpsw_priv *priv = netdev_priv(ndev); 1586 1587 info->so_timestamping = 1588 SOF_TIMESTAMPING_TX_HARDWARE | 1589 SOF_TIMESTAMPING_TX_SOFTWARE | 1590 SOF_TIMESTAMPING_RX_HARDWARE | 1591 SOF_TIMESTAMPING_RX_SOFTWARE | 1592 SOF_TIMESTAMPING_SOFTWARE | 1593 SOF_TIMESTAMPING_RAW_HARDWARE; 1594 info->phc_index = priv->cpts->phc_index; 1595 info->tx_types = 1596 (1 << HWTSTAMP_TX_OFF) | 1597 (1 << HWTSTAMP_TX_ON); 1598 info->rx_filters = 1599 (1 << HWTSTAMP_FILTER_NONE) | 1600 (1 << HWTSTAMP_FILTER_PTP_V2_EVENT); 1601 #else 1602 info->so_timestamping = 1603 SOF_TIMESTAMPING_TX_SOFTWARE | 1604 SOF_TIMESTAMPING_RX_SOFTWARE | 1605 SOF_TIMESTAMPING_SOFTWARE; 1606 info->phc_index = -1; 1607 info->tx_types = 0; 1608 info->rx_filters = 0; 1609 #endif 1610 return 0; 1611 } 1612 1613 static int cpsw_get_settings(struct net_device *ndev, 1614 struct ethtool_cmd *ecmd) 1615 { 1616 struct cpsw_priv *priv = netdev_priv(ndev); 1617 int slave_no = cpsw_slave_index(priv); 1618 1619 if (priv->slaves[slave_no].phy) 1620 return phy_ethtool_gset(priv->slaves[slave_no].phy, ecmd); 1621 else 1622 return -EOPNOTSUPP; 1623 } 1624 1625 static int cpsw_set_settings(struct net_device *ndev, struct ethtool_cmd *ecmd) 1626 { 1627 struct cpsw_priv *priv = netdev_priv(ndev); 1628 int slave_no = cpsw_slave_index(priv); 1629 1630 if (priv->slaves[slave_no].phy) 1631 return phy_ethtool_sset(priv->slaves[slave_no].phy, ecmd); 1632 else 1633 return -EOPNOTSUPP; 1634 } 1635 1636 static void cpsw_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol) 1637 { 1638 struct cpsw_priv *priv = netdev_priv(ndev); 1639 int slave_no = cpsw_slave_index(priv); 1640 1641 wol->supported = 0; 1642 wol->wolopts = 0; 1643 1644 if (priv->slaves[slave_no].phy) 1645 phy_ethtool_get_wol(priv->slaves[slave_no].phy, wol); 1646 } 1647 1648 static int cpsw_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol) 1649 { 1650 struct cpsw_priv *priv = netdev_priv(ndev); 1651 int slave_no = cpsw_slave_index(priv); 1652 1653 if (priv->slaves[slave_no].phy) 1654 return phy_ethtool_set_wol(priv->slaves[slave_no].phy, wol); 1655 else 1656 return -EOPNOTSUPP; 1657 } 1658 1659 static const struct ethtool_ops cpsw_ethtool_ops = { 1660 .get_drvinfo = cpsw_get_drvinfo, 1661 .get_msglevel = cpsw_get_msglevel, 1662 .set_msglevel = cpsw_set_msglevel, 1663 .get_link = ethtool_op_get_link, 1664 .get_ts_info = cpsw_get_ts_info, 1665 .get_settings = cpsw_get_settings, 1666 .set_settings = cpsw_set_settings, 1667 .get_coalesce = cpsw_get_coalesce, 1668 .set_coalesce = cpsw_set_coalesce, 1669 .get_sset_count = cpsw_get_sset_count, 1670 .get_strings = cpsw_get_strings, 1671 .get_ethtool_stats = cpsw_get_ethtool_stats, 1672 .get_wol = cpsw_get_wol, 1673 .set_wol = cpsw_set_wol, 1674 }; 1675 1676 static void cpsw_slave_init(struct cpsw_slave *slave, struct cpsw_priv *priv, 1677 u32 slave_reg_ofs, u32 sliver_reg_ofs) 1678 { 1679 void __iomem *regs = priv->regs; 1680 int slave_num = slave->slave_num; 1681 struct cpsw_slave_data *data = priv->data.slave_data + slave_num; 1682 1683 slave->data = data; 1684 slave->regs = regs + slave_reg_ofs; 1685 slave->sliver = regs + sliver_reg_ofs; 1686 slave->port_vlan = data->dual_emac_res_vlan; 1687 } 1688 1689 static int cpsw_probe_dt(struct cpsw_platform_data *data, 1690 struct platform_device *pdev) 1691 { 1692 struct device_node *node = pdev->dev.of_node; 1693 struct device_node *slave_node; 1694 int i = 0, ret; 1695 u32 prop; 1696 1697 if (!node) 1698 return -EINVAL; 1699 1700 if (of_property_read_u32(node, "slaves", &prop)) { 1701 pr_err("Missing slaves property in the DT.\n"); 1702 return -EINVAL; 1703 } 1704 data->slaves = prop; 1705 1706 if (of_property_read_u32(node, "active_slave", &prop)) { 1707 pr_err("Missing active_slave property in the DT.\n"); 1708 ret = -EINVAL; 1709 goto error_ret; 1710 } 1711 data->active_slave = prop; 1712 1713 if (of_property_read_u32(node, "cpts_clock_mult", &prop)) { 1714 pr_err("Missing cpts_clock_mult property in the DT.\n"); 1715 ret = -EINVAL; 1716 goto error_ret; 1717 } 1718 data->cpts_clock_mult = prop; 1719 1720 if (of_property_read_u32(node, "cpts_clock_shift", &prop)) { 1721 pr_err("Missing cpts_clock_shift property in the DT.\n"); 1722 ret = -EINVAL; 1723 goto error_ret; 1724 } 1725 data->cpts_clock_shift = prop; 1726 1727 data->slave_data = kcalloc(data->slaves, sizeof(struct cpsw_slave_data), 1728 GFP_KERNEL); 1729 if (!data->slave_data) 1730 return -EINVAL; 1731 1732 if (of_property_read_u32(node, "cpdma_channels", &prop)) { 1733 pr_err("Missing cpdma_channels property in the DT.\n"); 1734 ret = -EINVAL; 1735 goto error_ret; 1736 } 1737 data->channels = prop; 1738 1739 if (of_property_read_u32(node, "ale_entries", &prop)) { 1740 pr_err("Missing ale_entries property in the DT.\n"); 1741 ret = -EINVAL; 1742 goto error_ret; 1743 } 1744 data->ale_entries = prop; 1745 1746 if (of_property_read_u32(node, "bd_ram_size", &prop)) { 1747 pr_err("Missing bd_ram_size property in the DT.\n"); 1748 ret = -EINVAL; 1749 goto error_ret; 1750 } 1751 data->bd_ram_size = prop; 1752 1753 if (of_property_read_u32(node, "rx_descs", &prop)) { 1754 pr_err("Missing rx_descs property in the DT.\n"); 1755 ret = -EINVAL; 1756 goto error_ret; 1757 } 1758 data->rx_descs = prop; 1759 1760 if (of_property_read_u32(node, "mac_control", &prop)) { 1761 pr_err("Missing mac_control property in the DT.\n"); 1762 ret = -EINVAL; 1763 goto error_ret; 1764 } 1765 data->mac_control = prop; 1766 1767 if (of_property_read_bool(node, "dual_emac")) 1768 data->dual_emac = 1; 1769 1770 /* 1771 * Populate all the child nodes here... 1772 */ 1773 ret = of_platform_populate(node, NULL, NULL, &pdev->dev); 1774 /* We do not want to force this, as in some cases may not have child */ 1775 if (ret) 1776 pr_warn("Doesn't have any child node\n"); 1777 1778 for_each_child_of_node(node, slave_node) { 1779 struct cpsw_slave_data *slave_data = data->slave_data + i; 1780 const void *mac_addr = NULL; 1781 u32 phyid; 1782 int lenp; 1783 const __be32 *parp; 1784 struct device_node *mdio_node; 1785 struct platform_device *mdio; 1786 1787 /* This is no slave child node, continue */ 1788 if (strcmp(slave_node->name, "slave")) 1789 continue; 1790 1791 parp = of_get_property(slave_node, "phy_id", &lenp); 1792 if ((parp == NULL) || (lenp != (sizeof(void *) * 2))) { 1793 pr_err("Missing slave[%d] phy_id property\n", i); 1794 ret = -EINVAL; 1795 goto error_ret; 1796 } 1797 mdio_node = of_find_node_by_phandle(be32_to_cpup(parp)); 1798 phyid = be32_to_cpup(parp+1); 1799 mdio = of_find_device_by_node(mdio_node); 1800 snprintf(slave_data->phy_id, sizeof(slave_data->phy_id), 1801 PHY_ID_FMT, mdio->name, phyid); 1802 1803 mac_addr = of_get_mac_address(slave_node); 1804 if (mac_addr) 1805 memcpy(slave_data->mac_addr, mac_addr, ETH_ALEN); 1806 1807 slave_data->phy_if = of_get_phy_mode(slave_node); 1808 1809 if (data->dual_emac) { 1810 if (of_property_read_u32(slave_node, "dual_emac_res_vlan", 1811 &prop)) { 1812 pr_err("Missing dual_emac_res_vlan in DT.\n"); 1813 slave_data->dual_emac_res_vlan = i+1; 1814 pr_err("Using %d as Reserved VLAN for %d slave\n", 1815 slave_data->dual_emac_res_vlan, i); 1816 } else { 1817 slave_data->dual_emac_res_vlan = prop; 1818 } 1819 } 1820 1821 i++; 1822 } 1823 1824 return 0; 1825 1826 error_ret: 1827 kfree(data->slave_data); 1828 return ret; 1829 } 1830 1831 static int cpsw_probe_dual_emac(struct platform_device *pdev, 1832 struct cpsw_priv *priv) 1833 { 1834 struct cpsw_platform_data *data = &priv->data; 1835 struct net_device *ndev; 1836 struct cpsw_priv *priv_sl2; 1837 int ret = 0, i; 1838 1839 ndev = alloc_etherdev(sizeof(struct cpsw_priv)); 1840 if (!ndev) { 1841 pr_err("cpsw: error allocating net_device\n"); 1842 return -ENOMEM; 1843 } 1844 1845 priv_sl2 = netdev_priv(ndev); 1846 spin_lock_init(&priv_sl2->lock); 1847 priv_sl2->data = *data; 1848 priv_sl2->pdev = pdev; 1849 priv_sl2->ndev = ndev; 1850 priv_sl2->dev = &ndev->dev; 1851 priv_sl2->msg_enable = netif_msg_init(debug_level, CPSW_DEBUG); 1852 priv_sl2->rx_packet_max = max(rx_packet_max, 128); 1853 1854 if (is_valid_ether_addr(data->slave_data[1].mac_addr)) { 1855 memcpy(priv_sl2->mac_addr, data->slave_data[1].mac_addr, 1856 ETH_ALEN); 1857 pr_info("cpsw: Detected MACID = %pM\n", priv_sl2->mac_addr); 1858 } else { 1859 random_ether_addr(priv_sl2->mac_addr); 1860 pr_info("cpsw: Random MACID = %pM\n", priv_sl2->mac_addr); 1861 } 1862 memcpy(ndev->dev_addr, priv_sl2->mac_addr, ETH_ALEN); 1863 1864 priv_sl2->slaves = priv->slaves; 1865 priv_sl2->clk = priv->clk; 1866 1867 priv_sl2->coal_intvl = 0; 1868 priv_sl2->bus_freq_mhz = priv->bus_freq_mhz; 1869 1870 priv_sl2->cpsw_res = priv->cpsw_res; 1871 priv_sl2->regs = priv->regs; 1872 priv_sl2->host_port = priv->host_port; 1873 priv_sl2->host_port_regs = priv->host_port_regs; 1874 priv_sl2->wr_regs = priv->wr_regs; 1875 priv_sl2->hw_stats = priv->hw_stats; 1876 priv_sl2->dma = priv->dma; 1877 priv_sl2->txch = priv->txch; 1878 priv_sl2->rxch = priv->rxch; 1879 priv_sl2->ale = priv->ale; 1880 priv_sl2->emac_port = 1; 1881 priv->slaves[1].ndev = ndev; 1882 priv_sl2->cpts = priv->cpts; 1883 priv_sl2->version = priv->version; 1884 1885 for (i = 0; i < priv->num_irqs; i++) { 1886 priv_sl2->irqs_table[i] = priv->irqs_table[i]; 1887 priv_sl2->num_irqs = priv->num_irqs; 1888 } 1889 ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER; 1890 1891 ndev->netdev_ops = &cpsw_netdev_ops; 1892 SET_ETHTOOL_OPS(ndev, &cpsw_ethtool_ops); 1893 netif_napi_add(ndev, &priv_sl2->napi, cpsw_poll, CPSW_POLL_WEIGHT); 1894 1895 /* register the network device */ 1896 SET_NETDEV_DEV(ndev, &pdev->dev); 1897 ret = register_netdev(ndev); 1898 if (ret) { 1899 pr_err("cpsw: error registering net device\n"); 1900 free_netdev(ndev); 1901 ret = -ENODEV; 1902 } 1903 1904 return ret; 1905 } 1906 1907 static int cpsw_probe(struct platform_device *pdev) 1908 { 1909 struct cpsw_platform_data *data; 1910 struct net_device *ndev; 1911 struct cpsw_priv *priv; 1912 struct cpdma_params dma_params; 1913 struct cpsw_ale_params ale_params; 1914 void __iomem *ss_regs, *wr_regs; 1915 struct resource *res; 1916 u32 slave_offset, sliver_offset, slave_size; 1917 int ret = 0, i, k = 0; 1918 1919 ndev = alloc_etherdev(sizeof(struct cpsw_priv)); 1920 if (!ndev) { 1921 pr_err("error allocating net_device\n"); 1922 return -ENOMEM; 1923 } 1924 1925 platform_set_drvdata(pdev, ndev); 1926 priv = netdev_priv(ndev); 1927 spin_lock_init(&priv->lock); 1928 priv->pdev = pdev; 1929 priv->ndev = ndev; 1930 priv->dev = &ndev->dev; 1931 priv->msg_enable = netif_msg_init(debug_level, CPSW_DEBUG); 1932 priv->rx_packet_max = max(rx_packet_max, 128); 1933 priv->cpts = devm_kzalloc(&pdev->dev, sizeof(struct cpts), GFP_KERNEL); 1934 priv->irq_enabled = true; 1935 if (!priv->cpts) { 1936 pr_err("error allocating cpts\n"); 1937 goto clean_ndev_ret; 1938 } 1939 1940 /* 1941 * This may be required here for child devices. 1942 */ 1943 pm_runtime_enable(&pdev->dev); 1944 1945 /* Select default pin state */ 1946 pinctrl_pm_select_default_state(&pdev->dev); 1947 1948 if (cpsw_probe_dt(&priv->data, pdev)) { 1949 pr_err("cpsw: platform data missing\n"); 1950 ret = -ENODEV; 1951 goto clean_ndev_ret; 1952 } 1953 data = &priv->data; 1954 1955 if (is_valid_ether_addr(data->slave_data[0].mac_addr)) { 1956 memcpy(priv->mac_addr, data->slave_data[0].mac_addr, ETH_ALEN); 1957 pr_info("Detected MACID = %pM\n", priv->mac_addr); 1958 } else { 1959 eth_random_addr(priv->mac_addr); 1960 pr_info("Random MACID = %pM\n", priv->mac_addr); 1961 } 1962 1963 memcpy(ndev->dev_addr, priv->mac_addr, ETH_ALEN); 1964 1965 priv->slaves = kzalloc(sizeof(struct cpsw_slave) * data->slaves, 1966 GFP_KERNEL); 1967 if (!priv->slaves) { 1968 ret = -EBUSY; 1969 goto clean_ndev_ret; 1970 } 1971 for (i = 0; i < data->slaves; i++) 1972 priv->slaves[i].slave_num = i; 1973 1974 priv->slaves[0].ndev = ndev; 1975 priv->emac_port = 0; 1976 1977 priv->clk = clk_get(&pdev->dev, "fck"); 1978 if (IS_ERR(priv->clk)) { 1979 dev_err(&pdev->dev, "fck is not found\n"); 1980 ret = -ENODEV; 1981 goto clean_slave_ret; 1982 } 1983 priv->coal_intvl = 0; 1984 priv->bus_freq_mhz = clk_get_rate(priv->clk) / 1000000; 1985 1986 priv->cpsw_res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1987 if (!priv->cpsw_res) { 1988 dev_err(priv->dev, "error getting i/o resource\n"); 1989 ret = -ENOENT; 1990 goto clean_clk_ret; 1991 } 1992 if (!request_mem_region(priv->cpsw_res->start, 1993 resource_size(priv->cpsw_res), ndev->name)) { 1994 dev_err(priv->dev, "failed request i/o region\n"); 1995 ret = -ENXIO; 1996 goto clean_clk_ret; 1997 } 1998 ss_regs = ioremap(priv->cpsw_res->start, resource_size(priv->cpsw_res)); 1999 if (!ss_regs) { 2000 dev_err(priv->dev, "unable to map i/o region\n"); 2001 goto clean_cpsw_iores_ret; 2002 } 2003 priv->regs = ss_regs; 2004 priv->version = __raw_readl(&priv->regs->id_ver); 2005 priv->host_port = HOST_PORT_NUM; 2006 2007 priv->cpsw_wr_res = platform_get_resource(pdev, IORESOURCE_MEM, 1); 2008 if (!priv->cpsw_wr_res) { 2009 dev_err(priv->dev, "error getting i/o resource\n"); 2010 ret = -ENOENT; 2011 goto clean_iomap_ret; 2012 } 2013 if (!request_mem_region(priv->cpsw_wr_res->start, 2014 resource_size(priv->cpsw_wr_res), ndev->name)) { 2015 dev_err(priv->dev, "failed request i/o region\n"); 2016 ret = -ENXIO; 2017 goto clean_iomap_ret; 2018 } 2019 wr_regs = ioremap(priv->cpsw_wr_res->start, 2020 resource_size(priv->cpsw_wr_res)); 2021 if (!wr_regs) { 2022 dev_err(priv->dev, "unable to map i/o region\n"); 2023 goto clean_cpsw_wr_iores_ret; 2024 } 2025 priv->wr_regs = wr_regs; 2026 2027 memset(&dma_params, 0, sizeof(dma_params)); 2028 memset(&ale_params, 0, sizeof(ale_params)); 2029 2030 switch (priv->version) { 2031 case CPSW_VERSION_1: 2032 priv->host_port_regs = ss_regs + CPSW1_HOST_PORT_OFFSET; 2033 priv->cpts->reg = ss_regs + CPSW1_CPTS_OFFSET; 2034 priv->hw_stats = ss_regs + CPSW1_HW_STATS; 2035 dma_params.dmaregs = ss_regs + CPSW1_CPDMA_OFFSET; 2036 dma_params.txhdp = ss_regs + CPSW1_STATERAM_OFFSET; 2037 ale_params.ale_regs = ss_regs + CPSW1_ALE_OFFSET; 2038 slave_offset = CPSW1_SLAVE_OFFSET; 2039 slave_size = CPSW1_SLAVE_SIZE; 2040 sliver_offset = CPSW1_SLIVER_OFFSET; 2041 dma_params.desc_mem_phys = 0; 2042 break; 2043 case CPSW_VERSION_2: 2044 case CPSW_VERSION_3: 2045 case CPSW_VERSION_4: 2046 priv->host_port_regs = ss_regs + CPSW2_HOST_PORT_OFFSET; 2047 priv->cpts->reg = ss_regs + CPSW2_CPTS_OFFSET; 2048 priv->hw_stats = ss_regs + CPSW2_HW_STATS; 2049 dma_params.dmaregs = ss_regs + CPSW2_CPDMA_OFFSET; 2050 dma_params.txhdp = ss_regs + CPSW2_STATERAM_OFFSET; 2051 ale_params.ale_regs = ss_regs + CPSW2_ALE_OFFSET; 2052 slave_offset = CPSW2_SLAVE_OFFSET; 2053 slave_size = CPSW2_SLAVE_SIZE; 2054 sliver_offset = CPSW2_SLIVER_OFFSET; 2055 dma_params.desc_mem_phys = 2056 (u32 __force) priv->cpsw_res->start + CPSW2_BD_OFFSET; 2057 break; 2058 default: 2059 dev_err(priv->dev, "unknown version 0x%08x\n", priv->version); 2060 ret = -ENODEV; 2061 goto clean_cpsw_wr_iores_ret; 2062 } 2063 for (i = 0; i < priv->data.slaves; i++) { 2064 struct cpsw_slave *slave = &priv->slaves[i]; 2065 cpsw_slave_init(slave, priv, slave_offset, sliver_offset); 2066 slave_offset += slave_size; 2067 sliver_offset += SLIVER_SIZE; 2068 } 2069 2070 dma_params.dev = &pdev->dev; 2071 dma_params.rxthresh = dma_params.dmaregs + CPDMA_RXTHRESH; 2072 dma_params.rxfree = dma_params.dmaregs + CPDMA_RXFREE; 2073 dma_params.rxhdp = dma_params.txhdp + CPDMA_RXHDP; 2074 dma_params.txcp = dma_params.txhdp + CPDMA_TXCP; 2075 dma_params.rxcp = dma_params.txhdp + CPDMA_RXCP; 2076 2077 dma_params.num_chan = data->channels; 2078 dma_params.has_soft_reset = true; 2079 dma_params.min_packet_size = CPSW_MIN_PACKET_SIZE; 2080 dma_params.desc_mem_size = data->bd_ram_size; 2081 dma_params.desc_align = 16; 2082 dma_params.has_ext_regs = true; 2083 dma_params.desc_hw_addr = dma_params.desc_mem_phys; 2084 2085 priv->dma = cpdma_ctlr_create(&dma_params); 2086 if (!priv->dma) { 2087 dev_err(priv->dev, "error initializing dma\n"); 2088 ret = -ENOMEM; 2089 goto clean_wr_iomap_ret; 2090 } 2091 2092 priv->txch = cpdma_chan_create(priv->dma, tx_chan_num(0), 2093 cpsw_tx_handler); 2094 priv->rxch = cpdma_chan_create(priv->dma, rx_chan_num(0), 2095 cpsw_rx_handler); 2096 2097 if (WARN_ON(!priv->txch || !priv->rxch)) { 2098 dev_err(priv->dev, "error initializing dma channels\n"); 2099 ret = -ENOMEM; 2100 goto clean_dma_ret; 2101 } 2102 2103 ale_params.dev = &ndev->dev; 2104 ale_params.ale_ageout = ale_ageout; 2105 ale_params.ale_entries = data->ale_entries; 2106 ale_params.ale_ports = data->slaves; 2107 2108 priv->ale = cpsw_ale_create(&ale_params); 2109 if (!priv->ale) { 2110 dev_err(priv->dev, "error initializing ale engine\n"); 2111 ret = -ENODEV; 2112 goto clean_dma_ret; 2113 } 2114 2115 ndev->irq = platform_get_irq(pdev, 0); 2116 if (ndev->irq < 0) { 2117 dev_err(priv->dev, "error getting irq resource\n"); 2118 ret = -ENOENT; 2119 goto clean_ale_ret; 2120 } 2121 2122 while ((res = platform_get_resource(priv->pdev, IORESOURCE_IRQ, k))) { 2123 for (i = res->start; i <= res->end; i++) { 2124 if (request_irq(i, cpsw_interrupt, 0, 2125 dev_name(&pdev->dev), priv)) { 2126 dev_err(priv->dev, "error attaching irq\n"); 2127 goto clean_ale_ret; 2128 } 2129 priv->irqs_table[k] = i; 2130 priv->num_irqs = k + 1; 2131 } 2132 k++; 2133 } 2134 2135 ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER; 2136 2137 ndev->netdev_ops = &cpsw_netdev_ops; 2138 SET_ETHTOOL_OPS(ndev, &cpsw_ethtool_ops); 2139 netif_napi_add(ndev, &priv->napi, cpsw_poll, CPSW_POLL_WEIGHT); 2140 2141 /* register the network device */ 2142 SET_NETDEV_DEV(ndev, &pdev->dev); 2143 ret = register_netdev(ndev); 2144 if (ret) { 2145 dev_err(priv->dev, "error registering net device\n"); 2146 ret = -ENODEV; 2147 goto clean_irq_ret; 2148 } 2149 2150 if (cpts_register(&pdev->dev, priv->cpts, 2151 data->cpts_clock_mult, data->cpts_clock_shift)) 2152 dev_err(priv->dev, "error registering cpts device\n"); 2153 2154 cpsw_notice(priv, probe, "initialized device (regs %x, irq %d)\n", 2155 priv->cpsw_res->start, ndev->irq); 2156 2157 if (priv->data.dual_emac) { 2158 ret = cpsw_probe_dual_emac(pdev, priv); 2159 if (ret) { 2160 cpsw_err(priv, probe, "error probe slave 2 emac interface\n"); 2161 goto clean_irq_ret; 2162 } 2163 } 2164 2165 return 0; 2166 2167 clean_irq_ret: 2168 for (i = 0; i < priv->num_irqs; i++) 2169 free_irq(priv->irqs_table[i], priv); 2170 clean_ale_ret: 2171 cpsw_ale_destroy(priv->ale); 2172 clean_dma_ret: 2173 cpdma_chan_destroy(priv->txch); 2174 cpdma_chan_destroy(priv->rxch); 2175 cpdma_ctlr_destroy(priv->dma); 2176 clean_wr_iomap_ret: 2177 iounmap(priv->wr_regs); 2178 clean_cpsw_wr_iores_ret: 2179 release_mem_region(priv->cpsw_wr_res->start, 2180 resource_size(priv->cpsw_wr_res)); 2181 clean_iomap_ret: 2182 iounmap(priv->regs); 2183 clean_cpsw_iores_ret: 2184 release_mem_region(priv->cpsw_res->start, 2185 resource_size(priv->cpsw_res)); 2186 clean_clk_ret: 2187 clk_put(priv->clk); 2188 clean_slave_ret: 2189 pm_runtime_disable(&pdev->dev); 2190 kfree(priv->slaves); 2191 clean_ndev_ret: 2192 kfree(priv->data.slave_data); 2193 free_netdev(priv->ndev); 2194 return ret; 2195 } 2196 2197 static int cpsw_remove(struct platform_device *pdev) 2198 { 2199 struct net_device *ndev = platform_get_drvdata(pdev); 2200 struct cpsw_priv *priv = netdev_priv(ndev); 2201 int i; 2202 2203 if (priv->data.dual_emac) 2204 unregister_netdev(cpsw_get_slave_ndev(priv, 1)); 2205 unregister_netdev(ndev); 2206 2207 cpts_unregister(priv->cpts); 2208 for (i = 0; i < priv->num_irqs; i++) 2209 free_irq(priv->irqs_table[i], priv); 2210 2211 cpsw_ale_destroy(priv->ale); 2212 cpdma_chan_destroy(priv->txch); 2213 cpdma_chan_destroy(priv->rxch); 2214 cpdma_ctlr_destroy(priv->dma); 2215 iounmap(priv->regs); 2216 release_mem_region(priv->cpsw_res->start, 2217 resource_size(priv->cpsw_res)); 2218 iounmap(priv->wr_regs); 2219 release_mem_region(priv->cpsw_wr_res->start, 2220 resource_size(priv->cpsw_wr_res)); 2221 pm_runtime_disable(&pdev->dev); 2222 clk_put(priv->clk); 2223 kfree(priv->slaves); 2224 kfree(priv->data.slave_data); 2225 if (priv->data.dual_emac) 2226 free_netdev(cpsw_get_slave_ndev(priv, 1)); 2227 free_netdev(ndev); 2228 return 0; 2229 } 2230 2231 static int cpsw_suspend(struct device *dev) 2232 { 2233 struct platform_device *pdev = to_platform_device(dev); 2234 struct net_device *ndev = platform_get_drvdata(pdev); 2235 struct cpsw_priv *priv = netdev_priv(ndev); 2236 2237 if (netif_running(ndev)) 2238 cpsw_ndo_stop(ndev); 2239 soft_reset("sliver 0", &priv->slaves[0].sliver->soft_reset); 2240 soft_reset("sliver 1", &priv->slaves[1].sliver->soft_reset); 2241 pm_runtime_put_sync(&pdev->dev); 2242 2243 /* Select sleep pin state */ 2244 pinctrl_pm_select_sleep_state(&pdev->dev); 2245 2246 return 0; 2247 } 2248 2249 static int cpsw_resume(struct device *dev) 2250 { 2251 struct platform_device *pdev = to_platform_device(dev); 2252 struct net_device *ndev = platform_get_drvdata(pdev); 2253 2254 pm_runtime_get_sync(&pdev->dev); 2255 2256 /* Select default pin state */ 2257 pinctrl_pm_select_default_state(&pdev->dev); 2258 2259 if (netif_running(ndev)) 2260 cpsw_ndo_open(ndev); 2261 return 0; 2262 } 2263 2264 static const struct dev_pm_ops cpsw_pm_ops = { 2265 .suspend = cpsw_suspend, 2266 .resume = cpsw_resume, 2267 }; 2268 2269 static const struct of_device_id cpsw_of_mtable[] = { 2270 { .compatible = "ti,cpsw", }, 2271 { /* sentinel */ }, 2272 }; 2273 MODULE_DEVICE_TABLE(of, cpsw_of_mtable); 2274 2275 static struct platform_driver cpsw_driver = { 2276 .driver = { 2277 .name = "cpsw", 2278 .owner = THIS_MODULE, 2279 .pm = &cpsw_pm_ops, 2280 .of_match_table = of_match_ptr(cpsw_of_mtable), 2281 }, 2282 .probe = cpsw_probe, 2283 .remove = cpsw_remove, 2284 }; 2285 2286 static int __init cpsw_init(void) 2287 { 2288 return platform_driver_register(&cpsw_driver); 2289 } 2290 late_initcall(cpsw_init); 2291 2292 static void __exit cpsw_exit(void) 2293 { 2294 platform_driver_unregister(&cpsw_driver); 2295 } 2296 module_exit(cpsw_exit); 2297 2298 MODULE_LICENSE("GPL"); 2299 MODULE_AUTHOR("Cyril Chemparathy <cyril@ti.com>"); 2300 MODULE_AUTHOR("Mugunthan V N <mugunthanvnm@ti.com>"); 2301 MODULE_DESCRIPTION("TI CPSW Ethernet driver"); 2302