1df828598SMugunthan V N /* 2df828598SMugunthan V N * Texas Instruments Ethernet Switch Driver 3df828598SMugunthan V N * 4df828598SMugunthan V N * Copyright (C) 2012 Texas Instruments 5df828598SMugunthan V N * 6df828598SMugunthan V N * This program is free software; you can redistribute it and/or 7df828598SMugunthan V N * modify it under the terms of the GNU General Public License as 8df828598SMugunthan V N * published by the Free Software Foundation version 2. 9df828598SMugunthan V N * 10df828598SMugunthan V N * This program is distributed "as is" WITHOUT ANY WARRANTY of any 11df828598SMugunthan V N * kind, whether express or implied; without even the implied warranty 12df828598SMugunthan V N * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13df828598SMugunthan V N * GNU General Public License for more details. 14df828598SMugunthan V N */ 15df828598SMugunthan V N 16df828598SMugunthan V N #include <linux/kernel.h> 17df828598SMugunthan V N #include <linux/io.h> 18df828598SMugunthan V N #include <linux/clk.h> 19df828598SMugunthan V N #include <linux/timer.h> 20df828598SMugunthan V N #include <linux/module.h> 21df828598SMugunthan V N #include <linux/platform_device.h> 22df828598SMugunthan V N #include <linux/irqreturn.h> 23df828598SMugunthan V N #include <linux/interrupt.h> 24df828598SMugunthan V N #include <linux/if_ether.h> 25df828598SMugunthan V N #include <linux/etherdevice.h> 26df828598SMugunthan V N #include <linux/netdevice.h> 272e5b38abSRichard Cochran #include <linux/net_tstamp.h> 28df828598SMugunthan V N #include <linux/phy.h> 29df828598SMugunthan V N #include <linux/workqueue.h> 30df828598SMugunthan V N #include <linux/delay.h> 31f150bd7fSMugunthan V N #include <linux/pm_runtime.h> 322eb32b0aSMugunthan V N #include <linux/of.h> 332eb32b0aSMugunthan V N #include <linux/of_net.h> 342eb32b0aSMugunthan V N #include <linux/of_device.h> 353b72c2feSMugunthan V N #include <linux/if_vlan.h> 36df828598SMugunthan V N 37df828598SMugunthan V N #include <linux/platform_data/cpsw.h> 38df828598SMugunthan V N 39df828598SMugunthan V N #include "cpsw_ale.h" 402e5b38abSRichard Cochran #include "cpts.h" 41df828598SMugunthan V N #include "davinci_cpdma.h" 42df828598SMugunthan V N 43df828598SMugunthan V N #define CPSW_DEBUG (NETIF_MSG_HW | NETIF_MSG_WOL | \ 44df828598SMugunthan V N NETIF_MSG_DRV | NETIF_MSG_LINK | \ 45df828598SMugunthan V N NETIF_MSG_IFUP | NETIF_MSG_INTR | \ 46df828598SMugunthan V N NETIF_MSG_PROBE | NETIF_MSG_TIMER | \ 47df828598SMugunthan V N NETIF_MSG_IFDOWN | NETIF_MSG_RX_ERR | \ 48df828598SMugunthan V N NETIF_MSG_TX_ERR | NETIF_MSG_TX_DONE | \ 49df828598SMugunthan V N NETIF_MSG_PKTDATA | NETIF_MSG_TX_QUEUED | \ 50df828598SMugunthan V N NETIF_MSG_RX_STATUS) 51df828598SMugunthan V N 52df828598SMugunthan V N #define cpsw_info(priv, type, format, ...) \ 53df828598SMugunthan V N do { \ 54df828598SMugunthan V N if (netif_msg_##type(priv) && net_ratelimit()) \ 55df828598SMugunthan V N dev_info(priv->dev, format, ## __VA_ARGS__); \ 56df828598SMugunthan V N } while (0) 57df828598SMugunthan V N 58df828598SMugunthan V N #define cpsw_err(priv, type, format, ...) \ 59df828598SMugunthan V N do { \ 60df828598SMugunthan V N if (netif_msg_##type(priv) && net_ratelimit()) \ 61df828598SMugunthan V N dev_err(priv->dev, format, ## __VA_ARGS__); \ 62df828598SMugunthan V N } while (0) 63df828598SMugunthan V N 64df828598SMugunthan V N #define cpsw_dbg(priv, type, format, ...) \ 65df828598SMugunthan V N do { \ 66df828598SMugunthan V N if (netif_msg_##type(priv) && net_ratelimit()) \ 67df828598SMugunthan V N dev_dbg(priv->dev, format, ## __VA_ARGS__); \ 68df828598SMugunthan V N } while (0) 69df828598SMugunthan V N 70df828598SMugunthan V N #define cpsw_notice(priv, type, format, ...) \ 71df828598SMugunthan V N do { \ 72df828598SMugunthan V N if (netif_msg_##type(priv) && net_ratelimit()) \ 73df828598SMugunthan V N dev_notice(priv->dev, format, ## __VA_ARGS__); \ 74df828598SMugunthan V N } while (0) 75df828598SMugunthan V N 765c50a856SMugunthan V N #define ALE_ALL_PORTS 0x7 775c50a856SMugunthan V N 78df828598SMugunthan V N #define CPSW_MAJOR_VERSION(reg) (reg >> 8 & 0x7) 79df828598SMugunthan V N #define CPSW_MINOR_VERSION(reg) (reg & 0xff) 80df828598SMugunthan V N #define CPSW_RTL_VERSION(reg) ((reg >> 11) & 0x1f) 81df828598SMugunthan V N 82e90cfac6SRichard Cochran #define CPSW_VERSION_1 0x19010a 83e90cfac6SRichard Cochran #define CPSW_VERSION_2 0x19010c 84549985eeSRichard Cochran 85549985eeSRichard Cochran #define HOST_PORT_NUM 0 86549985eeSRichard Cochran #define SLIVER_SIZE 0x40 87549985eeSRichard Cochran 88549985eeSRichard Cochran #define CPSW1_HOST_PORT_OFFSET 0x028 89549985eeSRichard Cochran #define CPSW1_SLAVE_OFFSET 0x050 90549985eeSRichard Cochran #define CPSW1_SLAVE_SIZE 0x040 91549985eeSRichard Cochran #define CPSW1_CPDMA_OFFSET 0x100 92549985eeSRichard Cochran #define CPSW1_STATERAM_OFFSET 0x200 93549985eeSRichard Cochran #define CPSW1_CPTS_OFFSET 0x500 94549985eeSRichard Cochran #define CPSW1_ALE_OFFSET 0x600 95549985eeSRichard Cochran #define CPSW1_SLIVER_OFFSET 0x700 96549985eeSRichard Cochran 97549985eeSRichard Cochran #define CPSW2_HOST_PORT_OFFSET 0x108 98549985eeSRichard Cochran #define CPSW2_SLAVE_OFFSET 0x200 99549985eeSRichard Cochran #define CPSW2_SLAVE_SIZE 0x100 100549985eeSRichard Cochran #define CPSW2_CPDMA_OFFSET 0x800 101549985eeSRichard Cochran #define CPSW2_STATERAM_OFFSET 0xa00 102549985eeSRichard Cochran #define CPSW2_CPTS_OFFSET 0xc00 103549985eeSRichard Cochran #define CPSW2_ALE_OFFSET 0xd00 104549985eeSRichard Cochran #define CPSW2_SLIVER_OFFSET 0xd80 105549985eeSRichard Cochran #define CPSW2_BD_OFFSET 0x2000 106549985eeSRichard Cochran 107df828598SMugunthan V N #define CPDMA_RXTHRESH 0x0c0 108df828598SMugunthan V N #define CPDMA_RXFREE 0x0e0 109df828598SMugunthan V N #define CPDMA_TXHDP 0x00 110df828598SMugunthan V N #define CPDMA_RXHDP 0x20 111df828598SMugunthan V N #define CPDMA_TXCP 0x40 112df828598SMugunthan V N #define CPDMA_RXCP 0x60 113df828598SMugunthan V N 114df828598SMugunthan V N #define CPSW_POLL_WEIGHT 64 115df828598SMugunthan V N #define CPSW_MIN_PACKET_SIZE 60 116df828598SMugunthan V N #define CPSW_MAX_PACKET_SIZE (1500 + 14 + 4 + 4) 117df828598SMugunthan V N 118df828598SMugunthan V N #define RX_PRIORITY_MAPPING 0x76543210 119df828598SMugunthan V N #define TX_PRIORITY_MAPPING 0x33221100 120df828598SMugunthan V N #define CPDMA_TX_PRIORITY_MAP 0x76543210 121df828598SMugunthan V N 1223b72c2feSMugunthan V N #define CPSW_VLAN_AWARE BIT(1) 1233b72c2feSMugunthan V N #define CPSW_ALE_VLAN_AWARE 1 1243b72c2feSMugunthan V N 125d9ba8f9eSMugunthan V N #define CPSW_FIFO_NORMAL_MODE (0 << 15) 126d9ba8f9eSMugunthan V N #define CPSW_FIFO_DUAL_MAC_MODE (1 << 15) 127d9ba8f9eSMugunthan V N #define CPSW_FIFO_RATE_LIMIT_MODE (2 << 15) 128d9ba8f9eSMugunthan V N 129ff5b8ef2SMugunthan V N #define CPSW_INTPACEEN (0x3f << 16) 130ff5b8ef2SMugunthan V N #define CPSW_INTPRESCALE_MASK (0x7FF << 0) 131ff5b8ef2SMugunthan V N #define CPSW_CMINTMAX_CNT 63 132ff5b8ef2SMugunthan V N #define CPSW_CMINTMIN_CNT 2 133ff5b8ef2SMugunthan V N #define CPSW_CMINTMAX_INTVL (1000 / CPSW_CMINTMIN_CNT) 134ff5b8ef2SMugunthan V N #define CPSW_CMINTMIN_INTVL ((1000 / CPSW_CMINTMAX_CNT) + 1) 135ff5b8ef2SMugunthan V N 136df828598SMugunthan V N #define cpsw_enable_irq(priv) \ 137df828598SMugunthan V N do { \ 138df828598SMugunthan V N u32 i; \ 139df828598SMugunthan V N for (i = 0; i < priv->num_irqs; i++) \ 140df828598SMugunthan V N enable_irq(priv->irqs_table[i]); \ 141df828598SMugunthan V N } while (0); 142df828598SMugunthan V N #define cpsw_disable_irq(priv) \ 143df828598SMugunthan V N do { \ 144df828598SMugunthan V N u32 i; \ 145df828598SMugunthan V N for (i = 0; i < priv->num_irqs; i++) \ 146df828598SMugunthan V N disable_irq_nosync(priv->irqs_table[i]); \ 147df828598SMugunthan V N } while (0); 148df828598SMugunthan V N 149d3bb9c58SMugunthan V N #define cpsw_slave_index(priv) \ 150d3bb9c58SMugunthan V N ((priv->data.dual_emac) ? priv->emac_port : \ 151d3bb9c58SMugunthan V N priv->data.active_slave) 152d3bb9c58SMugunthan V N 153df828598SMugunthan V N static int debug_level; 154df828598SMugunthan V N module_param(debug_level, int, 0); 155df828598SMugunthan V N MODULE_PARM_DESC(debug_level, "cpsw debug level (NETIF_MSG bits)"); 156df828598SMugunthan V N 157df828598SMugunthan V N static int ale_ageout = 10; 158df828598SMugunthan V N module_param(ale_ageout, int, 0); 159df828598SMugunthan V N MODULE_PARM_DESC(ale_ageout, "cpsw ale ageout interval (seconds)"); 160df828598SMugunthan V N 161df828598SMugunthan V N static int rx_packet_max = CPSW_MAX_PACKET_SIZE; 162df828598SMugunthan V N module_param(rx_packet_max, int, 0); 163df828598SMugunthan V N MODULE_PARM_DESC(rx_packet_max, "maximum receive packet size (bytes)"); 164df828598SMugunthan V N 165996a5c27SRichard Cochran struct cpsw_wr_regs { 166df828598SMugunthan V N u32 id_ver; 167df828598SMugunthan V N u32 soft_reset; 168df828598SMugunthan V N u32 control; 169df828598SMugunthan V N u32 int_control; 170df828598SMugunthan V N u32 rx_thresh_en; 171df828598SMugunthan V N u32 rx_en; 172df828598SMugunthan V N u32 tx_en; 173df828598SMugunthan V N u32 misc_en; 174ff5b8ef2SMugunthan V N u32 mem_allign1[8]; 175ff5b8ef2SMugunthan V N u32 rx_thresh_stat; 176ff5b8ef2SMugunthan V N u32 rx_stat; 177ff5b8ef2SMugunthan V N u32 tx_stat; 178ff5b8ef2SMugunthan V N u32 misc_stat; 179ff5b8ef2SMugunthan V N u32 mem_allign2[8]; 180ff5b8ef2SMugunthan V N u32 rx_imax; 181ff5b8ef2SMugunthan V N u32 tx_imax; 182ff5b8ef2SMugunthan V N 183df828598SMugunthan V N }; 184df828598SMugunthan V N 185996a5c27SRichard Cochran struct cpsw_ss_regs { 186df828598SMugunthan V N u32 id_ver; 187df828598SMugunthan V N u32 control; 188df828598SMugunthan V N u32 soft_reset; 189df828598SMugunthan V N u32 stat_port_en; 190df828598SMugunthan V N u32 ptype; 191bd357af2SRichard Cochran u32 soft_idle; 192bd357af2SRichard Cochran u32 thru_rate; 193bd357af2SRichard Cochran u32 gap_thresh; 194bd357af2SRichard Cochran u32 tx_start_wds; 195bd357af2SRichard Cochran u32 flow_control; 196bd357af2SRichard Cochran u32 vlan_ltype; 197bd357af2SRichard Cochran u32 ts_ltype; 198bd357af2SRichard Cochran u32 dlr_ltype; 199df828598SMugunthan V N }; 200df828598SMugunthan V N 2019750a3adSRichard Cochran /* CPSW_PORT_V1 */ 2029750a3adSRichard Cochran #define CPSW1_MAX_BLKS 0x00 /* Maximum FIFO Blocks */ 2039750a3adSRichard Cochran #define CPSW1_BLK_CNT 0x04 /* FIFO Block Usage Count (Read Only) */ 2049750a3adSRichard Cochran #define CPSW1_TX_IN_CTL 0x08 /* Transmit FIFO Control */ 2059750a3adSRichard Cochran #define CPSW1_PORT_VLAN 0x0c /* VLAN Register */ 2069750a3adSRichard Cochran #define CPSW1_TX_PRI_MAP 0x10 /* Tx Header Priority to Switch Pri Mapping */ 2079750a3adSRichard Cochran #define CPSW1_TS_CTL 0x14 /* Time Sync Control */ 2089750a3adSRichard Cochran #define CPSW1_TS_SEQ_LTYPE 0x18 /* Time Sync Sequence ID Offset and Msg Type */ 2099750a3adSRichard Cochran #define CPSW1_TS_VLAN 0x1c /* Time Sync VLAN1 and VLAN2 */ 2109750a3adSRichard Cochran 2119750a3adSRichard Cochran /* CPSW_PORT_V2 */ 2129750a3adSRichard Cochran #define CPSW2_CONTROL 0x00 /* Control Register */ 2139750a3adSRichard Cochran #define CPSW2_MAX_BLKS 0x08 /* Maximum FIFO Blocks */ 2149750a3adSRichard Cochran #define CPSW2_BLK_CNT 0x0c /* FIFO Block Usage Count (Read Only) */ 2159750a3adSRichard Cochran #define CPSW2_TX_IN_CTL 0x10 /* Transmit FIFO Control */ 2169750a3adSRichard Cochran #define CPSW2_PORT_VLAN 0x14 /* VLAN Register */ 2179750a3adSRichard Cochran #define CPSW2_TX_PRI_MAP 0x18 /* Tx Header Priority to Switch Pri Mapping */ 2189750a3adSRichard Cochran #define CPSW2_TS_SEQ_MTYPE 0x1c /* Time Sync Sequence ID Offset and Msg Type */ 2199750a3adSRichard Cochran 2209750a3adSRichard Cochran /* CPSW_PORT_V1 and V2 */ 2219750a3adSRichard Cochran #define SA_LO 0x20 /* CPGMAC_SL Source Address Low */ 2229750a3adSRichard Cochran #define SA_HI 0x24 /* CPGMAC_SL Source Address High */ 2239750a3adSRichard Cochran #define SEND_PERCENT 0x28 /* Transmit Queue Send Percentages */ 2249750a3adSRichard Cochran 2259750a3adSRichard Cochran /* CPSW_PORT_V2 only */ 2269750a3adSRichard Cochran #define RX_DSCP_PRI_MAP0 0x30 /* Rx DSCP Priority to Rx Packet Mapping */ 2279750a3adSRichard Cochran #define RX_DSCP_PRI_MAP1 0x34 /* Rx DSCP Priority to Rx Packet Mapping */ 2289750a3adSRichard Cochran #define RX_DSCP_PRI_MAP2 0x38 /* Rx DSCP Priority to Rx Packet Mapping */ 2299750a3adSRichard Cochran #define RX_DSCP_PRI_MAP3 0x3c /* Rx DSCP Priority to Rx Packet Mapping */ 2309750a3adSRichard Cochran #define RX_DSCP_PRI_MAP4 0x40 /* Rx DSCP Priority to Rx Packet Mapping */ 2319750a3adSRichard Cochran #define RX_DSCP_PRI_MAP5 0x44 /* Rx DSCP Priority to Rx Packet Mapping */ 2329750a3adSRichard Cochran #define RX_DSCP_PRI_MAP6 0x48 /* Rx DSCP Priority to Rx Packet Mapping */ 2339750a3adSRichard Cochran #define RX_DSCP_PRI_MAP7 0x4c /* Rx DSCP Priority to Rx Packet Mapping */ 2349750a3adSRichard Cochran 2359750a3adSRichard Cochran /* Bit definitions for the CPSW2_CONTROL register */ 2369750a3adSRichard Cochran #define PASS_PRI_TAGGED (1<<24) /* Pass Priority Tagged */ 2379750a3adSRichard Cochran #define VLAN_LTYPE2_EN (1<<21) /* VLAN LTYPE 2 enable */ 2389750a3adSRichard Cochran #define VLAN_LTYPE1_EN (1<<20) /* VLAN LTYPE 1 enable */ 2399750a3adSRichard Cochran #define DSCP_PRI_EN (1<<16) /* DSCP Priority Enable */ 2409750a3adSRichard Cochran #define TS_320 (1<<14) /* Time Sync Dest Port 320 enable */ 2419750a3adSRichard Cochran #define TS_319 (1<<13) /* Time Sync Dest Port 319 enable */ 2429750a3adSRichard Cochran #define TS_132 (1<<12) /* Time Sync Dest IP Addr 132 enable */ 2439750a3adSRichard Cochran #define TS_131 (1<<11) /* Time Sync Dest IP Addr 131 enable */ 2449750a3adSRichard Cochran #define TS_130 (1<<10) /* Time Sync Dest IP Addr 130 enable */ 2459750a3adSRichard Cochran #define TS_129 (1<<9) /* Time Sync Dest IP Addr 129 enable */ 2469750a3adSRichard Cochran #define TS_BIT8 (1<<8) /* ts_ttl_nonzero? */ 2479750a3adSRichard Cochran #define TS_ANNEX_D_EN (1<<4) /* Time Sync Annex D enable */ 2489750a3adSRichard Cochran #define TS_LTYPE2_EN (1<<3) /* Time Sync LTYPE 2 enable */ 2499750a3adSRichard Cochran #define TS_LTYPE1_EN (1<<2) /* Time Sync LTYPE 1 enable */ 2509750a3adSRichard Cochran #define TS_TX_EN (1<<1) /* Time Sync Transmit Enable */ 2519750a3adSRichard Cochran #define TS_RX_EN (1<<0) /* Time Sync Receive Enable */ 2529750a3adSRichard Cochran 2539750a3adSRichard Cochran #define CTRL_TS_BITS \ 2549750a3adSRichard Cochran (TS_320 | TS_319 | TS_132 | TS_131 | TS_130 | TS_129 | TS_BIT8 | \ 2559750a3adSRichard Cochran TS_ANNEX_D_EN | TS_LTYPE1_EN) 2569750a3adSRichard Cochran 2579750a3adSRichard Cochran #define CTRL_ALL_TS_MASK (CTRL_TS_BITS | TS_TX_EN | TS_RX_EN) 2589750a3adSRichard Cochran #define CTRL_TX_TS_BITS (CTRL_TS_BITS | TS_TX_EN) 2599750a3adSRichard Cochran #define CTRL_RX_TS_BITS (CTRL_TS_BITS | TS_RX_EN) 2609750a3adSRichard Cochran 2619750a3adSRichard Cochran /* Bit definitions for the CPSW2_TS_SEQ_MTYPE register */ 2629750a3adSRichard Cochran #define TS_SEQ_ID_OFFSET_SHIFT (16) /* Time Sync Sequence ID Offset */ 2639750a3adSRichard Cochran #define TS_SEQ_ID_OFFSET_MASK (0x3f) 2649750a3adSRichard Cochran #define TS_MSG_TYPE_EN_SHIFT (0) /* Time Sync Message Type Enable */ 2659750a3adSRichard Cochran #define TS_MSG_TYPE_EN_MASK (0xffff) 2669750a3adSRichard Cochran 2679750a3adSRichard Cochran /* The PTP event messages - Sync, Delay_Req, Pdelay_Req, and Pdelay_Resp. */ 2689750a3adSRichard Cochran #define EVENT_MSG_BITS ((1<<0) | (1<<1) | (1<<2) | (1<<3)) 269df828598SMugunthan V N 2702e5b38abSRichard Cochran /* Bit definitions for the CPSW1_TS_CTL register */ 2712e5b38abSRichard Cochran #define CPSW_V1_TS_RX_EN BIT(0) 2722e5b38abSRichard Cochran #define CPSW_V1_TS_TX_EN BIT(4) 2732e5b38abSRichard Cochran #define CPSW_V1_MSG_TYPE_OFS 16 2742e5b38abSRichard Cochran 2752e5b38abSRichard Cochran /* Bit definitions for the CPSW1_TS_SEQ_LTYPE register */ 2762e5b38abSRichard Cochran #define CPSW_V1_SEQ_ID_OFS_SHIFT 16 2772e5b38abSRichard Cochran 278df828598SMugunthan V N struct cpsw_host_regs { 279df828598SMugunthan V N u32 max_blks; 280df828598SMugunthan V N u32 blk_cnt; 281d9ba8f9eSMugunthan V N u32 tx_in_ctl; 282df828598SMugunthan V N u32 port_vlan; 283df828598SMugunthan V N u32 tx_pri_map; 284df828598SMugunthan V N u32 cpdma_tx_pri_map; 285df828598SMugunthan V N u32 cpdma_rx_chan_map; 286df828598SMugunthan V N }; 287df828598SMugunthan V N 288df828598SMugunthan V N struct cpsw_sliver_regs { 289df828598SMugunthan V N u32 id_ver; 290df828598SMugunthan V N u32 mac_control; 291df828598SMugunthan V N u32 mac_status; 292df828598SMugunthan V N u32 soft_reset; 293df828598SMugunthan V N u32 rx_maxlen; 294df828598SMugunthan V N u32 __reserved_0; 295df828598SMugunthan V N u32 rx_pause; 296df828598SMugunthan V N u32 tx_pause; 297df828598SMugunthan V N u32 __reserved_1; 298df828598SMugunthan V N u32 rx_pri_map; 299df828598SMugunthan V N }; 300df828598SMugunthan V N 301df828598SMugunthan V N struct cpsw_slave { 3029750a3adSRichard Cochran void __iomem *regs; 303df828598SMugunthan V N struct cpsw_sliver_regs __iomem *sliver; 304df828598SMugunthan V N int slave_num; 305df828598SMugunthan V N u32 mac_control; 306df828598SMugunthan V N struct cpsw_slave_data *data; 307df828598SMugunthan V N struct phy_device *phy; 308d9ba8f9eSMugunthan V N struct net_device *ndev; 309d9ba8f9eSMugunthan V N u32 port_vlan; 310d9ba8f9eSMugunthan V N u32 open_stat; 311df828598SMugunthan V N }; 312df828598SMugunthan V N 3139750a3adSRichard Cochran static inline u32 slave_read(struct cpsw_slave *slave, u32 offset) 3149750a3adSRichard Cochran { 3159750a3adSRichard Cochran return __raw_readl(slave->regs + offset); 3169750a3adSRichard Cochran } 3179750a3adSRichard Cochran 3189750a3adSRichard Cochran static inline void slave_write(struct cpsw_slave *slave, u32 val, u32 offset) 3199750a3adSRichard Cochran { 3209750a3adSRichard Cochran __raw_writel(val, slave->regs + offset); 3219750a3adSRichard Cochran } 3229750a3adSRichard Cochran 323df828598SMugunthan V N struct cpsw_priv { 324df828598SMugunthan V N spinlock_t lock; 325df828598SMugunthan V N struct platform_device *pdev; 326df828598SMugunthan V N struct net_device *ndev; 327df828598SMugunthan V N struct resource *cpsw_res; 328a65dd5b2SRichard Cochran struct resource *cpsw_wr_res; 329df828598SMugunthan V N struct napi_struct napi; 330df828598SMugunthan V N struct device *dev; 331df828598SMugunthan V N struct cpsw_platform_data data; 332996a5c27SRichard Cochran struct cpsw_ss_regs __iomem *regs; 333996a5c27SRichard Cochran struct cpsw_wr_regs __iomem *wr_regs; 334df828598SMugunthan V N struct cpsw_host_regs __iomem *host_port_regs; 335df828598SMugunthan V N u32 msg_enable; 336e90cfac6SRichard Cochran u32 version; 337ff5b8ef2SMugunthan V N u32 coal_intvl; 338ff5b8ef2SMugunthan V N u32 bus_freq_mhz; 339df828598SMugunthan V N struct net_device_stats stats; 340df828598SMugunthan V N int rx_packet_max; 341df828598SMugunthan V N int host_port; 342df828598SMugunthan V N struct clk *clk; 343df828598SMugunthan V N u8 mac_addr[ETH_ALEN]; 344df828598SMugunthan V N struct cpsw_slave *slaves; 345df828598SMugunthan V N struct cpdma_ctlr *dma; 346df828598SMugunthan V N struct cpdma_chan *txch, *rxch; 347df828598SMugunthan V N struct cpsw_ale *ale; 348df828598SMugunthan V N /* snapshot of IRQ numbers */ 349df828598SMugunthan V N u32 irqs_table[4]; 350df828598SMugunthan V N u32 num_irqs; 3519232b16dSMugunthan V N struct cpts *cpts; 352d9ba8f9eSMugunthan V N u32 emac_port; 353df828598SMugunthan V N }; 354df828598SMugunthan V N 355df828598SMugunthan V N #define napi_to_priv(napi) container_of(napi, struct cpsw_priv, napi) 356df828598SMugunthan V N #define for_each_slave(priv, func, arg...) \ 357df828598SMugunthan V N do { \ 358df828598SMugunthan V N int idx; \ 359d9ba8f9eSMugunthan V N if (priv->data.dual_emac) \ 360d9ba8f9eSMugunthan V N (func)((priv)->slaves + priv->emac_port, ##arg);\ 361d9ba8f9eSMugunthan V N else \ 362df828598SMugunthan V N for (idx = 0; idx < (priv)->data.slaves; idx++) \ 363df828598SMugunthan V N (func)((priv)->slaves + idx, ##arg); \ 364df828598SMugunthan V N } while (0) 365d9ba8f9eSMugunthan V N #define cpsw_get_slave_ndev(priv, __slave_no__) \ 366d9ba8f9eSMugunthan V N (priv->slaves[__slave_no__].ndev) 367d9ba8f9eSMugunthan V N #define cpsw_get_slave_priv(priv, __slave_no__) \ 368d9ba8f9eSMugunthan V N ((priv->slaves[__slave_no__].ndev) ? \ 369d9ba8f9eSMugunthan V N netdev_priv(priv->slaves[__slave_no__].ndev) : NULL) \ 370d9ba8f9eSMugunthan V N 371d9ba8f9eSMugunthan V N #define cpsw_dual_emac_src_port_detect(status, priv, ndev, skb) \ 372d9ba8f9eSMugunthan V N do { \ 373d9ba8f9eSMugunthan V N if (!priv->data.dual_emac) \ 374d9ba8f9eSMugunthan V N break; \ 375d9ba8f9eSMugunthan V N if (CPDMA_RX_SOURCE_PORT(status) == 1) { \ 376d9ba8f9eSMugunthan V N ndev = cpsw_get_slave_ndev(priv, 0); \ 377d9ba8f9eSMugunthan V N priv = netdev_priv(ndev); \ 378d9ba8f9eSMugunthan V N skb->dev = ndev; \ 379d9ba8f9eSMugunthan V N } else if (CPDMA_RX_SOURCE_PORT(status) == 2) { \ 380d9ba8f9eSMugunthan V N ndev = cpsw_get_slave_ndev(priv, 1); \ 381d9ba8f9eSMugunthan V N priv = netdev_priv(ndev); \ 382d9ba8f9eSMugunthan V N skb->dev = ndev; \ 383d9ba8f9eSMugunthan V N } \ 384d9ba8f9eSMugunthan V N } while (0) 385d9ba8f9eSMugunthan V N #define cpsw_add_mcast(priv, addr) \ 386d9ba8f9eSMugunthan V N do { \ 387d9ba8f9eSMugunthan V N if (priv->data.dual_emac) { \ 388d9ba8f9eSMugunthan V N struct cpsw_slave *slave = priv->slaves + \ 389d9ba8f9eSMugunthan V N priv->emac_port; \ 390d9ba8f9eSMugunthan V N int slave_port = cpsw_get_slave_port(priv, \ 391d9ba8f9eSMugunthan V N slave->slave_num); \ 392d9ba8f9eSMugunthan V N cpsw_ale_add_mcast(priv->ale, addr, \ 393d9ba8f9eSMugunthan V N 1 << slave_port | 1 << priv->host_port, \ 394d9ba8f9eSMugunthan V N ALE_VLAN, slave->port_vlan, 0); \ 395d9ba8f9eSMugunthan V N } else { \ 396d9ba8f9eSMugunthan V N cpsw_ale_add_mcast(priv->ale, addr, \ 397d9ba8f9eSMugunthan V N ALE_ALL_PORTS << priv->host_port, \ 398d9ba8f9eSMugunthan V N 0, 0, 0); \ 399d9ba8f9eSMugunthan V N } \ 400d9ba8f9eSMugunthan V N } while (0) 401d9ba8f9eSMugunthan V N 402d9ba8f9eSMugunthan V N static inline int cpsw_get_slave_port(struct cpsw_priv *priv, u32 slave_num) 403d9ba8f9eSMugunthan V N { 404d9ba8f9eSMugunthan V N if (priv->host_port == 0) 405d9ba8f9eSMugunthan V N return slave_num + 1; 406d9ba8f9eSMugunthan V N else 407d9ba8f9eSMugunthan V N return slave_num; 408d9ba8f9eSMugunthan V N } 409df828598SMugunthan V N 4105c50a856SMugunthan V N static void cpsw_ndo_set_rx_mode(struct net_device *ndev) 4115c50a856SMugunthan V N { 4125c50a856SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 4135c50a856SMugunthan V N 4145c50a856SMugunthan V N if (ndev->flags & IFF_PROMISC) { 4155c50a856SMugunthan V N /* Enable promiscuous mode */ 4165c50a856SMugunthan V N dev_err(priv->dev, "Ignoring Promiscuous mode\n"); 4175c50a856SMugunthan V N return; 4185c50a856SMugunthan V N } 4195c50a856SMugunthan V N 4205c50a856SMugunthan V N /* Clear all mcast from ALE */ 4215c50a856SMugunthan V N cpsw_ale_flush_multicast(priv->ale, ALE_ALL_PORTS << priv->host_port); 4225c50a856SMugunthan V N 4235c50a856SMugunthan V N if (!netdev_mc_empty(ndev)) { 4245c50a856SMugunthan V N struct netdev_hw_addr *ha; 4255c50a856SMugunthan V N 4265c50a856SMugunthan V N /* program multicast address list into ALE register */ 4275c50a856SMugunthan V N netdev_for_each_mc_addr(ha, ndev) { 428d9ba8f9eSMugunthan V N cpsw_add_mcast(priv, (u8 *)ha->addr); 4295c50a856SMugunthan V N } 4305c50a856SMugunthan V N } 4315c50a856SMugunthan V N } 4325c50a856SMugunthan V N 433df828598SMugunthan V N static void cpsw_intr_enable(struct cpsw_priv *priv) 434df828598SMugunthan V N { 435996a5c27SRichard Cochran __raw_writel(0xFF, &priv->wr_regs->tx_en); 436996a5c27SRichard Cochran __raw_writel(0xFF, &priv->wr_regs->rx_en); 437df828598SMugunthan V N 438df828598SMugunthan V N cpdma_ctlr_int_ctrl(priv->dma, true); 439df828598SMugunthan V N return; 440df828598SMugunthan V N } 441df828598SMugunthan V N 442df828598SMugunthan V N static void cpsw_intr_disable(struct cpsw_priv *priv) 443df828598SMugunthan V N { 444996a5c27SRichard Cochran __raw_writel(0, &priv->wr_regs->tx_en); 445996a5c27SRichard Cochran __raw_writel(0, &priv->wr_regs->rx_en); 446df828598SMugunthan V N 447df828598SMugunthan V N cpdma_ctlr_int_ctrl(priv->dma, false); 448df828598SMugunthan V N return; 449df828598SMugunthan V N } 450df828598SMugunthan V N 451df828598SMugunthan V N void cpsw_tx_handler(void *token, int len, int status) 452df828598SMugunthan V N { 453df828598SMugunthan V N struct sk_buff *skb = token; 454df828598SMugunthan V N struct net_device *ndev = skb->dev; 455df828598SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 456df828598SMugunthan V N 457fae50823SMugunthan V N /* Check whether the queue is stopped due to stalled tx dma, if the 458fae50823SMugunthan V N * queue is stopped then start the queue as we have free desc for tx 459fae50823SMugunthan V N */ 460df828598SMugunthan V N if (unlikely(netif_queue_stopped(ndev))) 461df828598SMugunthan V N netif_start_queue(ndev); 4629232b16dSMugunthan V N cpts_tx_timestamp(priv->cpts, skb); 463df828598SMugunthan V N priv->stats.tx_packets++; 464df828598SMugunthan V N priv->stats.tx_bytes += len; 465df828598SMugunthan V N dev_kfree_skb_any(skb); 466df828598SMugunthan V N } 467df828598SMugunthan V N 468df828598SMugunthan V N void cpsw_rx_handler(void *token, int len, int status) 469df828598SMugunthan V N { 470df828598SMugunthan V N struct sk_buff *skb = token; 471df828598SMugunthan V N struct net_device *ndev = skb->dev; 472df828598SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 473df828598SMugunthan V N int ret = 0; 474df828598SMugunthan V N 475d9ba8f9eSMugunthan V N cpsw_dual_emac_src_port_detect(status, priv, ndev, skb); 476d9ba8f9eSMugunthan V N 477df828598SMugunthan V N /* free and bail if we are shutting down */ 478df828598SMugunthan V N if (unlikely(!netif_running(ndev)) || 479df828598SMugunthan V N unlikely(!netif_carrier_ok(ndev))) { 480df828598SMugunthan V N dev_kfree_skb_any(skb); 481df828598SMugunthan V N return; 482df828598SMugunthan V N } 483df828598SMugunthan V N if (likely(status >= 0)) { 484df828598SMugunthan V N skb_put(skb, len); 4859232b16dSMugunthan V N cpts_rx_timestamp(priv->cpts, skb); 486df828598SMugunthan V N skb->protocol = eth_type_trans(skb, ndev); 487df828598SMugunthan V N netif_receive_skb(skb); 488df828598SMugunthan V N priv->stats.rx_bytes += len; 489df828598SMugunthan V N priv->stats.rx_packets++; 490df828598SMugunthan V N skb = NULL; 491df828598SMugunthan V N } 492df828598SMugunthan V N 493df828598SMugunthan V N if (unlikely(!netif_running(ndev))) { 494df828598SMugunthan V N if (skb) 495df828598SMugunthan V N dev_kfree_skb_any(skb); 496df828598SMugunthan V N return; 497df828598SMugunthan V N } 498df828598SMugunthan V N 499df828598SMugunthan V N if (likely(!skb)) { 500df828598SMugunthan V N skb = netdev_alloc_skb_ip_align(ndev, priv->rx_packet_max); 501df828598SMugunthan V N if (WARN_ON(!skb)) 502df828598SMugunthan V N return; 503df828598SMugunthan V N 504df828598SMugunthan V N ret = cpdma_chan_submit(priv->rxch, skb, skb->data, 505f6e135c8SMugunthan V N skb_tailroom(skb), 0, GFP_KERNEL); 506df828598SMugunthan V N } 507df828598SMugunthan V N WARN_ON(ret < 0); 508df828598SMugunthan V N } 509df828598SMugunthan V N 510df828598SMugunthan V N static irqreturn_t cpsw_interrupt(int irq, void *dev_id) 511df828598SMugunthan V N { 512df828598SMugunthan V N struct cpsw_priv *priv = dev_id; 513df828598SMugunthan V N 514df828598SMugunthan V N if (likely(netif_running(priv->ndev))) { 515df828598SMugunthan V N cpsw_intr_disable(priv); 516df828598SMugunthan V N cpsw_disable_irq(priv); 517df828598SMugunthan V N napi_schedule(&priv->napi); 518d9ba8f9eSMugunthan V N } else { 519d9ba8f9eSMugunthan V N priv = cpsw_get_slave_priv(priv, 1); 520d9ba8f9eSMugunthan V N if (likely(priv) && likely(netif_running(priv->ndev))) { 521d9ba8f9eSMugunthan V N cpsw_intr_disable(priv); 522d9ba8f9eSMugunthan V N cpsw_disable_irq(priv); 523d9ba8f9eSMugunthan V N napi_schedule(&priv->napi); 524d9ba8f9eSMugunthan V N } 525df828598SMugunthan V N } 526df828598SMugunthan V N return IRQ_HANDLED; 527df828598SMugunthan V N } 528df828598SMugunthan V N 529df828598SMugunthan V N static int cpsw_poll(struct napi_struct *napi, int budget) 530df828598SMugunthan V N { 531df828598SMugunthan V N struct cpsw_priv *priv = napi_to_priv(napi); 532df828598SMugunthan V N int num_tx, num_rx; 533df828598SMugunthan V N 534df828598SMugunthan V N num_tx = cpdma_chan_process(priv->txch, 128); 535510a1e72SMugunthan V N if (num_tx) 536510a1e72SMugunthan V N cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_TX); 537510a1e72SMugunthan V N 538df828598SMugunthan V N num_rx = cpdma_chan_process(priv->rxch, budget); 539510a1e72SMugunthan V N if (num_rx < budget) { 540510a1e72SMugunthan V N napi_complete(napi); 541510a1e72SMugunthan V N cpsw_intr_enable(priv); 542510a1e72SMugunthan V N cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_RX); 543510a1e72SMugunthan V N cpsw_enable_irq(priv); 544510a1e72SMugunthan V N } 545df828598SMugunthan V N 546df828598SMugunthan V N if (num_rx || num_tx) 547df828598SMugunthan V N cpsw_dbg(priv, intr, "poll %d rx, %d tx pkts\n", 548df828598SMugunthan V N num_rx, num_tx); 549df828598SMugunthan V N 550df828598SMugunthan V N return num_rx; 551df828598SMugunthan V N } 552df828598SMugunthan V N 553df828598SMugunthan V N static inline void soft_reset(const char *module, void __iomem *reg) 554df828598SMugunthan V N { 555df828598SMugunthan V N unsigned long timeout = jiffies + HZ; 556df828598SMugunthan V N 557df828598SMugunthan V N __raw_writel(1, reg); 558df828598SMugunthan V N do { 559df828598SMugunthan V N cpu_relax(); 560df828598SMugunthan V N } while ((__raw_readl(reg) & 1) && time_after(timeout, jiffies)); 561df828598SMugunthan V N 562df828598SMugunthan V N WARN(__raw_readl(reg) & 1, "failed to soft-reset %s\n", module); 563df828598SMugunthan V N } 564df828598SMugunthan V N 565df828598SMugunthan V N #define mac_hi(mac) (((mac)[0] << 0) | ((mac)[1] << 8) | \ 566df828598SMugunthan V N ((mac)[2] << 16) | ((mac)[3] << 24)) 567df828598SMugunthan V N #define mac_lo(mac) (((mac)[4] << 0) | ((mac)[5] << 8)) 568df828598SMugunthan V N 569df828598SMugunthan V N static void cpsw_set_slave_mac(struct cpsw_slave *slave, 570df828598SMugunthan V N struct cpsw_priv *priv) 571df828598SMugunthan V N { 5729750a3adSRichard Cochran slave_write(slave, mac_hi(priv->mac_addr), SA_HI); 5739750a3adSRichard Cochran slave_write(slave, mac_lo(priv->mac_addr), SA_LO); 574df828598SMugunthan V N } 575df828598SMugunthan V N 576df828598SMugunthan V N static void _cpsw_adjust_link(struct cpsw_slave *slave, 577df828598SMugunthan V N struct cpsw_priv *priv, bool *link) 578df828598SMugunthan V N { 579df828598SMugunthan V N struct phy_device *phy = slave->phy; 580df828598SMugunthan V N u32 mac_control = 0; 581df828598SMugunthan V N u32 slave_port; 582df828598SMugunthan V N 583df828598SMugunthan V N if (!phy) 584df828598SMugunthan V N return; 585df828598SMugunthan V N 586df828598SMugunthan V N slave_port = cpsw_get_slave_port(priv, slave->slave_num); 587df828598SMugunthan V N 588df828598SMugunthan V N if (phy->link) { 589df828598SMugunthan V N mac_control = priv->data.mac_control; 590df828598SMugunthan V N 591df828598SMugunthan V N /* enable forwarding */ 592df828598SMugunthan V N cpsw_ale_control_set(priv->ale, slave_port, 593df828598SMugunthan V N ALE_PORT_STATE, ALE_PORT_STATE_FORWARD); 594df828598SMugunthan V N 595df828598SMugunthan V N if (phy->speed == 1000) 596df828598SMugunthan V N mac_control |= BIT(7); /* GIGABITEN */ 597df828598SMugunthan V N if (phy->duplex) 598df828598SMugunthan V N mac_control |= BIT(0); /* FULLDUPLEXEN */ 599342b7b74SDaniel Mack 600342b7b74SDaniel Mack /* set speed_in input in case RMII mode is used in 100Mbps */ 601342b7b74SDaniel Mack if (phy->speed == 100) 602342b7b74SDaniel Mack mac_control |= BIT(15); 603342b7b74SDaniel Mack 604df828598SMugunthan V N *link = true; 605df828598SMugunthan V N } else { 606df828598SMugunthan V N mac_control = 0; 607df828598SMugunthan V N /* disable forwarding */ 608df828598SMugunthan V N cpsw_ale_control_set(priv->ale, slave_port, 609df828598SMugunthan V N ALE_PORT_STATE, ALE_PORT_STATE_DISABLE); 610df828598SMugunthan V N } 611df828598SMugunthan V N 612df828598SMugunthan V N if (mac_control != slave->mac_control) { 613df828598SMugunthan V N phy_print_status(phy); 614df828598SMugunthan V N __raw_writel(mac_control, &slave->sliver->mac_control); 615df828598SMugunthan V N } 616df828598SMugunthan V N 617df828598SMugunthan V N slave->mac_control = mac_control; 618df828598SMugunthan V N } 619df828598SMugunthan V N 620df828598SMugunthan V N static void cpsw_adjust_link(struct net_device *ndev) 621df828598SMugunthan V N { 622df828598SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 623df828598SMugunthan V N bool link = false; 624df828598SMugunthan V N 625df828598SMugunthan V N for_each_slave(priv, _cpsw_adjust_link, priv, &link); 626df828598SMugunthan V N 627df828598SMugunthan V N if (link) { 628df828598SMugunthan V N netif_carrier_on(ndev); 629df828598SMugunthan V N if (netif_running(ndev)) 630df828598SMugunthan V N netif_wake_queue(ndev); 631df828598SMugunthan V N } else { 632df828598SMugunthan V N netif_carrier_off(ndev); 633df828598SMugunthan V N netif_stop_queue(ndev); 634df828598SMugunthan V N } 635df828598SMugunthan V N } 636df828598SMugunthan V N 637ff5b8ef2SMugunthan V N static int cpsw_get_coalesce(struct net_device *ndev, 638ff5b8ef2SMugunthan V N struct ethtool_coalesce *coal) 639ff5b8ef2SMugunthan V N { 640ff5b8ef2SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 641ff5b8ef2SMugunthan V N 642ff5b8ef2SMugunthan V N coal->rx_coalesce_usecs = priv->coal_intvl; 643ff5b8ef2SMugunthan V N return 0; 644ff5b8ef2SMugunthan V N } 645ff5b8ef2SMugunthan V N 646ff5b8ef2SMugunthan V N static int cpsw_set_coalesce(struct net_device *ndev, 647ff5b8ef2SMugunthan V N struct ethtool_coalesce *coal) 648ff5b8ef2SMugunthan V N { 649ff5b8ef2SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 650ff5b8ef2SMugunthan V N u32 int_ctrl; 651ff5b8ef2SMugunthan V N u32 num_interrupts = 0; 652ff5b8ef2SMugunthan V N u32 prescale = 0; 653ff5b8ef2SMugunthan V N u32 addnl_dvdr = 1; 654ff5b8ef2SMugunthan V N u32 coal_intvl = 0; 655ff5b8ef2SMugunthan V N 656ff5b8ef2SMugunthan V N if (!coal->rx_coalesce_usecs) 657ff5b8ef2SMugunthan V N return -EINVAL; 658ff5b8ef2SMugunthan V N 659ff5b8ef2SMugunthan V N coal_intvl = coal->rx_coalesce_usecs; 660ff5b8ef2SMugunthan V N 661ff5b8ef2SMugunthan V N int_ctrl = readl(&priv->wr_regs->int_control); 662ff5b8ef2SMugunthan V N prescale = priv->bus_freq_mhz * 4; 663ff5b8ef2SMugunthan V N 664ff5b8ef2SMugunthan V N if (coal_intvl < CPSW_CMINTMIN_INTVL) 665ff5b8ef2SMugunthan V N coal_intvl = CPSW_CMINTMIN_INTVL; 666ff5b8ef2SMugunthan V N 667ff5b8ef2SMugunthan V N if (coal_intvl > CPSW_CMINTMAX_INTVL) { 668ff5b8ef2SMugunthan V N /* Interrupt pacer works with 4us Pulse, we can 669ff5b8ef2SMugunthan V N * throttle further by dilating the 4us pulse. 670ff5b8ef2SMugunthan V N */ 671ff5b8ef2SMugunthan V N addnl_dvdr = CPSW_INTPRESCALE_MASK / prescale; 672ff5b8ef2SMugunthan V N 673ff5b8ef2SMugunthan V N if (addnl_dvdr > 1) { 674ff5b8ef2SMugunthan V N prescale *= addnl_dvdr; 675ff5b8ef2SMugunthan V N if (coal_intvl > (CPSW_CMINTMAX_INTVL * addnl_dvdr)) 676ff5b8ef2SMugunthan V N coal_intvl = (CPSW_CMINTMAX_INTVL 677ff5b8ef2SMugunthan V N * addnl_dvdr); 678ff5b8ef2SMugunthan V N } else { 679ff5b8ef2SMugunthan V N addnl_dvdr = 1; 680ff5b8ef2SMugunthan V N coal_intvl = CPSW_CMINTMAX_INTVL; 681ff5b8ef2SMugunthan V N } 682ff5b8ef2SMugunthan V N } 683ff5b8ef2SMugunthan V N 684ff5b8ef2SMugunthan V N num_interrupts = (1000 * addnl_dvdr) / coal_intvl; 685ff5b8ef2SMugunthan V N writel(num_interrupts, &priv->wr_regs->rx_imax); 686ff5b8ef2SMugunthan V N writel(num_interrupts, &priv->wr_regs->tx_imax); 687ff5b8ef2SMugunthan V N 688ff5b8ef2SMugunthan V N int_ctrl |= CPSW_INTPACEEN; 689ff5b8ef2SMugunthan V N int_ctrl &= (~CPSW_INTPRESCALE_MASK); 690ff5b8ef2SMugunthan V N int_ctrl |= (prescale & CPSW_INTPRESCALE_MASK); 691ff5b8ef2SMugunthan V N writel(int_ctrl, &priv->wr_regs->int_control); 692ff5b8ef2SMugunthan V N 693ff5b8ef2SMugunthan V N cpsw_notice(priv, timer, "Set coalesce to %d usecs.\n", coal_intvl); 694ff5b8ef2SMugunthan V N if (priv->data.dual_emac) { 695ff5b8ef2SMugunthan V N int i; 696ff5b8ef2SMugunthan V N 697ff5b8ef2SMugunthan V N for (i = 0; i < priv->data.slaves; i++) { 698ff5b8ef2SMugunthan V N priv = netdev_priv(priv->slaves[i].ndev); 699ff5b8ef2SMugunthan V N priv->coal_intvl = coal_intvl; 700ff5b8ef2SMugunthan V N } 701ff5b8ef2SMugunthan V N } else { 702ff5b8ef2SMugunthan V N priv->coal_intvl = coal_intvl; 703ff5b8ef2SMugunthan V N } 704ff5b8ef2SMugunthan V N 705ff5b8ef2SMugunthan V N return 0; 706ff5b8ef2SMugunthan V N } 707ff5b8ef2SMugunthan V N 708df828598SMugunthan V N static inline int __show_stat(char *buf, int maxlen, const char *name, u32 val) 709df828598SMugunthan V N { 710df828598SMugunthan V N static char *leader = "........................................"; 711df828598SMugunthan V N 712df828598SMugunthan V N if (!val) 713df828598SMugunthan V N return 0; 714df828598SMugunthan V N else 715df828598SMugunthan V N return snprintf(buf, maxlen, "%s %s %10d\n", name, 716df828598SMugunthan V N leader + strlen(name), val); 717df828598SMugunthan V N } 718df828598SMugunthan V N 719d9ba8f9eSMugunthan V N static int cpsw_common_res_usage_state(struct cpsw_priv *priv) 720d9ba8f9eSMugunthan V N { 721d9ba8f9eSMugunthan V N u32 i; 722d9ba8f9eSMugunthan V N u32 usage_count = 0; 723d9ba8f9eSMugunthan V N 724d9ba8f9eSMugunthan V N if (!priv->data.dual_emac) 725d9ba8f9eSMugunthan V N return 0; 726d9ba8f9eSMugunthan V N 727d9ba8f9eSMugunthan V N for (i = 0; i < priv->data.slaves; i++) 728d9ba8f9eSMugunthan V N if (priv->slaves[i].open_stat) 729d9ba8f9eSMugunthan V N usage_count++; 730d9ba8f9eSMugunthan V N 731d9ba8f9eSMugunthan V N return usage_count; 732d9ba8f9eSMugunthan V N } 733d9ba8f9eSMugunthan V N 734d9ba8f9eSMugunthan V N static inline int cpsw_tx_packet_submit(struct net_device *ndev, 735d9ba8f9eSMugunthan V N struct cpsw_priv *priv, struct sk_buff *skb) 736d9ba8f9eSMugunthan V N { 737d9ba8f9eSMugunthan V N if (!priv->data.dual_emac) 738d9ba8f9eSMugunthan V N return cpdma_chan_submit(priv->txch, skb, skb->data, 739d9ba8f9eSMugunthan V N skb->len, 0, GFP_KERNEL); 740d9ba8f9eSMugunthan V N 741d9ba8f9eSMugunthan V N if (ndev == cpsw_get_slave_ndev(priv, 0)) 742d9ba8f9eSMugunthan V N return cpdma_chan_submit(priv->txch, skb, skb->data, 743d9ba8f9eSMugunthan V N skb->len, 1, GFP_KERNEL); 744d9ba8f9eSMugunthan V N else 745d9ba8f9eSMugunthan V N return cpdma_chan_submit(priv->txch, skb, skb->data, 746d9ba8f9eSMugunthan V N skb->len, 2, GFP_KERNEL); 747d9ba8f9eSMugunthan V N } 748d9ba8f9eSMugunthan V N 749d9ba8f9eSMugunthan V N static inline void cpsw_add_dual_emac_def_ale_entries( 750d9ba8f9eSMugunthan V N struct cpsw_priv *priv, struct cpsw_slave *slave, 751d9ba8f9eSMugunthan V N u32 slave_port) 752d9ba8f9eSMugunthan V N { 753d9ba8f9eSMugunthan V N u32 port_mask = 1 << slave_port | 1 << priv->host_port; 754d9ba8f9eSMugunthan V N 755d9ba8f9eSMugunthan V N if (priv->version == CPSW_VERSION_1) 756d9ba8f9eSMugunthan V N slave_write(slave, slave->port_vlan, CPSW1_PORT_VLAN); 757d9ba8f9eSMugunthan V N else 758d9ba8f9eSMugunthan V N slave_write(slave, slave->port_vlan, CPSW2_PORT_VLAN); 759d9ba8f9eSMugunthan V N cpsw_ale_add_vlan(priv->ale, slave->port_vlan, port_mask, 760d9ba8f9eSMugunthan V N port_mask, port_mask, 0); 761d9ba8f9eSMugunthan V N cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast, 762d9ba8f9eSMugunthan V N port_mask, ALE_VLAN, slave->port_vlan, 0); 763d9ba8f9eSMugunthan V N cpsw_ale_add_ucast(priv->ale, priv->mac_addr, 764d9ba8f9eSMugunthan V N priv->host_port, ALE_VLAN, slave->port_vlan); 765d9ba8f9eSMugunthan V N } 766d9ba8f9eSMugunthan V N 767df828598SMugunthan V N static void cpsw_slave_open(struct cpsw_slave *slave, struct cpsw_priv *priv) 768df828598SMugunthan V N { 769df828598SMugunthan V N char name[32]; 770df828598SMugunthan V N u32 slave_port; 771df828598SMugunthan V N 772df828598SMugunthan V N sprintf(name, "slave-%d", slave->slave_num); 773df828598SMugunthan V N 774df828598SMugunthan V N soft_reset(name, &slave->sliver->soft_reset); 775df828598SMugunthan V N 776df828598SMugunthan V N /* setup priority mapping */ 777df828598SMugunthan V N __raw_writel(RX_PRIORITY_MAPPING, &slave->sliver->rx_pri_map); 7789750a3adSRichard Cochran 7799750a3adSRichard Cochran switch (priv->version) { 7809750a3adSRichard Cochran case CPSW_VERSION_1: 7819750a3adSRichard Cochran slave_write(slave, TX_PRIORITY_MAPPING, CPSW1_TX_PRI_MAP); 7829750a3adSRichard Cochran break; 7839750a3adSRichard Cochran case CPSW_VERSION_2: 7849750a3adSRichard Cochran slave_write(slave, TX_PRIORITY_MAPPING, CPSW2_TX_PRI_MAP); 7859750a3adSRichard Cochran break; 7869750a3adSRichard Cochran } 787df828598SMugunthan V N 788df828598SMugunthan V N /* setup max packet size, and mac address */ 789df828598SMugunthan V N __raw_writel(priv->rx_packet_max, &slave->sliver->rx_maxlen); 790df828598SMugunthan V N cpsw_set_slave_mac(slave, priv); 791df828598SMugunthan V N 792df828598SMugunthan V N slave->mac_control = 0; /* no link yet */ 793df828598SMugunthan V N 794df828598SMugunthan V N slave_port = cpsw_get_slave_port(priv, slave->slave_num); 795df828598SMugunthan V N 796d9ba8f9eSMugunthan V N if (priv->data.dual_emac) 797d9ba8f9eSMugunthan V N cpsw_add_dual_emac_def_ale_entries(priv, slave, slave_port); 798d9ba8f9eSMugunthan V N else 799df828598SMugunthan V N cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast, 800e11b220fSMugunthan V N 1 << slave_port, 0, 0, ALE_MCAST_FWD_2); 801df828598SMugunthan V N 802df828598SMugunthan V N slave->phy = phy_connect(priv->ndev, slave->data->phy_id, 803f9a8f83bSFlorian Fainelli &cpsw_adjust_link, slave->data->phy_if); 804df828598SMugunthan V N if (IS_ERR(slave->phy)) { 805df828598SMugunthan V N dev_err(priv->dev, "phy %s not found on slave %d\n", 806df828598SMugunthan V N slave->data->phy_id, slave->slave_num); 807df828598SMugunthan V N slave->phy = NULL; 808df828598SMugunthan V N } else { 809df828598SMugunthan V N dev_info(priv->dev, "phy found : id is : 0x%x\n", 810df828598SMugunthan V N slave->phy->phy_id); 811df828598SMugunthan V N phy_start(slave->phy); 812df828598SMugunthan V N } 813df828598SMugunthan V N } 814df828598SMugunthan V N 8153b72c2feSMugunthan V N static inline void cpsw_add_default_vlan(struct cpsw_priv *priv) 8163b72c2feSMugunthan V N { 8173b72c2feSMugunthan V N const int vlan = priv->data.default_vlan; 8183b72c2feSMugunthan V N const int port = priv->host_port; 8193b72c2feSMugunthan V N u32 reg; 8203b72c2feSMugunthan V N int i; 8213b72c2feSMugunthan V N 8223b72c2feSMugunthan V N reg = (priv->version == CPSW_VERSION_1) ? CPSW1_PORT_VLAN : 8233b72c2feSMugunthan V N CPSW2_PORT_VLAN; 8243b72c2feSMugunthan V N 8253b72c2feSMugunthan V N writel(vlan, &priv->host_port_regs->port_vlan); 8263b72c2feSMugunthan V N 8270237c110SDaniel Mack for (i = 0; i < priv->data.slaves; i++) 8283b72c2feSMugunthan V N slave_write(priv->slaves + i, vlan, reg); 8293b72c2feSMugunthan V N 8303b72c2feSMugunthan V N cpsw_ale_add_vlan(priv->ale, vlan, ALE_ALL_PORTS << port, 8313b72c2feSMugunthan V N ALE_ALL_PORTS << port, ALE_ALL_PORTS << port, 8323b72c2feSMugunthan V N (ALE_PORT_1 | ALE_PORT_2) << port); 8333b72c2feSMugunthan V N } 8343b72c2feSMugunthan V N 835df828598SMugunthan V N static void cpsw_init_host_port(struct cpsw_priv *priv) 836df828598SMugunthan V N { 8373b72c2feSMugunthan V N u32 control_reg; 838d9ba8f9eSMugunthan V N u32 fifo_mode; 8393b72c2feSMugunthan V N 840df828598SMugunthan V N /* soft reset the controller and initialize ale */ 841df828598SMugunthan V N soft_reset("cpsw", &priv->regs->soft_reset); 842df828598SMugunthan V N cpsw_ale_start(priv->ale); 843df828598SMugunthan V N 844df828598SMugunthan V N /* switch to vlan unaware mode */ 8453b72c2feSMugunthan V N cpsw_ale_control_set(priv->ale, priv->host_port, ALE_VLAN_AWARE, 8463b72c2feSMugunthan V N CPSW_ALE_VLAN_AWARE); 8473b72c2feSMugunthan V N control_reg = readl(&priv->regs->control); 8483b72c2feSMugunthan V N control_reg |= CPSW_VLAN_AWARE; 8493b72c2feSMugunthan V N writel(control_reg, &priv->regs->control); 850d9ba8f9eSMugunthan V N fifo_mode = (priv->data.dual_emac) ? CPSW_FIFO_DUAL_MAC_MODE : 851d9ba8f9eSMugunthan V N CPSW_FIFO_NORMAL_MODE; 852d9ba8f9eSMugunthan V N writel(fifo_mode, &priv->host_port_regs->tx_in_ctl); 853df828598SMugunthan V N 854df828598SMugunthan V N /* setup host port priority mapping */ 855df828598SMugunthan V N __raw_writel(CPDMA_TX_PRIORITY_MAP, 856df828598SMugunthan V N &priv->host_port_regs->cpdma_tx_pri_map); 857df828598SMugunthan V N __raw_writel(0, &priv->host_port_regs->cpdma_rx_chan_map); 858df828598SMugunthan V N 859df828598SMugunthan V N cpsw_ale_control_set(priv->ale, priv->host_port, 860df828598SMugunthan V N ALE_PORT_STATE, ALE_PORT_STATE_FORWARD); 861df828598SMugunthan V N 862d9ba8f9eSMugunthan V N if (!priv->data.dual_emac) { 863d9ba8f9eSMugunthan V N cpsw_ale_add_ucast(priv->ale, priv->mac_addr, priv->host_port, 864d9ba8f9eSMugunthan V N 0, 0); 865df828598SMugunthan V N cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast, 866e11b220fSMugunthan V N 1 << priv->host_port, 0, 0, ALE_MCAST_FWD_2); 867df828598SMugunthan V N } 868d9ba8f9eSMugunthan V N } 869df828598SMugunthan V N 870df828598SMugunthan V N static int cpsw_ndo_open(struct net_device *ndev) 871df828598SMugunthan V N { 872df828598SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 873df828598SMugunthan V N int i, ret; 874df828598SMugunthan V N u32 reg; 875df828598SMugunthan V N 876d9ba8f9eSMugunthan V N if (!cpsw_common_res_usage_state(priv)) 877df828598SMugunthan V N cpsw_intr_disable(priv); 878df828598SMugunthan V N netif_carrier_off(ndev); 879df828598SMugunthan V N 880f150bd7fSMugunthan V N pm_runtime_get_sync(&priv->pdev->dev); 881df828598SMugunthan V N 882549985eeSRichard Cochran reg = priv->version; 883df828598SMugunthan V N 884df828598SMugunthan V N dev_info(priv->dev, "initializing cpsw version %d.%d (%d)\n", 885df828598SMugunthan V N CPSW_MAJOR_VERSION(reg), CPSW_MINOR_VERSION(reg), 886df828598SMugunthan V N CPSW_RTL_VERSION(reg)); 887df828598SMugunthan V N 888df828598SMugunthan V N /* initialize host and slave ports */ 889d9ba8f9eSMugunthan V N if (!cpsw_common_res_usage_state(priv)) 890df828598SMugunthan V N cpsw_init_host_port(priv); 891df828598SMugunthan V N for_each_slave(priv, cpsw_slave_open, priv); 892df828598SMugunthan V N 8933b72c2feSMugunthan V N /* Add default VLAN */ 894d9ba8f9eSMugunthan V N if (!priv->data.dual_emac) 8953b72c2feSMugunthan V N cpsw_add_default_vlan(priv); 8963b72c2feSMugunthan V N 897d9ba8f9eSMugunthan V N if (!cpsw_common_res_usage_state(priv)) { 898df828598SMugunthan V N /* setup tx dma to fixed prio and zero offset */ 899df828598SMugunthan V N cpdma_control_set(priv->dma, CPDMA_TX_PRIO_FIXED, 1); 900df828598SMugunthan V N cpdma_control_set(priv->dma, CPDMA_RX_BUFFER_OFFSET, 0); 901df828598SMugunthan V N 902d9ba8f9eSMugunthan V N /* disable priority elevation */ 903df828598SMugunthan V N __raw_writel(0, &priv->regs->ptype); 904df828598SMugunthan V N 905d9ba8f9eSMugunthan V N /* enable statistics collection only on all ports */ 906df828598SMugunthan V N __raw_writel(0x7, &priv->regs->stat_port_en); 907df828598SMugunthan V N 908df828598SMugunthan V N if (WARN_ON(!priv->data.rx_descs)) 909df828598SMugunthan V N priv->data.rx_descs = 128; 910df828598SMugunthan V N 911df828598SMugunthan V N for (i = 0; i < priv->data.rx_descs; i++) { 912df828598SMugunthan V N struct sk_buff *skb; 913df828598SMugunthan V N 914df828598SMugunthan V N ret = -ENOMEM; 915df828598SMugunthan V N skb = netdev_alloc_skb_ip_align(priv->ndev, 916df828598SMugunthan V N priv->rx_packet_max); 917df828598SMugunthan V N if (!skb) 918df828598SMugunthan V N break; 919df828598SMugunthan V N ret = cpdma_chan_submit(priv->rxch, skb, skb->data, 920f6e135c8SMugunthan V N skb_tailroom(skb), 0, GFP_KERNEL); 921df828598SMugunthan V N if (WARN_ON(ret < 0)) 922df828598SMugunthan V N break; 923df828598SMugunthan V N } 924d9ba8f9eSMugunthan V N /* continue even if we didn't manage to submit all 925d9ba8f9eSMugunthan V N * receive descs 926d9ba8f9eSMugunthan V N */ 927df828598SMugunthan V N cpsw_info(priv, ifup, "submitted %d rx descriptors\n", i); 928d9ba8f9eSMugunthan V N } 929df828598SMugunthan V N 930ff5b8ef2SMugunthan V N /* Enable Interrupt pacing if configured */ 931ff5b8ef2SMugunthan V N if (priv->coal_intvl != 0) { 932ff5b8ef2SMugunthan V N struct ethtool_coalesce coal; 933ff5b8ef2SMugunthan V N 934ff5b8ef2SMugunthan V N coal.rx_coalesce_usecs = (priv->coal_intvl << 4); 935ff5b8ef2SMugunthan V N cpsw_set_coalesce(ndev, &coal); 936ff5b8ef2SMugunthan V N } 937ff5b8ef2SMugunthan V N 938df828598SMugunthan V N cpdma_ctlr_start(priv->dma); 939df828598SMugunthan V N cpsw_intr_enable(priv); 940df828598SMugunthan V N napi_enable(&priv->napi); 941510a1e72SMugunthan V N cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_RX); 942510a1e72SMugunthan V N cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_TX); 943df828598SMugunthan V N 944d9ba8f9eSMugunthan V N if (priv->data.dual_emac) 945d9ba8f9eSMugunthan V N priv->slaves[priv->emac_port].open_stat = true; 946df828598SMugunthan V N return 0; 947df828598SMugunthan V N } 948df828598SMugunthan V N 949df828598SMugunthan V N static void cpsw_slave_stop(struct cpsw_slave *slave, struct cpsw_priv *priv) 950df828598SMugunthan V N { 951df828598SMugunthan V N if (!slave->phy) 952df828598SMugunthan V N return; 953df828598SMugunthan V N phy_stop(slave->phy); 954df828598SMugunthan V N phy_disconnect(slave->phy); 955df828598SMugunthan V N slave->phy = NULL; 956df828598SMugunthan V N } 957df828598SMugunthan V N 958df828598SMugunthan V N static int cpsw_ndo_stop(struct net_device *ndev) 959df828598SMugunthan V N { 960df828598SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 961df828598SMugunthan V N 962df828598SMugunthan V N cpsw_info(priv, ifdown, "shutting down cpsw device\n"); 963df828598SMugunthan V N netif_stop_queue(priv->ndev); 964df828598SMugunthan V N napi_disable(&priv->napi); 965df828598SMugunthan V N netif_carrier_off(priv->ndev); 966d9ba8f9eSMugunthan V N 967d9ba8f9eSMugunthan V N if (cpsw_common_res_usage_state(priv) <= 1) { 96871380f9bSMugunthan V N cpsw_intr_disable(priv); 96971380f9bSMugunthan V N cpdma_ctlr_int_ctrl(priv->dma, false); 97071380f9bSMugunthan V N cpdma_ctlr_stop(priv->dma); 971df828598SMugunthan V N cpsw_ale_stop(priv->ale); 972d9ba8f9eSMugunthan V N } 973df828598SMugunthan V N for_each_slave(priv, cpsw_slave_stop, priv); 974f150bd7fSMugunthan V N pm_runtime_put_sync(&priv->pdev->dev); 975d9ba8f9eSMugunthan V N if (priv->data.dual_emac) 976d9ba8f9eSMugunthan V N priv->slaves[priv->emac_port].open_stat = false; 977df828598SMugunthan V N return 0; 978df828598SMugunthan V N } 979df828598SMugunthan V N 980df828598SMugunthan V N static netdev_tx_t cpsw_ndo_start_xmit(struct sk_buff *skb, 981df828598SMugunthan V N struct net_device *ndev) 982df828598SMugunthan V N { 983df828598SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 984df828598SMugunthan V N int ret; 985df828598SMugunthan V N 986df828598SMugunthan V N ndev->trans_start = jiffies; 987df828598SMugunthan V N 988df828598SMugunthan V N if (skb_padto(skb, CPSW_MIN_PACKET_SIZE)) { 989df828598SMugunthan V N cpsw_err(priv, tx_err, "packet pad failed\n"); 990df828598SMugunthan V N priv->stats.tx_dropped++; 991df828598SMugunthan V N return NETDEV_TX_OK; 992df828598SMugunthan V N } 993df828598SMugunthan V N 9949232b16dSMugunthan V N if (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP && 9959232b16dSMugunthan V N priv->cpts->tx_enable) 9962e5b38abSRichard Cochran skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 9972e5b38abSRichard Cochran 9982e5b38abSRichard Cochran skb_tx_timestamp(skb); 9992e5b38abSRichard Cochran 1000d9ba8f9eSMugunthan V N ret = cpsw_tx_packet_submit(ndev, priv, skb); 1001df828598SMugunthan V N if (unlikely(ret != 0)) { 1002df828598SMugunthan V N cpsw_err(priv, tx_err, "desc submit failed\n"); 1003df828598SMugunthan V N goto fail; 1004df828598SMugunthan V N } 1005df828598SMugunthan V N 1006fae50823SMugunthan V N /* If there is no more tx desc left free then we need to 1007fae50823SMugunthan V N * tell the kernel to stop sending us tx frames. 1008fae50823SMugunthan V N */ 1009fae50823SMugunthan V N if (unlikely(cpdma_check_free_tx_desc(priv->txch))) 1010fae50823SMugunthan V N netif_stop_queue(ndev); 1011fae50823SMugunthan V N 1012df828598SMugunthan V N return NETDEV_TX_OK; 1013df828598SMugunthan V N fail: 1014df828598SMugunthan V N priv->stats.tx_dropped++; 1015df828598SMugunthan V N netif_stop_queue(ndev); 1016df828598SMugunthan V N return NETDEV_TX_BUSY; 1017df828598SMugunthan V N } 1018df828598SMugunthan V N 1019df828598SMugunthan V N static void cpsw_ndo_change_rx_flags(struct net_device *ndev, int flags) 1020df828598SMugunthan V N { 1021df828598SMugunthan V N /* 1022df828598SMugunthan V N * The switch cannot operate in promiscuous mode without substantial 1023df828598SMugunthan V N * headache. For promiscuous mode to work, we would need to put the 1024df828598SMugunthan V N * ALE in bypass mode and route all traffic to the host port. 1025df828598SMugunthan V N * Subsequently, the host will need to operate as a "bridge", learn, 1026df828598SMugunthan V N * and flood as needed. For now, we simply complain here and 1027df828598SMugunthan V N * do nothing about it :-) 1028df828598SMugunthan V N */ 1029df828598SMugunthan V N if ((flags & IFF_PROMISC) && (ndev->flags & IFF_PROMISC)) 1030df828598SMugunthan V N dev_err(&ndev->dev, "promiscuity ignored!\n"); 1031df828598SMugunthan V N 1032df828598SMugunthan V N /* 1033df828598SMugunthan V N * The switch cannot filter multicast traffic unless it is configured 1034df828598SMugunthan V N * in "VLAN Aware" mode. Unfortunately, VLAN awareness requires a 1035df828598SMugunthan V N * whole bunch of additional logic that this driver does not implement 1036df828598SMugunthan V N * at present. 1037df828598SMugunthan V N */ 1038df828598SMugunthan V N if ((flags & IFF_ALLMULTI) && !(ndev->flags & IFF_ALLMULTI)) 1039df828598SMugunthan V N dev_err(&ndev->dev, "multicast traffic cannot be filtered!\n"); 1040df828598SMugunthan V N } 1041df828598SMugunthan V N 10422e5b38abSRichard Cochran #ifdef CONFIG_TI_CPTS 10432e5b38abSRichard Cochran 10442e5b38abSRichard Cochran static void cpsw_hwtstamp_v1(struct cpsw_priv *priv) 10452e5b38abSRichard Cochran { 1046e86ac13bSMugunthan V N struct cpsw_slave *slave = &priv->slaves[priv->data.active_slave]; 10472e5b38abSRichard Cochran u32 ts_en, seq_id; 10482e5b38abSRichard Cochran 10499232b16dSMugunthan V N if (!priv->cpts->tx_enable && !priv->cpts->rx_enable) { 10502e5b38abSRichard Cochran slave_write(slave, 0, CPSW1_TS_CTL); 10512e5b38abSRichard Cochran return; 10522e5b38abSRichard Cochran } 10532e5b38abSRichard Cochran 10542e5b38abSRichard Cochran seq_id = (30 << CPSW_V1_SEQ_ID_OFS_SHIFT) | ETH_P_1588; 10552e5b38abSRichard Cochran ts_en = EVENT_MSG_BITS << CPSW_V1_MSG_TYPE_OFS; 10562e5b38abSRichard Cochran 10579232b16dSMugunthan V N if (priv->cpts->tx_enable) 10582e5b38abSRichard Cochran ts_en |= CPSW_V1_TS_TX_EN; 10592e5b38abSRichard Cochran 10609232b16dSMugunthan V N if (priv->cpts->rx_enable) 10612e5b38abSRichard Cochran ts_en |= CPSW_V1_TS_RX_EN; 10622e5b38abSRichard Cochran 10632e5b38abSRichard Cochran slave_write(slave, ts_en, CPSW1_TS_CTL); 10642e5b38abSRichard Cochran slave_write(slave, seq_id, CPSW1_TS_SEQ_LTYPE); 10652e5b38abSRichard Cochran } 10662e5b38abSRichard Cochran 10672e5b38abSRichard Cochran static void cpsw_hwtstamp_v2(struct cpsw_priv *priv) 10682e5b38abSRichard Cochran { 1069d9ba8f9eSMugunthan V N struct cpsw_slave *slave; 10702e5b38abSRichard Cochran u32 ctrl, mtype; 10712e5b38abSRichard Cochran 1072d9ba8f9eSMugunthan V N if (priv->data.dual_emac) 1073d9ba8f9eSMugunthan V N slave = &priv->slaves[priv->emac_port]; 1074d9ba8f9eSMugunthan V N else 1075e86ac13bSMugunthan V N slave = &priv->slaves[priv->data.active_slave]; 1076d9ba8f9eSMugunthan V N 10772e5b38abSRichard Cochran ctrl = slave_read(slave, CPSW2_CONTROL); 10782e5b38abSRichard Cochran ctrl &= ~CTRL_ALL_TS_MASK; 10792e5b38abSRichard Cochran 10809232b16dSMugunthan V N if (priv->cpts->tx_enable) 10812e5b38abSRichard Cochran ctrl |= CTRL_TX_TS_BITS; 10822e5b38abSRichard Cochran 10839232b16dSMugunthan V N if (priv->cpts->rx_enable) 10842e5b38abSRichard Cochran ctrl |= CTRL_RX_TS_BITS; 10852e5b38abSRichard Cochran 10862e5b38abSRichard Cochran mtype = (30 << TS_SEQ_ID_OFFSET_SHIFT) | EVENT_MSG_BITS; 10872e5b38abSRichard Cochran 10882e5b38abSRichard Cochran slave_write(slave, mtype, CPSW2_TS_SEQ_MTYPE); 10892e5b38abSRichard Cochran slave_write(slave, ctrl, CPSW2_CONTROL); 10902e5b38abSRichard Cochran __raw_writel(ETH_P_1588, &priv->regs->ts_ltype); 10912e5b38abSRichard Cochran } 10922e5b38abSRichard Cochran 10933177bf6fSMugunthan V N static int cpsw_hwtstamp_ioctl(struct net_device *dev, struct ifreq *ifr) 10942e5b38abSRichard Cochran { 10953177bf6fSMugunthan V N struct cpsw_priv *priv = netdev_priv(dev); 10969232b16dSMugunthan V N struct cpts *cpts = priv->cpts; 10972e5b38abSRichard Cochran struct hwtstamp_config cfg; 10982e5b38abSRichard Cochran 10992e5b38abSRichard Cochran if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg))) 11002e5b38abSRichard Cochran return -EFAULT; 11012e5b38abSRichard Cochran 11022e5b38abSRichard Cochran /* reserved for future extensions */ 11032e5b38abSRichard Cochran if (cfg.flags) 11042e5b38abSRichard Cochran return -EINVAL; 11052e5b38abSRichard Cochran 11062e5b38abSRichard Cochran switch (cfg.tx_type) { 11072e5b38abSRichard Cochran case HWTSTAMP_TX_OFF: 11082e5b38abSRichard Cochran cpts->tx_enable = 0; 11092e5b38abSRichard Cochran break; 11102e5b38abSRichard Cochran case HWTSTAMP_TX_ON: 11112e5b38abSRichard Cochran cpts->tx_enable = 1; 11122e5b38abSRichard Cochran break; 11132e5b38abSRichard Cochran default: 11142e5b38abSRichard Cochran return -ERANGE; 11152e5b38abSRichard Cochran } 11162e5b38abSRichard Cochran 11172e5b38abSRichard Cochran switch (cfg.rx_filter) { 11182e5b38abSRichard Cochran case HWTSTAMP_FILTER_NONE: 11192e5b38abSRichard Cochran cpts->rx_enable = 0; 11202e5b38abSRichard Cochran break; 11212e5b38abSRichard Cochran case HWTSTAMP_FILTER_ALL: 11222e5b38abSRichard Cochran case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: 11232e5b38abSRichard Cochran case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: 11242e5b38abSRichard Cochran case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: 11252e5b38abSRichard Cochran return -ERANGE; 11262e5b38abSRichard Cochran case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: 11272e5b38abSRichard Cochran case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 11282e5b38abSRichard Cochran case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 11292e5b38abSRichard Cochran case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: 11302e5b38abSRichard Cochran case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: 11312e5b38abSRichard Cochran case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: 11322e5b38abSRichard Cochran case HWTSTAMP_FILTER_PTP_V2_EVENT: 11332e5b38abSRichard Cochran case HWTSTAMP_FILTER_PTP_V2_SYNC: 11342e5b38abSRichard Cochran case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 11352e5b38abSRichard Cochran cpts->rx_enable = 1; 11362e5b38abSRichard Cochran cfg.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT; 11372e5b38abSRichard Cochran break; 11382e5b38abSRichard Cochran default: 11392e5b38abSRichard Cochran return -ERANGE; 11402e5b38abSRichard Cochran } 11412e5b38abSRichard Cochran 11422e5b38abSRichard Cochran switch (priv->version) { 11432e5b38abSRichard Cochran case CPSW_VERSION_1: 11442e5b38abSRichard Cochran cpsw_hwtstamp_v1(priv); 11452e5b38abSRichard Cochran break; 11462e5b38abSRichard Cochran case CPSW_VERSION_2: 11472e5b38abSRichard Cochran cpsw_hwtstamp_v2(priv); 11482e5b38abSRichard Cochran break; 11492e5b38abSRichard Cochran default: 11502e5b38abSRichard Cochran return -ENOTSUPP; 11512e5b38abSRichard Cochran } 11522e5b38abSRichard Cochran 11532e5b38abSRichard Cochran return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0; 11542e5b38abSRichard Cochran } 11552e5b38abSRichard Cochran 11562e5b38abSRichard Cochran #endif /*CONFIG_TI_CPTS*/ 11572e5b38abSRichard Cochran 11582e5b38abSRichard Cochran static int cpsw_ndo_ioctl(struct net_device *dev, struct ifreq *req, int cmd) 11592e5b38abSRichard Cochran { 11602e5b38abSRichard Cochran if (!netif_running(dev)) 11612e5b38abSRichard Cochran return -EINVAL; 11622e5b38abSRichard Cochran 11632e5b38abSRichard Cochran #ifdef CONFIG_TI_CPTS 11642e5b38abSRichard Cochran if (cmd == SIOCSHWTSTAMP) 11653177bf6fSMugunthan V N return cpsw_hwtstamp_ioctl(dev, req); 11662e5b38abSRichard Cochran #endif 11672e5b38abSRichard Cochran return -ENOTSUPP; 11682e5b38abSRichard Cochran } 11692e5b38abSRichard Cochran 1170df828598SMugunthan V N static void cpsw_ndo_tx_timeout(struct net_device *ndev) 1171df828598SMugunthan V N { 1172df828598SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 1173df828598SMugunthan V N 1174df828598SMugunthan V N cpsw_err(priv, tx_err, "transmit timeout, restarting dma\n"); 1175df828598SMugunthan V N priv->stats.tx_errors++; 1176df828598SMugunthan V N cpsw_intr_disable(priv); 1177df828598SMugunthan V N cpdma_ctlr_int_ctrl(priv->dma, false); 1178df828598SMugunthan V N cpdma_chan_stop(priv->txch); 1179df828598SMugunthan V N cpdma_chan_start(priv->txch); 1180df828598SMugunthan V N cpdma_ctlr_int_ctrl(priv->dma, true); 1181df828598SMugunthan V N cpsw_intr_enable(priv); 1182510a1e72SMugunthan V N cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_RX); 1183510a1e72SMugunthan V N cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_TX); 1184510a1e72SMugunthan V N 1185df828598SMugunthan V N } 1186df828598SMugunthan V N 1187df828598SMugunthan V N static struct net_device_stats *cpsw_ndo_get_stats(struct net_device *ndev) 1188df828598SMugunthan V N { 1189df828598SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 1190df828598SMugunthan V N return &priv->stats; 1191df828598SMugunthan V N } 1192df828598SMugunthan V N 1193df828598SMugunthan V N #ifdef CONFIG_NET_POLL_CONTROLLER 1194df828598SMugunthan V N static void cpsw_ndo_poll_controller(struct net_device *ndev) 1195df828598SMugunthan V N { 1196df828598SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 1197df828598SMugunthan V N 1198df828598SMugunthan V N cpsw_intr_disable(priv); 1199df828598SMugunthan V N cpdma_ctlr_int_ctrl(priv->dma, false); 1200df828598SMugunthan V N cpsw_interrupt(ndev->irq, priv); 1201df828598SMugunthan V N cpdma_ctlr_int_ctrl(priv->dma, true); 1202df828598SMugunthan V N cpsw_intr_enable(priv); 1203510a1e72SMugunthan V N cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_RX); 1204510a1e72SMugunthan V N cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_TX); 1205510a1e72SMugunthan V N 1206df828598SMugunthan V N } 1207df828598SMugunthan V N #endif 1208df828598SMugunthan V N 12093b72c2feSMugunthan V N static inline int cpsw_add_vlan_ale_entry(struct cpsw_priv *priv, 12103b72c2feSMugunthan V N unsigned short vid) 12113b72c2feSMugunthan V N { 12123b72c2feSMugunthan V N int ret; 12133b72c2feSMugunthan V N 12143b72c2feSMugunthan V N ret = cpsw_ale_add_vlan(priv->ale, vid, 12153b72c2feSMugunthan V N ALE_ALL_PORTS << priv->host_port, 12163b72c2feSMugunthan V N 0, ALE_ALL_PORTS << priv->host_port, 12173b72c2feSMugunthan V N (ALE_PORT_1 | ALE_PORT_2) << priv->host_port); 12183b72c2feSMugunthan V N if (ret != 0) 12193b72c2feSMugunthan V N return ret; 12203b72c2feSMugunthan V N 12213b72c2feSMugunthan V N ret = cpsw_ale_add_ucast(priv->ale, priv->mac_addr, 12223b72c2feSMugunthan V N priv->host_port, ALE_VLAN, vid); 12233b72c2feSMugunthan V N if (ret != 0) 12243b72c2feSMugunthan V N goto clean_vid; 12253b72c2feSMugunthan V N 12263b72c2feSMugunthan V N ret = cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast, 12273b72c2feSMugunthan V N ALE_ALL_PORTS << priv->host_port, 12283b72c2feSMugunthan V N ALE_VLAN, vid, 0); 12293b72c2feSMugunthan V N if (ret != 0) 12303b72c2feSMugunthan V N goto clean_vlan_ucast; 12313b72c2feSMugunthan V N return 0; 12323b72c2feSMugunthan V N 12333b72c2feSMugunthan V N clean_vlan_ucast: 12343b72c2feSMugunthan V N cpsw_ale_del_ucast(priv->ale, priv->mac_addr, 12353b72c2feSMugunthan V N priv->host_port, ALE_VLAN, vid); 12363b72c2feSMugunthan V N clean_vid: 12373b72c2feSMugunthan V N cpsw_ale_del_vlan(priv->ale, vid, 0); 12383b72c2feSMugunthan V N return ret; 12393b72c2feSMugunthan V N } 12403b72c2feSMugunthan V N 12413b72c2feSMugunthan V N static int cpsw_ndo_vlan_rx_add_vid(struct net_device *ndev, 12423b72c2feSMugunthan V N unsigned short vid) 12433b72c2feSMugunthan V N { 12443b72c2feSMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 12453b72c2feSMugunthan V N 12463b72c2feSMugunthan V N if (vid == priv->data.default_vlan) 12473b72c2feSMugunthan V N return 0; 12483b72c2feSMugunthan V N 12493b72c2feSMugunthan V N dev_info(priv->dev, "Adding vlanid %d to vlan filter\n", vid); 12503b72c2feSMugunthan V N return cpsw_add_vlan_ale_entry(priv, vid); 12513b72c2feSMugunthan V N } 12523b72c2feSMugunthan V N 12533b72c2feSMugunthan V N static int cpsw_ndo_vlan_rx_kill_vid(struct net_device *ndev, 12543b72c2feSMugunthan V N unsigned short vid) 12553b72c2feSMugunthan V N { 12563b72c2feSMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 12573b72c2feSMugunthan V N int ret; 12583b72c2feSMugunthan V N 12593b72c2feSMugunthan V N if (vid == priv->data.default_vlan) 12603b72c2feSMugunthan V N return 0; 12613b72c2feSMugunthan V N 12623b72c2feSMugunthan V N dev_info(priv->dev, "removing vlanid %d from vlan filter\n", vid); 12633b72c2feSMugunthan V N ret = cpsw_ale_del_vlan(priv->ale, vid, 0); 12643b72c2feSMugunthan V N if (ret != 0) 12653b72c2feSMugunthan V N return ret; 12663b72c2feSMugunthan V N 12673b72c2feSMugunthan V N ret = cpsw_ale_del_ucast(priv->ale, priv->mac_addr, 12683b72c2feSMugunthan V N priv->host_port, ALE_VLAN, vid); 12693b72c2feSMugunthan V N if (ret != 0) 12703b72c2feSMugunthan V N return ret; 12713b72c2feSMugunthan V N 12723b72c2feSMugunthan V N return cpsw_ale_del_mcast(priv->ale, priv->ndev->broadcast, 12733b72c2feSMugunthan V N 0, ALE_VLAN, vid); 12743b72c2feSMugunthan V N } 12753b72c2feSMugunthan V N 1276df828598SMugunthan V N static const struct net_device_ops cpsw_netdev_ops = { 1277df828598SMugunthan V N .ndo_open = cpsw_ndo_open, 1278df828598SMugunthan V N .ndo_stop = cpsw_ndo_stop, 1279df828598SMugunthan V N .ndo_start_xmit = cpsw_ndo_start_xmit, 1280df828598SMugunthan V N .ndo_change_rx_flags = cpsw_ndo_change_rx_flags, 12812e5b38abSRichard Cochran .ndo_do_ioctl = cpsw_ndo_ioctl, 1282df828598SMugunthan V N .ndo_validate_addr = eth_validate_addr, 12835c473ed2SDavid S. Miller .ndo_change_mtu = eth_change_mtu, 1284df828598SMugunthan V N .ndo_tx_timeout = cpsw_ndo_tx_timeout, 1285df828598SMugunthan V N .ndo_get_stats = cpsw_ndo_get_stats, 12865c50a856SMugunthan V N .ndo_set_rx_mode = cpsw_ndo_set_rx_mode, 1287df828598SMugunthan V N #ifdef CONFIG_NET_POLL_CONTROLLER 1288df828598SMugunthan V N .ndo_poll_controller = cpsw_ndo_poll_controller, 1289df828598SMugunthan V N #endif 12903b72c2feSMugunthan V N .ndo_vlan_rx_add_vid = cpsw_ndo_vlan_rx_add_vid, 12913b72c2feSMugunthan V N .ndo_vlan_rx_kill_vid = cpsw_ndo_vlan_rx_kill_vid, 1292df828598SMugunthan V N }; 1293df828598SMugunthan V N 1294df828598SMugunthan V N static void cpsw_get_drvinfo(struct net_device *ndev, 1295df828598SMugunthan V N struct ethtool_drvinfo *info) 1296df828598SMugunthan V N { 1297df828598SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 12987826d43fSJiri Pirko 12997826d43fSJiri Pirko strlcpy(info->driver, "TI CPSW Driver v1.0", sizeof(info->driver)); 13007826d43fSJiri Pirko strlcpy(info->version, "1.0", sizeof(info->version)); 13017826d43fSJiri Pirko strlcpy(info->bus_info, priv->pdev->name, sizeof(info->bus_info)); 1302df828598SMugunthan V N } 1303df828598SMugunthan V N 1304df828598SMugunthan V N static u32 cpsw_get_msglevel(struct net_device *ndev) 1305df828598SMugunthan V N { 1306df828598SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 1307df828598SMugunthan V N return priv->msg_enable; 1308df828598SMugunthan V N } 1309df828598SMugunthan V N 1310df828598SMugunthan V N static void cpsw_set_msglevel(struct net_device *ndev, u32 value) 1311df828598SMugunthan V N { 1312df828598SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 1313df828598SMugunthan V N priv->msg_enable = value; 1314df828598SMugunthan V N } 1315df828598SMugunthan V N 13162e5b38abSRichard Cochran static int cpsw_get_ts_info(struct net_device *ndev, 13172e5b38abSRichard Cochran struct ethtool_ts_info *info) 13182e5b38abSRichard Cochran { 13192e5b38abSRichard Cochran #ifdef CONFIG_TI_CPTS 13202e5b38abSRichard Cochran struct cpsw_priv *priv = netdev_priv(ndev); 13212e5b38abSRichard Cochran 13222e5b38abSRichard Cochran info->so_timestamping = 13232e5b38abSRichard Cochran SOF_TIMESTAMPING_TX_HARDWARE | 13242e5b38abSRichard Cochran SOF_TIMESTAMPING_TX_SOFTWARE | 13252e5b38abSRichard Cochran SOF_TIMESTAMPING_RX_HARDWARE | 13262e5b38abSRichard Cochran SOF_TIMESTAMPING_RX_SOFTWARE | 13272e5b38abSRichard Cochran SOF_TIMESTAMPING_SOFTWARE | 13282e5b38abSRichard Cochran SOF_TIMESTAMPING_RAW_HARDWARE; 13299232b16dSMugunthan V N info->phc_index = priv->cpts->phc_index; 13302e5b38abSRichard Cochran info->tx_types = 13312e5b38abSRichard Cochran (1 << HWTSTAMP_TX_OFF) | 13322e5b38abSRichard Cochran (1 << HWTSTAMP_TX_ON); 13332e5b38abSRichard Cochran info->rx_filters = 13342e5b38abSRichard Cochran (1 << HWTSTAMP_FILTER_NONE) | 13352e5b38abSRichard Cochran (1 << HWTSTAMP_FILTER_PTP_V2_EVENT); 13362e5b38abSRichard Cochran #else 13372e5b38abSRichard Cochran info->so_timestamping = 13382e5b38abSRichard Cochran SOF_TIMESTAMPING_TX_SOFTWARE | 13392e5b38abSRichard Cochran SOF_TIMESTAMPING_RX_SOFTWARE | 13402e5b38abSRichard Cochran SOF_TIMESTAMPING_SOFTWARE; 13412e5b38abSRichard Cochran info->phc_index = -1; 13422e5b38abSRichard Cochran info->tx_types = 0; 13432e5b38abSRichard Cochran info->rx_filters = 0; 13442e5b38abSRichard Cochran #endif 13452e5b38abSRichard Cochran return 0; 13462e5b38abSRichard Cochran } 13472e5b38abSRichard Cochran 1348d3bb9c58SMugunthan V N static int cpsw_get_settings(struct net_device *ndev, 1349d3bb9c58SMugunthan V N struct ethtool_cmd *ecmd) 1350d3bb9c58SMugunthan V N { 1351d3bb9c58SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 1352d3bb9c58SMugunthan V N int slave_no = cpsw_slave_index(priv); 1353d3bb9c58SMugunthan V N 1354d3bb9c58SMugunthan V N if (priv->slaves[slave_no].phy) 1355d3bb9c58SMugunthan V N return phy_ethtool_gset(priv->slaves[slave_no].phy, ecmd); 1356d3bb9c58SMugunthan V N else 1357d3bb9c58SMugunthan V N return -EOPNOTSUPP; 1358d3bb9c58SMugunthan V N } 1359d3bb9c58SMugunthan V N 1360d3bb9c58SMugunthan V N static int cpsw_set_settings(struct net_device *ndev, struct ethtool_cmd *ecmd) 1361d3bb9c58SMugunthan V N { 1362d3bb9c58SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 1363d3bb9c58SMugunthan V N int slave_no = cpsw_slave_index(priv); 1364d3bb9c58SMugunthan V N 1365d3bb9c58SMugunthan V N if (priv->slaves[slave_no].phy) 1366d3bb9c58SMugunthan V N return phy_ethtool_sset(priv->slaves[slave_no].phy, ecmd); 1367d3bb9c58SMugunthan V N else 1368d3bb9c58SMugunthan V N return -EOPNOTSUPP; 1369d3bb9c58SMugunthan V N } 1370d3bb9c58SMugunthan V N 1371df828598SMugunthan V N static const struct ethtool_ops cpsw_ethtool_ops = { 1372df828598SMugunthan V N .get_drvinfo = cpsw_get_drvinfo, 1373df828598SMugunthan V N .get_msglevel = cpsw_get_msglevel, 1374df828598SMugunthan V N .set_msglevel = cpsw_set_msglevel, 1375df828598SMugunthan V N .get_link = ethtool_op_get_link, 13762e5b38abSRichard Cochran .get_ts_info = cpsw_get_ts_info, 1377d3bb9c58SMugunthan V N .get_settings = cpsw_get_settings, 1378d3bb9c58SMugunthan V N .set_settings = cpsw_set_settings, 1379ff5b8ef2SMugunthan V N .get_coalesce = cpsw_get_coalesce, 1380ff5b8ef2SMugunthan V N .set_coalesce = cpsw_set_coalesce, 1381df828598SMugunthan V N }; 1382df828598SMugunthan V N 1383549985eeSRichard Cochran static void cpsw_slave_init(struct cpsw_slave *slave, struct cpsw_priv *priv, 1384549985eeSRichard Cochran u32 slave_reg_ofs, u32 sliver_reg_ofs) 1385df828598SMugunthan V N { 1386df828598SMugunthan V N void __iomem *regs = priv->regs; 1387df828598SMugunthan V N int slave_num = slave->slave_num; 1388df828598SMugunthan V N struct cpsw_slave_data *data = priv->data.slave_data + slave_num; 1389df828598SMugunthan V N 1390df828598SMugunthan V N slave->data = data; 1391549985eeSRichard Cochran slave->regs = regs + slave_reg_ofs; 1392549985eeSRichard Cochran slave->sliver = regs + sliver_reg_ofs; 1393d9ba8f9eSMugunthan V N slave->port_vlan = data->dual_emac_res_vlan; 1394df828598SMugunthan V N } 1395df828598SMugunthan V N 13962eb32b0aSMugunthan V N static int cpsw_probe_dt(struct cpsw_platform_data *data, 13972eb32b0aSMugunthan V N struct platform_device *pdev) 13982eb32b0aSMugunthan V N { 13992eb32b0aSMugunthan V N struct device_node *node = pdev->dev.of_node; 14002eb32b0aSMugunthan V N struct device_node *slave_node; 14012eb32b0aSMugunthan V N int i = 0, ret; 14022eb32b0aSMugunthan V N u32 prop; 14032eb32b0aSMugunthan V N 14042eb32b0aSMugunthan V N if (!node) 14052eb32b0aSMugunthan V N return -EINVAL; 14062eb32b0aSMugunthan V N 14072eb32b0aSMugunthan V N if (of_property_read_u32(node, "slaves", &prop)) { 14082eb32b0aSMugunthan V N pr_err("Missing slaves property in the DT.\n"); 14092eb32b0aSMugunthan V N return -EINVAL; 14102eb32b0aSMugunthan V N } 14112eb32b0aSMugunthan V N data->slaves = prop; 14122eb32b0aSMugunthan V N 1413e86ac13bSMugunthan V N if (of_property_read_u32(node, "active_slave", &prop)) { 1414e86ac13bSMugunthan V N pr_err("Missing active_slave property in the DT.\n"); 141578ca0b28SRichard Cochran ret = -EINVAL; 141678ca0b28SRichard Cochran goto error_ret; 141778ca0b28SRichard Cochran } 1418e86ac13bSMugunthan V N data->active_slave = prop; 141978ca0b28SRichard Cochran 142000ab94eeSRichard Cochran if (of_property_read_u32(node, "cpts_clock_mult", &prop)) { 142100ab94eeSRichard Cochran pr_err("Missing cpts_clock_mult property in the DT.\n"); 142200ab94eeSRichard Cochran ret = -EINVAL; 142300ab94eeSRichard Cochran goto error_ret; 142400ab94eeSRichard Cochran } 142500ab94eeSRichard Cochran data->cpts_clock_mult = prop; 142600ab94eeSRichard Cochran 142700ab94eeSRichard Cochran if (of_property_read_u32(node, "cpts_clock_shift", &prop)) { 142800ab94eeSRichard Cochran pr_err("Missing cpts_clock_shift property in the DT.\n"); 142900ab94eeSRichard Cochran ret = -EINVAL; 143000ab94eeSRichard Cochran goto error_ret; 143100ab94eeSRichard Cochran } 143200ab94eeSRichard Cochran data->cpts_clock_shift = prop; 143300ab94eeSRichard Cochran 1434b2adaca9SJoe Perches data->slave_data = kcalloc(data->slaves, sizeof(struct cpsw_slave_data), 1435b2adaca9SJoe Perches GFP_KERNEL); 1436b2adaca9SJoe Perches if (!data->slave_data) 14372eb32b0aSMugunthan V N return -EINVAL; 14382eb32b0aSMugunthan V N 14392eb32b0aSMugunthan V N if (of_property_read_u32(node, "cpdma_channels", &prop)) { 14402eb32b0aSMugunthan V N pr_err("Missing cpdma_channels property in the DT.\n"); 14412eb32b0aSMugunthan V N ret = -EINVAL; 14422eb32b0aSMugunthan V N goto error_ret; 14432eb32b0aSMugunthan V N } 14442eb32b0aSMugunthan V N data->channels = prop; 14452eb32b0aSMugunthan V N 14462eb32b0aSMugunthan V N if (of_property_read_u32(node, "ale_entries", &prop)) { 14472eb32b0aSMugunthan V N pr_err("Missing ale_entries property in the DT.\n"); 14482eb32b0aSMugunthan V N ret = -EINVAL; 14492eb32b0aSMugunthan V N goto error_ret; 14502eb32b0aSMugunthan V N } 14512eb32b0aSMugunthan V N data->ale_entries = prop; 14522eb32b0aSMugunthan V N 14532eb32b0aSMugunthan V N if (of_property_read_u32(node, "bd_ram_size", &prop)) { 14542eb32b0aSMugunthan V N pr_err("Missing bd_ram_size property in the DT.\n"); 14552eb32b0aSMugunthan V N ret = -EINVAL; 14562eb32b0aSMugunthan V N goto error_ret; 14572eb32b0aSMugunthan V N } 14582eb32b0aSMugunthan V N data->bd_ram_size = prop; 14592eb32b0aSMugunthan V N 14602eb32b0aSMugunthan V N if (of_property_read_u32(node, "rx_descs", &prop)) { 14612eb32b0aSMugunthan V N pr_err("Missing rx_descs property in the DT.\n"); 14622eb32b0aSMugunthan V N ret = -EINVAL; 14632eb32b0aSMugunthan V N goto error_ret; 14642eb32b0aSMugunthan V N } 14652eb32b0aSMugunthan V N data->rx_descs = prop; 14662eb32b0aSMugunthan V N 14672eb32b0aSMugunthan V N if (of_property_read_u32(node, "mac_control", &prop)) { 14682eb32b0aSMugunthan V N pr_err("Missing mac_control property in the DT.\n"); 14692eb32b0aSMugunthan V N ret = -EINVAL; 14702eb32b0aSMugunthan V N goto error_ret; 14712eb32b0aSMugunthan V N } 14722eb32b0aSMugunthan V N data->mac_control = prop; 14732eb32b0aSMugunthan V N 1474d9ba8f9eSMugunthan V N if (!of_property_read_u32(node, "dual_emac", &prop)) 1475d9ba8f9eSMugunthan V N data->dual_emac = prop; 1476d9ba8f9eSMugunthan V N 14771fb19aa7SVaibhav Hiremath /* 14781fb19aa7SVaibhav Hiremath * Populate all the child nodes here... 14791fb19aa7SVaibhav Hiremath */ 14801fb19aa7SVaibhav Hiremath ret = of_platform_populate(node, NULL, NULL, &pdev->dev); 14811fb19aa7SVaibhav Hiremath /* We do not want to force this, as in some cases may not have child */ 14821fb19aa7SVaibhav Hiremath if (ret) 14831fb19aa7SVaibhav Hiremath pr_warn("Doesn't have any child node\n"); 14841fb19aa7SVaibhav Hiremath 1485549985eeSRichard Cochran for_each_node_by_name(slave_node, "slave") { 1486549985eeSRichard Cochran struct cpsw_slave_data *slave_data = data->slave_data + i; 1487549985eeSRichard Cochran const void *mac_addr = NULL; 1488549985eeSRichard Cochran u32 phyid; 1489549985eeSRichard Cochran int lenp; 1490549985eeSRichard Cochran const __be32 *parp; 1491549985eeSRichard Cochran struct device_node *mdio_node; 1492549985eeSRichard Cochran struct platform_device *mdio; 1493549985eeSRichard Cochran 1494549985eeSRichard Cochran parp = of_get_property(slave_node, "phy_id", &lenp); 1495549985eeSRichard Cochran if ((parp == NULL) && (lenp != (sizeof(void *) * 2))) { 1496549985eeSRichard Cochran pr_err("Missing slave[%d] phy_id property\n", i); 1497549985eeSRichard Cochran ret = -EINVAL; 1498549985eeSRichard Cochran goto error_ret; 1499549985eeSRichard Cochran } 1500549985eeSRichard Cochran mdio_node = of_find_node_by_phandle(be32_to_cpup(parp)); 1501549985eeSRichard Cochran phyid = be32_to_cpup(parp+1); 1502549985eeSRichard Cochran mdio = of_find_device_by_node(mdio_node); 1503549985eeSRichard Cochran snprintf(slave_data->phy_id, sizeof(slave_data->phy_id), 1504549985eeSRichard Cochran PHY_ID_FMT, mdio->name, phyid); 1505549985eeSRichard Cochran 1506549985eeSRichard Cochran mac_addr = of_get_mac_address(slave_node); 1507549985eeSRichard Cochran if (mac_addr) 1508549985eeSRichard Cochran memcpy(slave_data->mac_addr, mac_addr, ETH_ALEN); 1509549985eeSRichard Cochran 1510d9ba8f9eSMugunthan V N if (data->dual_emac) { 1511d9ba8f9eSMugunthan V N if (of_property_read_u32(node, "dual_emac_res_vlan", 1512d9ba8f9eSMugunthan V N &prop)) { 1513d9ba8f9eSMugunthan V N pr_err("Missing dual_emac_res_vlan in DT.\n"); 1514d9ba8f9eSMugunthan V N slave_data->dual_emac_res_vlan = i+1; 1515d9ba8f9eSMugunthan V N pr_err("Using %d as Reserved VLAN for %d slave\n", 1516d9ba8f9eSMugunthan V N slave_data->dual_emac_res_vlan, i); 1517d9ba8f9eSMugunthan V N } else { 1518d9ba8f9eSMugunthan V N slave_data->dual_emac_res_vlan = prop; 1519d9ba8f9eSMugunthan V N } 1520d9ba8f9eSMugunthan V N } 1521d9ba8f9eSMugunthan V N 1522549985eeSRichard Cochran i++; 1523549985eeSRichard Cochran } 1524549985eeSRichard Cochran 15252eb32b0aSMugunthan V N return 0; 15262eb32b0aSMugunthan V N 15272eb32b0aSMugunthan V N error_ret: 15282eb32b0aSMugunthan V N kfree(data->slave_data); 15292eb32b0aSMugunthan V N return ret; 15302eb32b0aSMugunthan V N } 15312eb32b0aSMugunthan V N 1532d9ba8f9eSMugunthan V N static int cpsw_probe_dual_emac(struct platform_device *pdev, 1533d9ba8f9eSMugunthan V N struct cpsw_priv *priv) 1534d9ba8f9eSMugunthan V N { 1535d9ba8f9eSMugunthan V N struct cpsw_platform_data *data = &priv->data; 1536d9ba8f9eSMugunthan V N struct net_device *ndev; 1537d9ba8f9eSMugunthan V N struct cpsw_priv *priv_sl2; 1538d9ba8f9eSMugunthan V N int ret = 0, i; 1539d9ba8f9eSMugunthan V N 1540d9ba8f9eSMugunthan V N ndev = alloc_etherdev(sizeof(struct cpsw_priv)); 1541d9ba8f9eSMugunthan V N if (!ndev) { 1542d9ba8f9eSMugunthan V N pr_err("cpsw: error allocating net_device\n"); 1543d9ba8f9eSMugunthan V N return -ENOMEM; 1544d9ba8f9eSMugunthan V N } 1545d9ba8f9eSMugunthan V N 1546d9ba8f9eSMugunthan V N priv_sl2 = netdev_priv(ndev); 1547d9ba8f9eSMugunthan V N spin_lock_init(&priv_sl2->lock); 1548d9ba8f9eSMugunthan V N priv_sl2->data = *data; 1549d9ba8f9eSMugunthan V N priv_sl2->pdev = pdev; 1550d9ba8f9eSMugunthan V N priv_sl2->ndev = ndev; 1551d9ba8f9eSMugunthan V N priv_sl2->dev = &ndev->dev; 1552d9ba8f9eSMugunthan V N priv_sl2->msg_enable = netif_msg_init(debug_level, CPSW_DEBUG); 1553d9ba8f9eSMugunthan V N priv_sl2->rx_packet_max = max(rx_packet_max, 128); 1554d9ba8f9eSMugunthan V N 1555d9ba8f9eSMugunthan V N if (is_valid_ether_addr(data->slave_data[1].mac_addr)) { 1556d9ba8f9eSMugunthan V N memcpy(priv_sl2->mac_addr, data->slave_data[1].mac_addr, 1557d9ba8f9eSMugunthan V N ETH_ALEN); 1558d9ba8f9eSMugunthan V N pr_info("cpsw: Detected MACID = %pM\n", priv_sl2->mac_addr); 1559d9ba8f9eSMugunthan V N } else { 1560d9ba8f9eSMugunthan V N random_ether_addr(priv_sl2->mac_addr); 1561d9ba8f9eSMugunthan V N pr_info("cpsw: Random MACID = %pM\n", priv_sl2->mac_addr); 1562d9ba8f9eSMugunthan V N } 1563d9ba8f9eSMugunthan V N memcpy(ndev->dev_addr, priv_sl2->mac_addr, ETH_ALEN); 1564d9ba8f9eSMugunthan V N 1565d9ba8f9eSMugunthan V N priv_sl2->slaves = priv->slaves; 1566d9ba8f9eSMugunthan V N priv_sl2->clk = priv->clk; 1567d9ba8f9eSMugunthan V N 1568ff5b8ef2SMugunthan V N priv_sl2->coal_intvl = 0; 1569ff5b8ef2SMugunthan V N priv_sl2->bus_freq_mhz = priv->bus_freq_mhz; 1570ff5b8ef2SMugunthan V N 1571d9ba8f9eSMugunthan V N priv_sl2->cpsw_res = priv->cpsw_res; 1572d9ba8f9eSMugunthan V N priv_sl2->regs = priv->regs; 1573d9ba8f9eSMugunthan V N priv_sl2->host_port = priv->host_port; 1574d9ba8f9eSMugunthan V N priv_sl2->host_port_regs = priv->host_port_regs; 1575d9ba8f9eSMugunthan V N priv_sl2->wr_regs = priv->wr_regs; 1576d9ba8f9eSMugunthan V N priv_sl2->dma = priv->dma; 1577d9ba8f9eSMugunthan V N priv_sl2->txch = priv->txch; 1578d9ba8f9eSMugunthan V N priv_sl2->rxch = priv->rxch; 1579d9ba8f9eSMugunthan V N priv_sl2->ale = priv->ale; 1580d9ba8f9eSMugunthan V N priv_sl2->emac_port = 1; 1581d9ba8f9eSMugunthan V N priv->slaves[1].ndev = ndev; 1582d9ba8f9eSMugunthan V N priv_sl2->cpts = priv->cpts; 1583d9ba8f9eSMugunthan V N priv_sl2->version = priv->version; 1584d9ba8f9eSMugunthan V N 1585d9ba8f9eSMugunthan V N for (i = 0; i < priv->num_irqs; i++) { 1586d9ba8f9eSMugunthan V N priv_sl2->irqs_table[i] = priv->irqs_table[i]; 1587d9ba8f9eSMugunthan V N priv_sl2->num_irqs = priv->num_irqs; 1588d9ba8f9eSMugunthan V N } 1589d9ba8f9eSMugunthan V N 1590d9ba8f9eSMugunthan V N ndev->features |= NETIF_F_HW_VLAN_FILTER; 1591d9ba8f9eSMugunthan V N 1592d9ba8f9eSMugunthan V N ndev->netdev_ops = &cpsw_netdev_ops; 1593d9ba8f9eSMugunthan V N SET_ETHTOOL_OPS(ndev, &cpsw_ethtool_ops); 1594d9ba8f9eSMugunthan V N netif_napi_add(ndev, &priv_sl2->napi, cpsw_poll, CPSW_POLL_WEIGHT); 1595d9ba8f9eSMugunthan V N 1596d9ba8f9eSMugunthan V N /* register the network device */ 1597d9ba8f9eSMugunthan V N SET_NETDEV_DEV(ndev, &pdev->dev); 1598d9ba8f9eSMugunthan V N ret = register_netdev(ndev); 1599d9ba8f9eSMugunthan V N if (ret) { 1600d9ba8f9eSMugunthan V N pr_err("cpsw: error registering net device\n"); 1601d9ba8f9eSMugunthan V N free_netdev(ndev); 1602d9ba8f9eSMugunthan V N ret = -ENODEV; 1603d9ba8f9eSMugunthan V N } 1604d9ba8f9eSMugunthan V N 1605d9ba8f9eSMugunthan V N return ret; 1606d9ba8f9eSMugunthan V N } 1607d9ba8f9eSMugunthan V N 1608663e12e6SBill Pemberton static int cpsw_probe(struct platform_device *pdev) 1609df828598SMugunthan V N { 1610df828598SMugunthan V N struct cpsw_platform_data *data = pdev->dev.platform_data; 1611df828598SMugunthan V N struct net_device *ndev; 1612df828598SMugunthan V N struct cpsw_priv *priv; 1613df828598SMugunthan V N struct cpdma_params dma_params; 1614df828598SMugunthan V N struct cpsw_ale_params ale_params; 1615549985eeSRichard Cochran void __iomem *ss_regs, *wr_regs; 1616df828598SMugunthan V N struct resource *res; 1617549985eeSRichard Cochran u32 slave_offset, sliver_offset, slave_size; 1618df828598SMugunthan V N int ret = 0, i, k = 0; 1619df828598SMugunthan V N 1620df828598SMugunthan V N ndev = alloc_etherdev(sizeof(struct cpsw_priv)); 1621df828598SMugunthan V N if (!ndev) { 1622df828598SMugunthan V N pr_err("error allocating net_device\n"); 1623df828598SMugunthan V N return -ENOMEM; 1624df828598SMugunthan V N } 1625df828598SMugunthan V N 1626df828598SMugunthan V N platform_set_drvdata(pdev, ndev); 1627df828598SMugunthan V N priv = netdev_priv(ndev); 1628df828598SMugunthan V N spin_lock_init(&priv->lock); 1629df828598SMugunthan V N priv->pdev = pdev; 1630df828598SMugunthan V N priv->ndev = ndev; 1631df828598SMugunthan V N priv->dev = &ndev->dev; 1632df828598SMugunthan V N priv->msg_enable = netif_msg_init(debug_level, CPSW_DEBUG); 1633df828598SMugunthan V N priv->rx_packet_max = max(rx_packet_max, 128); 16349232b16dSMugunthan V N priv->cpts = devm_kzalloc(&pdev->dev, sizeof(struct cpts), GFP_KERNEL); 16359232b16dSMugunthan V N if (!ndev) { 16369232b16dSMugunthan V N pr_err("error allocating cpts\n"); 16379232b16dSMugunthan V N goto clean_ndev_ret; 16389232b16dSMugunthan V N } 1639df828598SMugunthan V N 16401fb19aa7SVaibhav Hiremath /* 16411fb19aa7SVaibhav Hiremath * This may be required here for child devices. 16421fb19aa7SVaibhav Hiremath */ 16431fb19aa7SVaibhav Hiremath pm_runtime_enable(&pdev->dev); 16441fb19aa7SVaibhav Hiremath 16452eb32b0aSMugunthan V N if (cpsw_probe_dt(&priv->data, pdev)) { 16462eb32b0aSMugunthan V N pr_err("cpsw: platform data missing\n"); 16472eb32b0aSMugunthan V N ret = -ENODEV; 16482eb32b0aSMugunthan V N goto clean_ndev_ret; 16492eb32b0aSMugunthan V N } 16502eb32b0aSMugunthan V N data = &priv->data; 16512eb32b0aSMugunthan V N 1652df828598SMugunthan V N if (is_valid_ether_addr(data->slave_data[0].mac_addr)) { 1653df828598SMugunthan V N memcpy(priv->mac_addr, data->slave_data[0].mac_addr, ETH_ALEN); 1654df828598SMugunthan V N pr_info("Detected MACID = %pM", priv->mac_addr); 1655df828598SMugunthan V N } else { 16567efd26d0SJoe Perches eth_random_addr(priv->mac_addr); 1657df828598SMugunthan V N pr_info("Random MACID = %pM", priv->mac_addr); 1658df828598SMugunthan V N } 1659df828598SMugunthan V N 1660df828598SMugunthan V N memcpy(ndev->dev_addr, priv->mac_addr, ETH_ALEN); 1661df828598SMugunthan V N 1662df828598SMugunthan V N priv->slaves = kzalloc(sizeof(struct cpsw_slave) * data->slaves, 1663df828598SMugunthan V N GFP_KERNEL); 1664df828598SMugunthan V N if (!priv->slaves) { 1665df828598SMugunthan V N ret = -EBUSY; 1666df828598SMugunthan V N goto clean_ndev_ret; 1667df828598SMugunthan V N } 1668df828598SMugunthan V N for (i = 0; i < data->slaves; i++) 1669df828598SMugunthan V N priv->slaves[i].slave_num = i; 1670df828598SMugunthan V N 1671d9ba8f9eSMugunthan V N priv->slaves[0].ndev = ndev; 1672d9ba8f9eSMugunthan V N priv->emac_port = 0; 1673d9ba8f9eSMugunthan V N 1674f150bd7fSMugunthan V N priv->clk = clk_get(&pdev->dev, "fck"); 1675df828598SMugunthan V N if (IS_ERR(priv->clk)) { 1676f150bd7fSMugunthan V N dev_err(&pdev->dev, "fck is not found\n"); 1677f150bd7fSMugunthan V N ret = -ENODEV; 1678f150bd7fSMugunthan V N goto clean_slave_ret; 1679df828598SMugunthan V N } 1680ff5b8ef2SMugunthan V N priv->coal_intvl = 0; 1681ff5b8ef2SMugunthan V N priv->bus_freq_mhz = clk_get_rate(priv->clk) / 1000000; 1682df828598SMugunthan V N 1683df828598SMugunthan V N priv->cpsw_res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1684df828598SMugunthan V N if (!priv->cpsw_res) { 1685df828598SMugunthan V N dev_err(priv->dev, "error getting i/o resource\n"); 1686df828598SMugunthan V N ret = -ENOENT; 1687df828598SMugunthan V N goto clean_clk_ret; 1688df828598SMugunthan V N } 1689df828598SMugunthan V N if (!request_mem_region(priv->cpsw_res->start, 1690df828598SMugunthan V N resource_size(priv->cpsw_res), ndev->name)) { 1691df828598SMugunthan V N dev_err(priv->dev, "failed request i/o region\n"); 1692df828598SMugunthan V N ret = -ENXIO; 1693df828598SMugunthan V N goto clean_clk_ret; 1694df828598SMugunthan V N } 1695549985eeSRichard Cochran ss_regs = ioremap(priv->cpsw_res->start, resource_size(priv->cpsw_res)); 1696549985eeSRichard Cochran if (!ss_regs) { 1697df828598SMugunthan V N dev_err(priv->dev, "unable to map i/o region\n"); 1698df828598SMugunthan V N goto clean_cpsw_iores_ret; 1699df828598SMugunthan V N } 1700549985eeSRichard Cochran priv->regs = ss_regs; 1701549985eeSRichard Cochran priv->version = __raw_readl(&priv->regs->id_ver); 1702549985eeSRichard Cochran priv->host_port = HOST_PORT_NUM; 1703df828598SMugunthan V N 1704a65dd5b2SRichard Cochran priv->cpsw_wr_res = platform_get_resource(pdev, IORESOURCE_MEM, 1); 1705a65dd5b2SRichard Cochran if (!priv->cpsw_wr_res) { 1706df828598SMugunthan V N dev_err(priv->dev, "error getting i/o resource\n"); 1707df828598SMugunthan V N ret = -ENOENT; 17085250c969SRichard Cochran goto clean_iomap_ret; 1709df828598SMugunthan V N } 1710a65dd5b2SRichard Cochran if (!request_mem_region(priv->cpsw_wr_res->start, 1711a65dd5b2SRichard Cochran resource_size(priv->cpsw_wr_res), ndev->name)) { 1712df828598SMugunthan V N dev_err(priv->dev, "failed request i/o region\n"); 1713df828598SMugunthan V N ret = -ENXIO; 17145250c969SRichard Cochran goto clean_iomap_ret; 1715df828598SMugunthan V N } 1716549985eeSRichard Cochran wr_regs = ioremap(priv->cpsw_wr_res->start, 1717a65dd5b2SRichard Cochran resource_size(priv->cpsw_wr_res)); 1718549985eeSRichard Cochran if (!wr_regs) { 1719df828598SMugunthan V N dev_err(priv->dev, "unable to map i/o region\n"); 1720a65dd5b2SRichard Cochran goto clean_cpsw_wr_iores_ret; 1721df828598SMugunthan V N } 1722549985eeSRichard Cochran priv->wr_regs = wr_regs; 1723df828598SMugunthan V N 1724df828598SMugunthan V N memset(&dma_params, 0, sizeof(dma_params)); 1725549985eeSRichard Cochran memset(&ale_params, 0, sizeof(ale_params)); 1726549985eeSRichard Cochran 1727549985eeSRichard Cochran switch (priv->version) { 1728549985eeSRichard Cochran case CPSW_VERSION_1: 1729549985eeSRichard Cochran priv->host_port_regs = ss_regs + CPSW1_HOST_PORT_OFFSET; 17309232b16dSMugunthan V N priv->cpts->reg = ss_regs + CPSW1_CPTS_OFFSET; 1731549985eeSRichard Cochran dma_params.dmaregs = ss_regs + CPSW1_CPDMA_OFFSET; 1732549985eeSRichard Cochran dma_params.txhdp = ss_regs + CPSW1_STATERAM_OFFSET; 1733549985eeSRichard Cochran ale_params.ale_regs = ss_regs + CPSW1_ALE_OFFSET; 1734549985eeSRichard Cochran slave_offset = CPSW1_SLAVE_OFFSET; 1735549985eeSRichard Cochran slave_size = CPSW1_SLAVE_SIZE; 1736549985eeSRichard Cochran sliver_offset = CPSW1_SLIVER_OFFSET; 1737549985eeSRichard Cochran dma_params.desc_mem_phys = 0; 1738549985eeSRichard Cochran break; 1739549985eeSRichard Cochran case CPSW_VERSION_2: 1740549985eeSRichard Cochran priv->host_port_regs = ss_regs + CPSW2_HOST_PORT_OFFSET; 17419232b16dSMugunthan V N priv->cpts->reg = ss_regs + CPSW2_CPTS_OFFSET; 1742549985eeSRichard Cochran dma_params.dmaregs = ss_regs + CPSW2_CPDMA_OFFSET; 1743549985eeSRichard Cochran dma_params.txhdp = ss_regs + CPSW2_STATERAM_OFFSET; 1744549985eeSRichard Cochran ale_params.ale_regs = ss_regs + CPSW2_ALE_OFFSET; 1745549985eeSRichard Cochran slave_offset = CPSW2_SLAVE_OFFSET; 1746549985eeSRichard Cochran slave_size = CPSW2_SLAVE_SIZE; 1747549985eeSRichard Cochran sliver_offset = CPSW2_SLIVER_OFFSET; 1748549985eeSRichard Cochran dma_params.desc_mem_phys = 1749549985eeSRichard Cochran (u32 __force) priv->cpsw_res->start + CPSW2_BD_OFFSET; 1750549985eeSRichard Cochran break; 1751549985eeSRichard Cochran default: 1752549985eeSRichard Cochran dev_err(priv->dev, "unknown version 0x%08x\n", priv->version); 1753549985eeSRichard Cochran ret = -ENODEV; 1754549985eeSRichard Cochran goto clean_cpsw_wr_iores_ret; 1755549985eeSRichard Cochran } 1756549985eeSRichard Cochran for (i = 0; i < priv->data.slaves; i++) { 1757549985eeSRichard Cochran struct cpsw_slave *slave = &priv->slaves[i]; 1758549985eeSRichard Cochran cpsw_slave_init(slave, priv, slave_offset, sliver_offset); 1759549985eeSRichard Cochran slave_offset += slave_size; 1760549985eeSRichard Cochran sliver_offset += SLIVER_SIZE; 1761549985eeSRichard Cochran } 1762549985eeSRichard Cochran 1763df828598SMugunthan V N dma_params.dev = &pdev->dev; 1764549985eeSRichard Cochran dma_params.rxthresh = dma_params.dmaregs + CPDMA_RXTHRESH; 1765549985eeSRichard Cochran dma_params.rxfree = dma_params.dmaregs + CPDMA_RXFREE; 1766549985eeSRichard Cochran dma_params.rxhdp = dma_params.txhdp + CPDMA_RXHDP; 1767549985eeSRichard Cochran dma_params.txcp = dma_params.txhdp + CPDMA_TXCP; 1768549985eeSRichard Cochran dma_params.rxcp = dma_params.txhdp + CPDMA_RXCP; 1769df828598SMugunthan V N 1770df828598SMugunthan V N dma_params.num_chan = data->channels; 1771df828598SMugunthan V N dma_params.has_soft_reset = true; 1772df828598SMugunthan V N dma_params.min_packet_size = CPSW_MIN_PACKET_SIZE; 1773df828598SMugunthan V N dma_params.desc_mem_size = data->bd_ram_size; 1774df828598SMugunthan V N dma_params.desc_align = 16; 1775df828598SMugunthan V N dma_params.has_ext_regs = true; 1776549985eeSRichard Cochran dma_params.desc_hw_addr = dma_params.desc_mem_phys; 1777df828598SMugunthan V N 1778df828598SMugunthan V N priv->dma = cpdma_ctlr_create(&dma_params); 1779df828598SMugunthan V N if (!priv->dma) { 1780df828598SMugunthan V N dev_err(priv->dev, "error initializing dma\n"); 1781df828598SMugunthan V N ret = -ENOMEM; 17825250c969SRichard Cochran goto clean_wr_iomap_ret; 1783df828598SMugunthan V N } 1784df828598SMugunthan V N 1785df828598SMugunthan V N priv->txch = cpdma_chan_create(priv->dma, tx_chan_num(0), 1786df828598SMugunthan V N cpsw_tx_handler); 1787df828598SMugunthan V N priv->rxch = cpdma_chan_create(priv->dma, rx_chan_num(0), 1788df828598SMugunthan V N cpsw_rx_handler); 1789df828598SMugunthan V N 1790df828598SMugunthan V N if (WARN_ON(!priv->txch || !priv->rxch)) { 1791df828598SMugunthan V N dev_err(priv->dev, "error initializing dma channels\n"); 1792df828598SMugunthan V N ret = -ENOMEM; 1793df828598SMugunthan V N goto clean_dma_ret; 1794df828598SMugunthan V N } 1795df828598SMugunthan V N 1796df828598SMugunthan V N ale_params.dev = &ndev->dev; 1797df828598SMugunthan V N ale_params.ale_ageout = ale_ageout; 1798df828598SMugunthan V N ale_params.ale_entries = data->ale_entries; 1799df828598SMugunthan V N ale_params.ale_ports = data->slaves; 1800df828598SMugunthan V N 1801df828598SMugunthan V N priv->ale = cpsw_ale_create(&ale_params); 1802df828598SMugunthan V N if (!priv->ale) { 1803df828598SMugunthan V N dev_err(priv->dev, "error initializing ale engine\n"); 1804df828598SMugunthan V N ret = -ENODEV; 1805df828598SMugunthan V N goto clean_dma_ret; 1806df828598SMugunthan V N } 1807df828598SMugunthan V N 1808df828598SMugunthan V N ndev->irq = platform_get_irq(pdev, 0); 1809df828598SMugunthan V N if (ndev->irq < 0) { 1810df828598SMugunthan V N dev_err(priv->dev, "error getting irq resource\n"); 1811df828598SMugunthan V N ret = -ENOENT; 1812df828598SMugunthan V N goto clean_ale_ret; 1813df828598SMugunthan V N } 1814df828598SMugunthan V N 1815df828598SMugunthan V N while ((res = platform_get_resource(priv->pdev, IORESOURCE_IRQ, k))) { 1816df828598SMugunthan V N for (i = res->start; i <= res->end; i++) { 1817df828598SMugunthan V N if (request_irq(i, cpsw_interrupt, IRQF_DISABLED, 1818df828598SMugunthan V N dev_name(&pdev->dev), priv)) { 1819df828598SMugunthan V N dev_err(priv->dev, "error attaching irq\n"); 1820df828598SMugunthan V N goto clean_ale_ret; 1821df828598SMugunthan V N } 1822df828598SMugunthan V N priv->irqs_table[k] = i; 1823df828598SMugunthan V N priv->num_irqs = k; 1824df828598SMugunthan V N } 1825df828598SMugunthan V N k++; 1826df828598SMugunthan V N } 1827df828598SMugunthan V N 18283b72c2feSMugunthan V N ndev->features |= NETIF_F_HW_VLAN_FILTER; 1829df828598SMugunthan V N 1830df828598SMugunthan V N ndev->netdev_ops = &cpsw_netdev_ops; 1831df828598SMugunthan V N SET_ETHTOOL_OPS(ndev, &cpsw_ethtool_ops); 1832df828598SMugunthan V N netif_napi_add(ndev, &priv->napi, cpsw_poll, CPSW_POLL_WEIGHT); 1833df828598SMugunthan V N 1834df828598SMugunthan V N /* register the network device */ 1835df828598SMugunthan V N SET_NETDEV_DEV(ndev, &pdev->dev); 1836df828598SMugunthan V N ret = register_netdev(ndev); 1837df828598SMugunthan V N if (ret) { 1838df828598SMugunthan V N dev_err(priv->dev, "error registering net device\n"); 1839df828598SMugunthan V N ret = -ENODEV; 1840df828598SMugunthan V N goto clean_irq_ret; 1841df828598SMugunthan V N } 1842df828598SMugunthan V N 18439232b16dSMugunthan V N if (cpts_register(&pdev->dev, priv->cpts, 18442e5b38abSRichard Cochran data->cpts_clock_mult, data->cpts_clock_shift)) 18452e5b38abSRichard Cochran dev_err(priv->dev, "error registering cpts device\n"); 18462e5b38abSRichard Cochran 1847df828598SMugunthan V N cpsw_notice(priv, probe, "initialized device (regs %x, irq %d)\n", 1848df828598SMugunthan V N priv->cpsw_res->start, ndev->irq); 1849df828598SMugunthan V N 1850d9ba8f9eSMugunthan V N if (priv->data.dual_emac) { 1851d9ba8f9eSMugunthan V N ret = cpsw_probe_dual_emac(pdev, priv); 1852d9ba8f9eSMugunthan V N if (ret) { 1853d9ba8f9eSMugunthan V N cpsw_err(priv, probe, "error probe slave 2 emac interface\n"); 1854d9ba8f9eSMugunthan V N goto clean_irq_ret; 1855d9ba8f9eSMugunthan V N } 1856d9ba8f9eSMugunthan V N } 1857d9ba8f9eSMugunthan V N 1858df828598SMugunthan V N return 0; 1859df828598SMugunthan V N 1860df828598SMugunthan V N clean_irq_ret: 1861df828598SMugunthan V N free_irq(ndev->irq, priv); 1862df828598SMugunthan V N clean_ale_ret: 1863df828598SMugunthan V N cpsw_ale_destroy(priv->ale); 1864df828598SMugunthan V N clean_dma_ret: 1865df828598SMugunthan V N cpdma_chan_destroy(priv->txch); 1866df828598SMugunthan V N cpdma_chan_destroy(priv->rxch); 1867df828598SMugunthan V N cpdma_ctlr_destroy(priv->dma); 18685250c969SRichard Cochran clean_wr_iomap_ret: 18695250c969SRichard Cochran iounmap(priv->wr_regs); 1870a65dd5b2SRichard Cochran clean_cpsw_wr_iores_ret: 1871a65dd5b2SRichard Cochran release_mem_region(priv->cpsw_wr_res->start, 1872a65dd5b2SRichard Cochran resource_size(priv->cpsw_wr_res)); 18735250c969SRichard Cochran clean_iomap_ret: 18745250c969SRichard Cochran iounmap(priv->regs); 1875df828598SMugunthan V N clean_cpsw_iores_ret: 1876df828598SMugunthan V N release_mem_region(priv->cpsw_res->start, 1877df828598SMugunthan V N resource_size(priv->cpsw_res)); 1878df828598SMugunthan V N clean_clk_ret: 1879df828598SMugunthan V N clk_put(priv->clk); 1880f150bd7fSMugunthan V N clean_slave_ret: 1881f150bd7fSMugunthan V N pm_runtime_disable(&pdev->dev); 1882df828598SMugunthan V N kfree(priv->slaves); 1883df828598SMugunthan V N clean_ndev_ret: 1884df828598SMugunthan V N free_netdev(ndev); 1885df828598SMugunthan V N return ret; 1886df828598SMugunthan V N } 1887df828598SMugunthan V N 1888663e12e6SBill Pemberton static int cpsw_remove(struct platform_device *pdev) 1889df828598SMugunthan V N { 1890df828598SMugunthan V N struct net_device *ndev = platform_get_drvdata(pdev); 1891df828598SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 1892df828598SMugunthan V N 1893df828598SMugunthan V N pr_info("removing device"); 1894df828598SMugunthan V N platform_set_drvdata(pdev, NULL); 1895df828598SMugunthan V N 18969232b16dSMugunthan V N cpts_unregister(priv->cpts); 1897df828598SMugunthan V N free_irq(ndev->irq, priv); 1898df828598SMugunthan V N cpsw_ale_destroy(priv->ale); 1899df828598SMugunthan V N cpdma_chan_destroy(priv->txch); 1900df828598SMugunthan V N cpdma_chan_destroy(priv->rxch); 1901df828598SMugunthan V N cpdma_ctlr_destroy(priv->dma); 1902df828598SMugunthan V N iounmap(priv->regs); 1903df828598SMugunthan V N release_mem_region(priv->cpsw_res->start, 1904df828598SMugunthan V N resource_size(priv->cpsw_res)); 19055250c969SRichard Cochran iounmap(priv->wr_regs); 1906a65dd5b2SRichard Cochran release_mem_region(priv->cpsw_wr_res->start, 1907a65dd5b2SRichard Cochran resource_size(priv->cpsw_wr_res)); 1908f150bd7fSMugunthan V N pm_runtime_disable(&pdev->dev); 1909df828598SMugunthan V N clk_put(priv->clk); 1910df828598SMugunthan V N kfree(priv->slaves); 1911df828598SMugunthan V N free_netdev(ndev); 1912df828598SMugunthan V N 1913df828598SMugunthan V N return 0; 1914df828598SMugunthan V N } 1915df828598SMugunthan V N 1916df828598SMugunthan V N static int cpsw_suspend(struct device *dev) 1917df828598SMugunthan V N { 1918df828598SMugunthan V N struct platform_device *pdev = to_platform_device(dev); 1919df828598SMugunthan V N struct net_device *ndev = platform_get_drvdata(pdev); 1920df828598SMugunthan V N 1921df828598SMugunthan V N if (netif_running(ndev)) 1922df828598SMugunthan V N cpsw_ndo_stop(ndev); 1923f150bd7fSMugunthan V N pm_runtime_put_sync(&pdev->dev); 1924f150bd7fSMugunthan V N 1925df828598SMugunthan V N return 0; 1926df828598SMugunthan V N } 1927df828598SMugunthan V N 1928df828598SMugunthan V N static int cpsw_resume(struct device *dev) 1929df828598SMugunthan V N { 1930df828598SMugunthan V N struct platform_device *pdev = to_platform_device(dev); 1931df828598SMugunthan V N struct net_device *ndev = platform_get_drvdata(pdev); 1932df828598SMugunthan V N 1933f150bd7fSMugunthan V N pm_runtime_get_sync(&pdev->dev); 1934df828598SMugunthan V N if (netif_running(ndev)) 1935df828598SMugunthan V N cpsw_ndo_open(ndev); 1936df828598SMugunthan V N return 0; 1937df828598SMugunthan V N } 1938df828598SMugunthan V N 1939df828598SMugunthan V N static const struct dev_pm_ops cpsw_pm_ops = { 1940df828598SMugunthan V N .suspend = cpsw_suspend, 1941df828598SMugunthan V N .resume = cpsw_resume, 1942df828598SMugunthan V N }; 1943df828598SMugunthan V N 19442eb32b0aSMugunthan V N static const struct of_device_id cpsw_of_mtable[] = { 19452eb32b0aSMugunthan V N { .compatible = "ti,cpsw", }, 19462eb32b0aSMugunthan V N { /* sentinel */ }, 19472eb32b0aSMugunthan V N }; 19482eb32b0aSMugunthan V N 1949df828598SMugunthan V N static struct platform_driver cpsw_driver = { 1950df828598SMugunthan V N .driver = { 1951df828598SMugunthan V N .name = "cpsw", 1952df828598SMugunthan V N .owner = THIS_MODULE, 1953df828598SMugunthan V N .pm = &cpsw_pm_ops, 19542eb32b0aSMugunthan V N .of_match_table = of_match_ptr(cpsw_of_mtable), 1955df828598SMugunthan V N }, 1956df828598SMugunthan V N .probe = cpsw_probe, 1957663e12e6SBill Pemberton .remove = cpsw_remove, 1958df828598SMugunthan V N }; 1959df828598SMugunthan V N 1960df828598SMugunthan V N static int __init cpsw_init(void) 1961df828598SMugunthan V N { 1962df828598SMugunthan V N return platform_driver_register(&cpsw_driver); 1963df828598SMugunthan V N } 1964df828598SMugunthan V N late_initcall(cpsw_init); 1965df828598SMugunthan V N 1966df828598SMugunthan V N static void __exit cpsw_exit(void) 1967df828598SMugunthan V N { 1968df828598SMugunthan V N platform_driver_unregister(&cpsw_driver); 1969df828598SMugunthan V N } 1970df828598SMugunthan V N module_exit(cpsw_exit); 1971df828598SMugunthan V N 1972df828598SMugunthan V N MODULE_LICENSE("GPL"); 1973df828598SMugunthan V N MODULE_AUTHOR("Cyril Chemparathy <cyril@ti.com>"); 1974df828598SMugunthan V N MODULE_AUTHOR("Mugunthan V N <mugunthanvnm@ti.com>"); 1975df828598SMugunthan V N MODULE_DESCRIPTION("TI CPSW Ethernet driver"); 1976