1df828598SMugunthan V N /* 2df828598SMugunthan V N * Texas Instruments Ethernet Switch Driver 3df828598SMugunthan V N * 4df828598SMugunthan V N * Copyright (C) 2012 Texas Instruments 5df828598SMugunthan V N * 6df828598SMugunthan V N * This program is free software; you can redistribute it and/or 7df828598SMugunthan V N * modify it under the terms of the GNU General Public License as 8df828598SMugunthan V N * published by the Free Software Foundation version 2. 9df828598SMugunthan V N * 10df828598SMugunthan V N * This program is distributed "as is" WITHOUT ANY WARRANTY of any 11df828598SMugunthan V N * kind, whether express or implied; without even the implied warranty 12df828598SMugunthan V N * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13df828598SMugunthan V N * GNU General Public License for more details. 14df828598SMugunthan V N */ 15df828598SMugunthan V N 16df828598SMugunthan V N #include <linux/kernel.h> 17df828598SMugunthan V N #include <linux/io.h> 18df828598SMugunthan V N #include <linux/clk.h> 19df828598SMugunthan V N #include <linux/timer.h> 20df828598SMugunthan V N #include <linux/module.h> 21df828598SMugunthan V N #include <linux/platform_device.h> 22df828598SMugunthan V N #include <linux/irqreturn.h> 23df828598SMugunthan V N #include <linux/interrupt.h> 24df828598SMugunthan V N #include <linux/if_ether.h> 25df828598SMugunthan V N #include <linux/etherdevice.h> 26df828598SMugunthan V N #include <linux/netdevice.h> 272e5b38abSRichard Cochran #include <linux/net_tstamp.h> 28df828598SMugunthan V N #include <linux/phy.h> 29df828598SMugunthan V N #include <linux/workqueue.h> 30df828598SMugunthan V N #include <linux/delay.h> 31f150bd7fSMugunthan V N #include <linux/pm_runtime.h> 32e2b3e493SArnd Bergmann #include <linux/gpio/consumer.h> 332eb32b0aSMugunthan V N #include <linux/of.h> 349e42f715SHeiko Schocher #include <linux/of_mdio.h> 352eb32b0aSMugunthan V N #include <linux/of_net.h> 362eb32b0aSMugunthan V N #include <linux/of_device.h> 373b72c2feSMugunthan V N #include <linux/if_vlan.h> 38514c6032SRandy Dunlap #include <linux/kmemleak.h> 399611d6d6SIvan Khoronzhuk #include <linux/sys_soc.h> 40df828598SMugunthan V N 41739683b4SMugunthan V N #include <linux/pinctrl/consumer.h> 427929a668SIvan Khoronzhuk #include <net/pkt_cls.h> 43df828598SMugunthan V N 44dbe34724SMugunthan V N #include "cpsw.h" 45df828598SMugunthan V N #include "cpsw_ale.h" 462e5b38abSRichard Cochran #include "cpts.h" 47df828598SMugunthan V N #include "davinci_cpdma.h" 48df828598SMugunthan V N 4957d90148SIvan Khoronzhuk #include <net/pkt_sched.h> 5057d90148SIvan Khoronzhuk 51df828598SMugunthan V N #define CPSW_DEBUG (NETIF_MSG_HW | NETIF_MSG_WOL | \ 52df828598SMugunthan V N NETIF_MSG_DRV | NETIF_MSG_LINK | \ 53df828598SMugunthan V N NETIF_MSG_IFUP | NETIF_MSG_INTR | \ 54df828598SMugunthan V N NETIF_MSG_PROBE | NETIF_MSG_TIMER | \ 55df828598SMugunthan V N NETIF_MSG_IFDOWN | NETIF_MSG_RX_ERR | \ 56df828598SMugunthan V N NETIF_MSG_TX_ERR | NETIF_MSG_TX_DONE | \ 57df828598SMugunthan V N NETIF_MSG_PKTDATA | NETIF_MSG_TX_QUEUED | \ 58df828598SMugunthan V N NETIF_MSG_RX_STATUS) 59df828598SMugunthan V N 60df828598SMugunthan V N #define cpsw_info(priv, type, format, ...) \ 61df828598SMugunthan V N do { \ 62df828598SMugunthan V N if (netif_msg_##type(priv) && net_ratelimit()) \ 63df828598SMugunthan V N dev_info(priv->dev, format, ## __VA_ARGS__); \ 64df828598SMugunthan V N } while (0) 65df828598SMugunthan V N 66df828598SMugunthan V N #define cpsw_err(priv, type, format, ...) \ 67df828598SMugunthan V N do { \ 68df828598SMugunthan V N if (netif_msg_##type(priv) && net_ratelimit()) \ 69df828598SMugunthan V N dev_err(priv->dev, format, ## __VA_ARGS__); \ 70df828598SMugunthan V N } while (0) 71df828598SMugunthan V N 72df828598SMugunthan V N #define cpsw_dbg(priv, type, format, ...) \ 73df828598SMugunthan V N do { \ 74df828598SMugunthan V N if (netif_msg_##type(priv) && net_ratelimit()) \ 75df828598SMugunthan V N dev_dbg(priv->dev, format, ## __VA_ARGS__); \ 76df828598SMugunthan V N } while (0) 77df828598SMugunthan V N 78df828598SMugunthan V N #define cpsw_notice(priv, type, format, ...) \ 79df828598SMugunthan V N do { \ 80df828598SMugunthan V N if (netif_msg_##type(priv) && net_ratelimit()) \ 81df828598SMugunthan V N dev_notice(priv->dev, format, ## __VA_ARGS__); \ 82df828598SMugunthan V N } while (0) 83df828598SMugunthan V N 845c50a856SMugunthan V N #define ALE_ALL_PORTS 0x7 855c50a856SMugunthan V N 86df828598SMugunthan V N #define CPSW_MAJOR_VERSION(reg) (reg >> 8 & 0x7) 87df828598SMugunthan V N #define CPSW_MINOR_VERSION(reg) (reg & 0xff) 88df828598SMugunthan V N #define CPSW_RTL_VERSION(reg) ((reg >> 11) & 0x1f) 89df828598SMugunthan V N 90e90cfac6SRichard Cochran #define CPSW_VERSION_1 0x19010a 91e90cfac6SRichard Cochran #define CPSW_VERSION_2 0x19010c 92c193f365SMugunthan V N #define CPSW_VERSION_3 0x19010f 93926489beSMugunthan V N #define CPSW_VERSION_4 0x190112 94549985eeSRichard Cochran 95549985eeSRichard Cochran #define HOST_PORT_NUM 0 96c6395f12SGrygorii Strashko #define CPSW_ALE_PORTS_NUM 3 97549985eeSRichard Cochran #define SLIVER_SIZE 0x40 98549985eeSRichard Cochran 99549985eeSRichard Cochran #define CPSW1_HOST_PORT_OFFSET 0x028 100549985eeSRichard Cochran #define CPSW1_SLAVE_OFFSET 0x050 101549985eeSRichard Cochran #define CPSW1_SLAVE_SIZE 0x040 102549985eeSRichard Cochran #define CPSW1_CPDMA_OFFSET 0x100 103549985eeSRichard Cochran #define CPSW1_STATERAM_OFFSET 0x200 104d9718546SMugunthan V N #define CPSW1_HW_STATS 0x400 105549985eeSRichard Cochran #define CPSW1_CPTS_OFFSET 0x500 106549985eeSRichard Cochran #define CPSW1_ALE_OFFSET 0x600 107549985eeSRichard Cochran #define CPSW1_SLIVER_OFFSET 0x700 108549985eeSRichard Cochran 109549985eeSRichard Cochran #define CPSW2_HOST_PORT_OFFSET 0x108 110549985eeSRichard Cochran #define CPSW2_SLAVE_OFFSET 0x200 111549985eeSRichard Cochran #define CPSW2_SLAVE_SIZE 0x100 112549985eeSRichard Cochran #define CPSW2_CPDMA_OFFSET 0x800 113d9718546SMugunthan V N #define CPSW2_HW_STATS 0x900 114549985eeSRichard Cochran #define CPSW2_STATERAM_OFFSET 0xa00 115549985eeSRichard Cochran #define CPSW2_CPTS_OFFSET 0xc00 116549985eeSRichard Cochran #define CPSW2_ALE_OFFSET 0xd00 117549985eeSRichard Cochran #define CPSW2_SLIVER_OFFSET 0xd80 118549985eeSRichard Cochran #define CPSW2_BD_OFFSET 0x2000 119549985eeSRichard Cochran 120df828598SMugunthan V N #define CPDMA_RXTHRESH 0x0c0 121df828598SMugunthan V N #define CPDMA_RXFREE 0x0e0 122df828598SMugunthan V N #define CPDMA_TXHDP 0x00 123df828598SMugunthan V N #define CPDMA_RXHDP 0x20 124df828598SMugunthan V N #define CPDMA_TXCP 0x40 125df828598SMugunthan V N #define CPDMA_RXCP 0x60 126df828598SMugunthan V N 127df828598SMugunthan V N #define CPSW_POLL_WEIGHT 64 128a3a41d2fSGrygorii Strashko #define CPSW_RX_VLAN_ENCAP_HDR_SIZE 4 1299421c901SGrygorii Strashko #define CPSW_MIN_PACKET_SIZE (VLAN_ETH_ZLEN) 130a3a41d2fSGrygorii Strashko #define CPSW_MAX_PACKET_SIZE (VLAN_ETH_FRAME_LEN +\ 131a3a41d2fSGrygorii Strashko ETH_FCS_LEN +\ 132a3a41d2fSGrygorii Strashko CPSW_RX_VLAN_ENCAP_HDR_SIZE) 133df828598SMugunthan V N 134df828598SMugunthan V N #define RX_PRIORITY_MAPPING 0x76543210 135df828598SMugunthan V N #define TX_PRIORITY_MAPPING 0x33221100 1365e391dc5SIvan Khoronzhuk #define CPDMA_TX_PRIORITY_MAP 0x76543210 137df828598SMugunthan V N 1383b72c2feSMugunthan V N #define CPSW_VLAN_AWARE BIT(1) 139a3a41d2fSGrygorii Strashko #define CPSW_RX_VLAN_ENCAP BIT(2) 1403b72c2feSMugunthan V N #define CPSW_ALE_VLAN_AWARE 1 1413b72c2feSMugunthan V N 14235717d8dSJohn Ogness #define CPSW_FIFO_NORMAL_MODE (0 << 16) 14335717d8dSJohn Ogness #define CPSW_FIFO_DUAL_MAC_MODE (1 << 16) 14435717d8dSJohn Ogness #define CPSW_FIFO_RATE_LIMIT_MODE (2 << 16) 145d9ba8f9eSMugunthan V N 146ff5b8ef2SMugunthan V N #define CPSW_INTPACEEN (0x3f << 16) 147ff5b8ef2SMugunthan V N #define CPSW_INTPRESCALE_MASK (0x7FF << 0) 148ff5b8ef2SMugunthan V N #define CPSW_CMINTMAX_CNT 63 149ff5b8ef2SMugunthan V N #define CPSW_CMINTMIN_CNT 2 150ff5b8ef2SMugunthan V N #define CPSW_CMINTMAX_INTVL (1000 / CPSW_CMINTMIN_CNT) 151ff5b8ef2SMugunthan V N #define CPSW_CMINTMIN_INTVL ((1000 / CPSW_CMINTMAX_CNT) + 1) 152ff5b8ef2SMugunthan V N 153606f3993SIvan Khoronzhuk #define cpsw_slave_index(cpsw, priv) \ 154606f3993SIvan Khoronzhuk ((cpsw->data.dual_emac) ? priv->emac_port : \ 155606f3993SIvan Khoronzhuk cpsw->data.active_slave) 156e38b5a3dSIvan Khoronzhuk #define IRQ_NUM 2 157e05107e6SIvan Khoronzhuk #define CPSW_MAX_QUEUES 8 15890225bf0SGrygorii Strashko #define CPSW_CPDMA_DESCS_POOL_SIZE_DEFAULT 256 15957d90148SIvan Khoronzhuk #define CPSW_FIFO_QUEUE_TYPE_SHIFT 16 16057d90148SIvan Khoronzhuk #define CPSW_FIFO_SHAPE_EN_SHIFT 16 16157d90148SIvan Khoronzhuk #define CPSW_FIFO_RATE_EN_SHIFT 20 1627929a668SIvan Khoronzhuk #define CPSW_TC_NUM 4 1637929a668SIvan Khoronzhuk #define CPSW_FIFO_SHAPERS_NUM (CPSW_TC_NUM - 1) 16457d90148SIvan Khoronzhuk #define CPSW_PCT_MASK 0x7f 165d3bb9c58SMugunthan V N 166a3a41d2fSGrygorii Strashko #define CPSW_RX_VLAN_ENCAP_HDR_PRIO_SHIFT 29 167a3a41d2fSGrygorii Strashko #define CPSW_RX_VLAN_ENCAP_HDR_PRIO_MSK GENMASK(2, 0) 168a3a41d2fSGrygorii Strashko #define CPSW_RX_VLAN_ENCAP_HDR_VID_SHIFT 16 169a3a41d2fSGrygorii Strashko #define CPSW_RX_VLAN_ENCAP_HDR_PKT_TYPE_SHIFT 8 170a3a41d2fSGrygorii Strashko #define CPSW_RX_VLAN_ENCAP_HDR_PKT_TYPE_MSK GENMASK(1, 0) 171a3a41d2fSGrygorii Strashko enum { 172a3a41d2fSGrygorii Strashko CPSW_RX_VLAN_ENCAP_HDR_PKT_VLAN_TAG = 0, 173a3a41d2fSGrygorii Strashko CPSW_RX_VLAN_ENCAP_HDR_PKT_RESERV, 174a3a41d2fSGrygorii Strashko CPSW_RX_VLAN_ENCAP_HDR_PKT_PRIO_TAG, 175a3a41d2fSGrygorii Strashko CPSW_RX_VLAN_ENCAP_HDR_PKT_UNTAG, 176a3a41d2fSGrygorii Strashko }; 177a3a41d2fSGrygorii Strashko 178df828598SMugunthan V N static int debug_level; 179df828598SMugunthan V N module_param(debug_level, int, 0); 180df828598SMugunthan V N MODULE_PARM_DESC(debug_level, "cpsw debug level (NETIF_MSG bits)"); 181df828598SMugunthan V N 182df828598SMugunthan V N static int ale_ageout = 10; 183df828598SMugunthan V N module_param(ale_ageout, int, 0); 184df828598SMugunthan V N MODULE_PARM_DESC(ale_ageout, "cpsw ale ageout interval (seconds)"); 185df828598SMugunthan V N 186df828598SMugunthan V N static int rx_packet_max = CPSW_MAX_PACKET_SIZE; 187df828598SMugunthan V N module_param(rx_packet_max, int, 0); 188df828598SMugunthan V N MODULE_PARM_DESC(rx_packet_max, "maximum receive packet size (bytes)"); 189df828598SMugunthan V N 19090225bf0SGrygorii Strashko static int descs_pool_size = CPSW_CPDMA_DESCS_POOL_SIZE_DEFAULT; 19190225bf0SGrygorii Strashko module_param(descs_pool_size, int, 0444); 19290225bf0SGrygorii Strashko MODULE_PARM_DESC(descs_pool_size, "Number of CPDMA CPPI descriptors in pool"); 19390225bf0SGrygorii Strashko 194996a5c27SRichard Cochran struct cpsw_wr_regs { 195df828598SMugunthan V N u32 id_ver; 196df828598SMugunthan V N u32 soft_reset; 197df828598SMugunthan V N u32 control; 198df828598SMugunthan V N u32 int_control; 199df828598SMugunthan V N u32 rx_thresh_en; 200df828598SMugunthan V N u32 rx_en; 201df828598SMugunthan V N u32 tx_en; 202df828598SMugunthan V N u32 misc_en; 203ff5b8ef2SMugunthan V N u32 mem_allign1[8]; 204ff5b8ef2SMugunthan V N u32 rx_thresh_stat; 205ff5b8ef2SMugunthan V N u32 rx_stat; 206ff5b8ef2SMugunthan V N u32 tx_stat; 207ff5b8ef2SMugunthan V N u32 misc_stat; 208ff5b8ef2SMugunthan V N u32 mem_allign2[8]; 209ff5b8ef2SMugunthan V N u32 rx_imax; 210ff5b8ef2SMugunthan V N u32 tx_imax; 211ff5b8ef2SMugunthan V N 212df828598SMugunthan V N }; 213df828598SMugunthan V N 214996a5c27SRichard Cochran struct cpsw_ss_regs { 215df828598SMugunthan V N u32 id_ver; 216df828598SMugunthan V N u32 control; 217df828598SMugunthan V N u32 soft_reset; 218df828598SMugunthan V N u32 stat_port_en; 219df828598SMugunthan V N u32 ptype; 220bd357af2SRichard Cochran u32 soft_idle; 221bd357af2SRichard Cochran u32 thru_rate; 222bd357af2SRichard Cochran u32 gap_thresh; 223bd357af2SRichard Cochran u32 tx_start_wds; 224bd357af2SRichard Cochran u32 flow_control; 225bd357af2SRichard Cochran u32 vlan_ltype; 226bd357af2SRichard Cochran u32 ts_ltype; 227bd357af2SRichard Cochran u32 dlr_ltype; 228df828598SMugunthan V N }; 229df828598SMugunthan V N 2309750a3adSRichard Cochran /* CPSW_PORT_V1 */ 2319750a3adSRichard Cochran #define CPSW1_MAX_BLKS 0x00 /* Maximum FIFO Blocks */ 2329750a3adSRichard Cochran #define CPSW1_BLK_CNT 0x04 /* FIFO Block Usage Count (Read Only) */ 2339750a3adSRichard Cochran #define CPSW1_TX_IN_CTL 0x08 /* Transmit FIFO Control */ 2349750a3adSRichard Cochran #define CPSW1_PORT_VLAN 0x0c /* VLAN Register */ 2359750a3adSRichard Cochran #define CPSW1_TX_PRI_MAP 0x10 /* Tx Header Priority to Switch Pri Mapping */ 2369750a3adSRichard Cochran #define CPSW1_TS_CTL 0x14 /* Time Sync Control */ 2379750a3adSRichard Cochran #define CPSW1_TS_SEQ_LTYPE 0x18 /* Time Sync Sequence ID Offset and Msg Type */ 2389750a3adSRichard Cochran #define CPSW1_TS_VLAN 0x1c /* Time Sync VLAN1 and VLAN2 */ 2399750a3adSRichard Cochran 2409750a3adSRichard Cochran /* CPSW_PORT_V2 */ 2419750a3adSRichard Cochran #define CPSW2_CONTROL 0x00 /* Control Register */ 2429750a3adSRichard Cochran #define CPSW2_MAX_BLKS 0x08 /* Maximum FIFO Blocks */ 2439750a3adSRichard Cochran #define CPSW2_BLK_CNT 0x0c /* FIFO Block Usage Count (Read Only) */ 2449750a3adSRichard Cochran #define CPSW2_TX_IN_CTL 0x10 /* Transmit FIFO Control */ 2459750a3adSRichard Cochran #define CPSW2_PORT_VLAN 0x14 /* VLAN Register */ 2469750a3adSRichard Cochran #define CPSW2_TX_PRI_MAP 0x18 /* Tx Header Priority to Switch Pri Mapping */ 2479750a3adSRichard Cochran #define CPSW2_TS_SEQ_MTYPE 0x1c /* Time Sync Sequence ID Offset and Msg Type */ 2489750a3adSRichard Cochran 2499750a3adSRichard Cochran /* CPSW_PORT_V1 and V2 */ 2509750a3adSRichard Cochran #define SA_LO 0x20 /* CPGMAC_SL Source Address Low */ 2519750a3adSRichard Cochran #define SA_HI 0x24 /* CPGMAC_SL Source Address High */ 2529750a3adSRichard Cochran #define SEND_PERCENT 0x28 /* Transmit Queue Send Percentages */ 2539750a3adSRichard Cochran 2549750a3adSRichard Cochran /* CPSW_PORT_V2 only */ 2559750a3adSRichard Cochran #define RX_DSCP_PRI_MAP0 0x30 /* Rx DSCP Priority to Rx Packet Mapping */ 2569750a3adSRichard Cochran #define RX_DSCP_PRI_MAP1 0x34 /* Rx DSCP Priority to Rx Packet Mapping */ 2579750a3adSRichard Cochran #define RX_DSCP_PRI_MAP2 0x38 /* Rx DSCP Priority to Rx Packet Mapping */ 2589750a3adSRichard Cochran #define RX_DSCP_PRI_MAP3 0x3c /* Rx DSCP Priority to Rx Packet Mapping */ 2599750a3adSRichard Cochran #define RX_DSCP_PRI_MAP4 0x40 /* Rx DSCP Priority to Rx Packet Mapping */ 2609750a3adSRichard Cochran #define RX_DSCP_PRI_MAP5 0x44 /* Rx DSCP Priority to Rx Packet Mapping */ 2619750a3adSRichard Cochran #define RX_DSCP_PRI_MAP6 0x48 /* Rx DSCP Priority to Rx Packet Mapping */ 2629750a3adSRichard Cochran #define RX_DSCP_PRI_MAP7 0x4c /* Rx DSCP Priority to Rx Packet Mapping */ 2639750a3adSRichard Cochran 2649750a3adSRichard Cochran /* Bit definitions for the CPSW2_CONTROL register */ 2651239a96aSIvan Khoronzhuk #define PASS_PRI_TAGGED BIT(24) /* Pass Priority Tagged */ 2661239a96aSIvan Khoronzhuk #define VLAN_LTYPE2_EN BIT(21) /* VLAN LTYPE 2 enable */ 2671239a96aSIvan Khoronzhuk #define VLAN_LTYPE1_EN BIT(20) /* VLAN LTYPE 1 enable */ 2681239a96aSIvan Khoronzhuk #define DSCP_PRI_EN BIT(16) /* DSCP Priority Enable */ 2691c0e8123SIvan Khoronzhuk #define TS_107 BIT(15) /* Tyme Sync Dest IP Address 107 */ 2701239a96aSIvan Khoronzhuk #define TS_320 BIT(14) /* Time Sync Dest Port 320 enable */ 2711239a96aSIvan Khoronzhuk #define TS_319 BIT(13) /* Time Sync Dest Port 319 enable */ 2721239a96aSIvan Khoronzhuk #define TS_132 BIT(12) /* Time Sync Dest IP Addr 132 enable */ 2731239a96aSIvan Khoronzhuk #define TS_131 BIT(11) /* Time Sync Dest IP Addr 131 enable */ 2741239a96aSIvan Khoronzhuk #define TS_130 BIT(10) /* Time Sync Dest IP Addr 130 enable */ 2751239a96aSIvan Khoronzhuk #define TS_129 BIT(9) /* Time Sync Dest IP Addr 129 enable */ 2761239a96aSIvan Khoronzhuk #define TS_TTL_NONZERO BIT(8) /* Time Sync Time To Live Non-zero enable */ 2771239a96aSIvan Khoronzhuk #define TS_ANNEX_F_EN BIT(6) /* Time Sync Annex F enable */ 2781239a96aSIvan Khoronzhuk #define TS_ANNEX_D_EN BIT(4) /* Time Sync Annex D enable */ 2791239a96aSIvan Khoronzhuk #define TS_LTYPE2_EN BIT(3) /* Time Sync LTYPE 2 enable */ 2801239a96aSIvan Khoronzhuk #define TS_LTYPE1_EN BIT(2) /* Time Sync LTYPE 1 enable */ 2811239a96aSIvan Khoronzhuk #define TS_TX_EN BIT(1) /* Time Sync Transmit Enable */ 2821239a96aSIvan Khoronzhuk #define TS_RX_EN BIT(0) /* Time Sync Receive Enable */ 2839750a3adSRichard Cochran 28409c55372SGeorge Cherian #define CTRL_V2_TS_BITS \ 28509c55372SGeorge Cherian (TS_320 | TS_319 | TS_132 | TS_131 | TS_130 | TS_129 |\ 28609c55372SGeorge Cherian TS_TTL_NONZERO | TS_ANNEX_D_EN | TS_LTYPE1_EN) 2879750a3adSRichard Cochran 28809c55372SGeorge Cherian #define CTRL_V2_ALL_TS_MASK (CTRL_V2_TS_BITS | TS_TX_EN | TS_RX_EN) 28909c55372SGeorge Cherian #define CTRL_V2_TX_TS_BITS (CTRL_V2_TS_BITS | TS_TX_EN) 29009c55372SGeorge Cherian #define CTRL_V2_RX_TS_BITS (CTRL_V2_TS_BITS | TS_RX_EN) 29109c55372SGeorge Cherian 29209c55372SGeorge Cherian 29309c55372SGeorge Cherian #define CTRL_V3_TS_BITS \ 2941c0e8123SIvan Khoronzhuk (TS_107 | TS_320 | TS_319 | TS_132 | TS_131 | TS_130 | TS_129 |\ 29509c55372SGeorge Cherian TS_TTL_NONZERO | TS_ANNEX_F_EN | TS_ANNEX_D_EN |\ 29609c55372SGeorge Cherian TS_LTYPE1_EN) 29709c55372SGeorge Cherian 29809c55372SGeorge Cherian #define CTRL_V3_ALL_TS_MASK (CTRL_V3_TS_BITS | TS_TX_EN | TS_RX_EN) 29909c55372SGeorge Cherian #define CTRL_V3_TX_TS_BITS (CTRL_V3_TS_BITS | TS_TX_EN) 30009c55372SGeorge Cherian #define CTRL_V3_RX_TS_BITS (CTRL_V3_TS_BITS | TS_RX_EN) 3019750a3adSRichard Cochran 3029750a3adSRichard Cochran /* Bit definitions for the CPSW2_TS_SEQ_MTYPE register */ 3039750a3adSRichard Cochran #define TS_SEQ_ID_OFFSET_SHIFT (16) /* Time Sync Sequence ID Offset */ 3049750a3adSRichard Cochran #define TS_SEQ_ID_OFFSET_MASK (0x3f) 3059750a3adSRichard Cochran #define TS_MSG_TYPE_EN_SHIFT (0) /* Time Sync Message Type Enable */ 3069750a3adSRichard Cochran #define TS_MSG_TYPE_EN_MASK (0xffff) 3079750a3adSRichard Cochran 3089750a3adSRichard Cochran /* The PTP event messages - Sync, Delay_Req, Pdelay_Req, and Pdelay_Resp. */ 3099750a3adSRichard Cochran #define EVENT_MSG_BITS ((1<<0) | (1<<1) | (1<<2) | (1<<3)) 310df828598SMugunthan V N 3112e5b38abSRichard Cochran /* Bit definitions for the CPSW1_TS_CTL register */ 3122e5b38abSRichard Cochran #define CPSW_V1_TS_RX_EN BIT(0) 3132e5b38abSRichard Cochran #define CPSW_V1_TS_TX_EN BIT(4) 3142e5b38abSRichard Cochran #define CPSW_V1_MSG_TYPE_OFS 16 3152e5b38abSRichard Cochran 3162e5b38abSRichard Cochran /* Bit definitions for the CPSW1_TS_SEQ_LTYPE register */ 3172e5b38abSRichard Cochran #define CPSW_V1_SEQ_ID_OFS_SHIFT 16 3182e5b38abSRichard Cochran 31948f5bcccSGrygorii Strashko #define CPSW_MAX_BLKS_TX 15 32048f5bcccSGrygorii Strashko #define CPSW_MAX_BLKS_TX_SHIFT 4 32148f5bcccSGrygorii Strashko #define CPSW_MAX_BLKS_RX 5 32248f5bcccSGrygorii Strashko 323df828598SMugunthan V N struct cpsw_host_regs { 324df828598SMugunthan V N u32 max_blks; 325df828598SMugunthan V N u32 blk_cnt; 326d9ba8f9eSMugunthan V N u32 tx_in_ctl; 327df828598SMugunthan V N u32 port_vlan; 328df828598SMugunthan V N u32 tx_pri_map; 329df828598SMugunthan V N u32 cpdma_tx_pri_map; 330df828598SMugunthan V N u32 cpdma_rx_chan_map; 331df828598SMugunthan V N }; 332df828598SMugunthan V N 333df828598SMugunthan V N struct cpsw_sliver_regs { 334df828598SMugunthan V N u32 id_ver; 335df828598SMugunthan V N u32 mac_control; 336df828598SMugunthan V N u32 mac_status; 337df828598SMugunthan V N u32 soft_reset; 338df828598SMugunthan V N u32 rx_maxlen; 339df828598SMugunthan V N u32 __reserved_0; 340df828598SMugunthan V N u32 rx_pause; 341df828598SMugunthan V N u32 tx_pause; 342df828598SMugunthan V N u32 __reserved_1; 343df828598SMugunthan V N u32 rx_pri_map; 344df828598SMugunthan V N }; 345df828598SMugunthan V N 346d9718546SMugunthan V N struct cpsw_hw_stats { 347d9718546SMugunthan V N u32 rxgoodframes; 348d9718546SMugunthan V N u32 rxbroadcastframes; 349d9718546SMugunthan V N u32 rxmulticastframes; 350d9718546SMugunthan V N u32 rxpauseframes; 351d9718546SMugunthan V N u32 rxcrcerrors; 352d9718546SMugunthan V N u32 rxaligncodeerrors; 353d9718546SMugunthan V N u32 rxoversizedframes; 354d9718546SMugunthan V N u32 rxjabberframes; 355d9718546SMugunthan V N u32 rxundersizedframes; 356d9718546SMugunthan V N u32 rxfragments; 357d9718546SMugunthan V N u32 __pad_0[2]; 358d9718546SMugunthan V N u32 rxoctets; 359d9718546SMugunthan V N u32 txgoodframes; 360d9718546SMugunthan V N u32 txbroadcastframes; 361d9718546SMugunthan V N u32 txmulticastframes; 362d9718546SMugunthan V N u32 txpauseframes; 363d9718546SMugunthan V N u32 txdeferredframes; 364d9718546SMugunthan V N u32 txcollisionframes; 365d9718546SMugunthan V N u32 txsinglecollframes; 366d9718546SMugunthan V N u32 txmultcollframes; 367d9718546SMugunthan V N u32 txexcessivecollisions; 368d9718546SMugunthan V N u32 txlatecollisions; 369d9718546SMugunthan V N u32 txunderrun; 370d9718546SMugunthan V N u32 txcarriersenseerrors; 371d9718546SMugunthan V N u32 txoctets; 372d9718546SMugunthan V N u32 octetframes64; 373d9718546SMugunthan V N u32 octetframes65t127; 374d9718546SMugunthan V N u32 octetframes128t255; 375d9718546SMugunthan V N u32 octetframes256t511; 376d9718546SMugunthan V N u32 octetframes512t1023; 377d9718546SMugunthan V N u32 octetframes1024tup; 378d9718546SMugunthan V N u32 netoctets; 379d9718546SMugunthan V N u32 rxsofoverruns; 380d9718546SMugunthan V N u32 rxmofoverruns; 381d9718546SMugunthan V N u32 rxdmaoverruns; 382d9718546SMugunthan V N }; 383d9718546SMugunthan V N 3842c8a14d6SGrygorii Strashko struct cpsw_slave_data { 3852c8a14d6SGrygorii Strashko struct device_node *phy_node; 3862c8a14d6SGrygorii Strashko char phy_id[MII_BUS_ID_SIZE]; 3872c8a14d6SGrygorii Strashko int phy_if; 3882c8a14d6SGrygorii Strashko u8 mac_addr[ETH_ALEN]; 3892c8a14d6SGrygorii Strashko u16 dual_emac_res_vlan; /* Reserved VLAN for DualEMAC */ 3902c8a14d6SGrygorii Strashko }; 3912c8a14d6SGrygorii Strashko 3922c8a14d6SGrygorii Strashko struct cpsw_platform_data { 3932c8a14d6SGrygorii Strashko struct cpsw_slave_data *slave_data; 3942c8a14d6SGrygorii Strashko u32 ss_reg_ofs; /* Subsystem control register offset */ 3952c8a14d6SGrygorii Strashko u32 channels; /* number of cpdma channels (symmetric) */ 3962c8a14d6SGrygorii Strashko u32 slaves; /* number of slave cpgmac ports */ 3972c8a14d6SGrygorii Strashko u32 active_slave; /* time stamping, ethtool and SIOCGMIIPHY slave */ 3982c8a14d6SGrygorii Strashko u32 ale_entries; /* ale table size */ 3992c8a14d6SGrygorii Strashko u32 bd_ram_size; /*buffer descriptor ram size */ 4002c8a14d6SGrygorii Strashko u32 mac_control; /* Mac control register */ 4012c8a14d6SGrygorii Strashko u16 default_vlan; /* Def VLAN for ALE lookup in VLAN aware mode*/ 4022c8a14d6SGrygorii Strashko bool dual_emac; /* Enable Dual EMAC mode */ 4032c8a14d6SGrygorii Strashko }; 4042c8a14d6SGrygorii Strashko 405df828598SMugunthan V N struct cpsw_slave { 4069750a3adSRichard Cochran void __iomem *regs; 407df828598SMugunthan V N struct cpsw_sliver_regs __iomem *sliver; 408df828598SMugunthan V N int slave_num; 409df828598SMugunthan V N u32 mac_control; 410df828598SMugunthan V N struct cpsw_slave_data *data; 411df828598SMugunthan V N struct phy_device *phy; 412d9ba8f9eSMugunthan V N struct net_device *ndev; 413d9ba8f9eSMugunthan V N u32 port_vlan; 414df828598SMugunthan V N }; 415df828598SMugunthan V N 4169750a3adSRichard Cochran static inline u32 slave_read(struct cpsw_slave *slave, u32 offset) 4179750a3adSRichard Cochran { 418dda5f5feSGrygorii Strashko return readl_relaxed(slave->regs + offset); 4199750a3adSRichard Cochran } 4209750a3adSRichard Cochran 4219750a3adSRichard Cochran static inline void slave_write(struct cpsw_slave *slave, u32 val, u32 offset) 4229750a3adSRichard Cochran { 423dda5f5feSGrygorii Strashko writel_relaxed(val, slave->regs + offset); 4249750a3adSRichard Cochran } 4259750a3adSRichard Cochran 4268feb0a19SIvan Khoronzhuk struct cpsw_vector { 4278feb0a19SIvan Khoronzhuk struct cpdma_chan *ch; 4288feb0a19SIvan Khoronzhuk int budget; 4298feb0a19SIvan Khoronzhuk }; 4308feb0a19SIvan Khoronzhuk 431649a1688SIvan Khoronzhuk struct cpsw_common { 43256e31bd8SIvan Khoronzhuk struct device *dev; 433606f3993SIvan Khoronzhuk struct cpsw_platform_data data; 434dbc4ec52SIvan Khoronzhuk struct napi_struct napi_rx; 435dbc4ec52SIvan Khoronzhuk struct napi_struct napi_tx; 4365d8d0d4dSIvan Khoronzhuk struct cpsw_ss_regs __iomem *regs; 4375d8d0d4dSIvan Khoronzhuk struct cpsw_wr_regs __iomem *wr_regs; 4385d8d0d4dSIvan Khoronzhuk u8 __iomem *hw_stats; 4395d8d0d4dSIvan Khoronzhuk struct cpsw_host_regs __iomem *host_port_regs; 4402a05a622SIvan Khoronzhuk u32 version; 4412a05a622SIvan Khoronzhuk u32 coal_intvl; 4422a05a622SIvan Khoronzhuk u32 bus_freq_mhz; 4432a05a622SIvan Khoronzhuk int rx_packet_max; 444606f3993SIvan Khoronzhuk struct cpsw_slave *slaves; 4452c836bd9SIvan Khoronzhuk struct cpdma_ctlr *dma; 4468feb0a19SIvan Khoronzhuk struct cpsw_vector txv[CPSW_MAX_QUEUES]; 4478feb0a19SIvan Khoronzhuk struct cpsw_vector rxv[CPSW_MAX_QUEUES]; 4482a05a622SIvan Khoronzhuk struct cpsw_ale *ale; 449e38b5a3dSIvan Khoronzhuk bool quirk_irq; 450e38b5a3dSIvan Khoronzhuk bool rx_irq_disabled; 451e38b5a3dSIvan Khoronzhuk bool tx_irq_disabled; 452e38b5a3dSIvan Khoronzhuk u32 irqs_table[IRQ_NUM]; 4532a05a622SIvan Khoronzhuk struct cpts *cpts; 454e05107e6SIvan Khoronzhuk int rx_ch_num, tx_ch_num; 4550be01b8eSIvan Khoronzhuk int speed; 456d5bc1613SIvan Khoronzhuk int usage_count; 457649a1688SIvan Khoronzhuk }; 458649a1688SIvan Khoronzhuk 459649a1688SIvan Khoronzhuk struct cpsw_priv { 460df828598SMugunthan V N struct net_device *ndev; 461df828598SMugunthan V N struct device *dev; 462df828598SMugunthan V N u32 msg_enable; 463df828598SMugunthan V N u8 mac_addr[ETH_ALEN]; 4641923d6e4SMugunthan V N bool rx_pause; 4651923d6e4SMugunthan V N bool tx_pause; 4667929a668SIvan Khoronzhuk bool mqprio_hw; 46757d90148SIvan Khoronzhuk int fifo_bw[CPSW_TC_NUM]; 46857d90148SIvan Khoronzhuk int shp_cfg_speed; 469d9ba8f9eSMugunthan V N u32 emac_port; 470649a1688SIvan Khoronzhuk struct cpsw_common *cpsw; 471df828598SMugunthan V N }; 472df828598SMugunthan V N 473d9718546SMugunthan V N struct cpsw_stats { 474d9718546SMugunthan V N char stat_string[ETH_GSTRING_LEN]; 475d9718546SMugunthan V N int type; 476d9718546SMugunthan V N int sizeof_stat; 477d9718546SMugunthan V N int stat_offset; 478d9718546SMugunthan V N }; 479d9718546SMugunthan V N 480d9718546SMugunthan V N enum { 481d9718546SMugunthan V N CPSW_STATS, 482d9718546SMugunthan V N CPDMA_RX_STATS, 483d9718546SMugunthan V N CPDMA_TX_STATS, 484d9718546SMugunthan V N }; 485d9718546SMugunthan V N 486d9718546SMugunthan V N #define CPSW_STAT(m) CPSW_STATS, \ 487d9718546SMugunthan V N sizeof(((struct cpsw_hw_stats *)0)->m), \ 488d9718546SMugunthan V N offsetof(struct cpsw_hw_stats, m) 489d9718546SMugunthan V N #define CPDMA_RX_STAT(m) CPDMA_RX_STATS, \ 490d9718546SMugunthan V N sizeof(((struct cpdma_chan_stats *)0)->m), \ 491d9718546SMugunthan V N offsetof(struct cpdma_chan_stats, m) 492d9718546SMugunthan V N #define CPDMA_TX_STAT(m) CPDMA_TX_STATS, \ 493d9718546SMugunthan V N sizeof(((struct cpdma_chan_stats *)0)->m), \ 494d9718546SMugunthan V N offsetof(struct cpdma_chan_stats, m) 495d9718546SMugunthan V N 496d9718546SMugunthan V N static const struct cpsw_stats cpsw_gstrings_stats[] = { 497d9718546SMugunthan V N { "Good Rx Frames", CPSW_STAT(rxgoodframes) }, 498d9718546SMugunthan V N { "Broadcast Rx Frames", CPSW_STAT(rxbroadcastframes) }, 499d9718546SMugunthan V N { "Multicast Rx Frames", CPSW_STAT(rxmulticastframes) }, 500d9718546SMugunthan V N { "Pause Rx Frames", CPSW_STAT(rxpauseframes) }, 501d9718546SMugunthan V N { "Rx CRC Errors", CPSW_STAT(rxcrcerrors) }, 502d9718546SMugunthan V N { "Rx Align/Code Errors", CPSW_STAT(rxaligncodeerrors) }, 503d9718546SMugunthan V N { "Oversize Rx Frames", CPSW_STAT(rxoversizedframes) }, 504d9718546SMugunthan V N { "Rx Jabbers", CPSW_STAT(rxjabberframes) }, 505d9718546SMugunthan V N { "Undersize (Short) Rx Frames", CPSW_STAT(rxundersizedframes) }, 506d9718546SMugunthan V N { "Rx Fragments", CPSW_STAT(rxfragments) }, 507d9718546SMugunthan V N { "Rx Octets", CPSW_STAT(rxoctets) }, 508d9718546SMugunthan V N { "Good Tx Frames", CPSW_STAT(txgoodframes) }, 509d9718546SMugunthan V N { "Broadcast Tx Frames", CPSW_STAT(txbroadcastframes) }, 510d9718546SMugunthan V N { "Multicast Tx Frames", CPSW_STAT(txmulticastframes) }, 511d9718546SMugunthan V N { "Pause Tx Frames", CPSW_STAT(txpauseframes) }, 512d9718546SMugunthan V N { "Deferred Tx Frames", CPSW_STAT(txdeferredframes) }, 513d9718546SMugunthan V N { "Collisions", CPSW_STAT(txcollisionframes) }, 514d9718546SMugunthan V N { "Single Collision Tx Frames", CPSW_STAT(txsinglecollframes) }, 515d9718546SMugunthan V N { "Multiple Collision Tx Frames", CPSW_STAT(txmultcollframes) }, 516d9718546SMugunthan V N { "Excessive Collisions", CPSW_STAT(txexcessivecollisions) }, 517d9718546SMugunthan V N { "Late Collisions", CPSW_STAT(txlatecollisions) }, 518d9718546SMugunthan V N { "Tx Underrun", CPSW_STAT(txunderrun) }, 519d9718546SMugunthan V N { "Carrier Sense Errors", CPSW_STAT(txcarriersenseerrors) }, 520d9718546SMugunthan V N { "Tx Octets", CPSW_STAT(txoctets) }, 521d9718546SMugunthan V N { "Rx + Tx 64 Octet Frames", CPSW_STAT(octetframes64) }, 522d9718546SMugunthan V N { "Rx + Tx 65-127 Octet Frames", CPSW_STAT(octetframes65t127) }, 523d9718546SMugunthan V N { "Rx + Tx 128-255 Octet Frames", CPSW_STAT(octetframes128t255) }, 524d9718546SMugunthan V N { "Rx + Tx 256-511 Octet Frames", CPSW_STAT(octetframes256t511) }, 525d9718546SMugunthan V N { "Rx + Tx 512-1023 Octet Frames", CPSW_STAT(octetframes512t1023) }, 526d9718546SMugunthan V N { "Rx + Tx 1024-Up Octet Frames", CPSW_STAT(octetframes1024tup) }, 527d9718546SMugunthan V N { "Net Octets", CPSW_STAT(netoctets) }, 528d9718546SMugunthan V N { "Rx Start of Frame Overruns", CPSW_STAT(rxsofoverruns) }, 529d9718546SMugunthan V N { "Rx Middle of Frame Overruns", CPSW_STAT(rxmofoverruns) }, 530d9718546SMugunthan V N { "Rx DMA Overruns", CPSW_STAT(rxdmaoverruns) }, 531d9718546SMugunthan V N }; 532d9718546SMugunthan V N 533e05107e6SIvan Khoronzhuk static const struct cpsw_stats cpsw_gstrings_ch_stats[] = { 534e05107e6SIvan Khoronzhuk { "head_enqueue", CPDMA_RX_STAT(head_enqueue) }, 535e05107e6SIvan Khoronzhuk { "tail_enqueue", CPDMA_RX_STAT(tail_enqueue) }, 536e05107e6SIvan Khoronzhuk { "pad_enqueue", CPDMA_RX_STAT(pad_enqueue) }, 537e05107e6SIvan Khoronzhuk { "misqueued", CPDMA_RX_STAT(misqueued) }, 538e05107e6SIvan Khoronzhuk { "desc_alloc_fail", CPDMA_RX_STAT(desc_alloc_fail) }, 539e05107e6SIvan Khoronzhuk { "pad_alloc_fail", CPDMA_RX_STAT(pad_alloc_fail) }, 540e05107e6SIvan Khoronzhuk { "runt_receive_buf", CPDMA_RX_STAT(runt_receive_buff) }, 541e05107e6SIvan Khoronzhuk { "runt_transmit_buf", CPDMA_RX_STAT(runt_transmit_buff) }, 542e05107e6SIvan Khoronzhuk { "empty_dequeue", CPDMA_RX_STAT(empty_dequeue) }, 543e05107e6SIvan Khoronzhuk { "busy_dequeue", CPDMA_RX_STAT(busy_dequeue) }, 544e05107e6SIvan Khoronzhuk { "good_dequeue", CPDMA_RX_STAT(good_dequeue) }, 545e05107e6SIvan Khoronzhuk { "requeue", CPDMA_RX_STAT(requeue) }, 546e05107e6SIvan Khoronzhuk { "teardown_dequeue", CPDMA_RX_STAT(teardown_dequeue) }, 547e05107e6SIvan Khoronzhuk }; 548e05107e6SIvan Khoronzhuk 549e05107e6SIvan Khoronzhuk #define CPSW_STATS_COMMON_LEN ARRAY_SIZE(cpsw_gstrings_stats) 550e05107e6SIvan Khoronzhuk #define CPSW_STATS_CH_LEN ARRAY_SIZE(cpsw_gstrings_ch_stats) 551d9718546SMugunthan V N 552649a1688SIvan Khoronzhuk #define ndev_to_cpsw(ndev) (((struct cpsw_priv *)netdev_priv(ndev))->cpsw) 553dbc4ec52SIvan Khoronzhuk #define napi_to_cpsw(napi) container_of(napi, struct cpsw_common, napi) 554df828598SMugunthan V N #define for_each_slave(priv, func, arg...) \ 555df828598SMugunthan V N do { \ 5566e6ceaedSSebastian Siewior struct cpsw_slave *slave; \ 557606f3993SIvan Khoronzhuk struct cpsw_common *cpsw = (priv)->cpsw; \ 5586e6ceaedSSebastian Siewior int n; \ 559606f3993SIvan Khoronzhuk if (cpsw->data.dual_emac) \ 560606f3993SIvan Khoronzhuk (func)((cpsw)->slaves + priv->emac_port, ##arg);\ 561d9ba8f9eSMugunthan V N else \ 562606f3993SIvan Khoronzhuk for (n = cpsw->data.slaves, \ 563606f3993SIvan Khoronzhuk slave = cpsw->slaves; \ 5646e6ceaedSSebastian Siewior n; n--) \ 5656e6ceaedSSebastian Siewior (func)(slave++, ##arg); \ 566df828598SMugunthan V N } while (0) 567d9ba8f9eSMugunthan V N 5686f1f5836SIvan Khoronzhuk static inline int cpsw_get_slave_port(u32 slave_num) 569d9ba8f9eSMugunthan V N { 570d9ba8f9eSMugunthan V N return slave_num + 1; 571d9ba8f9eSMugunthan V N } 572df828598SMugunthan V N 573fea49f60SIvan Khoronzhuk static void cpsw_add_mcast(struct cpsw_priv *priv, u8 *addr) 574fea49f60SIvan Khoronzhuk { 575fea49f60SIvan Khoronzhuk struct cpsw_common *cpsw = priv->cpsw; 576fea49f60SIvan Khoronzhuk 577fea49f60SIvan Khoronzhuk if (cpsw->data.dual_emac) { 578fea49f60SIvan Khoronzhuk struct cpsw_slave *slave = cpsw->slaves + priv->emac_port; 579fea49f60SIvan Khoronzhuk int slave_port = cpsw_get_slave_port(slave->slave_num); 580fea49f60SIvan Khoronzhuk 581fea49f60SIvan Khoronzhuk cpsw_ale_add_mcast(cpsw->ale, addr, 582fea49f60SIvan Khoronzhuk 1 << slave_port | ALE_PORT_HOST, 583fea49f60SIvan Khoronzhuk ALE_VLAN, slave->port_vlan, 0); 584fea49f60SIvan Khoronzhuk return; 585fea49f60SIvan Khoronzhuk } 586fea49f60SIvan Khoronzhuk 587fea49f60SIvan Khoronzhuk cpsw_ale_add_mcast(cpsw->ale, addr, ALE_ALL_PORTS, 0, 0, 0); 588fea49f60SIvan Khoronzhuk } 589fea49f60SIvan Khoronzhuk 5900cd8f9ccSMugunthan V N static void cpsw_set_promiscious(struct net_device *ndev, bool enable) 5910cd8f9ccSMugunthan V N { 5922a05a622SIvan Khoronzhuk struct cpsw_common *cpsw = ndev_to_cpsw(ndev); 5932a05a622SIvan Khoronzhuk struct cpsw_ale *ale = cpsw->ale; 5940cd8f9ccSMugunthan V N int i; 5950cd8f9ccSMugunthan V N 596606f3993SIvan Khoronzhuk if (cpsw->data.dual_emac) { 5970cd8f9ccSMugunthan V N bool flag = false; 5980cd8f9ccSMugunthan V N 5990cd8f9ccSMugunthan V N /* Enabling promiscuous mode for one interface will be 6000cd8f9ccSMugunthan V N * common for both the interface as the interface shares 6010cd8f9ccSMugunthan V N * the same hardware resource. 6020cd8f9ccSMugunthan V N */ 603606f3993SIvan Khoronzhuk for (i = 0; i < cpsw->data.slaves; i++) 604606f3993SIvan Khoronzhuk if (cpsw->slaves[i].ndev->flags & IFF_PROMISC) 6050cd8f9ccSMugunthan V N flag = true; 6060cd8f9ccSMugunthan V N 6070cd8f9ccSMugunthan V N if (!enable && flag) { 6080cd8f9ccSMugunthan V N enable = true; 6090cd8f9ccSMugunthan V N dev_err(&ndev->dev, "promiscuity not disabled as the other interface is still in promiscuity mode\n"); 6100cd8f9ccSMugunthan V N } 6110cd8f9ccSMugunthan V N 6120cd8f9ccSMugunthan V N if (enable) { 6130cd8f9ccSMugunthan V N /* Enable Bypass */ 6140cd8f9ccSMugunthan V N cpsw_ale_control_set(ale, 0, ALE_BYPASS, 1); 6150cd8f9ccSMugunthan V N 6160cd8f9ccSMugunthan V N dev_dbg(&ndev->dev, "promiscuity enabled\n"); 6170cd8f9ccSMugunthan V N } else { 6180cd8f9ccSMugunthan V N /* Disable Bypass */ 6190cd8f9ccSMugunthan V N cpsw_ale_control_set(ale, 0, ALE_BYPASS, 0); 6200cd8f9ccSMugunthan V N dev_dbg(&ndev->dev, "promiscuity disabled\n"); 6210cd8f9ccSMugunthan V N } 6220cd8f9ccSMugunthan V N } else { 6230cd8f9ccSMugunthan V N if (enable) { 6240cd8f9ccSMugunthan V N unsigned long timeout = jiffies + HZ; 6250cd8f9ccSMugunthan V N 6266f979eb3SLennart Sorensen /* Disable Learn for all ports (host is port 0 and slaves are port 1 and up */ 627606f3993SIvan Khoronzhuk for (i = 0; i <= cpsw->data.slaves; i++) { 6280cd8f9ccSMugunthan V N cpsw_ale_control_set(ale, i, 6290cd8f9ccSMugunthan V N ALE_PORT_NOLEARN, 1); 6300cd8f9ccSMugunthan V N cpsw_ale_control_set(ale, i, 6310cd8f9ccSMugunthan V N ALE_PORT_NO_SA_UPDATE, 1); 6320cd8f9ccSMugunthan V N } 6330cd8f9ccSMugunthan V N 6340cd8f9ccSMugunthan V N /* Clear All Untouched entries */ 6350cd8f9ccSMugunthan V N cpsw_ale_control_set(ale, 0, ALE_AGEOUT, 1); 6360cd8f9ccSMugunthan V N do { 6370cd8f9ccSMugunthan V N cpu_relax(); 6380cd8f9ccSMugunthan V N if (cpsw_ale_control_get(ale, 0, ALE_AGEOUT)) 6390cd8f9ccSMugunthan V N break; 6400cd8f9ccSMugunthan V N } while (time_after(timeout, jiffies)); 6410cd8f9ccSMugunthan V N cpsw_ale_control_set(ale, 0, ALE_AGEOUT, 1); 6420cd8f9ccSMugunthan V N 6430cd8f9ccSMugunthan V N /* Clear all mcast from ALE */ 64461f1cef9SGrygorii Strashko cpsw_ale_flush_multicast(ale, ALE_ALL_PORTS, -1); 6450cd8f9ccSMugunthan V N 6460cd8f9ccSMugunthan V N /* Flood All Unicast Packets to Host port */ 6470cd8f9ccSMugunthan V N cpsw_ale_control_set(ale, 0, ALE_P0_UNI_FLOOD, 1); 6480cd8f9ccSMugunthan V N dev_dbg(&ndev->dev, "promiscuity enabled\n"); 6490cd8f9ccSMugunthan V N } else { 6506f979eb3SLennart Sorensen /* Don't Flood All Unicast Packets to Host port */ 6510cd8f9ccSMugunthan V N cpsw_ale_control_set(ale, 0, ALE_P0_UNI_FLOOD, 0); 6520cd8f9ccSMugunthan V N 6536f979eb3SLennart Sorensen /* Enable Learn for all ports (host is port 0 and slaves are port 1 and up */ 654606f3993SIvan Khoronzhuk for (i = 0; i <= cpsw->data.slaves; i++) { 6550cd8f9ccSMugunthan V N cpsw_ale_control_set(ale, i, 6560cd8f9ccSMugunthan V N ALE_PORT_NOLEARN, 0); 6570cd8f9ccSMugunthan V N cpsw_ale_control_set(ale, i, 6580cd8f9ccSMugunthan V N ALE_PORT_NO_SA_UPDATE, 0); 6590cd8f9ccSMugunthan V N } 6600cd8f9ccSMugunthan V N dev_dbg(&ndev->dev, "promiscuity disabled\n"); 6610cd8f9ccSMugunthan V N } 6620cd8f9ccSMugunthan V N } 6630cd8f9ccSMugunthan V N } 6640cd8f9ccSMugunthan V N 6655c50a856SMugunthan V N static void cpsw_ndo_set_rx_mode(struct net_device *ndev) 6665c50a856SMugunthan V N { 6675c50a856SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 668606f3993SIvan Khoronzhuk struct cpsw_common *cpsw = priv->cpsw; 66925906052SMugunthan V N int vid; 67025906052SMugunthan V N 671606f3993SIvan Khoronzhuk if (cpsw->data.dual_emac) 672606f3993SIvan Khoronzhuk vid = cpsw->slaves[priv->emac_port].port_vlan; 67325906052SMugunthan V N else 674606f3993SIvan Khoronzhuk vid = cpsw->data.default_vlan; 6755c50a856SMugunthan V N 6765c50a856SMugunthan V N if (ndev->flags & IFF_PROMISC) { 6775c50a856SMugunthan V N /* Enable promiscuous mode */ 6780cd8f9ccSMugunthan V N cpsw_set_promiscious(ndev, true); 6792a05a622SIvan Khoronzhuk cpsw_ale_set_allmulti(cpsw->ale, IFF_ALLMULTI); 6805c50a856SMugunthan V N return; 6810cd8f9ccSMugunthan V N } else { 6820cd8f9ccSMugunthan V N /* Disable promiscuous mode */ 6830cd8f9ccSMugunthan V N cpsw_set_promiscious(ndev, false); 6845c50a856SMugunthan V N } 6855c50a856SMugunthan V N 6861e5c4bc4SLennart Sorensen /* Restore allmulti on vlans if necessary */ 6872a05a622SIvan Khoronzhuk cpsw_ale_set_allmulti(cpsw->ale, priv->ndev->flags & IFF_ALLMULTI); 6881e5c4bc4SLennart Sorensen 6895c50a856SMugunthan V N /* Clear all mcast from ALE */ 6902a05a622SIvan Khoronzhuk cpsw_ale_flush_multicast(cpsw->ale, ALE_ALL_PORTS, vid); 6915c50a856SMugunthan V N 6925c50a856SMugunthan V N if (!netdev_mc_empty(ndev)) { 6935c50a856SMugunthan V N struct netdev_hw_addr *ha; 6945c50a856SMugunthan V N 6955c50a856SMugunthan V N /* program multicast address list into ALE register */ 6965c50a856SMugunthan V N netdev_for_each_mc_addr(ha, ndev) { 697fea49f60SIvan Khoronzhuk cpsw_add_mcast(priv, ha->addr); 6985c50a856SMugunthan V N } 6995c50a856SMugunthan V N } 7005c50a856SMugunthan V N } 7015c50a856SMugunthan V N 7022c836bd9SIvan Khoronzhuk static void cpsw_intr_enable(struct cpsw_common *cpsw) 703df828598SMugunthan V N { 704dda5f5feSGrygorii Strashko writel_relaxed(0xFF, &cpsw->wr_regs->tx_en); 705dda5f5feSGrygorii Strashko writel_relaxed(0xFF, &cpsw->wr_regs->rx_en); 706df828598SMugunthan V N 7072c836bd9SIvan Khoronzhuk cpdma_ctlr_int_ctrl(cpsw->dma, true); 708df828598SMugunthan V N return; 709df828598SMugunthan V N } 710df828598SMugunthan V N 7112c836bd9SIvan Khoronzhuk static void cpsw_intr_disable(struct cpsw_common *cpsw) 712df828598SMugunthan V N { 713dda5f5feSGrygorii Strashko writel_relaxed(0, &cpsw->wr_regs->tx_en); 714dda5f5feSGrygorii Strashko writel_relaxed(0, &cpsw->wr_regs->rx_en); 715df828598SMugunthan V N 7162c836bd9SIvan Khoronzhuk cpdma_ctlr_int_ctrl(cpsw->dma, false); 717df828598SMugunthan V N return; 718df828598SMugunthan V N } 719df828598SMugunthan V N 7201a3b5056SOlof Johansson static void cpsw_tx_handler(void *token, int len, int status) 721df828598SMugunthan V N { 722e05107e6SIvan Khoronzhuk struct netdev_queue *txq; 723df828598SMugunthan V N struct sk_buff *skb = token; 724df828598SMugunthan V N struct net_device *ndev = skb->dev; 7252a05a622SIvan Khoronzhuk struct cpsw_common *cpsw = ndev_to_cpsw(ndev); 726df828598SMugunthan V N 727fae50823SMugunthan V N /* Check whether the queue is stopped due to stalled tx dma, if the 728fae50823SMugunthan V N * queue is stopped then start the queue as we have free desc for tx 729fae50823SMugunthan V N */ 730e05107e6SIvan Khoronzhuk txq = netdev_get_tx_queue(ndev, skb_get_queue_mapping(skb)); 731e05107e6SIvan Khoronzhuk if (unlikely(netif_tx_queue_stopped(txq))) 732e05107e6SIvan Khoronzhuk netif_tx_wake_queue(txq); 733e05107e6SIvan Khoronzhuk 7342a05a622SIvan Khoronzhuk cpts_tx_timestamp(cpsw->cpts, skb); 7358dc43ddcSTobias Klauser ndev->stats.tx_packets++; 7368dc43ddcSTobias Klauser ndev->stats.tx_bytes += len; 737df828598SMugunthan V N dev_kfree_skb_any(skb); 738df828598SMugunthan V N } 739df828598SMugunthan V N 740a3a41d2fSGrygorii Strashko static void cpsw_rx_vlan_encap(struct sk_buff *skb) 741a3a41d2fSGrygorii Strashko { 742a3a41d2fSGrygorii Strashko struct cpsw_priv *priv = netdev_priv(skb->dev); 743a3a41d2fSGrygorii Strashko struct cpsw_common *cpsw = priv->cpsw; 744a3a41d2fSGrygorii Strashko u32 rx_vlan_encap_hdr = *((u32 *)skb->data); 745a3a41d2fSGrygorii Strashko u16 vtag, vid, prio, pkt_type; 746a3a41d2fSGrygorii Strashko 747a3a41d2fSGrygorii Strashko /* Remove VLAN header encapsulation word */ 748a3a41d2fSGrygorii Strashko skb_pull(skb, CPSW_RX_VLAN_ENCAP_HDR_SIZE); 749a3a41d2fSGrygorii Strashko 750a3a41d2fSGrygorii Strashko pkt_type = (rx_vlan_encap_hdr >> 751a3a41d2fSGrygorii Strashko CPSW_RX_VLAN_ENCAP_HDR_PKT_TYPE_SHIFT) & 752a3a41d2fSGrygorii Strashko CPSW_RX_VLAN_ENCAP_HDR_PKT_TYPE_MSK; 753a3a41d2fSGrygorii Strashko /* Ignore unknown & Priority-tagged packets*/ 754a3a41d2fSGrygorii Strashko if (pkt_type == CPSW_RX_VLAN_ENCAP_HDR_PKT_RESERV || 755a3a41d2fSGrygorii Strashko pkt_type == CPSW_RX_VLAN_ENCAP_HDR_PKT_PRIO_TAG) 756a3a41d2fSGrygorii Strashko return; 757a3a41d2fSGrygorii Strashko 758a3a41d2fSGrygorii Strashko vid = (rx_vlan_encap_hdr >> 759a3a41d2fSGrygorii Strashko CPSW_RX_VLAN_ENCAP_HDR_VID_SHIFT) & 760a3a41d2fSGrygorii Strashko VLAN_VID_MASK; 761a3a41d2fSGrygorii Strashko /* Ignore vid 0 and pass packet as is */ 762a3a41d2fSGrygorii Strashko if (!vid) 763a3a41d2fSGrygorii Strashko return; 764a3a41d2fSGrygorii Strashko /* Ignore default vlans in dual mac mode */ 765a3a41d2fSGrygorii Strashko if (cpsw->data.dual_emac && 766a3a41d2fSGrygorii Strashko vid == cpsw->slaves[priv->emac_port].port_vlan) 767a3a41d2fSGrygorii Strashko return; 768a3a41d2fSGrygorii Strashko 769a3a41d2fSGrygorii Strashko prio = (rx_vlan_encap_hdr >> 770a3a41d2fSGrygorii Strashko CPSW_RX_VLAN_ENCAP_HDR_PRIO_SHIFT) & 771a3a41d2fSGrygorii Strashko CPSW_RX_VLAN_ENCAP_HDR_PRIO_MSK; 772a3a41d2fSGrygorii Strashko 773a3a41d2fSGrygorii Strashko vtag = (prio << VLAN_PRIO_SHIFT) | vid; 774a3a41d2fSGrygorii Strashko __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vtag); 775a3a41d2fSGrygorii Strashko 776a3a41d2fSGrygorii Strashko /* strip vlan tag for VLAN-tagged packet */ 777a3a41d2fSGrygorii Strashko if (pkt_type == CPSW_RX_VLAN_ENCAP_HDR_PKT_VLAN_TAG) { 778a3a41d2fSGrygorii Strashko memmove(skb->data + VLAN_HLEN, skb->data, 2 * ETH_ALEN); 779a3a41d2fSGrygorii Strashko skb_pull(skb, VLAN_HLEN); 780a3a41d2fSGrygorii Strashko } 781a3a41d2fSGrygorii Strashko } 782a3a41d2fSGrygorii Strashko 7831a3b5056SOlof Johansson static void cpsw_rx_handler(void *token, int len, int status) 784df828598SMugunthan V N { 785e05107e6SIvan Khoronzhuk struct cpdma_chan *ch; 786df828598SMugunthan V N struct sk_buff *skb = token; 787b4727e69SSebastian Siewior struct sk_buff *new_skb; 788df828598SMugunthan V N struct net_device *ndev = skb->dev; 789fea49f60SIvan Khoronzhuk int ret = 0, port; 7902a05a622SIvan Khoronzhuk struct cpsw_common *cpsw = ndev_to_cpsw(ndev); 791df828598SMugunthan V N 792fea49f60SIvan Khoronzhuk if (cpsw->data.dual_emac) { 793fea49f60SIvan Khoronzhuk port = CPDMA_RX_SOURCE_PORT(status); 794fea49f60SIvan Khoronzhuk if (port) { 795fea49f60SIvan Khoronzhuk ndev = cpsw->slaves[--port].ndev; 796fea49f60SIvan Khoronzhuk skb->dev = ndev; 797fea49f60SIvan Khoronzhuk } 798fea49f60SIvan Khoronzhuk } 799d9ba8f9eSMugunthan V N 80016e5c57dSMugunthan V N if (unlikely(status < 0) || unlikely(!netif_running(ndev))) { 801a0e2c822SMugunthan V N /* In dual emac mode check for all interfaces */ 802d5bc1613SIvan Khoronzhuk if (cpsw->data.dual_emac && cpsw->usage_count && 803fe734d0aSIvan Khoronzhuk (status >= 0)) { 804a0e2c822SMugunthan V N /* The packet received is for the interface which 805a0e2c822SMugunthan V N * is already down and the other interface is up 806dbedd44eSJoe Perches * and running, instead of freeing which results 807a0e2c822SMugunthan V N * in reducing of the number of rx descriptor in 808a0e2c822SMugunthan V N * DMA engine, requeue skb back to cpdma. 809a0e2c822SMugunthan V N */ 810a0e2c822SMugunthan V N new_skb = skb; 811a0e2c822SMugunthan V N goto requeue; 812a0e2c822SMugunthan V N } 813a0e2c822SMugunthan V N 814b4727e69SSebastian Siewior /* the interface is going down, skbs are purged */ 815df828598SMugunthan V N dev_kfree_skb_any(skb); 816df828598SMugunthan V N return; 817df828598SMugunthan V N } 818b4727e69SSebastian Siewior 8192a05a622SIvan Khoronzhuk new_skb = netdev_alloc_skb_ip_align(ndev, cpsw->rx_packet_max); 820b4727e69SSebastian Siewior if (new_skb) { 821e05107e6SIvan Khoronzhuk skb_copy_queue_mapping(new_skb, skb); 822df828598SMugunthan V N skb_put(skb, len); 823a3a41d2fSGrygorii Strashko if (status & CPDMA_RX_VLAN_ENCAP) 824a3a41d2fSGrygorii Strashko cpsw_rx_vlan_encap(skb); 8252a05a622SIvan Khoronzhuk cpts_rx_timestamp(cpsw->cpts, skb); 826df828598SMugunthan V N skb->protocol = eth_type_trans(skb, ndev); 827df828598SMugunthan V N netif_receive_skb(skb); 8288dc43ddcSTobias Klauser ndev->stats.rx_bytes += len; 8298dc43ddcSTobias Klauser ndev->stats.rx_packets++; 830254a49d5SGrygorii Strashko kmemleak_not_leak(new_skb); 831b4727e69SSebastian Siewior } else { 8328dc43ddcSTobias Klauser ndev->stats.rx_dropped++; 833b4727e69SSebastian Siewior new_skb = skb; 834df828598SMugunthan V N } 835df828598SMugunthan V N 836a0e2c822SMugunthan V N requeue: 837ce52c744SIvan Khoronzhuk if (netif_dormant(ndev)) { 838ce52c744SIvan Khoronzhuk dev_kfree_skb_any(new_skb); 839ce52c744SIvan Khoronzhuk return; 840ce52c744SIvan Khoronzhuk } 841ce52c744SIvan Khoronzhuk 8428feb0a19SIvan Khoronzhuk ch = cpsw->rxv[skb_get_queue_mapping(new_skb)].ch; 843e05107e6SIvan Khoronzhuk ret = cpdma_chan_submit(ch, new_skb, new_skb->data, 844b4727e69SSebastian Siewior skb_tailroom(new_skb), 0); 845b4727e69SSebastian Siewior if (WARN_ON(ret < 0)) 846b4727e69SSebastian Siewior dev_kfree_skb_any(new_skb); 847df828598SMugunthan V N } 848df828598SMugunthan V N 84932b78d85SIvan Khoronzhuk static void cpsw_split_res(struct net_device *ndev) 85048e0a83eSIvan Khoronzhuk { 85148e0a83eSIvan Khoronzhuk struct cpsw_priv *priv = netdev_priv(ndev); 85232b78d85SIvan Khoronzhuk u32 consumed_rate = 0, bigest_rate = 0; 85348e0a83eSIvan Khoronzhuk struct cpsw_common *cpsw = priv->cpsw; 85448e0a83eSIvan Khoronzhuk struct cpsw_vector *txv = cpsw->txv; 85532b78d85SIvan Khoronzhuk int i, ch_weight, rlim_ch_num = 0; 85648e0a83eSIvan Khoronzhuk int budget, bigest_rate_ch = 0; 85748e0a83eSIvan Khoronzhuk u32 ch_rate, max_rate; 85848e0a83eSIvan Khoronzhuk int ch_budget = 0; 85948e0a83eSIvan Khoronzhuk 86048e0a83eSIvan Khoronzhuk for (i = 0; i < cpsw->tx_ch_num; i++) { 86148e0a83eSIvan Khoronzhuk ch_rate = cpdma_chan_get_rate(txv[i].ch); 86248e0a83eSIvan Khoronzhuk if (!ch_rate) 86348e0a83eSIvan Khoronzhuk continue; 86448e0a83eSIvan Khoronzhuk 86548e0a83eSIvan Khoronzhuk rlim_ch_num++; 86648e0a83eSIvan Khoronzhuk consumed_rate += ch_rate; 86748e0a83eSIvan Khoronzhuk } 86848e0a83eSIvan Khoronzhuk 86948e0a83eSIvan Khoronzhuk if (cpsw->tx_ch_num == rlim_ch_num) { 87048e0a83eSIvan Khoronzhuk max_rate = consumed_rate; 87132b78d85SIvan Khoronzhuk } else if (!rlim_ch_num) { 87232b78d85SIvan Khoronzhuk ch_budget = CPSW_POLL_WEIGHT / cpsw->tx_ch_num; 87332b78d85SIvan Khoronzhuk bigest_rate = 0; 87432b78d85SIvan Khoronzhuk max_rate = consumed_rate; 87548e0a83eSIvan Khoronzhuk } else { 8760be01b8eSIvan Khoronzhuk max_rate = cpsw->speed * 1000; 8770be01b8eSIvan Khoronzhuk 8780be01b8eSIvan Khoronzhuk /* if max_rate is less then expected due to reduced link speed, 8790be01b8eSIvan Khoronzhuk * split proportionally according next potential max speed 8800be01b8eSIvan Khoronzhuk */ 8810be01b8eSIvan Khoronzhuk if (max_rate < consumed_rate) 8820be01b8eSIvan Khoronzhuk max_rate *= 10; 8830be01b8eSIvan Khoronzhuk 8840be01b8eSIvan Khoronzhuk if (max_rate < consumed_rate) 8850be01b8eSIvan Khoronzhuk max_rate *= 10; 88632b78d85SIvan Khoronzhuk 88748e0a83eSIvan Khoronzhuk ch_budget = (consumed_rate * CPSW_POLL_WEIGHT) / max_rate; 88848e0a83eSIvan Khoronzhuk ch_budget = (CPSW_POLL_WEIGHT - ch_budget) / 88948e0a83eSIvan Khoronzhuk (cpsw->tx_ch_num - rlim_ch_num); 89048e0a83eSIvan Khoronzhuk bigest_rate = (max_rate - consumed_rate) / 89148e0a83eSIvan Khoronzhuk (cpsw->tx_ch_num - rlim_ch_num); 89248e0a83eSIvan Khoronzhuk } 89348e0a83eSIvan Khoronzhuk 89432b78d85SIvan Khoronzhuk /* split tx weight/budget */ 89548e0a83eSIvan Khoronzhuk budget = CPSW_POLL_WEIGHT; 89648e0a83eSIvan Khoronzhuk for (i = 0; i < cpsw->tx_ch_num; i++) { 89748e0a83eSIvan Khoronzhuk ch_rate = cpdma_chan_get_rate(txv[i].ch); 89848e0a83eSIvan Khoronzhuk if (ch_rate) { 89948e0a83eSIvan Khoronzhuk txv[i].budget = (ch_rate * CPSW_POLL_WEIGHT) / max_rate; 90048e0a83eSIvan Khoronzhuk if (!txv[i].budget) 90132b78d85SIvan Khoronzhuk txv[i].budget++; 90248e0a83eSIvan Khoronzhuk if (ch_rate > bigest_rate) { 90348e0a83eSIvan Khoronzhuk bigest_rate_ch = i; 90448e0a83eSIvan Khoronzhuk bigest_rate = ch_rate; 90548e0a83eSIvan Khoronzhuk } 90632b78d85SIvan Khoronzhuk 90732b78d85SIvan Khoronzhuk ch_weight = (ch_rate * 100) / max_rate; 90832b78d85SIvan Khoronzhuk if (!ch_weight) 90932b78d85SIvan Khoronzhuk ch_weight++; 91032b78d85SIvan Khoronzhuk cpdma_chan_set_weight(cpsw->txv[i].ch, ch_weight); 91148e0a83eSIvan Khoronzhuk } else { 91248e0a83eSIvan Khoronzhuk txv[i].budget = ch_budget; 91348e0a83eSIvan Khoronzhuk if (!bigest_rate_ch) 91448e0a83eSIvan Khoronzhuk bigest_rate_ch = i; 91532b78d85SIvan Khoronzhuk cpdma_chan_set_weight(cpsw->txv[i].ch, 0); 91648e0a83eSIvan Khoronzhuk } 91748e0a83eSIvan Khoronzhuk 91848e0a83eSIvan Khoronzhuk budget -= txv[i].budget; 91948e0a83eSIvan Khoronzhuk } 92048e0a83eSIvan Khoronzhuk 92148e0a83eSIvan Khoronzhuk if (budget) 92248e0a83eSIvan Khoronzhuk txv[bigest_rate_ch].budget += budget; 92348e0a83eSIvan Khoronzhuk 92448e0a83eSIvan Khoronzhuk /* split rx budget */ 92548e0a83eSIvan Khoronzhuk budget = CPSW_POLL_WEIGHT; 92648e0a83eSIvan Khoronzhuk ch_budget = budget / cpsw->rx_ch_num; 92748e0a83eSIvan Khoronzhuk for (i = 0; i < cpsw->rx_ch_num; i++) { 92848e0a83eSIvan Khoronzhuk cpsw->rxv[i].budget = ch_budget; 92948e0a83eSIvan Khoronzhuk budget -= ch_budget; 93048e0a83eSIvan Khoronzhuk } 93148e0a83eSIvan Khoronzhuk 93248e0a83eSIvan Khoronzhuk if (budget) 93348e0a83eSIvan Khoronzhuk cpsw->rxv[0].budget += budget; 93448e0a83eSIvan Khoronzhuk } 93548e0a83eSIvan Khoronzhuk 936c03abd84SFelipe Balbi static irqreturn_t cpsw_tx_interrupt(int irq, void *dev_id) 937df828598SMugunthan V N { 938dbc4ec52SIvan Khoronzhuk struct cpsw_common *cpsw = dev_id; 9397ce67a38SFelipe Balbi 9405d8d0d4dSIvan Khoronzhuk writel(0, &cpsw->wr_regs->tx_en); 9412c836bd9SIvan Khoronzhuk cpdma_ctlr_eoi(cpsw->dma, CPDMA_EOI_TX); 942c03abd84SFelipe Balbi 943e38b5a3dSIvan Khoronzhuk if (cpsw->quirk_irq) { 944e38b5a3dSIvan Khoronzhuk disable_irq_nosync(cpsw->irqs_table[1]); 945e38b5a3dSIvan Khoronzhuk cpsw->tx_irq_disabled = true; 9467da11600SMugunthan V N } 9477da11600SMugunthan V N 948dbc4ec52SIvan Khoronzhuk napi_schedule(&cpsw->napi_tx); 949c03abd84SFelipe Balbi return IRQ_HANDLED; 950c03abd84SFelipe Balbi } 951c03abd84SFelipe Balbi 952c03abd84SFelipe Balbi static irqreturn_t cpsw_rx_interrupt(int irq, void *dev_id) 953c03abd84SFelipe Balbi { 954dbc4ec52SIvan Khoronzhuk struct cpsw_common *cpsw = dev_id; 955c03abd84SFelipe Balbi 9562c836bd9SIvan Khoronzhuk cpdma_ctlr_eoi(cpsw->dma, CPDMA_EOI_RX); 9575d8d0d4dSIvan Khoronzhuk writel(0, &cpsw->wr_regs->rx_en); 958fd51cf19SSebastian Siewior 959e38b5a3dSIvan Khoronzhuk if (cpsw->quirk_irq) { 960e38b5a3dSIvan Khoronzhuk disable_irq_nosync(cpsw->irqs_table[0]); 961e38b5a3dSIvan Khoronzhuk cpsw->rx_irq_disabled = true; 9627da11600SMugunthan V N } 9637da11600SMugunthan V N 964dbc4ec52SIvan Khoronzhuk napi_schedule(&cpsw->napi_rx); 965df828598SMugunthan V N return IRQ_HANDLED; 966df828598SMugunthan V N } 967df828598SMugunthan V N 9689611d6d6SIvan Khoronzhuk static int cpsw_tx_mq_poll(struct napi_struct *napi_tx, int budget) 969df828598SMugunthan V N { 970e05107e6SIvan Khoronzhuk u32 ch_map; 9718feb0a19SIvan Khoronzhuk int num_tx, cur_budget, ch; 972dbc4ec52SIvan Khoronzhuk struct cpsw_common *cpsw = napi_to_cpsw(napi_tx); 9738feb0a19SIvan Khoronzhuk struct cpsw_vector *txv; 97432a7432cSMugunthan V N 975e05107e6SIvan Khoronzhuk /* process every unprocessed channel */ 976e05107e6SIvan Khoronzhuk ch_map = cpdma_ctrl_txchs_state(cpsw->dma); 97779b3325dSIvan Khoronzhuk for (ch = 0, num_tx = 0; ch_map & 0xff; ch_map <<= 1, ch++) { 97879b3325dSIvan Khoronzhuk if (!(ch_map & 0x80)) 979e05107e6SIvan Khoronzhuk continue; 980e05107e6SIvan Khoronzhuk 9818feb0a19SIvan Khoronzhuk txv = &cpsw->txv[ch]; 9828feb0a19SIvan Khoronzhuk if (unlikely(txv->budget > budget - num_tx)) 9838feb0a19SIvan Khoronzhuk cur_budget = budget - num_tx; 9848feb0a19SIvan Khoronzhuk else 9858feb0a19SIvan Khoronzhuk cur_budget = txv->budget; 9868feb0a19SIvan Khoronzhuk 9878feb0a19SIvan Khoronzhuk num_tx += cpdma_chan_process(txv->ch, cur_budget); 988342934a5SIvan Khoronzhuk if (num_tx >= budget) 989342934a5SIvan Khoronzhuk break; 990e05107e6SIvan Khoronzhuk } 991e05107e6SIvan Khoronzhuk 99232a7432cSMugunthan V N if (num_tx < budget) { 99332a7432cSMugunthan V N napi_complete(napi_tx); 9945d8d0d4dSIvan Khoronzhuk writel(0xff, &cpsw->wr_regs->tx_en); 9959611d6d6SIvan Khoronzhuk } 9969611d6d6SIvan Khoronzhuk 9979611d6d6SIvan Khoronzhuk return num_tx; 9989611d6d6SIvan Khoronzhuk } 9999611d6d6SIvan Khoronzhuk 10009611d6d6SIvan Khoronzhuk static int cpsw_tx_poll(struct napi_struct *napi_tx, int budget) 10019611d6d6SIvan Khoronzhuk { 10029611d6d6SIvan Khoronzhuk struct cpsw_common *cpsw = napi_to_cpsw(napi_tx); 10039611d6d6SIvan Khoronzhuk int num_tx; 10049611d6d6SIvan Khoronzhuk 10059611d6d6SIvan Khoronzhuk num_tx = cpdma_chan_process(cpsw->txv[0].ch, budget); 10069611d6d6SIvan Khoronzhuk if (num_tx < budget) { 10079611d6d6SIvan Khoronzhuk napi_complete(napi_tx); 10089611d6d6SIvan Khoronzhuk writel(0xff, &cpsw->wr_regs->tx_en); 10099611d6d6SIvan Khoronzhuk if (cpsw->tx_irq_disabled) { 1010e38b5a3dSIvan Khoronzhuk cpsw->tx_irq_disabled = false; 1011e38b5a3dSIvan Khoronzhuk enable_irq(cpsw->irqs_table[1]); 10127da11600SMugunthan V N } 101332a7432cSMugunthan V N } 101432a7432cSMugunthan V N 101532a7432cSMugunthan V N return num_tx; 101632a7432cSMugunthan V N } 101732a7432cSMugunthan V N 10189611d6d6SIvan Khoronzhuk static int cpsw_rx_mq_poll(struct napi_struct *napi_rx, int budget) 101932a7432cSMugunthan V N { 1020e05107e6SIvan Khoronzhuk u32 ch_map; 10218feb0a19SIvan Khoronzhuk int num_rx, cur_budget, ch; 1022dbc4ec52SIvan Khoronzhuk struct cpsw_common *cpsw = napi_to_cpsw(napi_rx); 10238feb0a19SIvan Khoronzhuk struct cpsw_vector *rxv; 1024510a1e72SMugunthan V N 1025e05107e6SIvan Khoronzhuk /* process every unprocessed channel */ 1026e05107e6SIvan Khoronzhuk ch_map = cpdma_ctrl_rxchs_state(cpsw->dma); 1027342934a5SIvan Khoronzhuk for (ch = 0, num_rx = 0; ch_map; ch_map >>= 1, ch++) { 1028e05107e6SIvan Khoronzhuk if (!(ch_map & 0x01)) 1029e05107e6SIvan Khoronzhuk continue; 1030e05107e6SIvan Khoronzhuk 10318feb0a19SIvan Khoronzhuk rxv = &cpsw->rxv[ch]; 10328feb0a19SIvan Khoronzhuk if (unlikely(rxv->budget > budget - num_rx)) 10338feb0a19SIvan Khoronzhuk cur_budget = budget - num_rx; 10348feb0a19SIvan Khoronzhuk else 10358feb0a19SIvan Khoronzhuk cur_budget = rxv->budget; 10368feb0a19SIvan Khoronzhuk 10378feb0a19SIvan Khoronzhuk num_rx += cpdma_chan_process(rxv->ch, cur_budget); 1038342934a5SIvan Khoronzhuk if (num_rx >= budget) 1039342934a5SIvan Khoronzhuk break; 1040e05107e6SIvan Khoronzhuk } 1041e05107e6SIvan Khoronzhuk 1042510a1e72SMugunthan V N if (num_rx < budget) { 10436ad20165SEric Dumazet napi_complete_done(napi_rx, num_rx); 10445d8d0d4dSIvan Khoronzhuk writel(0xff, &cpsw->wr_regs->rx_en); 10459611d6d6SIvan Khoronzhuk } 10469611d6d6SIvan Khoronzhuk 10479611d6d6SIvan Khoronzhuk return num_rx; 10489611d6d6SIvan Khoronzhuk } 10499611d6d6SIvan Khoronzhuk 10509611d6d6SIvan Khoronzhuk static int cpsw_rx_poll(struct napi_struct *napi_rx, int budget) 10519611d6d6SIvan Khoronzhuk { 10529611d6d6SIvan Khoronzhuk struct cpsw_common *cpsw = napi_to_cpsw(napi_rx); 10539611d6d6SIvan Khoronzhuk int num_rx; 10549611d6d6SIvan Khoronzhuk 10559611d6d6SIvan Khoronzhuk num_rx = cpdma_chan_process(cpsw->rxv[0].ch, budget); 10569611d6d6SIvan Khoronzhuk if (num_rx < budget) { 10579611d6d6SIvan Khoronzhuk napi_complete_done(napi_rx, num_rx); 10589611d6d6SIvan Khoronzhuk writel(0xff, &cpsw->wr_regs->rx_en); 10599611d6d6SIvan Khoronzhuk if (cpsw->rx_irq_disabled) { 1060e38b5a3dSIvan Khoronzhuk cpsw->rx_irq_disabled = false; 1061e38b5a3dSIvan Khoronzhuk enable_irq(cpsw->irqs_table[0]); 10627da11600SMugunthan V N } 1063510a1e72SMugunthan V N } 1064df828598SMugunthan V N 1065df828598SMugunthan V N return num_rx; 1066df828598SMugunthan V N } 1067df828598SMugunthan V N 1068df828598SMugunthan V N static inline void soft_reset(const char *module, void __iomem *reg) 1069df828598SMugunthan V N { 1070df828598SMugunthan V N unsigned long timeout = jiffies + HZ; 1071df828598SMugunthan V N 1072dda5f5feSGrygorii Strashko writel_relaxed(1, reg); 1073df828598SMugunthan V N do { 1074df828598SMugunthan V N cpu_relax(); 1075dda5f5feSGrygorii Strashko } while ((readl_relaxed(reg) & 1) && time_after(timeout, jiffies)); 1076df828598SMugunthan V N 1077dda5f5feSGrygorii Strashko WARN(readl_relaxed(reg) & 1, "failed to soft-reset %s\n", module); 1078df828598SMugunthan V N } 1079df828598SMugunthan V N 1080df828598SMugunthan V N static void cpsw_set_slave_mac(struct cpsw_slave *slave, 1081df828598SMugunthan V N struct cpsw_priv *priv) 1082df828598SMugunthan V N { 10839750a3adSRichard Cochran slave_write(slave, mac_hi(priv->mac_addr), SA_HI); 10849750a3adSRichard Cochran slave_write(slave, mac_lo(priv->mac_addr), SA_LO); 1085df828598SMugunthan V N } 1086df828598SMugunthan V N 108757d90148SIvan Khoronzhuk static bool cpsw_shp_is_off(struct cpsw_priv *priv) 108857d90148SIvan Khoronzhuk { 108957d90148SIvan Khoronzhuk struct cpsw_common *cpsw = priv->cpsw; 109057d90148SIvan Khoronzhuk struct cpsw_slave *slave; 109157d90148SIvan Khoronzhuk u32 shift, mask, val; 109257d90148SIvan Khoronzhuk 109357d90148SIvan Khoronzhuk val = readl_relaxed(&cpsw->regs->ptype); 109457d90148SIvan Khoronzhuk 109557d90148SIvan Khoronzhuk slave = &cpsw->slaves[cpsw_slave_index(cpsw, priv)]; 109657d90148SIvan Khoronzhuk shift = CPSW_FIFO_SHAPE_EN_SHIFT + 3 * slave->slave_num; 109757d90148SIvan Khoronzhuk mask = 7 << shift; 109857d90148SIvan Khoronzhuk val = val & mask; 109957d90148SIvan Khoronzhuk 110057d90148SIvan Khoronzhuk return !val; 110157d90148SIvan Khoronzhuk } 110257d90148SIvan Khoronzhuk 110357d90148SIvan Khoronzhuk static void cpsw_fifo_shp_on(struct cpsw_priv *priv, int fifo, int on) 110457d90148SIvan Khoronzhuk { 110557d90148SIvan Khoronzhuk struct cpsw_common *cpsw = priv->cpsw; 110657d90148SIvan Khoronzhuk struct cpsw_slave *slave; 110757d90148SIvan Khoronzhuk u32 shift, mask, val; 110857d90148SIvan Khoronzhuk 110957d90148SIvan Khoronzhuk val = readl_relaxed(&cpsw->regs->ptype); 111057d90148SIvan Khoronzhuk 111157d90148SIvan Khoronzhuk slave = &cpsw->slaves[cpsw_slave_index(cpsw, priv)]; 111257d90148SIvan Khoronzhuk shift = CPSW_FIFO_SHAPE_EN_SHIFT + 3 * slave->slave_num; 111357d90148SIvan Khoronzhuk mask = (1 << --fifo) << shift; 111457d90148SIvan Khoronzhuk val = on ? val | mask : val & ~mask; 111557d90148SIvan Khoronzhuk 111657d90148SIvan Khoronzhuk writel_relaxed(val, &cpsw->regs->ptype); 111757d90148SIvan Khoronzhuk } 111857d90148SIvan Khoronzhuk 1119df828598SMugunthan V N static void _cpsw_adjust_link(struct cpsw_slave *slave, 1120df828598SMugunthan V N struct cpsw_priv *priv, bool *link) 1121df828598SMugunthan V N { 1122df828598SMugunthan V N struct phy_device *phy = slave->phy; 1123df828598SMugunthan V N u32 mac_control = 0; 1124df828598SMugunthan V N u32 slave_port; 1125606f3993SIvan Khoronzhuk struct cpsw_common *cpsw = priv->cpsw; 1126df828598SMugunthan V N 1127df828598SMugunthan V N if (!phy) 1128df828598SMugunthan V N return; 1129df828598SMugunthan V N 11306f1f5836SIvan Khoronzhuk slave_port = cpsw_get_slave_port(slave->slave_num); 1131df828598SMugunthan V N 1132df828598SMugunthan V N if (phy->link) { 1133606f3993SIvan Khoronzhuk mac_control = cpsw->data.mac_control; 1134df828598SMugunthan V N 1135df828598SMugunthan V N /* enable forwarding */ 11362a05a622SIvan Khoronzhuk cpsw_ale_control_set(cpsw->ale, slave_port, 1137df828598SMugunthan V N ALE_PORT_STATE, ALE_PORT_STATE_FORWARD); 1138df828598SMugunthan V N 1139df828598SMugunthan V N if (phy->speed == 1000) 1140df828598SMugunthan V N mac_control |= BIT(7); /* GIGABITEN */ 1141df828598SMugunthan V N if (phy->duplex) 1142df828598SMugunthan V N mac_control |= BIT(0); /* FULLDUPLEXEN */ 1143342b7b74SDaniel Mack 1144342b7b74SDaniel Mack /* set speed_in input in case RMII mode is used in 100Mbps */ 1145342b7b74SDaniel Mack if (phy->speed == 100) 1146342b7b74SDaniel Mack mac_control |= BIT(15); 1147f9db5069SSZ Lin (林上智) /* in band mode only works in 10Mbps RGMII mode */ 1148f9db5069SSZ Lin (林上智) else if ((phy->speed == 10) && phy_interface_is_rgmii(phy)) 1149a81d8762SMugunthan V N mac_control |= BIT(18); /* In Band mode */ 1150342b7b74SDaniel Mack 11511923d6e4SMugunthan V N if (priv->rx_pause) 11521923d6e4SMugunthan V N mac_control |= BIT(3); 11531923d6e4SMugunthan V N 11541923d6e4SMugunthan V N if (priv->tx_pause) 11551923d6e4SMugunthan V N mac_control |= BIT(4); 11561923d6e4SMugunthan V N 1157df828598SMugunthan V N *link = true; 115857d90148SIvan Khoronzhuk 115957d90148SIvan Khoronzhuk if (priv->shp_cfg_speed && 116057d90148SIvan Khoronzhuk priv->shp_cfg_speed != slave->phy->speed && 116157d90148SIvan Khoronzhuk !cpsw_shp_is_off(priv)) 116257d90148SIvan Khoronzhuk dev_warn(priv->dev, 116357d90148SIvan Khoronzhuk "Speed was changed, CBS shaper speeds are changed!"); 1164df828598SMugunthan V N } else { 1165df828598SMugunthan V N mac_control = 0; 1166df828598SMugunthan V N /* disable forwarding */ 11672a05a622SIvan Khoronzhuk cpsw_ale_control_set(cpsw->ale, slave_port, 1168df828598SMugunthan V N ALE_PORT_STATE, ALE_PORT_STATE_DISABLE); 1169df828598SMugunthan V N } 1170df828598SMugunthan V N 1171df828598SMugunthan V N if (mac_control != slave->mac_control) { 1172df828598SMugunthan V N phy_print_status(phy); 1173dda5f5feSGrygorii Strashko writel_relaxed(mac_control, &slave->sliver->mac_control); 1174df828598SMugunthan V N } 1175df828598SMugunthan V N 1176df828598SMugunthan V N slave->mac_control = mac_control; 1177df828598SMugunthan V N } 1178df828598SMugunthan V N 11790be01b8eSIvan Khoronzhuk static int cpsw_get_common_speed(struct cpsw_common *cpsw) 11800be01b8eSIvan Khoronzhuk { 11810be01b8eSIvan Khoronzhuk int i, speed; 11820be01b8eSIvan Khoronzhuk 11830be01b8eSIvan Khoronzhuk for (i = 0, speed = 0; i < cpsw->data.slaves; i++) 11840be01b8eSIvan Khoronzhuk if (cpsw->slaves[i].phy && cpsw->slaves[i].phy->link) 11850be01b8eSIvan Khoronzhuk speed += cpsw->slaves[i].phy->speed; 11860be01b8eSIvan Khoronzhuk 11870be01b8eSIvan Khoronzhuk return speed; 11880be01b8eSIvan Khoronzhuk } 11890be01b8eSIvan Khoronzhuk 11900be01b8eSIvan Khoronzhuk static int cpsw_need_resplit(struct cpsw_common *cpsw) 11910be01b8eSIvan Khoronzhuk { 11920be01b8eSIvan Khoronzhuk int i, rlim_ch_num; 11930be01b8eSIvan Khoronzhuk int speed, ch_rate; 11940be01b8eSIvan Khoronzhuk 11950be01b8eSIvan Khoronzhuk /* re-split resources only in case speed was changed */ 11960be01b8eSIvan Khoronzhuk speed = cpsw_get_common_speed(cpsw); 11970be01b8eSIvan Khoronzhuk if (speed == cpsw->speed || !speed) 11980be01b8eSIvan Khoronzhuk return 0; 11990be01b8eSIvan Khoronzhuk 12000be01b8eSIvan Khoronzhuk cpsw->speed = speed; 12010be01b8eSIvan Khoronzhuk 12020be01b8eSIvan Khoronzhuk for (i = 0, rlim_ch_num = 0; i < cpsw->tx_ch_num; i++) { 12030be01b8eSIvan Khoronzhuk ch_rate = cpdma_chan_get_rate(cpsw->txv[i].ch); 12040be01b8eSIvan Khoronzhuk if (!ch_rate) 12050be01b8eSIvan Khoronzhuk break; 12060be01b8eSIvan Khoronzhuk 12070be01b8eSIvan Khoronzhuk rlim_ch_num++; 12080be01b8eSIvan Khoronzhuk } 12090be01b8eSIvan Khoronzhuk 12100be01b8eSIvan Khoronzhuk /* cases not dependent on speed */ 12110be01b8eSIvan Khoronzhuk if (!rlim_ch_num || rlim_ch_num == cpsw->tx_ch_num) 12120be01b8eSIvan Khoronzhuk return 0; 12130be01b8eSIvan Khoronzhuk 12140be01b8eSIvan Khoronzhuk return 1; 12150be01b8eSIvan Khoronzhuk } 12160be01b8eSIvan Khoronzhuk 1217df828598SMugunthan V N static void cpsw_adjust_link(struct net_device *ndev) 1218df828598SMugunthan V N { 1219df828598SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 12200be01b8eSIvan Khoronzhuk struct cpsw_common *cpsw = priv->cpsw; 1221df828598SMugunthan V N bool link = false; 1222df828598SMugunthan V N 1223df828598SMugunthan V N for_each_slave(priv, _cpsw_adjust_link, priv, &link); 1224df828598SMugunthan V N 1225df828598SMugunthan V N if (link) { 12260be01b8eSIvan Khoronzhuk if (cpsw_need_resplit(cpsw)) 12270be01b8eSIvan Khoronzhuk cpsw_split_res(ndev); 12280be01b8eSIvan Khoronzhuk 1229df828598SMugunthan V N netif_carrier_on(ndev); 1230df828598SMugunthan V N if (netif_running(ndev)) 1231e05107e6SIvan Khoronzhuk netif_tx_wake_all_queues(ndev); 1232df828598SMugunthan V N } else { 1233df828598SMugunthan V N netif_carrier_off(ndev); 1234e05107e6SIvan Khoronzhuk netif_tx_stop_all_queues(ndev); 1235df828598SMugunthan V N } 1236df828598SMugunthan V N } 1237df828598SMugunthan V N 1238ff5b8ef2SMugunthan V N static int cpsw_get_coalesce(struct net_device *ndev, 1239ff5b8ef2SMugunthan V N struct ethtool_coalesce *coal) 1240ff5b8ef2SMugunthan V N { 12412a05a622SIvan Khoronzhuk struct cpsw_common *cpsw = ndev_to_cpsw(ndev); 1242ff5b8ef2SMugunthan V N 12432a05a622SIvan Khoronzhuk coal->rx_coalesce_usecs = cpsw->coal_intvl; 1244ff5b8ef2SMugunthan V N return 0; 1245ff5b8ef2SMugunthan V N } 1246ff5b8ef2SMugunthan V N 1247ff5b8ef2SMugunthan V N static int cpsw_set_coalesce(struct net_device *ndev, 1248ff5b8ef2SMugunthan V N struct ethtool_coalesce *coal) 1249ff5b8ef2SMugunthan V N { 1250ff5b8ef2SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 1251ff5b8ef2SMugunthan V N u32 int_ctrl; 1252ff5b8ef2SMugunthan V N u32 num_interrupts = 0; 1253ff5b8ef2SMugunthan V N u32 prescale = 0; 1254ff5b8ef2SMugunthan V N u32 addnl_dvdr = 1; 1255ff5b8ef2SMugunthan V N u32 coal_intvl = 0; 12565d8d0d4dSIvan Khoronzhuk struct cpsw_common *cpsw = priv->cpsw; 1257ff5b8ef2SMugunthan V N 1258ff5b8ef2SMugunthan V N coal_intvl = coal->rx_coalesce_usecs; 1259ff5b8ef2SMugunthan V N 12605d8d0d4dSIvan Khoronzhuk int_ctrl = readl(&cpsw->wr_regs->int_control); 12612a05a622SIvan Khoronzhuk prescale = cpsw->bus_freq_mhz * 4; 1262ff5b8ef2SMugunthan V N 1263a84bc2a9SMugunthan V N if (!coal->rx_coalesce_usecs) { 1264a84bc2a9SMugunthan V N int_ctrl &= ~(CPSW_INTPRESCALE_MASK | CPSW_INTPACEEN); 1265a84bc2a9SMugunthan V N goto update_return; 1266a84bc2a9SMugunthan V N } 1267a84bc2a9SMugunthan V N 1268ff5b8ef2SMugunthan V N if (coal_intvl < CPSW_CMINTMIN_INTVL) 1269ff5b8ef2SMugunthan V N coal_intvl = CPSW_CMINTMIN_INTVL; 1270ff5b8ef2SMugunthan V N 1271ff5b8ef2SMugunthan V N if (coal_intvl > CPSW_CMINTMAX_INTVL) { 1272ff5b8ef2SMugunthan V N /* Interrupt pacer works with 4us Pulse, we can 1273ff5b8ef2SMugunthan V N * throttle further by dilating the 4us pulse. 1274ff5b8ef2SMugunthan V N */ 1275ff5b8ef2SMugunthan V N addnl_dvdr = CPSW_INTPRESCALE_MASK / prescale; 1276ff5b8ef2SMugunthan V N 1277ff5b8ef2SMugunthan V N if (addnl_dvdr > 1) { 1278ff5b8ef2SMugunthan V N prescale *= addnl_dvdr; 1279ff5b8ef2SMugunthan V N if (coal_intvl > (CPSW_CMINTMAX_INTVL * addnl_dvdr)) 1280ff5b8ef2SMugunthan V N coal_intvl = (CPSW_CMINTMAX_INTVL 1281ff5b8ef2SMugunthan V N * addnl_dvdr); 1282ff5b8ef2SMugunthan V N } else { 1283ff5b8ef2SMugunthan V N addnl_dvdr = 1; 1284ff5b8ef2SMugunthan V N coal_intvl = CPSW_CMINTMAX_INTVL; 1285ff5b8ef2SMugunthan V N } 1286ff5b8ef2SMugunthan V N } 1287ff5b8ef2SMugunthan V N 1288ff5b8ef2SMugunthan V N num_interrupts = (1000 * addnl_dvdr) / coal_intvl; 12895d8d0d4dSIvan Khoronzhuk writel(num_interrupts, &cpsw->wr_regs->rx_imax); 12905d8d0d4dSIvan Khoronzhuk writel(num_interrupts, &cpsw->wr_regs->tx_imax); 1291ff5b8ef2SMugunthan V N 1292ff5b8ef2SMugunthan V N int_ctrl |= CPSW_INTPACEEN; 1293ff5b8ef2SMugunthan V N int_ctrl &= (~CPSW_INTPRESCALE_MASK); 1294ff5b8ef2SMugunthan V N int_ctrl |= (prescale & CPSW_INTPRESCALE_MASK); 1295a84bc2a9SMugunthan V N 1296a84bc2a9SMugunthan V N update_return: 12975d8d0d4dSIvan Khoronzhuk writel(int_ctrl, &cpsw->wr_regs->int_control); 1298ff5b8ef2SMugunthan V N 1299ff5b8ef2SMugunthan V N cpsw_notice(priv, timer, "Set coalesce to %d usecs.\n", coal_intvl); 13002a05a622SIvan Khoronzhuk cpsw->coal_intvl = coal_intvl; 1301ff5b8ef2SMugunthan V N 1302ff5b8ef2SMugunthan V N return 0; 1303ff5b8ef2SMugunthan V N } 1304ff5b8ef2SMugunthan V N 1305d9718546SMugunthan V N static int cpsw_get_sset_count(struct net_device *ndev, int sset) 1306d9718546SMugunthan V N { 1307e05107e6SIvan Khoronzhuk struct cpsw_common *cpsw = ndev_to_cpsw(ndev); 1308e05107e6SIvan Khoronzhuk 1309d9718546SMugunthan V N switch (sset) { 1310d9718546SMugunthan V N case ETH_SS_STATS: 1311e05107e6SIvan Khoronzhuk return (CPSW_STATS_COMMON_LEN + 1312e05107e6SIvan Khoronzhuk (cpsw->rx_ch_num + cpsw->tx_ch_num) * 1313e05107e6SIvan Khoronzhuk CPSW_STATS_CH_LEN); 1314d9718546SMugunthan V N default: 1315d9718546SMugunthan V N return -EOPNOTSUPP; 1316d9718546SMugunthan V N } 1317d9718546SMugunthan V N } 1318d9718546SMugunthan V N 1319e05107e6SIvan Khoronzhuk static void cpsw_add_ch_strings(u8 **p, int ch_num, int rx_dir) 1320e05107e6SIvan Khoronzhuk { 1321e05107e6SIvan Khoronzhuk int ch_stats_len; 1322e05107e6SIvan Khoronzhuk int line; 1323e05107e6SIvan Khoronzhuk int i; 1324e05107e6SIvan Khoronzhuk 1325e05107e6SIvan Khoronzhuk ch_stats_len = CPSW_STATS_CH_LEN * ch_num; 1326e05107e6SIvan Khoronzhuk for (i = 0; i < ch_stats_len; i++) { 1327e05107e6SIvan Khoronzhuk line = i % CPSW_STATS_CH_LEN; 1328e05107e6SIvan Khoronzhuk snprintf(*p, ETH_GSTRING_LEN, 1329bf2ce3fdSFlorian Fainelli "%s DMA chan %ld: %s", rx_dir ? "Rx" : "Tx", 1330bf2ce3fdSFlorian Fainelli (long)(i / CPSW_STATS_CH_LEN), 1331e05107e6SIvan Khoronzhuk cpsw_gstrings_ch_stats[line].stat_string); 1332e05107e6SIvan Khoronzhuk *p += ETH_GSTRING_LEN; 1333e05107e6SIvan Khoronzhuk } 1334e05107e6SIvan Khoronzhuk } 1335e05107e6SIvan Khoronzhuk 1336d9718546SMugunthan V N static void cpsw_get_strings(struct net_device *ndev, u32 stringset, u8 *data) 1337d9718546SMugunthan V N { 1338e05107e6SIvan Khoronzhuk struct cpsw_common *cpsw = ndev_to_cpsw(ndev); 1339d9718546SMugunthan V N u8 *p = data; 1340d9718546SMugunthan V N int i; 1341d9718546SMugunthan V N 1342d9718546SMugunthan V N switch (stringset) { 1343d9718546SMugunthan V N case ETH_SS_STATS: 1344e05107e6SIvan Khoronzhuk for (i = 0; i < CPSW_STATS_COMMON_LEN; i++) { 1345d9718546SMugunthan V N memcpy(p, cpsw_gstrings_stats[i].stat_string, 1346d9718546SMugunthan V N ETH_GSTRING_LEN); 1347d9718546SMugunthan V N p += ETH_GSTRING_LEN; 1348d9718546SMugunthan V N } 1349e05107e6SIvan Khoronzhuk 1350e05107e6SIvan Khoronzhuk cpsw_add_ch_strings(&p, cpsw->rx_ch_num, 1); 1351e05107e6SIvan Khoronzhuk cpsw_add_ch_strings(&p, cpsw->tx_ch_num, 0); 1352d9718546SMugunthan V N break; 1353d9718546SMugunthan V N } 1354d9718546SMugunthan V N } 1355d9718546SMugunthan V N 1356d9718546SMugunthan V N static void cpsw_get_ethtool_stats(struct net_device *ndev, 1357d9718546SMugunthan V N struct ethtool_stats *stats, u64 *data) 1358d9718546SMugunthan V N { 1359d9718546SMugunthan V N u8 *p; 13602c836bd9SIvan Khoronzhuk struct cpsw_common *cpsw = ndev_to_cpsw(ndev); 1361e05107e6SIvan Khoronzhuk struct cpdma_chan_stats ch_stats; 1362e05107e6SIvan Khoronzhuk int i, l, ch; 1363d9718546SMugunthan V N 1364d9718546SMugunthan V N /* Collect Davinci CPDMA stats for Rx and Tx Channel */ 1365e05107e6SIvan Khoronzhuk for (l = 0; l < CPSW_STATS_COMMON_LEN; l++) 1366e05107e6SIvan Khoronzhuk data[l] = readl(cpsw->hw_stats + 1367e05107e6SIvan Khoronzhuk cpsw_gstrings_stats[l].stat_offset); 1368d9718546SMugunthan V N 1369e05107e6SIvan Khoronzhuk for (ch = 0; ch < cpsw->rx_ch_num; ch++) { 13708feb0a19SIvan Khoronzhuk cpdma_chan_get_stats(cpsw->rxv[ch].ch, &ch_stats); 1371e05107e6SIvan Khoronzhuk for (i = 0; i < CPSW_STATS_CH_LEN; i++, l++) { 1372e05107e6SIvan Khoronzhuk p = (u8 *)&ch_stats + 1373e05107e6SIvan Khoronzhuk cpsw_gstrings_ch_stats[i].stat_offset; 1374e05107e6SIvan Khoronzhuk data[l] = *(u32 *)p; 1375e05107e6SIvan Khoronzhuk } 1376e05107e6SIvan Khoronzhuk } 1377d9718546SMugunthan V N 1378e05107e6SIvan Khoronzhuk for (ch = 0; ch < cpsw->tx_ch_num; ch++) { 13798feb0a19SIvan Khoronzhuk cpdma_chan_get_stats(cpsw->txv[ch].ch, &ch_stats); 1380e05107e6SIvan Khoronzhuk for (i = 0; i < CPSW_STATS_CH_LEN; i++, l++) { 1381e05107e6SIvan Khoronzhuk p = (u8 *)&ch_stats + 1382e05107e6SIvan Khoronzhuk cpsw_gstrings_ch_stats[i].stat_offset; 1383e05107e6SIvan Khoronzhuk data[l] = *(u32 *)p; 1384d9718546SMugunthan V N } 1385d9718546SMugunthan V N } 1386d9718546SMugunthan V N } 1387d9718546SMugunthan V N 138827e9e103SIvan Khoronzhuk static inline int cpsw_tx_packet_submit(struct cpsw_priv *priv, 1389e05107e6SIvan Khoronzhuk struct sk_buff *skb, 1390e05107e6SIvan Khoronzhuk struct cpdma_chan *txch) 1391d9ba8f9eSMugunthan V N { 13922c836bd9SIvan Khoronzhuk struct cpsw_common *cpsw = priv->cpsw; 13932c836bd9SIvan Khoronzhuk 139498fdd857SIvan Khoronzhuk skb_tx_timestamp(skb); 1395e05107e6SIvan Khoronzhuk return cpdma_chan_submit(txch, skb, skb->data, skb->len, 1396606f3993SIvan Khoronzhuk priv->emac_port + cpsw->data.dual_emac); 1397d9ba8f9eSMugunthan V N } 1398d9ba8f9eSMugunthan V N 1399d9ba8f9eSMugunthan V N static inline void cpsw_add_dual_emac_def_ale_entries( 1400d9ba8f9eSMugunthan V N struct cpsw_priv *priv, struct cpsw_slave *slave, 1401d9ba8f9eSMugunthan V N u32 slave_port) 1402d9ba8f9eSMugunthan V N { 14032a05a622SIvan Khoronzhuk struct cpsw_common *cpsw = priv->cpsw; 140471a2cbb7SGrygorii Strashko u32 port_mask = 1 << slave_port | ALE_PORT_HOST; 1405d9ba8f9eSMugunthan V N 14062a05a622SIvan Khoronzhuk if (cpsw->version == CPSW_VERSION_1) 1407d9ba8f9eSMugunthan V N slave_write(slave, slave->port_vlan, CPSW1_PORT_VLAN); 1408d9ba8f9eSMugunthan V N else 1409d9ba8f9eSMugunthan V N slave_write(slave, slave->port_vlan, CPSW2_PORT_VLAN); 14102a05a622SIvan Khoronzhuk cpsw_ale_add_vlan(cpsw->ale, slave->port_vlan, port_mask, 1411d9ba8f9eSMugunthan V N port_mask, port_mask, 0); 14122a05a622SIvan Khoronzhuk cpsw_ale_add_mcast(cpsw->ale, priv->ndev->broadcast, 1413d9ba8f9eSMugunthan V N port_mask, ALE_VLAN, slave->port_vlan, 0); 14142a05a622SIvan Khoronzhuk cpsw_ale_add_ucast(cpsw->ale, priv->mac_addr, 14152a05a622SIvan Khoronzhuk HOST_PORT_NUM, ALE_VLAN | 14162a05a622SIvan Khoronzhuk ALE_SECURE, slave->port_vlan); 14175e5add17SGrygorii Strashko cpsw_ale_control_set(cpsw->ale, slave_port, 14185e5add17SGrygorii Strashko ALE_PORT_DROP_UNKNOWN_VLAN, 1); 1419d9ba8f9eSMugunthan V N } 1420d9ba8f9eSMugunthan V N 14211e7a2e21SDaniel Mack static void soft_reset_slave(struct cpsw_slave *slave) 1422df828598SMugunthan V N { 1423df828598SMugunthan V N char name[32]; 14241e7a2e21SDaniel Mack 14251e7a2e21SDaniel Mack snprintf(name, sizeof(name), "slave-%d", slave->slave_num); 14261e7a2e21SDaniel Mack soft_reset(name, &slave->sliver->soft_reset); 14271e7a2e21SDaniel Mack } 14281e7a2e21SDaniel Mack 14291e7a2e21SDaniel Mack static void cpsw_slave_open(struct cpsw_slave *slave, struct cpsw_priv *priv) 14301e7a2e21SDaniel Mack { 1431df828598SMugunthan V N u32 slave_port; 143230c57f07SSekhar Nori struct phy_device *phy; 1433649a1688SIvan Khoronzhuk struct cpsw_common *cpsw = priv->cpsw; 1434df828598SMugunthan V N 14351e7a2e21SDaniel Mack soft_reset_slave(slave); 1436df828598SMugunthan V N 1437df828598SMugunthan V N /* setup priority mapping */ 1438dda5f5feSGrygorii Strashko writel_relaxed(RX_PRIORITY_MAPPING, &slave->sliver->rx_pri_map); 14399750a3adSRichard Cochran 14402a05a622SIvan Khoronzhuk switch (cpsw->version) { 14419750a3adSRichard Cochran case CPSW_VERSION_1: 14429750a3adSRichard Cochran slave_write(slave, TX_PRIORITY_MAPPING, CPSW1_TX_PRI_MAP); 144348f5bcccSGrygorii Strashko /* Increase RX FIFO size to 5 for supporting fullduplex 144448f5bcccSGrygorii Strashko * flow control mode 144548f5bcccSGrygorii Strashko */ 144648f5bcccSGrygorii Strashko slave_write(slave, 144748f5bcccSGrygorii Strashko (CPSW_MAX_BLKS_TX << CPSW_MAX_BLKS_TX_SHIFT) | 144848f5bcccSGrygorii Strashko CPSW_MAX_BLKS_RX, CPSW1_MAX_BLKS); 14499750a3adSRichard Cochran break; 14509750a3adSRichard Cochran case CPSW_VERSION_2: 1451c193f365SMugunthan V N case CPSW_VERSION_3: 1452926489beSMugunthan V N case CPSW_VERSION_4: 14539750a3adSRichard Cochran slave_write(slave, TX_PRIORITY_MAPPING, CPSW2_TX_PRI_MAP); 145448f5bcccSGrygorii Strashko /* Increase RX FIFO size to 5 for supporting fullduplex 145548f5bcccSGrygorii Strashko * flow control mode 145648f5bcccSGrygorii Strashko */ 145748f5bcccSGrygorii Strashko slave_write(slave, 145848f5bcccSGrygorii Strashko (CPSW_MAX_BLKS_TX << CPSW_MAX_BLKS_TX_SHIFT) | 145948f5bcccSGrygorii Strashko CPSW_MAX_BLKS_RX, CPSW2_MAX_BLKS); 14609750a3adSRichard Cochran break; 14619750a3adSRichard Cochran } 1462df828598SMugunthan V N 1463df828598SMugunthan V N /* setup max packet size, and mac address */ 1464dda5f5feSGrygorii Strashko writel_relaxed(cpsw->rx_packet_max, &slave->sliver->rx_maxlen); 1465df828598SMugunthan V N cpsw_set_slave_mac(slave, priv); 1466df828598SMugunthan V N 1467df828598SMugunthan V N slave->mac_control = 0; /* no link yet */ 1468df828598SMugunthan V N 14696f1f5836SIvan Khoronzhuk slave_port = cpsw_get_slave_port(slave->slave_num); 1470df828598SMugunthan V N 1471606f3993SIvan Khoronzhuk if (cpsw->data.dual_emac) 1472d9ba8f9eSMugunthan V N cpsw_add_dual_emac_def_ale_entries(priv, slave, slave_port); 1473d9ba8f9eSMugunthan V N else 14742a05a622SIvan Khoronzhuk cpsw_ale_add_mcast(cpsw->ale, priv->ndev->broadcast, 1475e11b220fSMugunthan V N 1 << slave_port, 0, 0, ALE_MCAST_FWD_2); 1476df828598SMugunthan V N 1477d733f754SDavid Rivshin if (slave->data->phy_node) { 147830c57f07SSekhar Nori phy = of_phy_connect(priv->ndev, slave->data->phy_node, 14799e42f715SHeiko Schocher &cpsw_adjust_link, 0, slave->data->phy_if); 148030c57f07SSekhar Nori if (!phy) { 1481f7ce9103SRob Herring dev_err(priv->dev, "phy \"%pOF\" not found on slave %d\n", 1482f7ce9103SRob Herring slave->data->phy_node, 1483d733f754SDavid Rivshin slave->slave_num); 1484d733f754SDavid Rivshin return; 1485d733f754SDavid Rivshin } 1486d733f754SDavid Rivshin } else { 148730c57f07SSekhar Nori phy = phy_connect(priv->ndev, slave->data->phy_id, 1488f9a8f83bSFlorian Fainelli &cpsw_adjust_link, slave->data->phy_if); 148930c57f07SSekhar Nori if (IS_ERR(phy)) { 1490d733f754SDavid Rivshin dev_err(priv->dev, 1491d733f754SDavid Rivshin "phy \"%s\" not found on slave %d, err %ld\n", 1492d733f754SDavid Rivshin slave->data->phy_id, slave->slave_num, 149330c57f07SSekhar Nori PTR_ERR(phy)); 1494d733f754SDavid Rivshin return; 1495d733f754SDavid Rivshin } 1496d733f754SDavid Rivshin } 1497d733f754SDavid Rivshin 149830c57f07SSekhar Nori slave->phy = phy; 149930c57f07SSekhar Nori 15002220943aSAndrew Lunn phy_attached_info(slave->phy); 15012220943aSAndrew Lunn 1502df828598SMugunthan V N phy_start(slave->phy); 1503388367a5SMugunthan V N 1504388367a5SMugunthan V N /* Configure GMII_SEL register */ 150556e31bd8SIvan Khoronzhuk cpsw_phy_sel(cpsw->dev, slave->phy->interface, slave->slave_num); 1506df828598SMugunthan V N } 1507df828598SMugunthan V N 15083b72c2feSMugunthan V N static inline void cpsw_add_default_vlan(struct cpsw_priv *priv) 15093b72c2feSMugunthan V N { 1510606f3993SIvan Khoronzhuk struct cpsw_common *cpsw = priv->cpsw; 1511606f3993SIvan Khoronzhuk const int vlan = cpsw->data.default_vlan; 15123b72c2feSMugunthan V N u32 reg; 15133b72c2feSMugunthan V N int i; 15141e5c4bc4SLennart Sorensen int unreg_mcast_mask; 15153b72c2feSMugunthan V N 15162a05a622SIvan Khoronzhuk reg = (cpsw->version == CPSW_VERSION_1) ? CPSW1_PORT_VLAN : 15173b72c2feSMugunthan V N CPSW2_PORT_VLAN; 15183b72c2feSMugunthan V N 15195d8d0d4dSIvan Khoronzhuk writel(vlan, &cpsw->host_port_regs->port_vlan); 15203b72c2feSMugunthan V N 1521606f3993SIvan Khoronzhuk for (i = 0; i < cpsw->data.slaves; i++) 1522606f3993SIvan Khoronzhuk slave_write(cpsw->slaves + i, vlan, reg); 15233b72c2feSMugunthan V N 15241e5c4bc4SLennart Sorensen if (priv->ndev->flags & IFF_ALLMULTI) 15251e5c4bc4SLennart Sorensen unreg_mcast_mask = ALE_ALL_PORTS; 15261e5c4bc4SLennart Sorensen else 15271e5c4bc4SLennart Sorensen unreg_mcast_mask = ALE_PORT_1 | ALE_PORT_2; 15281e5c4bc4SLennart Sorensen 15292a05a622SIvan Khoronzhuk cpsw_ale_add_vlan(cpsw->ale, vlan, ALE_ALL_PORTS, 153061f1cef9SGrygorii Strashko ALE_ALL_PORTS, ALE_ALL_PORTS, 153161f1cef9SGrygorii Strashko unreg_mcast_mask); 15323b72c2feSMugunthan V N } 15333b72c2feSMugunthan V N 1534df828598SMugunthan V N static void cpsw_init_host_port(struct cpsw_priv *priv) 1535df828598SMugunthan V N { 1536d9ba8f9eSMugunthan V N u32 fifo_mode; 15375d8d0d4dSIvan Khoronzhuk u32 control_reg; 15385d8d0d4dSIvan Khoronzhuk struct cpsw_common *cpsw = priv->cpsw; 15393b72c2feSMugunthan V N 1540df828598SMugunthan V N /* soft reset the controller and initialize ale */ 15415d8d0d4dSIvan Khoronzhuk soft_reset("cpsw", &cpsw->regs->soft_reset); 15422a05a622SIvan Khoronzhuk cpsw_ale_start(cpsw->ale); 1543df828598SMugunthan V N 1544df828598SMugunthan V N /* switch to vlan unaware mode */ 15452a05a622SIvan Khoronzhuk cpsw_ale_control_set(cpsw->ale, HOST_PORT_NUM, ALE_VLAN_AWARE, 15463b72c2feSMugunthan V N CPSW_ALE_VLAN_AWARE); 15475d8d0d4dSIvan Khoronzhuk control_reg = readl(&cpsw->regs->control); 1548a3a41d2fSGrygorii Strashko control_reg |= CPSW_VLAN_AWARE | CPSW_RX_VLAN_ENCAP; 15495d8d0d4dSIvan Khoronzhuk writel(control_reg, &cpsw->regs->control); 1550606f3993SIvan Khoronzhuk fifo_mode = (cpsw->data.dual_emac) ? CPSW_FIFO_DUAL_MAC_MODE : 1551d9ba8f9eSMugunthan V N CPSW_FIFO_NORMAL_MODE; 15525d8d0d4dSIvan Khoronzhuk writel(fifo_mode, &cpsw->host_port_regs->tx_in_ctl); 1553df828598SMugunthan V N 1554df828598SMugunthan V N /* setup host port priority mapping */ 1555dda5f5feSGrygorii Strashko writel_relaxed(CPDMA_TX_PRIORITY_MAP, 15565d8d0d4dSIvan Khoronzhuk &cpsw->host_port_regs->cpdma_tx_pri_map); 1557dda5f5feSGrygorii Strashko writel_relaxed(0, &cpsw->host_port_regs->cpdma_rx_chan_map); 1558df828598SMugunthan V N 15592a05a622SIvan Khoronzhuk cpsw_ale_control_set(cpsw->ale, HOST_PORT_NUM, 1560df828598SMugunthan V N ALE_PORT_STATE, ALE_PORT_STATE_FORWARD); 1561df828598SMugunthan V N 1562606f3993SIvan Khoronzhuk if (!cpsw->data.dual_emac) { 15632a05a622SIvan Khoronzhuk cpsw_ale_add_ucast(cpsw->ale, priv->mac_addr, HOST_PORT_NUM, 1564d9ba8f9eSMugunthan V N 0, 0); 15652a05a622SIvan Khoronzhuk cpsw_ale_add_mcast(cpsw->ale, priv->ndev->broadcast, 156671a2cbb7SGrygorii Strashko ALE_PORT_HOST, 0, 0, ALE_MCAST_FWD_2); 1567df828598SMugunthan V N } 1568d9ba8f9eSMugunthan V N } 1569df828598SMugunthan V N 15703802dce1SIvan Khoronzhuk static int cpsw_fill_rx_channels(struct cpsw_priv *priv) 15713802dce1SIvan Khoronzhuk { 15723802dce1SIvan Khoronzhuk struct cpsw_common *cpsw = priv->cpsw; 15733802dce1SIvan Khoronzhuk struct sk_buff *skb; 15743802dce1SIvan Khoronzhuk int ch_buf_num; 1575e05107e6SIvan Khoronzhuk int ch, i, ret; 15763802dce1SIvan Khoronzhuk 1577e05107e6SIvan Khoronzhuk for (ch = 0; ch < cpsw->rx_ch_num; ch++) { 15788feb0a19SIvan Khoronzhuk ch_buf_num = cpdma_chan_get_rx_buf_num(cpsw->rxv[ch].ch); 15793802dce1SIvan Khoronzhuk for (i = 0; i < ch_buf_num; i++) { 15803802dce1SIvan Khoronzhuk skb = __netdev_alloc_skb_ip_align(priv->ndev, 15813802dce1SIvan Khoronzhuk cpsw->rx_packet_max, 15823802dce1SIvan Khoronzhuk GFP_KERNEL); 15833802dce1SIvan Khoronzhuk if (!skb) { 15843802dce1SIvan Khoronzhuk cpsw_err(priv, ifup, "cannot allocate skb\n"); 15853802dce1SIvan Khoronzhuk return -ENOMEM; 15863802dce1SIvan Khoronzhuk } 15873802dce1SIvan Khoronzhuk 1588e05107e6SIvan Khoronzhuk skb_set_queue_mapping(skb, ch); 15898feb0a19SIvan Khoronzhuk ret = cpdma_chan_submit(cpsw->rxv[ch].ch, skb, 15908feb0a19SIvan Khoronzhuk skb->data, skb_tailroom(skb), 15918feb0a19SIvan Khoronzhuk 0); 15923802dce1SIvan Khoronzhuk if (ret < 0) { 15933802dce1SIvan Khoronzhuk cpsw_err(priv, ifup, 1594e05107e6SIvan Khoronzhuk "cannot submit skb to channel %d rx, error %d\n", 1595e05107e6SIvan Khoronzhuk ch, ret); 15963802dce1SIvan Khoronzhuk kfree_skb(skb); 15973802dce1SIvan Khoronzhuk return ret; 15983802dce1SIvan Khoronzhuk } 15993802dce1SIvan Khoronzhuk kmemleak_not_leak(skb); 16003802dce1SIvan Khoronzhuk } 16013802dce1SIvan Khoronzhuk 1602e05107e6SIvan Khoronzhuk cpsw_info(priv, ifup, "ch %d rx, submitted %d descriptors\n", 1603e05107e6SIvan Khoronzhuk ch, ch_buf_num); 1604e05107e6SIvan Khoronzhuk } 16053802dce1SIvan Khoronzhuk 1606e05107e6SIvan Khoronzhuk return 0; 16073802dce1SIvan Khoronzhuk } 16083802dce1SIvan Khoronzhuk 16092a05a622SIvan Khoronzhuk static void cpsw_slave_stop(struct cpsw_slave *slave, struct cpsw_common *cpsw) 1610aacebbf8SSebastian Siewior { 16113995d265SSchuyler Patton u32 slave_port; 16123995d265SSchuyler Patton 16136f1f5836SIvan Khoronzhuk slave_port = cpsw_get_slave_port(slave->slave_num); 16143995d265SSchuyler Patton 1615aacebbf8SSebastian Siewior if (!slave->phy) 1616aacebbf8SSebastian Siewior return; 1617aacebbf8SSebastian Siewior phy_stop(slave->phy); 1618aacebbf8SSebastian Siewior phy_disconnect(slave->phy); 1619aacebbf8SSebastian Siewior slave->phy = NULL; 16202a05a622SIvan Khoronzhuk cpsw_ale_control_set(cpsw->ale, slave_port, 16213995d265SSchuyler Patton ALE_PORT_STATE, ALE_PORT_STATE_DISABLE); 16221f95ba00SGrygorii Strashko soft_reset_slave(slave); 1623aacebbf8SSebastian Siewior } 1624aacebbf8SSebastian Siewior 16257929a668SIvan Khoronzhuk static int cpsw_tc_to_fifo(int tc, int num_tc) 16267929a668SIvan Khoronzhuk { 16277929a668SIvan Khoronzhuk if (tc == num_tc - 1) 16287929a668SIvan Khoronzhuk return 0; 16297929a668SIvan Khoronzhuk 16307929a668SIvan Khoronzhuk return CPSW_FIFO_SHAPERS_NUM - tc; 16317929a668SIvan Khoronzhuk } 16327929a668SIvan Khoronzhuk 163357d90148SIvan Khoronzhuk static int cpsw_set_fifo_bw(struct cpsw_priv *priv, int fifo, int bw) 163457d90148SIvan Khoronzhuk { 163557d90148SIvan Khoronzhuk struct cpsw_common *cpsw = priv->cpsw; 163657d90148SIvan Khoronzhuk u32 val = 0, send_pct, shift; 163757d90148SIvan Khoronzhuk struct cpsw_slave *slave; 163857d90148SIvan Khoronzhuk int pct = 0, i; 163957d90148SIvan Khoronzhuk 164057d90148SIvan Khoronzhuk if (bw > priv->shp_cfg_speed * 1000) 164157d90148SIvan Khoronzhuk goto err; 164257d90148SIvan Khoronzhuk 164357d90148SIvan Khoronzhuk /* shaping has to stay enabled for highest fifos linearly 164457d90148SIvan Khoronzhuk * and fifo bw no more then interface can allow 164557d90148SIvan Khoronzhuk */ 164657d90148SIvan Khoronzhuk slave = &cpsw->slaves[cpsw_slave_index(cpsw, priv)]; 164757d90148SIvan Khoronzhuk send_pct = slave_read(slave, SEND_PERCENT); 164857d90148SIvan Khoronzhuk for (i = CPSW_FIFO_SHAPERS_NUM; i > 0; i--) { 164957d90148SIvan Khoronzhuk if (!bw) { 165057d90148SIvan Khoronzhuk if (i >= fifo || !priv->fifo_bw[i]) 165157d90148SIvan Khoronzhuk continue; 165257d90148SIvan Khoronzhuk 165357d90148SIvan Khoronzhuk dev_warn(priv->dev, "Prev FIFO%d is shaped", i); 165457d90148SIvan Khoronzhuk continue; 165557d90148SIvan Khoronzhuk } 165657d90148SIvan Khoronzhuk 165757d90148SIvan Khoronzhuk if (!priv->fifo_bw[i] && i > fifo) { 165857d90148SIvan Khoronzhuk dev_err(priv->dev, "Upper FIFO%d is not shaped", i); 165957d90148SIvan Khoronzhuk return -EINVAL; 166057d90148SIvan Khoronzhuk } 166157d90148SIvan Khoronzhuk 166257d90148SIvan Khoronzhuk shift = (i - 1) * 8; 166357d90148SIvan Khoronzhuk if (i == fifo) { 166457d90148SIvan Khoronzhuk send_pct &= ~(CPSW_PCT_MASK << shift); 166557d90148SIvan Khoronzhuk val = DIV_ROUND_UP(bw, priv->shp_cfg_speed * 10); 166657d90148SIvan Khoronzhuk if (!val) 166757d90148SIvan Khoronzhuk val = 1; 166857d90148SIvan Khoronzhuk 166957d90148SIvan Khoronzhuk send_pct |= val << shift; 167057d90148SIvan Khoronzhuk pct += val; 167157d90148SIvan Khoronzhuk continue; 167257d90148SIvan Khoronzhuk } 167357d90148SIvan Khoronzhuk 167457d90148SIvan Khoronzhuk if (priv->fifo_bw[i]) 167557d90148SIvan Khoronzhuk pct += (send_pct >> shift) & CPSW_PCT_MASK; 167657d90148SIvan Khoronzhuk } 167757d90148SIvan Khoronzhuk 167857d90148SIvan Khoronzhuk if (pct >= 100) 167957d90148SIvan Khoronzhuk goto err; 168057d90148SIvan Khoronzhuk 168157d90148SIvan Khoronzhuk slave_write(slave, send_pct, SEND_PERCENT); 168257d90148SIvan Khoronzhuk priv->fifo_bw[fifo] = bw; 168357d90148SIvan Khoronzhuk 168457d90148SIvan Khoronzhuk dev_warn(priv->dev, "set FIFO%d bw = %d\n", fifo, 168557d90148SIvan Khoronzhuk DIV_ROUND_CLOSEST(val * priv->shp_cfg_speed, 100)); 168657d90148SIvan Khoronzhuk 168757d90148SIvan Khoronzhuk return 0; 168857d90148SIvan Khoronzhuk err: 168957d90148SIvan Khoronzhuk dev_err(priv->dev, "Bandwidth doesn't fit in tc configuration"); 169057d90148SIvan Khoronzhuk return -EINVAL; 169157d90148SIvan Khoronzhuk } 169257d90148SIvan Khoronzhuk 169357d90148SIvan Khoronzhuk static int cpsw_set_fifo_rlimit(struct cpsw_priv *priv, int fifo, int bw) 169457d90148SIvan Khoronzhuk { 169557d90148SIvan Khoronzhuk struct cpsw_common *cpsw = priv->cpsw; 169657d90148SIvan Khoronzhuk struct cpsw_slave *slave; 169757d90148SIvan Khoronzhuk u32 tx_in_ctl_rg, val; 169857d90148SIvan Khoronzhuk int ret; 169957d90148SIvan Khoronzhuk 170057d90148SIvan Khoronzhuk ret = cpsw_set_fifo_bw(priv, fifo, bw); 170157d90148SIvan Khoronzhuk if (ret) 170257d90148SIvan Khoronzhuk return ret; 170357d90148SIvan Khoronzhuk 170457d90148SIvan Khoronzhuk slave = &cpsw->slaves[cpsw_slave_index(cpsw, priv)]; 170557d90148SIvan Khoronzhuk tx_in_ctl_rg = cpsw->version == CPSW_VERSION_1 ? 170657d90148SIvan Khoronzhuk CPSW1_TX_IN_CTL : CPSW2_TX_IN_CTL; 170757d90148SIvan Khoronzhuk 170857d90148SIvan Khoronzhuk if (!bw) 170957d90148SIvan Khoronzhuk cpsw_fifo_shp_on(priv, fifo, bw); 171057d90148SIvan Khoronzhuk 171157d90148SIvan Khoronzhuk val = slave_read(slave, tx_in_ctl_rg); 171257d90148SIvan Khoronzhuk if (cpsw_shp_is_off(priv)) { 171357d90148SIvan Khoronzhuk /* disable FIFOs rate limited queues */ 171457d90148SIvan Khoronzhuk val &= ~(0xf << CPSW_FIFO_RATE_EN_SHIFT); 171557d90148SIvan Khoronzhuk 171657d90148SIvan Khoronzhuk /* set type of FIFO queues to normal priority mode */ 171757d90148SIvan Khoronzhuk val &= ~(3 << CPSW_FIFO_QUEUE_TYPE_SHIFT); 171857d90148SIvan Khoronzhuk 171957d90148SIvan Khoronzhuk /* set type of FIFO queues to be rate limited */ 172057d90148SIvan Khoronzhuk if (bw) 172157d90148SIvan Khoronzhuk val |= 2 << CPSW_FIFO_QUEUE_TYPE_SHIFT; 172257d90148SIvan Khoronzhuk else 172357d90148SIvan Khoronzhuk priv->shp_cfg_speed = 0; 172457d90148SIvan Khoronzhuk } 172557d90148SIvan Khoronzhuk 172657d90148SIvan Khoronzhuk /* toggle a FIFO rate limited queue */ 172757d90148SIvan Khoronzhuk if (bw) 172857d90148SIvan Khoronzhuk val |= BIT(fifo + CPSW_FIFO_RATE_EN_SHIFT); 172957d90148SIvan Khoronzhuk else 173057d90148SIvan Khoronzhuk val &= ~BIT(fifo + CPSW_FIFO_RATE_EN_SHIFT); 173157d90148SIvan Khoronzhuk slave_write(slave, val, tx_in_ctl_rg); 173257d90148SIvan Khoronzhuk 173357d90148SIvan Khoronzhuk /* FIFO transmit shape enable */ 173457d90148SIvan Khoronzhuk cpsw_fifo_shp_on(priv, fifo, bw); 173557d90148SIvan Khoronzhuk return 0; 173657d90148SIvan Khoronzhuk } 173757d90148SIvan Khoronzhuk 173857d90148SIvan Khoronzhuk /* Defaults: 173957d90148SIvan Khoronzhuk * class A - prio 3 174057d90148SIvan Khoronzhuk * class B - prio 2 174157d90148SIvan Khoronzhuk * shaping for class A should be set first 174257d90148SIvan Khoronzhuk */ 174357d90148SIvan Khoronzhuk static int cpsw_set_cbs(struct net_device *ndev, 174457d90148SIvan Khoronzhuk struct tc_cbs_qopt_offload *qopt) 174557d90148SIvan Khoronzhuk { 174657d90148SIvan Khoronzhuk struct cpsw_priv *priv = netdev_priv(ndev); 174757d90148SIvan Khoronzhuk struct cpsw_common *cpsw = priv->cpsw; 174857d90148SIvan Khoronzhuk struct cpsw_slave *slave; 174957d90148SIvan Khoronzhuk int prev_speed = 0; 175057d90148SIvan Khoronzhuk int tc, ret, fifo; 175157d90148SIvan Khoronzhuk u32 bw = 0; 175257d90148SIvan Khoronzhuk 175357d90148SIvan Khoronzhuk tc = netdev_txq_to_tc(priv->ndev, qopt->queue); 175457d90148SIvan Khoronzhuk 175557d90148SIvan Khoronzhuk /* enable channels in backward order, as highest FIFOs must be rate 175657d90148SIvan Khoronzhuk * limited first and for compliance with CPDMA rate limited channels 175757d90148SIvan Khoronzhuk * that also used in bacward order. FIFO0 cannot be rate limited. 175857d90148SIvan Khoronzhuk */ 175957d90148SIvan Khoronzhuk fifo = cpsw_tc_to_fifo(tc, ndev->num_tc); 176057d90148SIvan Khoronzhuk if (!fifo) { 176157d90148SIvan Khoronzhuk dev_err(priv->dev, "Last tc%d can't be rate limited", tc); 176257d90148SIvan Khoronzhuk return -EINVAL; 176357d90148SIvan Khoronzhuk } 176457d90148SIvan Khoronzhuk 176557d90148SIvan Khoronzhuk /* do nothing, it's disabled anyway */ 176657d90148SIvan Khoronzhuk if (!qopt->enable && !priv->fifo_bw[fifo]) 176757d90148SIvan Khoronzhuk return 0; 176857d90148SIvan Khoronzhuk 176957d90148SIvan Khoronzhuk /* shapers can be set if link speed is known */ 177057d90148SIvan Khoronzhuk slave = &cpsw->slaves[cpsw_slave_index(cpsw, priv)]; 177157d90148SIvan Khoronzhuk if (slave->phy && slave->phy->link) { 177257d90148SIvan Khoronzhuk if (priv->shp_cfg_speed && 177357d90148SIvan Khoronzhuk priv->shp_cfg_speed != slave->phy->speed) 177457d90148SIvan Khoronzhuk prev_speed = priv->shp_cfg_speed; 177557d90148SIvan Khoronzhuk 177657d90148SIvan Khoronzhuk priv->shp_cfg_speed = slave->phy->speed; 177757d90148SIvan Khoronzhuk } 177857d90148SIvan Khoronzhuk 177957d90148SIvan Khoronzhuk if (!priv->shp_cfg_speed) { 178057d90148SIvan Khoronzhuk dev_err(priv->dev, "Link speed is not known"); 178157d90148SIvan Khoronzhuk return -1; 178257d90148SIvan Khoronzhuk } 178357d90148SIvan Khoronzhuk 178457d90148SIvan Khoronzhuk ret = pm_runtime_get_sync(cpsw->dev); 178557d90148SIvan Khoronzhuk if (ret < 0) { 178657d90148SIvan Khoronzhuk pm_runtime_put_noidle(cpsw->dev); 178757d90148SIvan Khoronzhuk return ret; 178857d90148SIvan Khoronzhuk } 178957d90148SIvan Khoronzhuk 179057d90148SIvan Khoronzhuk bw = qopt->enable ? qopt->idleslope : 0; 179157d90148SIvan Khoronzhuk ret = cpsw_set_fifo_rlimit(priv, fifo, bw); 179257d90148SIvan Khoronzhuk if (ret) { 179357d90148SIvan Khoronzhuk priv->shp_cfg_speed = prev_speed; 179457d90148SIvan Khoronzhuk prev_speed = 0; 179557d90148SIvan Khoronzhuk } 179657d90148SIvan Khoronzhuk 179757d90148SIvan Khoronzhuk if (bw && prev_speed) 179857d90148SIvan Khoronzhuk dev_warn(priv->dev, 179957d90148SIvan Khoronzhuk "Speed was changed, CBS shaper speeds are changed!"); 180057d90148SIvan Khoronzhuk 180157d90148SIvan Khoronzhuk pm_runtime_put_sync(cpsw->dev); 180257d90148SIvan Khoronzhuk return ret; 180357d90148SIvan Khoronzhuk } 180457d90148SIvan Khoronzhuk 18054b4255edSIvan Khoronzhuk static void cpsw_cbs_resume(struct cpsw_slave *slave, struct cpsw_priv *priv) 18064b4255edSIvan Khoronzhuk { 18074b4255edSIvan Khoronzhuk int fifo, bw; 18084b4255edSIvan Khoronzhuk 18094b4255edSIvan Khoronzhuk for (fifo = CPSW_FIFO_SHAPERS_NUM; fifo > 0; fifo--) { 18104b4255edSIvan Khoronzhuk bw = priv->fifo_bw[fifo]; 18114b4255edSIvan Khoronzhuk if (!bw) 18124b4255edSIvan Khoronzhuk continue; 18134b4255edSIvan Khoronzhuk 18144b4255edSIvan Khoronzhuk cpsw_set_fifo_rlimit(priv, fifo, bw); 18154b4255edSIvan Khoronzhuk } 18164b4255edSIvan Khoronzhuk } 18174b4255edSIvan Khoronzhuk 18184b4255edSIvan Khoronzhuk static void cpsw_mqprio_resume(struct cpsw_slave *slave, struct cpsw_priv *priv) 18194b4255edSIvan Khoronzhuk { 18204b4255edSIvan Khoronzhuk struct cpsw_common *cpsw = priv->cpsw; 18214b4255edSIvan Khoronzhuk u32 tx_prio_map = 0; 18224b4255edSIvan Khoronzhuk int i, tc, fifo; 18234b4255edSIvan Khoronzhuk u32 tx_prio_rg; 18244b4255edSIvan Khoronzhuk 18254b4255edSIvan Khoronzhuk if (!priv->mqprio_hw) 18264b4255edSIvan Khoronzhuk return; 18274b4255edSIvan Khoronzhuk 18284b4255edSIvan Khoronzhuk for (i = 0; i < 8; i++) { 18294b4255edSIvan Khoronzhuk tc = netdev_get_prio_tc_map(priv->ndev, i); 18304b4255edSIvan Khoronzhuk fifo = CPSW_FIFO_SHAPERS_NUM - tc; 18314b4255edSIvan Khoronzhuk tx_prio_map |= fifo << (4 * i); 18324b4255edSIvan Khoronzhuk } 18334b4255edSIvan Khoronzhuk 18344b4255edSIvan Khoronzhuk tx_prio_rg = cpsw->version == CPSW_VERSION_1 ? 18354b4255edSIvan Khoronzhuk CPSW1_TX_PRI_MAP : CPSW2_TX_PRI_MAP; 18364b4255edSIvan Khoronzhuk 18374b4255edSIvan Khoronzhuk slave_write(slave, tx_prio_map, tx_prio_rg); 18384b4255edSIvan Khoronzhuk } 18394b4255edSIvan Khoronzhuk 18404b4255edSIvan Khoronzhuk /* restore resources after port reset */ 18414b4255edSIvan Khoronzhuk static void cpsw_restore(struct cpsw_priv *priv) 18424b4255edSIvan Khoronzhuk { 18434b4255edSIvan Khoronzhuk /* restore MQPRIO offload */ 18444b4255edSIvan Khoronzhuk for_each_slave(priv, cpsw_mqprio_resume, priv); 18454b4255edSIvan Khoronzhuk 18464b4255edSIvan Khoronzhuk /* restore CBS offload */ 18474b4255edSIvan Khoronzhuk for_each_slave(priv, cpsw_cbs_resume, priv); 18484b4255edSIvan Khoronzhuk } 18494b4255edSIvan Khoronzhuk 1850df828598SMugunthan V N static int cpsw_ndo_open(struct net_device *ndev) 1851df828598SMugunthan V N { 1852df828598SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 1853649a1688SIvan Khoronzhuk struct cpsw_common *cpsw = priv->cpsw; 18543802dce1SIvan Khoronzhuk int ret; 1855df828598SMugunthan V N u32 reg; 1856df828598SMugunthan V N 185756e31bd8SIvan Khoronzhuk ret = pm_runtime_get_sync(cpsw->dev); 1858108a6537SGrygorii Strashko if (ret < 0) { 185956e31bd8SIvan Khoronzhuk pm_runtime_put_noidle(cpsw->dev); 1860108a6537SGrygorii Strashko return ret; 1861108a6537SGrygorii Strashko } 18623fa88c51SGrygorii Strashko 1863df828598SMugunthan V N netif_carrier_off(ndev); 1864df828598SMugunthan V N 1865e05107e6SIvan Khoronzhuk /* Notify the stack of the actual queue counts. */ 1866e05107e6SIvan Khoronzhuk ret = netif_set_real_num_tx_queues(ndev, cpsw->tx_ch_num); 1867e05107e6SIvan Khoronzhuk if (ret) { 1868e05107e6SIvan Khoronzhuk dev_err(priv->dev, "cannot set real number of tx queues\n"); 1869e05107e6SIvan Khoronzhuk goto err_cleanup; 1870e05107e6SIvan Khoronzhuk } 1871e05107e6SIvan Khoronzhuk 1872e05107e6SIvan Khoronzhuk ret = netif_set_real_num_rx_queues(ndev, cpsw->rx_ch_num); 1873e05107e6SIvan Khoronzhuk if (ret) { 1874e05107e6SIvan Khoronzhuk dev_err(priv->dev, "cannot set real number of rx queues\n"); 1875e05107e6SIvan Khoronzhuk goto err_cleanup; 1876e05107e6SIvan Khoronzhuk } 1877e05107e6SIvan Khoronzhuk 18782a05a622SIvan Khoronzhuk reg = cpsw->version; 1879df828598SMugunthan V N 1880df828598SMugunthan V N dev_info(priv->dev, "initializing cpsw version %d.%d (%d)\n", 1881df828598SMugunthan V N CPSW_MAJOR_VERSION(reg), CPSW_MINOR_VERSION(reg), 1882df828598SMugunthan V N CPSW_RTL_VERSION(reg)); 1883df828598SMugunthan V N 1884d5bc1613SIvan Khoronzhuk /* Initialize host and slave ports */ 1885d5bc1613SIvan Khoronzhuk if (!cpsw->usage_count) 1886df828598SMugunthan V N cpsw_init_host_port(priv); 1887df828598SMugunthan V N for_each_slave(priv, cpsw_slave_open, priv); 1888df828598SMugunthan V N 18893b72c2feSMugunthan V N /* Add default VLAN */ 1890606f3993SIvan Khoronzhuk if (!cpsw->data.dual_emac) 18913b72c2feSMugunthan V N cpsw_add_default_vlan(priv); 1892e6afea0bSMugunthan V N else 18932a05a622SIvan Khoronzhuk cpsw_ale_add_vlan(cpsw->ale, cpsw->data.default_vlan, 189461f1cef9SGrygorii Strashko ALE_ALL_PORTS, ALE_ALL_PORTS, 0, 0); 18953b72c2feSMugunthan V N 1896d5bc1613SIvan Khoronzhuk /* initialize shared resources for every ndev */ 1897d5bc1613SIvan Khoronzhuk if (!cpsw->usage_count) { 1898d9ba8f9eSMugunthan V N /* disable priority elevation */ 1899dda5f5feSGrygorii Strashko writel_relaxed(0, &cpsw->regs->ptype); 1900df828598SMugunthan V N 1901d9ba8f9eSMugunthan V N /* enable statistics collection only on all ports */ 1902dda5f5feSGrygorii Strashko writel_relaxed(0x7, &cpsw->regs->stat_port_en); 1903df828598SMugunthan V N 19041923d6e4SMugunthan V N /* Enable internal fifo flow control */ 19055d8d0d4dSIvan Khoronzhuk writel(0x7, &cpsw->regs->flow_control); 19061923d6e4SMugunthan V N 1907dbc4ec52SIvan Khoronzhuk napi_enable(&cpsw->napi_rx); 1908dbc4ec52SIvan Khoronzhuk napi_enable(&cpsw->napi_tx); 1909d354eb85SMugunthan V N 1910e38b5a3dSIvan Khoronzhuk if (cpsw->tx_irq_disabled) { 1911e38b5a3dSIvan Khoronzhuk cpsw->tx_irq_disabled = false; 1912e38b5a3dSIvan Khoronzhuk enable_irq(cpsw->irqs_table[1]); 19137da11600SMugunthan V N } 19147da11600SMugunthan V N 1915e38b5a3dSIvan Khoronzhuk if (cpsw->rx_irq_disabled) { 1916e38b5a3dSIvan Khoronzhuk cpsw->rx_irq_disabled = false; 1917e38b5a3dSIvan Khoronzhuk enable_irq(cpsw->irqs_table[0]); 19187da11600SMugunthan V N } 19197da11600SMugunthan V N 19203802dce1SIvan Khoronzhuk ret = cpsw_fill_rx_channels(priv); 19213802dce1SIvan Khoronzhuk if (ret < 0) 1922aacebbf8SSebastian Siewior goto err_cleanup; 1923f280e89aSMugunthan V N 19248a2c9a5aSGrygorii Strashko if (cpts_register(cpsw->cpts)) 1925f280e89aSMugunthan V N dev_err(priv->dev, "error registering cpts device\n"); 1926f280e89aSMugunthan V N 1927d9ba8f9eSMugunthan V N } 1928df828598SMugunthan V N 19294b4255edSIvan Khoronzhuk cpsw_restore(priv); 19304b4255edSIvan Khoronzhuk 1931ff5b8ef2SMugunthan V N /* Enable Interrupt pacing if configured */ 19322a05a622SIvan Khoronzhuk if (cpsw->coal_intvl != 0) { 1933ff5b8ef2SMugunthan V N struct ethtool_coalesce coal; 1934ff5b8ef2SMugunthan V N 19352a05a622SIvan Khoronzhuk coal.rx_coalesce_usecs = cpsw->coal_intvl; 1936ff5b8ef2SMugunthan V N cpsw_set_coalesce(ndev, &coal); 1937ff5b8ef2SMugunthan V N } 1938ff5b8ef2SMugunthan V N 19392c836bd9SIvan Khoronzhuk cpdma_ctlr_start(cpsw->dma); 19402c836bd9SIvan Khoronzhuk cpsw_intr_enable(cpsw); 1941d5bc1613SIvan Khoronzhuk cpsw->usage_count++; 1942f63a975eSMugunthan V N 1943df828598SMugunthan V N return 0; 1944df828598SMugunthan V N 1945aacebbf8SSebastian Siewior err_cleanup: 19462c836bd9SIvan Khoronzhuk cpdma_ctlr_stop(cpsw->dma); 19472a05a622SIvan Khoronzhuk for_each_slave(priv, cpsw_slave_stop, cpsw); 194856e31bd8SIvan Khoronzhuk pm_runtime_put_sync(cpsw->dev); 1949aacebbf8SSebastian Siewior netif_carrier_off(priv->ndev); 1950aacebbf8SSebastian Siewior return ret; 1951df828598SMugunthan V N } 1952df828598SMugunthan V N 1953df828598SMugunthan V N static int cpsw_ndo_stop(struct net_device *ndev) 1954df828598SMugunthan V N { 1955df828598SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 1956649a1688SIvan Khoronzhuk struct cpsw_common *cpsw = priv->cpsw; 1957df828598SMugunthan V N 1958df828598SMugunthan V N cpsw_info(priv, ifdown, "shutting down cpsw device\n"); 1959e05107e6SIvan Khoronzhuk netif_tx_stop_all_queues(priv->ndev); 1960df828598SMugunthan V N netif_carrier_off(priv->ndev); 1961d9ba8f9eSMugunthan V N 1962d5bc1613SIvan Khoronzhuk if (cpsw->usage_count <= 1) { 1963dbc4ec52SIvan Khoronzhuk napi_disable(&cpsw->napi_rx); 1964dbc4ec52SIvan Khoronzhuk napi_disable(&cpsw->napi_tx); 19652a05a622SIvan Khoronzhuk cpts_unregister(cpsw->cpts); 19662c836bd9SIvan Khoronzhuk cpsw_intr_disable(cpsw); 19672c836bd9SIvan Khoronzhuk cpdma_ctlr_stop(cpsw->dma); 19682a05a622SIvan Khoronzhuk cpsw_ale_stop(cpsw->ale); 1969d9ba8f9eSMugunthan V N } 19702a05a622SIvan Khoronzhuk for_each_slave(priv, cpsw_slave_stop, cpsw); 19710be01b8eSIvan Khoronzhuk 19720be01b8eSIvan Khoronzhuk if (cpsw_need_resplit(cpsw)) 19730be01b8eSIvan Khoronzhuk cpsw_split_res(ndev); 19740be01b8eSIvan Khoronzhuk 1975d5bc1613SIvan Khoronzhuk cpsw->usage_count--; 197656e31bd8SIvan Khoronzhuk pm_runtime_put_sync(cpsw->dev); 1977df828598SMugunthan V N return 0; 1978df828598SMugunthan V N } 1979df828598SMugunthan V N 1980df828598SMugunthan V N static netdev_tx_t cpsw_ndo_start_xmit(struct sk_buff *skb, 1981df828598SMugunthan V N struct net_device *ndev) 1982df828598SMugunthan V N { 1983df828598SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 19842c836bd9SIvan Khoronzhuk struct cpsw_common *cpsw = priv->cpsw; 1985f44f8417SIvan Khoronzhuk struct cpts *cpts = cpsw->cpts; 1986e05107e6SIvan Khoronzhuk struct netdev_queue *txq; 1987e05107e6SIvan Khoronzhuk struct cpdma_chan *txch; 1988e05107e6SIvan Khoronzhuk int ret, q_idx; 1989df828598SMugunthan V N 1990df828598SMugunthan V N if (skb_padto(skb, CPSW_MIN_PACKET_SIZE)) { 1991df828598SMugunthan V N cpsw_err(priv, tx_err, "packet pad failed\n"); 19928dc43ddcSTobias Klauser ndev->stats.tx_dropped++; 19931bf96050SIvan Khoronzhuk return NET_XMIT_DROP; 1994df828598SMugunthan V N } 1995df828598SMugunthan V N 19969232b16dSMugunthan V N if (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP && 1997f44f8417SIvan Khoronzhuk cpts_is_tx_enabled(cpts) && cpts_can_timestamp(cpts, skb)) 19982e5b38abSRichard Cochran skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 19992e5b38abSRichard Cochran 2000e05107e6SIvan Khoronzhuk q_idx = skb_get_queue_mapping(skb); 2001e05107e6SIvan Khoronzhuk if (q_idx >= cpsw->tx_ch_num) 2002e05107e6SIvan Khoronzhuk q_idx = q_idx % cpsw->tx_ch_num; 2003e05107e6SIvan Khoronzhuk 20048feb0a19SIvan Khoronzhuk txch = cpsw->txv[q_idx].ch; 200562f94c21SGrygorii Strashko txq = netdev_get_tx_queue(ndev, q_idx); 2006e05107e6SIvan Khoronzhuk ret = cpsw_tx_packet_submit(priv, skb, txch); 2007df828598SMugunthan V N if (unlikely(ret != 0)) { 2008df828598SMugunthan V N cpsw_err(priv, tx_err, "desc submit failed\n"); 2009df828598SMugunthan V N goto fail; 2010df828598SMugunthan V N } 2011df828598SMugunthan V N 2012fae50823SMugunthan V N /* If there is no more tx desc left free then we need to 2013fae50823SMugunthan V N * tell the kernel to stop sending us tx frames. 2014fae50823SMugunthan V N */ 2015e05107e6SIvan Khoronzhuk if (unlikely(!cpdma_check_free_tx_desc(txch))) { 2016e05107e6SIvan Khoronzhuk netif_tx_stop_queue(txq); 201762f94c21SGrygorii Strashko 201862f94c21SGrygorii Strashko /* Barrier, so that stop_queue visible to other cpus */ 201962f94c21SGrygorii Strashko smp_mb__after_atomic(); 202062f94c21SGrygorii Strashko 202162f94c21SGrygorii Strashko if (cpdma_check_free_tx_desc(txch)) 202262f94c21SGrygorii Strashko netif_tx_wake_queue(txq); 2023e05107e6SIvan Khoronzhuk } 2024fae50823SMugunthan V N 2025df828598SMugunthan V N return NETDEV_TX_OK; 2026df828598SMugunthan V N fail: 20278dc43ddcSTobias Klauser ndev->stats.tx_dropped++; 2028e05107e6SIvan Khoronzhuk netif_tx_stop_queue(txq); 202962f94c21SGrygorii Strashko 203062f94c21SGrygorii Strashko /* Barrier, so that stop_queue visible to other cpus */ 203162f94c21SGrygorii Strashko smp_mb__after_atomic(); 203262f94c21SGrygorii Strashko 203362f94c21SGrygorii Strashko if (cpdma_check_free_tx_desc(txch)) 203462f94c21SGrygorii Strashko netif_tx_wake_queue(txq); 203562f94c21SGrygorii Strashko 2036df828598SMugunthan V N return NETDEV_TX_BUSY; 2037df828598SMugunthan V N } 2038df828598SMugunthan V N 2039c8395d4eSGrygorii Strashko #if IS_ENABLED(CONFIG_TI_CPTS) 20402e5b38abSRichard Cochran 20412a05a622SIvan Khoronzhuk static void cpsw_hwtstamp_v1(struct cpsw_common *cpsw) 20422e5b38abSRichard Cochran { 2043606f3993SIvan Khoronzhuk struct cpsw_slave *slave = &cpsw->slaves[cpsw->data.active_slave]; 20442e5b38abSRichard Cochran u32 ts_en, seq_id; 20452e5b38abSRichard Cochran 2046b63ba58eSGrygorii Strashko if (!cpts_is_tx_enabled(cpsw->cpts) && 2047b63ba58eSGrygorii Strashko !cpts_is_rx_enabled(cpsw->cpts)) { 20482e5b38abSRichard Cochran slave_write(slave, 0, CPSW1_TS_CTL); 20492e5b38abSRichard Cochran return; 20502e5b38abSRichard Cochran } 20512e5b38abSRichard Cochran 20522e5b38abSRichard Cochran seq_id = (30 << CPSW_V1_SEQ_ID_OFS_SHIFT) | ETH_P_1588; 20532e5b38abSRichard Cochran ts_en = EVENT_MSG_BITS << CPSW_V1_MSG_TYPE_OFS; 20542e5b38abSRichard Cochran 2055b63ba58eSGrygorii Strashko if (cpts_is_tx_enabled(cpsw->cpts)) 20562e5b38abSRichard Cochran ts_en |= CPSW_V1_TS_TX_EN; 20572e5b38abSRichard Cochran 2058b63ba58eSGrygorii Strashko if (cpts_is_rx_enabled(cpsw->cpts)) 20592e5b38abSRichard Cochran ts_en |= CPSW_V1_TS_RX_EN; 20602e5b38abSRichard Cochran 20612e5b38abSRichard Cochran slave_write(slave, ts_en, CPSW1_TS_CTL); 20622e5b38abSRichard Cochran slave_write(slave, seq_id, CPSW1_TS_SEQ_LTYPE); 20632e5b38abSRichard Cochran } 20642e5b38abSRichard Cochran 20652e5b38abSRichard Cochran static void cpsw_hwtstamp_v2(struct cpsw_priv *priv) 20662e5b38abSRichard Cochran { 2067d9ba8f9eSMugunthan V N struct cpsw_slave *slave; 20685d8d0d4dSIvan Khoronzhuk struct cpsw_common *cpsw = priv->cpsw; 20692e5b38abSRichard Cochran u32 ctrl, mtype; 20702e5b38abSRichard Cochran 2071cb7d78d0SIvan Khoronzhuk slave = &cpsw->slaves[cpsw_slave_index(cpsw, priv)]; 2072d9ba8f9eSMugunthan V N 20732e5b38abSRichard Cochran ctrl = slave_read(slave, CPSW2_CONTROL); 20742a05a622SIvan Khoronzhuk switch (cpsw->version) { 207509c55372SGeorge Cherian case CPSW_VERSION_2: 207609c55372SGeorge Cherian ctrl &= ~CTRL_V2_ALL_TS_MASK; 20772e5b38abSRichard Cochran 2078b63ba58eSGrygorii Strashko if (cpts_is_tx_enabled(cpsw->cpts)) 207909c55372SGeorge Cherian ctrl |= CTRL_V2_TX_TS_BITS; 20802e5b38abSRichard Cochran 2081b63ba58eSGrygorii Strashko if (cpts_is_rx_enabled(cpsw->cpts)) 208209c55372SGeorge Cherian ctrl |= CTRL_V2_RX_TS_BITS; 208309c55372SGeorge Cherian break; 208409c55372SGeorge Cherian case CPSW_VERSION_3: 208509c55372SGeorge Cherian default: 208609c55372SGeorge Cherian ctrl &= ~CTRL_V3_ALL_TS_MASK; 208709c55372SGeorge Cherian 2088b63ba58eSGrygorii Strashko if (cpts_is_tx_enabled(cpsw->cpts)) 208909c55372SGeorge Cherian ctrl |= CTRL_V3_TX_TS_BITS; 209009c55372SGeorge Cherian 2091b63ba58eSGrygorii Strashko if (cpts_is_rx_enabled(cpsw->cpts)) 209209c55372SGeorge Cherian ctrl |= CTRL_V3_RX_TS_BITS; 209309c55372SGeorge Cherian break; 209409c55372SGeorge Cherian } 20952e5b38abSRichard Cochran 20962e5b38abSRichard Cochran mtype = (30 << TS_SEQ_ID_OFFSET_SHIFT) | EVENT_MSG_BITS; 20972e5b38abSRichard Cochran 20982e5b38abSRichard Cochran slave_write(slave, mtype, CPSW2_TS_SEQ_MTYPE); 20992e5b38abSRichard Cochran slave_write(slave, ctrl, CPSW2_CONTROL); 2100dda5f5feSGrygorii Strashko writel_relaxed(ETH_P_1588, &cpsw->regs->ts_ltype); 21012e5b38abSRichard Cochran } 21022e5b38abSRichard Cochran 2103a5b4145bSBen Hutchings static int cpsw_hwtstamp_set(struct net_device *dev, struct ifreq *ifr) 21042e5b38abSRichard Cochran { 21053177bf6fSMugunthan V N struct cpsw_priv *priv = netdev_priv(dev); 21062e5b38abSRichard Cochran struct hwtstamp_config cfg; 21072a05a622SIvan Khoronzhuk struct cpsw_common *cpsw = priv->cpsw; 21082a05a622SIvan Khoronzhuk struct cpts *cpts = cpsw->cpts; 21092e5b38abSRichard Cochran 21102a05a622SIvan Khoronzhuk if (cpsw->version != CPSW_VERSION_1 && 21112a05a622SIvan Khoronzhuk cpsw->version != CPSW_VERSION_2 && 21122a05a622SIvan Khoronzhuk cpsw->version != CPSW_VERSION_3) 21132ee91e54SBen Hutchings return -EOPNOTSUPP; 21142ee91e54SBen Hutchings 21152e5b38abSRichard Cochran if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg))) 21162e5b38abSRichard Cochran return -EFAULT; 21172e5b38abSRichard Cochran 21182e5b38abSRichard Cochran /* reserved for future extensions */ 21192e5b38abSRichard Cochran if (cfg.flags) 21202e5b38abSRichard Cochran return -EINVAL; 21212e5b38abSRichard Cochran 21222ee91e54SBen Hutchings if (cfg.tx_type != HWTSTAMP_TX_OFF && cfg.tx_type != HWTSTAMP_TX_ON) 21232e5b38abSRichard Cochran return -ERANGE; 21242e5b38abSRichard Cochran 21252e5b38abSRichard Cochran switch (cfg.rx_filter) { 21262e5b38abSRichard Cochran case HWTSTAMP_FILTER_NONE: 2127b63ba58eSGrygorii Strashko cpts_rx_enable(cpts, 0); 21282e5b38abSRichard Cochran break; 21292e5b38abSRichard Cochran case HWTSTAMP_FILTER_ALL: 2130e9523a5aSGrygorii Strashko case HWTSTAMP_FILTER_NTP_ALL: 2131e9523a5aSGrygorii Strashko return -ERANGE; 21322e5b38abSRichard Cochran case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: 21332e5b38abSRichard Cochran case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: 21342e5b38abSRichard Cochran case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: 2135e9523a5aSGrygorii Strashko cpts_rx_enable(cpts, HWTSTAMP_FILTER_PTP_V1_L4_EVENT); 2136e9523a5aSGrygorii Strashko cfg.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT; 2137e9523a5aSGrygorii Strashko break; 21382e5b38abSRichard Cochran case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: 21392e5b38abSRichard Cochran case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 21402e5b38abSRichard Cochran case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 21412e5b38abSRichard Cochran case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: 21422e5b38abSRichard Cochran case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: 21432e5b38abSRichard Cochran case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: 21442e5b38abSRichard Cochran case HWTSTAMP_FILTER_PTP_V2_EVENT: 21452e5b38abSRichard Cochran case HWTSTAMP_FILTER_PTP_V2_SYNC: 21462e5b38abSRichard Cochran case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 2147e9523a5aSGrygorii Strashko cpts_rx_enable(cpts, HWTSTAMP_FILTER_PTP_V2_EVENT); 21482e5b38abSRichard Cochran cfg.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT; 21492e5b38abSRichard Cochran break; 21502e5b38abSRichard Cochran default: 21512e5b38abSRichard Cochran return -ERANGE; 21522e5b38abSRichard Cochran } 21532e5b38abSRichard Cochran 2154b63ba58eSGrygorii Strashko cpts_tx_enable(cpts, cfg.tx_type == HWTSTAMP_TX_ON); 21552ee91e54SBen Hutchings 21562a05a622SIvan Khoronzhuk switch (cpsw->version) { 21572e5b38abSRichard Cochran case CPSW_VERSION_1: 21582a05a622SIvan Khoronzhuk cpsw_hwtstamp_v1(cpsw); 21592e5b38abSRichard Cochran break; 21602e5b38abSRichard Cochran case CPSW_VERSION_2: 2161f7d403cbSGeorge Cherian case CPSW_VERSION_3: 21622e5b38abSRichard Cochran cpsw_hwtstamp_v2(priv); 21632e5b38abSRichard Cochran break; 21642e5b38abSRichard Cochran default: 21652ee91e54SBen Hutchings WARN_ON(1); 21662e5b38abSRichard Cochran } 21672e5b38abSRichard Cochran 21682e5b38abSRichard Cochran return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0; 21692e5b38abSRichard Cochran } 21702e5b38abSRichard Cochran 2171a5b4145bSBen Hutchings static int cpsw_hwtstamp_get(struct net_device *dev, struct ifreq *ifr) 2172a5b4145bSBen Hutchings { 21732a05a622SIvan Khoronzhuk struct cpsw_common *cpsw = ndev_to_cpsw(dev); 21742a05a622SIvan Khoronzhuk struct cpts *cpts = cpsw->cpts; 2175a5b4145bSBen Hutchings struct hwtstamp_config cfg; 2176a5b4145bSBen Hutchings 21772a05a622SIvan Khoronzhuk if (cpsw->version != CPSW_VERSION_1 && 21782a05a622SIvan Khoronzhuk cpsw->version != CPSW_VERSION_2 && 21792a05a622SIvan Khoronzhuk cpsw->version != CPSW_VERSION_3) 2180a5b4145bSBen Hutchings return -EOPNOTSUPP; 2181a5b4145bSBen Hutchings 2182a5b4145bSBen Hutchings cfg.flags = 0; 2183b63ba58eSGrygorii Strashko cfg.tx_type = cpts_is_tx_enabled(cpts) ? 2184b63ba58eSGrygorii Strashko HWTSTAMP_TX_ON : HWTSTAMP_TX_OFF; 2185b63ba58eSGrygorii Strashko cfg.rx_filter = (cpts_is_rx_enabled(cpts) ? 2186e9523a5aSGrygorii Strashko cpts->rx_enable : HWTSTAMP_FILTER_NONE); 2187a5b4145bSBen Hutchings 2188a5b4145bSBen Hutchings return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0; 2189a5b4145bSBen Hutchings } 2190c8395d4eSGrygorii Strashko #else 2191c8395d4eSGrygorii Strashko static int cpsw_hwtstamp_get(struct net_device *dev, struct ifreq *ifr) 2192c8395d4eSGrygorii Strashko { 2193c8395d4eSGrygorii Strashko return -EOPNOTSUPP; 2194c8395d4eSGrygorii Strashko } 2195a5b4145bSBen Hutchings 2196c8395d4eSGrygorii Strashko static int cpsw_hwtstamp_set(struct net_device *dev, struct ifreq *ifr) 2197c8395d4eSGrygorii Strashko { 2198c8395d4eSGrygorii Strashko return -EOPNOTSUPP; 2199c8395d4eSGrygorii Strashko } 22002e5b38abSRichard Cochran #endif /*CONFIG_TI_CPTS*/ 22012e5b38abSRichard Cochran 22022e5b38abSRichard Cochran static int cpsw_ndo_ioctl(struct net_device *dev, struct ifreq *req, int cmd) 22032e5b38abSRichard Cochran { 220411f2c988SMugunthan V N struct cpsw_priv *priv = netdev_priv(dev); 2205606f3993SIvan Khoronzhuk struct cpsw_common *cpsw = priv->cpsw; 2206606f3993SIvan Khoronzhuk int slave_no = cpsw_slave_index(cpsw, priv); 220711f2c988SMugunthan V N 22082e5b38abSRichard Cochran if (!netif_running(dev)) 22092e5b38abSRichard Cochran return -EINVAL; 22102e5b38abSRichard Cochran 221111f2c988SMugunthan V N switch (cmd) { 221211f2c988SMugunthan V N case SIOCSHWTSTAMP: 2213a5b4145bSBen Hutchings return cpsw_hwtstamp_set(dev, req); 2214a5b4145bSBen Hutchings case SIOCGHWTSTAMP: 2215a5b4145bSBen Hutchings return cpsw_hwtstamp_get(dev, req); 22162e5b38abSRichard Cochran } 22172e5b38abSRichard Cochran 2218606f3993SIvan Khoronzhuk if (!cpsw->slaves[slave_no].phy) 2219c1b59947SStefan Sørensen return -EOPNOTSUPP; 2220606f3993SIvan Khoronzhuk return phy_mii_ioctl(cpsw->slaves[slave_no].phy, req, cmd); 222111f2c988SMugunthan V N } 222211f2c988SMugunthan V N 2223df828598SMugunthan V N static void cpsw_ndo_tx_timeout(struct net_device *ndev) 2224df828598SMugunthan V N { 2225df828598SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 22262c836bd9SIvan Khoronzhuk struct cpsw_common *cpsw = priv->cpsw; 2227e05107e6SIvan Khoronzhuk int ch; 2228df828598SMugunthan V N 2229df828598SMugunthan V N cpsw_err(priv, tx_err, "transmit timeout, restarting dma\n"); 22308dc43ddcSTobias Klauser ndev->stats.tx_errors++; 22312c836bd9SIvan Khoronzhuk cpsw_intr_disable(cpsw); 2232e05107e6SIvan Khoronzhuk for (ch = 0; ch < cpsw->tx_ch_num; ch++) { 22338feb0a19SIvan Khoronzhuk cpdma_chan_stop(cpsw->txv[ch].ch); 22348feb0a19SIvan Khoronzhuk cpdma_chan_start(cpsw->txv[ch].ch); 2235e05107e6SIvan Khoronzhuk } 2236e05107e6SIvan Khoronzhuk 22372c836bd9SIvan Khoronzhuk cpsw_intr_enable(cpsw); 223875514b66SGrygorii Strashko netif_trans_update(ndev); 223975514b66SGrygorii Strashko netif_tx_wake_all_queues(ndev); 2240df828598SMugunthan V N } 2241df828598SMugunthan V N 2242dcfd8d58SMugunthan V N static int cpsw_ndo_set_mac_address(struct net_device *ndev, void *p) 2243dcfd8d58SMugunthan V N { 2244dcfd8d58SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 2245dcfd8d58SMugunthan V N struct sockaddr *addr = (struct sockaddr *)p; 2246649a1688SIvan Khoronzhuk struct cpsw_common *cpsw = priv->cpsw; 2247dcfd8d58SMugunthan V N int flags = 0; 2248dcfd8d58SMugunthan V N u16 vid = 0; 2249a6c5d14fSGrygorii Strashko int ret; 2250dcfd8d58SMugunthan V N 2251dcfd8d58SMugunthan V N if (!is_valid_ether_addr(addr->sa_data)) 2252dcfd8d58SMugunthan V N return -EADDRNOTAVAIL; 2253dcfd8d58SMugunthan V N 225456e31bd8SIvan Khoronzhuk ret = pm_runtime_get_sync(cpsw->dev); 2255a6c5d14fSGrygorii Strashko if (ret < 0) { 225656e31bd8SIvan Khoronzhuk pm_runtime_put_noidle(cpsw->dev); 2257a6c5d14fSGrygorii Strashko return ret; 2258a6c5d14fSGrygorii Strashko } 2259a6c5d14fSGrygorii Strashko 2260606f3993SIvan Khoronzhuk if (cpsw->data.dual_emac) { 2261606f3993SIvan Khoronzhuk vid = cpsw->slaves[priv->emac_port].port_vlan; 2262dcfd8d58SMugunthan V N flags = ALE_VLAN; 2263dcfd8d58SMugunthan V N } 2264dcfd8d58SMugunthan V N 22652a05a622SIvan Khoronzhuk cpsw_ale_del_ucast(cpsw->ale, priv->mac_addr, HOST_PORT_NUM, 2266dcfd8d58SMugunthan V N flags, vid); 22672a05a622SIvan Khoronzhuk cpsw_ale_add_ucast(cpsw->ale, addr->sa_data, HOST_PORT_NUM, 2268dcfd8d58SMugunthan V N flags, vid); 2269dcfd8d58SMugunthan V N 2270dcfd8d58SMugunthan V N memcpy(priv->mac_addr, addr->sa_data, ETH_ALEN); 2271dcfd8d58SMugunthan V N memcpy(ndev->dev_addr, priv->mac_addr, ETH_ALEN); 2272dcfd8d58SMugunthan V N for_each_slave(priv, cpsw_set_slave_mac, priv); 2273dcfd8d58SMugunthan V N 227456e31bd8SIvan Khoronzhuk pm_runtime_put(cpsw->dev); 2275a6c5d14fSGrygorii Strashko 2276dcfd8d58SMugunthan V N return 0; 2277dcfd8d58SMugunthan V N } 2278dcfd8d58SMugunthan V N 2279df828598SMugunthan V N #ifdef CONFIG_NET_POLL_CONTROLLER 2280df828598SMugunthan V N static void cpsw_ndo_poll_controller(struct net_device *ndev) 2281df828598SMugunthan V N { 2282dbc4ec52SIvan Khoronzhuk struct cpsw_common *cpsw = ndev_to_cpsw(ndev); 2283df828598SMugunthan V N 2284dbc4ec52SIvan Khoronzhuk cpsw_intr_disable(cpsw); 2285dbc4ec52SIvan Khoronzhuk cpsw_rx_interrupt(cpsw->irqs_table[0], cpsw); 2286dbc4ec52SIvan Khoronzhuk cpsw_tx_interrupt(cpsw->irqs_table[1], cpsw); 2287dbc4ec52SIvan Khoronzhuk cpsw_intr_enable(cpsw); 2288df828598SMugunthan V N } 2289df828598SMugunthan V N #endif 2290df828598SMugunthan V N 22913b72c2feSMugunthan V N static inline int cpsw_add_vlan_ale_entry(struct cpsw_priv *priv, 22923b72c2feSMugunthan V N unsigned short vid) 22933b72c2feSMugunthan V N { 22943b72c2feSMugunthan V N int ret; 22959f6bd8faSMugunthan V N int unreg_mcast_mask = 0; 22969f6bd8faSMugunthan V N u32 port_mask; 2297606f3993SIvan Khoronzhuk struct cpsw_common *cpsw = priv->cpsw; 22989f6bd8faSMugunthan V N 2299606f3993SIvan Khoronzhuk if (cpsw->data.dual_emac) { 23009f6bd8faSMugunthan V N port_mask = (1 << (priv->emac_port + 1)) | ALE_PORT_HOST; 23019f6bd8faSMugunthan V N 23029f6bd8faSMugunthan V N if (priv->ndev->flags & IFF_ALLMULTI) 23039f6bd8faSMugunthan V N unreg_mcast_mask = port_mask; 23049f6bd8faSMugunthan V N } else { 23059f6bd8faSMugunthan V N port_mask = ALE_ALL_PORTS; 23061e5c4bc4SLennart Sorensen 23071e5c4bc4SLennart Sorensen if (priv->ndev->flags & IFF_ALLMULTI) 23081e5c4bc4SLennart Sorensen unreg_mcast_mask = ALE_ALL_PORTS; 23091e5c4bc4SLennart Sorensen else 23101e5c4bc4SLennart Sorensen unreg_mcast_mask = ALE_PORT_1 | ALE_PORT_2; 23119f6bd8faSMugunthan V N } 23123b72c2feSMugunthan V N 23132a05a622SIvan Khoronzhuk ret = cpsw_ale_add_vlan(cpsw->ale, vid, port_mask, 0, port_mask, 231461f1cef9SGrygorii Strashko unreg_mcast_mask); 23153b72c2feSMugunthan V N if (ret != 0) 23163b72c2feSMugunthan V N return ret; 23173b72c2feSMugunthan V N 23182a05a622SIvan Khoronzhuk ret = cpsw_ale_add_ucast(cpsw->ale, priv->mac_addr, 231971a2cbb7SGrygorii Strashko HOST_PORT_NUM, ALE_VLAN, vid); 23203b72c2feSMugunthan V N if (ret != 0) 23213b72c2feSMugunthan V N goto clean_vid; 23223b72c2feSMugunthan V N 23232a05a622SIvan Khoronzhuk ret = cpsw_ale_add_mcast(cpsw->ale, priv->ndev->broadcast, 23249f6bd8faSMugunthan V N port_mask, ALE_VLAN, vid, 0); 23253b72c2feSMugunthan V N if (ret != 0) 23263b72c2feSMugunthan V N goto clean_vlan_ucast; 23273b72c2feSMugunthan V N return 0; 23283b72c2feSMugunthan V N 23293b72c2feSMugunthan V N clean_vlan_ucast: 23302a05a622SIvan Khoronzhuk cpsw_ale_del_ucast(cpsw->ale, priv->mac_addr, 233171a2cbb7SGrygorii Strashko HOST_PORT_NUM, ALE_VLAN, vid); 23323b72c2feSMugunthan V N clean_vid: 23332a05a622SIvan Khoronzhuk cpsw_ale_del_vlan(cpsw->ale, vid, 0); 23343b72c2feSMugunthan V N return ret; 23353b72c2feSMugunthan V N } 23363b72c2feSMugunthan V N 23373b72c2feSMugunthan V N static int cpsw_ndo_vlan_rx_add_vid(struct net_device *ndev, 233880d5c368SPatrick McHardy __be16 proto, u16 vid) 23393b72c2feSMugunthan V N { 23403b72c2feSMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 2341649a1688SIvan Khoronzhuk struct cpsw_common *cpsw = priv->cpsw; 2342a6c5d14fSGrygorii Strashko int ret; 23433b72c2feSMugunthan V N 2344606f3993SIvan Khoronzhuk if (vid == cpsw->data.default_vlan) 23453b72c2feSMugunthan V N return 0; 23463b72c2feSMugunthan V N 234756e31bd8SIvan Khoronzhuk ret = pm_runtime_get_sync(cpsw->dev); 2348a6c5d14fSGrygorii Strashko if (ret < 0) { 234956e31bd8SIvan Khoronzhuk pm_runtime_put_noidle(cpsw->dev); 2350a6c5d14fSGrygorii Strashko return ret; 2351a6c5d14fSGrygorii Strashko } 2352a6c5d14fSGrygorii Strashko 2353606f3993SIvan Khoronzhuk if (cpsw->data.dual_emac) { 235402a54164SMugunthan V N /* In dual EMAC, reserved VLAN id should not be used for 235502a54164SMugunthan V N * creating VLAN interfaces as this can break the dual 235602a54164SMugunthan V N * EMAC port separation 235702a54164SMugunthan V N */ 235802a54164SMugunthan V N int i; 235902a54164SMugunthan V N 2360606f3993SIvan Khoronzhuk for (i = 0; i < cpsw->data.slaves; i++) { 2361606f3993SIvan Khoronzhuk if (vid == cpsw->slaves[i].port_vlan) 236202a54164SMugunthan V N return -EINVAL; 236302a54164SMugunthan V N } 236402a54164SMugunthan V N } 236502a54164SMugunthan V N 23663b72c2feSMugunthan V N dev_info(priv->dev, "Adding vlanid %d to vlan filter\n", vid); 2367a6c5d14fSGrygorii Strashko ret = cpsw_add_vlan_ale_entry(priv, vid); 2368a6c5d14fSGrygorii Strashko 236956e31bd8SIvan Khoronzhuk pm_runtime_put(cpsw->dev); 2370a6c5d14fSGrygorii Strashko return ret; 23713b72c2feSMugunthan V N } 23723b72c2feSMugunthan V N 23733b72c2feSMugunthan V N static int cpsw_ndo_vlan_rx_kill_vid(struct net_device *ndev, 237480d5c368SPatrick McHardy __be16 proto, u16 vid) 23753b72c2feSMugunthan V N { 23763b72c2feSMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 2377649a1688SIvan Khoronzhuk struct cpsw_common *cpsw = priv->cpsw; 23783b72c2feSMugunthan V N int ret; 23793b72c2feSMugunthan V N 2380606f3993SIvan Khoronzhuk if (vid == cpsw->data.default_vlan) 23813b72c2feSMugunthan V N return 0; 23823b72c2feSMugunthan V N 238356e31bd8SIvan Khoronzhuk ret = pm_runtime_get_sync(cpsw->dev); 2384a6c5d14fSGrygorii Strashko if (ret < 0) { 238556e31bd8SIvan Khoronzhuk pm_runtime_put_noidle(cpsw->dev); 2386a6c5d14fSGrygorii Strashko return ret; 2387a6c5d14fSGrygorii Strashko } 2388a6c5d14fSGrygorii Strashko 2389606f3993SIvan Khoronzhuk if (cpsw->data.dual_emac) { 239002a54164SMugunthan V N int i; 239102a54164SMugunthan V N 2392606f3993SIvan Khoronzhuk for (i = 0; i < cpsw->data.slaves; i++) { 2393606f3993SIvan Khoronzhuk if (vid == cpsw->slaves[i].port_vlan) 239402a54164SMugunthan V N return -EINVAL; 239502a54164SMugunthan V N } 239602a54164SMugunthan V N } 239702a54164SMugunthan V N 23983b72c2feSMugunthan V N dev_info(priv->dev, "removing vlanid %d from vlan filter\n", vid); 23992a05a622SIvan Khoronzhuk ret = cpsw_ale_del_vlan(cpsw->ale, vid, 0); 24003b72c2feSMugunthan V N if (ret != 0) 24013b72c2feSMugunthan V N return ret; 24023b72c2feSMugunthan V N 24032a05a622SIvan Khoronzhuk ret = cpsw_ale_del_ucast(cpsw->ale, priv->mac_addr, 240461f1cef9SGrygorii Strashko HOST_PORT_NUM, ALE_VLAN, vid); 24053b72c2feSMugunthan V N if (ret != 0) 24063b72c2feSMugunthan V N return ret; 24073b72c2feSMugunthan V N 24082a05a622SIvan Khoronzhuk ret = cpsw_ale_del_mcast(cpsw->ale, priv->ndev->broadcast, 24093b72c2feSMugunthan V N 0, ALE_VLAN, vid); 241056e31bd8SIvan Khoronzhuk pm_runtime_put(cpsw->dev); 2411a6c5d14fSGrygorii Strashko return ret; 24123b72c2feSMugunthan V N } 24133b72c2feSMugunthan V N 241483fcad0cSIvan Khoronzhuk static int cpsw_ndo_set_tx_maxrate(struct net_device *ndev, int queue, u32 rate) 241583fcad0cSIvan Khoronzhuk { 241683fcad0cSIvan Khoronzhuk struct cpsw_priv *priv = netdev_priv(ndev); 241783fcad0cSIvan Khoronzhuk struct cpsw_common *cpsw = priv->cpsw; 241852986a2fSIvan Khoronzhuk struct cpsw_slave *slave; 241932b78d85SIvan Khoronzhuk u32 min_rate; 242083fcad0cSIvan Khoronzhuk u32 ch_rate; 242152986a2fSIvan Khoronzhuk int i, ret; 242283fcad0cSIvan Khoronzhuk 242383fcad0cSIvan Khoronzhuk ch_rate = netdev_get_tx_queue(ndev, queue)->tx_maxrate; 242483fcad0cSIvan Khoronzhuk if (ch_rate == rate) 242583fcad0cSIvan Khoronzhuk return 0; 242683fcad0cSIvan Khoronzhuk 242732b78d85SIvan Khoronzhuk ch_rate = rate * 1000; 242883fcad0cSIvan Khoronzhuk min_rate = cpdma_chan_get_min_rate(cpsw->dma); 242932b78d85SIvan Khoronzhuk if ((ch_rate < min_rate && ch_rate)) { 243032b78d85SIvan Khoronzhuk dev_err(priv->dev, "The channel rate cannot be less than %dMbps", 243183fcad0cSIvan Khoronzhuk min_rate); 243283fcad0cSIvan Khoronzhuk return -EINVAL; 243383fcad0cSIvan Khoronzhuk } 243483fcad0cSIvan Khoronzhuk 24350be01b8eSIvan Khoronzhuk if (rate > cpsw->speed) { 243632b78d85SIvan Khoronzhuk dev_err(priv->dev, "The channel rate cannot be more than 2Gbps"); 243732b78d85SIvan Khoronzhuk return -EINVAL; 243832b78d85SIvan Khoronzhuk } 243932b78d85SIvan Khoronzhuk 244083fcad0cSIvan Khoronzhuk ret = pm_runtime_get_sync(cpsw->dev); 244183fcad0cSIvan Khoronzhuk if (ret < 0) { 244283fcad0cSIvan Khoronzhuk pm_runtime_put_noidle(cpsw->dev); 244383fcad0cSIvan Khoronzhuk return ret; 244483fcad0cSIvan Khoronzhuk } 244583fcad0cSIvan Khoronzhuk 244632b78d85SIvan Khoronzhuk ret = cpdma_chan_set_rate(cpsw->txv[queue].ch, ch_rate); 244783fcad0cSIvan Khoronzhuk pm_runtime_put(cpsw->dev); 244832b78d85SIvan Khoronzhuk 244932b78d85SIvan Khoronzhuk if (ret) 245032b78d85SIvan Khoronzhuk return ret; 245132b78d85SIvan Khoronzhuk 245252986a2fSIvan Khoronzhuk /* update rates for slaves tx queues */ 245352986a2fSIvan Khoronzhuk for (i = 0; i < cpsw->data.slaves; i++) { 245452986a2fSIvan Khoronzhuk slave = &cpsw->slaves[i]; 245552986a2fSIvan Khoronzhuk if (!slave->ndev) 245652986a2fSIvan Khoronzhuk continue; 245752986a2fSIvan Khoronzhuk 245852986a2fSIvan Khoronzhuk netdev_get_tx_queue(slave->ndev, queue)->tx_maxrate = rate; 245952986a2fSIvan Khoronzhuk } 246052986a2fSIvan Khoronzhuk 246132b78d85SIvan Khoronzhuk cpsw_split_res(ndev); 246283fcad0cSIvan Khoronzhuk return ret; 246383fcad0cSIvan Khoronzhuk } 246483fcad0cSIvan Khoronzhuk 24657929a668SIvan Khoronzhuk static int cpsw_set_mqprio(struct net_device *ndev, void *type_data) 24667929a668SIvan Khoronzhuk { 24677929a668SIvan Khoronzhuk struct tc_mqprio_qopt_offload *mqprio = type_data; 24687929a668SIvan Khoronzhuk struct cpsw_priv *priv = netdev_priv(ndev); 24697929a668SIvan Khoronzhuk struct cpsw_common *cpsw = priv->cpsw; 24707929a668SIvan Khoronzhuk int fifo, num_tc, count, offset; 24717929a668SIvan Khoronzhuk struct cpsw_slave *slave; 24727929a668SIvan Khoronzhuk u32 tx_prio_map = 0; 24737929a668SIvan Khoronzhuk int i, tc, ret; 24747929a668SIvan Khoronzhuk 24757929a668SIvan Khoronzhuk num_tc = mqprio->qopt.num_tc; 24767929a668SIvan Khoronzhuk if (num_tc > CPSW_TC_NUM) 24777929a668SIvan Khoronzhuk return -EINVAL; 24787929a668SIvan Khoronzhuk 24797929a668SIvan Khoronzhuk if (mqprio->mode != TC_MQPRIO_MODE_DCB) 24807929a668SIvan Khoronzhuk return -EINVAL; 24817929a668SIvan Khoronzhuk 24827929a668SIvan Khoronzhuk ret = pm_runtime_get_sync(cpsw->dev); 24837929a668SIvan Khoronzhuk if (ret < 0) { 24847929a668SIvan Khoronzhuk pm_runtime_put_noidle(cpsw->dev); 24857929a668SIvan Khoronzhuk return ret; 24867929a668SIvan Khoronzhuk } 24877929a668SIvan Khoronzhuk 24887929a668SIvan Khoronzhuk if (num_tc) { 24897929a668SIvan Khoronzhuk for (i = 0; i < 8; i++) { 24907929a668SIvan Khoronzhuk tc = mqprio->qopt.prio_tc_map[i]; 24917929a668SIvan Khoronzhuk fifo = cpsw_tc_to_fifo(tc, num_tc); 24927929a668SIvan Khoronzhuk tx_prio_map |= fifo << (4 * i); 24937929a668SIvan Khoronzhuk } 24947929a668SIvan Khoronzhuk 24957929a668SIvan Khoronzhuk netdev_set_num_tc(ndev, num_tc); 24967929a668SIvan Khoronzhuk for (i = 0; i < num_tc; i++) { 24977929a668SIvan Khoronzhuk count = mqprio->qopt.count[i]; 24987929a668SIvan Khoronzhuk offset = mqprio->qopt.offset[i]; 24997929a668SIvan Khoronzhuk netdev_set_tc_queue(ndev, i, count, offset); 25007929a668SIvan Khoronzhuk } 25017929a668SIvan Khoronzhuk } 25027929a668SIvan Khoronzhuk 25037929a668SIvan Khoronzhuk if (!mqprio->qopt.hw) { 25047929a668SIvan Khoronzhuk /* restore default configuration */ 25057929a668SIvan Khoronzhuk netdev_reset_tc(ndev); 25067929a668SIvan Khoronzhuk tx_prio_map = TX_PRIORITY_MAPPING; 25077929a668SIvan Khoronzhuk } 25087929a668SIvan Khoronzhuk 25097929a668SIvan Khoronzhuk priv->mqprio_hw = mqprio->qopt.hw; 25107929a668SIvan Khoronzhuk 25117929a668SIvan Khoronzhuk offset = cpsw->version == CPSW_VERSION_1 ? 25127929a668SIvan Khoronzhuk CPSW1_TX_PRI_MAP : CPSW2_TX_PRI_MAP; 25137929a668SIvan Khoronzhuk 25147929a668SIvan Khoronzhuk slave = &cpsw->slaves[cpsw_slave_index(cpsw, priv)]; 25157929a668SIvan Khoronzhuk slave_write(slave, tx_prio_map, offset); 25167929a668SIvan Khoronzhuk 25177929a668SIvan Khoronzhuk pm_runtime_put_sync(cpsw->dev); 25187929a668SIvan Khoronzhuk 25197929a668SIvan Khoronzhuk return 0; 25207929a668SIvan Khoronzhuk } 25217929a668SIvan Khoronzhuk 25227929a668SIvan Khoronzhuk static int cpsw_ndo_setup_tc(struct net_device *ndev, enum tc_setup_type type, 25237929a668SIvan Khoronzhuk void *type_data) 25247929a668SIvan Khoronzhuk { 25257929a668SIvan Khoronzhuk switch (type) { 252657d90148SIvan Khoronzhuk case TC_SETUP_QDISC_CBS: 252757d90148SIvan Khoronzhuk return cpsw_set_cbs(ndev, type_data); 252857d90148SIvan Khoronzhuk 25297929a668SIvan Khoronzhuk case TC_SETUP_QDISC_MQPRIO: 25307929a668SIvan Khoronzhuk return cpsw_set_mqprio(ndev, type_data); 25317929a668SIvan Khoronzhuk 25327929a668SIvan Khoronzhuk default: 25337929a668SIvan Khoronzhuk return -EOPNOTSUPP; 25347929a668SIvan Khoronzhuk } 25357929a668SIvan Khoronzhuk } 25367929a668SIvan Khoronzhuk 2537df828598SMugunthan V N static const struct net_device_ops cpsw_netdev_ops = { 2538df828598SMugunthan V N .ndo_open = cpsw_ndo_open, 2539df828598SMugunthan V N .ndo_stop = cpsw_ndo_stop, 2540df828598SMugunthan V N .ndo_start_xmit = cpsw_ndo_start_xmit, 2541dcfd8d58SMugunthan V N .ndo_set_mac_address = cpsw_ndo_set_mac_address, 25422e5b38abSRichard Cochran .ndo_do_ioctl = cpsw_ndo_ioctl, 2543df828598SMugunthan V N .ndo_validate_addr = eth_validate_addr, 2544df828598SMugunthan V N .ndo_tx_timeout = cpsw_ndo_tx_timeout, 25455c50a856SMugunthan V N .ndo_set_rx_mode = cpsw_ndo_set_rx_mode, 254683fcad0cSIvan Khoronzhuk .ndo_set_tx_maxrate = cpsw_ndo_set_tx_maxrate, 2547df828598SMugunthan V N #ifdef CONFIG_NET_POLL_CONTROLLER 2548df828598SMugunthan V N .ndo_poll_controller = cpsw_ndo_poll_controller, 2549df828598SMugunthan V N #endif 25503b72c2feSMugunthan V N .ndo_vlan_rx_add_vid = cpsw_ndo_vlan_rx_add_vid, 25513b72c2feSMugunthan V N .ndo_vlan_rx_kill_vid = cpsw_ndo_vlan_rx_kill_vid, 25527929a668SIvan Khoronzhuk .ndo_setup_tc = cpsw_ndo_setup_tc, 2553df828598SMugunthan V N }; 2554df828598SMugunthan V N 255552c4f0ecSMugunthan V N static int cpsw_get_regs_len(struct net_device *ndev) 255652c4f0ecSMugunthan V N { 2557606f3993SIvan Khoronzhuk struct cpsw_common *cpsw = ndev_to_cpsw(ndev); 255852c4f0ecSMugunthan V N 2559606f3993SIvan Khoronzhuk return cpsw->data.ale_entries * ALE_ENTRY_WORDS * sizeof(u32); 256052c4f0ecSMugunthan V N } 256152c4f0ecSMugunthan V N 256252c4f0ecSMugunthan V N static void cpsw_get_regs(struct net_device *ndev, 256352c4f0ecSMugunthan V N struct ethtool_regs *regs, void *p) 256452c4f0ecSMugunthan V N { 256552c4f0ecSMugunthan V N u32 *reg = p; 25662a05a622SIvan Khoronzhuk struct cpsw_common *cpsw = ndev_to_cpsw(ndev); 256752c4f0ecSMugunthan V N 256852c4f0ecSMugunthan V N /* update CPSW IP version */ 25692a05a622SIvan Khoronzhuk regs->version = cpsw->version; 257052c4f0ecSMugunthan V N 25712a05a622SIvan Khoronzhuk cpsw_ale_dump(cpsw->ale, reg); 257252c4f0ecSMugunthan V N } 257352c4f0ecSMugunthan V N 2574df828598SMugunthan V N static void cpsw_get_drvinfo(struct net_device *ndev, 2575df828598SMugunthan V N struct ethtool_drvinfo *info) 2576df828598SMugunthan V N { 2577649a1688SIvan Khoronzhuk struct cpsw_common *cpsw = ndev_to_cpsw(ndev); 257856e31bd8SIvan Khoronzhuk struct platform_device *pdev = to_platform_device(cpsw->dev); 25797826d43fSJiri Pirko 258052c4f0ecSMugunthan V N strlcpy(info->driver, "cpsw", sizeof(info->driver)); 25817826d43fSJiri Pirko strlcpy(info->version, "1.0", sizeof(info->version)); 258256e31bd8SIvan Khoronzhuk strlcpy(info->bus_info, pdev->name, sizeof(info->bus_info)); 2583df828598SMugunthan V N } 2584df828598SMugunthan V N 2585df828598SMugunthan V N static u32 cpsw_get_msglevel(struct net_device *ndev) 2586df828598SMugunthan V N { 2587df828598SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 2588df828598SMugunthan V N return priv->msg_enable; 2589df828598SMugunthan V N } 2590df828598SMugunthan V N 2591df828598SMugunthan V N static void cpsw_set_msglevel(struct net_device *ndev, u32 value) 2592df828598SMugunthan V N { 2593df828598SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 2594df828598SMugunthan V N priv->msg_enable = value; 2595df828598SMugunthan V N } 2596df828598SMugunthan V N 2597c8395d4eSGrygorii Strashko #if IS_ENABLED(CONFIG_TI_CPTS) 25982e5b38abSRichard Cochran static int cpsw_get_ts_info(struct net_device *ndev, 25992e5b38abSRichard Cochran struct ethtool_ts_info *info) 26002e5b38abSRichard Cochran { 26012a05a622SIvan Khoronzhuk struct cpsw_common *cpsw = ndev_to_cpsw(ndev); 26022e5b38abSRichard Cochran 26032e5b38abSRichard Cochran info->so_timestamping = 26042e5b38abSRichard Cochran SOF_TIMESTAMPING_TX_HARDWARE | 26052e5b38abSRichard Cochran SOF_TIMESTAMPING_TX_SOFTWARE | 26062e5b38abSRichard Cochran SOF_TIMESTAMPING_RX_HARDWARE | 26072e5b38abSRichard Cochran SOF_TIMESTAMPING_RX_SOFTWARE | 26082e5b38abSRichard Cochran SOF_TIMESTAMPING_SOFTWARE | 26092e5b38abSRichard Cochran SOF_TIMESTAMPING_RAW_HARDWARE; 26102a05a622SIvan Khoronzhuk info->phc_index = cpsw->cpts->phc_index; 26112e5b38abSRichard Cochran info->tx_types = 26122e5b38abSRichard Cochran (1 << HWTSTAMP_TX_OFF) | 26132e5b38abSRichard Cochran (1 << HWTSTAMP_TX_ON); 26142e5b38abSRichard Cochran info->rx_filters = 26152e5b38abSRichard Cochran (1 << HWTSTAMP_FILTER_NONE) | 2616e9523a5aSGrygorii Strashko (1 << HWTSTAMP_FILTER_PTP_V1_L4_EVENT) | 26172e5b38abSRichard Cochran (1 << HWTSTAMP_FILTER_PTP_V2_EVENT); 2618c8395d4eSGrygorii Strashko return 0; 2619c8395d4eSGrygorii Strashko } 26202e5b38abSRichard Cochran #else 2621c8395d4eSGrygorii Strashko static int cpsw_get_ts_info(struct net_device *ndev, 2622c8395d4eSGrygorii Strashko struct ethtool_ts_info *info) 2623c8395d4eSGrygorii Strashko { 26242e5b38abSRichard Cochran info->so_timestamping = 26252e5b38abSRichard Cochran SOF_TIMESTAMPING_TX_SOFTWARE | 26262e5b38abSRichard Cochran SOF_TIMESTAMPING_RX_SOFTWARE | 26272e5b38abSRichard Cochran SOF_TIMESTAMPING_SOFTWARE; 26282e5b38abSRichard Cochran info->phc_index = -1; 26292e5b38abSRichard Cochran info->tx_types = 0; 26302e5b38abSRichard Cochran info->rx_filters = 0; 26312e5b38abSRichard Cochran return 0; 26322e5b38abSRichard Cochran } 2633c8395d4eSGrygorii Strashko #endif 26342e5b38abSRichard Cochran 26352479876dSPhilippe Reynes static int cpsw_get_link_ksettings(struct net_device *ndev, 26362479876dSPhilippe Reynes struct ethtool_link_ksettings *ecmd) 2637d3bb9c58SMugunthan V N { 2638d3bb9c58SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 2639606f3993SIvan Khoronzhuk struct cpsw_common *cpsw = priv->cpsw; 2640606f3993SIvan Khoronzhuk int slave_no = cpsw_slave_index(cpsw, priv); 2641d3bb9c58SMugunthan V N 26425514174fSyuval.shaia@oracle.com if (!cpsw->slaves[slave_no].phy) 2643d3bb9c58SMugunthan V N return -EOPNOTSUPP; 26445514174fSyuval.shaia@oracle.com 26455514174fSyuval.shaia@oracle.com phy_ethtool_ksettings_get(cpsw->slaves[slave_no].phy, ecmd); 26465514174fSyuval.shaia@oracle.com return 0; 2647d3bb9c58SMugunthan V N } 2648d3bb9c58SMugunthan V N 26492479876dSPhilippe Reynes static int cpsw_set_link_ksettings(struct net_device *ndev, 26502479876dSPhilippe Reynes const struct ethtool_link_ksettings *ecmd) 2651d3bb9c58SMugunthan V N { 2652d3bb9c58SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 2653606f3993SIvan Khoronzhuk struct cpsw_common *cpsw = priv->cpsw; 2654606f3993SIvan Khoronzhuk int slave_no = cpsw_slave_index(cpsw, priv); 2655d3bb9c58SMugunthan V N 2656606f3993SIvan Khoronzhuk if (cpsw->slaves[slave_no].phy) 26572479876dSPhilippe Reynes return phy_ethtool_ksettings_set(cpsw->slaves[slave_no].phy, 26582479876dSPhilippe Reynes ecmd); 2659d3bb9c58SMugunthan V N else 2660d3bb9c58SMugunthan V N return -EOPNOTSUPP; 2661d3bb9c58SMugunthan V N } 2662d3bb9c58SMugunthan V N 2663d8a64420SMatus Ujhelyi static void cpsw_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol) 2664d8a64420SMatus Ujhelyi { 2665d8a64420SMatus Ujhelyi struct cpsw_priv *priv = netdev_priv(ndev); 2666606f3993SIvan Khoronzhuk struct cpsw_common *cpsw = priv->cpsw; 2667606f3993SIvan Khoronzhuk int slave_no = cpsw_slave_index(cpsw, priv); 2668d8a64420SMatus Ujhelyi 2669d8a64420SMatus Ujhelyi wol->supported = 0; 2670d8a64420SMatus Ujhelyi wol->wolopts = 0; 2671d8a64420SMatus Ujhelyi 2672606f3993SIvan Khoronzhuk if (cpsw->slaves[slave_no].phy) 2673606f3993SIvan Khoronzhuk phy_ethtool_get_wol(cpsw->slaves[slave_no].phy, wol); 2674d8a64420SMatus Ujhelyi } 2675d8a64420SMatus Ujhelyi 2676d8a64420SMatus Ujhelyi static int cpsw_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol) 2677d8a64420SMatus Ujhelyi { 2678d8a64420SMatus Ujhelyi struct cpsw_priv *priv = netdev_priv(ndev); 2679606f3993SIvan Khoronzhuk struct cpsw_common *cpsw = priv->cpsw; 2680606f3993SIvan Khoronzhuk int slave_no = cpsw_slave_index(cpsw, priv); 2681d8a64420SMatus Ujhelyi 2682606f3993SIvan Khoronzhuk if (cpsw->slaves[slave_no].phy) 2683606f3993SIvan Khoronzhuk return phy_ethtool_set_wol(cpsw->slaves[slave_no].phy, wol); 2684d8a64420SMatus Ujhelyi else 2685d8a64420SMatus Ujhelyi return -EOPNOTSUPP; 2686d8a64420SMatus Ujhelyi } 2687d8a64420SMatus Ujhelyi 26881923d6e4SMugunthan V N static void cpsw_get_pauseparam(struct net_device *ndev, 26891923d6e4SMugunthan V N struct ethtool_pauseparam *pause) 26901923d6e4SMugunthan V N { 26911923d6e4SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 26921923d6e4SMugunthan V N 26931923d6e4SMugunthan V N pause->autoneg = AUTONEG_DISABLE; 26941923d6e4SMugunthan V N pause->rx_pause = priv->rx_pause ? true : false; 26951923d6e4SMugunthan V N pause->tx_pause = priv->tx_pause ? true : false; 26961923d6e4SMugunthan V N } 26971923d6e4SMugunthan V N 26981923d6e4SMugunthan V N static int cpsw_set_pauseparam(struct net_device *ndev, 26991923d6e4SMugunthan V N struct ethtool_pauseparam *pause) 27001923d6e4SMugunthan V N { 27011923d6e4SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 27021923d6e4SMugunthan V N bool link; 27031923d6e4SMugunthan V N 27041923d6e4SMugunthan V N priv->rx_pause = pause->rx_pause ? true : false; 27051923d6e4SMugunthan V N priv->tx_pause = pause->tx_pause ? true : false; 27061923d6e4SMugunthan V N 27071923d6e4SMugunthan V N for_each_slave(priv, _cpsw_adjust_link, priv, &link); 27081923d6e4SMugunthan V N return 0; 27091923d6e4SMugunthan V N } 27101923d6e4SMugunthan V N 27117898b1daSGrygorii Strashko static int cpsw_ethtool_op_begin(struct net_device *ndev) 27127898b1daSGrygorii Strashko { 27137898b1daSGrygorii Strashko struct cpsw_priv *priv = netdev_priv(ndev); 2714649a1688SIvan Khoronzhuk struct cpsw_common *cpsw = priv->cpsw; 27157898b1daSGrygorii Strashko int ret; 27167898b1daSGrygorii Strashko 271756e31bd8SIvan Khoronzhuk ret = pm_runtime_get_sync(cpsw->dev); 27187898b1daSGrygorii Strashko if (ret < 0) { 27197898b1daSGrygorii Strashko cpsw_err(priv, drv, "ethtool begin failed %d\n", ret); 272056e31bd8SIvan Khoronzhuk pm_runtime_put_noidle(cpsw->dev); 27217898b1daSGrygorii Strashko } 27227898b1daSGrygorii Strashko 27237898b1daSGrygorii Strashko return ret; 27247898b1daSGrygorii Strashko } 27257898b1daSGrygorii Strashko 27267898b1daSGrygorii Strashko static void cpsw_ethtool_op_complete(struct net_device *ndev) 27277898b1daSGrygorii Strashko { 27287898b1daSGrygorii Strashko struct cpsw_priv *priv = netdev_priv(ndev); 27297898b1daSGrygorii Strashko int ret; 27307898b1daSGrygorii Strashko 273156e31bd8SIvan Khoronzhuk ret = pm_runtime_put(priv->cpsw->dev); 27327898b1daSGrygorii Strashko if (ret < 0) 27337898b1daSGrygorii Strashko cpsw_err(priv, drv, "ethtool complete failed %d\n", ret); 27347898b1daSGrygorii Strashko } 27357898b1daSGrygorii Strashko 2736ce52c744SIvan Khoronzhuk static void cpsw_get_channels(struct net_device *ndev, 2737ce52c744SIvan Khoronzhuk struct ethtool_channels *ch) 2738ce52c744SIvan Khoronzhuk { 2739ce52c744SIvan Khoronzhuk struct cpsw_common *cpsw = ndev_to_cpsw(ndev); 2740ce52c744SIvan Khoronzhuk 27419611d6d6SIvan Khoronzhuk ch->max_rx = cpsw->quirk_irq ? 1 : CPSW_MAX_QUEUES; 27429611d6d6SIvan Khoronzhuk ch->max_tx = cpsw->quirk_irq ? 1 : CPSW_MAX_QUEUES; 2743ce52c744SIvan Khoronzhuk ch->max_combined = 0; 2744ce52c744SIvan Khoronzhuk ch->max_other = 0; 2745ce52c744SIvan Khoronzhuk ch->other_count = 0; 2746ce52c744SIvan Khoronzhuk ch->rx_count = cpsw->rx_ch_num; 2747ce52c744SIvan Khoronzhuk ch->tx_count = cpsw->tx_ch_num; 2748ce52c744SIvan Khoronzhuk ch->combined_count = 0; 2749ce52c744SIvan Khoronzhuk } 2750ce52c744SIvan Khoronzhuk 2751ce52c744SIvan Khoronzhuk static int cpsw_check_ch_settings(struct cpsw_common *cpsw, 2752ce52c744SIvan Khoronzhuk struct ethtool_channels *ch) 2753ce52c744SIvan Khoronzhuk { 27549611d6d6SIvan Khoronzhuk if (cpsw->quirk_irq) { 27559611d6d6SIvan Khoronzhuk dev_err(cpsw->dev, "Maximum one tx/rx queue is allowed"); 27569611d6d6SIvan Khoronzhuk return -EOPNOTSUPP; 27579611d6d6SIvan Khoronzhuk } 27589611d6d6SIvan Khoronzhuk 2759ce52c744SIvan Khoronzhuk if (ch->combined_count) 2760ce52c744SIvan Khoronzhuk return -EINVAL; 2761ce52c744SIvan Khoronzhuk 2762ce52c744SIvan Khoronzhuk /* verify we have at least one channel in each direction */ 2763ce52c744SIvan Khoronzhuk if (!ch->rx_count || !ch->tx_count) 2764ce52c744SIvan Khoronzhuk return -EINVAL; 2765ce52c744SIvan Khoronzhuk 2766ce52c744SIvan Khoronzhuk if (ch->rx_count > cpsw->data.channels || 2767ce52c744SIvan Khoronzhuk ch->tx_count > cpsw->data.channels) 2768ce52c744SIvan Khoronzhuk return -EINVAL; 2769ce52c744SIvan Khoronzhuk 2770ce52c744SIvan Khoronzhuk return 0; 2771ce52c744SIvan Khoronzhuk } 2772ce52c744SIvan Khoronzhuk 2773ce52c744SIvan Khoronzhuk static int cpsw_update_channels_res(struct cpsw_priv *priv, int ch_num, int rx) 2774ce52c744SIvan Khoronzhuk { 2775ce52c744SIvan Khoronzhuk struct cpsw_common *cpsw = priv->cpsw; 2776ce52c744SIvan Khoronzhuk void (*handler)(void *, int, int); 277783fcad0cSIvan Khoronzhuk struct netdev_queue *queue; 27788feb0a19SIvan Khoronzhuk struct cpsw_vector *vec; 277979b3325dSIvan Khoronzhuk int ret, *ch, vch; 2780ce52c744SIvan Khoronzhuk 2781ce52c744SIvan Khoronzhuk if (rx) { 2782ce52c744SIvan Khoronzhuk ch = &cpsw->rx_ch_num; 27838feb0a19SIvan Khoronzhuk vec = cpsw->rxv; 2784ce52c744SIvan Khoronzhuk handler = cpsw_rx_handler; 2785ce52c744SIvan Khoronzhuk } else { 2786ce52c744SIvan Khoronzhuk ch = &cpsw->tx_ch_num; 27878feb0a19SIvan Khoronzhuk vec = cpsw->txv; 2788ce52c744SIvan Khoronzhuk handler = cpsw_tx_handler; 2789ce52c744SIvan Khoronzhuk } 2790ce52c744SIvan Khoronzhuk 2791ce52c744SIvan Khoronzhuk while (*ch < ch_num) { 279279b3325dSIvan Khoronzhuk vch = rx ? *ch : 7 - *ch; 279379b3325dSIvan Khoronzhuk vec[*ch].ch = cpdma_chan_create(cpsw->dma, vch, handler, rx); 279483fcad0cSIvan Khoronzhuk queue = netdev_get_tx_queue(priv->ndev, *ch); 279583fcad0cSIvan Khoronzhuk queue->tx_maxrate = 0; 2796ce52c744SIvan Khoronzhuk 27978feb0a19SIvan Khoronzhuk if (IS_ERR(vec[*ch].ch)) 27988feb0a19SIvan Khoronzhuk return PTR_ERR(vec[*ch].ch); 2799ce52c744SIvan Khoronzhuk 28008feb0a19SIvan Khoronzhuk if (!vec[*ch].ch) 2801ce52c744SIvan Khoronzhuk return -EINVAL; 2802ce52c744SIvan Khoronzhuk 2803ce52c744SIvan Khoronzhuk cpsw_info(priv, ifup, "created new %d %s channel\n", *ch, 2804ce52c744SIvan Khoronzhuk (rx ? "rx" : "tx")); 2805ce52c744SIvan Khoronzhuk (*ch)++; 2806ce52c744SIvan Khoronzhuk } 2807ce52c744SIvan Khoronzhuk 2808ce52c744SIvan Khoronzhuk while (*ch > ch_num) { 2809ce52c744SIvan Khoronzhuk (*ch)--; 2810ce52c744SIvan Khoronzhuk 28118feb0a19SIvan Khoronzhuk ret = cpdma_chan_destroy(vec[*ch].ch); 2812ce52c744SIvan Khoronzhuk if (ret) 2813ce52c744SIvan Khoronzhuk return ret; 2814ce52c744SIvan Khoronzhuk 2815ce52c744SIvan Khoronzhuk cpsw_info(priv, ifup, "destroyed %d %s channel\n", *ch, 2816ce52c744SIvan Khoronzhuk (rx ? "rx" : "tx")); 2817ce52c744SIvan Khoronzhuk } 2818ce52c744SIvan Khoronzhuk 2819ce52c744SIvan Khoronzhuk return 0; 2820ce52c744SIvan Khoronzhuk } 2821ce52c744SIvan Khoronzhuk 2822ce52c744SIvan Khoronzhuk static int cpsw_update_channels(struct cpsw_priv *priv, 2823ce52c744SIvan Khoronzhuk struct ethtool_channels *ch) 2824ce52c744SIvan Khoronzhuk { 2825ce52c744SIvan Khoronzhuk int ret; 2826ce52c744SIvan Khoronzhuk 2827ce52c744SIvan Khoronzhuk ret = cpsw_update_channels_res(priv, ch->rx_count, 1); 2828ce52c744SIvan Khoronzhuk if (ret) 2829ce52c744SIvan Khoronzhuk return ret; 2830ce52c744SIvan Khoronzhuk 2831ce52c744SIvan Khoronzhuk ret = cpsw_update_channels_res(priv, ch->tx_count, 0); 2832ce52c744SIvan Khoronzhuk if (ret) 2833ce52c744SIvan Khoronzhuk return ret; 2834ce52c744SIvan Khoronzhuk 2835ce52c744SIvan Khoronzhuk return 0; 2836ce52c744SIvan Khoronzhuk } 2837ce52c744SIvan Khoronzhuk 2838022d7ad7SIvan Khoronzhuk static void cpsw_suspend_data_pass(struct net_device *ndev) 2839ce52c744SIvan Khoronzhuk { 2840022d7ad7SIvan Khoronzhuk struct cpsw_common *cpsw = ndev_to_cpsw(ndev); 2841ce52c744SIvan Khoronzhuk struct cpsw_slave *slave; 2842022d7ad7SIvan Khoronzhuk int i; 2843ce52c744SIvan Khoronzhuk 2844ce52c744SIvan Khoronzhuk /* Disable NAPI scheduling */ 2845ce52c744SIvan Khoronzhuk cpsw_intr_disable(cpsw); 2846ce52c744SIvan Khoronzhuk 2847ce52c744SIvan Khoronzhuk /* Stop all transmit queues for every network device. 2848ce52c744SIvan Khoronzhuk * Disable re-using rx descriptors with dormant_on. 2849ce52c744SIvan Khoronzhuk */ 2850ce52c744SIvan Khoronzhuk for (i = cpsw->data.slaves, slave = cpsw->slaves; i; i--, slave++) { 2851ce52c744SIvan Khoronzhuk if (!(slave->ndev && netif_running(slave->ndev))) 2852ce52c744SIvan Khoronzhuk continue; 2853ce52c744SIvan Khoronzhuk 2854ce52c744SIvan Khoronzhuk netif_tx_stop_all_queues(slave->ndev); 2855ce52c744SIvan Khoronzhuk netif_dormant_on(slave->ndev); 2856ce52c744SIvan Khoronzhuk } 2857ce52c744SIvan Khoronzhuk 2858ce52c744SIvan Khoronzhuk /* Handle rest of tx packets and stop cpdma channels */ 2859ce52c744SIvan Khoronzhuk cpdma_ctlr_stop(cpsw->dma); 2860022d7ad7SIvan Khoronzhuk } 2861022d7ad7SIvan Khoronzhuk 2862022d7ad7SIvan Khoronzhuk static int cpsw_resume_data_pass(struct net_device *ndev) 2863022d7ad7SIvan Khoronzhuk { 2864022d7ad7SIvan Khoronzhuk struct cpsw_priv *priv = netdev_priv(ndev); 2865022d7ad7SIvan Khoronzhuk struct cpsw_common *cpsw = priv->cpsw; 2866022d7ad7SIvan Khoronzhuk struct cpsw_slave *slave; 2867022d7ad7SIvan Khoronzhuk int i, ret; 2868022d7ad7SIvan Khoronzhuk 2869022d7ad7SIvan Khoronzhuk /* Allow rx packets handling */ 2870022d7ad7SIvan Khoronzhuk for (i = cpsw->data.slaves, slave = cpsw->slaves; i; i--, slave++) 2871022d7ad7SIvan Khoronzhuk if (slave->ndev && netif_running(slave->ndev)) 2872022d7ad7SIvan Khoronzhuk netif_dormant_off(slave->ndev); 2873022d7ad7SIvan Khoronzhuk 2874022d7ad7SIvan Khoronzhuk /* After this receive is started */ 2875d5bc1613SIvan Khoronzhuk if (cpsw->usage_count) { 2876022d7ad7SIvan Khoronzhuk ret = cpsw_fill_rx_channels(priv); 2877022d7ad7SIvan Khoronzhuk if (ret) 2878022d7ad7SIvan Khoronzhuk return ret; 2879022d7ad7SIvan Khoronzhuk 2880022d7ad7SIvan Khoronzhuk cpdma_ctlr_start(cpsw->dma); 2881022d7ad7SIvan Khoronzhuk cpsw_intr_enable(cpsw); 2882022d7ad7SIvan Khoronzhuk } 2883022d7ad7SIvan Khoronzhuk 2884022d7ad7SIvan Khoronzhuk /* Resume transmit for every affected interface */ 2885022d7ad7SIvan Khoronzhuk for (i = cpsw->data.slaves, slave = cpsw->slaves; i; i--, slave++) 2886022d7ad7SIvan Khoronzhuk if (slave->ndev && netif_running(slave->ndev)) 2887022d7ad7SIvan Khoronzhuk netif_tx_start_all_queues(slave->ndev); 2888022d7ad7SIvan Khoronzhuk 2889022d7ad7SIvan Khoronzhuk return 0; 2890022d7ad7SIvan Khoronzhuk } 2891022d7ad7SIvan Khoronzhuk 2892022d7ad7SIvan Khoronzhuk static int cpsw_set_channels(struct net_device *ndev, 2893022d7ad7SIvan Khoronzhuk struct ethtool_channels *chs) 2894022d7ad7SIvan Khoronzhuk { 2895022d7ad7SIvan Khoronzhuk struct cpsw_priv *priv = netdev_priv(ndev); 2896022d7ad7SIvan Khoronzhuk struct cpsw_common *cpsw = priv->cpsw; 2897022d7ad7SIvan Khoronzhuk struct cpsw_slave *slave; 2898022d7ad7SIvan Khoronzhuk int i, ret; 2899022d7ad7SIvan Khoronzhuk 2900022d7ad7SIvan Khoronzhuk ret = cpsw_check_ch_settings(cpsw, chs); 2901022d7ad7SIvan Khoronzhuk if (ret < 0) 2902022d7ad7SIvan Khoronzhuk return ret; 2903022d7ad7SIvan Khoronzhuk 2904022d7ad7SIvan Khoronzhuk cpsw_suspend_data_pass(ndev); 2905ce52c744SIvan Khoronzhuk ret = cpsw_update_channels(priv, chs); 2906ce52c744SIvan Khoronzhuk if (ret) 2907ce52c744SIvan Khoronzhuk goto err; 2908ce52c744SIvan Khoronzhuk 2909ce52c744SIvan Khoronzhuk for (i = cpsw->data.slaves, slave = cpsw->slaves; i; i--, slave++) { 2910ce52c744SIvan Khoronzhuk if (!(slave->ndev && netif_running(slave->ndev))) 2911ce52c744SIvan Khoronzhuk continue; 2912ce52c744SIvan Khoronzhuk 2913ce52c744SIvan Khoronzhuk /* Inform stack about new count of queues */ 2914ce52c744SIvan Khoronzhuk ret = netif_set_real_num_tx_queues(slave->ndev, 2915ce52c744SIvan Khoronzhuk cpsw->tx_ch_num); 2916ce52c744SIvan Khoronzhuk if (ret) { 2917ce52c744SIvan Khoronzhuk dev_err(priv->dev, "cannot set real number of tx queues\n"); 2918ce52c744SIvan Khoronzhuk goto err; 2919ce52c744SIvan Khoronzhuk } 2920ce52c744SIvan Khoronzhuk 2921ce52c744SIvan Khoronzhuk ret = netif_set_real_num_rx_queues(slave->ndev, 2922ce52c744SIvan Khoronzhuk cpsw->rx_ch_num); 2923ce52c744SIvan Khoronzhuk if (ret) { 2924ce52c744SIvan Khoronzhuk dev_err(priv->dev, "cannot set real number of rx queues\n"); 2925ce52c744SIvan Khoronzhuk goto err; 2926ce52c744SIvan Khoronzhuk } 2927ce52c744SIvan Khoronzhuk } 2928ce52c744SIvan Khoronzhuk 2929d5bc1613SIvan Khoronzhuk if (cpsw->usage_count) 293032b78d85SIvan Khoronzhuk cpsw_split_res(ndev); 29318feb0a19SIvan Khoronzhuk 2932022d7ad7SIvan Khoronzhuk ret = cpsw_resume_data_pass(ndev); 2933022d7ad7SIvan Khoronzhuk if (!ret) 2934ce52c744SIvan Khoronzhuk return 0; 2935ce52c744SIvan Khoronzhuk err: 2936ce52c744SIvan Khoronzhuk dev_err(priv->dev, "cannot update channels number, closing device\n"); 2937ce52c744SIvan Khoronzhuk dev_close(ndev); 2938ce52c744SIvan Khoronzhuk return ret; 2939ce52c744SIvan Khoronzhuk } 2940ce52c744SIvan Khoronzhuk 2941a0909949SYegor Yefremov static int cpsw_get_eee(struct net_device *ndev, struct ethtool_eee *edata) 2942a0909949SYegor Yefremov { 2943a0909949SYegor Yefremov struct cpsw_priv *priv = netdev_priv(ndev); 2944a0909949SYegor Yefremov struct cpsw_common *cpsw = priv->cpsw; 2945a0909949SYegor Yefremov int slave_no = cpsw_slave_index(cpsw, priv); 2946a0909949SYegor Yefremov 2947a0909949SYegor Yefremov if (cpsw->slaves[slave_no].phy) 2948a0909949SYegor Yefremov return phy_ethtool_get_eee(cpsw->slaves[slave_no].phy, edata); 2949a0909949SYegor Yefremov else 2950a0909949SYegor Yefremov return -EOPNOTSUPP; 2951a0909949SYegor Yefremov } 2952a0909949SYegor Yefremov 2953a0909949SYegor Yefremov static int cpsw_set_eee(struct net_device *ndev, struct ethtool_eee *edata) 2954a0909949SYegor Yefremov { 2955a0909949SYegor Yefremov struct cpsw_priv *priv = netdev_priv(ndev); 2956a0909949SYegor Yefremov struct cpsw_common *cpsw = priv->cpsw; 2957a0909949SYegor Yefremov int slave_no = cpsw_slave_index(cpsw, priv); 2958a0909949SYegor Yefremov 2959a0909949SYegor Yefremov if (cpsw->slaves[slave_no].phy) 2960a0909949SYegor Yefremov return phy_ethtool_set_eee(cpsw->slaves[slave_no].phy, edata); 2961a0909949SYegor Yefremov else 2962a0909949SYegor Yefremov return -EOPNOTSUPP; 2963a0909949SYegor Yefremov } 2964a0909949SYegor Yefremov 29656bb10c2bSYegor Yefremov static int cpsw_nway_reset(struct net_device *ndev) 29666bb10c2bSYegor Yefremov { 29676bb10c2bSYegor Yefremov struct cpsw_priv *priv = netdev_priv(ndev); 29686bb10c2bSYegor Yefremov struct cpsw_common *cpsw = priv->cpsw; 29696bb10c2bSYegor Yefremov int slave_no = cpsw_slave_index(cpsw, priv); 29706bb10c2bSYegor Yefremov 29716bb10c2bSYegor Yefremov if (cpsw->slaves[slave_no].phy) 29726bb10c2bSYegor Yefremov return genphy_restart_aneg(cpsw->slaves[slave_no].phy); 29736bb10c2bSYegor Yefremov else 29746bb10c2bSYegor Yefremov return -EOPNOTSUPP; 29756bb10c2bSYegor Yefremov } 29766bb10c2bSYegor Yefremov 2977be034fc1SGrygorii Strashko static void cpsw_get_ringparam(struct net_device *ndev, 2978be034fc1SGrygorii Strashko struct ethtool_ringparam *ering) 2979be034fc1SGrygorii Strashko { 2980be034fc1SGrygorii Strashko struct cpsw_priv *priv = netdev_priv(ndev); 2981be034fc1SGrygorii Strashko struct cpsw_common *cpsw = priv->cpsw; 2982be034fc1SGrygorii Strashko 2983be034fc1SGrygorii Strashko /* not supported */ 2984be034fc1SGrygorii Strashko ering->tx_max_pending = 0; 2985be034fc1SGrygorii Strashko ering->tx_pending = cpdma_get_num_tx_descs(cpsw->dma); 2986f89d21b9SIvan Khoronzhuk ering->rx_max_pending = descs_pool_size - CPSW_MAX_QUEUES; 2987be034fc1SGrygorii Strashko ering->rx_pending = cpdma_get_num_rx_descs(cpsw->dma); 2988be034fc1SGrygorii Strashko } 2989be034fc1SGrygorii Strashko 2990be034fc1SGrygorii Strashko static int cpsw_set_ringparam(struct net_device *ndev, 2991be034fc1SGrygorii Strashko struct ethtool_ringparam *ering) 2992be034fc1SGrygorii Strashko { 2993be034fc1SGrygorii Strashko struct cpsw_priv *priv = netdev_priv(ndev); 2994be034fc1SGrygorii Strashko struct cpsw_common *cpsw = priv->cpsw; 2995022d7ad7SIvan Khoronzhuk int ret; 2996be034fc1SGrygorii Strashko 2997be034fc1SGrygorii Strashko /* ignore ering->tx_pending - only rx_pending adjustment is supported */ 2998be034fc1SGrygorii Strashko 2999be034fc1SGrygorii Strashko if (ering->rx_mini_pending || ering->rx_jumbo_pending || 3000f89d21b9SIvan Khoronzhuk ering->rx_pending < CPSW_MAX_QUEUES || 3001f89d21b9SIvan Khoronzhuk ering->rx_pending > (descs_pool_size - CPSW_MAX_QUEUES)) 3002be034fc1SGrygorii Strashko return -EINVAL; 3003be034fc1SGrygorii Strashko 3004be034fc1SGrygorii Strashko if (ering->rx_pending == cpdma_get_num_rx_descs(cpsw->dma)) 3005be034fc1SGrygorii Strashko return 0; 3006be034fc1SGrygorii Strashko 3007022d7ad7SIvan Khoronzhuk cpsw_suspend_data_pass(ndev); 3008be034fc1SGrygorii Strashko 3009be034fc1SGrygorii Strashko cpdma_set_num_rx_descs(cpsw->dma, ering->rx_pending); 3010be034fc1SGrygorii Strashko 3011d5bc1613SIvan Khoronzhuk if (cpsw->usage_count) 3012be034fc1SGrygorii Strashko cpdma_chan_split_pool(cpsw->dma); 3013be034fc1SGrygorii Strashko 3014022d7ad7SIvan Khoronzhuk ret = cpsw_resume_data_pass(ndev); 3015022d7ad7SIvan Khoronzhuk if (!ret) 3016be034fc1SGrygorii Strashko return 0; 3017022d7ad7SIvan Khoronzhuk 3018022d7ad7SIvan Khoronzhuk dev_err(&ndev->dev, "cannot set ring params, closing device\n"); 3019be034fc1SGrygorii Strashko dev_close(ndev); 3020be034fc1SGrygorii Strashko return ret; 3021be034fc1SGrygorii Strashko } 3022be034fc1SGrygorii Strashko 3023df828598SMugunthan V N static const struct ethtool_ops cpsw_ethtool_ops = { 3024df828598SMugunthan V N .get_drvinfo = cpsw_get_drvinfo, 3025df828598SMugunthan V N .get_msglevel = cpsw_get_msglevel, 3026df828598SMugunthan V N .set_msglevel = cpsw_set_msglevel, 3027df828598SMugunthan V N .get_link = ethtool_op_get_link, 30282e5b38abSRichard Cochran .get_ts_info = cpsw_get_ts_info, 3029ff5b8ef2SMugunthan V N .get_coalesce = cpsw_get_coalesce, 3030ff5b8ef2SMugunthan V N .set_coalesce = cpsw_set_coalesce, 3031d9718546SMugunthan V N .get_sset_count = cpsw_get_sset_count, 3032d9718546SMugunthan V N .get_strings = cpsw_get_strings, 3033d9718546SMugunthan V N .get_ethtool_stats = cpsw_get_ethtool_stats, 30341923d6e4SMugunthan V N .get_pauseparam = cpsw_get_pauseparam, 30351923d6e4SMugunthan V N .set_pauseparam = cpsw_set_pauseparam, 3036d8a64420SMatus Ujhelyi .get_wol = cpsw_get_wol, 3037d8a64420SMatus Ujhelyi .set_wol = cpsw_set_wol, 303852c4f0ecSMugunthan V N .get_regs_len = cpsw_get_regs_len, 303952c4f0ecSMugunthan V N .get_regs = cpsw_get_regs, 30407898b1daSGrygorii Strashko .begin = cpsw_ethtool_op_begin, 30417898b1daSGrygorii Strashko .complete = cpsw_ethtool_op_complete, 3042ce52c744SIvan Khoronzhuk .get_channels = cpsw_get_channels, 3043ce52c744SIvan Khoronzhuk .set_channels = cpsw_set_channels, 30442479876dSPhilippe Reynes .get_link_ksettings = cpsw_get_link_ksettings, 30452479876dSPhilippe Reynes .set_link_ksettings = cpsw_set_link_ksettings, 3046a0909949SYegor Yefremov .get_eee = cpsw_get_eee, 3047a0909949SYegor Yefremov .set_eee = cpsw_set_eee, 30486bb10c2bSYegor Yefremov .nway_reset = cpsw_nway_reset, 3049be034fc1SGrygorii Strashko .get_ringparam = cpsw_get_ringparam, 3050be034fc1SGrygorii Strashko .set_ringparam = cpsw_set_ringparam, 3051df828598SMugunthan V N }; 3052df828598SMugunthan V N 3053606f3993SIvan Khoronzhuk static void cpsw_slave_init(struct cpsw_slave *slave, struct cpsw_common *cpsw, 3054549985eeSRichard Cochran u32 slave_reg_ofs, u32 sliver_reg_ofs) 3055df828598SMugunthan V N { 30565d8d0d4dSIvan Khoronzhuk void __iomem *regs = cpsw->regs; 3057df828598SMugunthan V N int slave_num = slave->slave_num; 3058606f3993SIvan Khoronzhuk struct cpsw_slave_data *data = cpsw->data.slave_data + slave_num; 3059df828598SMugunthan V N 3060df828598SMugunthan V N slave->data = data; 3061549985eeSRichard Cochran slave->regs = regs + slave_reg_ofs; 3062549985eeSRichard Cochran slave->sliver = regs + sliver_reg_ofs; 3063d9ba8f9eSMugunthan V N slave->port_vlan = data->dual_emac_res_vlan; 3064df828598SMugunthan V N } 3065df828598SMugunthan V N 3066552165bcSDavid Rivshin static int cpsw_probe_dt(struct cpsw_platform_data *data, 30672eb32b0aSMugunthan V N struct platform_device *pdev) 30682eb32b0aSMugunthan V N { 30692eb32b0aSMugunthan V N struct device_node *node = pdev->dev.of_node; 30702eb32b0aSMugunthan V N struct device_node *slave_node; 30712eb32b0aSMugunthan V N int i = 0, ret; 30722eb32b0aSMugunthan V N u32 prop; 30732eb32b0aSMugunthan V N 30742eb32b0aSMugunthan V N if (!node) 30752eb32b0aSMugunthan V N return -EINVAL; 30762eb32b0aSMugunthan V N 30772eb32b0aSMugunthan V N if (of_property_read_u32(node, "slaves", &prop)) { 307888c99ff6SGeorge Cherian dev_err(&pdev->dev, "Missing slaves property in the DT.\n"); 30792eb32b0aSMugunthan V N return -EINVAL; 30802eb32b0aSMugunthan V N } 30812eb32b0aSMugunthan V N data->slaves = prop; 30822eb32b0aSMugunthan V N 3083e86ac13bSMugunthan V N if (of_property_read_u32(node, "active_slave", &prop)) { 308488c99ff6SGeorge Cherian dev_err(&pdev->dev, "Missing active_slave property in the DT.\n"); 3085aa1a15e2SDaniel Mack return -EINVAL; 308678ca0b28SRichard Cochran } 3087e86ac13bSMugunthan V N data->active_slave = prop; 308878ca0b28SRichard Cochran 3089a86854d0SKees Cook data->slave_data = devm_kcalloc(&pdev->dev, 3090a86854d0SKees Cook data->slaves, 3091a86854d0SKees Cook sizeof(struct cpsw_slave_data), 3092b2adaca9SJoe Perches GFP_KERNEL); 3093b2adaca9SJoe Perches if (!data->slave_data) 3094aa1a15e2SDaniel Mack return -ENOMEM; 30952eb32b0aSMugunthan V N 30962eb32b0aSMugunthan V N if (of_property_read_u32(node, "cpdma_channels", &prop)) { 309788c99ff6SGeorge Cherian dev_err(&pdev->dev, "Missing cpdma_channels property in the DT.\n"); 3098aa1a15e2SDaniel Mack return -EINVAL; 30992eb32b0aSMugunthan V N } 31002eb32b0aSMugunthan V N data->channels = prop; 31012eb32b0aSMugunthan V N 31022eb32b0aSMugunthan V N if (of_property_read_u32(node, "ale_entries", &prop)) { 310388c99ff6SGeorge Cherian dev_err(&pdev->dev, "Missing ale_entries property in the DT.\n"); 3104aa1a15e2SDaniel Mack return -EINVAL; 31052eb32b0aSMugunthan V N } 31062eb32b0aSMugunthan V N data->ale_entries = prop; 31072eb32b0aSMugunthan V N 31082eb32b0aSMugunthan V N if (of_property_read_u32(node, "bd_ram_size", &prop)) { 310988c99ff6SGeorge Cherian dev_err(&pdev->dev, "Missing bd_ram_size property in the DT.\n"); 3110aa1a15e2SDaniel Mack return -EINVAL; 31112eb32b0aSMugunthan V N } 31122eb32b0aSMugunthan V N data->bd_ram_size = prop; 31132eb32b0aSMugunthan V N 31142eb32b0aSMugunthan V N if (of_property_read_u32(node, "mac_control", &prop)) { 311588c99ff6SGeorge Cherian dev_err(&pdev->dev, "Missing mac_control property in the DT.\n"); 3116aa1a15e2SDaniel Mack return -EINVAL; 31172eb32b0aSMugunthan V N } 31182eb32b0aSMugunthan V N data->mac_control = prop; 31192eb32b0aSMugunthan V N 3120281abd96SMarkus Pargmann if (of_property_read_bool(node, "dual_emac")) 3121281abd96SMarkus Pargmann data->dual_emac = 1; 3122d9ba8f9eSMugunthan V N 31231fb19aa7SVaibhav Hiremath /* 31241fb19aa7SVaibhav Hiremath * Populate all the child nodes here... 31251fb19aa7SVaibhav Hiremath */ 31261fb19aa7SVaibhav Hiremath ret = of_platform_populate(node, NULL, NULL, &pdev->dev); 31271fb19aa7SVaibhav Hiremath /* We do not want to force this, as in some cases may not have child */ 31281fb19aa7SVaibhav Hiremath if (ret) 312988c99ff6SGeorge Cherian dev_warn(&pdev->dev, "Doesn't have any child node\n"); 31301fb19aa7SVaibhav Hiremath 31318658aaf2SBen Hutchings for_each_available_child_of_node(node, slave_node) { 3132549985eeSRichard Cochran struct cpsw_slave_data *slave_data = data->slave_data + i; 3133549985eeSRichard Cochran const void *mac_addr = NULL; 3134549985eeSRichard Cochran int lenp; 3135549985eeSRichard Cochran const __be32 *parp; 3136549985eeSRichard Cochran 3137f468b10eSMarkus Pargmann /* This is no slave child node, continue */ 3138f468b10eSMarkus Pargmann if (strcmp(slave_node->name, "slave")) 3139f468b10eSMarkus Pargmann continue; 3140f468b10eSMarkus Pargmann 3141552165bcSDavid Rivshin slave_data->phy_node = of_parse_phandle(slave_node, 3142552165bcSDavid Rivshin "phy-handle", 0); 3143f1eea5c1SDavid Rivshin parp = of_get_property(slave_node, "phy_id", &lenp); 3144ae092b5bSDavid Rivshin if (slave_data->phy_node) { 3145ae092b5bSDavid Rivshin dev_dbg(&pdev->dev, 3146f7ce9103SRob Herring "slave[%d] using phy-handle=\"%pOF\"\n", 3147f7ce9103SRob Herring i, slave_data->phy_node); 3148ae092b5bSDavid Rivshin } else if (of_phy_is_fixed_link(slave_node)) { 3149dfc0a6d3SDavid Rivshin /* In the case of a fixed PHY, the DT node associated 3150dfc0a6d3SDavid Rivshin * to the PHY is the Ethernet MAC DT node. 3151dfc0a6d3SDavid Rivshin */ 31521f71e8c9SMarkus Brunner ret = of_phy_register_fixed_link(slave_node); 315323a09873SJohan Hovold if (ret) { 315423a09873SJohan Hovold if (ret != -EPROBE_DEFER) 315523a09873SJohan Hovold dev_err(&pdev->dev, "failed to register fixed-link phy: %d\n", ret); 31561f71e8c9SMarkus Brunner return ret; 315723a09873SJohan Hovold } 315806cd6d6eSDavid Rivshin slave_data->phy_node = of_node_get(slave_node); 3159f1eea5c1SDavid Rivshin } else if (parp) { 3160f1eea5c1SDavid Rivshin u32 phyid; 3161f1eea5c1SDavid Rivshin struct device_node *mdio_node; 3162f1eea5c1SDavid Rivshin struct platform_device *mdio; 3163f1eea5c1SDavid Rivshin 3164f1eea5c1SDavid Rivshin if (lenp != (sizeof(__be32) * 2)) { 3165f1eea5c1SDavid Rivshin dev_err(&pdev->dev, "Invalid slave[%d] phy_id property\n", i); 316647276fccSMugunthan V N goto no_phy_slave; 3167549985eeSRichard Cochran } 3168549985eeSRichard Cochran mdio_node = of_find_node_by_phandle(be32_to_cpup(parp)); 3169549985eeSRichard Cochran phyid = be32_to_cpup(parp+1); 3170549985eeSRichard Cochran mdio = of_find_device_by_node(mdio_node); 317160e71ab5SJohan Hovold of_node_put(mdio_node); 31726954cc1fSJohan Hovold if (!mdio) { 317356fdb2e0SMarkus Pargmann dev_err(&pdev->dev, "Missing mdio platform device\n"); 31746954cc1fSJohan Hovold return -EINVAL; 31756954cc1fSJohan Hovold } 3176549985eeSRichard Cochran snprintf(slave_data->phy_id, sizeof(slave_data->phy_id), 3177549985eeSRichard Cochran PHY_ID_FMT, mdio->name, phyid); 317886e1d5adSJohan Hovold put_device(&mdio->dev); 3179f1eea5c1SDavid Rivshin } else { 3180ae092b5bSDavid Rivshin dev_err(&pdev->dev, 3181ae092b5bSDavid Rivshin "No slave[%d] phy_id, phy-handle, or fixed-link property\n", 3182ae092b5bSDavid Rivshin i); 3183f1eea5c1SDavid Rivshin goto no_phy_slave; 3184f1eea5c1SDavid Rivshin } 318547276fccSMugunthan V N slave_data->phy_if = of_get_phy_mode(slave_node); 318647276fccSMugunthan V N if (slave_data->phy_if < 0) { 318747276fccSMugunthan V N dev_err(&pdev->dev, "Missing or malformed slave[%d] phy-mode property\n", 318847276fccSMugunthan V N i); 318947276fccSMugunthan V N return slave_data->phy_if; 319047276fccSMugunthan V N } 319147276fccSMugunthan V N 319247276fccSMugunthan V N no_phy_slave: 3193549985eeSRichard Cochran mac_addr = of_get_mac_address(slave_node); 31940ba517b1SMarkus Pargmann if (mac_addr) { 3195549985eeSRichard Cochran memcpy(slave_data->mac_addr, mac_addr, ETH_ALEN); 31960ba517b1SMarkus Pargmann } else { 3197b6745f6eSMugunthan V N ret = ti_cm_get_macid(&pdev->dev, i, 31980ba517b1SMarkus Pargmann slave_data->mac_addr); 31990ba517b1SMarkus Pargmann if (ret) 32000ba517b1SMarkus Pargmann return ret; 32010ba517b1SMarkus Pargmann } 3202d9ba8f9eSMugunthan V N if (data->dual_emac) { 320391c4166cSMugunthan V N if (of_property_read_u32(slave_node, "dual_emac_res_vlan", 3204d9ba8f9eSMugunthan V N &prop)) { 320588c99ff6SGeorge Cherian dev_err(&pdev->dev, "Missing dual_emac_res_vlan in DT.\n"); 3206d9ba8f9eSMugunthan V N slave_data->dual_emac_res_vlan = i+1; 320788c99ff6SGeorge Cherian dev_err(&pdev->dev, "Using %d as Reserved VLAN for %d slave\n", 3208d9ba8f9eSMugunthan V N slave_data->dual_emac_res_vlan, i); 3209d9ba8f9eSMugunthan V N } else { 3210d9ba8f9eSMugunthan V N slave_data->dual_emac_res_vlan = prop; 3211d9ba8f9eSMugunthan V N } 3212d9ba8f9eSMugunthan V N } 3213d9ba8f9eSMugunthan V N 3214549985eeSRichard Cochran i++; 32153a27bfacSMugunthan V N if (i == data->slaves) 32163a27bfacSMugunthan V N break; 3217549985eeSRichard Cochran } 3218549985eeSRichard Cochran 32192eb32b0aSMugunthan V N return 0; 32202eb32b0aSMugunthan V N } 32212eb32b0aSMugunthan V N 3222a4e32b0dSJohan Hovold static void cpsw_remove_dt(struct platform_device *pdev) 3223a4e32b0dSJohan Hovold { 32248cbcc466SJohan Hovold struct net_device *ndev = platform_get_drvdata(pdev); 32258cbcc466SJohan Hovold struct cpsw_common *cpsw = ndev_to_cpsw(ndev); 32268cbcc466SJohan Hovold struct cpsw_platform_data *data = &cpsw->data; 32278cbcc466SJohan Hovold struct device_node *node = pdev->dev.of_node; 32288cbcc466SJohan Hovold struct device_node *slave_node; 32298cbcc466SJohan Hovold int i = 0; 32308cbcc466SJohan Hovold 32318cbcc466SJohan Hovold for_each_available_child_of_node(node, slave_node) { 32328cbcc466SJohan Hovold struct cpsw_slave_data *slave_data = &data->slave_data[i]; 32338cbcc466SJohan Hovold 32348cbcc466SJohan Hovold if (strcmp(slave_node->name, "slave")) 32358cbcc466SJohan Hovold continue; 32368cbcc466SJohan Hovold 32373f65047cSJohan Hovold if (of_phy_is_fixed_link(slave_node)) 32383f65047cSJohan Hovold of_phy_deregister_fixed_link(slave_node); 32398cbcc466SJohan Hovold 32408cbcc466SJohan Hovold of_node_put(slave_data->phy_node); 32418cbcc466SJohan Hovold 32428cbcc466SJohan Hovold i++; 32438cbcc466SJohan Hovold if (i == data->slaves) 32448cbcc466SJohan Hovold break; 32458cbcc466SJohan Hovold } 32468cbcc466SJohan Hovold 3247a4e32b0dSJohan Hovold of_platform_depopulate(&pdev->dev); 3248a4e32b0dSJohan Hovold } 3249a4e32b0dSJohan Hovold 325056e31bd8SIvan Khoronzhuk static int cpsw_probe_dual_emac(struct cpsw_priv *priv) 3251d9ba8f9eSMugunthan V N { 3252606f3993SIvan Khoronzhuk struct cpsw_common *cpsw = priv->cpsw; 3253606f3993SIvan Khoronzhuk struct cpsw_platform_data *data = &cpsw->data; 3254d9ba8f9eSMugunthan V N struct net_device *ndev; 3255d9ba8f9eSMugunthan V N struct cpsw_priv *priv_sl2; 3256e38b5a3dSIvan Khoronzhuk int ret = 0; 3257d9ba8f9eSMugunthan V N 3258e05107e6SIvan Khoronzhuk ndev = alloc_etherdev_mq(sizeof(struct cpsw_priv), CPSW_MAX_QUEUES); 3259d9ba8f9eSMugunthan V N if (!ndev) { 326056e31bd8SIvan Khoronzhuk dev_err(cpsw->dev, "cpsw: error allocating net_device\n"); 3261d9ba8f9eSMugunthan V N return -ENOMEM; 3262d9ba8f9eSMugunthan V N } 3263d9ba8f9eSMugunthan V N 3264d9ba8f9eSMugunthan V N priv_sl2 = netdev_priv(ndev); 3265606f3993SIvan Khoronzhuk priv_sl2->cpsw = cpsw; 3266d9ba8f9eSMugunthan V N priv_sl2->ndev = ndev; 3267d9ba8f9eSMugunthan V N priv_sl2->dev = &ndev->dev; 3268d9ba8f9eSMugunthan V N priv_sl2->msg_enable = netif_msg_init(debug_level, CPSW_DEBUG); 3269d9ba8f9eSMugunthan V N 3270d9ba8f9eSMugunthan V N if (is_valid_ether_addr(data->slave_data[1].mac_addr)) { 3271d9ba8f9eSMugunthan V N memcpy(priv_sl2->mac_addr, data->slave_data[1].mac_addr, 3272d9ba8f9eSMugunthan V N ETH_ALEN); 327356e31bd8SIvan Khoronzhuk dev_info(cpsw->dev, "cpsw: Detected MACID = %pM\n", 327456e31bd8SIvan Khoronzhuk priv_sl2->mac_addr); 3275d9ba8f9eSMugunthan V N } else { 32766c1f0a1fSJoe Perches eth_random_addr(priv_sl2->mac_addr); 327756e31bd8SIvan Khoronzhuk dev_info(cpsw->dev, "cpsw: Random MACID = %pM\n", 327856e31bd8SIvan Khoronzhuk priv_sl2->mac_addr); 3279d9ba8f9eSMugunthan V N } 3280d9ba8f9eSMugunthan V N memcpy(ndev->dev_addr, priv_sl2->mac_addr, ETH_ALEN); 3281d9ba8f9eSMugunthan V N 3282d9ba8f9eSMugunthan V N priv_sl2->emac_port = 1; 3283606f3993SIvan Khoronzhuk cpsw->slaves[1].ndev = ndev; 3284193736c8SIvan Khoronzhuk ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER | NETIF_F_HW_VLAN_CTAG_RX; 3285d9ba8f9eSMugunthan V N 3286d9ba8f9eSMugunthan V N ndev->netdev_ops = &cpsw_netdev_ops; 32877ad24ea4SWilfried Klaebe ndev->ethtool_ops = &cpsw_ethtool_ops; 3288d9ba8f9eSMugunthan V N 3289d9ba8f9eSMugunthan V N /* register the network device */ 329056e31bd8SIvan Khoronzhuk SET_NETDEV_DEV(ndev, cpsw->dev); 3291d9ba8f9eSMugunthan V N ret = register_netdev(ndev); 3292d9ba8f9eSMugunthan V N if (ret) { 329356e31bd8SIvan Khoronzhuk dev_err(cpsw->dev, "cpsw: error registering net device\n"); 3294d9ba8f9eSMugunthan V N free_netdev(ndev); 3295d9ba8f9eSMugunthan V N ret = -ENODEV; 3296d9ba8f9eSMugunthan V N } 3297d9ba8f9eSMugunthan V N 3298d9ba8f9eSMugunthan V N return ret; 3299d9ba8f9eSMugunthan V N } 3300d9ba8f9eSMugunthan V N 33017da11600SMugunthan V N static const struct of_device_id cpsw_of_mtable[] = { 33029611d6d6SIvan Khoronzhuk { .compatible = "ti,cpsw"}, 33039611d6d6SIvan Khoronzhuk { .compatible = "ti,am335x-cpsw"}, 33049611d6d6SIvan Khoronzhuk { .compatible = "ti,am4372-cpsw"}, 33059611d6d6SIvan Khoronzhuk { .compatible = "ti,dra7-cpsw"}, 33067da11600SMugunthan V N { /* sentinel */ }, 33077da11600SMugunthan V N }; 33087da11600SMugunthan V N MODULE_DEVICE_TABLE(of, cpsw_of_mtable); 33097da11600SMugunthan V N 33109611d6d6SIvan Khoronzhuk static const struct soc_device_attribute cpsw_soc_devices[] = { 33119611d6d6SIvan Khoronzhuk { .family = "AM33xx", .revision = "ES1.0"}, 33129611d6d6SIvan Khoronzhuk { /* sentinel */ } 33139611d6d6SIvan Khoronzhuk }; 33149611d6d6SIvan Khoronzhuk 3315663e12e6SBill Pemberton static int cpsw_probe(struct platform_device *pdev) 3316df828598SMugunthan V N { 3317ef4183a1SIvan Khoronzhuk struct clk *clk; 3318d1bd9acfSSebastian Siewior struct cpsw_platform_data *data; 3319df828598SMugunthan V N struct net_device *ndev; 3320df828598SMugunthan V N struct cpsw_priv *priv; 3321df828598SMugunthan V N struct cpdma_params dma_params; 3322df828598SMugunthan V N struct cpsw_ale_params ale_params; 3323aa1a15e2SDaniel Mack void __iomem *ss_regs; 33248a2c9a5aSGrygorii Strashko void __iomem *cpts_regs; 3325aa1a15e2SDaniel Mack struct resource *res, *ss_res; 33261d147ccbSMugunthan V N struct gpio_descs *mode; 3327549985eeSRichard Cochran u32 slave_offset, sliver_offset, slave_size; 33289611d6d6SIvan Khoronzhuk const struct soc_device_attribute *soc; 3329649a1688SIvan Khoronzhuk struct cpsw_common *cpsw; 333079b3325dSIvan Khoronzhuk int ret = 0, i, ch; 33315087b915SFelipe Balbi int irq; 3332df828598SMugunthan V N 3333649a1688SIvan Khoronzhuk cpsw = devm_kzalloc(&pdev->dev, sizeof(struct cpsw_common), GFP_KERNEL); 33343420ea88SJohan Hovold if (!cpsw) 33353420ea88SJohan Hovold return -ENOMEM; 33363420ea88SJohan Hovold 333756e31bd8SIvan Khoronzhuk cpsw->dev = &pdev->dev; 3338649a1688SIvan Khoronzhuk 3339e05107e6SIvan Khoronzhuk ndev = alloc_etherdev_mq(sizeof(struct cpsw_priv), CPSW_MAX_QUEUES); 3340df828598SMugunthan V N if (!ndev) { 334188c99ff6SGeorge Cherian dev_err(&pdev->dev, "error allocating net_device\n"); 3342df828598SMugunthan V N return -ENOMEM; 3343df828598SMugunthan V N } 3344df828598SMugunthan V N 3345df828598SMugunthan V N platform_set_drvdata(pdev, ndev); 3346df828598SMugunthan V N priv = netdev_priv(ndev); 3347649a1688SIvan Khoronzhuk priv->cpsw = cpsw; 3348df828598SMugunthan V N priv->ndev = ndev; 3349df828598SMugunthan V N priv->dev = &ndev->dev; 3350df828598SMugunthan V N priv->msg_enable = netif_msg_init(debug_level, CPSW_DEBUG); 33512a05a622SIvan Khoronzhuk cpsw->rx_packet_max = max(rx_packet_max, 128); 3352df828598SMugunthan V N 33531d147ccbSMugunthan V N mode = devm_gpiod_get_array_optional(&pdev->dev, "mode", GPIOD_OUT_LOW); 33541d147ccbSMugunthan V N if (IS_ERR(mode)) { 33551d147ccbSMugunthan V N ret = PTR_ERR(mode); 33561d147ccbSMugunthan V N dev_err(&pdev->dev, "gpio request failed, ret %d\n", ret); 33571d147ccbSMugunthan V N goto clean_ndev_ret; 33581d147ccbSMugunthan V N } 33591d147ccbSMugunthan V N 33601fb19aa7SVaibhav Hiremath /* 33611fb19aa7SVaibhav Hiremath * This may be required here for child devices. 33621fb19aa7SVaibhav Hiremath */ 33631fb19aa7SVaibhav Hiremath pm_runtime_enable(&pdev->dev); 33641fb19aa7SVaibhav Hiremath 3365739683b4SMugunthan V N /* Select default pin state */ 3366739683b4SMugunthan V N pinctrl_pm_select_default_state(&pdev->dev); 3367739683b4SMugunthan V N 3368a4e32b0dSJohan Hovold /* Need to enable clocks with runtime PM api to access module 3369a4e32b0dSJohan Hovold * registers 3370a4e32b0dSJohan Hovold */ 3371a4e32b0dSJohan Hovold ret = pm_runtime_get_sync(&pdev->dev); 3372a4e32b0dSJohan Hovold if (ret < 0) { 3373a4e32b0dSJohan Hovold pm_runtime_put_noidle(&pdev->dev); 3374aa1a15e2SDaniel Mack goto clean_runtime_disable_ret; 33752eb32b0aSMugunthan V N } 3376a4e32b0dSJohan Hovold 337723a09873SJohan Hovold ret = cpsw_probe_dt(&cpsw->data, pdev); 337823a09873SJohan Hovold if (ret) 3379a4e32b0dSJohan Hovold goto clean_dt_ret; 338023a09873SJohan Hovold 3381606f3993SIvan Khoronzhuk data = &cpsw->data; 3382e05107e6SIvan Khoronzhuk cpsw->rx_ch_num = 1; 3383e05107e6SIvan Khoronzhuk cpsw->tx_ch_num = 1; 33842eb32b0aSMugunthan V N 3385df828598SMugunthan V N if (is_valid_ether_addr(data->slave_data[0].mac_addr)) { 3386df828598SMugunthan V N memcpy(priv->mac_addr, data->slave_data[0].mac_addr, ETH_ALEN); 338788c99ff6SGeorge Cherian dev_info(&pdev->dev, "Detected MACID = %pM\n", priv->mac_addr); 3388df828598SMugunthan V N } else { 33897efd26d0SJoe Perches eth_random_addr(priv->mac_addr); 339088c99ff6SGeorge Cherian dev_info(&pdev->dev, "Random MACID = %pM\n", priv->mac_addr); 3391df828598SMugunthan V N } 3392df828598SMugunthan V N 3393df828598SMugunthan V N memcpy(ndev->dev_addr, priv->mac_addr, ETH_ALEN); 3394df828598SMugunthan V N 3395a86854d0SKees Cook cpsw->slaves = devm_kcalloc(&pdev->dev, 3396a86854d0SKees Cook data->slaves, sizeof(struct cpsw_slave), 3397df828598SMugunthan V N GFP_KERNEL); 3398606f3993SIvan Khoronzhuk if (!cpsw->slaves) { 3399aa1a15e2SDaniel Mack ret = -ENOMEM; 3400a4e32b0dSJohan Hovold goto clean_dt_ret; 3401df828598SMugunthan V N } 3402df828598SMugunthan V N for (i = 0; i < data->slaves; i++) 3403606f3993SIvan Khoronzhuk cpsw->slaves[i].slave_num = i; 3404df828598SMugunthan V N 3405606f3993SIvan Khoronzhuk cpsw->slaves[0].ndev = ndev; 3406d9ba8f9eSMugunthan V N priv->emac_port = 0; 3407d9ba8f9eSMugunthan V N 3408ef4183a1SIvan Khoronzhuk clk = devm_clk_get(&pdev->dev, "fck"); 3409ef4183a1SIvan Khoronzhuk if (IS_ERR(clk)) { 3410aa1a15e2SDaniel Mack dev_err(priv->dev, "fck is not found\n"); 3411f150bd7fSMugunthan V N ret = -ENODEV; 3412a4e32b0dSJohan Hovold goto clean_dt_ret; 3413df828598SMugunthan V N } 34142a05a622SIvan Khoronzhuk cpsw->bus_freq_mhz = clk_get_rate(clk) / 1000000; 3415df828598SMugunthan V N 3416aa1a15e2SDaniel Mack ss_res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 3417aa1a15e2SDaniel Mack ss_regs = devm_ioremap_resource(&pdev->dev, ss_res); 3418aa1a15e2SDaniel Mack if (IS_ERR(ss_regs)) { 3419aa1a15e2SDaniel Mack ret = PTR_ERR(ss_regs); 3420a4e32b0dSJohan Hovold goto clean_dt_ret; 3421df828598SMugunthan V N } 34225d8d0d4dSIvan Khoronzhuk cpsw->regs = ss_regs; 3423df828598SMugunthan V N 34242a05a622SIvan Khoronzhuk cpsw->version = readl(&cpsw->regs->id_ver); 3425f280e89aSMugunthan V N 3426aa1a15e2SDaniel Mack res = platform_get_resource(pdev, IORESOURCE_MEM, 1); 34275d8d0d4dSIvan Khoronzhuk cpsw->wr_regs = devm_ioremap_resource(&pdev->dev, res); 34285d8d0d4dSIvan Khoronzhuk if (IS_ERR(cpsw->wr_regs)) { 34295d8d0d4dSIvan Khoronzhuk ret = PTR_ERR(cpsw->wr_regs); 3430a4e32b0dSJohan Hovold goto clean_dt_ret; 3431df828598SMugunthan V N } 3432df828598SMugunthan V N 3433df828598SMugunthan V N memset(&dma_params, 0, sizeof(dma_params)); 3434549985eeSRichard Cochran memset(&ale_params, 0, sizeof(ale_params)); 3435549985eeSRichard Cochran 34362a05a622SIvan Khoronzhuk switch (cpsw->version) { 3437549985eeSRichard Cochran case CPSW_VERSION_1: 34385d8d0d4dSIvan Khoronzhuk cpsw->host_port_regs = ss_regs + CPSW1_HOST_PORT_OFFSET; 34398a2c9a5aSGrygorii Strashko cpts_regs = ss_regs + CPSW1_CPTS_OFFSET; 34405d8d0d4dSIvan Khoronzhuk cpsw->hw_stats = ss_regs + CPSW1_HW_STATS; 3441549985eeSRichard Cochran dma_params.dmaregs = ss_regs + CPSW1_CPDMA_OFFSET; 3442549985eeSRichard Cochran dma_params.txhdp = ss_regs + CPSW1_STATERAM_OFFSET; 3443549985eeSRichard Cochran ale_params.ale_regs = ss_regs + CPSW1_ALE_OFFSET; 3444549985eeSRichard Cochran slave_offset = CPSW1_SLAVE_OFFSET; 3445549985eeSRichard Cochran slave_size = CPSW1_SLAVE_SIZE; 3446549985eeSRichard Cochran sliver_offset = CPSW1_SLIVER_OFFSET; 3447549985eeSRichard Cochran dma_params.desc_mem_phys = 0; 3448549985eeSRichard Cochran break; 3449549985eeSRichard Cochran case CPSW_VERSION_2: 3450c193f365SMugunthan V N case CPSW_VERSION_3: 3451926489beSMugunthan V N case CPSW_VERSION_4: 34525d8d0d4dSIvan Khoronzhuk cpsw->host_port_regs = ss_regs + CPSW2_HOST_PORT_OFFSET; 34538a2c9a5aSGrygorii Strashko cpts_regs = ss_regs + CPSW2_CPTS_OFFSET; 34545d8d0d4dSIvan Khoronzhuk cpsw->hw_stats = ss_regs + CPSW2_HW_STATS; 3455549985eeSRichard Cochran dma_params.dmaregs = ss_regs + CPSW2_CPDMA_OFFSET; 3456549985eeSRichard Cochran dma_params.txhdp = ss_regs + CPSW2_STATERAM_OFFSET; 3457549985eeSRichard Cochran ale_params.ale_regs = ss_regs + CPSW2_ALE_OFFSET; 3458549985eeSRichard Cochran slave_offset = CPSW2_SLAVE_OFFSET; 3459549985eeSRichard Cochran slave_size = CPSW2_SLAVE_SIZE; 3460549985eeSRichard Cochran sliver_offset = CPSW2_SLIVER_OFFSET; 3461549985eeSRichard Cochran dma_params.desc_mem_phys = 3462aa1a15e2SDaniel Mack (u32 __force) ss_res->start + CPSW2_BD_OFFSET; 3463549985eeSRichard Cochran break; 3464549985eeSRichard Cochran default: 34652a05a622SIvan Khoronzhuk dev_err(priv->dev, "unknown version 0x%08x\n", cpsw->version); 3466549985eeSRichard Cochran ret = -ENODEV; 3467a4e32b0dSJohan Hovold goto clean_dt_ret; 3468549985eeSRichard Cochran } 3469606f3993SIvan Khoronzhuk for (i = 0; i < cpsw->data.slaves; i++) { 3470606f3993SIvan Khoronzhuk struct cpsw_slave *slave = &cpsw->slaves[i]; 3471606f3993SIvan Khoronzhuk 3472606f3993SIvan Khoronzhuk cpsw_slave_init(slave, cpsw, slave_offset, sliver_offset); 3473549985eeSRichard Cochran slave_offset += slave_size; 3474549985eeSRichard Cochran sliver_offset += SLIVER_SIZE; 3475549985eeSRichard Cochran } 3476549985eeSRichard Cochran 3477df828598SMugunthan V N dma_params.dev = &pdev->dev; 3478549985eeSRichard Cochran dma_params.rxthresh = dma_params.dmaregs + CPDMA_RXTHRESH; 3479549985eeSRichard Cochran dma_params.rxfree = dma_params.dmaregs + CPDMA_RXFREE; 3480549985eeSRichard Cochran dma_params.rxhdp = dma_params.txhdp + CPDMA_RXHDP; 3481549985eeSRichard Cochran dma_params.txcp = dma_params.txhdp + CPDMA_TXCP; 3482549985eeSRichard Cochran dma_params.rxcp = dma_params.txhdp + CPDMA_RXCP; 3483df828598SMugunthan V N 3484df828598SMugunthan V N dma_params.num_chan = data->channels; 3485df828598SMugunthan V N dma_params.has_soft_reset = true; 3486df828598SMugunthan V N dma_params.min_packet_size = CPSW_MIN_PACKET_SIZE; 3487df828598SMugunthan V N dma_params.desc_mem_size = data->bd_ram_size; 3488df828598SMugunthan V N dma_params.desc_align = 16; 3489df828598SMugunthan V N dma_params.has_ext_regs = true; 3490549985eeSRichard Cochran dma_params.desc_hw_addr = dma_params.desc_mem_phys; 349183fcad0cSIvan Khoronzhuk dma_params.bus_freq_mhz = cpsw->bus_freq_mhz; 349290225bf0SGrygorii Strashko dma_params.descs_pool_size = descs_pool_size; 3493df828598SMugunthan V N 34942c836bd9SIvan Khoronzhuk cpsw->dma = cpdma_ctlr_create(&dma_params); 34952c836bd9SIvan Khoronzhuk if (!cpsw->dma) { 3496df828598SMugunthan V N dev_err(priv->dev, "error initializing dma\n"); 3497df828598SMugunthan V N ret = -ENOMEM; 3498a4e32b0dSJohan Hovold goto clean_dt_ret; 3499df828598SMugunthan V N } 3500df828598SMugunthan V N 35019611d6d6SIvan Khoronzhuk soc = soc_device_match(cpsw_soc_devices); 35029611d6d6SIvan Khoronzhuk if (soc) 35039611d6d6SIvan Khoronzhuk cpsw->quirk_irq = 1; 35049611d6d6SIvan Khoronzhuk 350579b3325dSIvan Khoronzhuk ch = cpsw->quirk_irq ? 0 : 7; 350679b3325dSIvan Khoronzhuk cpsw->txv[0].ch = cpdma_chan_create(cpsw->dma, ch, cpsw_tx_handler, 0); 35078a83c5d7SIvan Khoronzhuk if (IS_ERR(cpsw->txv[0].ch)) { 35088a83c5d7SIvan Khoronzhuk dev_err(priv->dev, "error initializing tx dma channel\n"); 35098a83c5d7SIvan Khoronzhuk ret = PTR_ERR(cpsw->txv[0].ch); 35108a83c5d7SIvan Khoronzhuk goto clean_dma_ret; 35118a83c5d7SIvan Khoronzhuk } 35128a83c5d7SIvan Khoronzhuk 35138feb0a19SIvan Khoronzhuk cpsw->rxv[0].ch = cpdma_chan_create(cpsw->dma, 0, cpsw_rx_handler, 1); 35148a83c5d7SIvan Khoronzhuk if (IS_ERR(cpsw->rxv[0].ch)) { 35158a83c5d7SIvan Khoronzhuk dev_err(priv->dev, "error initializing rx dma channel\n"); 35168a83c5d7SIvan Khoronzhuk ret = PTR_ERR(cpsw->rxv[0].ch); 3517df828598SMugunthan V N goto clean_dma_ret; 3518df828598SMugunthan V N } 3519df828598SMugunthan V N 35209fe9aa0bSIvan Khoronzhuk ale_params.dev = &pdev->dev; 3521df828598SMugunthan V N ale_params.ale_ageout = ale_ageout; 3522df828598SMugunthan V N ale_params.ale_entries = data->ale_entries; 3523c6395f12SGrygorii Strashko ale_params.ale_ports = CPSW_ALE_PORTS_NUM; 3524df828598SMugunthan V N 35252a05a622SIvan Khoronzhuk cpsw->ale = cpsw_ale_create(&ale_params); 35262a05a622SIvan Khoronzhuk if (!cpsw->ale) { 3527df828598SMugunthan V N dev_err(priv->dev, "error initializing ale engine\n"); 3528df828598SMugunthan V N ret = -ENODEV; 3529df828598SMugunthan V N goto clean_dma_ret; 3530df828598SMugunthan V N } 3531df828598SMugunthan V N 35324a88fb95SGrygorii Strashko cpsw->cpts = cpts_create(cpsw->dev, cpts_regs, cpsw->dev->of_node); 35338a2c9a5aSGrygorii Strashko if (IS_ERR(cpsw->cpts)) { 35348a2c9a5aSGrygorii Strashko ret = PTR_ERR(cpsw->cpts); 35351971ab58SGrygorii Strashko goto clean_dma_ret; 35368a2c9a5aSGrygorii Strashko } 35378a2c9a5aSGrygorii Strashko 3538c03abd84SFelipe Balbi ndev->irq = platform_get_irq(pdev, 1); 3539df828598SMugunthan V N if (ndev->irq < 0) { 3540df828598SMugunthan V N dev_err(priv->dev, "error getting irq resource\n"); 3541c1e3334fSJulia Lawall ret = ndev->irq; 35421971ab58SGrygorii Strashko goto clean_dma_ret; 3543df828598SMugunthan V N } 3544df828598SMugunthan V N 3545a3a41d2fSGrygorii Strashko ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER | NETIF_F_HW_VLAN_CTAG_RX; 3546070f9c65SKeerthy 3547070f9c65SKeerthy ndev->netdev_ops = &cpsw_netdev_ops; 3548070f9c65SKeerthy ndev->ethtool_ops = &cpsw_ethtool_ops; 35499611d6d6SIvan Khoronzhuk netif_napi_add(ndev, &cpsw->napi_rx, 35509611d6d6SIvan Khoronzhuk cpsw->quirk_irq ? cpsw_rx_poll : cpsw_rx_mq_poll, 35519611d6d6SIvan Khoronzhuk CPSW_POLL_WEIGHT); 35529611d6d6SIvan Khoronzhuk netif_tx_napi_add(ndev, &cpsw->napi_tx, 35539611d6d6SIvan Khoronzhuk cpsw->quirk_irq ? cpsw_tx_poll : cpsw_tx_mq_poll, 35549611d6d6SIvan Khoronzhuk CPSW_POLL_WEIGHT); 3555070f9c65SKeerthy cpsw_split_res(ndev); 3556070f9c65SKeerthy 3557070f9c65SKeerthy /* register the network device */ 3558070f9c65SKeerthy SET_NETDEV_DEV(ndev, &pdev->dev); 3559070f9c65SKeerthy ret = register_netdev(ndev); 3560070f9c65SKeerthy if (ret) { 3561070f9c65SKeerthy dev_err(priv->dev, "error registering net device\n"); 3562070f9c65SKeerthy ret = -ENODEV; 35631971ab58SGrygorii Strashko goto clean_dma_ret; 3564070f9c65SKeerthy } 3565070f9c65SKeerthy 3566070f9c65SKeerthy if (cpsw->data.dual_emac) { 3567070f9c65SKeerthy ret = cpsw_probe_dual_emac(priv); 3568070f9c65SKeerthy if (ret) { 3569070f9c65SKeerthy cpsw_err(priv, probe, "error probe slave 2 emac interface\n"); 3570070f9c65SKeerthy goto clean_unregister_netdev_ret; 3571070f9c65SKeerthy } 3572070f9c65SKeerthy } 3573070f9c65SKeerthy 3574c03abd84SFelipe Balbi /* Grab RX and TX IRQs. Note that we also have RX_THRESHOLD and 3575c03abd84SFelipe Balbi * MISC IRQs which are always kept disabled with this driver so 3576c03abd84SFelipe Balbi * we will not request them. 3577c03abd84SFelipe Balbi * 3578c03abd84SFelipe Balbi * If anyone wants to implement support for those, make sure to 3579c03abd84SFelipe Balbi * first request and append them to irqs_table array. 3580c03abd84SFelipe Balbi */ 3581c2b32e58SDaniel Mack 3582c03abd84SFelipe Balbi /* RX IRQ */ 35835087b915SFelipe Balbi irq = platform_get_irq(pdev, 1); 3584c1e3334fSJulia Lawall if (irq < 0) { 3585c1e3334fSJulia Lawall ret = irq; 35861971ab58SGrygorii Strashko goto clean_dma_ret; 3587c1e3334fSJulia Lawall } 35885087b915SFelipe Balbi 3589e38b5a3dSIvan Khoronzhuk cpsw->irqs_table[0] = irq; 3590c03abd84SFelipe Balbi ret = devm_request_irq(&pdev->dev, irq, cpsw_rx_interrupt, 3591dbc4ec52SIvan Khoronzhuk 0, dev_name(&pdev->dev), cpsw); 35925087b915SFelipe Balbi if (ret < 0) { 35935087b915SFelipe Balbi dev_err(priv->dev, "error attaching irq (%d)\n", ret); 35941971ab58SGrygorii Strashko goto clean_dma_ret; 3595df828598SMugunthan V N } 3596df828598SMugunthan V N 3597c03abd84SFelipe Balbi /* TX IRQ */ 35985087b915SFelipe Balbi irq = platform_get_irq(pdev, 2); 3599c1e3334fSJulia Lawall if (irq < 0) { 3600c1e3334fSJulia Lawall ret = irq; 36011971ab58SGrygorii Strashko goto clean_dma_ret; 3602c1e3334fSJulia Lawall } 36035087b915SFelipe Balbi 3604e38b5a3dSIvan Khoronzhuk cpsw->irqs_table[1] = irq; 3605c03abd84SFelipe Balbi ret = devm_request_irq(&pdev->dev, irq, cpsw_tx_interrupt, 3606dbc4ec52SIvan Khoronzhuk 0, dev_name(&pdev->dev), cpsw); 36075087b915SFelipe Balbi if (ret < 0) { 36085087b915SFelipe Balbi dev_err(priv->dev, "error attaching irq (%d)\n", ret); 36091971ab58SGrygorii Strashko goto clean_dma_ret; 36105087b915SFelipe Balbi } 3611c2b32e58SDaniel Mack 361290225bf0SGrygorii Strashko cpsw_notice(priv, probe, 361390225bf0SGrygorii Strashko "initialized device (regs %pa, irq %d, pool size %d)\n", 361490225bf0SGrygorii Strashko &ss_res->start, ndev->irq, dma_params.descs_pool_size); 3615d9ba8f9eSMugunthan V N 3616c46ab7e0SJohan Hovold pm_runtime_put(&pdev->dev); 3617c46ab7e0SJohan Hovold 3618df828598SMugunthan V N return 0; 3619df828598SMugunthan V N 3620a7fe9d46SJohan Hovold clean_unregister_netdev_ret: 3621a7fe9d46SJohan Hovold unregister_netdev(ndev); 3622df828598SMugunthan V N clean_dma_ret: 36232c836bd9SIvan Khoronzhuk cpdma_ctlr_destroy(cpsw->dma); 3624a4e32b0dSJohan Hovold clean_dt_ret: 3625a4e32b0dSJohan Hovold cpsw_remove_dt(pdev); 3626c46ab7e0SJohan Hovold pm_runtime_put_sync(&pdev->dev); 3627aa1a15e2SDaniel Mack clean_runtime_disable_ret: 3628f150bd7fSMugunthan V N pm_runtime_disable(&pdev->dev); 3629df828598SMugunthan V N clean_ndev_ret: 3630d1bd9acfSSebastian Siewior free_netdev(priv->ndev); 3631df828598SMugunthan V N return ret; 3632df828598SMugunthan V N } 3633df828598SMugunthan V N 3634663e12e6SBill Pemberton static int cpsw_remove(struct platform_device *pdev) 3635df828598SMugunthan V N { 3636df828598SMugunthan V N struct net_device *ndev = platform_get_drvdata(pdev); 36372a05a622SIvan Khoronzhuk struct cpsw_common *cpsw = ndev_to_cpsw(ndev); 36388a0b6dc9SGrygorii Strashko int ret; 36398a0b6dc9SGrygorii Strashko 36408a0b6dc9SGrygorii Strashko ret = pm_runtime_get_sync(&pdev->dev); 36418a0b6dc9SGrygorii Strashko if (ret < 0) { 36428a0b6dc9SGrygorii Strashko pm_runtime_put_noidle(&pdev->dev); 36438a0b6dc9SGrygorii Strashko return ret; 36448a0b6dc9SGrygorii Strashko } 3645df828598SMugunthan V N 3646606f3993SIvan Khoronzhuk if (cpsw->data.dual_emac) 3647606f3993SIvan Khoronzhuk unregister_netdev(cpsw->slaves[1].ndev); 3648d1bd9acfSSebastian Siewior unregister_netdev(ndev); 3649df828598SMugunthan V N 36508a2c9a5aSGrygorii Strashko cpts_release(cpsw->cpts); 36512c836bd9SIvan Khoronzhuk cpdma_ctlr_destroy(cpsw->dma); 3652a4e32b0dSJohan Hovold cpsw_remove_dt(pdev); 36538a0b6dc9SGrygorii Strashko pm_runtime_put_sync(&pdev->dev); 36548a0b6dc9SGrygorii Strashko pm_runtime_disable(&pdev->dev); 3655606f3993SIvan Khoronzhuk if (cpsw->data.dual_emac) 3656606f3993SIvan Khoronzhuk free_netdev(cpsw->slaves[1].ndev); 3657df828598SMugunthan V N free_netdev(ndev); 3658df828598SMugunthan V N return 0; 3659df828598SMugunthan V N } 3660df828598SMugunthan V N 36618963a504SGrygorii Strashko #ifdef CONFIG_PM_SLEEP 3662df828598SMugunthan V N static int cpsw_suspend(struct device *dev) 3663df828598SMugunthan V N { 3664df828598SMugunthan V N struct platform_device *pdev = to_platform_device(dev); 3665df828598SMugunthan V N struct net_device *ndev = platform_get_drvdata(pdev); 3666606f3993SIvan Khoronzhuk struct cpsw_common *cpsw = ndev_to_cpsw(ndev); 3667df828598SMugunthan V N 3668606f3993SIvan Khoronzhuk if (cpsw->data.dual_emac) { 3669618073e3SMugunthan V N int i; 3670618073e3SMugunthan V N 3671606f3993SIvan Khoronzhuk for (i = 0; i < cpsw->data.slaves; i++) { 3672606f3993SIvan Khoronzhuk if (netif_running(cpsw->slaves[i].ndev)) 3673606f3993SIvan Khoronzhuk cpsw_ndo_stop(cpsw->slaves[i].ndev); 3674618073e3SMugunthan V N } 3675618073e3SMugunthan V N } else { 3676df828598SMugunthan V N if (netif_running(ndev)) 3677df828598SMugunthan V N cpsw_ndo_stop(ndev); 3678618073e3SMugunthan V N } 36791e7a2e21SDaniel Mack 3680739683b4SMugunthan V N /* Select sleep pin state */ 368156e31bd8SIvan Khoronzhuk pinctrl_pm_select_sleep_state(dev); 3682739683b4SMugunthan V N 3683df828598SMugunthan V N return 0; 3684df828598SMugunthan V N } 3685df828598SMugunthan V N 3686df828598SMugunthan V N static int cpsw_resume(struct device *dev) 3687df828598SMugunthan V N { 3688df828598SMugunthan V N struct platform_device *pdev = to_platform_device(dev); 3689df828598SMugunthan V N struct net_device *ndev = platform_get_drvdata(pdev); 3690a60ced99SIvan Khoronzhuk struct cpsw_common *cpsw = ndev_to_cpsw(ndev); 3691df828598SMugunthan V N 3692739683b4SMugunthan V N /* Select default pin state */ 369356e31bd8SIvan Khoronzhuk pinctrl_pm_select_default_state(dev); 3694739683b4SMugunthan V N 36954ccfd638SGrygorii Strashko /* shut up ASSERT_RTNL() warning in netif_set_real_num_tx/rx_queues */ 36964ccfd638SGrygorii Strashko rtnl_lock(); 3697606f3993SIvan Khoronzhuk if (cpsw->data.dual_emac) { 3698618073e3SMugunthan V N int i; 3699618073e3SMugunthan V N 3700606f3993SIvan Khoronzhuk for (i = 0; i < cpsw->data.slaves; i++) { 3701606f3993SIvan Khoronzhuk if (netif_running(cpsw->slaves[i].ndev)) 3702606f3993SIvan Khoronzhuk cpsw_ndo_open(cpsw->slaves[i].ndev); 3703618073e3SMugunthan V N } 3704618073e3SMugunthan V N } else { 3705df828598SMugunthan V N if (netif_running(ndev)) 3706df828598SMugunthan V N cpsw_ndo_open(ndev); 3707618073e3SMugunthan V N } 37084ccfd638SGrygorii Strashko rtnl_unlock(); 37094ccfd638SGrygorii Strashko 3710df828598SMugunthan V N return 0; 3711df828598SMugunthan V N } 37128963a504SGrygorii Strashko #endif 3713df828598SMugunthan V N 37148963a504SGrygorii Strashko static SIMPLE_DEV_PM_OPS(cpsw_pm_ops, cpsw_suspend, cpsw_resume); 3715df828598SMugunthan V N 3716df828598SMugunthan V N static struct platform_driver cpsw_driver = { 3717df828598SMugunthan V N .driver = { 3718df828598SMugunthan V N .name = "cpsw", 3719df828598SMugunthan V N .pm = &cpsw_pm_ops, 37201e5c76d4SSachin Kamat .of_match_table = cpsw_of_mtable, 3721df828598SMugunthan V N }, 3722df828598SMugunthan V N .probe = cpsw_probe, 3723663e12e6SBill Pemberton .remove = cpsw_remove, 3724df828598SMugunthan V N }; 3725df828598SMugunthan V N 37266fb3b6b5SGrygorii Strashko module_platform_driver(cpsw_driver); 3727df828598SMugunthan V N 3728df828598SMugunthan V N MODULE_LICENSE("GPL"); 3729df828598SMugunthan V N MODULE_AUTHOR("Cyril Chemparathy <cyril@ti.com>"); 3730df828598SMugunthan V N MODULE_AUTHOR("Mugunthan V N <mugunthanvnm@ti.com>"); 3731df828598SMugunthan V N MODULE_DESCRIPTION("TI CPSW Ethernet driver"); 3732