1df828598SMugunthan V N /* 2df828598SMugunthan V N * Texas Instruments Ethernet Switch Driver 3df828598SMugunthan V N * 4df828598SMugunthan V N * Copyright (C) 2012 Texas Instruments 5df828598SMugunthan V N * 6df828598SMugunthan V N * This program is free software; you can redistribute it and/or 7df828598SMugunthan V N * modify it under the terms of the GNU General Public License as 8df828598SMugunthan V N * published by the Free Software Foundation version 2. 9df828598SMugunthan V N * 10df828598SMugunthan V N * This program is distributed "as is" WITHOUT ANY WARRANTY of any 11df828598SMugunthan V N * kind, whether express or implied; without even the implied warranty 12df828598SMugunthan V N * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13df828598SMugunthan V N * GNU General Public License for more details. 14df828598SMugunthan V N */ 15df828598SMugunthan V N 16df828598SMugunthan V N #include <linux/kernel.h> 17df828598SMugunthan V N #include <linux/io.h> 18df828598SMugunthan V N #include <linux/clk.h> 19df828598SMugunthan V N #include <linux/timer.h> 20df828598SMugunthan V N #include <linux/module.h> 21df828598SMugunthan V N #include <linux/platform_device.h> 22df828598SMugunthan V N #include <linux/irqreturn.h> 23df828598SMugunthan V N #include <linux/interrupt.h> 24df828598SMugunthan V N #include <linux/if_ether.h> 25df828598SMugunthan V N #include <linux/etherdevice.h> 26df828598SMugunthan V N #include <linux/netdevice.h> 272e5b38abSRichard Cochran #include <linux/net_tstamp.h> 28df828598SMugunthan V N #include <linux/phy.h> 29df828598SMugunthan V N #include <linux/workqueue.h> 30df828598SMugunthan V N #include <linux/delay.h> 31f150bd7fSMugunthan V N #include <linux/pm_runtime.h> 322eb32b0aSMugunthan V N #include <linux/of.h> 332eb32b0aSMugunthan V N #include <linux/of_net.h> 342eb32b0aSMugunthan V N #include <linux/of_device.h> 353b72c2feSMugunthan V N #include <linux/if_vlan.h> 36df828598SMugunthan V N 37df828598SMugunthan V N #include <linux/platform_data/cpsw.h> 38df828598SMugunthan V N 39df828598SMugunthan V N #include "cpsw_ale.h" 402e5b38abSRichard Cochran #include "cpts.h" 41df828598SMugunthan V N #include "davinci_cpdma.h" 42df828598SMugunthan V N 43df828598SMugunthan V N #define CPSW_DEBUG (NETIF_MSG_HW | NETIF_MSG_WOL | \ 44df828598SMugunthan V N NETIF_MSG_DRV | NETIF_MSG_LINK | \ 45df828598SMugunthan V N NETIF_MSG_IFUP | NETIF_MSG_INTR | \ 46df828598SMugunthan V N NETIF_MSG_PROBE | NETIF_MSG_TIMER | \ 47df828598SMugunthan V N NETIF_MSG_IFDOWN | NETIF_MSG_RX_ERR | \ 48df828598SMugunthan V N NETIF_MSG_TX_ERR | NETIF_MSG_TX_DONE | \ 49df828598SMugunthan V N NETIF_MSG_PKTDATA | NETIF_MSG_TX_QUEUED | \ 50df828598SMugunthan V N NETIF_MSG_RX_STATUS) 51df828598SMugunthan V N 52df828598SMugunthan V N #define cpsw_info(priv, type, format, ...) \ 53df828598SMugunthan V N do { \ 54df828598SMugunthan V N if (netif_msg_##type(priv) && net_ratelimit()) \ 55df828598SMugunthan V N dev_info(priv->dev, format, ## __VA_ARGS__); \ 56df828598SMugunthan V N } while (0) 57df828598SMugunthan V N 58df828598SMugunthan V N #define cpsw_err(priv, type, format, ...) \ 59df828598SMugunthan V N do { \ 60df828598SMugunthan V N if (netif_msg_##type(priv) && net_ratelimit()) \ 61df828598SMugunthan V N dev_err(priv->dev, format, ## __VA_ARGS__); \ 62df828598SMugunthan V N } while (0) 63df828598SMugunthan V N 64df828598SMugunthan V N #define cpsw_dbg(priv, type, format, ...) \ 65df828598SMugunthan V N do { \ 66df828598SMugunthan V N if (netif_msg_##type(priv) && net_ratelimit()) \ 67df828598SMugunthan V N dev_dbg(priv->dev, format, ## __VA_ARGS__); \ 68df828598SMugunthan V N } while (0) 69df828598SMugunthan V N 70df828598SMugunthan V N #define cpsw_notice(priv, type, format, ...) \ 71df828598SMugunthan V N do { \ 72df828598SMugunthan V N if (netif_msg_##type(priv) && net_ratelimit()) \ 73df828598SMugunthan V N dev_notice(priv->dev, format, ## __VA_ARGS__); \ 74df828598SMugunthan V N } while (0) 75df828598SMugunthan V N 765c50a856SMugunthan V N #define ALE_ALL_PORTS 0x7 775c50a856SMugunthan V N 78df828598SMugunthan V N #define CPSW_MAJOR_VERSION(reg) (reg >> 8 & 0x7) 79df828598SMugunthan V N #define CPSW_MINOR_VERSION(reg) (reg & 0xff) 80df828598SMugunthan V N #define CPSW_RTL_VERSION(reg) ((reg >> 11) & 0x1f) 81df828598SMugunthan V N 82e90cfac6SRichard Cochran #define CPSW_VERSION_1 0x19010a 83e90cfac6SRichard Cochran #define CPSW_VERSION_2 0x19010c 84549985eeSRichard Cochran 85549985eeSRichard Cochran #define HOST_PORT_NUM 0 86549985eeSRichard Cochran #define SLIVER_SIZE 0x40 87549985eeSRichard Cochran 88549985eeSRichard Cochran #define CPSW1_HOST_PORT_OFFSET 0x028 89549985eeSRichard Cochran #define CPSW1_SLAVE_OFFSET 0x050 90549985eeSRichard Cochran #define CPSW1_SLAVE_SIZE 0x040 91549985eeSRichard Cochran #define CPSW1_CPDMA_OFFSET 0x100 92549985eeSRichard Cochran #define CPSW1_STATERAM_OFFSET 0x200 93549985eeSRichard Cochran #define CPSW1_CPTS_OFFSET 0x500 94549985eeSRichard Cochran #define CPSW1_ALE_OFFSET 0x600 95549985eeSRichard Cochran #define CPSW1_SLIVER_OFFSET 0x700 96549985eeSRichard Cochran 97549985eeSRichard Cochran #define CPSW2_HOST_PORT_OFFSET 0x108 98549985eeSRichard Cochran #define CPSW2_SLAVE_OFFSET 0x200 99549985eeSRichard Cochran #define CPSW2_SLAVE_SIZE 0x100 100549985eeSRichard Cochran #define CPSW2_CPDMA_OFFSET 0x800 101549985eeSRichard Cochran #define CPSW2_STATERAM_OFFSET 0xa00 102549985eeSRichard Cochran #define CPSW2_CPTS_OFFSET 0xc00 103549985eeSRichard Cochran #define CPSW2_ALE_OFFSET 0xd00 104549985eeSRichard Cochran #define CPSW2_SLIVER_OFFSET 0xd80 105549985eeSRichard Cochran #define CPSW2_BD_OFFSET 0x2000 106549985eeSRichard Cochran 107df828598SMugunthan V N #define CPDMA_RXTHRESH 0x0c0 108df828598SMugunthan V N #define CPDMA_RXFREE 0x0e0 109df828598SMugunthan V N #define CPDMA_TXHDP 0x00 110df828598SMugunthan V N #define CPDMA_RXHDP 0x20 111df828598SMugunthan V N #define CPDMA_TXCP 0x40 112df828598SMugunthan V N #define CPDMA_RXCP 0x60 113df828598SMugunthan V N 114df828598SMugunthan V N #define CPSW_POLL_WEIGHT 64 115df828598SMugunthan V N #define CPSW_MIN_PACKET_SIZE 60 116df828598SMugunthan V N #define CPSW_MAX_PACKET_SIZE (1500 + 14 + 4 + 4) 117df828598SMugunthan V N 118df828598SMugunthan V N #define RX_PRIORITY_MAPPING 0x76543210 119df828598SMugunthan V N #define TX_PRIORITY_MAPPING 0x33221100 120df828598SMugunthan V N #define CPDMA_TX_PRIORITY_MAP 0x76543210 121df828598SMugunthan V N 1223b72c2feSMugunthan V N #define CPSW_VLAN_AWARE BIT(1) 1233b72c2feSMugunthan V N #define CPSW_ALE_VLAN_AWARE 1 1243b72c2feSMugunthan V N 125df828598SMugunthan V N #define cpsw_enable_irq(priv) \ 126df828598SMugunthan V N do { \ 127df828598SMugunthan V N u32 i; \ 128df828598SMugunthan V N for (i = 0; i < priv->num_irqs; i++) \ 129df828598SMugunthan V N enable_irq(priv->irqs_table[i]); \ 130df828598SMugunthan V N } while (0); 131df828598SMugunthan V N #define cpsw_disable_irq(priv) \ 132df828598SMugunthan V N do { \ 133df828598SMugunthan V N u32 i; \ 134df828598SMugunthan V N for (i = 0; i < priv->num_irqs; i++) \ 135df828598SMugunthan V N disable_irq_nosync(priv->irqs_table[i]); \ 136df828598SMugunthan V N } while (0); 137df828598SMugunthan V N 138df828598SMugunthan V N static int debug_level; 139df828598SMugunthan V N module_param(debug_level, int, 0); 140df828598SMugunthan V N MODULE_PARM_DESC(debug_level, "cpsw debug level (NETIF_MSG bits)"); 141df828598SMugunthan V N 142df828598SMugunthan V N static int ale_ageout = 10; 143df828598SMugunthan V N module_param(ale_ageout, int, 0); 144df828598SMugunthan V N MODULE_PARM_DESC(ale_ageout, "cpsw ale ageout interval (seconds)"); 145df828598SMugunthan V N 146df828598SMugunthan V N static int rx_packet_max = CPSW_MAX_PACKET_SIZE; 147df828598SMugunthan V N module_param(rx_packet_max, int, 0); 148df828598SMugunthan V N MODULE_PARM_DESC(rx_packet_max, "maximum receive packet size (bytes)"); 149df828598SMugunthan V N 150996a5c27SRichard Cochran struct cpsw_wr_regs { 151df828598SMugunthan V N u32 id_ver; 152df828598SMugunthan V N u32 soft_reset; 153df828598SMugunthan V N u32 control; 154df828598SMugunthan V N u32 int_control; 155df828598SMugunthan V N u32 rx_thresh_en; 156df828598SMugunthan V N u32 rx_en; 157df828598SMugunthan V N u32 tx_en; 158df828598SMugunthan V N u32 misc_en; 159df828598SMugunthan V N }; 160df828598SMugunthan V N 161996a5c27SRichard Cochran struct cpsw_ss_regs { 162df828598SMugunthan V N u32 id_ver; 163df828598SMugunthan V N u32 control; 164df828598SMugunthan V N u32 soft_reset; 165df828598SMugunthan V N u32 stat_port_en; 166df828598SMugunthan V N u32 ptype; 167bd357af2SRichard Cochran u32 soft_idle; 168bd357af2SRichard Cochran u32 thru_rate; 169bd357af2SRichard Cochran u32 gap_thresh; 170bd357af2SRichard Cochran u32 tx_start_wds; 171bd357af2SRichard Cochran u32 flow_control; 172bd357af2SRichard Cochran u32 vlan_ltype; 173bd357af2SRichard Cochran u32 ts_ltype; 174bd357af2SRichard Cochran u32 dlr_ltype; 175df828598SMugunthan V N }; 176df828598SMugunthan V N 1779750a3adSRichard Cochran /* CPSW_PORT_V1 */ 1789750a3adSRichard Cochran #define CPSW1_MAX_BLKS 0x00 /* Maximum FIFO Blocks */ 1799750a3adSRichard Cochran #define CPSW1_BLK_CNT 0x04 /* FIFO Block Usage Count (Read Only) */ 1809750a3adSRichard Cochran #define CPSW1_TX_IN_CTL 0x08 /* Transmit FIFO Control */ 1819750a3adSRichard Cochran #define CPSW1_PORT_VLAN 0x0c /* VLAN Register */ 1829750a3adSRichard Cochran #define CPSW1_TX_PRI_MAP 0x10 /* Tx Header Priority to Switch Pri Mapping */ 1839750a3adSRichard Cochran #define CPSW1_TS_CTL 0x14 /* Time Sync Control */ 1849750a3adSRichard Cochran #define CPSW1_TS_SEQ_LTYPE 0x18 /* Time Sync Sequence ID Offset and Msg Type */ 1859750a3adSRichard Cochran #define CPSW1_TS_VLAN 0x1c /* Time Sync VLAN1 and VLAN2 */ 1869750a3adSRichard Cochran 1879750a3adSRichard Cochran /* CPSW_PORT_V2 */ 1889750a3adSRichard Cochran #define CPSW2_CONTROL 0x00 /* Control Register */ 1899750a3adSRichard Cochran #define CPSW2_MAX_BLKS 0x08 /* Maximum FIFO Blocks */ 1909750a3adSRichard Cochran #define CPSW2_BLK_CNT 0x0c /* FIFO Block Usage Count (Read Only) */ 1919750a3adSRichard Cochran #define CPSW2_TX_IN_CTL 0x10 /* Transmit FIFO Control */ 1929750a3adSRichard Cochran #define CPSW2_PORT_VLAN 0x14 /* VLAN Register */ 1939750a3adSRichard Cochran #define CPSW2_TX_PRI_MAP 0x18 /* Tx Header Priority to Switch Pri Mapping */ 1949750a3adSRichard Cochran #define CPSW2_TS_SEQ_MTYPE 0x1c /* Time Sync Sequence ID Offset and Msg Type */ 1959750a3adSRichard Cochran 1969750a3adSRichard Cochran /* CPSW_PORT_V1 and V2 */ 1979750a3adSRichard Cochran #define SA_LO 0x20 /* CPGMAC_SL Source Address Low */ 1989750a3adSRichard Cochran #define SA_HI 0x24 /* CPGMAC_SL Source Address High */ 1999750a3adSRichard Cochran #define SEND_PERCENT 0x28 /* Transmit Queue Send Percentages */ 2009750a3adSRichard Cochran 2019750a3adSRichard Cochran /* CPSW_PORT_V2 only */ 2029750a3adSRichard Cochran #define RX_DSCP_PRI_MAP0 0x30 /* Rx DSCP Priority to Rx Packet Mapping */ 2039750a3adSRichard Cochran #define RX_DSCP_PRI_MAP1 0x34 /* Rx DSCP Priority to Rx Packet Mapping */ 2049750a3adSRichard Cochran #define RX_DSCP_PRI_MAP2 0x38 /* Rx DSCP Priority to Rx Packet Mapping */ 2059750a3adSRichard Cochran #define RX_DSCP_PRI_MAP3 0x3c /* Rx DSCP Priority to Rx Packet Mapping */ 2069750a3adSRichard Cochran #define RX_DSCP_PRI_MAP4 0x40 /* Rx DSCP Priority to Rx Packet Mapping */ 2079750a3adSRichard Cochran #define RX_DSCP_PRI_MAP5 0x44 /* Rx DSCP Priority to Rx Packet Mapping */ 2089750a3adSRichard Cochran #define RX_DSCP_PRI_MAP6 0x48 /* Rx DSCP Priority to Rx Packet Mapping */ 2099750a3adSRichard Cochran #define RX_DSCP_PRI_MAP7 0x4c /* Rx DSCP Priority to Rx Packet Mapping */ 2109750a3adSRichard Cochran 2119750a3adSRichard Cochran /* Bit definitions for the CPSW2_CONTROL register */ 2129750a3adSRichard Cochran #define PASS_PRI_TAGGED (1<<24) /* Pass Priority Tagged */ 2139750a3adSRichard Cochran #define VLAN_LTYPE2_EN (1<<21) /* VLAN LTYPE 2 enable */ 2149750a3adSRichard Cochran #define VLAN_LTYPE1_EN (1<<20) /* VLAN LTYPE 1 enable */ 2159750a3adSRichard Cochran #define DSCP_PRI_EN (1<<16) /* DSCP Priority Enable */ 2169750a3adSRichard Cochran #define TS_320 (1<<14) /* Time Sync Dest Port 320 enable */ 2179750a3adSRichard Cochran #define TS_319 (1<<13) /* Time Sync Dest Port 319 enable */ 2189750a3adSRichard Cochran #define TS_132 (1<<12) /* Time Sync Dest IP Addr 132 enable */ 2199750a3adSRichard Cochran #define TS_131 (1<<11) /* Time Sync Dest IP Addr 131 enable */ 2209750a3adSRichard Cochran #define TS_130 (1<<10) /* Time Sync Dest IP Addr 130 enable */ 2219750a3adSRichard Cochran #define TS_129 (1<<9) /* Time Sync Dest IP Addr 129 enable */ 2229750a3adSRichard Cochran #define TS_BIT8 (1<<8) /* ts_ttl_nonzero? */ 2239750a3adSRichard Cochran #define TS_ANNEX_D_EN (1<<4) /* Time Sync Annex D enable */ 2249750a3adSRichard Cochran #define TS_LTYPE2_EN (1<<3) /* Time Sync LTYPE 2 enable */ 2259750a3adSRichard Cochran #define TS_LTYPE1_EN (1<<2) /* Time Sync LTYPE 1 enable */ 2269750a3adSRichard Cochran #define TS_TX_EN (1<<1) /* Time Sync Transmit Enable */ 2279750a3adSRichard Cochran #define TS_RX_EN (1<<0) /* Time Sync Receive Enable */ 2289750a3adSRichard Cochran 2299750a3adSRichard Cochran #define CTRL_TS_BITS \ 2309750a3adSRichard Cochran (TS_320 | TS_319 | TS_132 | TS_131 | TS_130 | TS_129 | TS_BIT8 | \ 2319750a3adSRichard Cochran TS_ANNEX_D_EN | TS_LTYPE1_EN) 2329750a3adSRichard Cochran 2339750a3adSRichard Cochran #define CTRL_ALL_TS_MASK (CTRL_TS_BITS | TS_TX_EN | TS_RX_EN) 2349750a3adSRichard Cochran #define CTRL_TX_TS_BITS (CTRL_TS_BITS | TS_TX_EN) 2359750a3adSRichard Cochran #define CTRL_RX_TS_BITS (CTRL_TS_BITS | TS_RX_EN) 2369750a3adSRichard Cochran 2379750a3adSRichard Cochran /* Bit definitions for the CPSW2_TS_SEQ_MTYPE register */ 2389750a3adSRichard Cochran #define TS_SEQ_ID_OFFSET_SHIFT (16) /* Time Sync Sequence ID Offset */ 2399750a3adSRichard Cochran #define TS_SEQ_ID_OFFSET_MASK (0x3f) 2409750a3adSRichard Cochran #define TS_MSG_TYPE_EN_SHIFT (0) /* Time Sync Message Type Enable */ 2419750a3adSRichard Cochran #define TS_MSG_TYPE_EN_MASK (0xffff) 2429750a3adSRichard Cochran 2439750a3adSRichard Cochran /* The PTP event messages - Sync, Delay_Req, Pdelay_Req, and Pdelay_Resp. */ 2449750a3adSRichard Cochran #define EVENT_MSG_BITS ((1<<0) | (1<<1) | (1<<2) | (1<<3)) 245df828598SMugunthan V N 2462e5b38abSRichard Cochran /* Bit definitions for the CPSW1_TS_CTL register */ 2472e5b38abSRichard Cochran #define CPSW_V1_TS_RX_EN BIT(0) 2482e5b38abSRichard Cochran #define CPSW_V1_TS_TX_EN BIT(4) 2492e5b38abSRichard Cochran #define CPSW_V1_MSG_TYPE_OFS 16 2502e5b38abSRichard Cochran 2512e5b38abSRichard Cochran /* Bit definitions for the CPSW1_TS_SEQ_LTYPE register */ 2522e5b38abSRichard Cochran #define CPSW_V1_SEQ_ID_OFS_SHIFT 16 2532e5b38abSRichard Cochran 254df828598SMugunthan V N struct cpsw_host_regs { 255df828598SMugunthan V N u32 max_blks; 256df828598SMugunthan V N u32 blk_cnt; 257df828598SMugunthan V N u32 flow_thresh; 258df828598SMugunthan V N u32 port_vlan; 259df828598SMugunthan V N u32 tx_pri_map; 260df828598SMugunthan V N u32 cpdma_tx_pri_map; 261df828598SMugunthan V N u32 cpdma_rx_chan_map; 262df828598SMugunthan V N }; 263df828598SMugunthan V N 264df828598SMugunthan V N struct cpsw_sliver_regs { 265df828598SMugunthan V N u32 id_ver; 266df828598SMugunthan V N u32 mac_control; 267df828598SMugunthan V N u32 mac_status; 268df828598SMugunthan V N u32 soft_reset; 269df828598SMugunthan V N u32 rx_maxlen; 270df828598SMugunthan V N u32 __reserved_0; 271df828598SMugunthan V N u32 rx_pause; 272df828598SMugunthan V N u32 tx_pause; 273df828598SMugunthan V N u32 __reserved_1; 274df828598SMugunthan V N u32 rx_pri_map; 275df828598SMugunthan V N }; 276df828598SMugunthan V N 277df828598SMugunthan V N struct cpsw_slave { 2789750a3adSRichard Cochran void __iomem *regs; 279df828598SMugunthan V N struct cpsw_sliver_regs __iomem *sliver; 280df828598SMugunthan V N int slave_num; 281df828598SMugunthan V N u32 mac_control; 282df828598SMugunthan V N struct cpsw_slave_data *data; 283df828598SMugunthan V N struct phy_device *phy; 284df828598SMugunthan V N }; 285df828598SMugunthan V N 2869750a3adSRichard Cochran static inline u32 slave_read(struct cpsw_slave *slave, u32 offset) 2879750a3adSRichard Cochran { 2889750a3adSRichard Cochran return __raw_readl(slave->regs + offset); 2899750a3adSRichard Cochran } 2909750a3adSRichard Cochran 2919750a3adSRichard Cochran static inline void slave_write(struct cpsw_slave *slave, u32 val, u32 offset) 2929750a3adSRichard Cochran { 2939750a3adSRichard Cochran __raw_writel(val, slave->regs + offset); 2949750a3adSRichard Cochran } 2959750a3adSRichard Cochran 296df828598SMugunthan V N struct cpsw_priv { 297df828598SMugunthan V N spinlock_t lock; 298df828598SMugunthan V N struct platform_device *pdev; 299df828598SMugunthan V N struct net_device *ndev; 300df828598SMugunthan V N struct resource *cpsw_res; 301a65dd5b2SRichard Cochran struct resource *cpsw_wr_res; 302df828598SMugunthan V N struct napi_struct napi; 303df828598SMugunthan V N struct device *dev; 304df828598SMugunthan V N struct cpsw_platform_data data; 305996a5c27SRichard Cochran struct cpsw_ss_regs __iomem *regs; 306996a5c27SRichard Cochran struct cpsw_wr_regs __iomem *wr_regs; 307df828598SMugunthan V N struct cpsw_host_regs __iomem *host_port_regs; 308df828598SMugunthan V N u32 msg_enable; 309e90cfac6SRichard Cochran u32 version; 310df828598SMugunthan V N struct net_device_stats stats; 311df828598SMugunthan V N int rx_packet_max; 312df828598SMugunthan V N int host_port; 313df828598SMugunthan V N struct clk *clk; 314df828598SMugunthan V N u8 mac_addr[ETH_ALEN]; 315df828598SMugunthan V N struct cpsw_slave *slaves; 316df828598SMugunthan V N struct cpdma_ctlr *dma; 317df828598SMugunthan V N struct cpdma_chan *txch, *rxch; 318df828598SMugunthan V N struct cpsw_ale *ale; 319df828598SMugunthan V N /* snapshot of IRQ numbers */ 320df828598SMugunthan V N u32 irqs_table[4]; 321df828598SMugunthan V N u32 num_irqs; 3222e5b38abSRichard Cochran struct cpts cpts; 323df828598SMugunthan V N }; 324df828598SMugunthan V N 325df828598SMugunthan V N #define napi_to_priv(napi) container_of(napi, struct cpsw_priv, napi) 326df828598SMugunthan V N #define for_each_slave(priv, func, arg...) \ 327df828598SMugunthan V N do { \ 328df828598SMugunthan V N int idx; \ 329df828598SMugunthan V N for (idx = 0; idx < (priv)->data.slaves; idx++) \ 330df828598SMugunthan V N (func)((priv)->slaves + idx, ##arg); \ 331df828598SMugunthan V N } while (0) 332df828598SMugunthan V N 3335c50a856SMugunthan V N static void cpsw_ndo_set_rx_mode(struct net_device *ndev) 3345c50a856SMugunthan V N { 3355c50a856SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 3365c50a856SMugunthan V N 3375c50a856SMugunthan V N if (ndev->flags & IFF_PROMISC) { 3385c50a856SMugunthan V N /* Enable promiscuous mode */ 3395c50a856SMugunthan V N dev_err(priv->dev, "Ignoring Promiscuous mode\n"); 3405c50a856SMugunthan V N return; 3415c50a856SMugunthan V N } 3425c50a856SMugunthan V N 3435c50a856SMugunthan V N /* Clear all mcast from ALE */ 3445c50a856SMugunthan V N cpsw_ale_flush_multicast(priv->ale, ALE_ALL_PORTS << priv->host_port); 3455c50a856SMugunthan V N 3465c50a856SMugunthan V N if (!netdev_mc_empty(ndev)) { 3475c50a856SMugunthan V N struct netdev_hw_addr *ha; 3485c50a856SMugunthan V N 3495c50a856SMugunthan V N /* program multicast address list into ALE register */ 3505c50a856SMugunthan V N netdev_for_each_mc_addr(ha, ndev) { 3515c50a856SMugunthan V N cpsw_ale_add_mcast(priv->ale, (u8 *)ha->addr, 352e11b220fSMugunthan V N ALE_ALL_PORTS << priv->host_port, 0, 0, 0); 3535c50a856SMugunthan V N } 3545c50a856SMugunthan V N } 3555c50a856SMugunthan V N } 3565c50a856SMugunthan V N 357df828598SMugunthan V N static void cpsw_intr_enable(struct cpsw_priv *priv) 358df828598SMugunthan V N { 359996a5c27SRichard Cochran __raw_writel(0xFF, &priv->wr_regs->tx_en); 360996a5c27SRichard Cochran __raw_writel(0xFF, &priv->wr_regs->rx_en); 361df828598SMugunthan V N 362df828598SMugunthan V N cpdma_ctlr_int_ctrl(priv->dma, true); 363df828598SMugunthan V N return; 364df828598SMugunthan V N } 365df828598SMugunthan V N 366df828598SMugunthan V N static void cpsw_intr_disable(struct cpsw_priv *priv) 367df828598SMugunthan V N { 368996a5c27SRichard Cochran __raw_writel(0, &priv->wr_regs->tx_en); 369996a5c27SRichard Cochran __raw_writel(0, &priv->wr_regs->rx_en); 370df828598SMugunthan V N 371df828598SMugunthan V N cpdma_ctlr_int_ctrl(priv->dma, false); 372df828598SMugunthan V N return; 373df828598SMugunthan V N } 374df828598SMugunthan V N 375df828598SMugunthan V N void cpsw_tx_handler(void *token, int len, int status) 376df828598SMugunthan V N { 377df828598SMugunthan V N struct sk_buff *skb = token; 378df828598SMugunthan V N struct net_device *ndev = skb->dev; 379df828598SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 380df828598SMugunthan V N 381fae50823SMugunthan V N /* Check whether the queue is stopped due to stalled tx dma, if the 382fae50823SMugunthan V N * queue is stopped then start the queue as we have free desc for tx 383fae50823SMugunthan V N */ 384df828598SMugunthan V N if (unlikely(netif_queue_stopped(ndev))) 385df828598SMugunthan V N netif_start_queue(ndev); 3862e5b38abSRichard Cochran cpts_tx_timestamp(&priv->cpts, skb); 387df828598SMugunthan V N priv->stats.tx_packets++; 388df828598SMugunthan V N priv->stats.tx_bytes += len; 389df828598SMugunthan V N dev_kfree_skb_any(skb); 390df828598SMugunthan V N } 391df828598SMugunthan V N 392df828598SMugunthan V N void cpsw_rx_handler(void *token, int len, int status) 393df828598SMugunthan V N { 394df828598SMugunthan V N struct sk_buff *skb = token; 395df828598SMugunthan V N struct net_device *ndev = skb->dev; 396df828598SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 397df828598SMugunthan V N int ret = 0; 398df828598SMugunthan V N 399df828598SMugunthan V N /* free and bail if we are shutting down */ 400df828598SMugunthan V N if (unlikely(!netif_running(ndev)) || 401df828598SMugunthan V N unlikely(!netif_carrier_ok(ndev))) { 402df828598SMugunthan V N dev_kfree_skb_any(skb); 403df828598SMugunthan V N return; 404df828598SMugunthan V N } 405df828598SMugunthan V N if (likely(status >= 0)) { 406df828598SMugunthan V N skb_put(skb, len); 4072e5b38abSRichard Cochran cpts_rx_timestamp(&priv->cpts, skb); 408df828598SMugunthan V N skb->protocol = eth_type_trans(skb, ndev); 409df828598SMugunthan V N netif_receive_skb(skb); 410df828598SMugunthan V N priv->stats.rx_bytes += len; 411df828598SMugunthan V N priv->stats.rx_packets++; 412df828598SMugunthan V N skb = NULL; 413df828598SMugunthan V N } 414df828598SMugunthan V N 415df828598SMugunthan V N if (unlikely(!netif_running(ndev))) { 416df828598SMugunthan V N if (skb) 417df828598SMugunthan V N dev_kfree_skb_any(skb); 418df828598SMugunthan V N return; 419df828598SMugunthan V N } 420df828598SMugunthan V N 421df828598SMugunthan V N if (likely(!skb)) { 422df828598SMugunthan V N skb = netdev_alloc_skb_ip_align(ndev, priv->rx_packet_max); 423df828598SMugunthan V N if (WARN_ON(!skb)) 424df828598SMugunthan V N return; 425df828598SMugunthan V N 426df828598SMugunthan V N ret = cpdma_chan_submit(priv->rxch, skb, skb->data, 427f6e135c8SMugunthan V N skb_tailroom(skb), 0, GFP_KERNEL); 428df828598SMugunthan V N } 429df828598SMugunthan V N WARN_ON(ret < 0); 430df828598SMugunthan V N } 431df828598SMugunthan V N 432df828598SMugunthan V N static irqreturn_t cpsw_interrupt(int irq, void *dev_id) 433df828598SMugunthan V N { 434df828598SMugunthan V N struct cpsw_priv *priv = dev_id; 435df828598SMugunthan V N 436df828598SMugunthan V N if (likely(netif_running(priv->ndev))) { 437df828598SMugunthan V N cpsw_intr_disable(priv); 438df828598SMugunthan V N cpsw_disable_irq(priv); 439df828598SMugunthan V N napi_schedule(&priv->napi); 440df828598SMugunthan V N } 441df828598SMugunthan V N return IRQ_HANDLED; 442df828598SMugunthan V N } 443df828598SMugunthan V N 444df828598SMugunthan V N static inline int cpsw_get_slave_port(struct cpsw_priv *priv, u32 slave_num) 445df828598SMugunthan V N { 446df828598SMugunthan V N if (priv->host_port == 0) 447df828598SMugunthan V N return slave_num + 1; 448df828598SMugunthan V N else 449df828598SMugunthan V N return slave_num; 450df828598SMugunthan V N } 451df828598SMugunthan V N 452df828598SMugunthan V N static int cpsw_poll(struct napi_struct *napi, int budget) 453df828598SMugunthan V N { 454df828598SMugunthan V N struct cpsw_priv *priv = napi_to_priv(napi); 455df828598SMugunthan V N int num_tx, num_rx; 456df828598SMugunthan V N 457df828598SMugunthan V N num_tx = cpdma_chan_process(priv->txch, 128); 458df828598SMugunthan V N num_rx = cpdma_chan_process(priv->rxch, budget); 459df828598SMugunthan V N 460df828598SMugunthan V N if (num_rx || num_tx) 461df828598SMugunthan V N cpsw_dbg(priv, intr, "poll %d rx, %d tx pkts\n", 462df828598SMugunthan V N num_rx, num_tx); 463df828598SMugunthan V N 464df828598SMugunthan V N if (num_rx < budget) { 465df828598SMugunthan V N napi_complete(napi); 466df828598SMugunthan V N cpsw_intr_enable(priv); 467df828598SMugunthan V N cpdma_ctlr_eoi(priv->dma); 468df828598SMugunthan V N cpsw_enable_irq(priv); 469df828598SMugunthan V N } 470df828598SMugunthan V N 471df828598SMugunthan V N return num_rx; 472df828598SMugunthan V N } 473df828598SMugunthan V N 474df828598SMugunthan V N static inline void soft_reset(const char *module, void __iomem *reg) 475df828598SMugunthan V N { 476df828598SMugunthan V N unsigned long timeout = jiffies + HZ; 477df828598SMugunthan V N 478df828598SMugunthan V N __raw_writel(1, reg); 479df828598SMugunthan V N do { 480df828598SMugunthan V N cpu_relax(); 481df828598SMugunthan V N } while ((__raw_readl(reg) & 1) && time_after(timeout, jiffies)); 482df828598SMugunthan V N 483df828598SMugunthan V N WARN(__raw_readl(reg) & 1, "failed to soft-reset %s\n", module); 484df828598SMugunthan V N } 485df828598SMugunthan V N 486df828598SMugunthan V N #define mac_hi(mac) (((mac)[0] << 0) | ((mac)[1] << 8) | \ 487df828598SMugunthan V N ((mac)[2] << 16) | ((mac)[3] << 24)) 488df828598SMugunthan V N #define mac_lo(mac) (((mac)[4] << 0) | ((mac)[5] << 8)) 489df828598SMugunthan V N 490df828598SMugunthan V N static void cpsw_set_slave_mac(struct cpsw_slave *slave, 491df828598SMugunthan V N struct cpsw_priv *priv) 492df828598SMugunthan V N { 4939750a3adSRichard Cochran slave_write(slave, mac_hi(priv->mac_addr), SA_HI); 4949750a3adSRichard Cochran slave_write(slave, mac_lo(priv->mac_addr), SA_LO); 495df828598SMugunthan V N } 496df828598SMugunthan V N 497df828598SMugunthan V N static void _cpsw_adjust_link(struct cpsw_slave *slave, 498df828598SMugunthan V N struct cpsw_priv *priv, bool *link) 499df828598SMugunthan V N { 500df828598SMugunthan V N struct phy_device *phy = slave->phy; 501df828598SMugunthan V N u32 mac_control = 0; 502df828598SMugunthan V N u32 slave_port; 503df828598SMugunthan V N 504df828598SMugunthan V N if (!phy) 505df828598SMugunthan V N return; 506df828598SMugunthan V N 507df828598SMugunthan V N slave_port = cpsw_get_slave_port(priv, slave->slave_num); 508df828598SMugunthan V N 509df828598SMugunthan V N if (phy->link) { 510df828598SMugunthan V N mac_control = priv->data.mac_control; 511df828598SMugunthan V N 512df828598SMugunthan V N /* enable forwarding */ 513df828598SMugunthan V N cpsw_ale_control_set(priv->ale, slave_port, 514df828598SMugunthan V N ALE_PORT_STATE, ALE_PORT_STATE_FORWARD); 515df828598SMugunthan V N 516df828598SMugunthan V N if (phy->speed == 1000) 517df828598SMugunthan V N mac_control |= BIT(7); /* GIGABITEN */ 518df828598SMugunthan V N if (phy->duplex) 519df828598SMugunthan V N mac_control |= BIT(0); /* FULLDUPLEXEN */ 520342b7b74SDaniel Mack 521342b7b74SDaniel Mack /* set speed_in input in case RMII mode is used in 100Mbps */ 522342b7b74SDaniel Mack if (phy->speed == 100) 523342b7b74SDaniel Mack mac_control |= BIT(15); 524342b7b74SDaniel Mack 525df828598SMugunthan V N *link = true; 526df828598SMugunthan V N } else { 527df828598SMugunthan V N mac_control = 0; 528df828598SMugunthan V N /* disable forwarding */ 529df828598SMugunthan V N cpsw_ale_control_set(priv->ale, slave_port, 530df828598SMugunthan V N ALE_PORT_STATE, ALE_PORT_STATE_DISABLE); 531df828598SMugunthan V N } 532df828598SMugunthan V N 533df828598SMugunthan V N if (mac_control != slave->mac_control) { 534df828598SMugunthan V N phy_print_status(phy); 535df828598SMugunthan V N __raw_writel(mac_control, &slave->sliver->mac_control); 536df828598SMugunthan V N } 537df828598SMugunthan V N 538df828598SMugunthan V N slave->mac_control = mac_control; 539df828598SMugunthan V N } 540df828598SMugunthan V N 541df828598SMugunthan V N static void cpsw_adjust_link(struct net_device *ndev) 542df828598SMugunthan V N { 543df828598SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 544df828598SMugunthan V N bool link = false; 545df828598SMugunthan V N 546df828598SMugunthan V N for_each_slave(priv, _cpsw_adjust_link, priv, &link); 547df828598SMugunthan V N 548df828598SMugunthan V N if (link) { 549df828598SMugunthan V N netif_carrier_on(ndev); 550df828598SMugunthan V N if (netif_running(ndev)) 551df828598SMugunthan V N netif_wake_queue(ndev); 552df828598SMugunthan V N } else { 553df828598SMugunthan V N netif_carrier_off(ndev); 554df828598SMugunthan V N netif_stop_queue(ndev); 555df828598SMugunthan V N } 556df828598SMugunthan V N } 557df828598SMugunthan V N 558df828598SMugunthan V N static inline int __show_stat(char *buf, int maxlen, const char *name, u32 val) 559df828598SMugunthan V N { 560df828598SMugunthan V N static char *leader = "........................................"; 561df828598SMugunthan V N 562df828598SMugunthan V N if (!val) 563df828598SMugunthan V N return 0; 564df828598SMugunthan V N else 565df828598SMugunthan V N return snprintf(buf, maxlen, "%s %s %10d\n", name, 566df828598SMugunthan V N leader + strlen(name), val); 567df828598SMugunthan V N } 568df828598SMugunthan V N 569df828598SMugunthan V N static void cpsw_slave_open(struct cpsw_slave *slave, struct cpsw_priv *priv) 570df828598SMugunthan V N { 571df828598SMugunthan V N char name[32]; 572df828598SMugunthan V N u32 slave_port; 573df828598SMugunthan V N 574df828598SMugunthan V N sprintf(name, "slave-%d", slave->slave_num); 575df828598SMugunthan V N 576df828598SMugunthan V N soft_reset(name, &slave->sliver->soft_reset); 577df828598SMugunthan V N 578df828598SMugunthan V N /* setup priority mapping */ 579df828598SMugunthan V N __raw_writel(RX_PRIORITY_MAPPING, &slave->sliver->rx_pri_map); 5809750a3adSRichard Cochran 5819750a3adSRichard Cochran switch (priv->version) { 5829750a3adSRichard Cochran case CPSW_VERSION_1: 5839750a3adSRichard Cochran slave_write(slave, TX_PRIORITY_MAPPING, CPSW1_TX_PRI_MAP); 5849750a3adSRichard Cochran break; 5859750a3adSRichard Cochran case CPSW_VERSION_2: 5869750a3adSRichard Cochran slave_write(slave, TX_PRIORITY_MAPPING, CPSW2_TX_PRI_MAP); 5879750a3adSRichard Cochran break; 5889750a3adSRichard Cochran } 589df828598SMugunthan V N 590df828598SMugunthan V N /* setup max packet size, and mac address */ 591df828598SMugunthan V N __raw_writel(priv->rx_packet_max, &slave->sliver->rx_maxlen); 592df828598SMugunthan V N cpsw_set_slave_mac(slave, priv); 593df828598SMugunthan V N 594df828598SMugunthan V N slave->mac_control = 0; /* no link yet */ 595df828598SMugunthan V N 596df828598SMugunthan V N slave_port = cpsw_get_slave_port(priv, slave->slave_num); 597df828598SMugunthan V N 598df828598SMugunthan V N cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast, 599e11b220fSMugunthan V N 1 << slave_port, 0, 0, ALE_MCAST_FWD_2); 600df828598SMugunthan V N 601df828598SMugunthan V N slave->phy = phy_connect(priv->ndev, slave->data->phy_id, 602f9a8f83bSFlorian Fainelli &cpsw_adjust_link, slave->data->phy_if); 603df828598SMugunthan V N if (IS_ERR(slave->phy)) { 604df828598SMugunthan V N dev_err(priv->dev, "phy %s not found on slave %d\n", 605df828598SMugunthan V N slave->data->phy_id, slave->slave_num); 606df828598SMugunthan V N slave->phy = NULL; 607df828598SMugunthan V N } else { 608df828598SMugunthan V N dev_info(priv->dev, "phy found : id is : 0x%x\n", 609df828598SMugunthan V N slave->phy->phy_id); 610df828598SMugunthan V N phy_start(slave->phy); 611df828598SMugunthan V N } 612df828598SMugunthan V N } 613df828598SMugunthan V N 6143b72c2feSMugunthan V N static inline void cpsw_add_default_vlan(struct cpsw_priv *priv) 6153b72c2feSMugunthan V N { 6163b72c2feSMugunthan V N const int vlan = priv->data.default_vlan; 6173b72c2feSMugunthan V N const int port = priv->host_port; 6183b72c2feSMugunthan V N u32 reg; 6193b72c2feSMugunthan V N int i; 6203b72c2feSMugunthan V N 6213b72c2feSMugunthan V N reg = (priv->version == CPSW_VERSION_1) ? CPSW1_PORT_VLAN : 6223b72c2feSMugunthan V N CPSW2_PORT_VLAN; 6233b72c2feSMugunthan V N 6243b72c2feSMugunthan V N writel(vlan, &priv->host_port_regs->port_vlan); 6253b72c2feSMugunthan V N 6263b72c2feSMugunthan V N for (i = 0; i < 2; i++) 6273b72c2feSMugunthan V N slave_write(priv->slaves + i, vlan, reg); 6283b72c2feSMugunthan V N 6293b72c2feSMugunthan V N cpsw_ale_add_vlan(priv->ale, vlan, ALE_ALL_PORTS << port, 6303b72c2feSMugunthan V N ALE_ALL_PORTS << port, ALE_ALL_PORTS << port, 6313b72c2feSMugunthan V N (ALE_PORT_1 | ALE_PORT_2) << port); 6323b72c2feSMugunthan V N } 6333b72c2feSMugunthan V N 634df828598SMugunthan V N static void cpsw_init_host_port(struct cpsw_priv *priv) 635df828598SMugunthan V N { 6363b72c2feSMugunthan V N u32 control_reg; 6373b72c2feSMugunthan V N 638df828598SMugunthan V N /* soft reset the controller and initialize ale */ 639df828598SMugunthan V N soft_reset("cpsw", &priv->regs->soft_reset); 640df828598SMugunthan V N cpsw_ale_start(priv->ale); 641df828598SMugunthan V N 642df828598SMugunthan V N /* switch to vlan unaware mode */ 6433b72c2feSMugunthan V N cpsw_ale_control_set(priv->ale, priv->host_port, ALE_VLAN_AWARE, 6443b72c2feSMugunthan V N CPSW_ALE_VLAN_AWARE); 6453b72c2feSMugunthan V N control_reg = readl(&priv->regs->control); 6463b72c2feSMugunthan V N control_reg |= CPSW_VLAN_AWARE; 6473b72c2feSMugunthan V N writel(control_reg, &priv->regs->control); 648df828598SMugunthan V N 649df828598SMugunthan V N /* setup host port priority mapping */ 650df828598SMugunthan V N __raw_writel(CPDMA_TX_PRIORITY_MAP, 651df828598SMugunthan V N &priv->host_port_regs->cpdma_tx_pri_map); 652df828598SMugunthan V N __raw_writel(0, &priv->host_port_regs->cpdma_rx_chan_map); 653df828598SMugunthan V N 654df828598SMugunthan V N cpsw_ale_control_set(priv->ale, priv->host_port, 655df828598SMugunthan V N ALE_PORT_STATE, ALE_PORT_STATE_FORWARD); 656df828598SMugunthan V N 657e11b220fSMugunthan V N cpsw_ale_add_ucast(priv->ale, priv->mac_addr, priv->host_port, 0, 0); 658df828598SMugunthan V N cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast, 659e11b220fSMugunthan V N 1 << priv->host_port, 0, 0, ALE_MCAST_FWD_2); 660df828598SMugunthan V N } 661df828598SMugunthan V N 662df828598SMugunthan V N static int cpsw_ndo_open(struct net_device *ndev) 663df828598SMugunthan V N { 664df828598SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 665df828598SMugunthan V N int i, ret; 666df828598SMugunthan V N u32 reg; 667df828598SMugunthan V N 668df828598SMugunthan V N cpsw_intr_disable(priv); 669df828598SMugunthan V N netif_carrier_off(ndev); 670df828598SMugunthan V N 671f150bd7fSMugunthan V N pm_runtime_get_sync(&priv->pdev->dev); 672df828598SMugunthan V N 673549985eeSRichard Cochran reg = priv->version; 674df828598SMugunthan V N 675df828598SMugunthan V N dev_info(priv->dev, "initializing cpsw version %d.%d (%d)\n", 676df828598SMugunthan V N CPSW_MAJOR_VERSION(reg), CPSW_MINOR_VERSION(reg), 677df828598SMugunthan V N CPSW_RTL_VERSION(reg)); 678df828598SMugunthan V N 679df828598SMugunthan V N /* initialize host and slave ports */ 680df828598SMugunthan V N cpsw_init_host_port(priv); 681df828598SMugunthan V N for_each_slave(priv, cpsw_slave_open, priv); 682df828598SMugunthan V N 6833b72c2feSMugunthan V N /* Add default VLAN */ 6843b72c2feSMugunthan V N cpsw_add_default_vlan(priv); 6853b72c2feSMugunthan V N 686df828598SMugunthan V N /* setup tx dma to fixed prio and zero offset */ 687df828598SMugunthan V N cpdma_control_set(priv->dma, CPDMA_TX_PRIO_FIXED, 1); 688df828598SMugunthan V N cpdma_control_set(priv->dma, CPDMA_RX_BUFFER_OFFSET, 0); 689df828598SMugunthan V N 690df828598SMugunthan V N /* disable priority elevation and enable statistics on all ports */ 691df828598SMugunthan V N __raw_writel(0, &priv->regs->ptype); 692df828598SMugunthan V N 693df828598SMugunthan V N /* enable statistics collection only on the host port */ 694df828598SMugunthan V N __raw_writel(0x7, &priv->regs->stat_port_en); 695df828598SMugunthan V N 696df828598SMugunthan V N if (WARN_ON(!priv->data.rx_descs)) 697df828598SMugunthan V N priv->data.rx_descs = 128; 698df828598SMugunthan V N 699df828598SMugunthan V N for (i = 0; i < priv->data.rx_descs; i++) { 700df828598SMugunthan V N struct sk_buff *skb; 701df828598SMugunthan V N 702df828598SMugunthan V N ret = -ENOMEM; 703df828598SMugunthan V N skb = netdev_alloc_skb_ip_align(priv->ndev, 704df828598SMugunthan V N priv->rx_packet_max); 705df828598SMugunthan V N if (!skb) 706df828598SMugunthan V N break; 707df828598SMugunthan V N ret = cpdma_chan_submit(priv->rxch, skb, skb->data, 708f6e135c8SMugunthan V N skb_tailroom(skb), 0, GFP_KERNEL); 709df828598SMugunthan V N if (WARN_ON(ret < 0)) 710df828598SMugunthan V N break; 711df828598SMugunthan V N } 712df828598SMugunthan V N /* continue even if we didn't manage to submit all receive descs */ 713df828598SMugunthan V N cpsw_info(priv, ifup, "submitted %d rx descriptors\n", i); 714df828598SMugunthan V N 715df828598SMugunthan V N cpdma_ctlr_start(priv->dma); 716df828598SMugunthan V N cpsw_intr_enable(priv); 717df828598SMugunthan V N napi_enable(&priv->napi); 718df828598SMugunthan V N cpdma_ctlr_eoi(priv->dma); 719df828598SMugunthan V N 720df828598SMugunthan V N return 0; 721df828598SMugunthan V N } 722df828598SMugunthan V N 723df828598SMugunthan V N static void cpsw_slave_stop(struct cpsw_slave *slave, struct cpsw_priv *priv) 724df828598SMugunthan V N { 725df828598SMugunthan V N if (!slave->phy) 726df828598SMugunthan V N return; 727df828598SMugunthan V N phy_stop(slave->phy); 728df828598SMugunthan V N phy_disconnect(slave->phy); 729df828598SMugunthan V N slave->phy = NULL; 730df828598SMugunthan V N } 731df828598SMugunthan V N 732df828598SMugunthan V N static int cpsw_ndo_stop(struct net_device *ndev) 733df828598SMugunthan V N { 734df828598SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 735df828598SMugunthan V N 736df828598SMugunthan V N cpsw_info(priv, ifdown, "shutting down cpsw device\n"); 737df828598SMugunthan V N netif_stop_queue(priv->ndev); 738df828598SMugunthan V N napi_disable(&priv->napi); 739df828598SMugunthan V N netif_carrier_off(priv->ndev); 74071380f9bSMugunthan V N cpsw_intr_disable(priv); 74171380f9bSMugunthan V N cpdma_ctlr_int_ctrl(priv->dma, false); 74271380f9bSMugunthan V N cpdma_ctlr_stop(priv->dma); 743df828598SMugunthan V N cpsw_ale_stop(priv->ale); 744df828598SMugunthan V N for_each_slave(priv, cpsw_slave_stop, priv); 745f150bd7fSMugunthan V N pm_runtime_put_sync(&priv->pdev->dev); 746df828598SMugunthan V N return 0; 747df828598SMugunthan V N } 748df828598SMugunthan V N 749df828598SMugunthan V N static netdev_tx_t cpsw_ndo_start_xmit(struct sk_buff *skb, 750df828598SMugunthan V N struct net_device *ndev) 751df828598SMugunthan V N { 752df828598SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 753df828598SMugunthan V N int ret; 754df828598SMugunthan V N 755df828598SMugunthan V N ndev->trans_start = jiffies; 756df828598SMugunthan V N 757df828598SMugunthan V N if (skb_padto(skb, CPSW_MIN_PACKET_SIZE)) { 758df828598SMugunthan V N cpsw_err(priv, tx_err, "packet pad failed\n"); 759df828598SMugunthan V N priv->stats.tx_dropped++; 760df828598SMugunthan V N return NETDEV_TX_OK; 761df828598SMugunthan V N } 762df828598SMugunthan V N 7632e5b38abSRichard Cochran if (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP && priv->cpts.tx_enable) 7642e5b38abSRichard Cochran skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 7652e5b38abSRichard Cochran 7662e5b38abSRichard Cochran skb_tx_timestamp(skb); 7672e5b38abSRichard Cochran 768df828598SMugunthan V N ret = cpdma_chan_submit(priv->txch, skb, skb->data, 769f6e135c8SMugunthan V N skb->len, 0, GFP_KERNEL); 770df828598SMugunthan V N if (unlikely(ret != 0)) { 771df828598SMugunthan V N cpsw_err(priv, tx_err, "desc submit failed\n"); 772df828598SMugunthan V N goto fail; 773df828598SMugunthan V N } 774df828598SMugunthan V N 775fae50823SMugunthan V N /* If there is no more tx desc left free then we need to 776fae50823SMugunthan V N * tell the kernel to stop sending us tx frames. 777fae50823SMugunthan V N */ 778fae50823SMugunthan V N if (unlikely(cpdma_check_free_tx_desc(priv->txch))) 779fae50823SMugunthan V N netif_stop_queue(ndev); 780fae50823SMugunthan V N 781df828598SMugunthan V N return NETDEV_TX_OK; 782df828598SMugunthan V N fail: 783df828598SMugunthan V N priv->stats.tx_dropped++; 784df828598SMugunthan V N netif_stop_queue(ndev); 785df828598SMugunthan V N return NETDEV_TX_BUSY; 786df828598SMugunthan V N } 787df828598SMugunthan V N 788df828598SMugunthan V N static void cpsw_ndo_change_rx_flags(struct net_device *ndev, int flags) 789df828598SMugunthan V N { 790df828598SMugunthan V N /* 791df828598SMugunthan V N * The switch cannot operate in promiscuous mode without substantial 792df828598SMugunthan V N * headache. For promiscuous mode to work, we would need to put the 793df828598SMugunthan V N * ALE in bypass mode and route all traffic to the host port. 794df828598SMugunthan V N * Subsequently, the host will need to operate as a "bridge", learn, 795df828598SMugunthan V N * and flood as needed. For now, we simply complain here and 796df828598SMugunthan V N * do nothing about it :-) 797df828598SMugunthan V N */ 798df828598SMugunthan V N if ((flags & IFF_PROMISC) && (ndev->flags & IFF_PROMISC)) 799df828598SMugunthan V N dev_err(&ndev->dev, "promiscuity ignored!\n"); 800df828598SMugunthan V N 801df828598SMugunthan V N /* 802df828598SMugunthan V N * The switch cannot filter multicast traffic unless it is configured 803df828598SMugunthan V N * in "VLAN Aware" mode. Unfortunately, VLAN awareness requires a 804df828598SMugunthan V N * whole bunch of additional logic that this driver does not implement 805df828598SMugunthan V N * at present. 806df828598SMugunthan V N */ 807df828598SMugunthan V N if ((flags & IFF_ALLMULTI) && !(ndev->flags & IFF_ALLMULTI)) 808df828598SMugunthan V N dev_err(&ndev->dev, "multicast traffic cannot be filtered!\n"); 809df828598SMugunthan V N } 810df828598SMugunthan V N 8112e5b38abSRichard Cochran #ifdef CONFIG_TI_CPTS 8122e5b38abSRichard Cochran 8132e5b38abSRichard Cochran static void cpsw_hwtstamp_v1(struct cpsw_priv *priv) 8142e5b38abSRichard Cochran { 8152e5b38abSRichard Cochran struct cpsw_slave *slave = &priv->slaves[priv->data.cpts_active_slave]; 8162e5b38abSRichard Cochran u32 ts_en, seq_id; 8172e5b38abSRichard Cochran 8182e5b38abSRichard Cochran if (!priv->cpts.tx_enable && !priv->cpts.rx_enable) { 8192e5b38abSRichard Cochran slave_write(slave, 0, CPSW1_TS_CTL); 8202e5b38abSRichard Cochran return; 8212e5b38abSRichard Cochran } 8222e5b38abSRichard Cochran 8232e5b38abSRichard Cochran seq_id = (30 << CPSW_V1_SEQ_ID_OFS_SHIFT) | ETH_P_1588; 8242e5b38abSRichard Cochran ts_en = EVENT_MSG_BITS << CPSW_V1_MSG_TYPE_OFS; 8252e5b38abSRichard Cochran 8262e5b38abSRichard Cochran if (priv->cpts.tx_enable) 8272e5b38abSRichard Cochran ts_en |= CPSW_V1_TS_TX_EN; 8282e5b38abSRichard Cochran 8292e5b38abSRichard Cochran if (priv->cpts.rx_enable) 8302e5b38abSRichard Cochran ts_en |= CPSW_V1_TS_RX_EN; 8312e5b38abSRichard Cochran 8322e5b38abSRichard Cochran slave_write(slave, ts_en, CPSW1_TS_CTL); 8332e5b38abSRichard Cochran slave_write(slave, seq_id, CPSW1_TS_SEQ_LTYPE); 8342e5b38abSRichard Cochran } 8352e5b38abSRichard Cochran 8362e5b38abSRichard Cochran static void cpsw_hwtstamp_v2(struct cpsw_priv *priv) 8372e5b38abSRichard Cochran { 8382e5b38abSRichard Cochran struct cpsw_slave *slave = &priv->slaves[priv->data.cpts_active_slave]; 8392e5b38abSRichard Cochran u32 ctrl, mtype; 8402e5b38abSRichard Cochran 8412e5b38abSRichard Cochran ctrl = slave_read(slave, CPSW2_CONTROL); 8422e5b38abSRichard Cochran ctrl &= ~CTRL_ALL_TS_MASK; 8432e5b38abSRichard Cochran 8442e5b38abSRichard Cochran if (priv->cpts.tx_enable) 8452e5b38abSRichard Cochran ctrl |= CTRL_TX_TS_BITS; 8462e5b38abSRichard Cochran 8472e5b38abSRichard Cochran if (priv->cpts.rx_enable) 8482e5b38abSRichard Cochran ctrl |= CTRL_RX_TS_BITS; 8492e5b38abSRichard Cochran 8502e5b38abSRichard Cochran mtype = (30 << TS_SEQ_ID_OFFSET_SHIFT) | EVENT_MSG_BITS; 8512e5b38abSRichard Cochran 8522e5b38abSRichard Cochran slave_write(slave, mtype, CPSW2_TS_SEQ_MTYPE); 8532e5b38abSRichard Cochran slave_write(slave, ctrl, CPSW2_CONTROL); 8542e5b38abSRichard Cochran __raw_writel(ETH_P_1588, &priv->regs->ts_ltype); 8552e5b38abSRichard Cochran } 8562e5b38abSRichard Cochran 8573177bf6fSMugunthan V N static int cpsw_hwtstamp_ioctl(struct net_device *dev, struct ifreq *ifr) 8582e5b38abSRichard Cochran { 8593177bf6fSMugunthan V N struct cpsw_priv *priv = netdev_priv(dev); 8602e5b38abSRichard Cochran struct cpts *cpts = &priv->cpts; 8612e5b38abSRichard Cochran struct hwtstamp_config cfg; 8622e5b38abSRichard Cochran 8632e5b38abSRichard Cochran if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg))) 8642e5b38abSRichard Cochran return -EFAULT; 8652e5b38abSRichard Cochran 8662e5b38abSRichard Cochran /* reserved for future extensions */ 8672e5b38abSRichard Cochran if (cfg.flags) 8682e5b38abSRichard Cochran return -EINVAL; 8692e5b38abSRichard Cochran 8702e5b38abSRichard Cochran switch (cfg.tx_type) { 8712e5b38abSRichard Cochran case HWTSTAMP_TX_OFF: 8722e5b38abSRichard Cochran cpts->tx_enable = 0; 8732e5b38abSRichard Cochran break; 8742e5b38abSRichard Cochran case HWTSTAMP_TX_ON: 8752e5b38abSRichard Cochran cpts->tx_enable = 1; 8762e5b38abSRichard Cochran break; 8772e5b38abSRichard Cochran default: 8782e5b38abSRichard Cochran return -ERANGE; 8792e5b38abSRichard Cochran } 8802e5b38abSRichard Cochran 8812e5b38abSRichard Cochran switch (cfg.rx_filter) { 8822e5b38abSRichard Cochran case HWTSTAMP_FILTER_NONE: 8832e5b38abSRichard Cochran cpts->rx_enable = 0; 8842e5b38abSRichard Cochran break; 8852e5b38abSRichard Cochran case HWTSTAMP_FILTER_ALL: 8862e5b38abSRichard Cochran case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: 8872e5b38abSRichard Cochran case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: 8882e5b38abSRichard Cochran case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: 8892e5b38abSRichard Cochran return -ERANGE; 8902e5b38abSRichard Cochran case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: 8912e5b38abSRichard Cochran case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 8922e5b38abSRichard Cochran case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 8932e5b38abSRichard Cochran case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: 8942e5b38abSRichard Cochran case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: 8952e5b38abSRichard Cochran case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: 8962e5b38abSRichard Cochran case HWTSTAMP_FILTER_PTP_V2_EVENT: 8972e5b38abSRichard Cochran case HWTSTAMP_FILTER_PTP_V2_SYNC: 8982e5b38abSRichard Cochran case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 8992e5b38abSRichard Cochran cpts->rx_enable = 1; 9002e5b38abSRichard Cochran cfg.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT; 9012e5b38abSRichard Cochran break; 9022e5b38abSRichard Cochran default: 9032e5b38abSRichard Cochran return -ERANGE; 9042e5b38abSRichard Cochran } 9052e5b38abSRichard Cochran 9062e5b38abSRichard Cochran switch (priv->version) { 9072e5b38abSRichard Cochran case CPSW_VERSION_1: 9082e5b38abSRichard Cochran cpsw_hwtstamp_v1(priv); 9092e5b38abSRichard Cochran break; 9102e5b38abSRichard Cochran case CPSW_VERSION_2: 9112e5b38abSRichard Cochran cpsw_hwtstamp_v2(priv); 9122e5b38abSRichard Cochran break; 9132e5b38abSRichard Cochran default: 9142e5b38abSRichard Cochran return -ENOTSUPP; 9152e5b38abSRichard Cochran } 9162e5b38abSRichard Cochran 9172e5b38abSRichard Cochran return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0; 9182e5b38abSRichard Cochran } 9192e5b38abSRichard Cochran 9202e5b38abSRichard Cochran #endif /*CONFIG_TI_CPTS*/ 9212e5b38abSRichard Cochran 9222e5b38abSRichard Cochran static int cpsw_ndo_ioctl(struct net_device *dev, struct ifreq *req, int cmd) 9232e5b38abSRichard Cochran { 9242e5b38abSRichard Cochran if (!netif_running(dev)) 9252e5b38abSRichard Cochran return -EINVAL; 9262e5b38abSRichard Cochran 9272e5b38abSRichard Cochran #ifdef CONFIG_TI_CPTS 9282e5b38abSRichard Cochran if (cmd == SIOCSHWTSTAMP) 9293177bf6fSMugunthan V N return cpsw_hwtstamp_ioctl(dev, req); 9302e5b38abSRichard Cochran #endif 9312e5b38abSRichard Cochran return -ENOTSUPP; 9322e5b38abSRichard Cochran } 9332e5b38abSRichard Cochran 934df828598SMugunthan V N static void cpsw_ndo_tx_timeout(struct net_device *ndev) 935df828598SMugunthan V N { 936df828598SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 937df828598SMugunthan V N 938df828598SMugunthan V N cpsw_err(priv, tx_err, "transmit timeout, restarting dma\n"); 939df828598SMugunthan V N priv->stats.tx_errors++; 940df828598SMugunthan V N cpsw_intr_disable(priv); 941df828598SMugunthan V N cpdma_ctlr_int_ctrl(priv->dma, false); 942df828598SMugunthan V N cpdma_chan_stop(priv->txch); 943df828598SMugunthan V N cpdma_chan_start(priv->txch); 944df828598SMugunthan V N cpdma_ctlr_int_ctrl(priv->dma, true); 945df828598SMugunthan V N cpsw_intr_enable(priv); 946df828598SMugunthan V N cpdma_ctlr_eoi(priv->dma); 947df828598SMugunthan V N } 948df828598SMugunthan V N 949df828598SMugunthan V N static struct net_device_stats *cpsw_ndo_get_stats(struct net_device *ndev) 950df828598SMugunthan V N { 951df828598SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 952df828598SMugunthan V N return &priv->stats; 953df828598SMugunthan V N } 954df828598SMugunthan V N 955df828598SMugunthan V N #ifdef CONFIG_NET_POLL_CONTROLLER 956df828598SMugunthan V N static void cpsw_ndo_poll_controller(struct net_device *ndev) 957df828598SMugunthan V N { 958df828598SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 959df828598SMugunthan V N 960df828598SMugunthan V N cpsw_intr_disable(priv); 961df828598SMugunthan V N cpdma_ctlr_int_ctrl(priv->dma, false); 962df828598SMugunthan V N cpsw_interrupt(ndev->irq, priv); 963df828598SMugunthan V N cpdma_ctlr_int_ctrl(priv->dma, true); 964df828598SMugunthan V N cpsw_intr_enable(priv); 965df828598SMugunthan V N cpdma_ctlr_eoi(priv->dma); 966df828598SMugunthan V N } 967df828598SMugunthan V N #endif 968df828598SMugunthan V N 9693b72c2feSMugunthan V N static inline int cpsw_add_vlan_ale_entry(struct cpsw_priv *priv, 9703b72c2feSMugunthan V N unsigned short vid) 9713b72c2feSMugunthan V N { 9723b72c2feSMugunthan V N int ret; 9733b72c2feSMugunthan V N 9743b72c2feSMugunthan V N ret = cpsw_ale_add_vlan(priv->ale, vid, 9753b72c2feSMugunthan V N ALE_ALL_PORTS << priv->host_port, 9763b72c2feSMugunthan V N 0, ALE_ALL_PORTS << priv->host_port, 9773b72c2feSMugunthan V N (ALE_PORT_1 | ALE_PORT_2) << priv->host_port); 9783b72c2feSMugunthan V N if (ret != 0) 9793b72c2feSMugunthan V N return ret; 9803b72c2feSMugunthan V N 9813b72c2feSMugunthan V N ret = cpsw_ale_add_ucast(priv->ale, priv->mac_addr, 9823b72c2feSMugunthan V N priv->host_port, ALE_VLAN, vid); 9833b72c2feSMugunthan V N if (ret != 0) 9843b72c2feSMugunthan V N goto clean_vid; 9853b72c2feSMugunthan V N 9863b72c2feSMugunthan V N ret = cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast, 9873b72c2feSMugunthan V N ALE_ALL_PORTS << priv->host_port, 9883b72c2feSMugunthan V N ALE_VLAN, vid, 0); 9893b72c2feSMugunthan V N if (ret != 0) 9903b72c2feSMugunthan V N goto clean_vlan_ucast; 9913b72c2feSMugunthan V N return 0; 9923b72c2feSMugunthan V N 9933b72c2feSMugunthan V N clean_vlan_ucast: 9943b72c2feSMugunthan V N cpsw_ale_del_ucast(priv->ale, priv->mac_addr, 9953b72c2feSMugunthan V N priv->host_port, ALE_VLAN, vid); 9963b72c2feSMugunthan V N clean_vid: 9973b72c2feSMugunthan V N cpsw_ale_del_vlan(priv->ale, vid, 0); 9983b72c2feSMugunthan V N return ret; 9993b72c2feSMugunthan V N } 10003b72c2feSMugunthan V N 10013b72c2feSMugunthan V N static int cpsw_ndo_vlan_rx_add_vid(struct net_device *ndev, 10023b72c2feSMugunthan V N unsigned short vid) 10033b72c2feSMugunthan V N { 10043b72c2feSMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 10053b72c2feSMugunthan V N 10063b72c2feSMugunthan V N if (vid == priv->data.default_vlan) 10073b72c2feSMugunthan V N return 0; 10083b72c2feSMugunthan V N 10093b72c2feSMugunthan V N dev_info(priv->dev, "Adding vlanid %d to vlan filter\n", vid); 10103b72c2feSMugunthan V N return cpsw_add_vlan_ale_entry(priv, vid); 10113b72c2feSMugunthan V N } 10123b72c2feSMugunthan V N 10133b72c2feSMugunthan V N static int cpsw_ndo_vlan_rx_kill_vid(struct net_device *ndev, 10143b72c2feSMugunthan V N unsigned short vid) 10153b72c2feSMugunthan V N { 10163b72c2feSMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 10173b72c2feSMugunthan V N int ret; 10183b72c2feSMugunthan V N 10193b72c2feSMugunthan V N if (vid == priv->data.default_vlan) 10203b72c2feSMugunthan V N return 0; 10213b72c2feSMugunthan V N 10223b72c2feSMugunthan V N dev_info(priv->dev, "removing vlanid %d from vlan filter\n", vid); 10233b72c2feSMugunthan V N ret = cpsw_ale_del_vlan(priv->ale, vid, 0); 10243b72c2feSMugunthan V N if (ret != 0) 10253b72c2feSMugunthan V N return ret; 10263b72c2feSMugunthan V N 10273b72c2feSMugunthan V N ret = cpsw_ale_del_ucast(priv->ale, priv->mac_addr, 10283b72c2feSMugunthan V N priv->host_port, ALE_VLAN, vid); 10293b72c2feSMugunthan V N if (ret != 0) 10303b72c2feSMugunthan V N return ret; 10313b72c2feSMugunthan V N 10323b72c2feSMugunthan V N return cpsw_ale_del_mcast(priv->ale, priv->ndev->broadcast, 10333b72c2feSMugunthan V N 0, ALE_VLAN, vid); 10343b72c2feSMugunthan V N } 10353b72c2feSMugunthan V N 1036df828598SMugunthan V N static const struct net_device_ops cpsw_netdev_ops = { 1037df828598SMugunthan V N .ndo_open = cpsw_ndo_open, 1038df828598SMugunthan V N .ndo_stop = cpsw_ndo_stop, 1039df828598SMugunthan V N .ndo_start_xmit = cpsw_ndo_start_xmit, 1040df828598SMugunthan V N .ndo_change_rx_flags = cpsw_ndo_change_rx_flags, 10412e5b38abSRichard Cochran .ndo_do_ioctl = cpsw_ndo_ioctl, 1042df828598SMugunthan V N .ndo_validate_addr = eth_validate_addr, 10435c473ed2SDavid S. Miller .ndo_change_mtu = eth_change_mtu, 1044df828598SMugunthan V N .ndo_tx_timeout = cpsw_ndo_tx_timeout, 1045df828598SMugunthan V N .ndo_get_stats = cpsw_ndo_get_stats, 10465c50a856SMugunthan V N .ndo_set_rx_mode = cpsw_ndo_set_rx_mode, 1047df828598SMugunthan V N #ifdef CONFIG_NET_POLL_CONTROLLER 1048df828598SMugunthan V N .ndo_poll_controller = cpsw_ndo_poll_controller, 1049df828598SMugunthan V N #endif 10503b72c2feSMugunthan V N .ndo_vlan_rx_add_vid = cpsw_ndo_vlan_rx_add_vid, 10513b72c2feSMugunthan V N .ndo_vlan_rx_kill_vid = cpsw_ndo_vlan_rx_kill_vid, 1052df828598SMugunthan V N }; 1053df828598SMugunthan V N 1054df828598SMugunthan V N static void cpsw_get_drvinfo(struct net_device *ndev, 1055df828598SMugunthan V N struct ethtool_drvinfo *info) 1056df828598SMugunthan V N { 1057df828598SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 10587826d43fSJiri Pirko 10597826d43fSJiri Pirko strlcpy(info->driver, "TI CPSW Driver v1.0", sizeof(info->driver)); 10607826d43fSJiri Pirko strlcpy(info->version, "1.0", sizeof(info->version)); 10617826d43fSJiri Pirko strlcpy(info->bus_info, priv->pdev->name, sizeof(info->bus_info)); 1062df828598SMugunthan V N } 1063df828598SMugunthan V N 1064df828598SMugunthan V N static u32 cpsw_get_msglevel(struct net_device *ndev) 1065df828598SMugunthan V N { 1066df828598SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 1067df828598SMugunthan V N return priv->msg_enable; 1068df828598SMugunthan V N } 1069df828598SMugunthan V N 1070df828598SMugunthan V N static void cpsw_set_msglevel(struct net_device *ndev, u32 value) 1071df828598SMugunthan V N { 1072df828598SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 1073df828598SMugunthan V N priv->msg_enable = value; 1074df828598SMugunthan V N } 1075df828598SMugunthan V N 10762e5b38abSRichard Cochran static int cpsw_get_ts_info(struct net_device *ndev, 10772e5b38abSRichard Cochran struct ethtool_ts_info *info) 10782e5b38abSRichard Cochran { 10792e5b38abSRichard Cochran #ifdef CONFIG_TI_CPTS 10802e5b38abSRichard Cochran struct cpsw_priv *priv = netdev_priv(ndev); 10812e5b38abSRichard Cochran 10822e5b38abSRichard Cochran info->so_timestamping = 10832e5b38abSRichard Cochran SOF_TIMESTAMPING_TX_HARDWARE | 10842e5b38abSRichard Cochran SOF_TIMESTAMPING_TX_SOFTWARE | 10852e5b38abSRichard Cochran SOF_TIMESTAMPING_RX_HARDWARE | 10862e5b38abSRichard Cochran SOF_TIMESTAMPING_RX_SOFTWARE | 10872e5b38abSRichard Cochran SOF_TIMESTAMPING_SOFTWARE | 10882e5b38abSRichard Cochran SOF_TIMESTAMPING_RAW_HARDWARE; 10892e5b38abSRichard Cochran info->phc_index = priv->cpts.phc_index; 10902e5b38abSRichard Cochran info->tx_types = 10912e5b38abSRichard Cochran (1 << HWTSTAMP_TX_OFF) | 10922e5b38abSRichard Cochran (1 << HWTSTAMP_TX_ON); 10932e5b38abSRichard Cochran info->rx_filters = 10942e5b38abSRichard Cochran (1 << HWTSTAMP_FILTER_NONE) | 10952e5b38abSRichard Cochran (1 << HWTSTAMP_FILTER_PTP_V2_EVENT); 10962e5b38abSRichard Cochran #else 10972e5b38abSRichard Cochran info->so_timestamping = 10982e5b38abSRichard Cochran SOF_TIMESTAMPING_TX_SOFTWARE | 10992e5b38abSRichard Cochran SOF_TIMESTAMPING_RX_SOFTWARE | 11002e5b38abSRichard Cochran SOF_TIMESTAMPING_SOFTWARE; 11012e5b38abSRichard Cochran info->phc_index = -1; 11022e5b38abSRichard Cochran info->tx_types = 0; 11032e5b38abSRichard Cochran info->rx_filters = 0; 11042e5b38abSRichard Cochran #endif 11052e5b38abSRichard Cochran return 0; 11062e5b38abSRichard Cochran } 11072e5b38abSRichard Cochran 1108df828598SMugunthan V N static const struct ethtool_ops cpsw_ethtool_ops = { 1109df828598SMugunthan V N .get_drvinfo = cpsw_get_drvinfo, 1110df828598SMugunthan V N .get_msglevel = cpsw_get_msglevel, 1111df828598SMugunthan V N .set_msglevel = cpsw_set_msglevel, 1112df828598SMugunthan V N .get_link = ethtool_op_get_link, 11132e5b38abSRichard Cochran .get_ts_info = cpsw_get_ts_info, 1114df828598SMugunthan V N }; 1115df828598SMugunthan V N 1116549985eeSRichard Cochran static void cpsw_slave_init(struct cpsw_slave *slave, struct cpsw_priv *priv, 1117549985eeSRichard Cochran u32 slave_reg_ofs, u32 sliver_reg_ofs) 1118df828598SMugunthan V N { 1119df828598SMugunthan V N void __iomem *regs = priv->regs; 1120df828598SMugunthan V N int slave_num = slave->slave_num; 1121df828598SMugunthan V N struct cpsw_slave_data *data = priv->data.slave_data + slave_num; 1122df828598SMugunthan V N 1123df828598SMugunthan V N slave->data = data; 1124549985eeSRichard Cochran slave->regs = regs + slave_reg_ofs; 1125549985eeSRichard Cochran slave->sliver = regs + sliver_reg_ofs; 1126df828598SMugunthan V N } 1127df828598SMugunthan V N 11282eb32b0aSMugunthan V N static int cpsw_probe_dt(struct cpsw_platform_data *data, 11292eb32b0aSMugunthan V N struct platform_device *pdev) 11302eb32b0aSMugunthan V N { 11312eb32b0aSMugunthan V N struct device_node *node = pdev->dev.of_node; 11322eb32b0aSMugunthan V N struct device_node *slave_node; 11332eb32b0aSMugunthan V N int i = 0, ret; 11342eb32b0aSMugunthan V N u32 prop; 11352eb32b0aSMugunthan V N 11362eb32b0aSMugunthan V N if (!node) 11372eb32b0aSMugunthan V N return -EINVAL; 11382eb32b0aSMugunthan V N 11392eb32b0aSMugunthan V N if (of_property_read_u32(node, "slaves", &prop)) { 11402eb32b0aSMugunthan V N pr_err("Missing slaves property in the DT.\n"); 11412eb32b0aSMugunthan V N return -EINVAL; 11422eb32b0aSMugunthan V N } 11432eb32b0aSMugunthan V N data->slaves = prop; 11442eb32b0aSMugunthan V N 114578ca0b28SRichard Cochran if (of_property_read_u32(node, "cpts_active_slave", &prop)) { 114678ca0b28SRichard Cochran pr_err("Missing cpts_active_slave property in the DT.\n"); 114778ca0b28SRichard Cochran ret = -EINVAL; 114878ca0b28SRichard Cochran goto error_ret; 114978ca0b28SRichard Cochran } 115078ca0b28SRichard Cochran data->cpts_active_slave = prop; 115178ca0b28SRichard Cochran 115200ab94eeSRichard Cochran if (of_property_read_u32(node, "cpts_clock_mult", &prop)) { 115300ab94eeSRichard Cochran pr_err("Missing cpts_clock_mult property in the DT.\n"); 115400ab94eeSRichard Cochran ret = -EINVAL; 115500ab94eeSRichard Cochran goto error_ret; 115600ab94eeSRichard Cochran } 115700ab94eeSRichard Cochran data->cpts_clock_mult = prop; 115800ab94eeSRichard Cochran 115900ab94eeSRichard Cochran if (of_property_read_u32(node, "cpts_clock_shift", &prop)) { 116000ab94eeSRichard Cochran pr_err("Missing cpts_clock_shift property in the DT.\n"); 116100ab94eeSRichard Cochran ret = -EINVAL; 116200ab94eeSRichard Cochran goto error_ret; 116300ab94eeSRichard Cochran } 116400ab94eeSRichard Cochran data->cpts_clock_shift = prop; 116500ab94eeSRichard Cochran 1166b2adaca9SJoe Perches data->slave_data = kcalloc(data->slaves, sizeof(struct cpsw_slave_data), 1167b2adaca9SJoe Perches GFP_KERNEL); 1168b2adaca9SJoe Perches if (!data->slave_data) 11692eb32b0aSMugunthan V N return -EINVAL; 11702eb32b0aSMugunthan V N 11712eb32b0aSMugunthan V N if (of_property_read_u32(node, "cpdma_channels", &prop)) { 11722eb32b0aSMugunthan V N pr_err("Missing cpdma_channels property in the DT.\n"); 11732eb32b0aSMugunthan V N ret = -EINVAL; 11742eb32b0aSMugunthan V N goto error_ret; 11752eb32b0aSMugunthan V N } 11762eb32b0aSMugunthan V N data->channels = prop; 11772eb32b0aSMugunthan V N 11782eb32b0aSMugunthan V N if (of_property_read_u32(node, "ale_entries", &prop)) { 11792eb32b0aSMugunthan V N pr_err("Missing ale_entries property in the DT.\n"); 11802eb32b0aSMugunthan V N ret = -EINVAL; 11812eb32b0aSMugunthan V N goto error_ret; 11822eb32b0aSMugunthan V N } 11832eb32b0aSMugunthan V N data->ale_entries = prop; 11842eb32b0aSMugunthan V N 11852eb32b0aSMugunthan V N if (of_property_read_u32(node, "bd_ram_size", &prop)) { 11862eb32b0aSMugunthan V N pr_err("Missing bd_ram_size property in the DT.\n"); 11872eb32b0aSMugunthan V N ret = -EINVAL; 11882eb32b0aSMugunthan V N goto error_ret; 11892eb32b0aSMugunthan V N } 11902eb32b0aSMugunthan V N data->bd_ram_size = prop; 11912eb32b0aSMugunthan V N 11922eb32b0aSMugunthan V N if (of_property_read_u32(node, "rx_descs", &prop)) { 11932eb32b0aSMugunthan V N pr_err("Missing rx_descs property in the DT.\n"); 11942eb32b0aSMugunthan V N ret = -EINVAL; 11952eb32b0aSMugunthan V N goto error_ret; 11962eb32b0aSMugunthan V N } 11972eb32b0aSMugunthan V N data->rx_descs = prop; 11982eb32b0aSMugunthan V N 11992eb32b0aSMugunthan V N if (of_property_read_u32(node, "mac_control", &prop)) { 12002eb32b0aSMugunthan V N pr_err("Missing mac_control property in the DT.\n"); 12012eb32b0aSMugunthan V N ret = -EINVAL; 12022eb32b0aSMugunthan V N goto error_ret; 12032eb32b0aSMugunthan V N } 12042eb32b0aSMugunthan V N data->mac_control = prop; 12052eb32b0aSMugunthan V N 12061fb19aa7SVaibhav Hiremath /* 12071fb19aa7SVaibhav Hiremath * Populate all the child nodes here... 12081fb19aa7SVaibhav Hiremath */ 12091fb19aa7SVaibhav Hiremath ret = of_platform_populate(node, NULL, NULL, &pdev->dev); 12101fb19aa7SVaibhav Hiremath /* We do not want to force this, as in some cases may not have child */ 12111fb19aa7SVaibhav Hiremath if (ret) 12121fb19aa7SVaibhav Hiremath pr_warn("Doesn't have any child node\n"); 12131fb19aa7SVaibhav Hiremath 1214549985eeSRichard Cochran for_each_node_by_name(slave_node, "slave") { 1215549985eeSRichard Cochran struct cpsw_slave_data *slave_data = data->slave_data + i; 1216549985eeSRichard Cochran const void *mac_addr = NULL; 1217549985eeSRichard Cochran u32 phyid; 1218549985eeSRichard Cochran int lenp; 1219549985eeSRichard Cochran const __be32 *parp; 1220549985eeSRichard Cochran struct device_node *mdio_node; 1221549985eeSRichard Cochran struct platform_device *mdio; 1222549985eeSRichard Cochran 1223549985eeSRichard Cochran parp = of_get_property(slave_node, "phy_id", &lenp); 1224549985eeSRichard Cochran if ((parp == NULL) && (lenp != (sizeof(void *) * 2))) { 1225549985eeSRichard Cochran pr_err("Missing slave[%d] phy_id property\n", i); 1226549985eeSRichard Cochran ret = -EINVAL; 1227549985eeSRichard Cochran goto error_ret; 1228549985eeSRichard Cochran } 1229549985eeSRichard Cochran mdio_node = of_find_node_by_phandle(be32_to_cpup(parp)); 1230549985eeSRichard Cochran phyid = be32_to_cpup(parp+1); 1231549985eeSRichard Cochran mdio = of_find_device_by_node(mdio_node); 1232549985eeSRichard Cochran snprintf(slave_data->phy_id, sizeof(slave_data->phy_id), 1233549985eeSRichard Cochran PHY_ID_FMT, mdio->name, phyid); 1234549985eeSRichard Cochran 1235549985eeSRichard Cochran mac_addr = of_get_mac_address(slave_node); 1236549985eeSRichard Cochran if (mac_addr) 1237549985eeSRichard Cochran memcpy(slave_data->mac_addr, mac_addr, ETH_ALEN); 1238549985eeSRichard Cochran 1239549985eeSRichard Cochran i++; 1240549985eeSRichard Cochran } 1241549985eeSRichard Cochran 12422eb32b0aSMugunthan V N return 0; 12432eb32b0aSMugunthan V N 12442eb32b0aSMugunthan V N error_ret: 12452eb32b0aSMugunthan V N kfree(data->slave_data); 12462eb32b0aSMugunthan V N return ret; 12472eb32b0aSMugunthan V N } 12482eb32b0aSMugunthan V N 1249663e12e6SBill Pemberton static int cpsw_probe(struct platform_device *pdev) 1250df828598SMugunthan V N { 1251df828598SMugunthan V N struct cpsw_platform_data *data = pdev->dev.platform_data; 1252df828598SMugunthan V N struct net_device *ndev; 1253df828598SMugunthan V N struct cpsw_priv *priv; 1254df828598SMugunthan V N struct cpdma_params dma_params; 1255df828598SMugunthan V N struct cpsw_ale_params ale_params; 1256549985eeSRichard Cochran void __iomem *ss_regs, *wr_regs; 1257df828598SMugunthan V N struct resource *res; 1258549985eeSRichard Cochran u32 slave_offset, sliver_offset, slave_size; 1259df828598SMugunthan V N int ret = 0, i, k = 0; 1260df828598SMugunthan V N 1261df828598SMugunthan V N ndev = alloc_etherdev(sizeof(struct cpsw_priv)); 1262df828598SMugunthan V N if (!ndev) { 1263df828598SMugunthan V N pr_err("error allocating net_device\n"); 1264df828598SMugunthan V N return -ENOMEM; 1265df828598SMugunthan V N } 1266df828598SMugunthan V N 1267df828598SMugunthan V N platform_set_drvdata(pdev, ndev); 1268df828598SMugunthan V N priv = netdev_priv(ndev); 1269df828598SMugunthan V N spin_lock_init(&priv->lock); 1270df828598SMugunthan V N priv->pdev = pdev; 1271df828598SMugunthan V N priv->ndev = ndev; 1272df828598SMugunthan V N priv->dev = &ndev->dev; 1273df828598SMugunthan V N priv->msg_enable = netif_msg_init(debug_level, CPSW_DEBUG); 1274df828598SMugunthan V N priv->rx_packet_max = max(rx_packet_max, 128); 1275df828598SMugunthan V N 12761fb19aa7SVaibhav Hiremath /* 12771fb19aa7SVaibhav Hiremath * This may be required here for child devices. 12781fb19aa7SVaibhav Hiremath */ 12791fb19aa7SVaibhav Hiremath pm_runtime_enable(&pdev->dev); 12801fb19aa7SVaibhav Hiremath 12812eb32b0aSMugunthan V N if (cpsw_probe_dt(&priv->data, pdev)) { 12822eb32b0aSMugunthan V N pr_err("cpsw: platform data missing\n"); 12832eb32b0aSMugunthan V N ret = -ENODEV; 12842eb32b0aSMugunthan V N goto clean_ndev_ret; 12852eb32b0aSMugunthan V N } 12862eb32b0aSMugunthan V N data = &priv->data; 12872eb32b0aSMugunthan V N 1288df828598SMugunthan V N if (is_valid_ether_addr(data->slave_data[0].mac_addr)) { 1289df828598SMugunthan V N memcpy(priv->mac_addr, data->slave_data[0].mac_addr, ETH_ALEN); 1290df828598SMugunthan V N pr_info("Detected MACID = %pM", priv->mac_addr); 1291df828598SMugunthan V N } else { 12927efd26d0SJoe Perches eth_random_addr(priv->mac_addr); 1293df828598SMugunthan V N pr_info("Random MACID = %pM", priv->mac_addr); 1294df828598SMugunthan V N } 1295df828598SMugunthan V N 1296df828598SMugunthan V N memcpy(ndev->dev_addr, priv->mac_addr, ETH_ALEN); 1297df828598SMugunthan V N 1298df828598SMugunthan V N priv->slaves = kzalloc(sizeof(struct cpsw_slave) * data->slaves, 1299df828598SMugunthan V N GFP_KERNEL); 1300df828598SMugunthan V N if (!priv->slaves) { 1301df828598SMugunthan V N ret = -EBUSY; 1302df828598SMugunthan V N goto clean_ndev_ret; 1303df828598SMugunthan V N } 1304df828598SMugunthan V N for (i = 0; i < data->slaves; i++) 1305df828598SMugunthan V N priv->slaves[i].slave_num = i; 1306df828598SMugunthan V N 1307f150bd7fSMugunthan V N priv->clk = clk_get(&pdev->dev, "fck"); 1308df828598SMugunthan V N if (IS_ERR(priv->clk)) { 1309f150bd7fSMugunthan V N dev_err(&pdev->dev, "fck is not found\n"); 1310f150bd7fSMugunthan V N ret = -ENODEV; 1311f150bd7fSMugunthan V N goto clean_slave_ret; 1312df828598SMugunthan V N } 1313df828598SMugunthan V N 1314df828598SMugunthan V N priv->cpsw_res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1315df828598SMugunthan V N if (!priv->cpsw_res) { 1316df828598SMugunthan V N dev_err(priv->dev, "error getting i/o resource\n"); 1317df828598SMugunthan V N ret = -ENOENT; 1318df828598SMugunthan V N goto clean_clk_ret; 1319df828598SMugunthan V N } 1320df828598SMugunthan V N if (!request_mem_region(priv->cpsw_res->start, 1321df828598SMugunthan V N resource_size(priv->cpsw_res), ndev->name)) { 1322df828598SMugunthan V N dev_err(priv->dev, "failed request i/o region\n"); 1323df828598SMugunthan V N ret = -ENXIO; 1324df828598SMugunthan V N goto clean_clk_ret; 1325df828598SMugunthan V N } 1326549985eeSRichard Cochran ss_regs = ioremap(priv->cpsw_res->start, resource_size(priv->cpsw_res)); 1327549985eeSRichard Cochran if (!ss_regs) { 1328df828598SMugunthan V N dev_err(priv->dev, "unable to map i/o region\n"); 1329df828598SMugunthan V N goto clean_cpsw_iores_ret; 1330df828598SMugunthan V N } 1331549985eeSRichard Cochran priv->regs = ss_regs; 1332549985eeSRichard Cochran priv->version = __raw_readl(&priv->regs->id_ver); 1333549985eeSRichard Cochran priv->host_port = HOST_PORT_NUM; 1334df828598SMugunthan V N 1335a65dd5b2SRichard Cochran priv->cpsw_wr_res = platform_get_resource(pdev, IORESOURCE_MEM, 1); 1336a65dd5b2SRichard Cochran if (!priv->cpsw_wr_res) { 1337df828598SMugunthan V N dev_err(priv->dev, "error getting i/o resource\n"); 1338df828598SMugunthan V N ret = -ENOENT; 13395250c969SRichard Cochran goto clean_iomap_ret; 1340df828598SMugunthan V N } 1341a65dd5b2SRichard Cochran if (!request_mem_region(priv->cpsw_wr_res->start, 1342a65dd5b2SRichard Cochran resource_size(priv->cpsw_wr_res), ndev->name)) { 1343df828598SMugunthan V N dev_err(priv->dev, "failed request i/o region\n"); 1344df828598SMugunthan V N ret = -ENXIO; 13455250c969SRichard Cochran goto clean_iomap_ret; 1346df828598SMugunthan V N } 1347549985eeSRichard Cochran wr_regs = ioremap(priv->cpsw_wr_res->start, 1348a65dd5b2SRichard Cochran resource_size(priv->cpsw_wr_res)); 1349549985eeSRichard Cochran if (!wr_regs) { 1350df828598SMugunthan V N dev_err(priv->dev, "unable to map i/o region\n"); 1351a65dd5b2SRichard Cochran goto clean_cpsw_wr_iores_ret; 1352df828598SMugunthan V N } 1353549985eeSRichard Cochran priv->wr_regs = wr_regs; 1354df828598SMugunthan V N 1355df828598SMugunthan V N memset(&dma_params, 0, sizeof(dma_params)); 1356549985eeSRichard Cochran memset(&ale_params, 0, sizeof(ale_params)); 1357549985eeSRichard Cochran 1358549985eeSRichard Cochran switch (priv->version) { 1359549985eeSRichard Cochran case CPSW_VERSION_1: 1360549985eeSRichard Cochran priv->host_port_regs = ss_regs + CPSW1_HOST_PORT_OFFSET; 1361549985eeSRichard Cochran priv->cpts.reg = ss_regs + CPSW1_CPTS_OFFSET; 1362549985eeSRichard Cochran dma_params.dmaregs = ss_regs + CPSW1_CPDMA_OFFSET; 1363549985eeSRichard Cochran dma_params.txhdp = ss_regs + CPSW1_STATERAM_OFFSET; 1364549985eeSRichard Cochran ale_params.ale_regs = ss_regs + CPSW1_ALE_OFFSET; 1365549985eeSRichard Cochran slave_offset = CPSW1_SLAVE_OFFSET; 1366549985eeSRichard Cochran slave_size = CPSW1_SLAVE_SIZE; 1367549985eeSRichard Cochran sliver_offset = CPSW1_SLIVER_OFFSET; 1368549985eeSRichard Cochran dma_params.desc_mem_phys = 0; 1369549985eeSRichard Cochran break; 1370549985eeSRichard Cochran case CPSW_VERSION_2: 1371549985eeSRichard Cochran priv->host_port_regs = ss_regs + CPSW2_HOST_PORT_OFFSET; 1372549985eeSRichard Cochran priv->cpts.reg = ss_regs + CPSW2_CPTS_OFFSET; 1373549985eeSRichard Cochran dma_params.dmaregs = ss_regs + CPSW2_CPDMA_OFFSET; 1374549985eeSRichard Cochran dma_params.txhdp = ss_regs + CPSW2_STATERAM_OFFSET; 1375549985eeSRichard Cochran ale_params.ale_regs = ss_regs + CPSW2_ALE_OFFSET; 1376549985eeSRichard Cochran slave_offset = CPSW2_SLAVE_OFFSET; 1377549985eeSRichard Cochran slave_size = CPSW2_SLAVE_SIZE; 1378549985eeSRichard Cochran sliver_offset = CPSW2_SLIVER_OFFSET; 1379549985eeSRichard Cochran dma_params.desc_mem_phys = 1380549985eeSRichard Cochran (u32 __force) priv->cpsw_res->start + CPSW2_BD_OFFSET; 1381549985eeSRichard Cochran break; 1382549985eeSRichard Cochran default: 1383549985eeSRichard Cochran dev_err(priv->dev, "unknown version 0x%08x\n", priv->version); 1384549985eeSRichard Cochran ret = -ENODEV; 1385549985eeSRichard Cochran goto clean_cpsw_wr_iores_ret; 1386549985eeSRichard Cochran } 1387549985eeSRichard Cochran for (i = 0; i < priv->data.slaves; i++) { 1388549985eeSRichard Cochran struct cpsw_slave *slave = &priv->slaves[i]; 1389549985eeSRichard Cochran cpsw_slave_init(slave, priv, slave_offset, sliver_offset); 1390549985eeSRichard Cochran slave_offset += slave_size; 1391549985eeSRichard Cochran sliver_offset += SLIVER_SIZE; 1392549985eeSRichard Cochran } 1393549985eeSRichard Cochran 1394df828598SMugunthan V N dma_params.dev = &pdev->dev; 1395549985eeSRichard Cochran dma_params.rxthresh = dma_params.dmaregs + CPDMA_RXTHRESH; 1396549985eeSRichard Cochran dma_params.rxfree = dma_params.dmaregs + CPDMA_RXFREE; 1397549985eeSRichard Cochran dma_params.rxhdp = dma_params.txhdp + CPDMA_RXHDP; 1398549985eeSRichard Cochran dma_params.txcp = dma_params.txhdp + CPDMA_TXCP; 1399549985eeSRichard Cochran dma_params.rxcp = dma_params.txhdp + CPDMA_RXCP; 1400df828598SMugunthan V N 1401df828598SMugunthan V N dma_params.num_chan = data->channels; 1402df828598SMugunthan V N dma_params.has_soft_reset = true; 1403df828598SMugunthan V N dma_params.min_packet_size = CPSW_MIN_PACKET_SIZE; 1404df828598SMugunthan V N dma_params.desc_mem_size = data->bd_ram_size; 1405df828598SMugunthan V N dma_params.desc_align = 16; 1406df828598SMugunthan V N dma_params.has_ext_regs = true; 1407549985eeSRichard Cochran dma_params.desc_hw_addr = dma_params.desc_mem_phys; 1408df828598SMugunthan V N 1409df828598SMugunthan V N priv->dma = cpdma_ctlr_create(&dma_params); 1410df828598SMugunthan V N if (!priv->dma) { 1411df828598SMugunthan V N dev_err(priv->dev, "error initializing dma\n"); 1412df828598SMugunthan V N ret = -ENOMEM; 14135250c969SRichard Cochran goto clean_wr_iomap_ret; 1414df828598SMugunthan V N } 1415df828598SMugunthan V N 1416df828598SMugunthan V N priv->txch = cpdma_chan_create(priv->dma, tx_chan_num(0), 1417df828598SMugunthan V N cpsw_tx_handler); 1418df828598SMugunthan V N priv->rxch = cpdma_chan_create(priv->dma, rx_chan_num(0), 1419df828598SMugunthan V N cpsw_rx_handler); 1420df828598SMugunthan V N 1421df828598SMugunthan V N if (WARN_ON(!priv->txch || !priv->rxch)) { 1422df828598SMugunthan V N dev_err(priv->dev, "error initializing dma channels\n"); 1423df828598SMugunthan V N ret = -ENOMEM; 1424df828598SMugunthan V N goto clean_dma_ret; 1425df828598SMugunthan V N } 1426df828598SMugunthan V N 1427df828598SMugunthan V N ale_params.dev = &ndev->dev; 1428df828598SMugunthan V N ale_params.ale_ageout = ale_ageout; 1429df828598SMugunthan V N ale_params.ale_entries = data->ale_entries; 1430df828598SMugunthan V N ale_params.ale_ports = data->slaves; 1431df828598SMugunthan V N 1432df828598SMugunthan V N priv->ale = cpsw_ale_create(&ale_params); 1433df828598SMugunthan V N if (!priv->ale) { 1434df828598SMugunthan V N dev_err(priv->dev, "error initializing ale engine\n"); 1435df828598SMugunthan V N ret = -ENODEV; 1436df828598SMugunthan V N goto clean_dma_ret; 1437df828598SMugunthan V N } 1438df828598SMugunthan V N 1439df828598SMugunthan V N ndev->irq = platform_get_irq(pdev, 0); 1440df828598SMugunthan V N if (ndev->irq < 0) { 1441df828598SMugunthan V N dev_err(priv->dev, "error getting irq resource\n"); 1442df828598SMugunthan V N ret = -ENOENT; 1443df828598SMugunthan V N goto clean_ale_ret; 1444df828598SMugunthan V N } 1445df828598SMugunthan V N 1446df828598SMugunthan V N while ((res = platform_get_resource(priv->pdev, IORESOURCE_IRQ, k))) { 1447df828598SMugunthan V N for (i = res->start; i <= res->end; i++) { 1448df828598SMugunthan V N if (request_irq(i, cpsw_interrupt, IRQF_DISABLED, 1449df828598SMugunthan V N dev_name(&pdev->dev), priv)) { 1450df828598SMugunthan V N dev_err(priv->dev, "error attaching irq\n"); 1451df828598SMugunthan V N goto clean_ale_ret; 1452df828598SMugunthan V N } 1453df828598SMugunthan V N priv->irqs_table[k] = i; 1454df828598SMugunthan V N priv->num_irqs = k; 1455df828598SMugunthan V N } 1456df828598SMugunthan V N k++; 1457df828598SMugunthan V N } 1458df828598SMugunthan V N 14593b72c2feSMugunthan V N ndev->features |= NETIF_F_HW_VLAN_FILTER; 1460df828598SMugunthan V N 1461df828598SMugunthan V N ndev->netdev_ops = &cpsw_netdev_ops; 1462df828598SMugunthan V N SET_ETHTOOL_OPS(ndev, &cpsw_ethtool_ops); 1463df828598SMugunthan V N netif_napi_add(ndev, &priv->napi, cpsw_poll, CPSW_POLL_WEIGHT); 1464df828598SMugunthan V N 1465df828598SMugunthan V N /* register the network device */ 1466df828598SMugunthan V N SET_NETDEV_DEV(ndev, &pdev->dev); 1467df828598SMugunthan V N ret = register_netdev(ndev); 1468df828598SMugunthan V N if (ret) { 1469df828598SMugunthan V N dev_err(priv->dev, "error registering net device\n"); 1470df828598SMugunthan V N ret = -ENODEV; 1471df828598SMugunthan V N goto clean_irq_ret; 1472df828598SMugunthan V N } 1473df828598SMugunthan V N 14742e5b38abSRichard Cochran if (cpts_register(&pdev->dev, &priv->cpts, 14752e5b38abSRichard Cochran data->cpts_clock_mult, data->cpts_clock_shift)) 14762e5b38abSRichard Cochran dev_err(priv->dev, "error registering cpts device\n"); 14772e5b38abSRichard Cochran 1478df828598SMugunthan V N cpsw_notice(priv, probe, "initialized device (regs %x, irq %d)\n", 1479df828598SMugunthan V N priv->cpsw_res->start, ndev->irq); 1480df828598SMugunthan V N 1481df828598SMugunthan V N return 0; 1482df828598SMugunthan V N 1483df828598SMugunthan V N clean_irq_ret: 1484df828598SMugunthan V N free_irq(ndev->irq, priv); 1485df828598SMugunthan V N clean_ale_ret: 1486df828598SMugunthan V N cpsw_ale_destroy(priv->ale); 1487df828598SMugunthan V N clean_dma_ret: 1488df828598SMugunthan V N cpdma_chan_destroy(priv->txch); 1489df828598SMugunthan V N cpdma_chan_destroy(priv->rxch); 1490df828598SMugunthan V N cpdma_ctlr_destroy(priv->dma); 14915250c969SRichard Cochran clean_wr_iomap_ret: 14925250c969SRichard Cochran iounmap(priv->wr_regs); 1493a65dd5b2SRichard Cochran clean_cpsw_wr_iores_ret: 1494a65dd5b2SRichard Cochran release_mem_region(priv->cpsw_wr_res->start, 1495a65dd5b2SRichard Cochran resource_size(priv->cpsw_wr_res)); 14965250c969SRichard Cochran clean_iomap_ret: 14975250c969SRichard Cochran iounmap(priv->regs); 1498df828598SMugunthan V N clean_cpsw_iores_ret: 1499df828598SMugunthan V N release_mem_region(priv->cpsw_res->start, 1500df828598SMugunthan V N resource_size(priv->cpsw_res)); 1501df828598SMugunthan V N clean_clk_ret: 1502df828598SMugunthan V N clk_put(priv->clk); 1503f150bd7fSMugunthan V N clean_slave_ret: 1504f150bd7fSMugunthan V N pm_runtime_disable(&pdev->dev); 1505df828598SMugunthan V N kfree(priv->slaves); 1506df828598SMugunthan V N clean_ndev_ret: 1507df828598SMugunthan V N free_netdev(ndev); 1508df828598SMugunthan V N return ret; 1509df828598SMugunthan V N } 1510df828598SMugunthan V N 1511663e12e6SBill Pemberton static int cpsw_remove(struct platform_device *pdev) 1512df828598SMugunthan V N { 1513df828598SMugunthan V N struct net_device *ndev = platform_get_drvdata(pdev); 1514df828598SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 1515df828598SMugunthan V N 1516df828598SMugunthan V N pr_info("removing device"); 1517df828598SMugunthan V N platform_set_drvdata(pdev, NULL); 1518df828598SMugunthan V N 15192e5b38abSRichard Cochran cpts_unregister(&priv->cpts); 1520df828598SMugunthan V N free_irq(ndev->irq, priv); 1521df828598SMugunthan V N cpsw_ale_destroy(priv->ale); 1522df828598SMugunthan V N cpdma_chan_destroy(priv->txch); 1523df828598SMugunthan V N cpdma_chan_destroy(priv->rxch); 1524df828598SMugunthan V N cpdma_ctlr_destroy(priv->dma); 1525df828598SMugunthan V N iounmap(priv->regs); 1526df828598SMugunthan V N release_mem_region(priv->cpsw_res->start, 1527df828598SMugunthan V N resource_size(priv->cpsw_res)); 15285250c969SRichard Cochran iounmap(priv->wr_regs); 1529a65dd5b2SRichard Cochran release_mem_region(priv->cpsw_wr_res->start, 1530a65dd5b2SRichard Cochran resource_size(priv->cpsw_wr_res)); 1531f150bd7fSMugunthan V N pm_runtime_disable(&pdev->dev); 1532df828598SMugunthan V N clk_put(priv->clk); 1533df828598SMugunthan V N kfree(priv->slaves); 1534df828598SMugunthan V N free_netdev(ndev); 1535df828598SMugunthan V N 1536df828598SMugunthan V N return 0; 1537df828598SMugunthan V N } 1538df828598SMugunthan V N 1539df828598SMugunthan V N static int cpsw_suspend(struct device *dev) 1540df828598SMugunthan V N { 1541df828598SMugunthan V N struct platform_device *pdev = to_platform_device(dev); 1542df828598SMugunthan V N struct net_device *ndev = platform_get_drvdata(pdev); 1543df828598SMugunthan V N 1544df828598SMugunthan V N if (netif_running(ndev)) 1545df828598SMugunthan V N cpsw_ndo_stop(ndev); 1546f150bd7fSMugunthan V N pm_runtime_put_sync(&pdev->dev); 1547f150bd7fSMugunthan V N 1548df828598SMugunthan V N return 0; 1549df828598SMugunthan V N } 1550df828598SMugunthan V N 1551df828598SMugunthan V N static int cpsw_resume(struct device *dev) 1552df828598SMugunthan V N { 1553df828598SMugunthan V N struct platform_device *pdev = to_platform_device(dev); 1554df828598SMugunthan V N struct net_device *ndev = platform_get_drvdata(pdev); 1555df828598SMugunthan V N 1556f150bd7fSMugunthan V N pm_runtime_get_sync(&pdev->dev); 1557df828598SMugunthan V N if (netif_running(ndev)) 1558df828598SMugunthan V N cpsw_ndo_open(ndev); 1559df828598SMugunthan V N return 0; 1560df828598SMugunthan V N } 1561df828598SMugunthan V N 1562df828598SMugunthan V N static const struct dev_pm_ops cpsw_pm_ops = { 1563df828598SMugunthan V N .suspend = cpsw_suspend, 1564df828598SMugunthan V N .resume = cpsw_resume, 1565df828598SMugunthan V N }; 1566df828598SMugunthan V N 15672eb32b0aSMugunthan V N static const struct of_device_id cpsw_of_mtable[] = { 15682eb32b0aSMugunthan V N { .compatible = "ti,cpsw", }, 15692eb32b0aSMugunthan V N { /* sentinel */ }, 15702eb32b0aSMugunthan V N }; 15712eb32b0aSMugunthan V N 1572df828598SMugunthan V N static struct platform_driver cpsw_driver = { 1573df828598SMugunthan V N .driver = { 1574df828598SMugunthan V N .name = "cpsw", 1575df828598SMugunthan V N .owner = THIS_MODULE, 1576df828598SMugunthan V N .pm = &cpsw_pm_ops, 15772eb32b0aSMugunthan V N .of_match_table = of_match_ptr(cpsw_of_mtable), 1578df828598SMugunthan V N }, 1579df828598SMugunthan V N .probe = cpsw_probe, 1580663e12e6SBill Pemberton .remove = cpsw_remove, 1581df828598SMugunthan V N }; 1582df828598SMugunthan V N 1583df828598SMugunthan V N static int __init cpsw_init(void) 1584df828598SMugunthan V N { 1585df828598SMugunthan V N return platform_driver_register(&cpsw_driver); 1586df828598SMugunthan V N } 1587df828598SMugunthan V N late_initcall(cpsw_init); 1588df828598SMugunthan V N 1589df828598SMugunthan V N static void __exit cpsw_exit(void) 1590df828598SMugunthan V N { 1591df828598SMugunthan V N platform_driver_unregister(&cpsw_driver); 1592df828598SMugunthan V N } 1593df828598SMugunthan V N module_exit(cpsw_exit); 1594df828598SMugunthan V N 1595df828598SMugunthan V N MODULE_LICENSE("GPL"); 1596df828598SMugunthan V N MODULE_AUTHOR("Cyril Chemparathy <cyril@ti.com>"); 1597df828598SMugunthan V N MODULE_AUTHOR("Mugunthan V N <mugunthanvnm@ti.com>"); 1598df828598SMugunthan V N MODULE_DESCRIPTION("TI CPSW Ethernet driver"); 1599