1df828598SMugunthan V N /* 2df828598SMugunthan V N * Texas Instruments Ethernet Switch Driver 3df828598SMugunthan V N * 4df828598SMugunthan V N * Copyright (C) 2012 Texas Instruments 5df828598SMugunthan V N * 6df828598SMugunthan V N * This program is free software; you can redistribute it and/or 7df828598SMugunthan V N * modify it under the terms of the GNU General Public License as 8df828598SMugunthan V N * published by the Free Software Foundation version 2. 9df828598SMugunthan V N * 10df828598SMugunthan V N * This program is distributed "as is" WITHOUT ANY WARRANTY of any 11df828598SMugunthan V N * kind, whether express or implied; without even the implied warranty 12df828598SMugunthan V N * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13df828598SMugunthan V N * GNU General Public License for more details. 14df828598SMugunthan V N */ 15df828598SMugunthan V N 16df828598SMugunthan V N #include <linux/kernel.h> 17df828598SMugunthan V N #include <linux/io.h> 18df828598SMugunthan V N #include <linux/clk.h> 19df828598SMugunthan V N #include <linux/timer.h> 20df828598SMugunthan V N #include <linux/module.h> 21df828598SMugunthan V N #include <linux/platform_device.h> 22df828598SMugunthan V N #include <linux/irqreturn.h> 23df828598SMugunthan V N #include <linux/interrupt.h> 24df828598SMugunthan V N #include <linux/if_ether.h> 25df828598SMugunthan V N #include <linux/etherdevice.h> 26df828598SMugunthan V N #include <linux/netdevice.h> 272e5b38abSRichard Cochran #include <linux/net_tstamp.h> 28df828598SMugunthan V N #include <linux/phy.h> 29df828598SMugunthan V N #include <linux/workqueue.h> 30df828598SMugunthan V N #include <linux/delay.h> 31f150bd7fSMugunthan V N #include <linux/pm_runtime.h> 322eb32b0aSMugunthan V N #include <linux/of.h> 332eb32b0aSMugunthan V N #include <linux/of_net.h> 342eb32b0aSMugunthan V N #include <linux/of_device.h> 353b72c2feSMugunthan V N #include <linux/if_vlan.h> 36df828598SMugunthan V N 37df828598SMugunthan V N #include <linux/platform_data/cpsw.h> 38739683b4SMugunthan V N #include <linux/pinctrl/consumer.h> 39df828598SMugunthan V N 40df828598SMugunthan V N #include "cpsw_ale.h" 412e5b38abSRichard Cochran #include "cpts.h" 42df828598SMugunthan V N #include "davinci_cpdma.h" 43df828598SMugunthan V N 44df828598SMugunthan V N #define CPSW_DEBUG (NETIF_MSG_HW | NETIF_MSG_WOL | \ 45df828598SMugunthan V N NETIF_MSG_DRV | NETIF_MSG_LINK | \ 46df828598SMugunthan V N NETIF_MSG_IFUP | NETIF_MSG_INTR | \ 47df828598SMugunthan V N NETIF_MSG_PROBE | NETIF_MSG_TIMER | \ 48df828598SMugunthan V N NETIF_MSG_IFDOWN | NETIF_MSG_RX_ERR | \ 49df828598SMugunthan V N NETIF_MSG_TX_ERR | NETIF_MSG_TX_DONE | \ 50df828598SMugunthan V N NETIF_MSG_PKTDATA | NETIF_MSG_TX_QUEUED | \ 51df828598SMugunthan V N NETIF_MSG_RX_STATUS) 52df828598SMugunthan V N 53df828598SMugunthan V N #define cpsw_info(priv, type, format, ...) \ 54df828598SMugunthan V N do { \ 55df828598SMugunthan V N if (netif_msg_##type(priv) && net_ratelimit()) \ 56df828598SMugunthan V N dev_info(priv->dev, format, ## __VA_ARGS__); \ 57df828598SMugunthan V N } while (0) 58df828598SMugunthan V N 59df828598SMugunthan V N #define cpsw_err(priv, type, format, ...) \ 60df828598SMugunthan V N do { \ 61df828598SMugunthan V N if (netif_msg_##type(priv) && net_ratelimit()) \ 62df828598SMugunthan V N dev_err(priv->dev, format, ## __VA_ARGS__); \ 63df828598SMugunthan V N } while (0) 64df828598SMugunthan V N 65df828598SMugunthan V N #define cpsw_dbg(priv, type, format, ...) \ 66df828598SMugunthan V N do { \ 67df828598SMugunthan V N if (netif_msg_##type(priv) && net_ratelimit()) \ 68df828598SMugunthan V N dev_dbg(priv->dev, format, ## __VA_ARGS__); \ 69df828598SMugunthan V N } while (0) 70df828598SMugunthan V N 71df828598SMugunthan V N #define cpsw_notice(priv, type, format, ...) \ 72df828598SMugunthan V N do { \ 73df828598SMugunthan V N if (netif_msg_##type(priv) && net_ratelimit()) \ 74df828598SMugunthan V N dev_notice(priv->dev, format, ## __VA_ARGS__); \ 75df828598SMugunthan V N } while (0) 76df828598SMugunthan V N 775c50a856SMugunthan V N #define ALE_ALL_PORTS 0x7 785c50a856SMugunthan V N 79df828598SMugunthan V N #define CPSW_MAJOR_VERSION(reg) (reg >> 8 & 0x7) 80df828598SMugunthan V N #define CPSW_MINOR_VERSION(reg) (reg & 0xff) 81df828598SMugunthan V N #define CPSW_RTL_VERSION(reg) ((reg >> 11) & 0x1f) 82df828598SMugunthan V N 83e90cfac6SRichard Cochran #define CPSW_VERSION_1 0x19010a 84e90cfac6SRichard Cochran #define CPSW_VERSION_2 0x19010c 85549985eeSRichard Cochran 86549985eeSRichard Cochran #define HOST_PORT_NUM 0 87549985eeSRichard Cochran #define SLIVER_SIZE 0x40 88549985eeSRichard Cochran 89549985eeSRichard Cochran #define CPSW1_HOST_PORT_OFFSET 0x028 90549985eeSRichard Cochran #define CPSW1_SLAVE_OFFSET 0x050 91549985eeSRichard Cochran #define CPSW1_SLAVE_SIZE 0x040 92549985eeSRichard Cochran #define CPSW1_CPDMA_OFFSET 0x100 93549985eeSRichard Cochran #define CPSW1_STATERAM_OFFSET 0x200 94d9718546SMugunthan V N #define CPSW1_HW_STATS 0x400 95549985eeSRichard Cochran #define CPSW1_CPTS_OFFSET 0x500 96549985eeSRichard Cochran #define CPSW1_ALE_OFFSET 0x600 97549985eeSRichard Cochran #define CPSW1_SLIVER_OFFSET 0x700 98549985eeSRichard Cochran 99549985eeSRichard Cochran #define CPSW2_HOST_PORT_OFFSET 0x108 100549985eeSRichard Cochran #define CPSW2_SLAVE_OFFSET 0x200 101549985eeSRichard Cochran #define CPSW2_SLAVE_SIZE 0x100 102549985eeSRichard Cochran #define CPSW2_CPDMA_OFFSET 0x800 103d9718546SMugunthan V N #define CPSW2_HW_STATS 0x900 104549985eeSRichard Cochran #define CPSW2_STATERAM_OFFSET 0xa00 105549985eeSRichard Cochran #define CPSW2_CPTS_OFFSET 0xc00 106549985eeSRichard Cochran #define CPSW2_ALE_OFFSET 0xd00 107549985eeSRichard Cochran #define CPSW2_SLIVER_OFFSET 0xd80 108549985eeSRichard Cochran #define CPSW2_BD_OFFSET 0x2000 109549985eeSRichard Cochran 110df828598SMugunthan V N #define CPDMA_RXTHRESH 0x0c0 111df828598SMugunthan V N #define CPDMA_RXFREE 0x0e0 112df828598SMugunthan V N #define CPDMA_TXHDP 0x00 113df828598SMugunthan V N #define CPDMA_RXHDP 0x20 114df828598SMugunthan V N #define CPDMA_TXCP 0x40 115df828598SMugunthan V N #define CPDMA_RXCP 0x60 116df828598SMugunthan V N 117df828598SMugunthan V N #define CPSW_POLL_WEIGHT 64 118df828598SMugunthan V N #define CPSW_MIN_PACKET_SIZE 60 119df828598SMugunthan V N #define CPSW_MAX_PACKET_SIZE (1500 + 14 + 4 + 4) 120df828598SMugunthan V N 121df828598SMugunthan V N #define RX_PRIORITY_MAPPING 0x76543210 122df828598SMugunthan V N #define TX_PRIORITY_MAPPING 0x33221100 123df828598SMugunthan V N #define CPDMA_TX_PRIORITY_MAP 0x76543210 124df828598SMugunthan V N 1253b72c2feSMugunthan V N #define CPSW_VLAN_AWARE BIT(1) 1263b72c2feSMugunthan V N #define CPSW_ALE_VLAN_AWARE 1 1273b72c2feSMugunthan V N 128d9ba8f9eSMugunthan V N #define CPSW_FIFO_NORMAL_MODE (0 << 15) 129d9ba8f9eSMugunthan V N #define CPSW_FIFO_DUAL_MAC_MODE (1 << 15) 130d9ba8f9eSMugunthan V N #define CPSW_FIFO_RATE_LIMIT_MODE (2 << 15) 131d9ba8f9eSMugunthan V N 132ff5b8ef2SMugunthan V N #define CPSW_INTPACEEN (0x3f << 16) 133ff5b8ef2SMugunthan V N #define CPSW_INTPRESCALE_MASK (0x7FF << 0) 134ff5b8ef2SMugunthan V N #define CPSW_CMINTMAX_CNT 63 135ff5b8ef2SMugunthan V N #define CPSW_CMINTMIN_CNT 2 136ff5b8ef2SMugunthan V N #define CPSW_CMINTMAX_INTVL (1000 / CPSW_CMINTMIN_CNT) 137ff5b8ef2SMugunthan V N #define CPSW_CMINTMIN_INTVL ((1000 / CPSW_CMINTMAX_CNT) + 1) 138ff5b8ef2SMugunthan V N 139df828598SMugunthan V N #define cpsw_enable_irq(priv) \ 140df828598SMugunthan V N do { \ 141df828598SMugunthan V N u32 i; \ 142df828598SMugunthan V N for (i = 0; i < priv->num_irqs; i++) \ 143df828598SMugunthan V N enable_irq(priv->irqs_table[i]); \ 144df828598SMugunthan V N } while (0); 145df828598SMugunthan V N #define cpsw_disable_irq(priv) \ 146df828598SMugunthan V N do { \ 147df828598SMugunthan V N u32 i; \ 148df828598SMugunthan V N for (i = 0; i < priv->num_irqs; i++) \ 149df828598SMugunthan V N disable_irq_nosync(priv->irqs_table[i]); \ 150df828598SMugunthan V N } while (0); 151df828598SMugunthan V N 152d3bb9c58SMugunthan V N #define cpsw_slave_index(priv) \ 153d3bb9c58SMugunthan V N ((priv->data.dual_emac) ? priv->emac_port : \ 154d3bb9c58SMugunthan V N priv->data.active_slave) 155d3bb9c58SMugunthan V N 156df828598SMugunthan V N static int debug_level; 157df828598SMugunthan V N module_param(debug_level, int, 0); 158df828598SMugunthan V N MODULE_PARM_DESC(debug_level, "cpsw debug level (NETIF_MSG bits)"); 159df828598SMugunthan V N 160df828598SMugunthan V N static int ale_ageout = 10; 161df828598SMugunthan V N module_param(ale_ageout, int, 0); 162df828598SMugunthan V N MODULE_PARM_DESC(ale_ageout, "cpsw ale ageout interval (seconds)"); 163df828598SMugunthan V N 164df828598SMugunthan V N static int rx_packet_max = CPSW_MAX_PACKET_SIZE; 165df828598SMugunthan V N module_param(rx_packet_max, int, 0); 166df828598SMugunthan V N MODULE_PARM_DESC(rx_packet_max, "maximum receive packet size (bytes)"); 167df828598SMugunthan V N 168996a5c27SRichard Cochran struct cpsw_wr_regs { 169df828598SMugunthan V N u32 id_ver; 170df828598SMugunthan V N u32 soft_reset; 171df828598SMugunthan V N u32 control; 172df828598SMugunthan V N u32 int_control; 173df828598SMugunthan V N u32 rx_thresh_en; 174df828598SMugunthan V N u32 rx_en; 175df828598SMugunthan V N u32 tx_en; 176df828598SMugunthan V N u32 misc_en; 177ff5b8ef2SMugunthan V N u32 mem_allign1[8]; 178ff5b8ef2SMugunthan V N u32 rx_thresh_stat; 179ff5b8ef2SMugunthan V N u32 rx_stat; 180ff5b8ef2SMugunthan V N u32 tx_stat; 181ff5b8ef2SMugunthan V N u32 misc_stat; 182ff5b8ef2SMugunthan V N u32 mem_allign2[8]; 183ff5b8ef2SMugunthan V N u32 rx_imax; 184ff5b8ef2SMugunthan V N u32 tx_imax; 185ff5b8ef2SMugunthan V N 186df828598SMugunthan V N }; 187df828598SMugunthan V N 188996a5c27SRichard Cochran struct cpsw_ss_regs { 189df828598SMugunthan V N u32 id_ver; 190df828598SMugunthan V N u32 control; 191df828598SMugunthan V N u32 soft_reset; 192df828598SMugunthan V N u32 stat_port_en; 193df828598SMugunthan V N u32 ptype; 194bd357af2SRichard Cochran u32 soft_idle; 195bd357af2SRichard Cochran u32 thru_rate; 196bd357af2SRichard Cochran u32 gap_thresh; 197bd357af2SRichard Cochran u32 tx_start_wds; 198bd357af2SRichard Cochran u32 flow_control; 199bd357af2SRichard Cochran u32 vlan_ltype; 200bd357af2SRichard Cochran u32 ts_ltype; 201bd357af2SRichard Cochran u32 dlr_ltype; 202df828598SMugunthan V N }; 203df828598SMugunthan V N 2049750a3adSRichard Cochran /* CPSW_PORT_V1 */ 2059750a3adSRichard Cochran #define CPSW1_MAX_BLKS 0x00 /* Maximum FIFO Blocks */ 2069750a3adSRichard Cochran #define CPSW1_BLK_CNT 0x04 /* FIFO Block Usage Count (Read Only) */ 2079750a3adSRichard Cochran #define CPSW1_TX_IN_CTL 0x08 /* Transmit FIFO Control */ 2089750a3adSRichard Cochran #define CPSW1_PORT_VLAN 0x0c /* VLAN Register */ 2099750a3adSRichard Cochran #define CPSW1_TX_PRI_MAP 0x10 /* Tx Header Priority to Switch Pri Mapping */ 2109750a3adSRichard Cochran #define CPSW1_TS_CTL 0x14 /* Time Sync Control */ 2119750a3adSRichard Cochran #define CPSW1_TS_SEQ_LTYPE 0x18 /* Time Sync Sequence ID Offset and Msg Type */ 2129750a3adSRichard Cochran #define CPSW1_TS_VLAN 0x1c /* Time Sync VLAN1 and VLAN2 */ 2139750a3adSRichard Cochran 2149750a3adSRichard Cochran /* CPSW_PORT_V2 */ 2159750a3adSRichard Cochran #define CPSW2_CONTROL 0x00 /* Control Register */ 2169750a3adSRichard Cochran #define CPSW2_MAX_BLKS 0x08 /* Maximum FIFO Blocks */ 2179750a3adSRichard Cochran #define CPSW2_BLK_CNT 0x0c /* FIFO Block Usage Count (Read Only) */ 2189750a3adSRichard Cochran #define CPSW2_TX_IN_CTL 0x10 /* Transmit FIFO Control */ 2199750a3adSRichard Cochran #define CPSW2_PORT_VLAN 0x14 /* VLAN Register */ 2209750a3adSRichard Cochran #define CPSW2_TX_PRI_MAP 0x18 /* Tx Header Priority to Switch Pri Mapping */ 2219750a3adSRichard Cochran #define CPSW2_TS_SEQ_MTYPE 0x1c /* Time Sync Sequence ID Offset and Msg Type */ 2229750a3adSRichard Cochran 2239750a3adSRichard Cochran /* CPSW_PORT_V1 and V2 */ 2249750a3adSRichard Cochran #define SA_LO 0x20 /* CPGMAC_SL Source Address Low */ 2259750a3adSRichard Cochran #define SA_HI 0x24 /* CPGMAC_SL Source Address High */ 2269750a3adSRichard Cochran #define SEND_PERCENT 0x28 /* Transmit Queue Send Percentages */ 2279750a3adSRichard Cochran 2289750a3adSRichard Cochran /* CPSW_PORT_V2 only */ 2299750a3adSRichard Cochran #define RX_DSCP_PRI_MAP0 0x30 /* Rx DSCP Priority to Rx Packet Mapping */ 2309750a3adSRichard Cochran #define RX_DSCP_PRI_MAP1 0x34 /* Rx DSCP Priority to Rx Packet Mapping */ 2319750a3adSRichard Cochran #define RX_DSCP_PRI_MAP2 0x38 /* Rx DSCP Priority to Rx Packet Mapping */ 2329750a3adSRichard Cochran #define RX_DSCP_PRI_MAP3 0x3c /* Rx DSCP Priority to Rx Packet Mapping */ 2339750a3adSRichard Cochran #define RX_DSCP_PRI_MAP4 0x40 /* Rx DSCP Priority to Rx Packet Mapping */ 2349750a3adSRichard Cochran #define RX_DSCP_PRI_MAP5 0x44 /* Rx DSCP Priority to Rx Packet Mapping */ 2359750a3adSRichard Cochran #define RX_DSCP_PRI_MAP6 0x48 /* Rx DSCP Priority to Rx Packet Mapping */ 2369750a3adSRichard Cochran #define RX_DSCP_PRI_MAP7 0x4c /* Rx DSCP Priority to Rx Packet Mapping */ 2379750a3adSRichard Cochran 2389750a3adSRichard Cochran /* Bit definitions for the CPSW2_CONTROL register */ 2399750a3adSRichard Cochran #define PASS_PRI_TAGGED (1<<24) /* Pass Priority Tagged */ 2409750a3adSRichard Cochran #define VLAN_LTYPE2_EN (1<<21) /* VLAN LTYPE 2 enable */ 2419750a3adSRichard Cochran #define VLAN_LTYPE1_EN (1<<20) /* VLAN LTYPE 1 enable */ 2429750a3adSRichard Cochran #define DSCP_PRI_EN (1<<16) /* DSCP Priority Enable */ 2439750a3adSRichard Cochran #define TS_320 (1<<14) /* Time Sync Dest Port 320 enable */ 2449750a3adSRichard Cochran #define TS_319 (1<<13) /* Time Sync Dest Port 319 enable */ 2459750a3adSRichard Cochran #define TS_132 (1<<12) /* Time Sync Dest IP Addr 132 enable */ 2469750a3adSRichard Cochran #define TS_131 (1<<11) /* Time Sync Dest IP Addr 131 enable */ 2479750a3adSRichard Cochran #define TS_130 (1<<10) /* Time Sync Dest IP Addr 130 enable */ 2489750a3adSRichard Cochran #define TS_129 (1<<9) /* Time Sync Dest IP Addr 129 enable */ 2499750a3adSRichard Cochran #define TS_BIT8 (1<<8) /* ts_ttl_nonzero? */ 2509750a3adSRichard Cochran #define TS_ANNEX_D_EN (1<<4) /* Time Sync Annex D enable */ 2519750a3adSRichard Cochran #define TS_LTYPE2_EN (1<<3) /* Time Sync LTYPE 2 enable */ 2529750a3adSRichard Cochran #define TS_LTYPE1_EN (1<<2) /* Time Sync LTYPE 1 enable */ 2539750a3adSRichard Cochran #define TS_TX_EN (1<<1) /* Time Sync Transmit Enable */ 2549750a3adSRichard Cochran #define TS_RX_EN (1<<0) /* Time Sync Receive Enable */ 2559750a3adSRichard Cochran 2569750a3adSRichard Cochran #define CTRL_TS_BITS \ 2579750a3adSRichard Cochran (TS_320 | TS_319 | TS_132 | TS_131 | TS_130 | TS_129 | TS_BIT8 | \ 2589750a3adSRichard Cochran TS_ANNEX_D_EN | TS_LTYPE1_EN) 2599750a3adSRichard Cochran 2609750a3adSRichard Cochran #define CTRL_ALL_TS_MASK (CTRL_TS_BITS | TS_TX_EN | TS_RX_EN) 2619750a3adSRichard Cochran #define CTRL_TX_TS_BITS (CTRL_TS_BITS | TS_TX_EN) 2629750a3adSRichard Cochran #define CTRL_RX_TS_BITS (CTRL_TS_BITS | TS_RX_EN) 2639750a3adSRichard Cochran 2649750a3adSRichard Cochran /* Bit definitions for the CPSW2_TS_SEQ_MTYPE register */ 2659750a3adSRichard Cochran #define TS_SEQ_ID_OFFSET_SHIFT (16) /* Time Sync Sequence ID Offset */ 2669750a3adSRichard Cochran #define TS_SEQ_ID_OFFSET_MASK (0x3f) 2679750a3adSRichard Cochran #define TS_MSG_TYPE_EN_SHIFT (0) /* Time Sync Message Type Enable */ 2689750a3adSRichard Cochran #define TS_MSG_TYPE_EN_MASK (0xffff) 2699750a3adSRichard Cochran 2709750a3adSRichard Cochran /* The PTP event messages - Sync, Delay_Req, Pdelay_Req, and Pdelay_Resp. */ 2719750a3adSRichard Cochran #define EVENT_MSG_BITS ((1<<0) | (1<<1) | (1<<2) | (1<<3)) 272df828598SMugunthan V N 2732e5b38abSRichard Cochran /* Bit definitions for the CPSW1_TS_CTL register */ 2742e5b38abSRichard Cochran #define CPSW_V1_TS_RX_EN BIT(0) 2752e5b38abSRichard Cochran #define CPSW_V1_TS_TX_EN BIT(4) 2762e5b38abSRichard Cochran #define CPSW_V1_MSG_TYPE_OFS 16 2772e5b38abSRichard Cochran 2782e5b38abSRichard Cochran /* Bit definitions for the CPSW1_TS_SEQ_LTYPE register */ 2792e5b38abSRichard Cochran #define CPSW_V1_SEQ_ID_OFS_SHIFT 16 2802e5b38abSRichard Cochran 281df828598SMugunthan V N struct cpsw_host_regs { 282df828598SMugunthan V N u32 max_blks; 283df828598SMugunthan V N u32 blk_cnt; 284d9ba8f9eSMugunthan V N u32 tx_in_ctl; 285df828598SMugunthan V N u32 port_vlan; 286df828598SMugunthan V N u32 tx_pri_map; 287df828598SMugunthan V N u32 cpdma_tx_pri_map; 288df828598SMugunthan V N u32 cpdma_rx_chan_map; 289df828598SMugunthan V N }; 290df828598SMugunthan V N 291df828598SMugunthan V N struct cpsw_sliver_regs { 292df828598SMugunthan V N u32 id_ver; 293df828598SMugunthan V N u32 mac_control; 294df828598SMugunthan V N u32 mac_status; 295df828598SMugunthan V N u32 soft_reset; 296df828598SMugunthan V N u32 rx_maxlen; 297df828598SMugunthan V N u32 __reserved_0; 298df828598SMugunthan V N u32 rx_pause; 299df828598SMugunthan V N u32 tx_pause; 300df828598SMugunthan V N u32 __reserved_1; 301df828598SMugunthan V N u32 rx_pri_map; 302df828598SMugunthan V N }; 303df828598SMugunthan V N 304d9718546SMugunthan V N struct cpsw_hw_stats { 305d9718546SMugunthan V N u32 rxgoodframes; 306d9718546SMugunthan V N u32 rxbroadcastframes; 307d9718546SMugunthan V N u32 rxmulticastframes; 308d9718546SMugunthan V N u32 rxpauseframes; 309d9718546SMugunthan V N u32 rxcrcerrors; 310d9718546SMugunthan V N u32 rxaligncodeerrors; 311d9718546SMugunthan V N u32 rxoversizedframes; 312d9718546SMugunthan V N u32 rxjabberframes; 313d9718546SMugunthan V N u32 rxundersizedframes; 314d9718546SMugunthan V N u32 rxfragments; 315d9718546SMugunthan V N u32 __pad_0[2]; 316d9718546SMugunthan V N u32 rxoctets; 317d9718546SMugunthan V N u32 txgoodframes; 318d9718546SMugunthan V N u32 txbroadcastframes; 319d9718546SMugunthan V N u32 txmulticastframes; 320d9718546SMugunthan V N u32 txpauseframes; 321d9718546SMugunthan V N u32 txdeferredframes; 322d9718546SMugunthan V N u32 txcollisionframes; 323d9718546SMugunthan V N u32 txsinglecollframes; 324d9718546SMugunthan V N u32 txmultcollframes; 325d9718546SMugunthan V N u32 txexcessivecollisions; 326d9718546SMugunthan V N u32 txlatecollisions; 327d9718546SMugunthan V N u32 txunderrun; 328d9718546SMugunthan V N u32 txcarriersenseerrors; 329d9718546SMugunthan V N u32 txoctets; 330d9718546SMugunthan V N u32 octetframes64; 331d9718546SMugunthan V N u32 octetframes65t127; 332d9718546SMugunthan V N u32 octetframes128t255; 333d9718546SMugunthan V N u32 octetframes256t511; 334d9718546SMugunthan V N u32 octetframes512t1023; 335d9718546SMugunthan V N u32 octetframes1024tup; 336d9718546SMugunthan V N u32 netoctets; 337d9718546SMugunthan V N u32 rxsofoverruns; 338d9718546SMugunthan V N u32 rxmofoverruns; 339d9718546SMugunthan V N u32 rxdmaoverruns; 340d9718546SMugunthan V N }; 341d9718546SMugunthan V N 342df828598SMugunthan V N struct cpsw_slave { 3439750a3adSRichard Cochran void __iomem *regs; 344df828598SMugunthan V N struct cpsw_sliver_regs __iomem *sliver; 345df828598SMugunthan V N int slave_num; 346df828598SMugunthan V N u32 mac_control; 347df828598SMugunthan V N struct cpsw_slave_data *data; 348df828598SMugunthan V N struct phy_device *phy; 349d9ba8f9eSMugunthan V N struct net_device *ndev; 350d9ba8f9eSMugunthan V N u32 port_vlan; 351d9ba8f9eSMugunthan V N u32 open_stat; 352df828598SMugunthan V N }; 353df828598SMugunthan V N 3549750a3adSRichard Cochran static inline u32 slave_read(struct cpsw_slave *slave, u32 offset) 3559750a3adSRichard Cochran { 3569750a3adSRichard Cochran return __raw_readl(slave->regs + offset); 3579750a3adSRichard Cochran } 3589750a3adSRichard Cochran 3599750a3adSRichard Cochran static inline void slave_write(struct cpsw_slave *slave, u32 val, u32 offset) 3609750a3adSRichard Cochran { 3619750a3adSRichard Cochran __raw_writel(val, slave->regs + offset); 3629750a3adSRichard Cochran } 3639750a3adSRichard Cochran 364df828598SMugunthan V N struct cpsw_priv { 365df828598SMugunthan V N spinlock_t lock; 366df828598SMugunthan V N struct platform_device *pdev; 367df828598SMugunthan V N struct net_device *ndev; 368df828598SMugunthan V N struct resource *cpsw_res; 369a65dd5b2SRichard Cochran struct resource *cpsw_wr_res; 370df828598SMugunthan V N struct napi_struct napi; 371df828598SMugunthan V N struct device *dev; 372df828598SMugunthan V N struct cpsw_platform_data data; 373996a5c27SRichard Cochran struct cpsw_ss_regs __iomem *regs; 374996a5c27SRichard Cochran struct cpsw_wr_regs __iomem *wr_regs; 375d9718546SMugunthan V N u8 __iomem *hw_stats; 376df828598SMugunthan V N struct cpsw_host_regs __iomem *host_port_regs; 377df828598SMugunthan V N u32 msg_enable; 378e90cfac6SRichard Cochran u32 version; 379ff5b8ef2SMugunthan V N u32 coal_intvl; 380ff5b8ef2SMugunthan V N u32 bus_freq_mhz; 381df828598SMugunthan V N struct net_device_stats stats; 382df828598SMugunthan V N int rx_packet_max; 383df828598SMugunthan V N int host_port; 384df828598SMugunthan V N struct clk *clk; 385df828598SMugunthan V N u8 mac_addr[ETH_ALEN]; 386df828598SMugunthan V N struct cpsw_slave *slaves; 387df828598SMugunthan V N struct cpdma_ctlr *dma; 388df828598SMugunthan V N struct cpdma_chan *txch, *rxch; 389df828598SMugunthan V N struct cpsw_ale *ale; 390df828598SMugunthan V N /* snapshot of IRQ numbers */ 391df828598SMugunthan V N u32 irqs_table[4]; 392df828598SMugunthan V N u32 num_irqs; 393a11fbba9SSebastian Siewior bool irq_enabled; 3949232b16dSMugunthan V N struct cpts *cpts; 395d9ba8f9eSMugunthan V N u32 emac_port; 396df828598SMugunthan V N }; 397df828598SMugunthan V N 398d9718546SMugunthan V N struct cpsw_stats { 399d9718546SMugunthan V N char stat_string[ETH_GSTRING_LEN]; 400d9718546SMugunthan V N int type; 401d9718546SMugunthan V N int sizeof_stat; 402d9718546SMugunthan V N int stat_offset; 403d9718546SMugunthan V N }; 404d9718546SMugunthan V N 405d9718546SMugunthan V N enum { 406d9718546SMugunthan V N CPSW_STATS, 407d9718546SMugunthan V N CPDMA_RX_STATS, 408d9718546SMugunthan V N CPDMA_TX_STATS, 409d9718546SMugunthan V N }; 410d9718546SMugunthan V N 411d9718546SMugunthan V N #define CPSW_STAT(m) CPSW_STATS, \ 412d9718546SMugunthan V N sizeof(((struct cpsw_hw_stats *)0)->m), \ 413d9718546SMugunthan V N offsetof(struct cpsw_hw_stats, m) 414d9718546SMugunthan V N #define CPDMA_RX_STAT(m) CPDMA_RX_STATS, \ 415d9718546SMugunthan V N sizeof(((struct cpdma_chan_stats *)0)->m), \ 416d9718546SMugunthan V N offsetof(struct cpdma_chan_stats, m) 417d9718546SMugunthan V N #define CPDMA_TX_STAT(m) CPDMA_TX_STATS, \ 418d9718546SMugunthan V N sizeof(((struct cpdma_chan_stats *)0)->m), \ 419d9718546SMugunthan V N offsetof(struct cpdma_chan_stats, m) 420d9718546SMugunthan V N 421d9718546SMugunthan V N static const struct cpsw_stats cpsw_gstrings_stats[] = { 422d9718546SMugunthan V N { "Good Rx Frames", CPSW_STAT(rxgoodframes) }, 423d9718546SMugunthan V N { "Broadcast Rx Frames", CPSW_STAT(rxbroadcastframes) }, 424d9718546SMugunthan V N { "Multicast Rx Frames", CPSW_STAT(rxmulticastframes) }, 425d9718546SMugunthan V N { "Pause Rx Frames", CPSW_STAT(rxpauseframes) }, 426d9718546SMugunthan V N { "Rx CRC Errors", CPSW_STAT(rxcrcerrors) }, 427d9718546SMugunthan V N { "Rx Align/Code Errors", CPSW_STAT(rxaligncodeerrors) }, 428d9718546SMugunthan V N { "Oversize Rx Frames", CPSW_STAT(rxoversizedframes) }, 429d9718546SMugunthan V N { "Rx Jabbers", CPSW_STAT(rxjabberframes) }, 430d9718546SMugunthan V N { "Undersize (Short) Rx Frames", CPSW_STAT(rxundersizedframes) }, 431d9718546SMugunthan V N { "Rx Fragments", CPSW_STAT(rxfragments) }, 432d9718546SMugunthan V N { "Rx Octets", CPSW_STAT(rxoctets) }, 433d9718546SMugunthan V N { "Good Tx Frames", CPSW_STAT(txgoodframes) }, 434d9718546SMugunthan V N { "Broadcast Tx Frames", CPSW_STAT(txbroadcastframes) }, 435d9718546SMugunthan V N { "Multicast Tx Frames", CPSW_STAT(txmulticastframes) }, 436d9718546SMugunthan V N { "Pause Tx Frames", CPSW_STAT(txpauseframes) }, 437d9718546SMugunthan V N { "Deferred Tx Frames", CPSW_STAT(txdeferredframes) }, 438d9718546SMugunthan V N { "Collisions", CPSW_STAT(txcollisionframes) }, 439d9718546SMugunthan V N { "Single Collision Tx Frames", CPSW_STAT(txsinglecollframes) }, 440d9718546SMugunthan V N { "Multiple Collision Tx Frames", CPSW_STAT(txmultcollframes) }, 441d9718546SMugunthan V N { "Excessive Collisions", CPSW_STAT(txexcessivecollisions) }, 442d9718546SMugunthan V N { "Late Collisions", CPSW_STAT(txlatecollisions) }, 443d9718546SMugunthan V N { "Tx Underrun", CPSW_STAT(txunderrun) }, 444d9718546SMugunthan V N { "Carrier Sense Errors", CPSW_STAT(txcarriersenseerrors) }, 445d9718546SMugunthan V N { "Tx Octets", CPSW_STAT(txoctets) }, 446d9718546SMugunthan V N { "Rx + Tx 64 Octet Frames", CPSW_STAT(octetframes64) }, 447d9718546SMugunthan V N { "Rx + Tx 65-127 Octet Frames", CPSW_STAT(octetframes65t127) }, 448d9718546SMugunthan V N { "Rx + Tx 128-255 Octet Frames", CPSW_STAT(octetframes128t255) }, 449d9718546SMugunthan V N { "Rx + Tx 256-511 Octet Frames", CPSW_STAT(octetframes256t511) }, 450d9718546SMugunthan V N { "Rx + Tx 512-1023 Octet Frames", CPSW_STAT(octetframes512t1023) }, 451d9718546SMugunthan V N { "Rx + Tx 1024-Up Octet Frames", CPSW_STAT(octetframes1024tup) }, 452d9718546SMugunthan V N { "Net Octets", CPSW_STAT(netoctets) }, 453d9718546SMugunthan V N { "Rx Start of Frame Overruns", CPSW_STAT(rxsofoverruns) }, 454d9718546SMugunthan V N { "Rx Middle of Frame Overruns", CPSW_STAT(rxmofoverruns) }, 455d9718546SMugunthan V N { "Rx DMA Overruns", CPSW_STAT(rxdmaoverruns) }, 456d9718546SMugunthan V N { "Rx DMA chan: head_enqueue", CPDMA_RX_STAT(head_enqueue) }, 457d9718546SMugunthan V N { "Rx DMA chan: tail_enqueue", CPDMA_RX_STAT(tail_enqueue) }, 458d9718546SMugunthan V N { "Rx DMA chan: pad_enqueue", CPDMA_RX_STAT(pad_enqueue) }, 459d9718546SMugunthan V N { "Rx DMA chan: misqueued", CPDMA_RX_STAT(misqueued) }, 460d9718546SMugunthan V N { "Rx DMA chan: desc_alloc_fail", CPDMA_RX_STAT(desc_alloc_fail) }, 461d9718546SMugunthan V N { "Rx DMA chan: pad_alloc_fail", CPDMA_RX_STAT(pad_alloc_fail) }, 462d9718546SMugunthan V N { "Rx DMA chan: runt_receive_buf", CPDMA_RX_STAT(runt_receive_buff) }, 463d9718546SMugunthan V N { "Rx DMA chan: runt_transmit_buf", CPDMA_RX_STAT(runt_transmit_buff) }, 464d9718546SMugunthan V N { "Rx DMA chan: empty_dequeue", CPDMA_RX_STAT(empty_dequeue) }, 465d9718546SMugunthan V N { "Rx DMA chan: busy_dequeue", CPDMA_RX_STAT(busy_dequeue) }, 466d9718546SMugunthan V N { "Rx DMA chan: good_dequeue", CPDMA_RX_STAT(good_dequeue) }, 467d9718546SMugunthan V N { "Rx DMA chan: requeue", CPDMA_RX_STAT(requeue) }, 468d9718546SMugunthan V N { "Rx DMA chan: teardown_dequeue", CPDMA_RX_STAT(teardown_dequeue) }, 469d9718546SMugunthan V N { "Tx DMA chan: head_enqueue", CPDMA_TX_STAT(head_enqueue) }, 470d9718546SMugunthan V N { "Tx DMA chan: tail_enqueue", CPDMA_TX_STAT(tail_enqueue) }, 471d9718546SMugunthan V N { "Tx DMA chan: pad_enqueue", CPDMA_TX_STAT(pad_enqueue) }, 472d9718546SMugunthan V N { "Tx DMA chan: misqueued", CPDMA_TX_STAT(misqueued) }, 473d9718546SMugunthan V N { "Tx DMA chan: desc_alloc_fail", CPDMA_TX_STAT(desc_alloc_fail) }, 474d9718546SMugunthan V N { "Tx DMA chan: pad_alloc_fail", CPDMA_TX_STAT(pad_alloc_fail) }, 475d9718546SMugunthan V N { "Tx DMA chan: runt_receive_buf", CPDMA_TX_STAT(runt_receive_buff) }, 476d9718546SMugunthan V N { "Tx DMA chan: runt_transmit_buf", CPDMA_TX_STAT(runt_transmit_buff) }, 477d9718546SMugunthan V N { "Tx DMA chan: empty_dequeue", CPDMA_TX_STAT(empty_dequeue) }, 478d9718546SMugunthan V N { "Tx DMA chan: busy_dequeue", CPDMA_TX_STAT(busy_dequeue) }, 479d9718546SMugunthan V N { "Tx DMA chan: good_dequeue", CPDMA_TX_STAT(good_dequeue) }, 480d9718546SMugunthan V N { "Tx DMA chan: requeue", CPDMA_TX_STAT(requeue) }, 481d9718546SMugunthan V N { "Tx DMA chan: teardown_dequeue", CPDMA_TX_STAT(teardown_dequeue) }, 482d9718546SMugunthan V N }; 483d9718546SMugunthan V N 484d9718546SMugunthan V N #define CPSW_STATS_LEN ARRAY_SIZE(cpsw_gstrings_stats) 485d9718546SMugunthan V N 486df828598SMugunthan V N #define napi_to_priv(napi) container_of(napi, struct cpsw_priv, napi) 487df828598SMugunthan V N #define for_each_slave(priv, func, arg...) \ 488df828598SMugunthan V N do { \ 4896e6ceaedSSebastian Siewior struct cpsw_slave *slave; \ 4906e6ceaedSSebastian Siewior int n; \ 491d9ba8f9eSMugunthan V N if (priv->data.dual_emac) \ 492d9ba8f9eSMugunthan V N (func)((priv)->slaves + priv->emac_port, ##arg);\ 493d9ba8f9eSMugunthan V N else \ 4946e6ceaedSSebastian Siewior for (n = (priv)->data.slaves, \ 4956e6ceaedSSebastian Siewior slave = (priv)->slaves; \ 4966e6ceaedSSebastian Siewior n; n--) \ 4976e6ceaedSSebastian Siewior (func)(slave++, ##arg); \ 498df828598SMugunthan V N } while (0) 499d9ba8f9eSMugunthan V N #define cpsw_get_slave_ndev(priv, __slave_no__) \ 500d9ba8f9eSMugunthan V N (priv->slaves[__slave_no__].ndev) 501d9ba8f9eSMugunthan V N #define cpsw_get_slave_priv(priv, __slave_no__) \ 502d9ba8f9eSMugunthan V N ((priv->slaves[__slave_no__].ndev) ? \ 503d9ba8f9eSMugunthan V N netdev_priv(priv->slaves[__slave_no__].ndev) : NULL) \ 504d9ba8f9eSMugunthan V N 505d9ba8f9eSMugunthan V N #define cpsw_dual_emac_src_port_detect(status, priv, ndev, skb) \ 506d9ba8f9eSMugunthan V N do { \ 507d9ba8f9eSMugunthan V N if (!priv->data.dual_emac) \ 508d9ba8f9eSMugunthan V N break; \ 509d9ba8f9eSMugunthan V N if (CPDMA_RX_SOURCE_PORT(status) == 1) { \ 510d9ba8f9eSMugunthan V N ndev = cpsw_get_slave_ndev(priv, 0); \ 511d9ba8f9eSMugunthan V N priv = netdev_priv(ndev); \ 512d9ba8f9eSMugunthan V N skb->dev = ndev; \ 513d9ba8f9eSMugunthan V N } else if (CPDMA_RX_SOURCE_PORT(status) == 2) { \ 514d9ba8f9eSMugunthan V N ndev = cpsw_get_slave_ndev(priv, 1); \ 515d9ba8f9eSMugunthan V N priv = netdev_priv(ndev); \ 516d9ba8f9eSMugunthan V N skb->dev = ndev; \ 517d9ba8f9eSMugunthan V N } \ 518d9ba8f9eSMugunthan V N } while (0) 519d9ba8f9eSMugunthan V N #define cpsw_add_mcast(priv, addr) \ 520d9ba8f9eSMugunthan V N do { \ 521d9ba8f9eSMugunthan V N if (priv->data.dual_emac) { \ 522d9ba8f9eSMugunthan V N struct cpsw_slave *slave = priv->slaves + \ 523d9ba8f9eSMugunthan V N priv->emac_port; \ 524d9ba8f9eSMugunthan V N int slave_port = cpsw_get_slave_port(priv, \ 525d9ba8f9eSMugunthan V N slave->slave_num); \ 526d9ba8f9eSMugunthan V N cpsw_ale_add_mcast(priv->ale, addr, \ 527d9ba8f9eSMugunthan V N 1 << slave_port | 1 << priv->host_port, \ 528d9ba8f9eSMugunthan V N ALE_VLAN, slave->port_vlan, 0); \ 529d9ba8f9eSMugunthan V N } else { \ 530d9ba8f9eSMugunthan V N cpsw_ale_add_mcast(priv->ale, addr, \ 531d9ba8f9eSMugunthan V N ALE_ALL_PORTS << priv->host_port, \ 532d9ba8f9eSMugunthan V N 0, 0, 0); \ 533d9ba8f9eSMugunthan V N } \ 534d9ba8f9eSMugunthan V N } while (0) 535d9ba8f9eSMugunthan V N 536d9ba8f9eSMugunthan V N static inline int cpsw_get_slave_port(struct cpsw_priv *priv, u32 slave_num) 537d9ba8f9eSMugunthan V N { 538d9ba8f9eSMugunthan V N if (priv->host_port == 0) 539d9ba8f9eSMugunthan V N return slave_num + 1; 540d9ba8f9eSMugunthan V N else 541d9ba8f9eSMugunthan V N return slave_num; 542d9ba8f9eSMugunthan V N } 543df828598SMugunthan V N 5445c50a856SMugunthan V N static void cpsw_ndo_set_rx_mode(struct net_device *ndev) 5455c50a856SMugunthan V N { 5465c50a856SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 5475c50a856SMugunthan V N 5485c50a856SMugunthan V N if (ndev->flags & IFF_PROMISC) { 5495c50a856SMugunthan V N /* Enable promiscuous mode */ 5505c50a856SMugunthan V N dev_err(priv->dev, "Ignoring Promiscuous mode\n"); 5515c50a856SMugunthan V N return; 5525c50a856SMugunthan V N } 5535c50a856SMugunthan V N 5545c50a856SMugunthan V N /* Clear all mcast from ALE */ 5555c50a856SMugunthan V N cpsw_ale_flush_multicast(priv->ale, ALE_ALL_PORTS << priv->host_port); 5565c50a856SMugunthan V N 5575c50a856SMugunthan V N if (!netdev_mc_empty(ndev)) { 5585c50a856SMugunthan V N struct netdev_hw_addr *ha; 5595c50a856SMugunthan V N 5605c50a856SMugunthan V N /* program multicast address list into ALE register */ 5615c50a856SMugunthan V N netdev_for_each_mc_addr(ha, ndev) { 562d9ba8f9eSMugunthan V N cpsw_add_mcast(priv, (u8 *)ha->addr); 5635c50a856SMugunthan V N } 5645c50a856SMugunthan V N } 5655c50a856SMugunthan V N } 5665c50a856SMugunthan V N 567df828598SMugunthan V N static void cpsw_intr_enable(struct cpsw_priv *priv) 568df828598SMugunthan V N { 569996a5c27SRichard Cochran __raw_writel(0xFF, &priv->wr_regs->tx_en); 570996a5c27SRichard Cochran __raw_writel(0xFF, &priv->wr_regs->rx_en); 571df828598SMugunthan V N 572df828598SMugunthan V N cpdma_ctlr_int_ctrl(priv->dma, true); 573df828598SMugunthan V N return; 574df828598SMugunthan V N } 575df828598SMugunthan V N 576df828598SMugunthan V N static void cpsw_intr_disable(struct cpsw_priv *priv) 577df828598SMugunthan V N { 578996a5c27SRichard Cochran __raw_writel(0, &priv->wr_regs->tx_en); 579996a5c27SRichard Cochran __raw_writel(0, &priv->wr_regs->rx_en); 580df828598SMugunthan V N 581df828598SMugunthan V N cpdma_ctlr_int_ctrl(priv->dma, false); 582df828598SMugunthan V N return; 583df828598SMugunthan V N } 584df828598SMugunthan V N 585df828598SMugunthan V N void cpsw_tx_handler(void *token, int len, int status) 586df828598SMugunthan V N { 587df828598SMugunthan V N struct sk_buff *skb = token; 588df828598SMugunthan V N struct net_device *ndev = skb->dev; 589df828598SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 590df828598SMugunthan V N 591fae50823SMugunthan V N /* Check whether the queue is stopped due to stalled tx dma, if the 592fae50823SMugunthan V N * queue is stopped then start the queue as we have free desc for tx 593fae50823SMugunthan V N */ 594df828598SMugunthan V N if (unlikely(netif_queue_stopped(ndev))) 595b56d6b3fSMugunthan V N netif_wake_queue(ndev); 5969232b16dSMugunthan V N cpts_tx_timestamp(priv->cpts, skb); 597df828598SMugunthan V N priv->stats.tx_packets++; 598df828598SMugunthan V N priv->stats.tx_bytes += len; 599df828598SMugunthan V N dev_kfree_skb_any(skb); 600df828598SMugunthan V N } 601df828598SMugunthan V N 602df828598SMugunthan V N void cpsw_rx_handler(void *token, int len, int status) 603df828598SMugunthan V N { 604df828598SMugunthan V N struct sk_buff *skb = token; 605b4727e69SSebastian Siewior struct sk_buff *new_skb; 606df828598SMugunthan V N struct net_device *ndev = skb->dev; 607df828598SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 608df828598SMugunthan V N int ret = 0; 609df828598SMugunthan V N 610d9ba8f9eSMugunthan V N cpsw_dual_emac_src_port_detect(status, priv, ndev, skb); 611d9ba8f9eSMugunthan V N 612b4727e69SSebastian Siewior if (unlikely(status < 0)) { 613b4727e69SSebastian Siewior /* the interface is going down, skbs are purged */ 614df828598SMugunthan V N dev_kfree_skb_any(skb); 615df828598SMugunthan V N return; 616df828598SMugunthan V N } 617b4727e69SSebastian Siewior 618b4727e69SSebastian Siewior new_skb = netdev_alloc_skb_ip_align(ndev, priv->rx_packet_max); 619b4727e69SSebastian Siewior if (new_skb) { 620df828598SMugunthan V N skb_put(skb, len); 6219232b16dSMugunthan V N cpts_rx_timestamp(priv->cpts, skb); 622df828598SMugunthan V N skb->protocol = eth_type_trans(skb, ndev); 623df828598SMugunthan V N netif_receive_skb(skb); 624df828598SMugunthan V N priv->stats.rx_bytes += len; 625df828598SMugunthan V N priv->stats.rx_packets++; 626b4727e69SSebastian Siewior } else { 627b4727e69SSebastian Siewior priv->stats.rx_dropped++; 628b4727e69SSebastian Siewior new_skb = skb; 629df828598SMugunthan V N } 630df828598SMugunthan V N 631b4727e69SSebastian Siewior ret = cpdma_chan_submit(priv->rxch, new_skb, new_skb->data, 632b4727e69SSebastian Siewior skb_tailroom(new_skb), 0); 633b4727e69SSebastian Siewior if (WARN_ON(ret < 0)) 634b4727e69SSebastian Siewior dev_kfree_skb_any(new_skb); 635df828598SMugunthan V N } 636df828598SMugunthan V N 637df828598SMugunthan V N static irqreturn_t cpsw_interrupt(int irq, void *dev_id) 638df828598SMugunthan V N { 639df828598SMugunthan V N struct cpsw_priv *priv = dev_id; 640fd51cf19SSebastian Siewior u32 rx, tx, rx_thresh; 641df828598SMugunthan V N 642fd51cf19SSebastian Siewior rx_thresh = __raw_readl(&priv->wr_regs->rx_thresh_stat); 643fd51cf19SSebastian Siewior rx = __raw_readl(&priv->wr_regs->rx_stat); 644fd51cf19SSebastian Siewior tx = __raw_readl(&priv->wr_regs->tx_stat); 645fd51cf19SSebastian Siewior if (!rx_thresh && !rx && !tx) 646fd51cf19SSebastian Siewior return IRQ_NONE; 647fd51cf19SSebastian Siewior 648df828598SMugunthan V N cpsw_intr_disable(priv); 649a11fbba9SSebastian Siewior if (priv->irq_enabled == true) { 650df828598SMugunthan V N cpsw_disable_irq(priv); 651a11fbba9SSebastian Siewior priv->irq_enabled = false; 652a11fbba9SSebastian Siewior } 653fd51cf19SSebastian Siewior 654fd51cf19SSebastian Siewior if (netif_running(priv->ndev)) { 655df828598SMugunthan V N napi_schedule(&priv->napi); 656df828598SMugunthan V N return IRQ_HANDLED; 657df828598SMugunthan V N } 658df828598SMugunthan V N 659fd51cf19SSebastian Siewior priv = cpsw_get_slave_priv(priv, 1); 660fd51cf19SSebastian Siewior if (!priv) 661fd51cf19SSebastian Siewior return IRQ_NONE; 662fd51cf19SSebastian Siewior 663fd51cf19SSebastian Siewior if (netif_running(priv->ndev)) { 664fd51cf19SSebastian Siewior napi_schedule(&priv->napi); 665fd51cf19SSebastian Siewior return IRQ_HANDLED; 666fd51cf19SSebastian Siewior } 667fd51cf19SSebastian Siewior return IRQ_NONE; 668fd51cf19SSebastian Siewior } 669fd51cf19SSebastian Siewior 670df828598SMugunthan V N static int cpsw_poll(struct napi_struct *napi, int budget) 671df828598SMugunthan V N { 672df828598SMugunthan V N struct cpsw_priv *priv = napi_to_priv(napi); 673df828598SMugunthan V N int num_tx, num_rx; 674df828598SMugunthan V N 675df828598SMugunthan V N num_tx = cpdma_chan_process(priv->txch, 128); 676510a1e72SMugunthan V N if (num_tx) 677510a1e72SMugunthan V N cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_TX); 678510a1e72SMugunthan V N 679df828598SMugunthan V N num_rx = cpdma_chan_process(priv->rxch, budget); 680510a1e72SMugunthan V N if (num_rx < budget) { 681a11fbba9SSebastian Siewior struct cpsw_priv *prim_cpsw; 682a11fbba9SSebastian Siewior 683510a1e72SMugunthan V N napi_complete(napi); 684510a1e72SMugunthan V N cpsw_intr_enable(priv); 685510a1e72SMugunthan V N cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_RX); 686a11fbba9SSebastian Siewior prim_cpsw = cpsw_get_slave_priv(priv, 0); 687a11fbba9SSebastian Siewior if (prim_cpsw->irq_enabled == false) { 688a11fbba9SSebastian Siewior prim_cpsw->irq_enabled = true; 689af5c6df7SMugunthan V N cpsw_enable_irq(priv); 690a11fbba9SSebastian Siewior } 691510a1e72SMugunthan V N } 692df828598SMugunthan V N 693df828598SMugunthan V N if (num_rx || num_tx) 694df828598SMugunthan V N cpsw_dbg(priv, intr, "poll %d rx, %d tx pkts\n", 695df828598SMugunthan V N num_rx, num_tx); 696df828598SMugunthan V N 697df828598SMugunthan V N return num_rx; 698df828598SMugunthan V N } 699df828598SMugunthan V N 700df828598SMugunthan V N static inline void soft_reset(const char *module, void __iomem *reg) 701df828598SMugunthan V N { 702df828598SMugunthan V N unsigned long timeout = jiffies + HZ; 703df828598SMugunthan V N 704df828598SMugunthan V N __raw_writel(1, reg); 705df828598SMugunthan V N do { 706df828598SMugunthan V N cpu_relax(); 707df828598SMugunthan V N } while ((__raw_readl(reg) & 1) && time_after(timeout, jiffies)); 708df828598SMugunthan V N 709df828598SMugunthan V N WARN(__raw_readl(reg) & 1, "failed to soft-reset %s\n", module); 710df828598SMugunthan V N } 711df828598SMugunthan V N 712df828598SMugunthan V N #define mac_hi(mac) (((mac)[0] << 0) | ((mac)[1] << 8) | \ 713df828598SMugunthan V N ((mac)[2] << 16) | ((mac)[3] << 24)) 714df828598SMugunthan V N #define mac_lo(mac) (((mac)[4] << 0) | ((mac)[5] << 8)) 715df828598SMugunthan V N 716df828598SMugunthan V N static void cpsw_set_slave_mac(struct cpsw_slave *slave, 717df828598SMugunthan V N struct cpsw_priv *priv) 718df828598SMugunthan V N { 7199750a3adSRichard Cochran slave_write(slave, mac_hi(priv->mac_addr), SA_HI); 7209750a3adSRichard Cochran slave_write(slave, mac_lo(priv->mac_addr), SA_LO); 721df828598SMugunthan V N } 722df828598SMugunthan V N 723df828598SMugunthan V N static void _cpsw_adjust_link(struct cpsw_slave *slave, 724df828598SMugunthan V N struct cpsw_priv *priv, bool *link) 725df828598SMugunthan V N { 726df828598SMugunthan V N struct phy_device *phy = slave->phy; 727df828598SMugunthan V N u32 mac_control = 0; 728df828598SMugunthan V N u32 slave_port; 729df828598SMugunthan V N 730df828598SMugunthan V N if (!phy) 731df828598SMugunthan V N return; 732df828598SMugunthan V N 733df828598SMugunthan V N slave_port = cpsw_get_slave_port(priv, slave->slave_num); 734df828598SMugunthan V N 735df828598SMugunthan V N if (phy->link) { 736df828598SMugunthan V N mac_control = priv->data.mac_control; 737df828598SMugunthan V N 738df828598SMugunthan V N /* enable forwarding */ 739df828598SMugunthan V N cpsw_ale_control_set(priv->ale, slave_port, 740df828598SMugunthan V N ALE_PORT_STATE, ALE_PORT_STATE_FORWARD); 741df828598SMugunthan V N 742df828598SMugunthan V N if (phy->speed == 1000) 743df828598SMugunthan V N mac_control |= BIT(7); /* GIGABITEN */ 744df828598SMugunthan V N if (phy->duplex) 745df828598SMugunthan V N mac_control |= BIT(0); /* FULLDUPLEXEN */ 746342b7b74SDaniel Mack 747342b7b74SDaniel Mack /* set speed_in input in case RMII mode is used in 100Mbps */ 748342b7b74SDaniel Mack if (phy->speed == 100) 749342b7b74SDaniel Mack mac_control |= BIT(15); 750342b7b74SDaniel Mack 751df828598SMugunthan V N *link = true; 752df828598SMugunthan V N } else { 753df828598SMugunthan V N mac_control = 0; 754df828598SMugunthan V N /* disable forwarding */ 755df828598SMugunthan V N cpsw_ale_control_set(priv->ale, slave_port, 756df828598SMugunthan V N ALE_PORT_STATE, ALE_PORT_STATE_DISABLE); 757df828598SMugunthan V N } 758df828598SMugunthan V N 759df828598SMugunthan V N if (mac_control != slave->mac_control) { 760df828598SMugunthan V N phy_print_status(phy); 761df828598SMugunthan V N __raw_writel(mac_control, &slave->sliver->mac_control); 762df828598SMugunthan V N } 763df828598SMugunthan V N 764df828598SMugunthan V N slave->mac_control = mac_control; 765df828598SMugunthan V N } 766df828598SMugunthan V N 767df828598SMugunthan V N static void cpsw_adjust_link(struct net_device *ndev) 768df828598SMugunthan V N { 769df828598SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 770df828598SMugunthan V N bool link = false; 771df828598SMugunthan V N 772df828598SMugunthan V N for_each_slave(priv, _cpsw_adjust_link, priv, &link); 773df828598SMugunthan V N 774df828598SMugunthan V N if (link) { 775df828598SMugunthan V N netif_carrier_on(ndev); 776df828598SMugunthan V N if (netif_running(ndev)) 777df828598SMugunthan V N netif_wake_queue(ndev); 778df828598SMugunthan V N } else { 779df828598SMugunthan V N netif_carrier_off(ndev); 780df828598SMugunthan V N netif_stop_queue(ndev); 781df828598SMugunthan V N } 782df828598SMugunthan V N } 783df828598SMugunthan V N 784ff5b8ef2SMugunthan V N static int cpsw_get_coalesce(struct net_device *ndev, 785ff5b8ef2SMugunthan V N struct ethtool_coalesce *coal) 786ff5b8ef2SMugunthan V N { 787ff5b8ef2SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 788ff5b8ef2SMugunthan V N 789ff5b8ef2SMugunthan V N coal->rx_coalesce_usecs = priv->coal_intvl; 790ff5b8ef2SMugunthan V N return 0; 791ff5b8ef2SMugunthan V N } 792ff5b8ef2SMugunthan V N 793ff5b8ef2SMugunthan V N static int cpsw_set_coalesce(struct net_device *ndev, 794ff5b8ef2SMugunthan V N struct ethtool_coalesce *coal) 795ff5b8ef2SMugunthan V N { 796ff5b8ef2SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 797ff5b8ef2SMugunthan V N u32 int_ctrl; 798ff5b8ef2SMugunthan V N u32 num_interrupts = 0; 799ff5b8ef2SMugunthan V N u32 prescale = 0; 800ff5b8ef2SMugunthan V N u32 addnl_dvdr = 1; 801ff5b8ef2SMugunthan V N u32 coal_intvl = 0; 802ff5b8ef2SMugunthan V N 803ff5b8ef2SMugunthan V N if (!coal->rx_coalesce_usecs) 804ff5b8ef2SMugunthan V N return -EINVAL; 805ff5b8ef2SMugunthan V N 806ff5b8ef2SMugunthan V N coal_intvl = coal->rx_coalesce_usecs; 807ff5b8ef2SMugunthan V N 808ff5b8ef2SMugunthan V N int_ctrl = readl(&priv->wr_regs->int_control); 809ff5b8ef2SMugunthan V N prescale = priv->bus_freq_mhz * 4; 810ff5b8ef2SMugunthan V N 811ff5b8ef2SMugunthan V N if (coal_intvl < CPSW_CMINTMIN_INTVL) 812ff5b8ef2SMugunthan V N coal_intvl = CPSW_CMINTMIN_INTVL; 813ff5b8ef2SMugunthan V N 814ff5b8ef2SMugunthan V N if (coal_intvl > CPSW_CMINTMAX_INTVL) { 815ff5b8ef2SMugunthan V N /* Interrupt pacer works with 4us Pulse, we can 816ff5b8ef2SMugunthan V N * throttle further by dilating the 4us pulse. 817ff5b8ef2SMugunthan V N */ 818ff5b8ef2SMugunthan V N addnl_dvdr = CPSW_INTPRESCALE_MASK / prescale; 819ff5b8ef2SMugunthan V N 820ff5b8ef2SMugunthan V N if (addnl_dvdr > 1) { 821ff5b8ef2SMugunthan V N prescale *= addnl_dvdr; 822ff5b8ef2SMugunthan V N if (coal_intvl > (CPSW_CMINTMAX_INTVL * addnl_dvdr)) 823ff5b8ef2SMugunthan V N coal_intvl = (CPSW_CMINTMAX_INTVL 824ff5b8ef2SMugunthan V N * addnl_dvdr); 825ff5b8ef2SMugunthan V N } else { 826ff5b8ef2SMugunthan V N addnl_dvdr = 1; 827ff5b8ef2SMugunthan V N coal_intvl = CPSW_CMINTMAX_INTVL; 828ff5b8ef2SMugunthan V N } 829ff5b8ef2SMugunthan V N } 830ff5b8ef2SMugunthan V N 831ff5b8ef2SMugunthan V N num_interrupts = (1000 * addnl_dvdr) / coal_intvl; 832ff5b8ef2SMugunthan V N writel(num_interrupts, &priv->wr_regs->rx_imax); 833ff5b8ef2SMugunthan V N writel(num_interrupts, &priv->wr_regs->tx_imax); 834ff5b8ef2SMugunthan V N 835ff5b8ef2SMugunthan V N int_ctrl |= CPSW_INTPACEEN; 836ff5b8ef2SMugunthan V N int_ctrl &= (~CPSW_INTPRESCALE_MASK); 837ff5b8ef2SMugunthan V N int_ctrl |= (prescale & CPSW_INTPRESCALE_MASK); 838ff5b8ef2SMugunthan V N writel(int_ctrl, &priv->wr_regs->int_control); 839ff5b8ef2SMugunthan V N 840ff5b8ef2SMugunthan V N cpsw_notice(priv, timer, "Set coalesce to %d usecs.\n", coal_intvl); 841ff5b8ef2SMugunthan V N if (priv->data.dual_emac) { 842ff5b8ef2SMugunthan V N int i; 843ff5b8ef2SMugunthan V N 844ff5b8ef2SMugunthan V N for (i = 0; i < priv->data.slaves; i++) { 845ff5b8ef2SMugunthan V N priv = netdev_priv(priv->slaves[i].ndev); 846ff5b8ef2SMugunthan V N priv->coal_intvl = coal_intvl; 847ff5b8ef2SMugunthan V N } 848ff5b8ef2SMugunthan V N } else { 849ff5b8ef2SMugunthan V N priv->coal_intvl = coal_intvl; 850ff5b8ef2SMugunthan V N } 851ff5b8ef2SMugunthan V N 852ff5b8ef2SMugunthan V N return 0; 853ff5b8ef2SMugunthan V N } 854ff5b8ef2SMugunthan V N 855d9718546SMugunthan V N static int cpsw_get_sset_count(struct net_device *ndev, int sset) 856d9718546SMugunthan V N { 857d9718546SMugunthan V N switch (sset) { 858d9718546SMugunthan V N case ETH_SS_STATS: 859d9718546SMugunthan V N return CPSW_STATS_LEN; 860d9718546SMugunthan V N default: 861d9718546SMugunthan V N return -EOPNOTSUPP; 862d9718546SMugunthan V N } 863d9718546SMugunthan V N } 864d9718546SMugunthan V N 865d9718546SMugunthan V N static void cpsw_get_strings(struct net_device *ndev, u32 stringset, u8 *data) 866d9718546SMugunthan V N { 867d9718546SMugunthan V N u8 *p = data; 868d9718546SMugunthan V N int i; 869d9718546SMugunthan V N 870d9718546SMugunthan V N switch (stringset) { 871d9718546SMugunthan V N case ETH_SS_STATS: 872d9718546SMugunthan V N for (i = 0; i < CPSW_STATS_LEN; i++) { 873d9718546SMugunthan V N memcpy(p, cpsw_gstrings_stats[i].stat_string, 874d9718546SMugunthan V N ETH_GSTRING_LEN); 875d9718546SMugunthan V N p += ETH_GSTRING_LEN; 876d9718546SMugunthan V N } 877d9718546SMugunthan V N break; 878d9718546SMugunthan V N } 879d9718546SMugunthan V N } 880d9718546SMugunthan V N 881d9718546SMugunthan V N static void cpsw_get_ethtool_stats(struct net_device *ndev, 882d9718546SMugunthan V N struct ethtool_stats *stats, u64 *data) 883d9718546SMugunthan V N { 884d9718546SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 885d9718546SMugunthan V N struct cpdma_chan_stats rx_stats; 886d9718546SMugunthan V N struct cpdma_chan_stats tx_stats; 887d9718546SMugunthan V N u32 val; 888d9718546SMugunthan V N u8 *p; 889d9718546SMugunthan V N int i; 890d9718546SMugunthan V N 891d9718546SMugunthan V N /* Collect Davinci CPDMA stats for Rx and Tx Channel */ 892d9718546SMugunthan V N cpdma_chan_get_stats(priv->rxch, &rx_stats); 893d9718546SMugunthan V N cpdma_chan_get_stats(priv->txch, &tx_stats); 894d9718546SMugunthan V N 895d9718546SMugunthan V N for (i = 0; i < CPSW_STATS_LEN; i++) { 896d9718546SMugunthan V N switch (cpsw_gstrings_stats[i].type) { 897d9718546SMugunthan V N case CPSW_STATS: 898d9718546SMugunthan V N val = readl(priv->hw_stats + 899d9718546SMugunthan V N cpsw_gstrings_stats[i].stat_offset); 900d9718546SMugunthan V N data[i] = val; 901d9718546SMugunthan V N break; 902d9718546SMugunthan V N 903d9718546SMugunthan V N case CPDMA_RX_STATS: 904d9718546SMugunthan V N p = (u8 *)&rx_stats + 905d9718546SMugunthan V N cpsw_gstrings_stats[i].stat_offset; 906d9718546SMugunthan V N data[i] = *(u32 *)p; 907d9718546SMugunthan V N break; 908d9718546SMugunthan V N 909d9718546SMugunthan V N case CPDMA_TX_STATS: 910d9718546SMugunthan V N p = (u8 *)&tx_stats + 911d9718546SMugunthan V N cpsw_gstrings_stats[i].stat_offset; 912d9718546SMugunthan V N data[i] = *(u32 *)p; 913d9718546SMugunthan V N break; 914d9718546SMugunthan V N } 915d9718546SMugunthan V N } 916d9718546SMugunthan V N } 917d9718546SMugunthan V N 918df828598SMugunthan V N static inline int __show_stat(char *buf, int maxlen, const char *name, u32 val) 919df828598SMugunthan V N { 920df828598SMugunthan V N static char *leader = "........................................"; 921df828598SMugunthan V N 922df828598SMugunthan V N if (!val) 923df828598SMugunthan V N return 0; 924df828598SMugunthan V N else 925df828598SMugunthan V N return snprintf(buf, maxlen, "%s %s %10d\n", name, 926df828598SMugunthan V N leader + strlen(name), val); 927df828598SMugunthan V N } 928df828598SMugunthan V N 929d9ba8f9eSMugunthan V N static int cpsw_common_res_usage_state(struct cpsw_priv *priv) 930d9ba8f9eSMugunthan V N { 931d9ba8f9eSMugunthan V N u32 i; 932d9ba8f9eSMugunthan V N u32 usage_count = 0; 933d9ba8f9eSMugunthan V N 934d9ba8f9eSMugunthan V N if (!priv->data.dual_emac) 935d9ba8f9eSMugunthan V N return 0; 936d9ba8f9eSMugunthan V N 937d9ba8f9eSMugunthan V N for (i = 0; i < priv->data.slaves; i++) 938d9ba8f9eSMugunthan V N if (priv->slaves[i].open_stat) 939d9ba8f9eSMugunthan V N usage_count++; 940d9ba8f9eSMugunthan V N 941d9ba8f9eSMugunthan V N return usage_count; 942d9ba8f9eSMugunthan V N } 943d9ba8f9eSMugunthan V N 944d9ba8f9eSMugunthan V N static inline int cpsw_tx_packet_submit(struct net_device *ndev, 945d9ba8f9eSMugunthan V N struct cpsw_priv *priv, struct sk_buff *skb) 946d9ba8f9eSMugunthan V N { 947d9ba8f9eSMugunthan V N if (!priv->data.dual_emac) 948d9ba8f9eSMugunthan V N return cpdma_chan_submit(priv->txch, skb, skb->data, 949aef614e1SSebastian Siewior skb->len, 0); 950d9ba8f9eSMugunthan V N 951d9ba8f9eSMugunthan V N if (ndev == cpsw_get_slave_ndev(priv, 0)) 952d9ba8f9eSMugunthan V N return cpdma_chan_submit(priv->txch, skb, skb->data, 953aef614e1SSebastian Siewior skb->len, 1); 954d9ba8f9eSMugunthan V N else 955d9ba8f9eSMugunthan V N return cpdma_chan_submit(priv->txch, skb, skb->data, 956aef614e1SSebastian Siewior skb->len, 2); 957d9ba8f9eSMugunthan V N } 958d9ba8f9eSMugunthan V N 959d9ba8f9eSMugunthan V N static inline void cpsw_add_dual_emac_def_ale_entries( 960d9ba8f9eSMugunthan V N struct cpsw_priv *priv, struct cpsw_slave *slave, 961d9ba8f9eSMugunthan V N u32 slave_port) 962d9ba8f9eSMugunthan V N { 963d9ba8f9eSMugunthan V N u32 port_mask = 1 << slave_port | 1 << priv->host_port; 964d9ba8f9eSMugunthan V N 965d9ba8f9eSMugunthan V N if (priv->version == CPSW_VERSION_1) 966d9ba8f9eSMugunthan V N slave_write(slave, slave->port_vlan, CPSW1_PORT_VLAN); 967d9ba8f9eSMugunthan V N else 968d9ba8f9eSMugunthan V N slave_write(slave, slave->port_vlan, CPSW2_PORT_VLAN); 969d9ba8f9eSMugunthan V N cpsw_ale_add_vlan(priv->ale, slave->port_vlan, port_mask, 970d9ba8f9eSMugunthan V N port_mask, port_mask, 0); 971d9ba8f9eSMugunthan V N cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast, 972d9ba8f9eSMugunthan V N port_mask, ALE_VLAN, slave->port_vlan, 0); 973d9ba8f9eSMugunthan V N cpsw_ale_add_ucast(priv->ale, priv->mac_addr, 974d9ba8f9eSMugunthan V N priv->host_port, ALE_VLAN, slave->port_vlan); 975d9ba8f9eSMugunthan V N } 976d9ba8f9eSMugunthan V N 977df828598SMugunthan V N static void cpsw_slave_open(struct cpsw_slave *slave, struct cpsw_priv *priv) 978df828598SMugunthan V N { 979df828598SMugunthan V N char name[32]; 980df828598SMugunthan V N u32 slave_port; 981df828598SMugunthan V N 982df828598SMugunthan V N sprintf(name, "slave-%d", slave->slave_num); 983df828598SMugunthan V N 984df828598SMugunthan V N soft_reset(name, &slave->sliver->soft_reset); 985df828598SMugunthan V N 986df828598SMugunthan V N /* setup priority mapping */ 987df828598SMugunthan V N __raw_writel(RX_PRIORITY_MAPPING, &slave->sliver->rx_pri_map); 9889750a3adSRichard Cochran 9899750a3adSRichard Cochran switch (priv->version) { 9909750a3adSRichard Cochran case CPSW_VERSION_1: 9919750a3adSRichard Cochran slave_write(slave, TX_PRIORITY_MAPPING, CPSW1_TX_PRI_MAP); 9929750a3adSRichard Cochran break; 9939750a3adSRichard Cochran case CPSW_VERSION_2: 9949750a3adSRichard Cochran slave_write(slave, TX_PRIORITY_MAPPING, CPSW2_TX_PRI_MAP); 9959750a3adSRichard Cochran break; 9969750a3adSRichard Cochran } 997df828598SMugunthan V N 998df828598SMugunthan V N /* setup max packet size, and mac address */ 999df828598SMugunthan V N __raw_writel(priv->rx_packet_max, &slave->sliver->rx_maxlen); 1000df828598SMugunthan V N cpsw_set_slave_mac(slave, priv); 1001df828598SMugunthan V N 1002df828598SMugunthan V N slave->mac_control = 0; /* no link yet */ 1003df828598SMugunthan V N 1004df828598SMugunthan V N slave_port = cpsw_get_slave_port(priv, slave->slave_num); 1005df828598SMugunthan V N 1006d9ba8f9eSMugunthan V N if (priv->data.dual_emac) 1007d9ba8f9eSMugunthan V N cpsw_add_dual_emac_def_ale_entries(priv, slave, slave_port); 1008d9ba8f9eSMugunthan V N else 1009df828598SMugunthan V N cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast, 1010e11b220fSMugunthan V N 1 << slave_port, 0, 0, ALE_MCAST_FWD_2); 1011df828598SMugunthan V N 1012df828598SMugunthan V N slave->phy = phy_connect(priv->ndev, slave->data->phy_id, 1013f9a8f83bSFlorian Fainelli &cpsw_adjust_link, slave->data->phy_if); 1014df828598SMugunthan V N if (IS_ERR(slave->phy)) { 1015df828598SMugunthan V N dev_err(priv->dev, "phy %s not found on slave %d\n", 1016df828598SMugunthan V N slave->data->phy_id, slave->slave_num); 1017df828598SMugunthan V N slave->phy = NULL; 1018df828598SMugunthan V N } else { 1019df828598SMugunthan V N dev_info(priv->dev, "phy found : id is : 0x%x\n", 1020df828598SMugunthan V N slave->phy->phy_id); 1021df828598SMugunthan V N phy_start(slave->phy); 1022df828598SMugunthan V N } 1023df828598SMugunthan V N } 1024df828598SMugunthan V N 10253b72c2feSMugunthan V N static inline void cpsw_add_default_vlan(struct cpsw_priv *priv) 10263b72c2feSMugunthan V N { 10273b72c2feSMugunthan V N const int vlan = priv->data.default_vlan; 10283b72c2feSMugunthan V N const int port = priv->host_port; 10293b72c2feSMugunthan V N u32 reg; 10303b72c2feSMugunthan V N int i; 10313b72c2feSMugunthan V N 10323b72c2feSMugunthan V N reg = (priv->version == CPSW_VERSION_1) ? CPSW1_PORT_VLAN : 10333b72c2feSMugunthan V N CPSW2_PORT_VLAN; 10343b72c2feSMugunthan V N 10353b72c2feSMugunthan V N writel(vlan, &priv->host_port_regs->port_vlan); 10363b72c2feSMugunthan V N 10370237c110SDaniel Mack for (i = 0; i < priv->data.slaves; i++) 10383b72c2feSMugunthan V N slave_write(priv->slaves + i, vlan, reg); 10393b72c2feSMugunthan V N 10403b72c2feSMugunthan V N cpsw_ale_add_vlan(priv->ale, vlan, ALE_ALL_PORTS << port, 10413b72c2feSMugunthan V N ALE_ALL_PORTS << port, ALE_ALL_PORTS << port, 10423b72c2feSMugunthan V N (ALE_PORT_1 | ALE_PORT_2) << port); 10433b72c2feSMugunthan V N } 10443b72c2feSMugunthan V N 1045df828598SMugunthan V N static void cpsw_init_host_port(struct cpsw_priv *priv) 1046df828598SMugunthan V N { 10473b72c2feSMugunthan V N u32 control_reg; 1048d9ba8f9eSMugunthan V N u32 fifo_mode; 10493b72c2feSMugunthan V N 1050df828598SMugunthan V N /* soft reset the controller and initialize ale */ 1051df828598SMugunthan V N soft_reset("cpsw", &priv->regs->soft_reset); 1052df828598SMugunthan V N cpsw_ale_start(priv->ale); 1053df828598SMugunthan V N 1054df828598SMugunthan V N /* switch to vlan unaware mode */ 10553b72c2feSMugunthan V N cpsw_ale_control_set(priv->ale, priv->host_port, ALE_VLAN_AWARE, 10563b72c2feSMugunthan V N CPSW_ALE_VLAN_AWARE); 10573b72c2feSMugunthan V N control_reg = readl(&priv->regs->control); 10583b72c2feSMugunthan V N control_reg |= CPSW_VLAN_AWARE; 10593b72c2feSMugunthan V N writel(control_reg, &priv->regs->control); 1060d9ba8f9eSMugunthan V N fifo_mode = (priv->data.dual_emac) ? CPSW_FIFO_DUAL_MAC_MODE : 1061d9ba8f9eSMugunthan V N CPSW_FIFO_NORMAL_MODE; 1062d9ba8f9eSMugunthan V N writel(fifo_mode, &priv->host_port_regs->tx_in_ctl); 1063df828598SMugunthan V N 1064df828598SMugunthan V N /* setup host port priority mapping */ 1065df828598SMugunthan V N __raw_writel(CPDMA_TX_PRIORITY_MAP, 1066df828598SMugunthan V N &priv->host_port_regs->cpdma_tx_pri_map); 1067df828598SMugunthan V N __raw_writel(0, &priv->host_port_regs->cpdma_rx_chan_map); 1068df828598SMugunthan V N 1069df828598SMugunthan V N cpsw_ale_control_set(priv->ale, priv->host_port, 1070df828598SMugunthan V N ALE_PORT_STATE, ALE_PORT_STATE_FORWARD); 1071df828598SMugunthan V N 1072d9ba8f9eSMugunthan V N if (!priv->data.dual_emac) { 1073d9ba8f9eSMugunthan V N cpsw_ale_add_ucast(priv->ale, priv->mac_addr, priv->host_port, 1074d9ba8f9eSMugunthan V N 0, 0); 1075df828598SMugunthan V N cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast, 1076e11b220fSMugunthan V N 1 << priv->host_port, 0, 0, ALE_MCAST_FWD_2); 1077df828598SMugunthan V N } 1078d9ba8f9eSMugunthan V N } 1079df828598SMugunthan V N 1080aacebbf8SSebastian Siewior static void cpsw_slave_stop(struct cpsw_slave *slave, struct cpsw_priv *priv) 1081aacebbf8SSebastian Siewior { 1082aacebbf8SSebastian Siewior if (!slave->phy) 1083aacebbf8SSebastian Siewior return; 1084aacebbf8SSebastian Siewior phy_stop(slave->phy); 1085aacebbf8SSebastian Siewior phy_disconnect(slave->phy); 1086aacebbf8SSebastian Siewior slave->phy = NULL; 1087aacebbf8SSebastian Siewior } 1088aacebbf8SSebastian Siewior 1089df828598SMugunthan V N static int cpsw_ndo_open(struct net_device *ndev) 1090df828598SMugunthan V N { 1091df828598SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 1092a11fbba9SSebastian Siewior struct cpsw_priv *prim_cpsw; 1093df828598SMugunthan V N int i, ret; 1094df828598SMugunthan V N u32 reg; 1095df828598SMugunthan V N 1096d9ba8f9eSMugunthan V N if (!cpsw_common_res_usage_state(priv)) 1097df828598SMugunthan V N cpsw_intr_disable(priv); 1098df828598SMugunthan V N netif_carrier_off(ndev); 1099df828598SMugunthan V N 1100f150bd7fSMugunthan V N pm_runtime_get_sync(&priv->pdev->dev); 1101df828598SMugunthan V N 1102549985eeSRichard Cochran reg = priv->version; 1103df828598SMugunthan V N 1104df828598SMugunthan V N dev_info(priv->dev, "initializing cpsw version %d.%d (%d)\n", 1105df828598SMugunthan V N CPSW_MAJOR_VERSION(reg), CPSW_MINOR_VERSION(reg), 1106df828598SMugunthan V N CPSW_RTL_VERSION(reg)); 1107df828598SMugunthan V N 1108df828598SMugunthan V N /* initialize host and slave ports */ 1109d9ba8f9eSMugunthan V N if (!cpsw_common_res_usage_state(priv)) 1110df828598SMugunthan V N cpsw_init_host_port(priv); 1111df828598SMugunthan V N for_each_slave(priv, cpsw_slave_open, priv); 1112df828598SMugunthan V N 11133b72c2feSMugunthan V N /* Add default VLAN */ 1114d9ba8f9eSMugunthan V N if (!priv->data.dual_emac) 11153b72c2feSMugunthan V N cpsw_add_default_vlan(priv); 11163b72c2feSMugunthan V N 1117d9ba8f9eSMugunthan V N if (!cpsw_common_res_usage_state(priv)) { 1118df828598SMugunthan V N /* setup tx dma to fixed prio and zero offset */ 1119df828598SMugunthan V N cpdma_control_set(priv->dma, CPDMA_TX_PRIO_FIXED, 1); 1120df828598SMugunthan V N cpdma_control_set(priv->dma, CPDMA_RX_BUFFER_OFFSET, 0); 1121df828598SMugunthan V N 1122d9ba8f9eSMugunthan V N /* disable priority elevation */ 1123df828598SMugunthan V N __raw_writel(0, &priv->regs->ptype); 1124df828598SMugunthan V N 1125d9ba8f9eSMugunthan V N /* enable statistics collection only on all ports */ 1126df828598SMugunthan V N __raw_writel(0x7, &priv->regs->stat_port_en); 1127df828598SMugunthan V N 1128df828598SMugunthan V N if (WARN_ON(!priv->data.rx_descs)) 1129df828598SMugunthan V N priv->data.rx_descs = 128; 1130df828598SMugunthan V N 1131df828598SMugunthan V N for (i = 0; i < priv->data.rx_descs; i++) { 1132df828598SMugunthan V N struct sk_buff *skb; 1133df828598SMugunthan V N 1134df828598SMugunthan V N ret = -ENOMEM; 1135aacebbf8SSebastian Siewior skb = __netdev_alloc_skb_ip_align(priv->ndev, 1136aacebbf8SSebastian Siewior priv->rx_packet_max, GFP_KERNEL); 1137df828598SMugunthan V N if (!skb) 1138aacebbf8SSebastian Siewior goto err_cleanup; 1139df828598SMugunthan V N ret = cpdma_chan_submit(priv->rxch, skb, skb->data, 1140aef614e1SSebastian Siewior skb_tailroom(skb), 0); 1141aacebbf8SSebastian Siewior if (ret < 0) { 1142aacebbf8SSebastian Siewior kfree_skb(skb); 1143aacebbf8SSebastian Siewior goto err_cleanup; 1144aacebbf8SSebastian Siewior } 1145df828598SMugunthan V N } 1146d9ba8f9eSMugunthan V N /* continue even if we didn't manage to submit all 1147d9ba8f9eSMugunthan V N * receive descs 1148d9ba8f9eSMugunthan V N */ 1149df828598SMugunthan V N cpsw_info(priv, ifup, "submitted %d rx descriptors\n", i); 1150d9ba8f9eSMugunthan V N } 1151df828598SMugunthan V N 1152ff5b8ef2SMugunthan V N /* Enable Interrupt pacing if configured */ 1153ff5b8ef2SMugunthan V N if (priv->coal_intvl != 0) { 1154ff5b8ef2SMugunthan V N struct ethtool_coalesce coal; 1155ff5b8ef2SMugunthan V N 1156ff5b8ef2SMugunthan V N coal.rx_coalesce_usecs = (priv->coal_intvl << 4); 1157ff5b8ef2SMugunthan V N cpsw_set_coalesce(ndev, &coal); 1158ff5b8ef2SMugunthan V N } 1159ff5b8ef2SMugunthan V N 1160a11fbba9SSebastian Siewior prim_cpsw = cpsw_get_slave_priv(priv, 0); 1161a11fbba9SSebastian Siewior if (prim_cpsw->irq_enabled == false) { 1162a11fbba9SSebastian Siewior if ((priv == prim_cpsw) || !netif_running(prim_cpsw->ndev)) { 1163a11fbba9SSebastian Siewior prim_cpsw->irq_enabled = true; 1164a11fbba9SSebastian Siewior cpsw_enable_irq(prim_cpsw); 1165a11fbba9SSebastian Siewior } 1166a11fbba9SSebastian Siewior } 1167a11fbba9SSebastian Siewior 1168df828598SMugunthan V N cpdma_ctlr_start(priv->dma); 1169df828598SMugunthan V N cpsw_intr_enable(priv); 1170df828598SMugunthan V N napi_enable(&priv->napi); 1171510a1e72SMugunthan V N cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_RX); 1172510a1e72SMugunthan V N cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_TX); 1173df828598SMugunthan V N 1174d9ba8f9eSMugunthan V N if (priv->data.dual_emac) 1175d9ba8f9eSMugunthan V N priv->slaves[priv->emac_port].open_stat = true; 1176df828598SMugunthan V N return 0; 1177df828598SMugunthan V N 1178aacebbf8SSebastian Siewior err_cleanup: 1179aacebbf8SSebastian Siewior cpdma_ctlr_stop(priv->dma); 1180aacebbf8SSebastian Siewior for_each_slave(priv, cpsw_slave_stop, priv); 1181aacebbf8SSebastian Siewior pm_runtime_put_sync(&priv->pdev->dev); 1182aacebbf8SSebastian Siewior netif_carrier_off(priv->ndev); 1183aacebbf8SSebastian Siewior return ret; 1184df828598SMugunthan V N } 1185df828598SMugunthan V N 1186df828598SMugunthan V N static int cpsw_ndo_stop(struct net_device *ndev) 1187df828598SMugunthan V N { 1188df828598SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 1189df828598SMugunthan V N 1190df828598SMugunthan V N cpsw_info(priv, ifdown, "shutting down cpsw device\n"); 1191df828598SMugunthan V N netif_stop_queue(priv->ndev); 1192df828598SMugunthan V N napi_disable(&priv->napi); 1193df828598SMugunthan V N netif_carrier_off(priv->ndev); 1194d9ba8f9eSMugunthan V N 1195d9ba8f9eSMugunthan V N if (cpsw_common_res_usage_state(priv) <= 1) { 119671380f9bSMugunthan V N cpsw_intr_disable(priv); 119771380f9bSMugunthan V N cpdma_ctlr_int_ctrl(priv->dma, false); 119871380f9bSMugunthan V N cpdma_ctlr_stop(priv->dma); 1199df828598SMugunthan V N cpsw_ale_stop(priv->ale); 1200d9ba8f9eSMugunthan V N } 1201df828598SMugunthan V N for_each_slave(priv, cpsw_slave_stop, priv); 1202f150bd7fSMugunthan V N pm_runtime_put_sync(&priv->pdev->dev); 1203d9ba8f9eSMugunthan V N if (priv->data.dual_emac) 1204d9ba8f9eSMugunthan V N priv->slaves[priv->emac_port].open_stat = false; 1205df828598SMugunthan V N return 0; 1206df828598SMugunthan V N } 1207df828598SMugunthan V N 1208df828598SMugunthan V N static netdev_tx_t cpsw_ndo_start_xmit(struct sk_buff *skb, 1209df828598SMugunthan V N struct net_device *ndev) 1210df828598SMugunthan V N { 1211df828598SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 1212df828598SMugunthan V N int ret; 1213df828598SMugunthan V N 1214df828598SMugunthan V N ndev->trans_start = jiffies; 1215df828598SMugunthan V N 1216df828598SMugunthan V N if (skb_padto(skb, CPSW_MIN_PACKET_SIZE)) { 1217df828598SMugunthan V N cpsw_err(priv, tx_err, "packet pad failed\n"); 1218df828598SMugunthan V N priv->stats.tx_dropped++; 1219df828598SMugunthan V N return NETDEV_TX_OK; 1220df828598SMugunthan V N } 1221df828598SMugunthan V N 12229232b16dSMugunthan V N if (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP && 12239232b16dSMugunthan V N priv->cpts->tx_enable) 12242e5b38abSRichard Cochran skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 12252e5b38abSRichard Cochran 12262e5b38abSRichard Cochran skb_tx_timestamp(skb); 12272e5b38abSRichard Cochran 1228d9ba8f9eSMugunthan V N ret = cpsw_tx_packet_submit(ndev, priv, skb); 1229df828598SMugunthan V N if (unlikely(ret != 0)) { 1230df828598SMugunthan V N cpsw_err(priv, tx_err, "desc submit failed\n"); 1231df828598SMugunthan V N goto fail; 1232df828598SMugunthan V N } 1233df828598SMugunthan V N 1234fae50823SMugunthan V N /* If there is no more tx desc left free then we need to 1235fae50823SMugunthan V N * tell the kernel to stop sending us tx frames. 1236fae50823SMugunthan V N */ 1237d35162f8SDaniel Mack if (unlikely(!cpdma_check_free_tx_desc(priv->txch))) 1238fae50823SMugunthan V N netif_stop_queue(ndev); 1239fae50823SMugunthan V N 1240df828598SMugunthan V N return NETDEV_TX_OK; 1241df828598SMugunthan V N fail: 1242df828598SMugunthan V N priv->stats.tx_dropped++; 1243df828598SMugunthan V N netif_stop_queue(ndev); 1244df828598SMugunthan V N return NETDEV_TX_BUSY; 1245df828598SMugunthan V N } 1246df828598SMugunthan V N 1247df828598SMugunthan V N static void cpsw_ndo_change_rx_flags(struct net_device *ndev, int flags) 1248df828598SMugunthan V N { 1249df828598SMugunthan V N /* 1250df828598SMugunthan V N * The switch cannot operate in promiscuous mode without substantial 1251df828598SMugunthan V N * headache. For promiscuous mode to work, we would need to put the 1252df828598SMugunthan V N * ALE in bypass mode and route all traffic to the host port. 1253df828598SMugunthan V N * Subsequently, the host will need to operate as a "bridge", learn, 1254df828598SMugunthan V N * and flood as needed. For now, we simply complain here and 1255df828598SMugunthan V N * do nothing about it :-) 1256df828598SMugunthan V N */ 1257df828598SMugunthan V N if ((flags & IFF_PROMISC) && (ndev->flags & IFF_PROMISC)) 1258df828598SMugunthan V N dev_err(&ndev->dev, "promiscuity ignored!\n"); 1259df828598SMugunthan V N 1260df828598SMugunthan V N /* 1261df828598SMugunthan V N * The switch cannot filter multicast traffic unless it is configured 1262df828598SMugunthan V N * in "VLAN Aware" mode. Unfortunately, VLAN awareness requires a 1263df828598SMugunthan V N * whole bunch of additional logic that this driver does not implement 1264df828598SMugunthan V N * at present. 1265df828598SMugunthan V N */ 1266df828598SMugunthan V N if ((flags & IFF_ALLMULTI) && !(ndev->flags & IFF_ALLMULTI)) 1267df828598SMugunthan V N dev_err(&ndev->dev, "multicast traffic cannot be filtered!\n"); 1268df828598SMugunthan V N } 1269df828598SMugunthan V N 12702e5b38abSRichard Cochran #ifdef CONFIG_TI_CPTS 12712e5b38abSRichard Cochran 12722e5b38abSRichard Cochran static void cpsw_hwtstamp_v1(struct cpsw_priv *priv) 12732e5b38abSRichard Cochran { 1274e86ac13bSMugunthan V N struct cpsw_slave *slave = &priv->slaves[priv->data.active_slave]; 12752e5b38abSRichard Cochran u32 ts_en, seq_id; 12762e5b38abSRichard Cochran 12779232b16dSMugunthan V N if (!priv->cpts->tx_enable && !priv->cpts->rx_enable) { 12782e5b38abSRichard Cochran slave_write(slave, 0, CPSW1_TS_CTL); 12792e5b38abSRichard Cochran return; 12802e5b38abSRichard Cochran } 12812e5b38abSRichard Cochran 12822e5b38abSRichard Cochran seq_id = (30 << CPSW_V1_SEQ_ID_OFS_SHIFT) | ETH_P_1588; 12832e5b38abSRichard Cochran ts_en = EVENT_MSG_BITS << CPSW_V1_MSG_TYPE_OFS; 12842e5b38abSRichard Cochran 12859232b16dSMugunthan V N if (priv->cpts->tx_enable) 12862e5b38abSRichard Cochran ts_en |= CPSW_V1_TS_TX_EN; 12872e5b38abSRichard Cochran 12889232b16dSMugunthan V N if (priv->cpts->rx_enable) 12892e5b38abSRichard Cochran ts_en |= CPSW_V1_TS_RX_EN; 12902e5b38abSRichard Cochran 12912e5b38abSRichard Cochran slave_write(slave, ts_en, CPSW1_TS_CTL); 12922e5b38abSRichard Cochran slave_write(slave, seq_id, CPSW1_TS_SEQ_LTYPE); 12932e5b38abSRichard Cochran } 12942e5b38abSRichard Cochran 12952e5b38abSRichard Cochran static void cpsw_hwtstamp_v2(struct cpsw_priv *priv) 12962e5b38abSRichard Cochran { 1297d9ba8f9eSMugunthan V N struct cpsw_slave *slave; 12982e5b38abSRichard Cochran u32 ctrl, mtype; 12992e5b38abSRichard Cochran 1300d9ba8f9eSMugunthan V N if (priv->data.dual_emac) 1301d9ba8f9eSMugunthan V N slave = &priv->slaves[priv->emac_port]; 1302d9ba8f9eSMugunthan V N else 1303e86ac13bSMugunthan V N slave = &priv->slaves[priv->data.active_slave]; 1304d9ba8f9eSMugunthan V N 13052e5b38abSRichard Cochran ctrl = slave_read(slave, CPSW2_CONTROL); 13062e5b38abSRichard Cochran ctrl &= ~CTRL_ALL_TS_MASK; 13072e5b38abSRichard Cochran 13089232b16dSMugunthan V N if (priv->cpts->tx_enable) 13092e5b38abSRichard Cochran ctrl |= CTRL_TX_TS_BITS; 13102e5b38abSRichard Cochran 13119232b16dSMugunthan V N if (priv->cpts->rx_enable) 13122e5b38abSRichard Cochran ctrl |= CTRL_RX_TS_BITS; 13132e5b38abSRichard Cochran 13142e5b38abSRichard Cochran mtype = (30 << TS_SEQ_ID_OFFSET_SHIFT) | EVENT_MSG_BITS; 13152e5b38abSRichard Cochran 13162e5b38abSRichard Cochran slave_write(slave, mtype, CPSW2_TS_SEQ_MTYPE); 13172e5b38abSRichard Cochran slave_write(slave, ctrl, CPSW2_CONTROL); 13182e5b38abSRichard Cochran __raw_writel(ETH_P_1588, &priv->regs->ts_ltype); 13192e5b38abSRichard Cochran } 13202e5b38abSRichard Cochran 13213177bf6fSMugunthan V N static int cpsw_hwtstamp_ioctl(struct net_device *dev, struct ifreq *ifr) 13222e5b38abSRichard Cochran { 13233177bf6fSMugunthan V N struct cpsw_priv *priv = netdev_priv(dev); 13249232b16dSMugunthan V N struct cpts *cpts = priv->cpts; 13252e5b38abSRichard Cochran struct hwtstamp_config cfg; 13262e5b38abSRichard Cochran 13272e5b38abSRichard Cochran if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg))) 13282e5b38abSRichard Cochran return -EFAULT; 13292e5b38abSRichard Cochran 13302e5b38abSRichard Cochran /* reserved for future extensions */ 13312e5b38abSRichard Cochran if (cfg.flags) 13322e5b38abSRichard Cochran return -EINVAL; 13332e5b38abSRichard Cochran 13342e5b38abSRichard Cochran switch (cfg.tx_type) { 13352e5b38abSRichard Cochran case HWTSTAMP_TX_OFF: 13362e5b38abSRichard Cochran cpts->tx_enable = 0; 13372e5b38abSRichard Cochran break; 13382e5b38abSRichard Cochran case HWTSTAMP_TX_ON: 13392e5b38abSRichard Cochran cpts->tx_enable = 1; 13402e5b38abSRichard Cochran break; 13412e5b38abSRichard Cochran default: 13422e5b38abSRichard Cochran return -ERANGE; 13432e5b38abSRichard Cochran } 13442e5b38abSRichard Cochran 13452e5b38abSRichard Cochran switch (cfg.rx_filter) { 13462e5b38abSRichard Cochran case HWTSTAMP_FILTER_NONE: 13472e5b38abSRichard Cochran cpts->rx_enable = 0; 13482e5b38abSRichard Cochran break; 13492e5b38abSRichard Cochran case HWTSTAMP_FILTER_ALL: 13502e5b38abSRichard Cochran case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: 13512e5b38abSRichard Cochran case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: 13522e5b38abSRichard Cochran case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: 13532e5b38abSRichard Cochran return -ERANGE; 13542e5b38abSRichard Cochran case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: 13552e5b38abSRichard Cochran case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 13562e5b38abSRichard Cochran case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 13572e5b38abSRichard Cochran case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: 13582e5b38abSRichard Cochran case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: 13592e5b38abSRichard Cochran case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: 13602e5b38abSRichard Cochran case HWTSTAMP_FILTER_PTP_V2_EVENT: 13612e5b38abSRichard Cochran case HWTSTAMP_FILTER_PTP_V2_SYNC: 13622e5b38abSRichard Cochran case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 13632e5b38abSRichard Cochran cpts->rx_enable = 1; 13642e5b38abSRichard Cochran cfg.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT; 13652e5b38abSRichard Cochran break; 13662e5b38abSRichard Cochran default: 13672e5b38abSRichard Cochran return -ERANGE; 13682e5b38abSRichard Cochran } 13692e5b38abSRichard Cochran 13702e5b38abSRichard Cochran switch (priv->version) { 13712e5b38abSRichard Cochran case CPSW_VERSION_1: 13722e5b38abSRichard Cochran cpsw_hwtstamp_v1(priv); 13732e5b38abSRichard Cochran break; 13742e5b38abSRichard Cochran case CPSW_VERSION_2: 13752e5b38abSRichard Cochran cpsw_hwtstamp_v2(priv); 13762e5b38abSRichard Cochran break; 13772e5b38abSRichard Cochran default: 13782e5b38abSRichard Cochran return -ENOTSUPP; 13792e5b38abSRichard Cochran } 13802e5b38abSRichard Cochran 13812e5b38abSRichard Cochran return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0; 13822e5b38abSRichard Cochran } 13832e5b38abSRichard Cochran 13842e5b38abSRichard Cochran #endif /*CONFIG_TI_CPTS*/ 13852e5b38abSRichard Cochran 13862e5b38abSRichard Cochran static int cpsw_ndo_ioctl(struct net_device *dev, struct ifreq *req, int cmd) 13872e5b38abSRichard Cochran { 138811f2c988SMugunthan V N struct cpsw_priv *priv = netdev_priv(dev); 138911f2c988SMugunthan V N struct mii_ioctl_data *data = if_mii(req); 139011f2c988SMugunthan V N int slave_no = cpsw_slave_index(priv); 139111f2c988SMugunthan V N 13922e5b38abSRichard Cochran if (!netif_running(dev)) 13932e5b38abSRichard Cochran return -EINVAL; 13942e5b38abSRichard Cochran 139511f2c988SMugunthan V N switch (cmd) { 13962e5b38abSRichard Cochran #ifdef CONFIG_TI_CPTS 139711f2c988SMugunthan V N case SIOCSHWTSTAMP: 13983177bf6fSMugunthan V N return cpsw_hwtstamp_ioctl(dev, req); 13992e5b38abSRichard Cochran #endif 140011f2c988SMugunthan V N case SIOCGMIIPHY: 140111f2c988SMugunthan V N data->phy_id = priv->slaves[slave_no].phy->addr; 140211f2c988SMugunthan V N break; 140311f2c988SMugunthan V N default: 14042e5b38abSRichard Cochran return -ENOTSUPP; 14052e5b38abSRichard Cochran } 14062e5b38abSRichard Cochran 140711f2c988SMugunthan V N return 0; 140811f2c988SMugunthan V N } 140911f2c988SMugunthan V N 1410df828598SMugunthan V N static void cpsw_ndo_tx_timeout(struct net_device *ndev) 1411df828598SMugunthan V N { 1412df828598SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 1413df828598SMugunthan V N 1414df828598SMugunthan V N cpsw_err(priv, tx_err, "transmit timeout, restarting dma\n"); 1415df828598SMugunthan V N priv->stats.tx_errors++; 1416df828598SMugunthan V N cpsw_intr_disable(priv); 1417df828598SMugunthan V N cpdma_ctlr_int_ctrl(priv->dma, false); 1418df828598SMugunthan V N cpdma_chan_stop(priv->txch); 1419df828598SMugunthan V N cpdma_chan_start(priv->txch); 1420df828598SMugunthan V N cpdma_ctlr_int_ctrl(priv->dma, true); 1421df828598SMugunthan V N cpsw_intr_enable(priv); 1422510a1e72SMugunthan V N cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_RX); 1423510a1e72SMugunthan V N cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_TX); 1424510a1e72SMugunthan V N 1425df828598SMugunthan V N } 1426df828598SMugunthan V N 1427dcfd8d58SMugunthan V N static int cpsw_ndo_set_mac_address(struct net_device *ndev, void *p) 1428dcfd8d58SMugunthan V N { 1429dcfd8d58SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 1430dcfd8d58SMugunthan V N struct sockaddr *addr = (struct sockaddr *)p; 1431dcfd8d58SMugunthan V N int flags = 0; 1432dcfd8d58SMugunthan V N u16 vid = 0; 1433dcfd8d58SMugunthan V N 1434dcfd8d58SMugunthan V N if (!is_valid_ether_addr(addr->sa_data)) 1435dcfd8d58SMugunthan V N return -EADDRNOTAVAIL; 1436dcfd8d58SMugunthan V N 1437dcfd8d58SMugunthan V N if (priv->data.dual_emac) { 1438dcfd8d58SMugunthan V N vid = priv->slaves[priv->emac_port].port_vlan; 1439dcfd8d58SMugunthan V N flags = ALE_VLAN; 1440dcfd8d58SMugunthan V N } 1441dcfd8d58SMugunthan V N 1442dcfd8d58SMugunthan V N cpsw_ale_del_ucast(priv->ale, priv->mac_addr, priv->host_port, 1443dcfd8d58SMugunthan V N flags, vid); 1444dcfd8d58SMugunthan V N cpsw_ale_add_ucast(priv->ale, addr->sa_data, priv->host_port, 1445dcfd8d58SMugunthan V N flags, vid); 1446dcfd8d58SMugunthan V N 1447dcfd8d58SMugunthan V N memcpy(priv->mac_addr, addr->sa_data, ETH_ALEN); 1448dcfd8d58SMugunthan V N memcpy(ndev->dev_addr, priv->mac_addr, ETH_ALEN); 1449dcfd8d58SMugunthan V N for_each_slave(priv, cpsw_set_slave_mac, priv); 1450dcfd8d58SMugunthan V N 1451dcfd8d58SMugunthan V N return 0; 1452dcfd8d58SMugunthan V N } 1453dcfd8d58SMugunthan V N 1454df828598SMugunthan V N static struct net_device_stats *cpsw_ndo_get_stats(struct net_device *ndev) 1455df828598SMugunthan V N { 1456df828598SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 1457df828598SMugunthan V N return &priv->stats; 1458df828598SMugunthan V N } 1459df828598SMugunthan V N 1460df828598SMugunthan V N #ifdef CONFIG_NET_POLL_CONTROLLER 1461df828598SMugunthan V N static void cpsw_ndo_poll_controller(struct net_device *ndev) 1462df828598SMugunthan V N { 1463df828598SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 1464df828598SMugunthan V N 1465df828598SMugunthan V N cpsw_intr_disable(priv); 1466df828598SMugunthan V N cpdma_ctlr_int_ctrl(priv->dma, false); 1467df828598SMugunthan V N cpsw_interrupt(ndev->irq, priv); 1468df828598SMugunthan V N cpdma_ctlr_int_ctrl(priv->dma, true); 1469df828598SMugunthan V N cpsw_intr_enable(priv); 1470510a1e72SMugunthan V N cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_RX); 1471510a1e72SMugunthan V N cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_TX); 1472510a1e72SMugunthan V N 1473df828598SMugunthan V N } 1474df828598SMugunthan V N #endif 1475df828598SMugunthan V N 14763b72c2feSMugunthan V N static inline int cpsw_add_vlan_ale_entry(struct cpsw_priv *priv, 14773b72c2feSMugunthan V N unsigned short vid) 14783b72c2feSMugunthan V N { 14793b72c2feSMugunthan V N int ret; 14803b72c2feSMugunthan V N 14813b72c2feSMugunthan V N ret = cpsw_ale_add_vlan(priv->ale, vid, 14823b72c2feSMugunthan V N ALE_ALL_PORTS << priv->host_port, 14833b72c2feSMugunthan V N 0, ALE_ALL_PORTS << priv->host_port, 14843b72c2feSMugunthan V N (ALE_PORT_1 | ALE_PORT_2) << priv->host_port); 14853b72c2feSMugunthan V N if (ret != 0) 14863b72c2feSMugunthan V N return ret; 14873b72c2feSMugunthan V N 14883b72c2feSMugunthan V N ret = cpsw_ale_add_ucast(priv->ale, priv->mac_addr, 14893b72c2feSMugunthan V N priv->host_port, ALE_VLAN, vid); 14903b72c2feSMugunthan V N if (ret != 0) 14913b72c2feSMugunthan V N goto clean_vid; 14923b72c2feSMugunthan V N 14933b72c2feSMugunthan V N ret = cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast, 14943b72c2feSMugunthan V N ALE_ALL_PORTS << priv->host_port, 14953b72c2feSMugunthan V N ALE_VLAN, vid, 0); 14963b72c2feSMugunthan V N if (ret != 0) 14973b72c2feSMugunthan V N goto clean_vlan_ucast; 14983b72c2feSMugunthan V N return 0; 14993b72c2feSMugunthan V N 15003b72c2feSMugunthan V N clean_vlan_ucast: 15013b72c2feSMugunthan V N cpsw_ale_del_ucast(priv->ale, priv->mac_addr, 15023b72c2feSMugunthan V N priv->host_port, ALE_VLAN, vid); 15033b72c2feSMugunthan V N clean_vid: 15043b72c2feSMugunthan V N cpsw_ale_del_vlan(priv->ale, vid, 0); 15053b72c2feSMugunthan V N return ret; 15063b72c2feSMugunthan V N } 15073b72c2feSMugunthan V N 15083b72c2feSMugunthan V N static int cpsw_ndo_vlan_rx_add_vid(struct net_device *ndev, 150980d5c368SPatrick McHardy __be16 proto, u16 vid) 15103b72c2feSMugunthan V N { 15113b72c2feSMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 15123b72c2feSMugunthan V N 15133b72c2feSMugunthan V N if (vid == priv->data.default_vlan) 15143b72c2feSMugunthan V N return 0; 15153b72c2feSMugunthan V N 15163b72c2feSMugunthan V N dev_info(priv->dev, "Adding vlanid %d to vlan filter\n", vid); 15173b72c2feSMugunthan V N return cpsw_add_vlan_ale_entry(priv, vid); 15183b72c2feSMugunthan V N } 15193b72c2feSMugunthan V N 15203b72c2feSMugunthan V N static int cpsw_ndo_vlan_rx_kill_vid(struct net_device *ndev, 152180d5c368SPatrick McHardy __be16 proto, u16 vid) 15223b72c2feSMugunthan V N { 15233b72c2feSMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 15243b72c2feSMugunthan V N int ret; 15253b72c2feSMugunthan V N 15263b72c2feSMugunthan V N if (vid == priv->data.default_vlan) 15273b72c2feSMugunthan V N return 0; 15283b72c2feSMugunthan V N 15293b72c2feSMugunthan V N dev_info(priv->dev, "removing vlanid %d from vlan filter\n", vid); 15303b72c2feSMugunthan V N ret = cpsw_ale_del_vlan(priv->ale, vid, 0); 15313b72c2feSMugunthan V N if (ret != 0) 15323b72c2feSMugunthan V N return ret; 15333b72c2feSMugunthan V N 15343b72c2feSMugunthan V N ret = cpsw_ale_del_ucast(priv->ale, priv->mac_addr, 15353b72c2feSMugunthan V N priv->host_port, ALE_VLAN, vid); 15363b72c2feSMugunthan V N if (ret != 0) 15373b72c2feSMugunthan V N return ret; 15383b72c2feSMugunthan V N 15393b72c2feSMugunthan V N return cpsw_ale_del_mcast(priv->ale, priv->ndev->broadcast, 15403b72c2feSMugunthan V N 0, ALE_VLAN, vid); 15413b72c2feSMugunthan V N } 15423b72c2feSMugunthan V N 1543df828598SMugunthan V N static const struct net_device_ops cpsw_netdev_ops = { 1544df828598SMugunthan V N .ndo_open = cpsw_ndo_open, 1545df828598SMugunthan V N .ndo_stop = cpsw_ndo_stop, 1546df828598SMugunthan V N .ndo_start_xmit = cpsw_ndo_start_xmit, 1547df828598SMugunthan V N .ndo_change_rx_flags = cpsw_ndo_change_rx_flags, 1548dcfd8d58SMugunthan V N .ndo_set_mac_address = cpsw_ndo_set_mac_address, 15492e5b38abSRichard Cochran .ndo_do_ioctl = cpsw_ndo_ioctl, 1550df828598SMugunthan V N .ndo_validate_addr = eth_validate_addr, 15515c473ed2SDavid S. Miller .ndo_change_mtu = eth_change_mtu, 1552df828598SMugunthan V N .ndo_tx_timeout = cpsw_ndo_tx_timeout, 1553df828598SMugunthan V N .ndo_get_stats = cpsw_ndo_get_stats, 15545c50a856SMugunthan V N .ndo_set_rx_mode = cpsw_ndo_set_rx_mode, 1555df828598SMugunthan V N #ifdef CONFIG_NET_POLL_CONTROLLER 1556df828598SMugunthan V N .ndo_poll_controller = cpsw_ndo_poll_controller, 1557df828598SMugunthan V N #endif 15583b72c2feSMugunthan V N .ndo_vlan_rx_add_vid = cpsw_ndo_vlan_rx_add_vid, 15593b72c2feSMugunthan V N .ndo_vlan_rx_kill_vid = cpsw_ndo_vlan_rx_kill_vid, 1560df828598SMugunthan V N }; 1561df828598SMugunthan V N 1562df828598SMugunthan V N static void cpsw_get_drvinfo(struct net_device *ndev, 1563df828598SMugunthan V N struct ethtool_drvinfo *info) 1564df828598SMugunthan V N { 1565df828598SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 15667826d43fSJiri Pirko 15677826d43fSJiri Pirko strlcpy(info->driver, "TI CPSW Driver v1.0", sizeof(info->driver)); 15687826d43fSJiri Pirko strlcpy(info->version, "1.0", sizeof(info->version)); 15697826d43fSJiri Pirko strlcpy(info->bus_info, priv->pdev->name, sizeof(info->bus_info)); 1570df828598SMugunthan V N } 1571df828598SMugunthan V N 1572df828598SMugunthan V N static u32 cpsw_get_msglevel(struct net_device *ndev) 1573df828598SMugunthan V N { 1574df828598SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 1575df828598SMugunthan V N return priv->msg_enable; 1576df828598SMugunthan V N } 1577df828598SMugunthan V N 1578df828598SMugunthan V N static void cpsw_set_msglevel(struct net_device *ndev, u32 value) 1579df828598SMugunthan V N { 1580df828598SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 1581df828598SMugunthan V N priv->msg_enable = value; 1582df828598SMugunthan V N } 1583df828598SMugunthan V N 15842e5b38abSRichard Cochran static int cpsw_get_ts_info(struct net_device *ndev, 15852e5b38abSRichard Cochran struct ethtool_ts_info *info) 15862e5b38abSRichard Cochran { 15872e5b38abSRichard Cochran #ifdef CONFIG_TI_CPTS 15882e5b38abSRichard Cochran struct cpsw_priv *priv = netdev_priv(ndev); 15892e5b38abSRichard Cochran 15902e5b38abSRichard Cochran info->so_timestamping = 15912e5b38abSRichard Cochran SOF_TIMESTAMPING_TX_HARDWARE | 15922e5b38abSRichard Cochran SOF_TIMESTAMPING_TX_SOFTWARE | 15932e5b38abSRichard Cochran SOF_TIMESTAMPING_RX_HARDWARE | 15942e5b38abSRichard Cochran SOF_TIMESTAMPING_RX_SOFTWARE | 15952e5b38abSRichard Cochran SOF_TIMESTAMPING_SOFTWARE | 15962e5b38abSRichard Cochran SOF_TIMESTAMPING_RAW_HARDWARE; 15979232b16dSMugunthan V N info->phc_index = priv->cpts->phc_index; 15982e5b38abSRichard Cochran info->tx_types = 15992e5b38abSRichard Cochran (1 << HWTSTAMP_TX_OFF) | 16002e5b38abSRichard Cochran (1 << HWTSTAMP_TX_ON); 16012e5b38abSRichard Cochran info->rx_filters = 16022e5b38abSRichard Cochran (1 << HWTSTAMP_FILTER_NONE) | 16032e5b38abSRichard Cochran (1 << HWTSTAMP_FILTER_PTP_V2_EVENT); 16042e5b38abSRichard Cochran #else 16052e5b38abSRichard Cochran info->so_timestamping = 16062e5b38abSRichard Cochran SOF_TIMESTAMPING_TX_SOFTWARE | 16072e5b38abSRichard Cochran SOF_TIMESTAMPING_RX_SOFTWARE | 16082e5b38abSRichard Cochran SOF_TIMESTAMPING_SOFTWARE; 16092e5b38abSRichard Cochran info->phc_index = -1; 16102e5b38abSRichard Cochran info->tx_types = 0; 16112e5b38abSRichard Cochran info->rx_filters = 0; 16122e5b38abSRichard Cochran #endif 16132e5b38abSRichard Cochran return 0; 16142e5b38abSRichard Cochran } 16152e5b38abSRichard Cochran 1616d3bb9c58SMugunthan V N static int cpsw_get_settings(struct net_device *ndev, 1617d3bb9c58SMugunthan V N struct ethtool_cmd *ecmd) 1618d3bb9c58SMugunthan V N { 1619d3bb9c58SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 1620d3bb9c58SMugunthan V N int slave_no = cpsw_slave_index(priv); 1621d3bb9c58SMugunthan V N 1622d3bb9c58SMugunthan V N if (priv->slaves[slave_no].phy) 1623d3bb9c58SMugunthan V N return phy_ethtool_gset(priv->slaves[slave_no].phy, ecmd); 1624d3bb9c58SMugunthan V N else 1625d3bb9c58SMugunthan V N return -EOPNOTSUPP; 1626d3bb9c58SMugunthan V N } 1627d3bb9c58SMugunthan V N 1628d3bb9c58SMugunthan V N static int cpsw_set_settings(struct net_device *ndev, struct ethtool_cmd *ecmd) 1629d3bb9c58SMugunthan V N { 1630d3bb9c58SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 1631d3bb9c58SMugunthan V N int slave_no = cpsw_slave_index(priv); 1632d3bb9c58SMugunthan V N 1633d3bb9c58SMugunthan V N if (priv->slaves[slave_no].phy) 1634d3bb9c58SMugunthan V N return phy_ethtool_sset(priv->slaves[slave_no].phy, ecmd); 1635d3bb9c58SMugunthan V N else 1636d3bb9c58SMugunthan V N return -EOPNOTSUPP; 1637d3bb9c58SMugunthan V N } 1638d3bb9c58SMugunthan V N 1639df828598SMugunthan V N static const struct ethtool_ops cpsw_ethtool_ops = { 1640df828598SMugunthan V N .get_drvinfo = cpsw_get_drvinfo, 1641df828598SMugunthan V N .get_msglevel = cpsw_get_msglevel, 1642df828598SMugunthan V N .set_msglevel = cpsw_set_msglevel, 1643df828598SMugunthan V N .get_link = ethtool_op_get_link, 16442e5b38abSRichard Cochran .get_ts_info = cpsw_get_ts_info, 1645d3bb9c58SMugunthan V N .get_settings = cpsw_get_settings, 1646d3bb9c58SMugunthan V N .set_settings = cpsw_set_settings, 1647ff5b8ef2SMugunthan V N .get_coalesce = cpsw_get_coalesce, 1648ff5b8ef2SMugunthan V N .set_coalesce = cpsw_set_coalesce, 1649d9718546SMugunthan V N .get_sset_count = cpsw_get_sset_count, 1650d9718546SMugunthan V N .get_strings = cpsw_get_strings, 1651d9718546SMugunthan V N .get_ethtool_stats = cpsw_get_ethtool_stats, 1652df828598SMugunthan V N }; 1653df828598SMugunthan V N 1654549985eeSRichard Cochran static void cpsw_slave_init(struct cpsw_slave *slave, struct cpsw_priv *priv, 1655549985eeSRichard Cochran u32 slave_reg_ofs, u32 sliver_reg_ofs) 1656df828598SMugunthan V N { 1657df828598SMugunthan V N void __iomem *regs = priv->regs; 1658df828598SMugunthan V N int slave_num = slave->slave_num; 1659df828598SMugunthan V N struct cpsw_slave_data *data = priv->data.slave_data + slave_num; 1660df828598SMugunthan V N 1661df828598SMugunthan V N slave->data = data; 1662549985eeSRichard Cochran slave->regs = regs + slave_reg_ofs; 1663549985eeSRichard Cochran slave->sliver = regs + sliver_reg_ofs; 1664d9ba8f9eSMugunthan V N slave->port_vlan = data->dual_emac_res_vlan; 1665df828598SMugunthan V N } 1666df828598SMugunthan V N 16672eb32b0aSMugunthan V N static int cpsw_probe_dt(struct cpsw_platform_data *data, 16682eb32b0aSMugunthan V N struct platform_device *pdev) 16692eb32b0aSMugunthan V N { 16702eb32b0aSMugunthan V N struct device_node *node = pdev->dev.of_node; 16712eb32b0aSMugunthan V N struct device_node *slave_node; 16722eb32b0aSMugunthan V N int i = 0, ret; 16732eb32b0aSMugunthan V N u32 prop; 16742eb32b0aSMugunthan V N 16752eb32b0aSMugunthan V N if (!node) 16762eb32b0aSMugunthan V N return -EINVAL; 16772eb32b0aSMugunthan V N 16782eb32b0aSMugunthan V N if (of_property_read_u32(node, "slaves", &prop)) { 16792eb32b0aSMugunthan V N pr_err("Missing slaves property in the DT.\n"); 16802eb32b0aSMugunthan V N return -EINVAL; 16812eb32b0aSMugunthan V N } 16822eb32b0aSMugunthan V N data->slaves = prop; 16832eb32b0aSMugunthan V N 1684e86ac13bSMugunthan V N if (of_property_read_u32(node, "active_slave", &prop)) { 1685e86ac13bSMugunthan V N pr_err("Missing active_slave property in the DT.\n"); 168678ca0b28SRichard Cochran ret = -EINVAL; 168778ca0b28SRichard Cochran goto error_ret; 168878ca0b28SRichard Cochran } 1689e86ac13bSMugunthan V N data->active_slave = prop; 169078ca0b28SRichard Cochran 169100ab94eeSRichard Cochran if (of_property_read_u32(node, "cpts_clock_mult", &prop)) { 169200ab94eeSRichard Cochran pr_err("Missing cpts_clock_mult property in the DT.\n"); 169300ab94eeSRichard Cochran ret = -EINVAL; 169400ab94eeSRichard Cochran goto error_ret; 169500ab94eeSRichard Cochran } 169600ab94eeSRichard Cochran data->cpts_clock_mult = prop; 169700ab94eeSRichard Cochran 169800ab94eeSRichard Cochran if (of_property_read_u32(node, "cpts_clock_shift", &prop)) { 169900ab94eeSRichard Cochran pr_err("Missing cpts_clock_shift property in the DT.\n"); 170000ab94eeSRichard Cochran ret = -EINVAL; 170100ab94eeSRichard Cochran goto error_ret; 170200ab94eeSRichard Cochran } 170300ab94eeSRichard Cochran data->cpts_clock_shift = prop; 170400ab94eeSRichard Cochran 1705b2adaca9SJoe Perches data->slave_data = kcalloc(data->slaves, sizeof(struct cpsw_slave_data), 1706b2adaca9SJoe Perches GFP_KERNEL); 1707b2adaca9SJoe Perches if (!data->slave_data) 17082eb32b0aSMugunthan V N return -EINVAL; 17092eb32b0aSMugunthan V N 17102eb32b0aSMugunthan V N if (of_property_read_u32(node, "cpdma_channels", &prop)) { 17112eb32b0aSMugunthan V N pr_err("Missing cpdma_channels property in the DT.\n"); 17122eb32b0aSMugunthan V N ret = -EINVAL; 17132eb32b0aSMugunthan V N goto error_ret; 17142eb32b0aSMugunthan V N } 17152eb32b0aSMugunthan V N data->channels = prop; 17162eb32b0aSMugunthan V N 17172eb32b0aSMugunthan V N if (of_property_read_u32(node, "ale_entries", &prop)) { 17182eb32b0aSMugunthan V N pr_err("Missing ale_entries property in the DT.\n"); 17192eb32b0aSMugunthan V N ret = -EINVAL; 17202eb32b0aSMugunthan V N goto error_ret; 17212eb32b0aSMugunthan V N } 17222eb32b0aSMugunthan V N data->ale_entries = prop; 17232eb32b0aSMugunthan V N 17242eb32b0aSMugunthan V N if (of_property_read_u32(node, "bd_ram_size", &prop)) { 17252eb32b0aSMugunthan V N pr_err("Missing bd_ram_size property in the DT.\n"); 17262eb32b0aSMugunthan V N ret = -EINVAL; 17272eb32b0aSMugunthan V N goto error_ret; 17282eb32b0aSMugunthan V N } 17292eb32b0aSMugunthan V N data->bd_ram_size = prop; 17302eb32b0aSMugunthan V N 17312eb32b0aSMugunthan V N if (of_property_read_u32(node, "rx_descs", &prop)) { 17322eb32b0aSMugunthan V N pr_err("Missing rx_descs property in the DT.\n"); 17332eb32b0aSMugunthan V N ret = -EINVAL; 17342eb32b0aSMugunthan V N goto error_ret; 17352eb32b0aSMugunthan V N } 17362eb32b0aSMugunthan V N data->rx_descs = prop; 17372eb32b0aSMugunthan V N 17382eb32b0aSMugunthan V N if (of_property_read_u32(node, "mac_control", &prop)) { 17392eb32b0aSMugunthan V N pr_err("Missing mac_control property in the DT.\n"); 17402eb32b0aSMugunthan V N ret = -EINVAL; 17412eb32b0aSMugunthan V N goto error_ret; 17422eb32b0aSMugunthan V N } 17432eb32b0aSMugunthan V N data->mac_control = prop; 17442eb32b0aSMugunthan V N 1745d9ba8f9eSMugunthan V N if (!of_property_read_u32(node, "dual_emac", &prop)) 1746d9ba8f9eSMugunthan V N data->dual_emac = prop; 1747d9ba8f9eSMugunthan V N 17481fb19aa7SVaibhav Hiremath /* 17491fb19aa7SVaibhav Hiremath * Populate all the child nodes here... 17501fb19aa7SVaibhav Hiremath */ 17511fb19aa7SVaibhav Hiremath ret = of_platform_populate(node, NULL, NULL, &pdev->dev); 17521fb19aa7SVaibhav Hiremath /* We do not want to force this, as in some cases may not have child */ 17531fb19aa7SVaibhav Hiremath if (ret) 17541fb19aa7SVaibhav Hiremath pr_warn("Doesn't have any child node\n"); 17551fb19aa7SVaibhav Hiremath 1756549985eeSRichard Cochran for_each_node_by_name(slave_node, "slave") { 1757549985eeSRichard Cochran struct cpsw_slave_data *slave_data = data->slave_data + i; 1758549985eeSRichard Cochran const void *mac_addr = NULL; 1759549985eeSRichard Cochran u32 phyid; 1760549985eeSRichard Cochran int lenp; 1761549985eeSRichard Cochran const __be32 *parp; 1762549985eeSRichard Cochran struct device_node *mdio_node; 1763549985eeSRichard Cochran struct platform_device *mdio; 1764549985eeSRichard Cochran 1765549985eeSRichard Cochran parp = of_get_property(slave_node, "phy_id", &lenp); 1766ce16294fSLothar Waßmann if ((parp == NULL) || (lenp != (sizeof(void *) * 2))) { 1767549985eeSRichard Cochran pr_err("Missing slave[%d] phy_id property\n", i); 1768549985eeSRichard Cochran ret = -EINVAL; 1769549985eeSRichard Cochran goto error_ret; 1770549985eeSRichard Cochran } 1771549985eeSRichard Cochran mdio_node = of_find_node_by_phandle(be32_to_cpup(parp)); 1772549985eeSRichard Cochran phyid = be32_to_cpup(parp+1); 1773549985eeSRichard Cochran mdio = of_find_device_by_node(mdio_node); 1774549985eeSRichard Cochran snprintf(slave_data->phy_id, sizeof(slave_data->phy_id), 1775549985eeSRichard Cochran PHY_ID_FMT, mdio->name, phyid); 1776549985eeSRichard Cochran 1777549985eeSRichard Cochran mac_addr = of_get_mac_address(slave_node); 1778549985eeSRichard Cochran if (mac_addr) 1779549985eeSRichard Cochran memcpy(slave_data->mac_addr, mac_addr, ETH_ALEN); 1780549985eeSRichard Cochran 1781c5ceea7aSMugunthan V N slave_data->phy_if = of_get_phy_mode(slave_node); 1782c5ceea7aSMugunthan V N 1783d9ba8f9eSMugunthan V N if (data->dual_emac) { 178491c4166cSMugunthan V N if (of_property_read_u32(slave_node, "dual_emac_res_vlan", 1785d9ba8f9eSMugunthan V N &prop)) { 1786d9ba8f9eSMugunthan V N pr_err("Missing dual_emac_res_vlan in DT.\n"); 1787d9ba8f9eSMugunthan V N slave_data->dual_emac_res_vlan = i+1; 1788d9ba8f9eSMugunthan V N pr_err("Using %d as Reserved VLAN for %d slave\n", 1789d9ba8f9eSMugunthan V N slave_data->dual_emac_res_vlan, i); 1790d9ba8f9eSMugunthan V N } else { 1791d9ba8f9eSMugunthan V N slave_data->dual_emac_res_vlan = prop; 1792d9ba8f9eSMugunthan V N } 1793d9ba8f9eSMugunthan V N } 1794d9ba8f9eSMugunthan V N 1795549985eeSRichard Cochran i++; 1796549985eeSRichard Cochran } 1797549985eeSRichard Cochran 17982eb32b0aSMugunthan V N return 0; 17992eb32b0aSMugunthan V N 18002eb32b0aSMugunthan V N error_ret: 18012eb32b0aSMugunthan V N kfree(data->slave_data); 18022eb32b0aSMugunthan V N return ret; 18032eb32b0aSMugunthan V N } 18042eb32b0aSMugunthan V N 1805d9ba8f9eSMugunthan V N static int cpsw_probe_dual_emac(struct platform_device *pdev, 1806d9ba8f9eSMugunthan V N struct cpsw_priv *priv) 1807d9ba8f9eSMugunthan V N { 1808d9ba8f9eSMugunthan V N struct cpsw_platform_data *data = &priv->data; 1809d9ba8f9eSMugunthan V N struct net_device *ndev; 1810d9ba8f9eSMugunthan V N struct cpsw_priv *priv_sl2; 1811d9ba8f9eSMugunthan V N int ret = 0, i; 1812d9ba8f9eSMugunthan V N 1813d9ba8f9eSMugunthan V N ndev = alloc_etherdev(sizeof(struct cpsw_priv)); 1814d9ba8f9eSMugunthan V N if (!ndev) { 1815d9ba8f9eSMugunthan V N pr_err("cpsw: error allocating net_device\n"); 1816d9ba8f9eSMugunthan V N return -ENOMEM; 1817d9ba8f9eSMugunthan V N } 1818d9ba8f9eSMugunthan V N 1819d9ba8f9eSMugunthan V N priv_sl2 = netdev_priv(ndev); 1820d9ba8f9eSMugunthan V N spin_lock_init(&priv_sl2->lock); 1821d9ba8f9eSMugunthan V N priv_sl2->data = *data; 1822d9ba8f9eSMugunthan V N priv_sl2->pdev = pdev; 1823d9ba8f9eSMugunthan V N priv_sl2->ndev = ndev; 1824d9ba8f9eSMugunthan V N priv_sl2->dev = &ndev->dev; 1825d9ba8f9eSMugunthan V N priv_sl2->msg_enable = netif_msg_init(debug_level, CPSW_DEBUG); 1826d9ba8f9eSMugunthan V N priv_sl2->rx_packet_max = max(rx_packet_max, 128); 1827d9ba8f9eSMugunthan V N 1828d9ba8f9eSMugunthan V N if (is_valid_ether_addr(data->slave_data[1].mac_addr)) { 1829d9ba8f9eSMugunthan V N memcpy(priv_sl2->mac_addr, data->slave_data[1].mac_addr, 1830d9ba8f9eSMugunthan V N ETH_ALEN); 1831d9ba8f9eSMugunthan V N pr_info("cpsw: Detected MACID = %pM\n", priv_sl2->mac_addr); 1832d9ba8f9eSMugunthan V N } else { 1833d9ba8f9eSMugunthan V N random_ether_addr(priv_sl2->mac_addr); 1834d9ba8f9eSMugunthan V N pr_info("cpsw: Random MACID = %pM\n", priv_sl2->mac_addr); 1835d9ba8f9eSMugunthan V N } 1836d9ba8f9eSMugunthan V N memcpy(ndev->dev_addr, priv_sl2->mac_addr, ETH_ALEN); 1837d9ba8f9eSMugunthan V N 1838d9ba8f9eSMugunthan V N priv_sl2->slaves = priv->slaves; 1839d9ba8f9eSMugunthan V N priv_sl2->clk = priv->clk; 1840d9ba8f9eSMugunthan V N 1841ff5b8ef2SMugunthan V N priv_sl2->coal_intvl = 0; 1842ff5b8ef2SMugunthan V N priv_sl2->bus_freq_mhz = priv->bus_freq_mhz; 1843ff5b8ef2SMugunthan V N 1844d9ba8f9eSMugunthan V N priv_sl2->cpsw_res = priv->cpsw_res; 1845d9ba8f9eSMugunthan V N priv_sl2->regs = priv->regs; 1846d9ba8f9eSMugunthan V N priv_sl2->host_port = priv->host_port; 1847d9ba8f9eSMugunthan V N priv_sl2->host_port_regs = priv->host_port_regs; 1848d9ba8f9eSMugunthan V N priv_sl2->wr_regs = priv->wr_regs; 1849d9718546SMugunthan V N priv_sl2->hw_stats = priv->hw_stats; 1850d9ba8f9eSMugunthan V N priv_sl2->dma = priv->dma; 1851d9ba8f9eSMugunthan V N priv_sl2->txch = priv->txch; 1852d9ba8f9eSMugunthan V N priv_sl2->rxch = priv->rxch; 1853d9ba8f9eSMugunthan V N priv_sl2->ale = priv->ale; 1854d9ba8f9eSMugunthan V N priv_sl2->emac_port = 1; 1855d9ba8f9eSMugunthan V N priv->slaves[1].ndev = ndev; 1856d9ba8f9eSMugunthan V N priv_sl2->cpts = priv->cpts; 1857d9ba8f9eSMugunthan V N priv_sl2->version = priv->version; 1858d9ba8f9eSMugunthan V N 1859d9ba8f9eSMugunthan V N for (i = 0; i < priv->num_irqs; i++) { 1860d9ba8f9eSMugunthan V N priv_sl2->irqs_table[i] = priv->irqs_table[i]; 1861d9ba8f9eSMugunthan V N priv_sl2->num_irqs = priv->num_irqs; 1862d9ba8f9eSMugunthan V N } 1863f646968fSPatrick McHardy ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER; 1864d9ba8f9eSMugunthan V N 1865d9ba8f9eSMugunthan V N ndev->netdev_ops = &cpsw_netdev_ops; 1866d9ba8f9eSMugunthan V N SET_ETHTOOL_OPS(ndev, &cpsw_ethtool_ops); 1867d9ba8f9eSMugunthan V N netif_napi_add(ndev, &priv_sl2->napi, cpsw_poll, CPSW_POLL_WEIGHT); 1868d9ba8f9eSMugunthan V N 1869d9ba8f9eSMugunthan V N /* register the network device */ 1870d9ba8f9eSMugunthan V N SET_NETDEV_DEV(ndev, &pdev->dev); 1871d9ba8f9eSMugunthan V N ret = register_netdev(ndev); 1872d9ba8f9eSMugunthan V N if (ret) { 1873d9ba8f9eSMugunthan V N pr_err("cpsw: error registering net device\n"); 1874d9ba8f9eSMugunthan V N free_netdev(ndev); 1875d9ba8f9eSMugunthan V N ret = -ENODEV; 1876d9ba8f9eSMugunthan V N } 1877d9ba8f9eSMugunthan V N 1878d9ba8f9eSMugunthan V N return ret; 1879d9ba8f9eSMugunthan V N } 1880d9ba8f9eSMugunthan V N 1881663e12e6SBill Pemberton static int cpsw_probe(struct platform_device *pdev) 1882df828598SMugunthan V N { 1883d1bd9acfSSebastian Siewior struct cpsw_platform_data *data; 1884df828598SMugunthan V N struct net_device *ndev; 1885df828598SMugunthan V N struct cpsw_priv *priv; 1886df828598SMugunthan V N struct cpdma_params dma_params; 1887df828598SMugunthan V N struct cpsw_ale_params ale_params; 1888549985eeSRichard Cochran void __iomem *ss_regs, *wr_regs; 1889df828598SMugunthan V N struct resource *res; 1890549985eeSRichard Cochran u32 slave_offset, sliver_offset, slave_size; 1891df828598SMugunthan V N int ret = 0, i, k = 0; 1892df828598SMugunthan V N 1893df828598SMugunthan V N ndev = alloc_etherdev(sizeof(struct cpsw_priv)); 1894df828598SMugunthan V N if (!ndev) { 1895df828598SMugunthan V N pr_err("error allocating net_device\n"); 1896df828598SMugunthan V N return -ENOMEM; 1897df828598SMugunthan V N } 1898df828598SMugunthan V N 1899df828598SMugunthan V N platform_set_drvdata(pdev, ndev); 1900df828598SMugunthan V N priv = netdev_priv(ndev); 1901df828598SMugunthan V N spin_lock_init(&priv->lock); 1902df828598SMugunthan V N priv->pdev = pdev; 1903df828598SMugunthan V N priv->ndev = ndev; 1904df828598SMugunthan V N priv->dev = &ndev->dev; 1905df828598SMugunthan V N priv->msg_enable = netif_msg_init(debug_level, CPSW_DEBUG); 1906df828598SMugunthan V N priv->rx_packet_max = max(rx_packet_max, 128); 19079232b16dSMugunthan V N priv->cpts = devm_kzalloc(&pdev->dev, sizeof(struct cpts), GFP_KERNEL); 19087dcf313aSMugunthan V N priv->irq_enabled = true; 1909ab8e99d2SSebastian Siewior if (!priv->cpts) { 19109232b16dSMugunthan V N pr_err("error allocating cpts\n"); 19119232b16dSMugunthan V N goto clean_ndev_ret; 19129232b16dSMugunthan V N } 1913df828598SMugunthan V N 19141fb19aa7SVaibhav Hiremath /* 19151fb19aa7SVaibhav Hiremath * This may be required here for child devices. 19161fb19aa7SVaibhav Hiremath */ 19171fb19aa7SVaibhav Hiremath pm_runtime_enable(&pdev->dev); 19181fb19aa7SVaibhav Hiremath 1919739683b4SMugunthan V N /* Select default pin state */ 1920739683b4SMugunthan V N pinctrl_pm_select_default_state(&pdev->dev); 1921739683b4SMugunthan V N 19222eb32b0aSMugunthan V N if (cpsw_probe_dt(&priv->data, pdev)) { 19232eb32b0aSMugunthan V N pr_err("cpsw: platform data missing\n"); 19242eb32b0aSMugunthan V N ret = -ENODEV; 19252eb32b0aSMugunthan V N goto clean_ndev_ret; 19262eb32b0aSMugunthan V N } 19272eb32b0aSMugunthan V N data = &priv->data; 19282eb32b0aSMugunthan V N 1929df828598SMugunthan V N if (is_valid_ether_addr(data->slave_data[0].mac_addr)) { 1930df828598SMugunthan V N memcpy(priv->mac_addr, data->slave_data[0].mac_addr, ETH_ALEN); 1931cf6122beSDaniel Mack pr_info("Detected MACID = %pM\n", priv->mac_addr); 1932df828598SMugunthan V N } else { 19337efd26d0SJoe Perches eth_random_addr(priv->mac_addr); 1934cf6122beSDaniel Mack pr_info("Random MACID = %pM\n", priv->mac_addr); 1935df828598SMugunthan V N } 1936df828598SMugunthan V N 1937df828598SMugunthan V N memcpy(ndev->dev_addr, priv->mac_addr, ETH_ALEN); 1938df828598SMugunthan V N 1939df828598SMugunthan V N priv->slaves = kzalloc(sizeof(struct cpsw_slave) * data->slaves, 1940df828598SMugunthan V N GFP_KERNEL); 1941df828598SMugunthan V N if (!priv->slaves) { 1942df828598SMugunthan V N ret = -EBUSY; 1943df828598SMugunthan V N goto clean_ndev_ret; 1944df828598SMugunthan V N } 1945df828598SMugunthan V N for (i = 0; i < data->slaves; i++) 1946df828598SMugunthan V N priv->slaves[i].slave_num = i; 1947df828598SMugunthan V N 1948d9ba8f9eSMugunthan V N priv->slaves[0].ndev = ndev; 1949d9ba8f9eSMugunthan V N priv->emac_port = 0; 1950d9ba8f9eSMugunthan V N 1951f150bd7fSMugunthan V N priv->clk = clk_get(&pdev->dev, "fck"); 1952df828598SMugunthan V N if (IS_ERR(priv->clk)) { 1953f150bd7fSMugunthan V N dev_err(&pdev->dev, "fck is not found\n"); 1954f150bd7fSMugunthan V N ret = -ENODEV; 1955f150bd7fSMugunthan V N goto clean_slave_ret; 1956df828598SMugunthan V N } 1957ff5b8ef2SMugunthan V N priv->coal_intvl = 0; 1958ff5b8ef2SMugunthan V N priv->bus_freq_mhz = clk_get_rate(priv->clk) / 1000000; 1959df828598SMugunthan V N 1960df828598SMugunthan V N priv->cpsw_res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1961df828598SMugunthan V N if (!priv->cpsw_res) { 1962df828598SMugunthan V N dev_err(priv->dev, "error getting i/o resource\n"); 1963df828598SMugunthan V N ret = -ENOENT; 1964df828598SMugunthan V N goto clean_clk_ret; 1965df828598SMugunthan V N } 1966df828598SMugunthan V N if (!request_mem_region(priv->cpsw_res->start, 1967df828598SMugunthan V N resource_size(priv->cpsw_res), ndev->name)) { 1968df828598SMugunthan V N dev_err(priv->dev, "failed request i/o region\n"); 1969df828598SMugunthan V N ret = -ENXIO; 1970df828598SMugunthan V N goto clean_clk_ret; 1971df828598SMugunthan V N } 1972549985eeSRichard Cochran ss_regs = ioremap(priv->cpsw_res->start, resource_size(priv->cpsw_res)); 1973549985eeSRichard Cochran if (!ss_regs) { 1974df828598SMugunthan V N dev_err(priv->dev, "unable to map i/o region\n"); 1975df828598SMugunthan V N goto clean_cpsw_iores_ret; 1976df828598SMugunthan V N } 1977549985eeSRichard Cochran priv->regs = ss_regs; 1978549985eeSRichard Cochran priv->version = __raw_readl(&priv->regs->id_ver); 1979549985eeSRichard Cochran priv->host_port = HOST_PORT_NUM; 1980df828598SMugunthan V N 1981a65dd5b2SRichard Cochran priv->cpsw_wr_res = platform_get_resource(pdev, IORESOURCE_MEM, 1); 1982a65dd5b2SRichard Cochran if (!priv->cpsw_wr_res) { 1983df828598SMugunthan V N dev_err(priv->dev, "error getting i/o resource\n"); 1984df828598SMugunthan V N ret = -ENOENT; 19855250c969SRichard Cochran goto clean_iomap_ret; 1986df828598SMugunthan V N } 1987a65dd5b2SRichard Cochran if (!request_mem_region(priv->cpsw_wr_res->start, 1988a65dd5b2SRichard Cochran resource_size(priv->cpsw_wr_res), ndev->name)) { 1989df828598SMugunthan V N dev_err(priv->dev, "failed request i/o region\n"); 1990df828598SMugunthan V N ret = -ENXIO; 19915250c969SRichard Cochran goto clean_iomap_ret; 1992df828598SMugunthan V N } 1993549985eeSRichard Cochran wr_regs = ioremap(priv->cpsw_wr_res->start, 1994a65dd5b2SRichard Cochran resource_size(priv->cpsw_wr_res)); 1995549985eeSRichard Cochran if (!wr_regs) { 1996df828598SMugunthan V N dev_err(priv->dev, "unable to map i/o region\n"); 1997a65dd5b2SRichard Cochran goto clean_cpsw_wr_iores_ret; 1998df828598SMugunthan V N } 1999549985eeSRichard Cochran priv->wr_regs = wr_regs; 2000df828598SMugunthan V N 2001df828598SMugunthan V N memset(&dma_params, 0, sizeof(dma_params)); 2002549985eeSRichard Cochran memset(&ale_params, 0, sizeof(ale_params)); 2003549985eeSRichard Cochran 2004549985eeSRichard Cochran switch (priv->version) { 2005549985eeSRichard Cochran case CPSW_VERSION_1: 2006549985eeSRichard Cochran priv->host_port_regs = ss_regs + CPSW1_HOST_PORT_OFFSET; 20079232b16dSMugunthan V N priv->cpts->reg = ss_regs + CPSW1_CPTS_OFFSET; 2008d9718546SMugunthan V N priv->hw_stats = ss_regs + CPSW1_HW_STATS; 2009549985eeSRichard Cochran dma_params.dmaregs = ss_regs + CPSW1_CPDMA_OFFSET; 2010549985eeSRichard Cochran dma_params.txhdp = ss_regs + CPSW1_STATERAM_OFFSET; 2011549985eeSRichard Cochran ale_params.ale_regs = ss_regs + CPSW1_ALE_OFFSET; 2012549985eeSRichard Cochran slave_offset = CPSW1_SLAVE_OFFSET; 2013549985eeSRichard Cochran slave_size = CPSW1_SLAVE_SIZE; 2014549985eeSRichard Cochran sliver_offset = CPSW1_SLIVER_OFFSET; 2015549985eeSRichard Cochran dma_params.desc_mem_phys = 0; 2016549985eeSRichard Cochran break; 2017549985eeSRichard Cochran case CPSW_VERSION_2: 2018549985eeSRichard Cochran priv->host_port_regs = ss_regs + CPSW2_HOST_PORT_OFFSET; 20199232b16dSMugunthan V N priv->cpts->reg = ss_regs + CPSW2_CPTS_OFFSET; 2020d9718546SMugunthan V N priv->hw_stats = ss_regs + CPSW2_HW_STATS; 2021549985eeSRichard Cochran dma_params.dmaregs = ss_regs + CPSW2_CPDMA_OFFSET; 2022549985eeSRichard Cochran dma_params.txhdp = ss_regs + CPSW2_STATERAM_OFFSET; 2023549985eeSRichard Cochran ale_params.ale_regs = ss_regs + CPSW2_ALE_OFFSET; 2024549985eeSRichard Cochran slave_offset = CPSW2_SLAVE_OFFSET; 2025549985eeSRichard Cochran slave_size = CPSW2_SLAVE_SIZE; 2026549985eeSRichard Cochran sliver_offset = CPSW2_SLIVER_OFFSET; 2027549985eeSRichard Cochran dma_params.desc_mem_phys = 2028549985eeSRichard Cochran (u32 __force) priv->cpsw_res->start + CPSW2_BD_OFFSET; 2029549985eeSRichard Cochran break; 2030549985eeSRichard Cochran default: 2031549985eeSRichard Cochran dev_err(priv->dev, "unknown version 0x%08x\n", priv->version); 2032549985eeSRichard Cochran ret = -ENODEV; 2033549985eeSRichard Cochran goto clean_cpsw_wr_iores_ret; 2034549985eeSRichard Cochran } 2035549985eeSRichard Cochran for (i = 0; i < priv->data.slaves; i++) { 2036549985eeSRichard Cochran struct cpsw_slave *slave = &priv->slaves[i]; 2037549985eeSRichard Cochran cpsw_slave_init(slave, priv, slave_offset, sliver_offset); 2038549985eeSRichard Cochran slave_offset += slave_size; 2039549985eeSRichard Cochran sliver_offset += SLIVER_SIZE; 2040549985eeSRichard Cochran } 2041549985eeSRichard Cochran 2042df828598SMugunthan V N dma_params.dev = &pdev->dev; 2043549985eeSRichard Cochran dma_params.rxthresh = dma_params.dmaregs + CPDMA_RXTHRESH; 2044549985eeSRichard Cochran dma_params.rxfree = dma_params.dmaregs + CPDMA_RXFREE; 2045549985eeSRichard Cochran dma_params.rxhdp = dma_params.txhdp + CPDMA_RXHDP; 2046549985eeSRichard Cochran dma_params.txcp = dma_params.txhdp + CPDMA_TXCP; 2047549985eeSRichard Cochran dma_params.rxcp = dma_params.txhdp + CPDMA_RXCP; 2048df828598SMugunthan V N 2049df828598SMugunthan V N dma_params.num_chan = data->channels; 2050df828598SMugunthan V N dma_params.has_soft_reset = true; 2051df828598SMugunthan V N dma_params.min_packet_size = CPSW_MIN_PACKET_SIZE; 2052df828598SMugunthan V N dma_params.desc_mem_size = data->bd_ram_size; 2053df828598SMugunthan V N dma_params.desc_align = 16; 2054df828598SMugunthan V N dma_params.has_ext_regs = true; 2055549985eeSRichard Cochran dma_params.desc_hw_addr = dma_params.desc_mem_phys; 2056df828598SMugunthan V N 2057df828598SMugunthan V N priv->dma = cpdma_ctlr_create(&dma_params); 2058df828598SMugunthan V N if (!priv->dma) { 2059df828598SMugunthan V N dev_err(priv->dev, "error initializing dma\n"); 2060df828598SMugunthan V N ret = -ENOMEM; 20615250c969SRichard Cochran goto clean_wr_iomap_ret; 2062df828598SMugunthan V N } 2063df828598SMugunthan V N 2064df828598SMugunthan V N priv->txch = cpdma_chan_create(priv->dma, tx_chan_num(0), 2065df828598SMugunthan V N cpsw_tx_handler); 2066df828598SMugunthan V N priv->rxch = cpdma_chan_create(priv->dma, rx_chan_num(0), 2067df828598SMugunthan V N cpsw_rx_handler); 2068df828598SMugunthan V N 2069df828598SMugunthan V N if (WARN_ON(!priv->txch || !priv->rxch)) { 2070df828598SMugunthan V N dev_err(priv->dev, "error initializing dma channels\n"); 2071df828598SMugunthan V N ret = -ENOMEM; 2072df828598SMugunthan V N goto clean_dma_ret; 2073df828598SMugunthan V N } 2074df828598SMugunthan V N 2075df828598SMugunthan V N ale_params.dev = &ndev->dev; 2076df828598SMugunthan V N ale_params.ale_ageout = ale_ageout; 2077df828598SMugunthan V N ale_params.ale_entries = data->ale_entries; 2078df828598SMugunthan V N ale_params.ale_ports = data->slaves; 2079df828598SMugunthan V N 2080df828598SMugunthan V N priv->ale = cpsw_ale_create(&ale_params); 2081df828598SMugunthan V N if (!priv->ale) { 2082df828598SMugunthan V N dev_err(priv->dev, "error initializing ale engine\n"); 2083df828598SMugunthan V N ret = -ENODEV; 2084df828598SMugunthan V N goto clean_dma_ret; 2085df828598SMugunthan V N } 2086df828598SMugunthan V N 2087df828598SMugunthan V N ndev->irq = platform_get_irq(pdev, 0); 2088df828598SMugunthan V N if (ndev->irq < 0) { 2089df828598SMugunthan V N dev_err(priv->dev, "error getting irq resource\n"); 2090df828598SMugunthan V N ret = -ENOENT; 2091df828598SMugunthan V N goto clean_ale_ret; 2092df828598SMugunthan V N } 2093df828598SMugunthan V N 2094df828598SMugunthan V N while ((res = platform_get_resource(priv->pdev, IORESOURCE_IRQ, k))) { 2095df828598SMugunthan V N for (i = res->start; i <= res->end; i++) { 2096df828598SMugunthan V N if (request_irq(i, cpsw_interrupt, IRQF_DISABLED, 2097df828598SMugunthan V N dev_name(&pdev->dev), priv)) { 2098df828598SMugunthan V N dev_err(priv->dev, "error attaching irq\n"); 2099df828598SMugunthan V N goto clean_ale_ret; 2100df828598SMugunthan V N } 2101df828598SMugunthan V N priv->irqs_table[k] = i; 2102d1bd9acfSSebastian Siewior priv->num_irqs = k + 1; 2103df828598SMugunthan V N } 2104df828598SMugunthan V N k++; 2105df828598SMugunthan V N } 2106df828598SMugunthan V N 2107f646968fSPatrick McHardy ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER; 2108df828598SMugunthan V N 2109df828598SMugunthan V N ndev->netdev_ops = &cpsw_netdev_ops; 2110df828598SMugunthan V N SET_ETHTOOL_OPS(ndev, &cpsw_ethtool_ops); 2111df828598SMugunthan V N netif_napi_add(ndev, &priv->napi, cpsw_poll, CPSW_POLL_WEIGHT); 2112df828598SMugunthan V N 2113df828598SMugunthan V N /* register the network device */ 2114df828598SMugunthan V N SET_NETDEV_DEV(ndev, &pdev->dev); 2115df828598SMugunthan V N ret = register_netdev(ndev); 2116df828598SMugunthan V N if (ret) { 2117df828598SMugunthan V N dev_err(priv->dev, "error registering net device\n"); 2118df828598SMugunthan V N ret = -ENODEV; 2119df828598SMugunthan V N goto clean_irq_ret; 2120df828598SMugunthan V N } 2121df828598SMugunthan V N 21229232b16dSMugunthan V N if (cpts_register(&pdev->dev, priv->cpts, 21232e5b38abSRichard Cochran data->cpts_clock_mult, data->cpts_clock_shift)) 21242e5b38abSRichard Cochran dev_err(priv->dev, "error registering cpts device\n"); 21252e5b38abSRichard Cochran 2126df828598SMugunthan V N cpsw_notice(priv, probe, "initialized device (regs %x, irq %d)\n", 2127df828598SMugunthan V N priv->cpsw_res->start, ndev->irq); 2128df828598SMugunthan V N 2129d9ba8f9eSMugunthan V N if (priv->data.dual_emac) { 2130d9ba8f9eSMugunthan V N ret = cpsw_probe_dual_emac(pdev, priv); 2131d9ba8f9eSMugunthan V N if (ret) { 2132d9ba8f9eSMugunthan V N cpsw_err(priv, probe, "error probe slave 2 emac interface\n"); 2133d9ba8f9eSMugunthan V N goto clean_irq_ret; 2134d9ba8f9eSMugunthan V N } 2135d9ba8f9eSMugunthan V N } 2136d9ba8f9eSMugunthan V N 2137df828598SMugunthan V N return 0; 2138df828598SMugunthan V N 2139df828598SMugunthan V N clean_irq_ret: 2140d1bd9acfSSebastian Siewior for (i = 0; i < priv->num_irqs; i++) 2141d1bd9acfSSebastian Siewior free_irq(priv->irqs_table[i], priv); 2142df828598SMugunthan V N clean_ale_ret: 2143df828598SMugunthan V N cpsw_ale_destroy(priv->ale); 2144df828598SMugunthan V N clean_dma_ret: 2145df828598SMugunthan V N cpdma_chan_destroy(priv->txch); 2146df828598SMugunthan V N cpdma_chan_destroy(priv->rxch); 2147df828598SMugunthan V N cpdma_ctlr_destroy(priv->dma); 21485250c969SRichard Cochran clean_wr_iomap_ret: 21495250c969SRichard Cochran iounmap(priv->wr_regs); 2150a65dd5b2SRichard Cochran clean_cpsw_wr_iores_ret: 2151a65dd5b2SRichard Cochran release_mem_region(priv->cpsw_wr_res->start, 2152a65dd5b2SRichard Cochran resource_size(priv->cpsw_wr_res)); 21535250c969SRichard Cochran clean_iomap_ret: 21545250c969SRichard Cochran iounmap(priv->regs); 2155df828598SMugunthan V N clean_cpsw_iores_ret: 2156df828598SMugunthan V N release_mem_region(priv->cpsw_res->start, 2157df828598SMugunthan V N resource_size(priv->cpsw_res)); 2158df828598SMugunthan V N clean_clk_ret: 2159df828598SMugunthan V N clk_put(priv->clk); 2160f150bd7fSMugunthan V N clean_slave_ret: 2161f150bd7fSMugunthan V N pm_runtime_disable(&pdev->dev); 2162df828598SMugunthan V N kfree(priv->slaves); 2163df828598SMugunthan V N clean_ndev_ret: 2164d1bd9acfSSebastian Siewior kfree(priv->data.slave_data); 2165d1bd9acfSSebastian Siewior free_netdev(priv->ndev); 2166df828598SMugunthan V N return ret; 2167df828598SMugunthan V N } 2168df828598SMugunthan V N 2169663e12e6SBill Pemberton static int cpsw_remove(struct platform_device *pdev) 2170df828598SMugunthan V N { 2171df828598SMugunthan V N struct net_device *ndev = platform_get_drvdata(pdev); 2172df828598SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 2173d1bd9acfSSebastian Siewior int i; 2174df828598SMugunthan V N 2175d1bd9acfSSebastian Siewior if (priv->data.dual_emac) 2176d1bd9acfSSebastian Siewior unregister_netdev(cpsw_get_slave_ndev(priv, 1)); 2177d1bd9acfSSebastian Siewior unregister_netdev(ndev); 2178df828598SMugunthan V N 21799232b16dSMugunthan V N cpts_unregister(priv->cpts); 2180d1bd9acfSSebastian Siewior for (i = 0; i < priv->num_irqs; i++) 2181d1bd9acfSSebastian Siewior free_irq(priv->irqs_table[i], priv); 2182d1bd9acfSSebastian Siewior 2183df828598SMugunthan V N cpsw_ale_destroy(priv->ale); 2184df828598SMugunthan V N cpdma_chan_destroy(priv->txch); 2185df828598SMugunthan V N cpdma_chan_destroy(priv->rxch); 2186df828598SMugunthan V N cpdma_ctlr_destroy(priv->dma); 2187df828598SMugunthan V N iounmap(priv->regs); 2188df828598SMugunthan V N release_mem_region(priv->cpsw_res->start, 2189df828598SMugunthan V N resource_size(priv->cpsw_res)); 21905250c969SRichard Cochran iounmap(priv->wr_regs); 2191a65dd5b2SRichard Cochran release_mem_region(priv->cpsw_wr_res->start, 2192a65dd5b2SRichard Cochran resource_size(priv->cpsw_wr_res)); 2193f150bd7fSMugunthan V N pm_runtime_disable(&pdev->dev); 2194df828598SMugunthan V N clk_put(priv->clk); 2195df828598SMugunthan V N kfree(priv->slaves); 2196d1bd9acfSSebastian Siewior kfree(priv->data.slave_data); 2197d1bd9acfSSebastian Siewior if (priv->data.dual_emac) 2198d1bd9acfSSebastian Siewior free_netdev(cpsw_get_slave_ndev(priv, 1)); 2199df828598SMugunthan V N free_netdev(ndev); 2200df828598SMugunthan V N return 0; 2201df828598SMugunthan V N } 2202df828598SMugunthan V N 2203df828598SMugunthan V N static int cpsw_suspend(struct device *dev) 2204df828598SMugunthan V N { 2205df828598SMugunthan V N struct platform_device *pdev = to_platform_device(dev); 2206df828598SMugunthan V N struct net_device *ndev = platform_get_drvdata(pdev); 2207b90fc27aSMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 2208df828598SMugunthan V N 2209df828598SMugunthan V N if (netif_running(ndev)) 2210df828598SMugunthan V N cpsw_ndo_stop(ndev); 22116d3d76f8SMugunthan V N soft_reset("sliver 0", &priv->slaves[0].sliver->soft_reset); 22126d3d76f8SMugunthan V N soft_reset("sliver 1", &priv->slaves[1].sliver->soft_reset); 2213f150bd7fSMugunthan V N pm_runtime_put_sync(&pdev->dev); 2214f150bd7fSMugunthan V N 2215739683b4SMugunthan V N /* Select sleep pin state */ 2216739683b4SMugunthan V N pinctrl_pm_select_sleep_state(&pdev->dev); 2217739683b4SMugunthan V N 2218df828598SMugunthan V N return 0; 2219df828598SMugunthan V N } 2220df828598SMugunthan V N 2221df828598SMugunthan V N static int cpsw_resume(struct device *dev) 2222df828598SMugunthan V N { 2223df828598SMugunthan V N struct platform_device *pdev = to_platform_device(dev); 2224df828598SMugunthan V N struct net_device *ndev = platform_get_drvdata(pdev); 2225df828598SMugunthan V N 2226f150bd7fSMugunthan V N pm_runtime_get_sync(&pdev->dev); 2227739683b4SMugunthan V N 2228739683b4SMugunthan V N /* Select default pin state */ 2229739683b4SMugunthan V N pinctrl_pm_select_default_state(&pdev->dev); 2230739683b4SMugunthan V N 2231df828598SMugunthan V N if (netif_running(ndev)) 2232df828598SMugunthan V N cpsw_ndo_open(ndev); 2233df828598SMugunthan V N return 0; 2234df828598SMugunthan V N } 2235df828598SMugunthan V N 2236df828598SMugunthan V N static const struct dev_pm_ops cpsw_pm_ops = { 2237df828598SMugunthan V N .suspend = cpsw_suspend, 2238df828598SMugunthan V N .resume = cpsw_resume, 2239df828598SMugunthan V N }; 2240df828598SMugunthan V N 22412eb32b0aSMugunthan V N static const struct of_device_id cpsw_of_mtable[] = { 22422eb32b0aSMugunthan V N { .compatible = "ti,cpsw", }, 22432eb32b0aSMugunthan V N { /* sentinel */ }, 22442eb32b0aSMugunthan V N }; 22454bc21d41SSebastian Siewior MODULE_DEVICE_TABLE(of, cpsw_of_mtable); 22462eb32b0aSMugunthan V N 2247df828598SMugunthan V N static struct platform_driver cpsw_driver = { 2248df828598SMugunthan V N .driver = { 2249df828598SMugunthan V N .name = "cpsw", 2250df828598SMugunthan V N .owner = THIS_MODULE, 2251df828598SMugunthan V N .pm = &cpsw_pm_ops, 22522eb32b0aSMugunthan V N .of_match_table = of_match_ptr(cpsw_of_mtable), 2253df828598SMugunthan V N }, 2254df828598SMugunthan V N .probe = cpsw_probe, 2255663e12e6SBill Pemberton .remove = cpsw_remove, 2256df828598SMugunthan V N }; 2257df828598SMugunthan V N 2258df828598SMugunthan V N static int __init cpsw_init(void) 2259df828598SMugunthan V N { 2260df828598SMugunthan V N return platform_driver_register(&cpsw_driver); 2261df828598SMugunthan V N } 2262df828598SMugunthan V N late_initcall(cpsw_init); 2263df828598SMugunthan V N 2264df828598SMugunthan V N static void __exit cpsw_exit(void) 2265df828598SMugunthan V N { 2266df828598SMugunthan V N platform_driver_unregister(&cpsw_driver); 2267df828598SMugunthan V N } 2268df828598SMugunthan V N module_exit(cpsw_exit); 2269df828598SMugunthan V N 2270df828598SMugunthan V N MODULE_LICENSE("GPL"); 2271df828598SMugunthan V N MODULE_AUTHOR("Cyril Chemparathy <cyril@ti.com>"); 2272df828598SMugunthan V N MODULE_AUTHOR("Mugunthan V N <mugunthanvnm@ti.com>"); 2273df828598SMugunthan V N MODULE_DESCRIPTION("TI CPSW Ethernet driver"); 2274