1df828598SMugunthan V N /* 2df828598SMugunthan V N * Texas Instruments Ethernet Switch Driver 3df828598SMugunthan V N * 4df828598SMugunthan V N * Copyright (C) 2012 Texas Instruments 5df828598SMugunthan V N * 6df828598SMugunthan V N * This program is free software; you can redistribute it and/or 7df828598SMugunthan V N * modify it under the terms of the GNU General Public License as 8df828598SMugunthan V N * published by the Free Software Foundation version 2. 9df828598SMugunthan V N * 10df828598SMugunthan V N * This program is distributed "as is" WITHOUT ANY WARRANTY of any 11df828598SMugunthan V N * kind, whether express or implied; without even the implied warranty 12df828598SMugunthan V N * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13df828598SMugunthan V N * GNU General Public License for more details. 14df828598SMugunthan V N */ 15df828598SMugunthan V N 16df828598SMugunthan V N #include <linux/kernel.h> 17df828598SMugunthan V N #include <linux/io.h> 18df828598SMugunthan V N #include <linux/clk.h> 19df828598SMugunthan V N #include <linux/timer.h> 20df828598SMugunthan V N #include <linux/module.h> 21df828598SMugunthan V N #include <linux/platform_device.h> 22df828598SMugunthan V N #include <linux/irqreturn.h> 23df828598SMugunthan V N #include <linux/interrupt.h> 24df828598SMugunthan V N #include <linux/if_ether.h> 25df828598SMugunthan V N #include <linux/etherdevice.h> 26df828598SMugunthan V N #include <linux/netdevice.h> 272e5b38abSRichard Cochran #include <linux/net_tstamp.h> 28df828598SMugunthan V N #include <linux/phy.h> 29df828598SMugunthan V N #include <linux/workqueue.h> 30df828598SMugunthan V N #include <linux/delay.h> 31f150bd7fSMugunthan V N #include <linux/pm_runtime.h> 322eb32b0aSMugunthan V N #include <linux/of.h> 332eb32b0aSMugunthan V N #include <linux/of_net.h> 342eb32b0aSMugunthan V N #include <linux/of_device.h> 353b72c2feSMugunthan V N #include <linux/if_vlan.h> 36df828598SMugunthan V N 37df828598SMugunthan V N #include <linux/platform_data/cpsw.h> 38739683b4SMugunthan V N #include <linux/pinctrl/consumer.h> 39df828598SMugunthan V N 40df828598SMugunthan V N #include "cpsw_ale.h" 412e5b38abSRichard Cochran #include "cpts.h" 42df828598SMugunthan V N #include "davinci_cpdma.h" 43df828598SMugunthan V N 44df828598SMugunthan V N #define CPSW_DEBUG (NETIF_MSG_HW | NETIF_MSG_WOL | \ 45df828598SMugunthan V N NETIF_MSG_DRV | NETIF_MSG_LINK | \ 46df828598SMugunthan V N NETIF_MSG_IFUP | NETIF_MSG_INTR | \ 47df828598SMugunthan V N NETIF_MSG_PROBE | NETIF_MSG_TIMER | \ 48df828598SMugunthan V N NETIF_MSG_IFDOWN | NETIF_MSG_RX_ERR | \ 49df828598SMugunthan V N NETIF_MSG_TX_ERR | NETIF_MSG_TX_DONE | \ 50df828598SMugunthan V N NETIF_MSG_PKTDATA | NETIF_MSG_TX_QUEUED | \ 51df828598SMugunthan V N NETIF_MSG_RX_STATUS) 52df828598SMugunthan V N 53df828598SMugunthan V N #define cpsw_info(priv, type, format, ...) \ 54df828598SMugunthan V N do { \ 55df828598SMugunthan V N if (netif_msg_##type(priv) && net_ratelimit()) \ 56df828598SMugunthan V N dev_info(priv->dev, format, ## __VA_ARGS__); \ 57df828598SMugunthan V N } while (0) 58df828598SMugunthan V N 59df828598SMugunthan V N #define cpsw_err(priv, type, format, ...) \ 60df828598SMugunthan V N do { \ 61df828598SMugunthan V N if (netif_msg_##type(priv) && net_ratelimit()) \ 62df828598SMugunthan V N dev_err(priv->dev, format, ## __VA_ARGS__); \ 63df828598SMugunthan V N } while (0) 64df828598SMugunthan V N 65df828598SMugunthan V N #define cpsw_dbg(priv, type, format, ...) \ 66df828598SMugunthan V N do { \ 67df828598SMugunthan V N if (netif_msg_##type(priv) && net_ratelimit()) \ 68df828598SMugunthan V N dev_dbg(priv->dev, format, ## __VA_ARGS__); \ 69df828598SMugunthan V N } while (0) 70df828598SMugunthan V N 71df828598SMugunthan V N #define cpsw_notice(priv, type, format, ...) \ 72df828598SMugunthan V N do { \ 73df828598SMugunthan V N if (netif_msg_##type(priv) && net_ratelimit()) \ 74df828598SMugunthan V N dev_notice(priv->dev, format, ## __VA_ARGS__); \ 75df828598SMugunthan V N } while (0) 76df828598SMugunthan V N 775c50a856SMugunthan V N #define ALE_ALL_PORTS 0x7 785c50a856SMugunthan V N 79df828598SMugunthan V N #define CPSW_MAJOR_VERSION(reg) (reg >> 8 & 0x7) 80df828598SMugunthan V N #define CPSW_MINOR_VERSION(reg) (reg & 0xff) 81df828598SMugunthan V N #define CPSW_RTL_VERSION(reg) ((reg >> 11) & 0x1f) 82df828598SMugunthan V N 83e90cfac6SRichard Cochran #define CPSW_VERSION_1 0x19010a 84e90cfac6SRichard Cochran #define CPSW_VERSION_2 0x19010c 85c193f365SMugunthan V N #define CPSW_VERSION_3 0x19010f 86549985eeSRichard Cochran 87549985eeSRichard Cochran #define HOST_PORT_NUM 0 88549985eeSRichard Cochran #define SLIVER_SIZE 0x40 89549985eeSRichard Cochran 90549985eeSRichard Cochran #define CPSW1_HOST_PORT_OFFSET 0x028 91549985eeSRichard Cochran #define CPSW1_SLAVE_OFFSET 0x050 92549985eeSRichard Cochran #define CPSW1_SLAVE_SIZE 0x040 93549985eeSRichard Cochran #define CPSW1_CPDMA_OFFSET 0x100 94549985eeSRichard Cochran #define CPSW1_STATERAM_OFFSET 0x200 95d9718546SMugunthan V N #define CPSW1_HW_STATS 0x400 96549985eeSRichard Cochran #define CPSW1_CPTS_OFFSET 0x500 97549985eeSRichard Cochran #define CPSW1_ALE_OFFSET 0x600 98549985eeSRichard Cochran #define CPSW1_SLIVER_OFFSET 0x700 99549985eeSRichard Cochran 100549985eeSRichard Cochran #define CPSW2_HOST_PORT_OFFSET 0x108 101549985eeSRichard Cochran #define CPSW2_SLAVE_OFFSET 0x200 102549985eeSRichard Cochran #define CPSW2_SLAVE_SIZE 0x100 103549985eeSRichard Cochran #define CPSW2_CPDMA_OFFSET 0x800 104d9718546SMugunthan V N #define CPSW2_HW_STATS 0x900 105549985eeSRichard Cochran #define CPSW2_STATERAM_OFFSET 0xa00 106549985eeSRichard Cochran #define CPSW2_CPTS_OFFSET 0xc00 107549985eeSRichard Cochran #define CPSW2_ALE_OFFSET 0xd00 108549985eeSRichard Cochran #define CPSW2_SLIVER_OFFSET 0xd80 109549985eeSRichard Cochran #define CPSW2_BD_OFFSET 0x2000 110549985eeSRichard Cochran 111df828598SMugunthan V N #define CPDMA_RXTHRESH 0x0c0 112df828598SMugunthan V N #define CPDMA_RXFREE 0x0e0 113df828598SMugunthan V N #define CPDMA_TXHDP 0x00 114df828598SMugunthan V N #define CPDMA_RXHDP 0x20 115df828598SMugunthan V N #define CPDMA_TXCP 0x40 116df828598SMugunthan V N #define CPDMA_RXCP 0x60 117df828598SMugunthan V N 118df828598SMugunthan V N #define CPSW_POLL_WEIGHT 64 119df828598SMugunthan V N #define CPSW_MIN_PACKET_SIZE 60 120df828598SMugunthan V N #define CPSW_MAX_PACKET_SIZE (1500 + 14 + 4 + 4) 121df828598SMugunthan V N 122df828598SMugunthan V N #define RX_PRIORITY_MAPPING 0x76543210 123df828598SMugunthan V N #define TX_PRIORITY_MAPPING 0x33221100 124df828598SMugunthan V N #define CPDMA_TX_PRIORITY_MAP 0x76543210 125df828598SMugunthan V N 1263b72c2feSMugunthan V N #define CPSW_VLAN_AWARE BIT(1) 1273b72c2feSMugunthan V N #define CPSW_ALE_VLAN_AWARE 1 1283b72c2feSMugunthan V N 129d9ba8f9eSMugunthan V N #define CPSW_FIFO_NORMAL_MODE (0 << 15) 130d9ba8f9eSMugunthan V N #define CPSW_FIFO_DUAL_MAC_MODE (1 << 15) 131d9ba8f9eSMugunthan V N #define CPSW_FIFO_RATE_LIMIT_MODE (2 << 15) 132d9ba8f9eSMugunthan V N 133ff5b8ef2SMugunthan V N #define CPSW_INTPACEEN (0x3f << 16) 134ff5b8ef2SMugunthan V N #define CPSW_INTPRESCALE_MASK (0x7FF << 0) 135ff5b8ef2SMugunthan V N #define CPSW_CMINTMAX_CNT 63 136ff5b8ef2SMugunthan V N #define CPSW_CMINTMIN_CNT 2 137ff5b8ef2SMugunthan V N #define CPSW_CMINTMAX_INTVL (1000 / CPSW_CMINTMIN_CNT) 138ff5b8ef2SMugunthan V N #define CPSW_CMINTMIN_INTVL ((1000 / CPSW_CMINTMAX_CNT) + 1) 139ff5b8ef2SMugunthan V N 140df828598SMugunthan V N #define cpsw_enable_irq(priv) \ 141df828598SMugunthan V N do { \ 142df828598SMugunthan V N u32 i; \ 143df828598SMugunthan V N for (i = 0; i < priv->num_irqs; i++) \ 144df828598SMugunthan V N enable_irq(priv->irqs_table[i]); \ 145df828598SMugunthan V N } while (0); 146df828598SMugunthan V N #define cpsw_disable_irq(priv) \ 147df828598SMugunthan V N do { \ 148df828598SMugunthan V N u32 i; \ 149df828598SMugunthan V N for (i = 0; i < priv->num_irqs; i++) \ 150df828598SMugunthan V N disable_irq_nosync(priv->irqs_table[i]); \ 151df828598SMugunthan V N } while (0); 152df828598SMugunthan V N 153d3bb9c58SMugunthan V N #define cpsw_slave_index(priv) \ 154d3bb9c58SMugunthan V N ((priv->data.dual_emac) ? priv->emac_port : \ 155d3bb9c58SMugunthan V N priv->data.active_slave) 156d3bb9c58SMugunthan V N 157df828598SMugunthan V N static int debug_level; 158df828598SMugunthan V N module_param(debug_level, int, 0); 159df828598SMugunthan V N MODULE_PARM_DESC(debug_level, "cpsw debug level (NETIF_MSG bits)"); 160df828598SMugunthan V N 161df828598SMugunthan V N static int ale_ageout = 10; 162df828598SMugunthan V N module_param(ale_ageout, int, 0); 163df828598SMugunthan V N MODULE_PARM_DESC(ale_ageout, "cpsw ale ageout interval (seconds)"); 164df828598SMugunthan V N 165df828598SMugunthan V N static int rx_packet_max = CPSW_MAX_PACKET_SIZE; 166df828598SMugunthan V N module_param(rx_packet_max, int, 0); 167df828598SMugunthan V N MODULE_PARM_DESC(rx_packet_max, "maximum receive packet size (bytes)"); 168df828598SMugunthan V N 169996a5c27SRichard Cochran struct cpsw_wr_regs { 170df828598SMugunthan V N u32 id_ver; 171df828598SMugunthan V N u32 soft_reset; 172df828598SMugunthan V N u32 control; 173df828598SMugunthan V N u32 int_control; 174df828598SMugunthan V N u32 rx_thresh_en; 175df828598SMugunthan V N u32 rx_en; 176df828598SMugunthan V N u32 tx_en; 177df828598SMugunthan V N u32 misc_en; 178ff5b8ef2SMugunthan V N u32 mem_allign1[8]; 179ff5b8ef2SMugunthan V N u32 rx_thresh_stat; 180ff5b8ef2SMugunthan V N u32 rx_stat; 181ff5b8ef2SMugunthan V N u32 tx_stat; 182ff5b8ef2SMugunthan V N u32 misc_stat; 183ff5b8ef2SMugunthan V N u32 mem_allign2[8]; 184ff5b8ef2SMugunthan V N u32 rx_imax; 185ff5b8ef2SMugunthan V N u32 tx_imax; 186ff5b8ef2SMugunthan V N 187df828598SMugunthan V N }; 188df828598SMugunthan V N 189996a5c27SRichard Cochran struct cpsw_ss_regs { 190df828598SMugunthan V N u32 id_ver; 191df828598SMugunthan V N u32 control; 192df828598SMugunthan V N u32 soft_reset; 193df828598SMugunthan V N u32 stat_port_en; 194df828598SMugunthan V N u32 ptype; 195bd357af2SRichard Cochran u32 soft_idle; 196bd357af2SRichard Cochran u32 thru_rate; 197bd357af2SRichard Cochran u32 gap_thresh; 198bd357af2SRichard Cochran u32 tx_start_wds; 199bd357af2SRichard Cochran u32 flow_control; 200bd357af2SRichard Cochran u32 vlan_ltype; 201bd357af2SRichard Cochran u32 ts_ltype; 202bd357af2SRichard Cochran u32 dlr_ltype; 203df828598SMugunthan V N }; 204df828598SMugunthan V N 2059750a3adSRichard Cochran /* CPSW_PORT_V1 */ 2069750a3adSRichard Cochran #define CPSW1_MAX_BLKS 0x00 /* Maximum FIFO Blocks */ 2079750a3adSRichard Cochran #define CPSW1_BLK_CNT 0x04 /* FIFO Block Usage Count (Read Only) */ 2089750a3adSRichard Cochran #define CPSW1_TX_IN_CTL 0x08 /* Transmit FIFO Control */ 2099750a3adSRichard Cochran #define CPSW1_PORT_VLAN 0x0c /* VLAN Register */ 2109750a3adSRichard Cochran #define CPSW1_TX_PRI_MAP 0x10 /* Tx Header Priority to Switch Pri Mapping */ 2119750a3adSRichard Cochran #define CPSW1_TS_CTL 0x14 /* Time Sync Control */ 2129750a3adSRichard Cochran #define CPSW1_TS_SEQ_LTYPE 0x18 /* Time Sync Sequence ID Offset and Msg Type */ 2139750a3adSRichard Cochran #define CPSW1_TS_VLAN 0x1c /* Time Sync VLAN1 and VLAN2 */ 2149750a3adSRichard Cochran 2159750a3adSRichard Cochran /* CPSW_PORT_V2 */ 2169750a3adSRichard Cochran #define CPSW2_CONTROL 0x00 /* Control Register */ 2179750a3adSRichard Cochran #define CPSW2_MAX_BLKS 0x08 /* Maximum FIFO Blocks */ 2189750a3adSRichard Cochran #define CPSW2_BLK_CNT 0x0c /* FIFO Block Usage Count (Read Only) */ 2199750a3adSRichard Cochran #define CPSW2_TX_IN_CTL 0x10 /* Transmit FIFO Control */ 2209750a3adSRichard Cochran #define CPSW2_PORT_VLAN 0x14 /* VLAN Register */ 2219750a3adSRichard Cochran #define CPSW2_TX_PRI_MAP 0x18 /* Tx Header Priority to Switch Pri Mapping */ 2229750a3adSRichard Cochran #define CPSW2_TS_SEQ_MTYPE 0x1c /* Time Sync Sequence ID Offset and Msg Type */ 2239750a3adSRichard Cochran 2249750a3adSRichard Cochran /* CPSW_PORT_V1 and V2 */ 2259750a3adSRichard Cochran #define SA_LO 0x20 /* CPGMAC_SL Source Address Low */ 2269750a3adSRichard Cochran #define SA_HI 0x24 /* CPGMAC_SL Source Address High */ 2279750a3adSRichard Cochran #define SEND_PERCENT 0x28 /* Transmit Queue Send Percentages */ 2289750a3adSRichard Cochran 2299750a3adSRichard Cochran /* CPSW_PORT_V2 only */ 2309750a3adSRichard Cochran #define RX_DSCP_PRI_MAP0 0x30 /* Rx DSCP Priority to Rx Packet Mapping */ 2319750a3adSRichard Cochran #define RX_DSCP_PRI_MAP1 0x34 /* Rx DSCP Priority to Rx Packet Mapping */ 2329750a3adSRichard Cochran #define RX_DSCP_PRI_MAP2 0x38 /* Rx DSCP Priority to Rx Packet Mapping */ 2339750a3adSRichard Cochran #define RX_DSCP_PRI_MAP3 0x3c /* Rx DSCP Priority to Rx Packet Mapping */ 2349750a3adSRichard Cochran #define RX_DSCP_PRI_MAP4 0x40 /* Rx DSCP Priority to Rx Packet Mapping */ 2359750a3adSRichard Cochran #define RX_DSCP_PRI_MAP5 0x44 /* Rx DSCP Priority to Rx Packet Mapping */ 2369750a3adSRichard Cochran #define RX_DSCP_PRI_MAP6 0x48 /* Rx DSCP Priority to Rx Packet Mapping */ 2379750a3adSRichard Cochran #define RX_DSCP_PRI_MAP7 0x4c /* Rx DSCP Priority to Rx Packet Mapping */ 2389750a3adSRichard Cochran 2399750a3adSRichard Cochran /* Bit definitions for the CPSW2_CONTROL register */ 2409750a3adSRichard Cochran #define PASS_PRI_TAGGED (1<<24) /* Pass Priority Tagged */ 2419750a3adSRichard Cochran #define VLAN_LTYPE2_EN (1<<21) /* VLAN LTYPE 2 enable */ 2429750a3adSRichard Cochran #define VLAN_LTYPE1_EN (1<<20) /* VLAN LTYPE 1 enable */ 2439750a3adSRichard Cochran #define DSCP_PRI_EN (1<<16) /* DSCP Priority Enable */ 2449750a3adSRichard Cochran #define TS_320 (1<<14) /* Time Sync Dest Port 320 enable */ 2459750a3adSRichard Cochran #define TS_319 (1<<13) /* Time Sync Dest Port 319 enable */ 2469750a3adSRichard Cochran #define TS_132 (1<<12) /* Time Sync Dest IP Addr 132 enable */ 2479750a3adSRichard Cochran #define TS_131 (1<<11) /* Time Sync Dest IP Addr 131 enable */ 2489750a3adSRichard Cochran #define TS_130 (1<<10) /* Time Sync Dest IP Addr 130 enable */ 2499750a3adSRichard Cochran #define TS_129 (1<<9) /* Time Sync Dest IP Addr 129 enable */ 2509750a3adSRichard Cochran #define TS_BIT8 (1<<8) /* ts_ttl_nonzero? */ 2519750a3adSRichard Cochran #define TS_ANNEX_D_EN (1<<4) /* Time Sync Annex D enable */ 2529750a3adSRichard Cochran #define TS_LTYPE2_EN (1<<3) /* Time Sync LTYPE 2 enable */ 2539750a3adSRichard Cochran #define TS_LTYPE1_EN (1<<2) /* Time Sync LTYPE 1 enable */ 2549750a3adSRichard Cochran #define TS_TX_EN (1<<1) /* Time Sync Transmit Enable */ 2559750a3adSRichard Cochran #define TS_RX_EN (1<<0) /* Time Sync Receive Enable */ 2569750a3adSRichard Cochran 2579750a3adSRichard Cochran #define CTRL_TS_BITS \ 2589750a3adSRichard Cochran (TS_320 | TS_319 | TS_132 | TS_131 | TS_130 | TS_129 | TS_BIT8 | \ 2599750a3adSRichard Cochran TS_ANNEX_D_EN | TS_LTYPE1_EN) 2609750a3adSRichard Cochran 2619750a3adSRichard Cochran #define CTRL_ALL_TS_MASK (CTRL_TS_BITS | TS_TX_EN | TS_RX_EN) 2629750a3adSRichard Cochran #define CTRL_TX_TS_BITS (CTRL_TS_BITS | TS_TX_EN) 2639750a3adSRichard Cochran #define CTRL_RX_TS_BITS (CTRL_TS_BITS | TS_RX_EN) 2649750a3adSRichard Cochran 2659750a3adSRichard Cochran /* Bit definitions for the CPSW2_TS_SEQ_MTYPE register */ 2669750a3adSRichard Cochran #define TS_SEQ_ID_OFFSET_SHIFT (16) /* Time Sync Sequence ID Offset */ 2679750a3adSRichard Cochran #define TS_SEQ_ID_OFFSET_MASK (0x3f) 2689750a3adSRichard Cochran #define TS_MSG_TYPE_EN_SHIFT (0) /* Time Sync Message Type Enable */ 2699750a3adSRichard Cochran #define TS_MSG_TYPE_EN_MASK (0xffff) 2709750a3adSRichard Cochran 2719750a3adSRichard Cochran /* The PTP event messages - Sync, Delay_Req, Pdelay_Req, and Pdelay_Resp. */ 2729750a3adSRichard Cochran #define EVENT_MSG_BITS ((1<<0) | (1<<1) | (1<<2) | (1<<3)) 273df828598SMugunthan V N 2742e5b38abSRichard Cochran /* Bit definitions for the CPSW1_TS_CTL register */ 2752e5b38abSRichard Cochran #define CPSW_V1_TS_RX_EN BIT(0) 2762e5b38abSRichard Cochran #define CPSW_V1_TS_TX_EN BIT(4) 2772e5b38abSRichard Cochran #define CPSW_V1_MSG_TYPE_OFS 16 2782e5b38abSRichard Cochran 2792e5b38abSRichard Cochran /* Bit definitions for the CPSW1_TS_SEQ_LTYPE register */ 2802e5b38abSRichard Cochran #define CPSW_V1_SEQ_ID_OFS_SHIFT 16 2812e5b38abSRichard Cochran 282df828598SMugunthan V N struct cpsw_host_regs { 283df828598SMugunthan V N u32 max_blks; 284df828598SMugunthan V N u32 blk_cnt; 285d9ba8f9eSMugunthan V N u32 tx_in_ctl; 286df828598SMugunthan V N u32 port_vlan; 287df828598SMugunthan V N u32 tx_pri_map; 288df828598SMugunthan V N u32 cpdma_tx_pri_map; 289df828598SMugunthan V N u32 cpdma_rx_chan_map; 290df828598SMugunthan V N }; 291df828598SMugunthan V N 292df828598SMugunthan V N struct cpsw_sliver_regs { 293df828598SMugunthan V N u32 id_ver; 294df828598SMugunthan V N u32 mac_control; 295df828598SMugunthan V N u32 mac_status; 296df828598SMugunthan V N u32 soft_reset; 297df828598SMugunthan V N u32 rx_maxlen; 298df828598SMugunthan V N u32 __reserved_0; 299df828598SMugunthan V N u32 rx_pause; 300df828598SMugunthan V N u32 tx_pause; 301df828598SMugunthan V N u32 __reserved_1; 302df828598SMugunthan V N u32 rx_pri_map; 303df828598SMugunthan V N }; 304df828598SMugunthan V N 305d9718546SMugunthan V N struct cpsw_hw_stats { 306d9718546SMugunthan V N u32 rxgoodframes; 307d9718546SMugunthan V N u32 rxbroadcastframes; 308d9718546SMugunthan V N u32 rxmulticastframes; 309d9718546SMugunthan V N u32 rxpauseframes; 310d9718546SMugunthan V N u32 rxcrcerrors; 311d9718546SMugunthan V N u32 rxaligncodeerrors; 312d9718546SMugunthan V N u32 rxoversizedframes; 313d9718546SMugunthan V N u32 rxjabberframes; 314d9718546SMugunthan V N u32 rxundersizedframes; 315d9718546SMugunthan V N u32 rxfragments; 316d9718546SMugunthan V N u32 __pad_0[2]; 317d9718546SMugunthan V N u32 rxoctets; 318d9718546SMugunthan V N u32 txgoodframes; 319d9718546SMugunthan V N u32 txbroadcastframes; 320d9718546SMugunthan V N u32 txmulticastframes; 321d9718546SMugunthan V N u32 txpauseframes; 322d9718546SMugunthan V N u32 txdeferredframes; 323d9718546SMugunthan V N u32 txcollisionframes; 324d9718546SMugunthan V N u32 txsinglecollframes; 325d9718546SMugunthan V N u32 txmultcollframes; 326d9718546SMugunthan V N u32 txexcessivecollisions; 327d9718546SMugunthan V N u32 txlatecollisions; 328d9718546SMugunthan V N u32 txunderrun; 329d9718546SMugunthan V N u32 txcarriersenseerrors; 330d9718546SMugunthan V N u32 txoctets; 331d9718546SMugunthan V N u32 octetframes64; 332d9718546SMugunthan V N u32 octetframes65t127; 333d9718546SMugunthan V N u32 octetframes128t255; 334d9718546SMugunthan V N u32 octetframes256t511; 335d9718546SMugunthan V N u32 octetframes512t1023; 336d9718546SMugunthan V N u32 octetframes1024tup; 337d9718546SMugunthan V N u32 netoctets; 338d9718546SMugunthan V N u32 rxsofoverruns; 339d9718546SMugunthan V N u32 rxmofoverruns; 340d9718546SMugunthan V N u32 rxdmaoverruns; 341d9718546SMugunthan V N }; 342d9718546SMugunthan V N 343df828598SMugunthan V N struct cpsw_slave { 3449750a3adSRichard Cochran void __iomem *regs; 345df828598SMugunthan V N struct cpsw_sliver_regs __iomem *sliver; 346df828598SMugunthan V N int slave_num; 347df828598SMugunthan V N u32 mac_control; 348df828598SMugunthan V N struct cpsw_slave_data *data; 349df828598SMugunthan V N struct phy_device *phy; 350d9ba8f9eSMugunthan V N struct net_device *ndev; 351d9ba8f9eSMugunthan V N u32 port_vlan; 352d9ba8f9eSMugunthan V N u32 open_stat; 353df828598SMugunthan V N }; 354df828598SMugunthan V N 3559750a3adSRichard Cochran static inline u32 slave_read(struct cpsw_slave *slave, u32 offset) 3569750a3adSRichard Cochran { 3579750a3adSRichard Cochran return __raw_readl(slave->regs + offset); 3589750a3adSRichard Cochran } 3599750a3adSRichard Cochran 3609750a3adSRichard Cochran static inline void slave_write(struct cpsw_slave *slave, u32 val, u32 offset) 3619750a3adSRichard Cochran { 3629750a3adSRichard Cochran __raw_writel(val, slave->regs + offset); 3639750a3adSRichard Cochran } 3649750a3adSRichard Cochran 365df828598SMugunthan V N struct cpsw_priv { 366df828598SMugunthan V N spinlock_t lock; 367df828598SMugunthan V N struct platform_device *pdev; 368df828598SMugunthan V N struct net_device *ndev; 369df828598SMugunthan V N struct resource *cpsw_res; 370a65dd5b2SRichard Cochran struct resource *cpsw_wr_res; 371df828598SMugunthan V N struct napi_struct napi; 372df828598SMugunthan V N struct device *dev; 373df828598SMugunthan V N struct cpsw_platform_data data; 374996a5c27SRichard Cochran struct cpsw_ss_regs __iomem *regs; 375996a5c27SRichard Cochran struct cpsw_wr_regs __iomem *wr_regs; 376d9718546SMugunthan V N u8 __iomem *hw_stats; 377df828598SMugunthan V N struct cpsw_host_regs __iomem *host_port_regs; 378df828598SMugunthan V N u32 msg_enable; 379e90cfac6SRichard Cochran u32 version; 380ff5b8ef2SMugunthan V N u32 coal_intvl; 381ff5b8ef2SMugunthan V N u32 bus_freq_mhz; 382df828598SMugunthan V N struct net_device_stats stats; 383df828598SMugunthan V N int rx_packet_max; 384df828598SMugunthan V N int host_port; 385df828598SMugunthan V N struct clk *clk; 386df828598SMugunthan V N u8 mac_addr[ETH_ALEN]; 387df828598SMugunthan V N struct cpsw_slave *slaves; 388df828598SMugunthan V N struct cpdma_ctlr *dma; 389df828598SMugunthan V N struct cpdma_chan *txch, *rxch; 390df828598SMugunthan V N struct cpsw_ale *ale; 391df828598SMugunthan V N /* snapshot of IRQ numbers */ 392df828598SMugunthan V N u32 irqs_table[4]; 393df828598SMugunthan V N u32 num_irqs; 394a11fbba9SSebastian Siewior bool irq_enabled; 3959232b16dSMugunthan V N struct cpts *cpts; 396d9ba8f9eSMugunthan V N u32 emac_port; 397df828598SMugunthan V N }; 398df828598SMugunthan V N 399d9718546SMugunthan V N struct cpsw_stats { 400d9718546SMugunthan V N char stat_string[ETH_GSTRING_LEN]; 401d9718546SMugunthan V N int type; 402d9718546SMugunthan V N int sizeof_stat; 403d9718546SMugunthan V N int stat_offset; 404d9718546SMugunthan V N }; 405d9718546SMugunthan V N 406d9718546SMugunthan V N enum { 407d9718546SMugunthan V N CPSW_STATS, 408d9718546SMugunthan V N CPDMA_RX_STATS, 409d9718546SMugunthan V N CPDMA_TX_STATS, 410d9718546SMugunthan V N }; 411d9718546SMugunthan V N 412d9718546SMugunthan V N #define CPSW_STAT(m) CPSW_STATS, \ 413d9718546SMugunthan V N sizeof(((struct cpsw_hw_stats *)0)->m), \ 414d9718546SMugunthan V N offsetof(struct cpsw_hw_stats, m) 415d9718546SMugunthan V N #define CPDMA_RX_STAT(m) CPDMA_RX_STATS, \ 416d9718546SMugunthan V N sizeof(((struct cpdma_chan_stats *)0)->m), \ 417d9718546SMugunthan V N offsetof(struct cpdma_chan_stats, m) 418d9718546SMugunthan V N #define CPDMA_TX_STAT(m) CPDMA_TX_STATS, \ 419d9718546SMugunthan V N sizeof(((struct cpdma_chan_stats *)0)->m), \ 420d9718546SMugunthan V N offsetof(struct cpdma_chan_stats, m) 421d9718546SMugunthan V N 422d9718546SMugunthan V N static const struct cpsw_stats cpsw_gstrings_stats[] = { 423d9718546SMugunthan V N { "Good Rx Frames", CPSW_STAT(rxgoodframes) }, 424d9718546SMugunthan V N { "Broadcast Rx Frames", CPSW_STAT(rxbroadcastframes) }, 425d9718546SMugunthan V N { "Multicast Rx Frames", CPSW_STAT(rxmulticastframes) }, 426d9718546SMugunthan V N { "Pause Rx Frames", CPSW_STAT(rxpauseframes) }, 427d9718546SMugunthan V N { "Rx CRC Errors", CPSW_STAT(rxcrcerrors) }, 428d9718546SMugunthan V N { "Rx Align/Code Errors", CPSW_STAT(rxaligncodeerrors) }, 429d9718546SMugunthan V N { "Oversize Rx Frames", CPSW_STAT(rxoversizedframes) }, 430d9718546SMugunthan V N { "Rx Jabbers", CPSW_STAT(rxjabberframes) }, 431d9718546SMugunthan V N { "Undersize (Short) Rx Frames", CPSW_STAT(rxundersizedframes) }, 432d9718546SMugunthan V N { "Rx Fragments", CPSW_STAT(rxfragments) }, 433d9718546SMugunthan V N { "Rx Octets", CPSW_STAT(rxoctets) }, 434d9718546SMugunthan V N { "Good Tx Frames", CPSW_STAT(txgoodframes) }, 435d9718546SMugunthan V N { "Broadcast Tx Frames", CPSW_STAT(txbroadcastframes) }, 436d9718546SMugunthan V N { "Multicast Tx Frames", CPSW_STAT(txmulticastframes) }, 437d9718546SMugunthan V N { "Pause Tx Frames", CPSW_STAT(txpauseframes) }, 438d9718546SMugunthan V N { "Deferred Tx Frames", CPSW_STAT(txdeferredframes) }, 439d9718546SMugunthan V N { "Collisions", CPSW_STAT(txcollisionframes) }, 440d9718546SMugunthan V N { "Single Collision Tx Frames", CPSW_STAT(txsinglecollframes) }, 441d9718546SMugunthan V N { "Multiple Collision Tx Frames", CPSW_STAT(txmultcollframes) }, 442d9718546SMugunthan V N { "Excessive Collisions", CPSW_STAT(txexcessivecollisions) }, 443d9718546SMugunthan V N { "Late Collisions", CPSW_STAT(txlatecollisions) }, 444d9718546SMugunthan V N { "Tx Underrun", CPSW_STAT(txunderrun) }, 445d9718546SMugunthan V N { "Carrier Sense Errors", CPSW_STAT(txcarriersenseerrors) }, 446d9718546SMugunthan V N { "Tx Octets", CPSW_STAT(txoctets) }, 447d9718546SMugunthan V N { "Rx + Tx 64 Octet Frames", CPSW_STAT(octetframes64) }, 448d9718546SMugunthan V N { "Rx + Tx 65-127 Octet Frames", CPSW_STAT(octetframes65t127) }, 449d9718546SMugunthan V N { "Rx + Tx 128-255 Octet Frames", CPSW_STAT(octetframes128t255) }, 450d9718546SMugunthan V N { "Rx + Tx 256-511 Octet Frames", CPSW_STAT(octetframes256t511) }, 451d9718546SMugunthan V N { "Rx + Tx 512-1023 Octet Frames", CPSW_STAT(octetframes512t1023) }, 452d9718546SMugunthan V N { "Rx + Tx 1024-Up Octet Frames", CPSW_STAT(octetframes1024tup) }, 453d9718546SMugunthan V N { "Net Octets", CPSW_STAT(netoctets) }, 454d9718546SMugunthan V N { "Rx Start of Frame Overruns", CPSW_STAT(rxsofoverruns) }, 455d9718546SMugunthan V N { "Rx Middle of Frame Overruns", CPSW_STAT(rxmofoverruns) }, 456d9718546SMugunthan V N { "Rx DMA Overruns", CPSW_STAT(rxdmaoverruns) }, 457d9718546SMugunthan V N { "Rx DMA chan: head_enqueue", CPDMA_RX_STAT(head_enqueue) }, 458d9718546SMugunthan V N { "Rx DMA chan: tail_enqueue", CPDMA_RX_STAT(tail_enqueue) }, 459d9718546SMugunthan V N { "Rx DMA chan: pad_enqueue", CPDMA_RX_STAT(pad_enqueue) }, 460d9718546SMugunthan V N { "Rx DMA chan: misqueued", CPDMA_RX_STAT(misqueued) }, 461d9718546SMugunthan V N { "Rx DMA chan: desc_alloc_fail", CPDMA_RX_STAT(desc_alloc_fail) }, 462d9718546SMugunthan V N { "Rx DMA chan: pad_alloc_fail", CPDMA_RX_STAT(pad_alloc_fail) }, 463d9718546SMugunthan V N { "Rx DMA chan: runt_receive_buf", CPDMA_RX_STAT(runt_receive_buff) }, 464d9718546SMugunthan V N { "Rx DMA chan: runt_transmit_buf", CPDMA_RX_STAT(runt_transmit_buff) }, 465d9718546SMugunthan V N { "Rx DMA chan: empty_dequeue", CPDMA_RX_STAT(empty_dequeue) }, 466d9718546SMugunthan V N { "Rx DMA chan: busy_dequeue", CPDMA_RX_STAT(busy_dequeue) }, 467d9718546SMugunthan V N { "Rx DMA chan: good_dequeue", CPDMA_RX_STAT(good_dequeue) }, 468d9718546SMugunthan V N { "Rx DMA chan: requeue", CPDMA_RX_STAT(requeue) }, 469d9718546SMugunthan V N { "Rx DMA chan: teardown_dequeue", CPDMA_RX_STAT(teardown_dequeue) }, 470d9718546SMugunthan V N { "Tx DMA chan: head_enqueue", CPDMA_TX_STAT(head_enqueue) }, 471d9718546SMugunthan V N { "Tx DMA chan: tail_enqueue", CPDMA_TX_STAT(tail_enqueue) }, 472d9718546SMugunthan V N { "Tx DMA chan: pad_enqueue", CPDMA_TX_STAT(pad_enqueue) }, 473d9718546SMugunthan V N { "Tx DMA chan: misqueued", CPDMA_TX_STAT(misqueued) }, 474d9718546SMugunthan V N { "Tx DMA chan: desc_alloc_fail", CPDMA_TX_STAT(desc_alloc_fail) }, 475d9718546SMugunthan V N { "Tx DMA chan: pad_alloc_fail", CPDMA_TX_STAT(pad_alloc_fail) }, 476d9718546SMugunthan V N { "Tx DMA chan: runt_receive_buf", CPDMA_TX_STAT(runt_receive_buff) }, 477d9718546SMugunthan V N { "Tx DMA chan: runt_transmit_buf", CPDMA_TX_STAT(runt_transmit_buff) }, 478d9718546SMugunthan V N { "Tx DMA chan: empty_dequeue", CPDMA_TX_STAT(empty_dequeue) }, 479d9718546SMugunthan V N { "Tx DMA chan: busy_dequeue", CPDMA_TX_STAT(busy_dequeue) }, 480d9718546SMugunthan V N { "Tx DMA chan: good_dequeue", CPDMA_TX_STAT(good_dequeue) }, 481d9718546SMugunthan V N { "Tx DMA chan: requeue", CPDMA_TX_STAT(requeue) }, 482d9718546SMugunthan V N { "Tx DMA chan: teardown_dequeue", CPDMA_TX_STAT(teardown_dequeue) }, 483d9718546SMugunthan V N }; 484d9718546SMugunthan V N 485d9718546SMugunthan V N #define CPSW_STATS_LEN ARRAY_SIZE(cpsw_gstrings_stats) 486d9718546SMugunthan V N 487df828598SMugunthan V N #define napi_to_priv(napi) container_of(napi, struct cpsw_priv, napi) 488df828598SMugunthan V N #define for_each_slave(priv, func, arg...) \ 489df828598SMugunthan V N do { \ 4906e6ceaedSSebastian Siewior struct cpsw_slave *slave; \ 4916e6ceaedSSebastian Siewior int n; \ 492d9ba8f9eSMugunthan V N if (priv->data.dual_emac) \ 493d9ba8f9eSMugunthan V N (func)((priv)->slaves + priv->emac_port, ##arg);\ 494d9ba8f9eSMugunthan V N else \ 4956e6ceaedSSebastian Siewior for (n = (priv)->data.slaves, \ 4966e6ceaedSSebastian Siewior slave = (priv)->slaves; \ 4976e6ceaedSSebastian Siewior n; n--) \ 4986e6ceaedSSebastian Siewior (func)(slave++, ##arg); \ 499df828598SMugunthan V N } while (0) 500d9ba8f9eSMugunthan V N #define cpsw_get_slave_ndev(priv, __slave_no__) \ 501d9ba8f9eSMugunthan V N (priv->slaves[__slave_no__].ndev) 502d9ba8f9eSMugunthan V N #define cpsw_get_slave_priv(priv, __slave_no__) \ 503d9ba8f9eSMugunthan V N ((priv->slaves[__slave_no__].ndev) ? \ 504d9ba8f9eSMugunthan V N netdev_priv(priv->slaves[__slave_no__].ndev) : NULL) \ 505d9ba8f9eSMugunthan V N 506d9ba8f9eSMugunthan V N #define cpsw_dual_emac_src_port_detect(status, priv, ndev, skb) \ 507d9ba8f9eSMugunthan V N do { \ 508d9ba8f9eSMugunthan V N if (!priv->data.dual_emac) \ 509d9ba8f9eSMugunthan V N break; \ 510d9ba8f9eSMugunthan V N if (CPDMA_RX_SOURCE_PORT(status) == 1) { \ 511d9ba8f9eSMugunthan V N ndev = cpsw_get_slave_ndev(priv, 0); \ 512d9ba8f9eSMugunthan V N priv = netdev_priv(ndev); \ 513d9ba8f9eSMugunthan V N skb->dev = ndev; \ 514d9ba8f9eSMugunthan V N } else if (CPDMA_RX_SOURCE_PORT(status) == 2) { \ 515d9ba8f9eSMugunthan V N ndev = cpsw_get_slave_ndev(priv, 1); \ 516d9ba8f9eSMugunthan V N priv = netdev_priv(ndev); \ 517d9ba8f9eSMugunthan V N skb->dev = ndev; \ 518d9ba8f9eSMugunthan V N } \ 519d9ba8f9eSMugunthan V N } while (0) 520d9ba8f9eSMugunthan V N #define cpsw_add_mcast(priv, addr) \ 521d9ba8f9eSMugunthan V N do { \ 522d9ba8f9eSMugunthan V N if (priv->data.dual_emac) { \ 523d9ba8f9eSMugunthan V N struct cpsw_slave *slave = priv->slaves + \ 524d9ba8f9eSMugunthan V N priv->emac_port; \ 525d9ba8f9eSMugunthan V N int slave_port = cpsw_get_slave_port(priv, \ 526d9ba8f9eSMugunthan V N slave->slave_num); \ 527d9ba8f9eSMugunthan V N cpsw_ale_add_mcast(priv->ale, addr, \ 528d9ba8f9eSMugunthan V N 1 << slave_port | 1 << priv->host_port, \ 529d9ba8f9eSMugunthan V N ALE_VLAN, slave->port_vlan, 0); \ 530d9ba8f9eSMugunthan V N } else { \ 531d9ba8f9eSMugunthan V N cpsw_ale_add_mcast(priv->ale, addr, \ 532d9ba8f9eSMugunthan V N ALE_ALL_PORTS << priv->host_port, \ 533d9ba8f9eSMugunthan V N 0, 0, 0); \ 534d9ba8f9eSMugunthan V N } \ 535d9ba8f9eSMugunthan V N } while (0) 536d9ba8f9eSMugunthan V N 537d9ba8f9eSMugunthan V N static inline int cpsw_get_slave_port(struct cpsw_priv *priv, u32 slave_num) 538d9ba8f9eSMugunthan V N { 539d9ba8f9eSMugunthan V N if (priv->host_port == 0) 540d9ba8f9eSMugunthan V N return slave_num + 1; 541d9ba8f9eSMugunthan V N else 542d9ba8f9eSMugunthan V N return slave_num; 543d9ba8f9eSMugunthan V N } 544df828598SMugunthan V N 5455c50a856SMugunthan V N static void cpsw_ndo_set_rx_mode(struct net_device *ndev) 5465c50a856SMugunthan V N { 5475c50a856SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 5485c50a856SMugunthan V N 5495c50a856SMugunthan V N if (ndev->flags & IFF_PROMISC) { 5505c50a856SMugunthan V N /* Enable promiscuous mode */ 5515c50a856SMugunthan V N dev_err(priv->dev, "Ignoring Promiscuous mode\n"); 5525c50a856SMugunthan V N return; 5535c50a856SMugunthan V N } 5545c50a856SMugunthan V N 5555c50a856SMugunthan V N /* Clear all mcast from ALE */ 5565c50a856SMugunthan V N cpsw_ale_flush_multicast(priv->ale, ALE_ALL_PORTS << priv->host_port); 5575c50a856SMugunthan V N 5585c50a856SMugunthan V N if (!netdev_mc_empty(ndev)) { 5595c50a856SMugunthan V N struct netdev_hw_addr *ha; 5605c50a856SMugunthan V N 5615c50a856SMugunthan V N /* program multicast address list into ALE register */ 5625c50a856SMugunthan V N netdev_for_each_mc_addr(ha, ndev) { 563d9ba8f9eSMugunthan V N cpsw_add_mcast(priv, (u8 *)ha->addr); 5645c50a856SMugunthan V N } 5655c50a856SMugunthan V N } 5665c50a856SMugunthan V N } 5675c50a856SMugunthan V N 568df828598SMugunthan V N static void cpsw_intr_enable(struct cpsw_priv *priv) 569df828598SMugunthan V N { 570996a5c27SRichard Cochran __raw_writel(0xFF, &priv->wr_regs->tx_en); 571996a5c27SRichard Cochran __raw_writel(0xFF, &priv->wr_regs->rx_en); 572df828598SMugunthan V N 573df828598SMugunthan V N cpdma_ctlr_int_ctrl(priv->dma, true); 574df828598SMugunthan V N return; 575df828598SMugunthan V N } 576df828598SMugunthan V N 577df828598SMugunthan V N static void cpsw_intr_disable(struct cpsw_priv *priv) 578df828598SMugunthan V N { 579996a5c27SRichard Cochran __raw_writel(0, &priv->wr_regs->tx_en); 580996a5c27SRichard Cochran __raw_writel(0, &priv->wr_regs->rx_en); 581df828598SMugunthan V N 582df828598SMugunthan V N cpdma_ctlr_int_ctrl(priv->dma, false); 583df828598SMugunthan V N return; 584df828598SMugunthan V N } 585df828598SMugunthan V N 586df828598SMugunthan V N void cpsw_tx_handler(void *token, int len, int status) 587df828598SMugunthan V N { 588df828598SMugunthan V N struct sk_buff *skb = token; 589df828598SMugunthan V N struct net_device *ndev = skb->dev; 590df828598SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 591df828598SMugunthan V N 592fae50823SMugunthan V N /* Check whether the queue is stopped due to stalled tx dma, if the 593fae50823SMugunthan V N * queue is stopped then start the queue as we have free desc for tx 594fae50823SMugunthan V N */ 595df828598SMugunthan V N if (unlikely(netif_queue_stopped(ndev))) 596b56d6b3fSMugunthan V N netif_wake_queue(ndev); 5979232b16dSMugunthan V N cpts_tx_timestamp(priv->cpts, skb); 598df828598SMugunthan V N priv->stats.tx_packets++; 599df828598SMugunthan V N priv->stats.tx_bytes += len; 600df828598SMugunthan V N dev_kfree_skb_any(skb); 601df828598SMugunthan V N } 602df828598SMugunthan V N 603df828598SMugunthan V N void cpsw_rx_handler(void *token, int len, int status) 604df828598SMugunthan V N { 605df828598SMugunthan V N struct sk_buff *skb = token; 606b4727e69SSebastian Siewior struct sk_buff *new_skb; 607df828598SMugunthan V N struct net_device *ndev = skb->dev; 608df828598SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 609df828598SMugunthan V N int ret = 0; 610df828598SMugunthan V N 611d9ba8f9eSMugunthan V N cpsw_dual_emac_src_port_detect(status, priv, ndev, skb); 612d9ba8f9eSMugunthan V N 613b4727e69SSebastian Siewior if (unlikely(status < 0)) { 614b4727e69SSebastian Siewior /* the interface is going down, skbs are purged */ 615df828598SMugunthan V N dev_kfree_skb_any(skb); 616df828598SMugunthan V N return; 617df828598SMugunthan V N } 618b4727e69SSebastian Siewior 619b4727e69SSebastian Siewior new_skb = netdev_alloc_skb_ip_align(ndev, priv->rx_packet_max); 620b4727e69SSebastian Siewior if (new_skb) { 621df828598SMugunthan V N skb_put(skb, len); 6229232b16dSMugunthan V N cpts_rx_timestamp(priv->cpts, skb); 623df828598SMugunthan V N skb->protocol = eth_type_trans(skb, ndev); 624df828598SMugunthan V N netif_receive_skb(skb); 625df828598SMugunthan V N priv->stats.rx_bytes += len; 626df828598SMugunthan V N priv->stats.rx_packets++; 627b4727e69SSebastian Siewior } else { 628b4727e69SSebastian Siewior priv->stats.rx_dropped++; 629b4727e69SSebastian Siewior new_skb = skb; 630df828598SMugunthan V N } 631df828598SMugunthan V N 632b4727e69SSebastian Siewior ret = cpdma_chan_submit(priv->rxch, new_skb, new_skb->data, 633b4727e69SSebastian Siewior skb_tailroom(new_skb), 0); 634b4727e69SSebastian Siewior if (WARN_ON(ret < 0)) 635b4727e69SSebastian Siewior dev_kfree_skb_any(new_skb); 636df828598SMugunthan V N } 637df828598SMugunthan V N 638df828598SMugunthan V N static irqreturn_t cpsw_interrupt(int irq, void *dev_id) 639df828598SMugunthan V N { 640df828598SMugunthan V N struct cpsw_priv *priv = dev_id; 641fd51cf19SSebastian Siewior u32 rx, tx, rx_thresh; 642df828598SMugunthan V N 643fd51cf19SSebastian Siewior rx_thresh = __raw_readl(&priv->wr_regs->rx_thresh_stat); 644fd51cf19SSebastian Siewior rx = __raw_readl(&priv->wr_regs->rx_stat); 645fd51cf19SSebastian Siewior tx = __raw_readl(&priv->wr_regs->tx_stat); 646fd51cf19SSebastian Siewior if (!rx_thresh && !rx && !tx) 647fd51cf19SSebastian Siewior return IRQ_NONE; 648fd51cf19SSebastian Siewior 649df828598SMugunthan V N cpsw_intr_disable(priv); 650a11fbba9SSebastian Siewior if (priv->irq_enabled == true) { 651df828598SMugunthan V N cpsw_disable_irq(priv); 652a11fbba9SSebastian Siewior priv->irq_enabled = false; 653a11fbba9SSebastian Siewior } 654fd51cf19SSebastian Siewior 655fd51cf19SSebastian Siewior if (netif_running(priv->ndev)) { 656df828598SMugunthan V N napi_schedule(&priv->napi); 657df828598SMugunthan V N return IRQ_HANDLED; 658df828598SMugunthan V N } 659df828598SMugunthan V N 660fd51cf19SSebastian Siewior priv = cpsw_get_slave_priv(priv, 1); 661fd51cf19SSebastian Siewior if (!priv) 662fd51cf19SSebastian Siewior return IRQ_NONE; 663fd51cf19SSebastian Siewior 664fd51cf19SSebastian Siewior if (netif_running(priv->ndev)) { 665fd51cf19SSebastian Siewior napi_schedule(&priv->napi); 666fd51cf19SSebastian Siewior return IRQ_HANDLED; 667fd51cf19SSebastian Siewior } 668fd51cf19SSebastian Siewior return IRQ_NONE; 669fd51cf19SSebastian Siewior } 670fd51cf19SSebastian Siewior 671df828598SMugunthan V N static int cpsw_poll(struct napi_struct *napi, int budget) 672df828598SMugunthan V N { 673df828598SMugunthan V N struct cpsw_priv *priv = napi_to_priv(napi); 674df828598SMugunthan V N int num_tx, num_rx; 675df828598SMugunthan V N 676df828598SMugunthan V N num_tx = cpdma_chan_process(priv->txch, 128); 677510a1e72SMugunthan V N if (num_tx) 678510a1e72SMugunthan V N cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_TX); 679510a1e72SMugunthan V N 680df828598SMugunthan V N num_rx = cpdma_chan_process(priv->rxch, budget); 681510a1e72SMugunthan V N if (num_rx < budget) { 682a11fbba9SSebastian Siewior struct cpsw_priv *prim_cpsw; 683a11fbba9SSebastian Siewior 684510a1e72SMugunthan V N napi_complete(napi); 685510a1e72SMugunthan V N cpsw_intr_enable(priv); 686510a1e72SMugunthan V N cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_RX); 687a11fbba9SSebastian Siewior prim_cpsw = cpsw_get_slave_priv(priv, 0); 688a11fbba9SSebastian Siewior if (prim_cpsw->irq_enabled == false) { 689a11fbba9SSebastian Siewior prim_cpsw->irq_enabled = true; 690af5c6df7SMugunthan V N cpsw_enable_irq(priv); 691a11fbba9SSebastian Siewior } 692510a1e72SMugunthan V N } 693df828598SMugunthan V N 694df828598SMugunthan V N if (num_rx || num_tx) 695df828598SMugunthan V N cpsw_dbg(priv, intr, "poll %d rx, %d tx pkts\n", 696df828598SMugunthan V N num_rx, num_tx); 697df828598SMugunthan V N 698df828598SMugunthan V N return num_rx; 699df828598SMugunthan V N } 700df828598SMugunthan V N 701df828598SMugunthan V N static inline void soft_reset(const char *module, void __iomem *reg) 702df828598SMugunthan V N { 703df828598SMugunthan V N unsigned long timeout = jiffies + HZ; 704df828598SMugunthan V N 705df828598SMugunthan V N __raw_writel(1, reg); 706df828598SMugunthan V N do { 707df828598SMugunthan V N cpu_relax(); 708df828598SMugunthan V N } while ((__raw_readl(reg) & 1) && time_after(timeout, jiffies)); 709df828598SMugunthan V N 710df828598SMugunthan V N WARN(__raw_readl(reg) & 1, "failed to soft-reset %s\n", module); 711df828598SMugunthan V N } 712df828598SMugunthan V N 713df828598SMugunthan V N #define mac_hi(mac) (((mac)[0] << 0) | ((mac)[1] << 8) | \ 714df828598SMugunthan V N ((mac)[2] << 16) | ((mac)[3] << 24)) 715df828598SMugunthan V N #define mac_lo(mac) (((mac)[4] << 0) | ((mac)[5] << 8)) 716df828598SMugunthan V N 717df828598SMugunthan V N static void cpsw_set_slave_mac(struct cpsw_slave *slave, 718df828598SMugunthan V N struct cpsw_priv *priv) 719df828598SMugunthan V N { 7209750a3adSRichard Cochran slave_write(slave, mac_hi(priv->mac_addr), SA_HI); 7219750a3adSRichard Cochran slave_write(slave, mac_lo(priv->mac_addr), SA_LO); 722df828598SMugunthan V N } 723df828598SMugunthan V N 724df828598SMugunthan V N static void _cpsw_adjust_link(struct cpsw_slave *slave, 725df828598SMugunthan V N struct cpsw_priv *priv, bool *link) 726df828598SMugunthan V N { 727df828598SMugunthan V N struct phy_device *phy = slave->phy; 728df828598SMugunthan V N u32 mac_control = 0; 729df828598SMugunthan V N u32 slave_port; 730df828598SMugunthan V N 731df828598SMugunthan V N if (!phy) 732df828598SMugunthan V N return; 733df828598SMugunthan V N 734df828598SMugunthan V N slave_port = cpsw_get_slave_port(priv, slave->slave_num); 735df828598SMugunthan V N 736df828598SMugunthan V N if (phy->link) { 737df828598SMugunthan V N mac_control = priv->data.mac_control; 738df828598SMugunthan V N 739df828598SMugunthan V N /* enable forwarding */ 740df828598SMugunthan V N cpsw_ale_control_set(priv->ale, slave_port, 741df828598SMugunthan V N ALE_PORT_STATE, ALE_PORT_STATE_FORWARD); 742df828598SMugunthan V N 743df828598SMugunthan V N if (phy->speed == 1000) 744df828598SMugunthan V N mac_control |= BIT(7); /* GIGABITEN */ 745df828598SMugunthan V N if (phy->duplex) 746df828598SMugunthan V N mac_control |= BIT(0); /* FULLDUPLEXEN */ 747342b7b74SDaniel Mack 748342b7b74SDaniel Mack /* set speed_in input in case RMII mode is used in 100Mbps */ 749342b7b74SDaniel Mack if (phy->speed == 100) 750342b7b74SDaniel Mack mac_control |= BIT(15); 751342b7b74SDaniel Mack 752df828598SMugunthan V N *link = true; 753df828598SMugunthan V N } else { 754df828598SMugunthan V N mac_control = 0; 755df828598SMugunthan V N /* disable forwarding */ 756df828598SMugunthan V N cpsw_ale_control_set(priv->ale, slave_port, 757df828598SMugunthan V N ALE_PORT_STATE, ALE_PORT_STATE_DISABLE); 758df828598SMugunthan V N } 759df828598SMugunthan V N 760df828598SMugunthan V N if (mac_control != slave->mac_control) { 761df828598SMugunthan V N phy_print_status(phy); 762df828598SMugunthan V N __raw_writel(mac_control, &slave->sliver->mac_control); 763df828598SMugunthan V N } 764df828598SMugunthan V N 765df828598SMugunthan V N slave->mac_control = mac_control; 766df828598SMugunthan V N } 767df828598SMugunthan V N 768df828598SMugunthan V N static void cpsw_adjust_link(struct net_device *ndev) 769df828598SMugunthan V N { 770df828598SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 771df828598SMugunthan V N bool link = false; 772df828598SMugunthan V N 773df828598SMugunthan V N for_each_slave(priv, _cpsw_adjust_link, priv, &link); 774df828598SMugunthan V N 775df828598SMugunthan V N if (link) { 776df828598SMugunthan V N netif_carrier_on(ndev); 777df828598SMugunthan V N if (netif_running(ndev)) 778df828598SMugunthan V N netif_wake_queue(ndev); 779df828598SMugunthan V N } else { 780df828598SMugunthan V N netif_carrier_off(ndev); 781df828598SMugunthan V N netif_stop_queue(ndev); 782df828598SMugunthan V N } 783df828598SMugunthan V N } 784df828598SMugunthan V N 785ff5b8ef2SMugunthan V N static int cpsw_get_coalesce(struct net_device *ndev, 786ff5b8ef2SMugunthan V N struct ethtool_coalesce *coal) 787ff5b8ef2SMugunthan V N { 788ff5b8ef2SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 789ff5b8ef2SMugunthan V N 790ff5b8ef2SMugunthan V N coal->rx_coalesce_usecs = priv->coal_intvl; 791ff5b8ef2SMugunthan V N return 0; 792ff5b8ef2SMugunthan V N } 793ff5b8ef2SMugunthan V N 794ff5b8ef2SMugunthan V N static int cpsw_set_coalesce(struct net_device *ndev, 795ff5b8ef2SMugunthan V N struct ethtool_coalesce *coal) 796ff5b8ef2SMugunthan V N { 797ff5b8ef2SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 798ff5b8ef2SMugunthan V N u32 int_ctrl; 799ff5b8ef2SMugunthan V N u32 num_interrupts = 0; 800ff5b8ef2SMugunthan V N u32 prescale = 0; 801ff5b8ef2SMugunthan V N u32 addnl_dvdr = 1; 802ff5b8ef2SMugunthan V N u32 coal_intvl = 0; 803ff5b8ef2SMugunthan V N 804ff5b8ef2SMugunthan V N if (!coal->rx_coalesce_usecs) 805ff5b8ef2SMugunthan V N return -EINVAL; 806ff5b8ef2SMugunthan V N 807ff5b8ef2SMugunthan V N coal_intvl = coal->rx_coalesce_usecs; 808ff5b8ef2SMugunthan V N 809ff5b8ef2SMugunthan V N int_ctrl = readl(&priv->wr_regs->int_control); 810ff5b8ef2SMugunthan V N prescale = priv->bus_freq_mhz * 4; 811ff5b8ef2SMugunthan V N 812ff5b8ef2SMugunthan V N if (coal_intvl < CPSW_CMINTMIN_INTVL) 813ff5b8ef2SMugunthan V N coal_intvl = CPSW_CMINTMIN_INTVL; 814ff5b8ef2SMugunthan V N 815ff5b8ef2SMugunthan V N if (coal_intvl > CPSW_CMINTMAX_INTVL) { 816ff5b8ef2SMugunthan V N /* Interrupt pacer works with 4us Pulse, we can 817ff5b8ef2SMugunthan V N * throttle further by dilating the 4us pulse. 818ff5b8ef2SMugunthan V N */ 819ff5b8ef2SMugunthan V N addnl_dvdr = CPSW_INTPRESCALE_MASK / prescale; 820ff5b8ef2SMugunthan V N 821ff5b8ef2SMugunthan V N if (addnl_dvdr > 1) { 822ff5b8ef2SMugunthan V N prescale *= addnl_dvdr; 823ff5b8ef2SMugunthan V N if (coal_intvl > (CPSW_CMINTMAX_INTVL * addnl_dvdr)) 824ff5b8ef2SMugunthan V N coal_intvl = (CPSW_CMINTMAX_INTVL 825ff5b8ef2SMugunthan V N * addnl_dvdr); 826ff5b8ef2SMugunthan V N } else { 827ff5b8ef2SMugunthan V N addnl_dvdr = 1; 828ff5b8ef2SMugunthan V N coal_intvl = CPSW_CMINTMAX_INTVL; 829ff5b8ef2SMugunthan V N } 830ff5b8ef2SMugunthan V N } 831ff5b8ef2SMugunthan V N 832ff5b8ef2SMugunthan V N num_interrupts = (1000 * addnl_dvdr) / coal_intvl; 833ff5b8ef2SMugunthan V N writel(num_interrupts, &priv->wr_regs->rx_imax); 834ff5b8ef2SMugunthan V N writel(num_interrupts, &priv->wr_regs->tx_imax); 835ff5b8ef2SMugunthan V N 836ff5b8ef2SMugunthan V N int_ctrl |= CPSW_INTPACEEN; 837ff5b8ef2SMugunthan V N int_ctrl &= (~CPSW_INTPRESCALE_MASK); 838ff5b8ef2SMugunthan V N int_ctrl |= (prescale & CPSW_INTPRESCALE_MASK); 839ff5b8ef2SMugunthan V N writel(int_ctrl, &priv->wr_regs->int_control); 840ff5b8ef2SMugunthan V N 841ff5b8ef2SMugunthan V N cpsw_notice(priv, timer, "Set coalesce to %d usecs.\n", coal_intvl); 842ff5b8ef2SMugunthan V N if (priv->data.dual_emac) { 843ff5b8ef2SMugunthan V N int i; 844ff5b8ef2SMugunthan V N 845ff5b8ef2SMugunthan V N for (i = 0; i < priv->data.slaves; i++) { 846ff5b8ef2SMugunthan V N priv = netdev_priv(priv->slaves[i].ndev); 847ff5b8ef2SMugunthan V N priv->coal_intvl = coal_intvl; 848ff5b8ef2SMugunthan V N } 849ff5b8ef2SMugunthan V N } else { 850ff5b8ef2SMugunthan V N priv->coal_intvl = coal_intvl; 851ff5b8ef2SMugunthan V N } 852ff5b8ef2SMugunthan V N 853ff5b8ef2SMugunthan V N return 0; 854ff5b8ef2SMugunthan V N } 855ff5b8ef2SMugunthan V N 856d9718546SMugunthan V N static int cpsw_get_sset_count(struct net_device *ndev, int sset) 857d9718546SMugunthan V N { 858d9718546SMugunthan V N switch (sset) { 859d9718546SMugunthan V N case ETH_SS_STATS: 860d9718546SMugunthan V N return CPSW_STATS_LEN; 861d9718546SMugunthan V N default: 862d9718546SMugunthan V N return -EOPNOTSUPP; 863d9718546SMugunthan V N } 864d9718546SMugunthan V N } 865d9718546SMugunthan V N 866d9718546SMugunthan V N static void cpsw_get_strings(struct net_device *ndev, u32 stringset, u8 *data) 867d9718546SMugunthan V N { 868d9718546SMugunthan V N u8 *p = data; 869d9718546SMugunthan V N int i; 870d9718546SMugunthan V N 871d9718546SMugunthan V N switch (stringset) { 872d9718546SMugunthan V N case ETH_SS_STATS: 873d9718546SMugunthan V N for (i = 0; i < CPSW_STATS_LEN; i++) { 874d9718546SMugunthan V N memcpy(p, cpsw_gstrings_stats[i].stat_string, 875d9718546SMugunthan V N ETH_GSTRING_LEN); 876d9718546SMugunthan V N p += ETH_GSTRING_LEN; 877d9718546SMugunthan V N } 878d9718546SMugunthan V N break; 879d9718546SMugunthan V N } 880d9718546SMugunthan V N } 881d9718546SMugunthan V N 882d9718546SMugunthan V N static void cpsw_get_ethtool_stats(struct net_device *ndev, 883d9718546SMugunthan V N struct ethtool_stats *stats, u64 *data) 884d9718546SMugunthan V N { 885d9718546SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 886d9718546SMugunthan V N struct cpdma_chan_stats rx_stats; 887d9718546SMugunthan V N struct cpdma_chan_stats tx_stats; 888d9718546SMugunthan V N u32 val; 889d9718546SMugunthan V N u8 *p; 890d9718546SMugunthan V N int i; 891d9718546SMugunthan V N 892d9718546SMugunthan V N /* Collect Davinci CPDMA stats for Rx and Tx Channel */ 893d9718546SMugunthan V N cpdma_chan_get_stats(priv->rxch, &rx_stats); 894d9718546SMugunthan V N cpdma_chan_get_stats(priv->txch, &tx_stats); 895d9718546SMugunthan V N 896d9718546SMugunthan V N for (i = 0; i < CPSW_STATS_LEN; i++) { 897d9718546SMugunthan V N switch (cpsw_gstrings_stats[i].type) { 898d9718546SMugunthan V N case CPSW_STATS: 899d9718546SMugunthan V N val = readl(priv->hw_stats + 900d9718546SMugunthan V N cpsw_gstrings_stats[i].stat_offset); 901d9718546SMugunthan V N data[i] = val; 902d9718546SMugunthan V N break; 903d9718546SMugunthan V N 904d9718546SMugunthan V N case CPDMA_RX_STATS: 905d9718546SMugunthan V N p = (u8 *)&rx_stats + 906d9718546SMugunthan V N cpsw_gstrings_stats[i].stat_offset; 907d9718546SMugunthan V N data[i] = *(u32 *)p; 908d9718546SMugunthan V N break; 909d9718546SMugunthan V N 910d9718546SMugunthan V N case CPDMA_TX_STATS: 911d9718546SMugunthan V N p = (u8 *)&tx_stats + 912d9718546SMugunthan V N cpsw_gstrings_stats[i].stat_offset; 913d9718546SMugunthan V N data[i] = *(u32 *)p; 914d9718546SMugunthan V N break; 915d9718546SMugunthan V N } 916d9718546SMugunthan V N } 917d9718546SMugunthan V N } 918d9718546SMugunthan V N 919df828598SMugunthan V N static inline int __show_stat(char *buf, int maxlen, const char *name, u32 val) 920df828598SMugunthan V N { 921df828598SMugunthan V N static char *leader = "........................................"; 922df828598SMugunthan V N 923df828598SMugunthan V N if (!val) 924df828598SMugunthan V N return 0; 925df828598SMugunthan V N else 926df828598SMugunthan V N return snprintf(buf, maxlen, "%s %s %10d\n", name, 927df828598SMugunthan V N leader + strlen(name), val); 928df828598SMugunthan V N } 929df828598SMugunthan V N 930d9ba8f9eSMugunthan V N static int cpsw_common_res_usage_state(struct cpsw_priv *priv) 931d9ba8f9eSMugunthan V N { 932d9ba8f9eSMugunthan V N u32 i; 933d9ba8f9eSMugunthan V N u32 usage_count = 0; 934d9ba8f9eSMugunthan V N 935d9ba8f9eSMugunthan V N if (!priv->data.dual_emac) 936d9ba8f9eSMugunthan V N return 0; 937d9ba8f9eSMugunthan V N 938d9ba8f9eSMugunthan V N for (i = 0; i < priv->data.slaves; i++) 939d9ba8f9eSMugunthan V N if (priv->slaves[i].open_stat) 940d9ba8f9eSMugunthan V N usage_count++; 941d9ba8f9eSMugunthan V N 942d9ba8f9eSMugunthan V N return usage_count; 943d9ba8f9eSMugunthan V N } 944d9ba8f9eSMugunthan V N 945d9ba8f9eSMugunthan V N static inline int cpsw_tx_packet_submit(struct net_device *ndev, 946d9ba8f9eSMugunthan V N struct cpsw_priv *priv, struct sk_buff *skb) 947d9ba8f9eSMugunthan V N { 948d9ba8f9eSMugunthan V N if (!priv->data.dual_emac) 949d9ba8f9eSMugunthan V N return cpdma_chan_submit(priv->txch, skb, skb->data, 950aef614e1SSebastian Siewior skb->len, 0); 951d9ba8f9eSMugunthan V N 952d9ba8f9eSMugunthan V N if (ndev == cpsw_get_slave_ndev(priv, 0)) 953d9ba8f9eSMugunthan V N return cpdma_chan_submit(priv->txch, skb, skb->data, 954aef614e1SSebastian Siewior skb->len, 1); 955d9ba8f9eSMugunthan V N else 956d9ba8f9eSMugunthan V N return cpdma_chan_submit(priv->txch, skb, skb->data, 957aef614e1SSebastian Siewior skb->len, 2); 958d9ba8f9eSMugunthan V N } 959d9ba8f9eSMugunthan V N 960d9ba8f9eSMugunthan V N static inline void cpsw_add_dual_emac_def_ale_entries( 961d9ba8f9eSMugunthan V N struct cpsw_priv *priv, struct cpsw_slave *slave, 962d9ba8f9eSMugunthan V N u32 slave_port) 963d9ba8f9eSMugunthan V N { 964d9ba8f9eSMugunthan V N u32 port_mask = 1 << slave_port | 1 << priv->host_port; 965d9ba8f9eSMugunthan V N 966d9ba8f9eSMugunthan V N if (priv->version == CPSW_VERSION_1) 967d9ba8f9eSMugunthan V N slave_write(slave, slave->port_vlan, CPSW1_PORT_VLAN); 968d9ba8f9eSMugunthan V N else 969d9ba8f9eSMugunthan V N slave_write(slave, slave->port_vlan, CPSW2_PORT_VLAN); 970d9ba8f9eSMugunthan V N cpsw_ale_add_vlan(priv->ale, slave->port_vlan, port_mask, 971d9ba8f9eSMugunthan V N port_mask, port_mask, 0); 972d9ba8f9eSMugunthan V N cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast, 973d9ba8f9eSMugunthan V N port_mask, ALE_VLAN, slave->port_vlan, 0); 974d9ba8f9eSMugunthan V N cpsw_ale_add_ucast(priv->ale, priv->mac_addr, 975d9ba8f9eSMugunthan V N priv->host_port, ALE_VLAN, slave->port_vlan); 976d9ba8f9eSMugunthan V N } 977d9ba8f9eSMugunthan V N 978df828598SMugunthan V N static void cpsw_slave_open(struct cpsw_slave *slave, struct cpsw_priv *priv) 979df828598SMugunthan V N { 980df828598SMugunthan V N char name[32]; 981df828598SMugunthan V N u32 slave_port; 982df828598SMugunthan V N 983df828598SMugunthan V N sprintf(name, "slave-%d", slave->slave_num); 984df828598SMugunthan V N 985df828598SMugunthan V N soft_reset(name, &slave->sliver->soft_reset); 986df828598SMugunthan V N 987df828598SMugunthan V N /* setup priority mapping */ 988df828598SMugunthan V N __raw_writel(RX_PRIORITY_MAPPING, &slave->sliver->rx_pri_map); 9899750a3adSRichard Cochran 9909750a3adSRichard Cochran switch (priv->version) { 9919750a3adSRichard Cochran case CPSW_VERSION_1: 9929750a3adSRichard Cochran slave_write(slave, TX_PRIORITY_MAPPING, CPSW1_TX_PRI_MAP); 9939750a3adSRichard Cochran break; 9949750a3adSRichard Cochran case CPSW_VERSION_2: 995c193f365SMugunthan V N case CPSW_VERSION_3: 9969750a3adSRichard Cochran slave_write(slave, TX_PRIORITY_MAPPING, CPSW2_TX_PRI_MAP); 9979750a3adSRichard Cochran break; 9989750a3adSRichard Cochran } 999df828598SMugunthan V N 1000df828598SMugunthan V N /* setup max packet size, and mac address */ 1001df828598SMugunthan V N __raw_writel(priv->rx_packet_max, &slave->sliver->rx_maxlen); 1002df828598SMugunthan V N cpsw_set_slave_mac(slave, priv); 1003df828598SMugunthan V N 1004df828598SMugunthan V N slave->mac_control = 0; /* no link yet */ 1005df828598SMugunthan V N 1006df828598SMugunthan V N slave_port = cpsw_get_slave_port(priv, slave->slave_num); 1007df828598SMugunthan V N 1008d9ba8f9eSMugunthan V N if (priv->data.dual_emac) 1009d9ba8f9eSMugunthan V N cpsw_add_dual_emac_def_ale_entries(priv, slave, slave_port); 1010d9ba8f9eSMugunthan V N else 1011df828598SMugunthan V N cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast, 1012e11b220fSMugunthan V N 1 << slave_port, 0, 0, ALE_MCAST_FWD_2); 1013df828598SMugunthan V N 1014df828598SMugunthan V N slave->phy = phy_connect(priv->ndev, slave->data->phy_id, 1015f9a8f83bSFlorian Fainelli &cpsw_adjust_link, slave->data->phy_if); 1016df828598SMugunthan V N if (IS_ERR(slave->phy)) { 1017df828598SMugunthan V N dev_err(priv->dev, "phy %s not found on slave %d\n", 1018df828598SMugunthan V N slave->data->phy_id, slave->slave_num); 1019df828598SMugunthan V N slave->phy = NULL; 1020df828598SMugunthan V N } else { 1021df828598SMugunthan V N dev_info(priv->dev, "phy found : id is : 0x%x\n", 1022df828598SMugunthan V N slave->phy->phy_id); 1023df828598SMugunthan V N phy_start(slave->phy); 1024df828598SMugunthan V N } 1025df828598SMugunthan V N } 1026df828598SMugunthan V N 10273b72c2feSMugunthan V N static inline void cpsw_add_default_vlan(struct cpsw_priv *priv) 10283b72c2feSMugunthan V N { 10293b72c2feSMugunthan V N const int vlan = priv->data.default_vlan; 10303b72c2feSMugunthan V N const int port = priv->host_port; 10313b72c2feSMugunthan V N u32 reg; 10323b72c2feSMugunthan V N int i; 10333b72c2feSMugunthan V N 10343b72c2feSMugunthan V N reg = (priv->version == CPSW_VERSION_1) ? CPSW1_PORT_VLAN : 10353b72c2feSMugunthan V N CPSW2_PORT_VLAN; 10363b72c2feSMugunthan V N 10373b72c2feSMugunthan V N writel(vlan, &priv->host_port_regs->port_vlan); 10383b72c2feSMugunthan V N 10390237c110SDaniel Mack for (i = 0; i < priv->data.slaves; i++) 10403b72c2feSMugunthan V N slave_write(priv->slaves + i, vlan, reg); 10413b72c2feSMugunthan V N 10423b72c2feSMugunthan V N cpsw_ale_add_vlan(priv->ale, vlan, ALE_ALL_PORTS << port, 10433b72c2feSMugunthan V N ALE_ALL_PORTS << port, ALE_ALL_PORTS << port, 10443b72c2feSMugunthan V N (ALE_PORT_1 | ALE_PORT_2) << port); 10453b72c2feSMugunthan V N } 10463b72c2feSMugunthan V N 1047df828598SMugunthan V N static void cpsw_init_host_port(struct cpsw_priv *priv) 1048df828598SMugunthan V N { 10493b72c2feSMugunthan V N u32 control_reg; 1050d9ba8f9eSMugunthan V N u32 fifo_mode; 10513b72c2feSMugunthan V N 1052df828598SMugunthan V N /* soft reset the controller and initialize ale */ 1053df828598SMugunthan V N soft_reset("cpsw", &priv->regs->soft_reset); 1054df828598SMugunthan V N cpsw_ale_start(priv->ale); 1055df828598SMugunthan V N 1056df828598SMugunthan V N /* switch to vlan unaware mode */ 10573b72c2feSMugunthan V N cpsw_ale_control_set(priv->ale, priv->host_port, ALE_VLAN_AWARE, 10583b72c2feSMugunthan V N CPSW_ALE_VLAN_AWARE); 10593b72c2feSMugunthan V N control_reg = readl(&priv->regs->control); 10603b72c2feSMugunthan V N control_reg |= CPSW_VLAN_AWARE; 10613b72c2feSMugunthan V N writel(control_reg, &priv->regs->control); 1062d9ba8f9eSMugunthan V N fifo_mode = (priv->data.dual_emac) ? CPSW_FIFO_DUAL_MAC_MODE : 1063d9ba8f9eSMugunthan V N CPSW_FIFO_NORMAL_MODE; 1064d9ba8f9eSMugunthan V N writel(fifo_mode, &priv->host_port_regs->tx_in_ctl); 1065df828598SMugunthan V N 1066df828598SMugunthan V N /* setup host port priority mapping */ 1067df828598SMugunthan V N __raw_writel(CPDMA_TX_PRIORITY_MAP, 1068df828598SMugunthan V N &priv->host_port_regs->cpdma_tx_pri_map); 1069df828598SMugunthan V N __raw_writel(0, &priv->host_port_regs->cpdma_rx_chan_map); 1070df828598SMugunthan V N 1071df828598SMugunthan V N cpsw_ale_control_set(priv->ale, priv->host_port, 1072df828598SMugunthan V N ALE_PORT_STATE, ALE_PORT_STATE_FORWARD); 1073df828598SMugunthan V N 1074d9ba8f9eSMugunthan V N if (!priv->data.dual_emac) { 1075d9ba8f9eSMugunthan V N cpsw_ale_add_ucast(priv->ale, priv->mac_addr, priv->host_port, 1076d9ba8f9eSMugunthan V N 0, 0); 1077df828598SMugunthan V N cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast, 1078e11b220fSMugunthan V N 1 << priv->host_port, 0, 0, ALE_MCAST_FWD_2); 1079df828598SMugunthan V N } 1080d9ba8f9eSMugunthan V N } 1081df828598SMugunthan V N 1082aacebbf8SSebastian Siewior static void cpsw_slave_stop(struct cpsw_slave *slave, struct cpsw_priv *priv) 1083aacebbf8SSebastian Siewior { 1084aacebbf8SSebastian Siewior if (!slave->phy) 1085aacebbf8SSebastian Siewior return; 1086aacebbf8SSebastian Siewior phy_stop(slave->phy); 1087aacebbf8SSebastian Siewior phy_disconnect(slave->phy); 1088aacebbf8SSebastian Siewior slave->phy = NULL; 1089aacebbf8SSebastian Siewior } 1090aacebbf8SSebastian Siewior 1091df828598SMugunthan V N static int cpsw_ndo_open(struct net_device *ndev) 1092df828598SMugunthan V N { 1093df828598SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 1094a11fbba9SSebastian Siewior struct cpsw_priv *prim_cpsw; 1095df828598SMugunthan V N int i, ret; 1096df828598SMugunthan V N u32 reg; 1097df828598SMugunthan V N 1098d9ba8f9eSMugunthan V N if (!cpsw_common_res_usage_state(priv)) 1099df828598SMugunthan V N cpsw_intr_disable(priv); 1100df828598SMugunthan V N netif_carrier_off(ndev); 1101df828598SMugunthan V N 1102f150bd7fSMugunthan V N pm_runtime_get_sync(&priv->pdev->dev); 1103df828598SMugunthan V N 1104549985eeSRichard Cochran reg = priv->version; 1105df828598SMugunthan V N 1106df828598SMugunthan V N dev_info(priv->dev, "initializing cpsw version %d.%d (%d)\n", 1107df828598SMugunthan V N CPSW_MAJOR_VERSION(reg), CPSW_MINOR_VERSION(reg), 1108df828598SMugunthan V N CPSW_RTL_VERSION(reg)); 1109df828598SMugunthan V N 1110df828598SMugunthan V N /* initialize host and slave ports */ 1111d9ba8f9eSMugunthan V N if (!cpsw_common_res_usage_state(priv)) 1112df828598SMugunthan V N cpsw_init_host_port(priv); 1113df828598SMugunthan V N for_each_slave(priv, cpsw_slave_open, priv); 1114df828598SMugunthan V N 11153b72c2feSMugunthan V N /* Add default VLAN */ 1116d9ba8f9eSMugunthan V N if (!priv->data.dual_emac) 11173b72c2feSMugunthan V N cpsw_add_default_vlan(priv); 11183b72c2feSMugunthan V N 1119d9ba8f9eSMugunthan V N if (!cpsw_common_res_usage_state(priv)) { 1120df828598SMugunthan V N /* setup tx dma to fixed prio and zero offset */ 1121df828598SMugunthan V N cpdma_control_set(priv->dma, CPDMA_TX_PRIO_FIXED, 1); 1122df828598SMugunthan V N cpdma_control_set(priv->dma, CPDMA_RX_BUFFER_OFFSET, 0); 1123df828598SMugunthan V N 1124d9ba8f9eSMugunthan V N /* disable priority elevation */ 1125df828598SMugunthan V N __raw_writel(0, &priv->regs->ptype); 1126df828598SMugunthan V N 1127d9ba8f9eSMugunthan V N /* enable statistics collection only on all ports */ 1128df828598SMugunthan V N __raw_writel(0x7, &priv->regs->stat_port_en); 1129df828598SMugunthan V N 1130df828598SMugunthan V N if (WARN_ON(!priv->data.rx_descs)) 1131df828598SMugunthan V N priv->data.rx_descs = 128; 1132df828598SMugunthan V N 1133df828598SMugunthan V N for (i = 0; i < priv->data.rx_descs; i++) { 1134df828598SMugunthan V N struct sk_buff *skb; 1135df828598SMugunthan V N 1136df828598SMugunthan V N ret = -ENOMEM; 1137aacebbf8SSebastian Siewior skb = __netdev_alloc_skb_ip_align(priv->ndev, 1138aacebbf8SSebastian Siewior priv->rx_packet_max, GFP_KERNEL); 1139df828598SMugunthan V N if (!skb) 1140aacebbf8SSebastian Siewior goto err_cleanup; 1141df828598SMugunthan V N ret = cpdma_chan_submit(priv->rxch, skb, skb->data, 1142aef614e1SSebastian Siewior skb_tailroom(skb), 0); 1143aacebbf8SSebastian Siewior if (ret < 0) { 1144aacebbf8SSebastian Siewior kfree_skb(skb); 1145aacebbf8SSebastian Siewior goto err_cleanup; 1146aacebbf8SSebastian Siewior } 1147df828598SMugunthan V N } 1148d9ba8f9eSMugunthan V N /* continue even if we didn't manage to submit all 1149d9ba8f9eSMugunthan V N * receive descs 1150d9ba8f9eSMugunthan V N */ 1151df828598SMugunthan V N cpsw_info(priv, ifup, "submitted %d rx descriptors\n", i); 1152d9ba8f9eSMugunthan V N } 1153df828598SMugunthan V N 1154ff5b8ef2SMugunthan V N /* Enable Interrupt pacing if configured */ 1155ff5b8ef2SMugunthan V N if (priv->coal_intvl != 0) { 1156ff5b8ef2SMugunthan V N struct ethtool_coalesce coal; 1157ff5b8ef2SMugunthan V N 1158ff5b8ef2SMugunthan V N coal.rx_coalesce_usecs = (priv->coal_intvl << 4); 1159ff5b8ef2SMugunthan V N cpsw_set_coalesce(ndev, &coal); 1160ff5b8ef2SMugunthan V N } 1161ff5b8ef2SMugunthan V N 1162a11fbba9SSebastian Siewior prim_cpsw = cpsw_get_slave_priv(priv, 0); 1163a11fbba9SSebastian Siewior if (prim_cpsw->irq_enabled == false) { 1164a11fbba9SSebastian Siewior if ((priv == prim_cpsw) || !netif_running(prim_cpsw->ndev)) { 1165a11fbba9SSebastian Siewior prim_cpsw->irq_enabled = true; 1166a11fbba9SSebastian Siewior cpsw_enable_irq(prim_cpsw); 1167a11fbba9SSebastian Siewior } 1168a11fbba9SSebastian Siewior } 1169a11fbba9SSebastian Siewior 1170df828598SMugunthan V N cpdma_ctlr_start(priv->dma); 1171df828598SMugunthan V N cpsw_intr_enable(priv); 1172df828598SMugunthan V N napi_enable(&priv->napi); 1173510a1e72SMugunthan V N cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_RX); 1174510a1e72SMugunthan V N cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_TX); 1175df828598SMugunthan V N 1176d9ba8f9eSMugunthan V N if (priv->data.dual_emac) 1177d9ba8f9eSMugunthan V N priv->slaves[priv->emac_port].open_stat = true; 1178df828598SMugunthan V N return 0; 1179df828598SMugunthan V N 1180aacebbf8SSebastian Siewior err_cleanup: 1181aacebbf8SSebastian Siewior cpdma_ctlr_stop(priv->dma); 1182aacebbf8SSebastian Siewior for_each_slave(priv, cpsw_slave_stop, priv); 1183aacebbf8SSebastian Siewior pm_runtime_put_sync(&priv->pdev->dev); 1184aacebbf8SSebastian Siewior netif_carrier_off(priv->ndev); 1185aacebbf8SSebastian Siewior return ret; 1186df828598SMugunthan V N } 1187df828598SMugunthan V N 1188df828598SMugunthan V N static int cpsw_ndo_stop(struct net_device *ndev) 1189df828598SMugunthan V N { 1190df828598SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 1191df828598SMugunthan V N 1192df828598SMugunthan V N cpsw_info(priv, ifdown, "shutting down cpsw device\n"); 1193df828598SMugunthan V N netif_stop_queue(priv->ndev); 1194df828598SMugunthan V N napi_disable(&priv->napi); 1195df828598SMugunthan V N netif_carrier_off(priv->ndev); 1196d9ba8f9eSMugunthan V N 1197d9ba8f9eSMugunthan V N if (cpsw_common_res_usage_state(priv) <= 1) { 119871380f9bSMugunthan V N cpsw_intr_disable(priv); 119971380f9bSMugunthan V N cpdma_ctlr_int_ctrl(priv->dma, false); 120071380f9bSMugunthan V N cpdma_ctlr_stop(priv->dma); 1201df828598SMugunthan V N cpsw_ale_stop(priv->ale); 1202d9ba8f9eSMugunthan V N } 1203df828598SMugunthan V N for_each_slave(priv, cpsw_slave_stop, priv); 1204f150bd7fSMugunthan V N pm_runtime_put_sync(&priv->pdev->dev); 1205d9ba8f9eSMugunthan V N if (priv->data.dual_emac) 1206d9ba8f9eSMugunthan V N priv->slaves[priv->emac_port].open_stat = false; 1207df828598SMugunthan V N return 0; 1208df828598SMugunthan V N } 1209df828598SMugunthan V N 1210df828598SMugunthan V N static netdev_tx_t cpsw_ndo_start_xmit(struct sk_buff *skb, 1211df828598SMugunthan V N struct net_device *ndev) 1212df828598SMugunthan V N { 1213df828598SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 1214df828598SMugunthan V N int ret; 1215df828598SMugunthan V N 1216df828598SMugunthan V N ndev->trans_start = jiffies; 1217df828598SMugunthan V N 1218df828598SMugunthan V N if (skb_padto(skb, CPSW_MIN_PACKET_SIZE)) { 1219df828598SMugunthan V N cpsw_err(priv, tx_err, "packet pad failed\n"); 1220df828598SMugunthan V N priv->stats.tx_dropped++; 1221df828598SMugunthan V N return NETDEV_TX_OK; 1222df828598SMugunthan V N } 1223df828598SMugunthan V N 12249232b16dSMugunthan V N if (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP && 12259232b16dSMugunthan V N priv->cpts->tx_enable) 12262e5b38abSRichard Cochran skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 12272e5b38abSRichard Cochran 12282e5b38abSRichard Cochran skb_tx_timestamp(skb); 12292e5b38abSRichard Cochran 1230d9ba8f9eSMugunthan V N ret = cpsw_tx_packet_submit(ndev, priv, skb); 1231df828598SMugunthan V N if (unlikely(ret != 0)) { 1232df828598SMugunthan V N cpsw_err(priv, tx_err, "desc submit failed\n"); 1233df828598SMugunthan V N goto fail; 1234df828598SMugunthan V N } 1235df828598SMugunthan V N 1236fae50823SMugunthan V N /* If there is no more tx desc left free then we need to 1237fae50823SMugunthan V N * tell the kernel to stop sending us tx frames. 1238fae50823SMugunthan V N */ 1239d35162f8SDaniel Mack if (unlikely(!cpdma_check_free_tx_desc(priv->txch))) 1240fae50823SMugunthan V N netif_stop_queue(ndev); 1241fae50823SMugunthan V N 1242df828598SMugunthan V N return NETDEV_TX_OK; 1243df828598SMugunthan V N fail: 1244df828598SMugunthan V N priv->stats.tx_dropped++; 1245df828598SMugunthan V N netif_stop_queue(ndev); 1246df828598SMugunthan V N return NETDEV_TX_BUSY; 1247df828598SMugunthan V N } 1248df828598SMugunthan V N 1249df828598SMugunthan V N static void cpsw_ndo_change_rx_flags(struct net_device *ndev, int flags) 1250df828598SMugunthan V N { 1251df828598SMugunthan V N /* 1252df828598SMugunthan V N * The switch cannot operate in promiscuous mode without substantial 1253df828598SMugunthan V N * headache. For promiscuous mode to work, we would need to put the 1254df828598SMugunthan V N * ALE in bypass mode and route all traffic to the host port. 1255df828598SMugunthan V N * Subsequently, the host will need to operate as a "bridge", learn, 1256df828598SMugunthan V N * and flood as needed. For now, we simply complain here and 1257df828598SMugunthan V N * do nothing about it :-) 1258df828598SMugunthan V N */ 1259df828598SMugunthan V N if ((flags & IFF_PROMISC) && (ndev->flags & IFF_PROMISC)) 1260df828598SMugunthan V N dev_err(&ndev->dev, "promiscuity ignored!\n"); 1261df828598SMugunthan V N 1262df828598SMugunthan V N /* 1263df828598SMugunthan V N * The switch cannot filter multicast traffic unless it is configured 1264df828598SMugunthan V N * in "VLAN Aware" mode. Unfortunately, VLAN awareness requires a 1265df828598SMugunthan V N * whole bunch of additional logic that this driver does not implement 1266df828598SMugunthan V N * at present. 1267df828598SMugunthan V N */ 1268df828598SMugunthan V N if ((flags & IFF_ALLMULTI) && !(ndev->flags & IFF_ALLMULTI)) 1269df828598SMugunthan V N dev_err(&ndev->dev, "multicast traffic cannot be filtered!\n"); 1270df828598SMugunthan V N } 1271df828598SMugunthan V N 12722e5b38abSRichard Cochran #ifdef CONFIG_TI_CPTS 12732e5b38abSRichard Cochran 12742e5b38abSRichard Cochran static void cpsw_hwtstamp_v1(struct cpsw_priv *priv) 12752e5b38abSRichard Cochran { 1276e86ac13bSMugunthan V N struct cpsw_slave *slave = &priv->slaves[priv->data.active_slave]; 12772e5b38abSRichard Cochran u32 ts_en, seq_id; 12782e5b38abSRichard Cochran 12799232b16dSMugunthan V N if (!priv->cpts->tx_enable && !priv->cpts->rx_enable) { 12802e5b38abSRichard Cochran slave_write(slave, 0, CPSW1_TS_CTL); 12812e5b38abSRichard Cochran return; 12822e5b38abSRichard Cochran } 12832e5b38abSRichard Cochran 12842e5b38abSRichard Cochran seq_id = (30 << CPSW_V1_SEQ_ID_OFS_SHIFT) | ETH_P_1588; 12852e5b38abSRichard Cochran ts_en = EVENT_MSG_BITS << CPSW_V1_MSG_TYPE_OFS; 12862e5b38abSRichard Cochran 12879232b16dSMugunthan V N if (priv->cpts->tx_enable) 12882e5b38abSRichard Cochran ts_en |= CPSW_V1_TS_TX_EN; 12892e5b38abSRichard Cochran 12909232b16dSMugunthan V N if (priv->cpts->rx_enable) 12912e5b38abSRichard Cochran ts_en |= CPSW_V1_TS_RX_EN; 12922e5b38abSRichard Cochran 12932e5b38abSRichard Cochran slave_write(slave, ts_en, CPSW1_TS_CTL); 12942e5b38abSRichard Cochran slave_write(slave, seq_id, CPSW1_TS_SEQ_LTYPE); 12952e5b38abSRichard Cochran } 12962e5b38abSRichard Cochran 12972e5b38abSRichard Cochran static void cpsw_hwtstamp_v2(struct cpsw_priv *priv) 12982e5b38abSRichard Cochran { 1299d9ba8f9eSMugunthan V N struct cpsw_slave *slave; 13002e5b38abSRichard Cochran u32 ctrl, mtype; 13012e5b38abSRichard Cochran 1302d9ba8f9eSMugunthan V N if (priv->data.dual_emac) 1303d9ba8f9eSMugunthan V N slave = &priv->slaves[priv->emac_port]; 1304d9ba8f9eSMugunthan V N else 1305e86ac13bSMugunthan V N slave = &priv->slaves[priv->data.active_slave]; 1306d9ba8f9eSMugunthan V N 13072e5b38abSRichard Cochran ctrl = slave_read(slave, CPSW2_CONTROL); 13082e5b38abSRichard Cochran ctrl &= ~CTRL_ALL_TS_MASK; 13092e5b38abSRichard Cochran 13109232b16dSMugunthan V N if (priv->cpts->tx_enable) 13112e5b38abSRichard Cochran ctrl |= CTRL_TX_TS_BITS; 13122e5b38abSRichard Cochran 13139232b16dSMugunthan V N if (priv->cpts->rx_enable) 13142e5b38abSRichard Cochran ctrl |= CTRL_RX_TS_BITS; 13152e5b38abSRichard Cochran 13162e5b38abSRichard Cochran mtype = (30 << TS_SEQ_ID_OFFSET_SHIFT) | EVENT_MSG_BITS; 13172e5b38abSRichard Cochran 13182e5b38abSRichard Cochran slave_write(slave, mtype, CPSW2_TS_SEQ_MTYPE); 13192e5b38abSRichard Cochran slave_write(slave, ctrl, CPSW2_CONTROL); 13202e5b38abSRichard Cochran __raw_writel(ETH_P_1588, &priv->regs->ts_ltype); 13212e5b38abSRichard Cochran } 13222e5b38abSRichard Cochran 13233177bf6fSMugunthan V N static int cpsw_hwtstamp_ioctl(struct net_device *dev, struct ifreq *ifr) 13242e5b38abSRichard Cochran { 13253177bf6fSMugunthan V N struct cpsw_priv *priv = netdev_priv(dev); 13269232b16dSMugunthan V N struct cpts *cpts = priv->cpts; 13272e5b38abSRichard Cochran struct hwtstamp_config cfg; 13282e5b38abSRichard Cochran 13292e5b38abSRichard Cochran if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg))) 13302e5b38abSRichard Cochran return -EFAULT; 13312e5b38abSRichard Cochran 13322e5b38abSRichard Cochran /* reserved for future extensions */ 13332e5b38abSRichard Cochran if (cfg.flags) 13342e5b38abSRichard Cochran return -EINVAL; 13352e5b38abSRichard Cochran 13362e5b38abSRichard Cochran switch (cfg.tx_type) { 13372e5b38abSRichard Cochran case HWTSTAMP_TX_OFF: 13382e5b38abSRichard Cochran cpts->tx_enable = 0; 13392e5b38abSRichard Cochran break; 13402e5b38abSRichard Cochran case HWTSTAMP_TX_ON: 13412e5b38abSRichard Cochran cpts->tx_enable = 1; 13422e5b38abSRichard Cochran break; 13432e5b38abSRichard Cochran default: 13442e5b38abSRichard Cochran return -ERANGE; 13452e5b38abSRichard Cochran } 13462e5b38abSRichard Cochran 13472e5b38abSRichard Cochran switch (cfg.rx_filter) { 13482e5b38abSRichard Cochran case HWTSTAMP_FILTER_NONE: 13492e5b38abSRichard Cochran cpts->rx_enable = 0; 13502e5b38abSRichard Cochran break; 13512e5b38abSRichard Cochran case HWTSTAMP_FILTER_ALL: 13522e5b38abSRichard Cochran case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: 13532e5b38abSRichard Cochran case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: 13542e5b38abSRichard Cochran case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: 13552e5b38abSRichard Cochran return -ERANGE; 13562e5b38abSRichard Cochran case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: 13572e5b38abSRichard Cochran case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 13582e5b38abSRichard Cochran case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 13592e5b38abSRichard Cochran case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: 13602e5b38abSRichard Cochran case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: 13612e5b38abSRichard Cochran case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: 13622e5b38abSRichard Cochran case HWTSTAMP_FILTER_PTP_V2_EVENT: 13632e5b38abSRichard Cochran case HWTSTAMP_FILTER_PTP_V2_SYNC: 13642e5b38abSRichard Cochran case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 13652e5b38abSRichard Cochran cpts->rx_enable = 1; 13662e5b38abSRichard Cochran cfg.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT; 13672e5b38abSRichard Cochran break; 13682e5b38abSRichard Cochran default: 13692e5b38abSRichard Cochran return -ERANGE; 13702e5b38abSRichard Cochran } 13712e5b38abSRichard Cochran 13722e5b38abSRichard Cochran switch (priv->version) { 13732e5b38abSRichard Cochran case CPSW_VERSION_1: 13742e5b38abSRichard Cochran cpsw_hwtstamp_v1(priv); 13752e5b38abSRichard Cochran break; 13762e5b38abSRichard Cochran case CPSW_VERSION_2: 13772e5b38abSRichard Cochran cpsw_hwtstamp_v2(priv); 13782e5b38abSRichard Cochran break; 13792e5b38abSRichard Cochran default: 13802e5b38abSRichard Cochran return -ENOTSUPP; 13812e5b38abSRichard Cochran } 13822e5b38abSRichard Cochran 13832e5b38abSRichard Cochran return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0; 13842e5b38abSRichard Cochran } 13852e5b38abSRichard Cochran 13862e5b38abSRichard Cochran #endif /*CONFIG_TI_CPTS*/ 13872e5b38abSRichard Cochran 13882e5b38abSRichard Cochran static int cpsw_ndo_ioctl(struct net_device *dev, struct ifreq *req, int cmd) 13892e5b38abSRichard Cochran { 139011f2c988SMugunthan V N struct cpsw_priv *priv = netdev_priv(dev); 139111f2c988SMugunthan V N struct mii_ioctl_data *data = if_mii(req); 139211f2c988SMugunthan V N int slave_no = cpsw_slave_index(priv); 139311f2c988SMugunthan V N 13942e5b38abSRichard Cochran if (!netif_running(dev)) 13952e5b38abSRichard Cochran return -EINVAL; 13962e5b38abSRichard Cochran 139711f2c988SMugunthan V N switch (cmd) { 13982e5b38abSRichard Cochran #ifdef CONFIG_TI_CPTS 139911f2c988SMugunthan V N case SIOCSHWTSTAMP: 14003177bf6fSMugunthan V N return cpsw_hwtstamp_ioctl(dev, req); 14012e5b38abSRichard Cochran #endif 140211f2c988SMugunthan V N case SIOCGMIIPHY: 140311f2c988SMugunthan V N data->phy_id = priv->slaves[slave_no].phy->addr; 140411f2c988SMugunthan V N break; 140511f2c988SMugunthan V N default: 14062e5b38abSRichard Cochran return -ENOTSUPP; 14072e5b38abSRichard Cochran } 14082e5b38abSRichard Cochran 140911f2c988SMugunthan V N return 0; 141011f2c988SMugunthan V N } 141111f2c988SMugunthan V N 1412df828598SMugunthan V N static void cpsw_ndo_tx_timeout(struct net_device *ndev) 1413df828598SMugunthan V N { 1414df828598SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 1415df828598SMugunthan V N 1416df828598SMugunthan V N cpsw_err(priv, tx_err, "transmit timeout, restarting dma\n"); 1417df828598SMugunthan V N priv->stats.tx_errors++; 1418df828598SMugunthan V N cpsw_intr_disable(priv); 1419df828598SMugunthan V N cpdma_ctlr_int_ctrl(priv->dma, false); 1420df828598SMugunthan V N cpdma_chan_stop(priv->txch); 1421df828598SMugunthan V N cpdma_chan_start(priv->txch); 1422df828598SMugunthan V N cpdma_ctlr_int_ctrl(priv->dma, true); 1423df828598SMugunthan V N cpsw_intr_enable(priv); 1424510a1e72SMugunthan V N cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_RX); 1425510a1e72SMugunthan V N cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_TX); 1426510a1e72SMugunthan V N 1427df828598SMugunthan V N } 1428df828598SMugunthan V N 1429dcfd8d58SMugunthan V N static int cpsw_ndo_set_mac_address(struct net_device *ndev, void *p) 1430dcfd8d58SMugunthan V N { 1431dcfd8d58SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 1432dcfd8d58SMugunthan V N struct sockaddr *addr = (struct sockaddr *)p; 1433dcfd8d58SMugunthan V N int flags = 0; 1434dcfd8d58SMugunthan V N u16 vid = 0; 1435dcfd8d58SMugunthan V N 1436dcfd8d58SMugunthan V N if (!is_valid_ether_addr(addr->sa_data)) 1437dcfd8d58SMugunthan V N return -EADDRNOTAVAIL; 1438dcfd8d58SMugunthan V N 1439dcfd8d58SMugunthan V N if (priv->data.dual_emac) { 1440dcfd8d58SMugunthan V N vid = priv->slaves[priv->emac_port].port_vlan; 1441dcfd8d58SMugunthan V N flags = ALE_VLAN; 1442dcfd8d58SMugunthan V N } 1443dcfd8d58SMugunthan V N 1444dcfd8d58SMugunthan V N cpsw_ale_del_ucast(priv->ale, priv->mac_addr, priv->host_port, 1445dcfd8d58SMugunthan V N flags, vid); 1446dcfd8d58SMugunthan V N cpsw_ale_add_ucast(priv->ale, addr->sa_data, priv->host_port, 1447dcfd8d58SMugunthan V N flags, vid); 1448dcfd8d58SMugunthan V N 1449dcfd8d58SMugunthan V N memcpy(priv->mac_addr, addr->sa_data, ETH_ALEN); 1450dcfd8d58SMugunthan V N memcpy(ndev->dev_addr, priv->mac_addr, ETH_ALEN); 1451dcfd8d58SMugunthan V N for_each_slave(priv, cpsw_set_slave_mac, priv); 1452dcfd8d58SMugunthan V N 1453dcfd8d58SMugunthan V N return 0; 1454dcfd8d58SMugunthan V N } 1455dcfd8d58SMugunthan V N 1456df828598SMugunthan V N static struct net_device_stats *cpsw_ndo_get_stats(struct net_device *ndev) 1457df828598SMugunthan V N { 1458df828598SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 1459df828598SMugunthan V N return &priv->stats; 1460df828598SMugunthan V N } 1461df828598SMugunthan V N 1462df828598SMugunthan V N #ifdef CONFIG_NET_POLL_CONTROLLER 1463df828598SMugunthan V N static void cpsw_ndo_poll_controller(struct net_device *ndev) 1464df828598SMugunthan V N { 1465df828598SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 1466df828598SMugunthan V N 1467df828598SMugunthan V N cpsw_intr_disable(priv); 1468df828598SMugunthan V N cpdma_ctlr_int_ctrl(priv->dma, false); 1469df828598SMugunthan V N cpsw_interrupt(ndev->irq, priv); 1470df828598SMugunthan V N cpdma_ctlr_int_ctrl(priv->dma, true); 1471df828598SMugunthan V N cpsw_intr_enable(priv); 1472510a1e72SMugunthan V N cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_RX); 1473510a1e72SMugunthan V N cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_TX); 1474510a1e72SMugunthan V N 1475df828598SMugunthan V N } 1476df828598SMugunthan V N #endif 1477df828598SMugunthan V N 14783b72c2feSMugunthan V N static inline int cpsw_add_vlan_ale_entry(struct cpsw_priv *priv, 14793b72c2feSMugunthan V N unsigned short vid) 14803b72c2feSMugunthan V N { 14813b72c2feSMugunthan V N int ret; 14823b72c2feSMugunthan V N 14833b72c2feSMugunthan V N ret = cpsw_ale_add_vlan(priv->ale, vid, 14843b72c2feSMugunthan V N ALE_ALL_PORTS << priv->host_port, 14853b72c2feSMugunthan V N 0, ALE_ALL_PORTS << priv->host_port, 14863b72c2feSMugunthan V N (ALE_PORT_1 | ALE_PORT_2) << priv->host_port); 14873b72c2feSMugunthan V N if (ret != 0) 14883b72c2feSMugunthan V N return ret; 14893b72c2feSMugunthan V N 14903b72c2feSMugunthan V N ret = cpsw_ale_add_ucast(priv->ale, priv->mac_addr, 14913b72c2feSMugunthan V N priv->host_port, ALE_VLAN, vid); 14923b72c2feSMugunthan V N if (ret != 0) 14933b72c2feSMugunthan V N goto clean_vid; 14943b72c2feSMugunthan V N 14953b72c2feSMugunthan V N ret = cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast, 14963b72c2feSMugunthan V N ALE_ALL_PORTS << priv->host_port, 14973b72c2feSMugunthan V N ALE_VLAN, vid, 0); 14983b72c2feSMugunthan V N if (ret != 0) 14993b72c2feSMugunthan V N goto clean_vlan_ucast; 15003b72c2feSMugunthan V N return 0; 15013b72c2feSMugunthan V N 15023b72c2feSMugunthan V N clean_vlan_ucast: 15033b72c2feSMugunthan V N cpsw_ale_del_ucast(priv->ale, priv->mac_addr, 15043b72c2feSMugunthan V N priv->host_port, ALE_VLAN, vid); 15053b72c2feSMugunthan V N clean_vid: 15063b72c2feSMugunthan V N cpsw_ale_del_vlan(priv->ale, vid, 0); 15073b72c2feSMugunthan V N return ret; 15083b72c2feSMugunthan V N } 15093b72c2feSMugunthan V N 15103b72c2feSMugunthan V N static int cpsw_ndo_vlan_rx_add_vid(struct net_device *ndev, 151180d5c368SPatrick McHardy __be16 proto, u16 vid) 15123b72c2feSMugunthan V N { 15133b72c2feSMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 15143b72c2feSMugunthan V N 15153b72c2feSMugunthan V N if (vid == priv->data.default_vlan) 15163b72c2feSMugunthan V N return 0; 15173b72c2feSMugunthan V N 15183b72c2feSMugunthan V N dev_info(priv->dev, "Adding vlanid %d to vlan filter\n", vid); 15193b72c2feSMugunthan V N return cpsw_add_vlan_ale_entry(priv, vid); 15203b72c2feSMugunthan V N } 15213b72c2feSMugunthan V N 15223b72c2feSMugunthan V N static int cpsw_ndo_vlan_rx_kill_vid(struct net_device *ndev, 152380d5c368SPatrick McHardy __be16 proto, u16 vid) 15243b72c2feSMugunthan V N { 15253b72c2feSMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 15263b72c2feSMugunthan V N int ret; 15273b72c2feSMugunthan V N 15283b72c2feSMugunthan V N if (vid == priv->data.default_vlan) 15293b72c2feSMugunthan V N return 0; 15303b72c2feSMugunthan V N 15313b72c2feSMugunthan V N dev_info(priv->dev, "removing vlanid %d from vlan filter\n", vid); 15323b72c2feSMugunthan V N ret = cpsw_ale_del_vlan(priv->ale, vid, 0); 15333b72c2feSMugunthan V N if (ret != 0) 15343b72c2feSMugunthan V N return ret; 15353b72c2feSMugunthan V N 15363b72c2feSMugunthan V N ret = cpsw_ale_del_ucast(priv->ale, priv->mac_addr, 15373b72c2feSMugunthan V N priv->host_port, ALE_VLAN, vid); 15383b72c2feSMugunthan V N if (ret != 0) 15393b72c2feSMugunthan V N return ret; 15403b72c2feSMugunthan V N 15413b72c2feSMugunthan V N return cpsw_ale_del_mcast(priv->ale, priv->ndev->broadcast, 15423b72c2feSMugunthan V N 0, ALE_VLAN, vid); 15433b72c2feSMugunthan V N } 15443b72c2feSMugunthan V N 1545df828598SMugunthan V N static const struct net_device_ops cpsw_netdev_ops = { 1546df828598SMugunthan V N .ndo_open = cpsw_ndo_open, 1547df828598SMugunthan V N .ndo_stop = cpsw_ndo_stop, 1548df828598SMugunthan V N .ndo_start_xmit = cpsw_ndo_start_xmit, 1549df828598SMugunthan V N .ndo_change_rx_flags = cpsw_ndo_change_rx_flags, 1550dcfd8d58SMugunthan V N .ndo_set_mac_address = cpsw_ndo_set_mac_address, 15512e5b38abSRichard Cochran .ndo_do_ioctl = cpsw_ndo_ioctl, 1552df828598SMugunthan V N .ndo_validate_addr = eth_validate_addr, 15535c473ed2SDavid S. Miller .ndo_change_mtu = eth_change_mtu, 1554df828598SMugunthan V N .ndo_tx_timeout = cpsw_ndo_tx_timeout, 1555df828598SMugunthan V N .ndo_get_stats = cpsw_ndo_get_stats, 15565c50a856SMugunthan V N .ndo_set_rx_mode = cpsw_ndo_set_rx_mode, 1557df828598SMugunthan V N #ifdef CONFIG_NET_POLL_CONTROLLER 1558df828598SMugunthan V N .ndo_poll_controller = cpsw_ndo_poll_controller, 1559df828598SMugunthan V N #endif 15603b72c2feSMugunthan V N .ndo_vlan_rx_add_vid = cpsw_ndo_vlan_rx_add_vid, 15613b72c2feSMugunthan V N .ndo_vlan_rx_kill_vid = cpsw_ndo_vlan_rx_kill_vid, 1562df828598SMugunthan V N }; 1563df828598SMugunthan V N 1564df828598SMugunthan V N static void cpsw_get_drvinfo(struct net_device *ndev, 1565df828598SMugunthan V N struct ethtool_drvinfo *info) 1566df828598SMugunthan V N { 1567df828598SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 15687826d43fSJiri Pirko 15697826d43fSJiri Pirko strlcpy(info->driver, "TI CPSW Driver v1.0", sizeof(info->driver)); 15707826d43fSJiri Pirko strlcpy(info->version, "1.0", sizeof(info->version)); 15717826d43fSJiri Pirko strlcpy(info->bus_info, priv->pdev->name, sizeof(info->bus_info)); 1572df828598SMugunthan V N } 1573df828598SMugunthan V N 1574df828598SMugunthan V N static u32 cpsw_get_msglevel(struct net_device *ndev) 1575df828598SMugunthan V N { 1576df828598SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 1577df828598SMugunthan V N return priv->msg_enable; 1578df828598SMugunthan V N } 1579df828598SMugunthan V N 1580df828598SMugunthan V N static void cpsw_set_msglevel(struct net_device *ndev, u32 value) 1581df828598SMugunthan V N { 1582df828598SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 1583df828598SMugunthan V N priv->msg_enable = value; 1584df828598SMugunthan V N } 1585df828598SMugunthan V N 15862e5b38abSRichard Cochran static int cpsw_get_ts_info(struct net_device *ndev, 15872e5b38abSRichard Cochran struct ethtool_ts_info *info) 15882e5b38abSRichard Cochran { 15892e5b38abSRichard Cochran #ifdef CONFIG_TI_CPTS 15902e5b38abSRichard Cochran struct cpsw_priv *priv = netdev_priv(ndev); 15912e5b38abSRichard Cochran 15922e5b38abSRichard Cochran info->so_timestamping = 15932e5b38abSRichard Cochran SOF_TIMESTAMPING_TX_HARDWARE | 15942e5b38abSRichard Cochran SOF_TIMESTAMPING_TX_SOFTWARE | 15952e5b38abSRichard Cochran SOF_TIMESTAMPING_RX_HARDWARE | 15962e5b38abSRichard Cochran SOF_TIMESTAMPING_RX_SOFTWARE | 15972e5b38abSRichard Cochran SOF_TIMESTAMPING_SOFTWARE | 15982e5b38abSRichard Cochran SOF_TIMESTAMPING_RAW_HARDWARE; 15999232b16dSMugunthan V N info->phc_index = priv->cpts->phc_index; 16002e5b38abSRichard Cochran info->tx_types = 16012e5b38abSRichard Cochran (1 << HWTSTAMP_TX_OFF) | 16022e5b38abSRichard Cochran (1 << HWTSTAMP_TX_ON); 16032e5b38abSRichard Cochran info->rx_filters = 16042e5b38abSRichard Cochran (1 << HWTSTAMP_FILTER_NONE) | 16052e5b38abSRichard Cochran (1 << HWTSTAMP_FILTER_PTP_V2_EVENT); 16062e5b38abSRichard Cochran #else 16072e5b38abSRichard Cochran info->so_timestamping = 16082e5b38abSRichard Cochran SOF_TIMESTAMPING_TX_SOFTWARE | 16092e5b38abSRichard Cochran SOF_TIMESTAMPING_RX_SOFTWARE | 16102e5b38abSRichard Cochran SOF_TIMESTAMPING_SOFTWARE; 16112e5b38abSRichard Cochran info->phc_index = -1; 16122e5b38abSRichard Cochran info->tx_types = 0; 16132e5b38abSRichard Cochran info->rx_filters = 0; 16142e5b38abSRichard Cochran #endif 16152e5b38abSRichard Cochran return 0; 16162e5b38abSRichard Cochran } 16172e5b38abSRichard Cochran 1618d3bb9c58SMugunthan V N static int cpsw_get_settings(struct net_device *ndev, 1619d3bb9c58SMugunthan V N struct ethtool_cmd *ecmd) 1620d3bb9c58SMugunthan V N { 1621d3bb9c58SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 1622d3bb9c58SMugunthan V N int slave_no = cpsw_slave_index(priv); 1623d3bb9c58SMugunthan V N 1624d3bb9c58SMugunthan V N if (priv->slaves[slave_no].phy) 1625d3bb9c58SMugunthan V N return phy_ethtool_gset(priv->slaves[slave_no].phy, ecmd); 1626d3bb9c58SMugunthan V N else 1627d3bb9c58SMugunthan V N return -EOPNOTSUPP; 1628d3bb9c58SMugunthan V N } 1629d3bb9c58SMugunthan V N 1630d3bb9c58SMugunthan V N static int cpsw_set_settings(struct net_device *ndev, struct ethtool_cmd *ecmd) 1631d3bb9c58SMugunthan V N { 1632d3bb9c58SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 1633d3bb9c58SMugunthan V N int slave_no = cpsw_slave_index(priv); 1634d3bb9c58SMugunthan V N 1635d3bb9c58SMugunthan V N if (priv->slaves[slave_no].phy) 1636d3bb9c58SMugunthan V N return phy_ethtool_sset(priv->slaves[slave_no].phy, ecmd); 1637d3bb9c58SMugunthan V N else 1638d3bb9c58SMugunthan V N return -EOPNOTSUPP; 1639d3bb9c58SMugunthan V N } 1640d3bb9c58SMugunthan V N 1641df828598SMugunthan V N static const struct ethtool_ops cpsw_ethtool_ops = { 1642df828598SMugunthan V N .get_drvinfo = cpsw_get_drvinfo, 1643df828598SMugunthan V N .get_msglevel = cpsw_get_msglevel, 1644df828598SMugunthan V N .set_msglevel = cpsw_set_msglevel, 1645df828598SMugunthan V N .get_link = ethtool_op_get_link, 16462e5b38abSRichard Cochran .get_ts_info = cpsw_get_ts_info, 1647d3bb9c58SMugunthan V N .get_settings = cpsw_get_settings, 1648d3bb9c58SMugunthan V N .set_settings = cpsw_set_settings, 1649ff5b8ef2SMugunthan V N .get_coalesce = cpsw_get_coalesce, 1650ff5b8ef2SMugunthan V N .set_coalesce = cpsw_set_coalesce, 1651d9718546SMugunthan V N .get_sset_count = cpsw_get_sset_count, 1652d9718546SMugunthan V N .get_strings = cpsw_get_strings, 1653d9718546SMugunthan V N .get_ethtool_stats = cpsw_get_ethtool_stats, 1654df828598SMugunthan V N }; 1655df828598SMugunthan V N 1656549985eeSRichard Cochran static void cpsw_slave_init(struct cpsw_slave *slave, struct cpsw_priv *priv, 1657549985eeSRichard Cochran u32 slave_reg_ofs, u32 sliver_reg_ofs) 1658df828598SMugunthan V N { 1659df828598SMugunthan V N void __iomem *regs = priv->regs; 1660df828598SMugunthan V N int slave_num = slave->slave_num; 1661df828598SMugunthan V N struct cpsw_slave_data *data = priv->data.slave_data + slave_num; 1662df828598SMugunthan V N 1663df828598SMugunthan V N slave->data = data; 1664549985eeSRichard Cochran slave->regs = regs + slave_reg_ofs; 1665549985eeSRichard Cochran slave->sliver = regs + sliver_reg_ofs; 1666d9ba8f9eSMugunthan V N slave->port_vlan = data->dual_emac_res_vlan; 1667df828598SMugunthan V N } 1668df828598SMugunthan V N 16692eb32b0aSMugunthan V N static int cpsw_probe_dt(struct cpsw_platform_data *data, 16702eb32b0aSMugunthan V N struct platform_device *pdev) 16712eb32b0aSMugunthan V N { 16722eb32b0aSMugunthan V N struct device_node *node = pdev->dev.of_node; 16732eb32b0aSMugunthan V N struct device_node *slave_node; 16742eb32b0aSMugunthan V N int i = 0, ret; 16752eb32b0aSMugunthan V N u32 prop; 16762eb32b0aSMugunthan V N 16772eb32b0aSMugunthan V N if (!node) 16782eb32b0aSMugunthan V N return -EINVAL; 16792eb32b0aSMugunthan V N 16802eb32b0aSMugunthan V N if (of_property_read_u32(node, "slaves", &prop)) { 16812eb32b0aSMugunthan V N pr_err("Missing slaves property in the DT.\n"); 16822eb32b0aSMugunthan V N return -EINVAL; 16832eb32b0aSMugunthan V N } 16842eb32b0aSMugunthan V N data->slaves = prop; 16852eb32b0aSMugunthan V N 1686e86ac13bSMugunthan V N if (of_property_read_u32(node, "active_slave", &prop)) { 1687e86ac13bSMugunthan V N pr_err("Missing active_slave property in the DT.\n"); 168878ca0b28SRichard Cochran ret = -EINVAL; 168978ca0b28SRichard Cochran goto error_ret; 169078ca0b28SRichard Cochran } 1691e86ac13bSMugunthan V N data->active_slave = prop; 169278ca0b28SRichard Cochran 169300ab94eeSRichard Cochran if (of_property_read_u32(node, "cpts_clock_mult", &prop)) { 169400ab94eeSRichard Cochran pr_err("Missing cpts_clock_mult property in the DT.\n"); 169500ab94eeSRichard Cochran ret = -EINVAL; 169600ab94eeSRichard Cochran goto error_ret; 169700ab94eeSRichard Cochran } 169800ab94eeSRichard Cochran data->cpts_clock_mult = prop; 169900ab94eeSRichard Cochran 170000ab94eeSRichard Cochran if (of_property_read_u32(node, "cpts_clock_shift", &prop)) { 170100ab94eeSRichard Cochran pr_err("Missing cpts_clock_shift property in the DT.\n"); 170200ab94eeSRichard Cochran ret = -EINVAL; 170300ab94eeSRichard Cochran goto error_ret; 170400ab94eeSRichard Cochran } 170500ab94eeSRichard Cochran data->cpts_clock_shift = prop; 170600ab94eeSRichard Cochran 1707b2adaca9SJoe Perches data->slave_data = kcalloc(data->slaves, sizeof(struct cpsw_slave_data), 1708b2adaca9SJoe Perches GFP_KERNEL); 1709b2adaca9SJoe Perches if (!data->slave_data) 17102eb32b0aSMugunthan V N return -EINVAL; 17112eb32b0aSMugunthan V N 17122eb32b0aSMugunthan V N if (of_property_read_u32(node, "cpdma_channels", &prop)) { 17132eb32b0aSMugunthan V N pr_err("Missing cpdma_channels property in the DT.\n"); 17142eb32b0aSMugunthan V N ret = -EINVAL; 17152eb32b0aSMugunthan V N goto error_ret; 17162eb32b0aSMugunthan V N } 17172eb32b0aSMugunthan V N data->channels = prop; 17182eb32b0aSMugunthan V N 17192eb32b0aSMugunthan V N if (of_property_read_u32(node, "ale_entries", &prop)) { 17202eb32b0aSMugunthan V N pr_err("Missing ale_entries property in the DT.\n"); 17212eb32b0aSMugunthan V N ret = -EINVAL; 17222eb32b0aSMugunthan V N goto error_ret; 17232eb32b0aSMugunthan V N } 17242eb32b0aSMugunthan V N data->ale_entries = prop; 17252eb32b0aSMugunthan V N 17262eb32b0aSMugunthan V N if (of_property_read_u32(node, "bd_ram_size", &prop)) { 17272eb32b0aSMugunthan V N pr_err("Missing bd_ram_size property in the DT.\n"); 17282eb32b0aSMugunthan V N ret = -EINVAL; 17292eb32b0aSMugunthan V N goto error_ret; 17302eb32b0aSMugunthan V N } 17312eb32b0aSMugunthan V N data->bd_ram_size = prop; 17322eb32b0aSMugunthan V N 17332eb32b0aSMugunthan V N if (of_property_read_u32(node, "rx_descs", &prop)) { 17342eb32b0aSMugunthan V N pr_err("Missing rx_descs property in the DT.\n"); 17352eb32b0aSMugunthan V N ret = -EINVAL; 17362eb32b0aSMugunthan V N goto error_ret; 17372eb32b0aSMugunthan V N } 17382eb32b0aSMugunthan V N data->rx_descs = prop; 17392eb32b0aSMugunthan V N 17402eb32b0aSMugunthan V N if (of_property_read_u32(node, "mac_control", &prop)) { 17412eb32b0aSMugunthan V N pr_err("Missing mac_control property in the DT.\n"); 17422eb32b0aSMugunthan V N ret = -EINVAL; 17432eb32b0aSMugunthan V N goto error_ret; 17442eb32b0aSMugunthan V N } 17452eb32b0aSMugunthan V N data->mac_control = prop; 17462eb32b0aSMugunthan V N 1747d9ba8f9eSMugunthan V N if (!of_property_read_u32(node, "dual_emac", &prop)) 1748d9ba8f9eSMugunthan V N data->dual_emac = prop; 1749d9ba8f9eSMugunthan V N 17501fb19aa7SVaibhav Hiremath /* 17511fb19aa7SVaibhav Hiremath * Populate all the child nodes here... 17521fb19aa7SVaibhav Hiremath */ 17531fb19aa7SVaibhav Hiremath ret = of_platform_populate(node, NULL, NULL, &pdev->dev); 17541fb19aa7SVaibhav Hiremath /* We do not want to force this, as in some cases may not have child */ 17551fb19aa7SVaibhav Hiremath if (ret) 17561fb19aa7SVaibhav Hiremath pr_warn("Doesn't have any child node\n"); 17571fb19aa7SVaibhav Hiremath 1758549985eeSRichard Cochran for_each_node_by_name(slave_node, "slave") { 1759549985eeSRichard Cochran struct cpsw_slave_data *slave_data = data->slave_data + i; 1760549985eeSRichard Cochran const void *mac_addr = NULL; 1761549985eeSRichard Cochran u32 phyid; 1762549985eeSRichard Cochran int lenp; 1763549985eeSRichard Cochran const __be32 *parp; 1764549985eeSRichard Cochran struct device_node *mdio_node; 1765549985eeSRichard Cochran struct platform_device *mdio; 1766549985eeSRichard Cochran 1767549985eeSRichard Cochran parp = of_get_property(slave_node, "phy_id", &lenp); 1768ce16294fSLothar Waßmann if ((parp == NULL) || (lenp != (sizeof(void *) * 2))) { 1769549985eeSRichard Cochran pr_err("Missing slave[%d] phy_id property\n", i); 1770549985eeSRichard Cochran ret = -EINVAL; 1771549985eeSRichard Cochran goto error_ret; 1772549985eeSRichard Cochran } 1773549985eeSRichard Cochran mdio_node = of_find_node_by_phandle(be32_to_cpup(parp)); 1774549985eeSRichard Cochran phyid = be32_to_cpup(parp+1); 1775549985eeSRichard Cochran mdio = of_find_device_by_node(mdio_node); 1776549985eeSRichard Cochran snprintf(slave_data->phy_id, sizeof(slave_data->phy_id), 1777549985eeSRichard Cochran PHY_ID_FMT, mdio->name, phyid); 1778549985eeSRichard Cochran 1779549985eeSRichard Cochran mac_addr = of_get_mac_address(slave_node); 1780549985eeSRichard Cochran if (mac_addr) 1781549985eeSRichard Cochran memcpy(slave_data->mac_addr, mac_addr, ETH_ALEN); 1782549985eeSRichard Cochran 1783c5ceea7aSMugunthan V N slave_data->phy_if = of_get_phy_mode(slave_node); 1784c5ceea7aSMugunthan V N 1785d9ba8f9eSMugunthan V N if (data->dual_emac) { 178691c4166cSMugunthan V N if (of_property_read_u32(slave_node, "dual_emac_res_vlan", 1787d9ba8f9eSMugunthan V N &prop)) { 1788d9ba8f9eSMugunthan V N pr_err("Missing dual_emac_res_vlan in DT.\n"); 1789d9ba8f9eSMugunthan V N slave_data->dual_emac_res_vlan = i+1; 1790d9ba8f9eSMugunthan V N pr_err("Using %d as Reserved VLAN for %d slave\n", 1791d9ba8f9eSMugunthan V N slave_data->dual_emac_res_vlan, i); 1792d9ba8f9eSMugunthan V N } else { 1793d9ba8f9eSMugunthan V N slave_data->dual_emac_res_vlan = prop; 1794d9ba8f9eSMugunthan V N } 1795d9ba8f9eSMugunthan V N } 1796d9ba8f9eSMugunthan V N 1797549985eeSRichard Cochran i++; 1798549985eeSRichard Cochran } 1799549985eeSRichard Cochran 18002eb32b0aSMugunthan V N return 0; 18012eb32b0aSMugunthan V N 18022eb32b0aSMugunthan V N error_ret: 18032eb32b0aSMugunthan V N kfree(data->slave_data); 18042eb32b0aSMugunthan V N return ret; 18052eb32b0aSMugunthan V N } 18062eb32b0aSMugunthan V N 1807d9ba8f9eSMugunthan V N static int cpsw_probe_dual_emac(struct platform_device *pdev, 1808d9ba8f9eSMugunthan V N struct cpsw_priv *priv) 1809d9ba8f9eSMugunthan V N { 1810d9ba8f9eSMugunthan V N struct cpsw_platform_data *data = &priv->data; 1811d9ba8f9eSMugunthan V N struct net_device *ndev; 1812d9ba8f9eSMugunthan V N struct cpsw_priv *priv_sl2; 1813d9ba8f9eSMugunthan V N int ret = 0, i; 1814d9ba8f9eSMugunthan V N 1815d9ba8f9eSMugunthan V N ndev = alloc_etherdev(sizeof(struct cpsw_priv)); 1816d9ba8f9eSMugunthan V N if (!ndev) { 1817d9ba8f9eSMugunthan V N pr_err("cpsw: error allocating net_device\n"); 1818d9ba8f9eSMugunthan V N return -ENOMEM; 1819d9ba8f9eSMugunthan V N } 1820d9ba8f9eSMugunthan V N 1821d9ba8f9eSMugunthan V N priv_sl2 = netdev_priv(ndev); 1822d9ba8f9eSMugunthan V N spin_lock_init(&priv_sl2->lock); 1823d9ba8f9eSMugunthan V N priv_sl2->data = *data; 1824d9ba8f9eSMugunthan V N priv_sl2->pdev = pdev; 1825d9ba8f9eSMugunthan V N priv_sl2->ndev = ndev; 1826d9ba8f9eSMugunthan V N priv_sl2->dev = &ndev->dev; 1827d9ba8f9eSMugunthan V N priv_sl2->msg_enable = netif_msg_init(debug_level, CPSW_DEBUG); 1828d9ba8f9eSMugunthan V N priv_sl2->rx_packet_max = max(rx_packet_max, 128); 1829d9ba8f9eSMugunthan V N 1830d9ba8f9eSMugunthan V N if (is_valid_ether_addr(data->slave_data[1].mac_addr)) { 1831d9ba8f9eSMugunthan V N memcpy(priv_sl2->mac_addr, data->slave_data[1].mac_addr, 1832d9ba8f9eSMugunthan V N ETH_ALEN); 1833d9ba8f9eSMugunthan V N pr_info("cpsw: Detected MACID = %pM\n", priv_sl2->mac_addr); 1834d9ba8f9eSMugunthan V N } else { 1835d9ba8f9eSMugunthan V N random_ether_addr(priv_sl2->mac_addr); 1836d9ba8f9eSMugunthan V N pr_info("cpsw: Random MACID = %pM\n", priv_sl2->mac_addr); 1837d9ba8f9eSMugunthan V N } 1838d9ba8f9eSMugunthan V N memcpy(ndev->dev_addr, priv_sl2->mac_addr, ETH_ALEN); 1839d9ba8f9eSMugunthan V N 1840d9ba8f9eSMugunthan V N priv_sl2->slaves = priv->slaves; 1841d9ba8f9eSMugunthan V N priv_sl2->clk = priv->clk; 1842d9ba8f9eSMugunthan V N 1843ff5b8ef2SMugunthan V N priv_sl2->coal_intvl = 0; 1844ff5b8ef2SMugunthan V N priv_sl2->bus_freq_mhz = priv->bus_freq_mhz; 1845ff5b8ef2SMugunthan V N 1846d9ba8f9eSMugunthan V N priv_sl2->cpsw_res = priv->cpsw_res; 1847d9ba8f9eSMugunthan V N priv_sl2->regs = priv->regs; 1848d9ba8f9eSMugunthan V N priv_sl2->host_port = priv->host_port; 1849d9ba8f9eSMugunthan V N priv_sl2->host_port_regs = priv->host_port_regs; 1850d9ba8f9eSMugunthan V N priv_sl2->wr_regs = priv->wr_regs; 1851d9718546SMugunthan V N priv_sl2->hw_stats = priv->hw_stats; 1852d9ba8f9eSMugunthan V N priv_sl2->dma = priv->dma; 1853d9ba8f9eSMugunthan V N priv_sl2->txch = priv->txch; 1854d9ba8f9eSMugunthan V N priv_sl2->rxch = priv->rxch; 1855d9ba8f9eSMugunthan V N priv_sl2->ale = priv->ale; 1856d9ba8f9eSMugunthan V N priv_sl2->emac_port = 1; 1857d9ba8f9eSMugunthan V N priv->slaves[1].ndev = ndev; 1858d9ba8f9eSMugunthan V N priv_sl2->cpts = priv->cpts; 1859d9ba8f9eSMugunthan V N priv_sl2->version = priv->version; 1860d9ba8f9eSMugunthan V N 1861d9ba8f9eSMugunthan V N for (i = 0; i < priv->num_irqs; i++) { 1862d9ba8f9eSMugunthan V N priv_sl2->irqs_table[i] = priv->irqs_table[i]; 1863d9ba8f9eSMugunthan V N priv_sl2->num_irqs = priv->num_irqs; 1864d9ba8f9eSMugunthan V N } 1865f646968fSPatrick McHardy ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER; 1866d9ba8f9eSMugunthan V N 1867d9ba8f9eSMugunthan V N ndev->netdev_ops = &cpsw_netdev_ops; 1868d9ba8f9eSMugunthan V N SET_ETHTOOL_OPS(ndev, &cpsw_ethtool_ops); 1869d9ba8f9eSMugunthan V N netif_napi_add(ndev, &priv_sl2->napi, cpsw_poll, CPSW_POLL_WEIGHT); 1870d9ba8f9eSMugunthan V N 1871d9ba8f9eSMugunthan V N /* register the network device */ 1872d9ba8f9eSMugunthan V N SET_NETDEV_DEV(ndev, &pdev->dev); 1873d9ba8f9eSMugunthan V N ret = register_netdev(ndev); 1874d9ba8f9eSMugunthan V N if (ret) { 1875d9ba8f9eSMugunthan V N pr_err("cpsw: error registering net device\n"); 1876d9ba8f9eSMugunthan V N free_netdev(ndev); 1877d9ba8f9eSMugunthan V N ret = -ENODEV; 1878d9ba8f9eSMugunthan V N } 1879d9ba8f9eSMugunthan V N 1880d9ba8f9eSMugunthan V N return ret; 1881d9ba8f9eSMugunthan V N } 1882d9ba8f9eSMugunthan V N 1883663e12e6SBill Pemberton static int cpsw_probe(struct platform_device *pdev) 1884df828598SMugunthan V N { 1885d1bd9acfSSebastian Siewior struct cpsw_platform_data *data; 1886df828598SMugunthan V N struct net_device *ndev; 1887df828598SMugunthan V N struct cpsw_priv *priv; 1888df828598SMugunthan V N struct cpdma_params dma_params; 1889df828598SMugunthan V N struct cpsw_ale_params ale_params; 1890549985eeSRichard Cochran void __iomem *ss_regs, *wr_regs; 1891df828598SMugunthan V N struct resource *res; 1892549985eeSRichard Cochran u32 slave_offset, sliver_offset, slave_size; 1893df828598SMugunthan V N int ret = 0, i, k = 0; 1894df828598SMugunthan V N 1895df828598SMugunthan V N ndev = alloc_etherdev(sizeof(struct cpsw_priv)); 1896df828598SMugunthan V N if (!ndev) { 1897df828598SMugunthan V N pr_err("error allocating net_device\n"); 1898df828598SMugunthan V N return -ENOMEM; 1899df828598SMugunthan V N } 1900df828598SMugunthan V N 1901df828598SMugunthan V N platform_set_drvdata(pdev, ndev); 1902df828598SMugunthan V N priv = netdev_priv(ndev); 1903df828598SMugunthan V N spin_lock_init(&priv->lock); 1904df828598SMugunthan V N priv->pdev = pdev; 1905df828598SMugunthan V N priv->ndev = ndev; 1906df828598SMugunthan V N priv->dev = &ndev->dev; 1907df828598SMugunthan V N priv->msg_enable = netif_msg_init(debug_level, CPSW_DEBUG); 1908df828598SMugunthan V N priv->rx_packet_max = max(rx_packet_max, 128); 19099232b16dSMugunthan V N priv->cpts = devm_kzalloc(&pdev->dev, sizeof(struct cpts), GFP_KERNEL); 19107dcf313aSMugunthan V N priv->irq_enabled = true; 1911ab8e99d2SSebastian Siewior if (!priv->cpts) { 19129232b16dSMugunthan V N pr_err("error allocating cpts\n"); 19139232b16dSMugunthan V N goto clean_ndev_ret; 19149232b16dSMugunthan V N } 1915df828598SMugunthan V N 19161fb19aa7SVaibhav Hiremath /* 19171fb19aa7SVaibhav Hiremath * This may be required here for child devices. 19181fb19aa7SVaibhav Hiremath */ 19191fb19aa7SVaibhav Hiremath pm_runtime_enable(&pdev->dev); 19201fb19aa7SVaibhav Hiremath 1921739683b4SMugunthan V N /* Select default pin state */ 1922739683b4SMugunthan V N pinctrl_pm_select_default_state(&pdev->dev); 1923739683b4SMugunthan V N 19242eb32b0aSMugunthan V N if (cpsw_probe_dt(&priv->data, pdev)) { 19252eb32b0aSMugunthan V N pr_err("cpsw: platform data missing\n"); 19262eb32b0aSMugunthan V N ret = -ENODEV; 19272eb32b0aSMugunthan V N goto clean_ndev_ret; 19282eb32b0aSMugunthan V N } 19292eb32b0aSMugunthan V N data = &priv->data; 19302eb32b0aSMugunthan V N 1931df828598SMugunthan V N if (is_valid_ether_addr(data->slave_data[0].mac_addr)) { 1932df828598SMugunthan V N memcpy(priv->mac_addr, data->slave_data[0].mac_addr, ETH_ALEN); 1933cf6122beSDaniel Mack pr_info("Detected MACID = %pM\n", priv->mac_addr); 1934df828598SMugunthan V N } else { 19357efd26d0SJoe Perches eth_random_addr(priv->mac_addr); 1936cf6122beSDaniel Mack pr_info("Random MACID = %pM\n", priv->mac_addr); 1937df828598SMugunthan V N } 1938df828598SMugunthan V N 1939df828598SMugunthan V N memcpy(ndev->dev_addr, priv->mac_addr, ETH_ALEN); 1940df828598SMugunthan V N 1941df828598SMugunthan V N priv->slaves = kzalloc(sizeof(struct cpsw_slave) * data->slaves, 1942df828598SMugunthan V N GFP_KERNEL); 1943df828598SMugunthan V N if (!priv->slaves) { 1944df828598SMugunthan V N ret = -EBUSY; 1945df828598SMugunthan V N goto clean_ndev_ret; 1946df828598SMugunthan V N } 1947df828598SMugunthan V N for (i = 0; i < data->slaves; i++) 1948df828598SMugunthan V N priv->slaves[i].slave_num = i; 1949df828598SMugunthan V N 1950d9ba8f9eSMugunthan V N priv->slaves[0].ndev = ndev; 1951d9ba8f9eSMugunthan V N priv->emac_port = 0; 1952d9ba8f9eSMugunthan V N 1953f150bd7fSMugunthan V N priv->clk = clk_get(&pdev->dev, "fck"); 1954df828598SMugunthan V N if (IS_ERR(priv->clk)) { 1955f150bd7fSMugunthan V N dev_err(&pdev->dev, "fck is not found\n"); 1956f150bd7fSMugunthan V N ret = -ENODEV; 1957f150bd7fSMugunthan V N goto clean_slave_ret; 1958df828598SMugunthan V N } 1959ff5b8ef2SMugunthan V N priv->coal_intvl = 0; 1960ff5b8ef2SMugunthan V N priv->bus_freq_mhz = clk_get_rate(priv->clk) / 1000000; 1961df828598SMugunthan V N 1962df828598SMugunthan V N priv->cpsw_res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1963df828598SMugunthan V N if (!priv->cpsw_res) { 1964df828598SMugunthan V N dev_err(priv->dev, "error getting i/o resource\n"); 1965df828598SMugunthan V N ret = -ENOENT; 1966df828598SMugunthan V N goto clean_clk_ret; 1967df828598SMugunthan V N } 1968df828598SMugunthan V N if (!request_mem_region(priv->cpsw_res->start, 1969df828598SMugunthan V N resource_size(priv->cpsw_res), ndev->name)) { 1970df828598SMugunthan V N dev_err(priv->dev, "failed request i/o region\n"); 1971df828598SMugunthan V N ret = -ENXIO; 1972df828598SMugunthan V N goto clean_clk_ret; 1973df828598SMugunthan V N } 1974549985eeSRichard Cochran ss_regs = ioremap(priv->cpsw_res->start, resource_size(priv->cpsw_res)); 1975549985eeSRichard Cochran if (!ss_regs) { 1976df828598SMugunthan V N dev_err(priv->dev, "unable to map i/o region\n"); 1977df828598SMugunthan V N goto clean_cpsw_iores_ret; 1978df828598SMugunthan V N } 1979549985eeSRichard Cochran priv->regs = ss_regs; 1980549985eeSRichard Cochran priv->version = __raw_readl(&priv->regs->id_ver); 1981549985eeSRichard Cochran priv->host_port = HOST_PORT_NUM; 1982df828598SMugunthan V N 1983a65dd5b2SRichard Cochran priv->cpsw_wr_res = platform_get_resource(pdev, IORESOURCE_MEM, 1); 1984a65dd5b2SRichard Cochran if (!priv->cpsw_wr_res) { 1985df828598SMugunthan V N dev_err(priv->dev, "error getting i/o resource\n"); 1986df828598SMugunthan V N ret = -ENOENT; 19875250c969SRichard Cochran goto clean_iomap_ret; 1988df828598SMugunthan V N } 1989a65dd5b2SRichard Cochran if (!request_mem_region(priv->cpsw_wr_res->start, 1990a65dd5b2SRichard Cochran resource_size(priv->cpsw_wr_res), ndev->name)) { 1991df828598SMugunthan V N dev_err(priv->dev, "failed request i/o region\n"); 1992df828598SMugunthan V N ret = -ENXIO; 19935250c969SRichard Cochran goto clean_iomap_ret; 1994df828598SMugunthan V N } 1995549985eeSRichard Cochran wr_regs = ioremap(priv->cpsw_wr_res->start, 1996a65dd5b2SRichard Cochran resource_size(priv->cpsw_wr_res)); 1997549985eeSRichard Cochran if (!wr_regs) { 1998df828598SMugunthan V N dev_err(priv->dev, "unable to map i/o region\n"); 1999a65dd5b2SRichard Cochran goto clean_cpsw_wr_iores_ret; 2000df828598SMugunthan V N } 2001549985eeSRichard Cochran priv->wr_regs = wr_regs; 2002df828598SMugunthan V N 2003df828598SMugunthan V N memset(&dma_params, 0, sizeof(dma_params)); 2004549985eeSRichard Cochran memset(&ale_params, 0, sizeof(ale_params)); 2005549985eeSRichard Cochran 2006549985eeSRichard Cochran switch (priv->version) { 2007549985eeSRichard Cochran case CPSW_VERSION_1: 2008549985eeSRichard Cochran priv->host_port_regs = ss_regs + CPSW1_HOST_PORT_OFFSET; 20099232b16dSMugunthan V N priv->cpts->reg = ss_regs + CPSW1_CPTS_OFFSET; 2010d9718546SMugunthan V N priv->hw_stats = ss_regs + CPSW1_HW_STATS; 2011549985eeSRichard Cochran dma_params.dmaregs = ss_regs + CPSW1_CPDMA_OFFSET; 2012549985eeSRichard Cochran dma_params.txhdp = ss_regs + CPSW1_STATERAM_OFFSET; 2013549985eeSRichard Cochran ale_params.ale_regs = ss_regs + CPSW1_ALE_OFFSET; 2014549985eeSRichard Cochran slave_offset = CPSW1_SLAVE_OFFSET; 2015549985eeSRichard Cochran slave_size = CPSW1_SLAVE_SIZE; 2016549985eeSRichard Cochran sliver_offset = CPSW1_SLIVER_OFFSET; 2017549985eeSRichard Cochran dma_params.desc_mem_phys = 0; 2018549985eeSRichard Cochran break; 2019549985eeSRichard Cochran case CPSW_VERSION_2: 2020c193f365SMugunthan V N case CPSW_VERSION_3: 2021549985eeSRichard Cochran priv->host_port_regs = ss_regs + CPSW2_HOST_PORT_OFFSET; 20229232b16dSMugunthan V N priv->cpts->reg = ss_regs + CPSW2_CPTS_OFFSET; 2023d9718546SMugunthan V N priv->hw_stats = ss_regs + CPSW2_HW_STATS; 2024549985eeSRichard Cochran dma_params.dmaregs = ss_regs + CPSW2_CPDMA_OFFSET; 2025549985eeSRichard Cochran dma_params.txhdp = ss_regs + CPSW2_STATERAM_OFFSET; 2026549985eeSRichard Cochran ale_params.ale_regs = ss_regs + CPSW2_ALE_OFFSET; 2027549985eeSRichard Cochran slave_offset = CPSW2_SLAVE_OFFSET; 2028549985eeSRichard Cochran slave_size = CPSW2_SLAVE_SIZE; 2029549985eeSRichard Cochran sliver_offset = CPSW2_SLIVER_OFFSET; 2030549985eeSRichard Cochran dma_params.desc_mem_phys = 2031549985eeSRichard Cochran (u32 __force) priv->cpsw_res->start + CPSW2_BD_OFFSET; 2032549985eeSRichard Cochran break; 2033549985eeSRichard Cochran default: 2034549985eeSRichard Cochran dev_err(priv->dev, "unknown version 0x%08x\n", priv->version); 2035549985eeSRichard Cochran ret = -ENODEV; 2036549985eeSRichard Cochran goto clean_cpsw_wr_iores_ret; 2037549985eeSRichard Cochran } 2038549985eeSRichard Cochran for (i = 0; i < priv->data.slaves; i++) { 2039549985eeSRichard Cochran struct cpsw_slave *slave = &priv->slaves[i]; 2040549985eeSRichard Cochran cpsw_slave_init(slave, priv, slave_offset, sliver_offset); 2041549985eeSRichard Cochran slave_offset += slave_size; 2042549985eeSRichard Cochran sliver_offset += SLIVER_SIZE; 2043549985eeSRichard Cochran } 2044549985eeSRichard Cochran 2045df828598SMugunthan V N dma_params.dev = &pdev->dev; 2046549985eeSRichard Cochran dma_params.rxthresh = dma_params.dmaregs + CPDMA_RXTHRESH; 2047549985eeSRichard Cochran dma_params.rxfree = dma_params.dmaregs + CPDMA_RXFREE; 2048549985eeSRichard Cochran dma_params.rxhdp = dma_params.txhdp + CPDMA_RXHDP; 2049549985eeSRichard Cochran dma_params.txcp = dma_params.txhdp + CPDMA_TXCP; 2050549985eeSRichard Cochran dma_params.rxcp = dma_params.txhdp + CPDMA_RXCP; 2051df828598SMugunthan V N 2052df828598SMugunthan V N dma_params.num_chan = data->channels; 2053df828598SMugunthan V N dma_params.has_soft_reset = true; 2054df828598SMugunthan V N dma_params.min_packet_size = CPSW_MIN_PACKET_SIZE; 2055df828598SMugunthan V N dma_params.desc_mem_size = data->bd_ram_size; 2056df828598SMugunthan V N dma_params.desc_align = 16; 2057df828598SMugunthan V N dma_params.has_ext_regs = true; 2058549985eeSRichard Cochran dma_params.desc_hw_addr = dma_params.desc_mem_phys; 2059df828598SMugunthan V N 2060df828598SMugunthan V N priv->dma = cpdma_ctlr_create(&dma_params); 2061df828598SMugunthan V N if (!priv->dma) { 2062df828598SMugunthan V N dev_err(priv->dev, "error initializing dma\n"); 2063df828598SMugunthan V N ret = -ENOMEM; 20645250c969SRichard Cochran goto clean_wr_iomap_ret; 2065df828598SMugunthan V N } 2066df828598SMugunthan V N 2067df828598SMugunthan V N priv->txch = cpdma_chan_create(priv->dma, tx_chan_num(0), 2068df828598SMugunthan V N cpsw_tx_handler); 2069df828598SMugunthan V N priv->rxch = cpdma_chan_create(priv->dma, rx_chan_num(0), 2070df828598SMugunthan V N cpsw_rx_handler); 2071df828598SMugunthan V N 2072df828598SMugunthan V N if (WARN_ON(!priv->txch || !priv->rxch)) { 2073df828598SMugunthan V N dev_err(priv->dev, "error initializing dma channels\n"); 2074df828598SMugunthan V N ret = -ENOMEM; 2075df828598SMugunthan V N goto clean_dma_ret; 2076df828598SMugunthan V N } 2077df828598SMugunthan V N 2078df828598SMugunthan V N ale_params.dev = &ndev->dev; 2079df828598SMugunthan V N ale_params.ale_ageout = ale_ageout; 2080df828598SMugunthan V N ale_params.ale_entries = data->ale_entries; 2081df828598SMugunthan V N ale_params.ale_ports = data->slaves; 2082df828598SMugunthan V N 2083df828598SMugunthan V N priv->ale = cpsw_ale_create(&ale_params); 2084df828598SMugunthan V N if (!priv->ale) { 2085df828598SMugunthan V N dev_err(priv->dev, "error initializing ale engine\n"); 2086df828598SMugunthan V N ret = -ENODEV; 2087df828598SMugunthan V N goto clean_dma_ret; 2088df828598SMugunthan V N } 2089df828598SMugunthan V N 2090df828598SMugunthan V N ndev->irq = platform_get_irq(pdev, 0); 2091df828598SMugunthan V N if (ndev->irq < 0) { 2092df828598SMugunthan V N dev_err(priv->dev, "error getting irq resource\n"); 2093df828598SMugunthan V N ret = -ENOENT; 2094df828598SMugunthan V N goto clean_ale_ret; 2095df828598SMugunthan V N } 2096df828598SMugunthan V N 2097df828598SMugunthan V N while ((res = platform_get_resource(priv->pdev, IORESOURCE_IRQ, k))) { 2098df828598SMugunthan V N for (i = res->start; i <= res->end; i++) { 20997069f982SFelipe Balbi if (request_irq(i, cpsw_interrupt, 0, 2100df828598SMugunthan V N dev_name(&pdev->dev), priv)) { 2101df828598SMugunthan V N dev_err(priv->dev, "error attaching irq\n"); 2102df828598SMugunthan V N goto clean_ale_ret; 2103df828598SMugunthan V N } 2104df828598SMugunthan V N priv->irqs_table[k] = i; 2105d1bd9acfSSebastian Siewior priv->num_irqs = k + 1; 2106df828598SMugunthan V N } 2107df828598SMugunthan V N k++; 2108df828598SMugunthan V N } 2109df828598SMugunthan V N 2110f646968fSPatrick McHardy ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER; 2111df828598SMugunthan V N 2112df828598SMugunthan V N ndev->netdev_ops = &cpsw_netdev_ops; 2113df828598SMugunthan V N SET_ETHTOOL_OPS(ndev, &cpsw_ethtool_ops); 2114df828598SMugunthan V N netif_napi_add(ndev, &priv->napi, cpsw_poll, CPSW_POLL_WEIGHT); 2115df828598SMugunthan V N 2116df828598SMugunthan V N /* register the network device */ 2117df828598SMugunthan V N SET_NETDEV_DEV(ndev, &pdev->dev); 2118df828598SMugunthan V N ret = register_netdev(ndev); 2119df828598SMugunthan V N if (ret) { 2120df828598SMugunthan V N dev_err(priv->dev, "error registering net device\n"); 2121df828598SMugunthan V N ret = -ENODEV; 2122df828598SMugunthan V N goto clean_irq_ret; 2123df828598SMugunthan V N } 2124df828598SMugunthan V N 21259232b16dSMugunthan V N if (cpts_register(&pdev->dev, priv->cpts, 21262e5b38abSRichard Cochran data->cpts_clock_mult, data->cpts_clock_shift)) 21272e5b38abSRichard Cochran dev_err(priv->dev, "error registering cpts device\n"); 21282e5b38abSRichard Cochran 2129df828598SMugunthan V N cpsw_notice(priv, probe, "initialized device (regs %x, irq %d)\n", 2130df828598SMugunthan V N priv->cpsw_res->start, ndev->irq); 2131df828598SMugunthan V N 2132d9ba8f9eSMugunthan V N if (priv->data.dual_emac) { 2133d9ba8f9eSMugunthan V N ret = cpsw_probe_dual_emac(pdev, priv); 2134d9ba8f9eSMugunthan V N if (ret) { 2135d9ba8f9eSMugunthan V N cpsw_err(priv, probe, "error probe slave 2 emac interface\n"); 2136d9ba8f9eSMugunthan V N goto clean_irq_ret; 2137d9ba8f9eSMugunthan V N } 2138d9ba8f9eSMugunthan V N } 2139d9ba8f9eSMugunthan V N 2140df828598SMugunthan V N return 0; 2141df828598SMugunthan V N 2142df828598SMugunthan V N clean_irq_ret: 2143d1bd9acfSSebastian Siewior for (i = 0; i < priv->num_irqs; i++) 2144d1bd9acfSSebastian Siewior free_irq(priv->irqs_table[i], priv); 2145df828598SMugunthan V N clean_ale_ret: 2146df828598SMugunthan V N cpsw_ale_destroy(priv->ale); 2147df828598SMugunthan V N clean_dma_ret: 2148df828598SMugunthan V N cpdma_chan_destroy(priv->txch); 2149df828598SMugunthan V N cpdma_chan_destroy(priv->rxch); 2150df828598SMugunthan V N cpdma_ctlr_destroy(priv->dma); 21515250c969SRichard Cochran clean_wr_iomap_ret: 21525250c969SRichard Cochran iounmap(priv->wr_regs); 2153a65dd5b2SRichard Cochran clean_cpsw_wr_iores_ret: 2154a65dd5b2SRichard Cochran release_mem_region(priv->cpsw_wr_res->start, 2155a65dd5b2SRichard Cochran resource_size(priv->cpsw_wr_res)); 21565250c969SRichard Cochran clean_iomap_ret: 21575250c969SRichard Cochran iounmap(priv->regs); 2158df828598SMugunthan V N clean_cpsw_iores_ret: 2159df828598SMugunthan V N release_mem_region(priv->cpsw_res->start, 2160df828598SMugunthan V N resource_size(priv->cpsw_res)); 2161df828598SMugunthan V N clean_clk_ret: 2162df828598SMugunthan V N clk_put(priv->clk); 2163f150bd7fSMugunthan V N clean_slave_ret: 2164f150bd7fSMugunthan V N pm_runtime_disable(&pdev->dev); 2165df828598SMugunthan V N kfree(priv->slaves); 2166df828598SMugunthan V N clean_ndev_ret: 2167d1bd9acfSSebastian Siewior kfree(priv->data.slave_data); 2168d1bd9acfSSebastian Siewior free_netdev(priv->ndev); 2169df828598SMugunthan V N return ret; 2170df828598SMugunthan V N } 2171df828598SMugunthan V N 2172663e12e6SBill Pemberton static int cpsw_remove(struct platform_device *pdev) 2173df828598SMugunthan V N { 2174df828598SMugunthan V N struct net_device *ndev = platform_get_drvdata(pdev); 2175df828598SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 2176d1bd9acfSSebastian Siewior int i; 2177df828598SMugunthan V N 2178d1bd9acfSSebastian Siewior if (priv->data.dual_emac) 2179d1bd9acfSSebastian Siewior unregister_netdev(cpsw_get_slave_ndev(priv, 1)); 2180d1bd9acfSSebastian Siewior unregister_netdev(ndev); 2181df828598SMugunthan V N 21829232b16dSMugunthan V N cpts_unregister(priv->cpts); 2183d1bd9acfSSebastian Siewior for (i = 0; i < priv->num_irqs; i++) 2184d1bd9acfSSebastian Siewior free_irq(priv->irqs_table[i], priv); 2185d1bd9acfSSebastian Siewior 2186df828598SMugunthan V N cpsw_ale_destroy(priv->ale); 2187df828598SMugunthan V N cpdma_chan_destroy(priv->txch); 2188df828598SMugunthan V N cpdma_chan_destroy(priv->rxch); 2189df828598SMugunthan V N cpdma_ctlr_destroy(priv->dma); 2190df828598SMugunthan V N iounmap(priv->regs); 2191df828598SMugunthan V N release_mem_region(priv->cpsw_res->start, 2192df828598SMugunthan V N resource_size(priv->cpsw_res)); 21935250c969SRichard Cochran iounmap(priv->wr_regs); 2194a65dd5b2SRichard Cochran release_mem_region(priv->cpsw_wr_res->start, 2195a65dd5b2SRichard Cochran resource_size(priv->cpsw_wr_res)); 2196f150bd7fSMugunthan V N pm_runtime_disable(&pdev->dev); 2197df828598SMugunthan V N clk_put(priv->clk); 2198df828598SMugunthan V N kfree(priv->slaves); 2199d1bd9acfSSebastian Siewior kfree(priv->data.slave_data); 2200d1bd9acfSSebastian Siewior if (priv->data.dual_emac) 2201d1bd9acfSSebastian Siewior free_netdev(cpsw_get_slave_ndev(priv, 1)); 2202df828598SMugunthan V N free_netdev(ndev); 2203df828598SMugunthan V N return 0; 2204df828598SMugunthan V N } 2205df828598SMugunthan V N 2206df828598SMugunthan V N static int cpsw_suspend(struct device *dev) 2207df828598SMugunthan V N { 2208df828598SMugunthan V N struct platform_device *pdev = to_platform_device(dev); 2209df828598SMugunthan V N struct net_device *ndev = platform_get_drvdata(pdev); 2210b90fc27aSMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 2211df828598SMugunthan V N 2212df828598SMugunthan V N if (netif_running(ndev)) 2213df828598SMugunthan V N cpsw_ndo_stop(ndev); 22146d3d76f8SMugunthan V N soft_reset("sliver 0", &priv->slaves[0].sliver->soft_reset); 22156d3d76f8SMugunthan V N soft_reset("sliver 1", &priv->slaves[1].sliver->soft_reset); 2216f150bd7fSMugunthan V N pm_runtime_put_sync(&pdev->dev); 2217f150bd7fSMugunthan V N 2218739683b4SMugunthan V N /* Select sleep pin state */ 2219739683b4SMugunthan V N pinctrl_pm_select_sleep_state(&pdev->dev); 2220739683b4SMugunthan V N 2221df828598SMugunthan V N return 0; 2222df828598SMugunthan V N } 2223df828598SMugunthan V N 2224df828598SMugunthan V N static int cpsw_resume(struct device *dev) 2225df828598SMugunthan V N { 2226df828598SMugunthan V N struct platform_device *pdev = to_platform_device(dev); 2227df828598SMugunthan V N struct net_device *ndev = platform_get_drvdata(pdev); 2228df828598SMugunthan V N 2229f150bd7fSMugunthan V N pm_runtime_get_sync(&pdev->dev); 2230739683b4SMugunthan V N 2231739683b4SMugunthan V N /* Select default pin state */ 2232739683b4SMugunthan V N pinctrl_pm_select_default_state(&pdev->dev); 2233739683b4SMugunthan V N 2234df828598SMugunthan V N if (netif_running(ndev)) 2235df828598SMugunthan V N cpsw_ndo_open(ndev); 2236df828598SMugunthan V N return 0; 2237df828598SMugunthan V N } 2238df828598SMugunthan V N 2239df828598SMugunthan V N static const struct dev_pm_ops cpsw_pm_ops = { 2240df828598SMugunthan V N .suspend = cpsw_suspend, 2241df828598SMugunthan V N .resume = cpsw_resume, 2242df828598SMugunthan V N }; 2243df828598SMugunthan V N 22442eb32b0aSMugunthan V N static const struct of_device_id cpsw_of_mtable[] = { 22452eb32b0aSMugunthan V N { .compatible = "ti,cpsw", }, 22462eb32b0aSMugunthan V N { /* sentinel */ }, 22472eb32b0aSMugunthan V N }; 22484bc21d41SSebastian Siewior MODULE_DEVICE_TABLE(of, cpsw_of_mtable); 22492eb32b0aSMugunthan V N 2250df828598SMugunthan V N static struct platform_driver cpsw_driver = { 2251df828598SMugunthan V N .driver = { 2252df828598SMugunthan V N .name = "cpsw", 2253df828598SMugunthan V N .owner = THIS_MODULE, 2254df828598SMugunthan V N .pm = &cpsw_pm_ops, 22552eb32b0aSMugunthan V N .of_match_table = of_match_ptr(cpsw_of_mtable), 2256df828598SMugunthan V N }, 2257df828598SMugunthan V N .probe = cpsw_probe, 2258663e12e6SBill Pemberton .remove = cpsw_remove, 2259df828598SMugunthan V N }; 2260df828598SMugunthan V N 2261df828598SMugunthan V N static int __init cpsw_init(void) 2262df828598SMugunthan V N { 2263df828598SMugunthan V N return platform_driver_register(&cpsw_driver); 2264df828598SMugunthan V N } 2265df828598SMugunthan V N late_initcall(cpsw_init); 2266df828598SMugunthan V N 2267df828598SMugunthan V N static void __exit cpsw_exit(void) 2268df828598SMugunthan V N { 2269df828598SMugunthan V N platform_driver_unregister(&cpsw_driver); 2270df828598SMugunthan V N } 2271df828598SMugunthan V N module_exit(cpsw_exit); 2272df828598SMugunthan V N 2273df828598SMugunthan V N MODULE_LICENSE("GPL"); 2274df828598SMugunthan V N MODULE_AUTHOR("Cyril Chemparathy <cyril@ti.com>"); 2275df828598SMugunthan V N MODULE_AUTHOR("Mugunthan V N <mugunthanvnm@ti.com>"); 2276df828598SMugunthan V N MODULE_DESCRIPTION("TI CPSW Ethernet driver"); 2277