1df828598SMugunthan V N /* 2df828598SMugunthan V N * Texas Instruments Ethernet Switch Driver 3df828598SMugunthan V N * 4df828598SMugunthan V N * Copyright (C) 2012 Texas Instruments 5df828598SMugunthan V N * 6df828598SMugunthan V N * This program is free software; you can redistribute it and/or 7df828598SMugunthan V N * modify it under the terms of the GNU General Public License as 8df828598SMugunthan V N * published by the Free Software Foundation version 2. 9df828598SMugunthan V N * 10df828598SMugunthan V N * This program is distributed "as is" WITHOUT ANY WARRANTY of any 11df828598SMugunthan V N * kind, whether express or implied; without even the implied warranty 12df828598SMugunthan V N * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13df828598SMugunthan V N * GNU General Public License for more details. 14df828598SMugunthan V N */ 15df828598SMugunthan V N 16df828598SMugunthan V N #include <linux/kernel.h> 17df828598SMugunthan V N #include <linux/io.h> 18df828598SMugunthan V N #include <linux/clk.h> 19df828598SMugunthan V N #include <linux/timer.h> 20df828598SMugunthan V N #include <linux/module.h> 21df828598SMugunthan V N #include <linux/platform_device.h> 22df828598SMugunthan V N #include <linux/irqreturn.h> 23df828598SMugunthan V N #include <linux/interrupt.h> 24df828598SMugunthan V N #include <linux/if_ether.h> 25df828598SMugunthan V N #include <linux/etherdevice.h> 26df828598SMugunthan V N #include <linux/netdevice.h> 272e5b38abSRichard Cochran #include <linux/net_tstamp.h> 28df828598SMugunthan V N #include <linux/phy.h> 29df828598SMugunthan V N #include <linux/workqueue.h> 30df828598SMugunthan V N #include <linux/delay.h> 31f150bd7fSMugunthan V N #include <linux/pm_runtime.h> 321d147ccbSMugunthan V N #include <linux/gpio.h> 332eb32b0aSMugunthan V N #include <linux/of.h> 349e42f715SHeiko Schocher #include <linux/of_mdio.h> 352eb32b0aSMugunthan V N #include <linux/of_net.h> 362eb32b0aSMugunthan V N #include <linux/of_device.h> 373b72c2feSMugunthan V N #include <linux/if_vlan.h> 38df828598SMugunthan V N 39739683b4SMugunthan V N #include <linux/pinctrl/consumer.h> 40df828598SMugunthan V N 41dbe34724SMugunthan V N #include "cpsw.h" 42df828598SMugunthan V N #include "cpsw_ale.h" 432e5b38abSRichard Cochran #include "cpts.h" 44df828598SMugunthan V N #include "davinci_cpdma.h" 45df828598SMugunthan V N 46df828598SMugunthan V N #define CPSW_DEBUG (NETIF_MSG_HW | NETIF_MSG_WOL | \ 47df828598SMugunthan V N NETIF_MSG_DRV | NETIF_MSG_LINK | \ 48df828598SMugunthan V N NETIF_MSG_IFUP | NETIF_MSG_INTR | \ 49df828598SMugunthan V N NETIF_MSG_PROBE | NETIF_MSG_TIMER | \ 50df828598SMugunthan V N NETIF_MSG_IFDOWN | NETIF_MSG_RX_ERR | \ 51df828598SMugunthan V N NETIF_MSG_TX_ERR | NETIF_MSG_TX_DONE | \ 52df828598SMugunthan V N NETIF_MSG_PKTDATA | NETIF_MSG_TX_QUEUED | \ 53df828598SMugunthan V N NETIF_MSG_RX_STATUS) 54df828598SMugunthan V N 55df828598SMugunthan V N #define cpsw_info(priv, type, format, ...) \ 56df828598SMugunthan V N do { \ 57df828598SMugunthan V N if (netif_msg_##type(priv) && net_ratelimit()) \ 58df828598SMugunthan V N dev_info(priv->dev, format, ## __VA_ARGS__); \ 59df828598SMugunthan V N } while (0) 60df828598SMugunthan V N 61df828598SMugunthan V N #define cpsw_err(priv, type, format, ...) \ 62df828598SMugunthan V N do { \ 63df828598SMugunthan V N if (netif_msg_##type(priv) && net_ratelimit()) \ 64df828598SMugunthan V N dev_err(priv->dev, format, ## __VA_ARGS__); \ 65df828598SMugunthan V N } while (0) 66df828598SMugunthan V N 67df828598SMugunthan V N #define cpsw_dbg(priv, type, format, ...) \ 68df828598SMugunthan V N do { \ 69df828598SMugunthan V N if (netif_msg_##type(priv) && net_ratelimit()) \ 70df828598SMugunthan V N dev_dbg(priv->dev, format, ## __VA_ARGS__); \ 71df828598SMugunthan V N } while (0) 72df828598SMugunthan V N 73df828598SMugunthan V N #define cpsw_notice(priv, type, format, ...) \ 74df828598SMugunthan V N do { \ 75df828598SMugunthan V N if (netif_msg_##type(priv) && net_ratelimit()) \ 76df828598SMugunthan V N dev_notice(priv->dev, format, ## __VA_ARGS__); \ 77df828598SMugunthan V N } while (0) 78df828598SMugunthan V N 795c50a856SMugunthan V N #define ALE_ALL_PORTS 0x7 805c50a856SMugunthan V N 81df828598SMugunthan V N #define CPSW_MAJOR_VERSION(reg) (reg >> 8 & 0x7) 82df828598SMugunthan V N #define CPSW_MINOR_VERSION(reg) (reg & 0xff) 83df828598SMugunthan V N #define CPSW_RTL_VERSION(reg) ((reg >> 11) & 0x1f) 84df828598SMugunthan V N 85e90cfac6SRichard Cochran #define CPSW_VERSION_1 0x19010a 86e90cfac6SRichard Cochran #define CPSW_VERSION_2 0x19010c 87c193f365SMugunthan V N #define CPSW_VERSION_3 0x19010f 88926489beSMugunthan V N #define CPSW_VERSION_4 0x190112 89549985eeSRichard Cochran 90549985eeSRichard Cochran #define HOST_PORT_NUM 0 91549985eeSRichard Cochran #define SLIVER_SIZE 0x40 92549985eeSRichard Cochran 93549985eeSRichard Cochran #define CPSW1_HOST_PORT_OFFSET 0x028 94549985eeSRichard Cochran #define CPSW1_SLAVE_OFFSET 0x050 95549985eeSRichard Cochran #define CPSW1_SLAVE_SIZE 0x040 96549985eeSRichard Cochran #define CPSW1_CPDMA_OFFSET 0x100 97549985eeSRichard Cochran #define CPSW1_STATERAM_OFFSET 0x200 98d9718546SMugunthan V N #define CPSW1_HW_STATS 0x400 99549985eeSRichard Cochran #define CPSW1_CPTS_OFFSET 0x500 100549985eeSRichard Cochran #define CPSW1_ALE_OFFSET 0x600 101549985eeSRichard Cochran #define CPSW1_SLIVER_OFFSET 0x700 102549985eeSRichard Cochran 103549985eeSRichard Cochran #define CPSW2_HOST_PORT_OFFSET 0x108 104549985eeSRichard Cochran #define CPSW2_SLAVE_OFFSET 0x200 105549985eeSRichard Cochran #define CPSW2_SLAVE_SIZE 0x100 106549985eeSRichard Cochran #define CPSW2_CPDMA_OFFSET 0x800 107d9718546SMugunthan V N #define CPSW2_HW_STATS 0x900 108549985eeSRichard Cochran #define CPSW2_STATERAM_OFFSET 0xa00 109549985eeSRichard Cochran #define CPSW2_CPTS_OFFSET 0xc00 110549985eeSRichard Cochran #define CPSW2_ALE_OFFSET 0xd00 111549985eeSRichard Cochran #define CPSW2_SLIVER_OFFSET 0xd80 112549985eeSRichard Cochran #define CPSW2_BD_OFFSET 0x2000 113549985eeSRichard Cochran 114df828598SMugunthan V N #define CPDMA_RXTHRESH 0x0c0 115df828598SMugunthan V N #define CPDMA_RXFREE 0x0e0 116df828598SMugunthan V N #define CPDMA_TXHDP 0x00 117df828598SMugunthan V N #define CPDMA_RXHDP 0x20 118df828598SMugunthan V N #define CPDMA_TXCP 0x40 119df828598SMugunthan V N #define CPDMA_RXCP 0x60 120df828598SMugunthan V N 121df828598SMugunthan V N #define CPSW_POLL_WEIGHT 64 122df828598SMugunthan V N #define CPSW_MIN_PACKET_SIZE 60 123df828598SMugunthan V N #define CPSW_MAX_PACKET_SIZE (1500 + 14 + 4 + 4) 124df828598SMugunthan V N 125df828598SMugunthan V N #define RX_PRIORITY_MAPPING 0x76543210 126df828598SMugunthan V N #define TX_PRIORITY_MAPPING 0x33221100 127e05107e6SIvan Khoronzhuk #define CPDMA_TX_PRIORITY_MAP 0x01234567 128df828598SMugunthan V N 1293b72c2feSMugunthan V N #define CPSW_VLAN_AWARE BIT(1) 1303b72c2feSMugunthan V N #define CPSW_ALE_VLAN_AWARE 1 1313b72c2feSMugunthan V N 13235717d8dSJohn Ogness #define CPSW_FIFO_NORMAL_MODE (0 << 16) 13335717d8dSJohn Ogness #define CPSW_FIFO_DUAL_MAC_MODE (1 << 16) 13435717d8dSJohn Ogness #define CPSW_FIFO_RATE_LIMIT_MODE (2 << 16) 135d9ba8f9eSMugunthan V N 136ff5b8ef2SMugunthan V N #define CPSW_INTPACEEN (0x3f << 16) 137ff5b8ef2SMugunthan V N #define CPSW_INTPRESCALE_MASK (0x7FF << 0) 138ff5b8ef2SMugunthan V N #define CPSW_CMINTMAX_CNT 63 139ff5b8ef2SMugunthan V N #define CPSW_CMINTMIN_CNT 2 140ff5b8ef2SMugunthan V N #define CPSW_CMINTMAX_INTVL (1000 / CPSW_CMINTMIN_CNT) 141ff5b8ef2SMugunthan V N #define CPSW_CMINTMIN_INTVL ((1000 / CPSW_CMINTMAX_CNT) + 1) 142ff5b8ef2SMugunthan V N 143606f3993SIvan Khoronzhuk #define cpsw_slave_index(cpsw, priv) \ 144606f3993SIvan Khoronzhuk ((cpsw->data.dual_emac) ? priv->emac_port : \ 145606f3993SIvan Khoronzhuk cpsw->data.active_slave) 146e38b5a3dSIvan Khoronzhuk #define IRQ_NUM 2 147e05107e6SIvan Khoronzhuk #define CPSW_MAX_QUEUES 8 148d3bb9c58SMugunthan V N 149df828598SMugunthan V N static int debug_level; 150df828598SMugunthan V N module_param(debug_level, int, 0); 151df828598SMugunthan V N MODULE_PARM_DESC(debug_level, "cpsw debug level (NETIF_MSG bits)"); 152df828598SMugunthan V N 153df828598SMugunthan V N static int ale_ageout = 10; 154df828598SMugunthan V N module_param(ale_ageout, int, 0); 155df828598SMugunthan V N MODULE_PARM_DESC(ale_ageout, "cpsw ale ageout interval (seconds)"); 156df828598SMugunthan V N 157df828598SMugunthan V N static int rx_packet_max = CPSW_MAX_PACKET_SIZE; 158df828598SMugunthan V N module_param(rx_packet_max, int, 0); 159df828598SMugunthan V N MODULE_PARM_DESC(rx_packet_max, "maximum receive packet size (bytes)"); 160df828598SMugunthan V N 161996a5c27SRichard Cochran struct cpsw_wr_regs { 162df828598SMugunthan V N u32 id_ver; 163df828598SMugunthan V N u32 soft_reset; 164df828598SMugunthan V N u32 control; 165df828598SMugunthan V N u32 int_control; 166df828598SMugunthan V N u32 rx_thresh_en; 167df828598SMugunthan V N u32 rx_en; 168df828598SMugunthan V N u32 tx_en; 169df828598SMugunthan V N u32 misc_en; 170ff5b8ef2SMugunthan V N u32 mem_allign1[8]; 171ff5b8ef2SMugunthan V N u32 rx_thresh_stat; 172ff5b8ef2SMugunthan V N u32 rx_stat; 173ff5b8ef2SMugunthan V N u32 tx_stat; 174ff5b8ef2SMugunthan V N u32 misc_stat; 175ff5b8ef2SMugunthan V N u32 mem_allign2[8]; 176ff5b8ef2SMugunthan V N u32 rx_imax; 177ff5b8ef2SMugunthan V N u32 tx_imax; 178ff5b8ef2SMugunthan V N 179df828598SMugunthan V N }; 180df828598SMugunthan V N 181996a5c27SRichard Cochran struct cpsw_ss_regs { 182df828598SMugunthan V N u32 id_ver; 183df828598SMugunthan V N u32 control; 184df828598SMugunthan V N u32 soft_reset; 185df828598SMugunthan V N u32 stat_port_en; 186df828598SMugunthan V N u32 ptype; 187bd357af2SRichard Cochran u32 soft_idle; 188bd357af2SRichard Cochran u32 thru_rate; 189bd357af2SRichard Cochran u32 gap_thresh; 190bd357af2SRichard Cochran u32 tx_start_wds; 191bd357af2SRichard Cochran u32 flow_control; 192bd357af2SRichard Cochran u32 vlan_ltype; 193bd357af2SRichard Cochran u32 ts_ltype; 194bd357af2SRichard Cochran u32 dlr_ltype; 195df828598SMugunthan V N }; 196df828598SMugunthan V N 1979750a3adSRichard Cochran /* CPSW_PORT_V1 */ 1989750a3adSRichard Cochran #define CPSW1_MAX_BLKS 0x00 /* Maximum FIFO Blocks */ 1999750a3adSRichard Cochran #define CPSW1_BLK_CNT 0x04 /* FIFO Block Usage Count (Read Only) */ 2009750a3adSRichard Cochran #define CPSW1_TX_IN_CTL 0x08 /* Transmit FIFO Control */ 2019750a3adSRichard Cochran #define CPSW1_PORT_VLAN 0x0c /* VLAN Register */ 2029750a3adSRichard Cochran #define CPSW1_TX_PRI_MAP 0x10 /* Tx Header Priority to Switch Pri Mapping */ 2039750a3adSRichard Cochran #define CPSW1_TS_CTL 0x14 /* Time Sync Control */ 2049750a3adSRichard Cochran #define CPSW1_TS_SEQ_LTYPE 0x18 /* Time Sync Sequence ID Offset and Msg Type */ 2059750a3adSRichard Cochran #define CPSW1_TS_VLAN 0x1c /* Time Sync VLAN1 and VLAN2 */ 2069750a3adSRichard Cochran 2079750a3adSRichard Cochran /* CPSW_PORT_V2 */ 2089750a3adSRichard Cochran #define CPSW2_CONTROL 0x00 /* Control Register */ 2099750a3adSRichard Cochran #define CPSW2_MAX_BLKS 0x08 /* Maximum FIFO Blocks */ 2109750a3adSRichard Cochran #define CPSW2_BLK_CNT 0x0c /* FIFO Block Usage Count (Read Only) */ 2119750a3adSRichard Cochran #define CPSW2_TX_IN_CTL 0x10 /* Transmit FIFO Control */ 2129750a3adSRichard Cochran #define CPSW2_PORT_VLAN 0x14 /* VLAN Register */ 2139750a3adSRichard Cochran #define CPSW2_TX_PRI_MAP 0x18 /* Tx Header Priority to Switch Pri Mapping */ 2149750a3adSRichard Cochran #define CPSW2_TS_SEQ_MTYPE 0x1c /* Time Sync Sequence ID Offset and Msg Type */ 2159750a3adSRichard Cochran 2169750a3adSRichard Cochran /* CPSW_PORT_V1 and V2 */ 2179750a3adSRichard Cochran #define SA_LO 0x20 /* CPGMAC_SL Source Address Low */ 2189750a3adSRichard Cochran #define SA_HI 0x24 /* CPGMAC_SL Source Address High */ 2199750a3adSRichard Cochran #define SEND_PERCENT 0x28 /* Transmit Queue Send Percentages */ 2209750a3adSRichard Cochran 2219750a3adSRichard Cochran /* CPSW_PORT_V2 only */ 2229750a3adSRichard Cochran #define RX_DSCP_PRI_MAP0 0x30 /* Rx DSCP Priority to Rx Packet Mapping */ 2239750a3adSRichard Cochran #define RX_DSCP_PRI_MAP1 0x34 /* Rx DSCP Priority to Rx Packet Mapping */ 2249750a3adSRichard Cochran #define RX_DSCP_PRI_MAP2 0x38 /* Rx DSCP Priority to Rx Packet Mapping */ 2259750a3adSRichard Cochran #define RX_DSCP_PRI_MAP3 0x3c /* Rx DSCP Priority to Rx Packet Mapping */ 2269750a3adSRichard Cochran #define RX_DSCP_PRI_MAP4 0x40 /* Rx DSCP Priority to Rx Packet Mapping */ 2279750a3adSRichard Cochran #define RX_DSCP_PRI_MAP5 0x44 /* Rx DSCP Priority to Rx Packet Mapping */ 2289750a3adSRichard Cochran #define RX_DSCP_PRI_MAP6 0x48 /* Rx DSCP Priority to Rx Packet Mapping */ 2299750a3adSRichard Cochran #define RX_DSCP_PRI_MAP7 0x4c /* Rx DSCP Priority to Rx Packet Mapping */ 2309750a3adSRichard Cochran 2319750a3adSRichard Cochran /* Bit definitions for the CPSW2_CONTROL register */ 2329750a3adSRichard Cochran #define PASS_PRI_TAGGED (1<<24) /* Pass Priority Tagged */ 2339750a3adSRichard Cochran #define VLAN_LTYPE2_EN (1<<21) /* VLAN LTYPE 2 enable */ 2349750a3adSRichard Cochran #define VLAN_LTYPE1_EN (1<<20) /* VLAN LTYPE 1 enable */ 2359750a3adSRichard Cochran #define DSCP_PRI_EN (1<<16) /* DSCP Priority Enable */ 2369750a3adSRichard Cochran #define TS_320 (1<<14) /* Time Sync Dest Port 320 enable */ 2379750a3adSRichard Cochran #define TS_319 (1<<13) /* Time Sync Dest Port 319 enable */ 2389750a3adSRichard Cochran #define TS_132 (1<<12) /* Time Sync Dest IP Addr 132 enable */ 2399750a3adSRichard Cochran #define TS_131 (1<<11) /* Time Sync Dest IP Addr 131 enable */ 2409750a3adSRichard Cochran #define TS_130 (1<<10) /* Time Sync Dest IP Addr 130 enable */ 2419750a3adSRichard Cochran #define TS_129 (1<<9) /* Time Sync Dest IP Addr 129 enable */ 24209c55372SGeorge Cherian #define TS_TTL_NONZERO (1<<8) /* Time Sync Time To Live Non-zero enable */ 24309c55372SGeorge Cherian #define TS_ANNEX_F_EN (1<<6) /* Time Sync Annex F enable */ 2449750a3adSRichard Cochran #define TS_ANNEX_D_EN (1<<4) /* Time Sync Annex D enable */ 2459750a3adSRichard Cochran #define TS_LTYPE2_EN (1<<3) /* Time Sync LTYPE 2 enable */ 2469750a3adSRichard Cochran #define TS_LTYPE1_EN (1<<2) /* Time Sync LTYPE 1 enable */ 2479750a3adSRichard Cochran #define TS_TX_EN (1<<1) /* Time Sync Transmit Enable */ 2489750a3adSRichard Cochran #define TS_RX_EN (1<<0) /* Time Sync Receive Enable */ 2499750a3adSRichard Cochran 25009c55372SGeorge Cherian #define CTRL_V2_TS_BITS \ 25109c55372SGeorge Cherian (TS_320 | TS_319 | TS_132 | TS_131 | TS_130 | TS_129 |\ 25209c55372SGeorge Cherian TS_TTL_NONZERO | TS_ANNEX_D_EN | TS_LTYPE1_EN) 2539750a3adSRichard Cochran 25409c55372SGeorge Cherian #define CTRL_V2_ALL_TS_MASK (CTRL_V2_TS_BITS | TS_TX_EN | TS_RX_EN) 25509c55372SGeorge Cherian #define CTRL_V2_TX_TS_BITS (CTRL_V2_TS_BITS | TS_TX_EN) 25609c55372SGeorge Cherian #define CTRL_V2_RX_TS_BITS (CTRL_V2_TS_BITS | TS_RX_EN) 25709c55372SGeorge Cherian 25809c55372SGeorge Cherian 25909c55372SGeorge Cherian #define CTRL_V3_TS_BITS \ 26009c55372SGeorge Cherian (TS_320 | TS_319 | TS_132 | TS_131 | TS_130 | TS_129 |\ 26109c55372SGeorge Cherian TS_TTL_NONZERO | TS_ANNEX_F_EN | TS_ANNEX_D_EN |\ 26209c55372SGeorge Cherian TS_LTYPE1_EN) 26309c55372SGeorge Cherian 26409c55372SGeorge Cherian #define CTRL_V3_ALL_TS_MASK (CTRL_V3_TS_BITS | TS_TX_EN | TS_RX_EN) 26509c55372SGeorge Cherian #define CTRL_V3_TX_TS_BITS (CTRL_V3_TS_BITS | TS_TX_EN) 26609c55372SGeorge Cherian #define CTRL_V3_RX_TS_BITS (CTRL_V3_TS_BITS | TS_RX_EN) 2679750a3adSRichard Cochran 2689750a3adSRichard Cochran /* Bit definitions for the CPSW2_TS_SEQ_MTYPE register */ 2699750a3adSRichard Cochran #define TS_SEQ_ID_OFFSET_SHIFT (16) /* Time Sync Sequence ID Offset */ 2709750a3adSRichard Cochran #define TS_SEQ_ID_OFFSET_MASK (0x3f) 2719750a3adSRichard Cochran #define TS_MSG_TYPE_EN_SHIFT (0) /* Time Sync Message Type Enable */ 2729750a3adSRichard Cochran #define TS_MSG_TYPE_EN_MASK (0xffff) 2739750a3adSRichard Cochran 2749750a3adSRichard Cochran /* The PTP event messages - Sync, Delay_Req, Pdelay_Req, and Pdelay_Resp. */ 2759750a3adSRichard Cochran #define EVENT_MSG_BITS ((1<<0) | (1<<1) | (1<<2) | (1<<3)) 276df828598SMugunthan V N 2772e5b38abSRichard Cochran /* Bit definitions for the CPSW1_TS_CTL register */ 2782e5b38abSRichard Cochran #define CPSW_V1_TS_RX_EN BIT(0) 2792e5b38abSRichard Cochran #define CPSW_V1_TS_TX_EN BIT(4) 2802e5b38abSRichard Cochran #define CPSW_V1_MSG_TYPE_OFS 16 2812e5b38abSRichard Cochran 2822e5b38abSRichard Cochran /* Bit definitions for the CPSW1_TS_SEQ_LTYPE register */ 2832e5b38abSRichard Cochran #define CPSW_V1_SEQ_ID_OFS_SHIFT 16 2842e5b38abSRichard Cochran 285df828598SMugunthan V N struct cpsw_host_regs { 286df828598SMugunthan V N u32 max_blks; 287df828598SMugunthan V N u32 blk_cnt; 288d9ba8f9eSMugunthan V N u32 tx_in_ctl; 289df828598SMugunthan V N u32 port_vlan; 290df828598SMugunthan V N u32 tx_pri_map; 291df828598SMugunthan V N u32 cpdma_tx_pri_map; 292df828598SMugunthan V N u32 cpdma_rx_chan_map; 293df828598SMugunthan V N }; 294df828598SMugunthan V N 295df828598SMugunthan V N struct cpsw_sliver_regs { 296df828598SMugunthan V N u32 id_ver; 297df828598SMugunthan V N u32 mac_control; 298df828598SMugunthan V N u32 mac_status; 299df828598SMugunthan V N u32 soft_reset; 300df828598SMugunthan V N u32 rx_maxlen; 301df828598SMugunthan V N u32 __reserved_0; 302df828598SMugunthan V N u32 rx_pause; 303df828598SMugunthan V N u32 tx_pause; 304df828598SMugunthan V N u32 __reserved_1; 305df828598SMugunthan V N u32 rx_pri_map; 306df828598SMugunthan V N }; 307df828598SMugunthan V N 308d9718546SMugunthan V N struct cpsw_hw_stats { 309d9718546SMugunthan V N u32 rxgoodframes; 310d9718546SMugunthan V N u32 rxbroadcastframes; 311d9718546SMugunthan V N u32 rxmulticastframes; 312d9718546SMugunthan V N u32 rxpauseframes; 313d9718546SMugunthan V N u32 rxcrcerrors; 314d9718546SMugunthan V N u32 rxaligncodeerrors; 315d9718546SMugunthan V N u32 rxoversizedframes; 316d9718546SMugunthan V N u32 rxjabberframes; 317d9718546SMugunthan V N u32 rxundersizedframes; 318d9718546SMugunthan V N u32 rxfragments; 319d9718546SMugunthan V N u32 __pad_0[2]; 320d9718546SMugunthan V N u32 rxoctets; 321d9718546SMugunthan V N u32 txgoodframes; 322d9718546SMugunthan V N u32 txbroadcastframes; 323d9718546SMugunthan V N u32 txmulticastframes; 324d9718546SMugunthan V N u32 txpauseframes; 325d9718546SMugunthan V N u32 txdeferredframes; 326d9718546SMugunthan V N u32 txcollisionframes; 327d9718546SMugunthan V N u32 txsinglecollframes; 328d9718546SMugunthan V N u32 txmultcollframes; 329d9718546SMugunthan V N u32 txexcessivecollisions; 330d9718546SMugunthan V N u32 txlatecollisions; 331d9718546SMugunthan V N u32 txunderrun; 332d9718546SMugunthan V N u32 txcarriersenseerrors; 333d9718546SMugunthan V N u32 txoctets; 334d9718546SMugunthan V N u32 octetframes64; 335d9718546SMugunthan V N u32 octetframes65t127; 336d9718546SMugunthan V N u32 octetframes128t255; 337d9718546SMugunthan V N u32 octetframes256t511; 338d9718546SMugunthan V N u32 octetframes512t1023; 339d9718546SMugunthan V N u32 octetframes1024tup; 340d9718546SMugunthan V N u32 netoctets; 341d9718546SMugunthan V N u32 rxsofoverruns; 342d9718546SMugunthan V N u32 rxmofoverruns; 343d9718546SMugunthan V N u32 rxdmaoverruns; 344d9718546SMugunthan V N }; 345d9718546SMugunthan V N 346df828598SMugunthan V N struct cpsw_slave { 3479750a3adSRichard Cochran void __iomem *regs; 348df828598SMugunthan V N struct cpsw_sliver_regs __iomem *sliver; 349df828598SMugunthan V N int slave_num; 350df828598SMugunthan V N u32 mac_control; 351df828598SMugunthan V N struct cpsw_slave_data *data; 352df828598SMugunthan V N struct phy_device *phy; 353d9ba8f9eSMugunthan V N struct net_device *ndev; 354d9ba8f9eSMugunthan V N u32 port_vlan; 355d9ba8f9eSMugunthan V N u32 open_stat; 356df828598SMugunthan V N }; 357df828598SMugunthan V N 3589750a3adSRichard Cochran static inline u32 slave_read(struct cpsw_slave *slave, u32 offset) 3599750a3adSRichard Cochran { 3609750a3adSRichard Cochran return __raw_readl(slave->regs + offset); 3619750a3adSRichard Cochran } 3629750a3adSRichard Cochran 3639750a3adSRichard Cochran static inline void slave_write(struct cpsw_slave *slave, u32 val, u32 offset) 3649750a3adSRichard Cochran { 3659750a3adSRichard Cochran __raw_writel(val, slave->regs + offset); 3669750a3adSRichard Cochran } 3679750a3adSRichard Cochran 368649a1688SIvan Khoronzhuk struct cpsw_common { 36956e31bd8SIvan Khoronzhuk struct device *dev; 370606f3993SIvan Khoronzhuk struct cpsw_platform_data data; 371dbc4ec52SIvan Khoronzhuk struct napi_struct napi_rx; 372dbc4ec52SIvan Khoronzhuk struct napi_struct napi_tx; 3735d8d0d4dSIvan Khoronzhuk struct cpsw_ss_regs __iomem *regs; 3745d8d0d4dSIvan Khoronzhuk struct cpsw_wr_regs __iomem *wr_regs; 3755d8d0d4dSIvan Khoronzhuk u8 __iomem *hw_stats; 3765d8d0d4dSIvan Khoronzhuk struct cpsw_host_regs __iomem *host_port_regs; 3772a05a622SIvan Khoronzhuk u32 version; 3782a05a622SIvan Khoronzhuk u32 coal_intvl; 3792a05a622SIvan Khoronzhuk u32 bus_freq_mhz; 3802a05a622SIvan Khoronzhuk int rx_packet_max; 381606f3993SIvan Khoronzhuk struct cpsw_slave *slaves; 3822c836bd9SIvan Khoronzhuk struct cpdma_ctlr *dma; 383e05107e6SIvan Khoronzhuk struct cpdma_chan *txch[CPSW_MAX_QUEUES]; 384e05107e6SIvan Khoronzhuk struct cpdma_chan *rxch[CPSW_MAX_QUEUES]; 3852a05a622SIvan Khoronzhuk struct cpsw_ale *ale; 386e38b5a3dSIvan Khoronzhuk bool quirk_irq; 387e38b5a3dSIvan Khoronzhuk bool rx_irq_disabled; 388e38b5a3dSIvan Khoronzhuk bool tx_irq_disabled; 389e38b5a3dSIvan Khoronzhuk u32 irqs_table[IRQ_NUM]; 3902a05a622SIvan Khoronzhuk struct cpts *cpts; 391e05107e6SIvan Khoronzhuk int rx_ch_num, tx_ch_num; 392649a1688SIvan Khoronzhuk }; 393649a1688SIvan Khoronzhuk 394649a1688SIvan Khoronzhuk struct cpsw_priv { 395df828598SMugunthan V N struct net_device *ndev; 396df828598SMugunthan V N struct device *dev; 397df828598SMugunthan V N u32 msg_enable; 398df828598SMugunthan V N u8 mac_addr[ETH_ALEN]; 3991923d6e4SMugunthan V N bool rx_pause; 4001923d6e4SMugunthan V N bool tx_pause; 401d9ba8f9eSMugunthan V N u32 emac_port; 402649a1688SIvan Khoronzhuk struct cpsw_common *cpsw; 403df828598SMugunthan V N }; 404df828598SMugunthan V N 405d9718546SMugunthan V N struct cpsw_stats { 406d9718546SMugunthan V N char stat_string[ETH_GSTRING_LEN]; 407d9718546SMugunthan V N int type; 408d9718546SMugunthan V N int sizeof_stat; 409d9718546SMugunthan V N int stat_offset; 410d9718546SMugunthan V N }; 411d9718546SMugunthan V N 412d9718546SMugunthan V N enum { 413d9718546SMugunthan V N CPSW_STATS, 414d9718546SMugunthan V N CPDMA_RX_STATS, 415d9718546SMugunthan V N CPDMA_TX_STATS, 416d9718546SMugunthan V N }; 417d9718546SMugunthan V N 418d9718546SMugunthan V N #define CPSW_STAT(m) CPSW_STATS, \ 419d9718546SMugunthan V N sizeof(((struct cpsw_hw_stats *)0)->m), \ 420d9718546SMugunthan V N offsetof(struct cpsw_hw_stats, m) 421d9718546SMugunthan V N #define CPDMA_RX_STAT(m) CPDMA_RX_STATS, \ 422d9718546SMugunthan V N sizeof(((struct cpdma_chan_stats *)0)->m), \ 423d9718546SMugunthan V N offsetof(struct cpdma_chan_stats, m) 424d9718546SMugunthan V N #define CPDMA_TX_STAT(m) CPDMA_TX_STATS, \ 425d9718546SMugunthan V N sizeof(((struct cpdma_chan_stats *)0)->m), \ 426d9718546SMugunthan V N offsetof(struct cpdma_chan_stats, m) 427d9718546SMugunthan V N 428d9718546SMugunthan V N static const struct cpsw_stats cpsw_gstrings_stats[] = { 429d9718546SMugunthan V N { "Good Rx Frames", CPSW_STAT(rxgoodframes) }, 430d9718546SMugunthan V N { "Broadcast Rx Frames", CPSW_STAT(rxbroadcastframes) }, 431d9718546SMugunthan V N { "Multicast Rx Frames", CPSW_STAT(rxmulticastframes) }, 432d9718546SMugunthan V N { "Pause Rx Frames", CPSW_STAT(rxpauseframes) }, 433d9718546SMugunthan V N { "Rx CRC Errors", CPSW_STAT(rxcrcerrors) }, 434d9718546SMugunthan V N { "Rx Align/Code Errors", CPSW_STAT(rxaligncodeerrors) }, 435d9718546SMugunthan V N { "Oversize Rx Frames", CPSW_STAT(rxoversizedframes) }, 436d9718546SMugunthan V N { "Rx Jabbers", CPSW_STAT(rxjabberframes) }, 437d9718546SMugunthan V N { "Undersize (Short) Rx Frames", CPSW_STAT(rxundersizedframes) }, 438d9718546SMugunthan V N { "Rx Fragments", CPSW_STAT(rxfragments) }, 439d9718546SMugunthan V N { "Rx Octets", CPSW_STAT(rxoctets) }, 440d9718546SMugunthan V N { "Good Tx Frames", CPSW_STAT(txgoodframes) }, 441d9718546SMugunthan V N { "Broadcast Tx Frames", CPSW_STAT(txbroadcastframes) }, 442d9718546SMugunthan V N { "Multicast Tx Frames", CPSW_STAT(txmulticastframes) }, 443d9718546SMugunthan V N { "Pause Tx Frames", CPSW_STAT(txpauseframes) }, 444d9718546SMugunthan V N { "Deferred Tx Frames", CPSW_STAT(txdeferredframes) }, 445d9718546SMugunthan V N { "Collisions", CPSW_STAT(txcollisionframes) }, 446d9718546SMugunthan V N { "Single Collision Tx Frames", CPSW_STAT(txsinglecollframes) }, 447d9718546SMugunthan V N { "Multiple Collision Tx Frames", CPSW_STAT(txmultcollframes) }, 448d9718546SMugunthan V N { "Excessive Collisions", CPSW_STAT(txexcessivecollisions) }, 449d9718546SMugunthan V N { "Late Collisions", CPSW_STAT(txlatecollisions) }, 450d9718546SMugunthan V N { "Tx Underrun", CPSW_STAT(txunderrun) }, 451d9718546SMugunthan V N { "Carrier Sense Errors", CPSW_STAT(txcarriersenseerrors) }, 452d9718546SMugunthan V N { "Tx Octets", CPSW_STAT(txoctets) }, 453d9718546SMugunthan V N { "Rx + Tx 64 Octet Frames", CPSW_STAT(octetframes64) }, 454d9718546SMugunthan V N { "Rx + Tx 65-127 Octet Frames", CPSW_STAT(octetframes65t127) }, 455d9718546SMugunthan V N { "Rx + Tx 128-255 Octet Frames", CPSW_STAT(octetframes128t255) }, 456d9718546SMugunthan V N { "Rx + Tx 256-511 Octet Frames", CPSW_STAT(octetframes256t511) }, 457d9718546SMugunthan V N { "Rx + Tx 512-1023 Octet Frames", CPSW_STAT(octetframes512t1023) }, 458d9718546SMugunthan V N { "Rx + Tx 1024-Up Octet Frames", CPSW_STAT(octetframes1024tup) }, 459d9718546SMugunthan V N { "Net Octets", CPSW_STAT(netoctets) }, 460d9718546SMugunthan V N { "Rx Start of Frame Overruns", CPSW_STAT(rxsofoverruns) }, 461d9718546SMugunthan V N { "Rx Middle of Frame Overruns", CPSW_STAT(rxmofoverruns) }, 462d9718546SMugunthan V N { "Rx DMA Overruns", CPSW_STAT(rxdmaoverruns) }, 463d9718546SMugunthan V N }; 464d9718546SMugunthan V N 465e05107e6SIvan Khoronzhuk static const struct cpsw_stats cpsw_gstrings_ch_stats[] = { 466e05107e6SIvan Khoronzhuk { "head_enqueue", CPDMA_RX_STAT(head_enqueue) }, 467e05107e6SIvan Khoronzhuk { "tail_enqueue", CPDMA_RX_STAT(tail_enqueue) }, 468e05107e6SIvan Khoronzhuk { "pad_enqueue", CPDMA_RX_STAT(pad_enqueue) }, 469e05107e6SIvan Khoronzhuk { "misqueued", CPDMA_RX_STAT(misqueued) }, 470e05107e6SIvan Khoronzhuk { "desc_alloc_fail", CPDMA_RX_STAT(desc_alloc_fail) }, 471e05107e6SIvan Khoronzhuk { "pad_alloc_fail", CPDMA_RX_STAT(pad_alloc_fail) }, 472e05107e6SIvan Khoronzhuk { "runt_receive_buf", CPDMA_RX_STAT(runt_receive_buff) }, 473e05107e6SIvan Khoronzhuk { "runt_transmit_buf", CPDMA_RX_STAT(runt_transmit_buff) }, 474e05107e6SIvan Khoronzhuk { "empty_dequeue", CPDMA_RX_STAT(empty_dequeue) }, 475e05107e6SIvan Khoronzhuk { "busy_dequeue", CPDMA_RX_STAT(busy_dequeue) }, 476e05107e6SIvan Khoronzhuk { "good_dequeue", CPDMA_RX_STAT(good_dequeue) }, 477e05107e6SIvan Khoronzhuk { "requeue", CPDMA_RX_STAT(requeue) }, 478e05107e6SIvan Khoronzhuk { "teardown_dequeue", CPDMA_RX_STAT(teardown_dequeue) }, 479e05107e6SIvan Khoronzhuk }; 480e05107e6SIvan Khoronzhuk 481e05107e6SIvan Khoronzhuk #define CPSW_STATS_COMMON_LEN ARRAY_SIZE(cpsw_gstrings_stats) 482e05107e6SIvan Khoronzhuk #define CPSW_STATS_CH_LEN ARRAY_SIZE(cpsw_gstrings_ch_stats) 483d9718546SMugunthan V N 484649a1688SIvan Khoronzhuk #define ndev_to_cpsw(ndev) (((struct cpsw_priv *)netdev_priv(ndev))->cpsw) 485dbc4ec52SIvan Khoronzhuk #define napi_to_cpsw(napi) container_of(napi, struct cpsw_common, napi) 486df828598SMugunthan V N #define for_each_slave(priv, func, arg...) \ 487df828598SMugunthan V N do { \ 4886e6ceaedSSebastian Siewior struct cpsw_slave *slave; \ 489606f3993SIvan Khoronzhuk struct cpsw_common *cpsw = (priv)->cpsw; \ 4906e6ceaedSSebastian Siewior int n; \ 491606f3993SIvan Khoronzhuk if (cpsw->data.dual_emac) \ 492606f3993SIvan Khoronzhuk (func)((cpsw)->slaves + priv->emac_port, ##arg);\ 493d9ba8f9eSMugunthan V N else \ 494606f3993SIvan Khoronzhuk for (n = cpsw->data.slaves, \ 495606f3993SIvan Khoronzhuk slave = cpsw->slaves; \ 4966e6ceaedSSebastian Siewior n; n--) \ 4976e6ceaedSSebastian Siewior (func)(slave++, ##arg); \ 498df828598SMugunthan V N } while (0) 499d9ba8f9eSMugunthan V N 5002a05a622SIvan Khoronzhuk #define cpsw_dual_emac_src_port_detect(cpsw, status, ndev, skb) \ 501d9ba8f9eSMugunthan V N do { \ 502606f3993SIvan Khoronzhuk if (!cpsw->data.dual_emac) \ 503d9ba8f9eSMugunthan V N break; \ 504d9ba8f9eSMugunthan V N if (CPDMA_RX_SOURCE_PORT(status) == 1) { \ 505606f3993SIvan Khoronzhuk ndev = cpsw->slaves[0].ndev; \ 506d9ba8f9eSMugunthan V N skb->dev = ndev; \ 507d9ba8f9eSMugunthan V N } else if (CPDMA_RX_SOURCE_PORT(status) == 2) { \ 508606f3993SIvan Khoronzhuk ndev = cpsw->slaves[1].ndev; \ 509d9ba8f9eSMugunthan V N skb->dev = ndev; \ 510d9ba8f9eSMugunthan V N } \ 511d9ba8f9eSMugunthan V N } while (0) 512606f3993SIvan Khoronzhuk #define cpsw_add_mcast(cpsw, priv, addr) \ 513d9ba8f9eSMugunthan V N do { \ 514606f3993SIvan Khoronzhuk if (cpsw->data.dual_emac) { \ 515606f3993SIvan Khoronzhuk struct cpsw_slave *slave = cpsw->slaves + \ 516d9ba8f9eSMugunthan V N priv->emac_port; \ 5176f1f5836SIvan Khoronzhuk int slave_port = cpsw_get_slave_port( \ 518d9ba8f9eSMugunthan V N slave->slave_num); \ 5192a05a622SIvan Khoronzhuk cpsw_ale_add_mcast(cpsw->ale, addr, \ 52071a2cbb7SGrygorii Strashko 1 << slave_port | ALE_PORT_HOST, \ 521d9ba8f9eSMugunthan V N ALE_VLAN, slave->port_vlan, 0); \ 522d9ba8f9eSMugunthan V N } else { \ 5232a05a622SIvan Khoronzhuk cpsw_ale_add_mcast(cpsw->ale, addr, \ 52461f1cef9SGrygorii Strashko ALE_ALL_PORTS, \ 525d9ba8f9eSMugunthan V N 0, 0, 0); \ 526d9ba8f9eSMugunthan V N } \ 527d9ba8f9eSMugunthan V N } while (0) 528d9ba8f9eSMugunthan V N 5296f1f5836SIvan Khoronzhuk static inline int cpsw_get_slave_port(u32 slave_num) 530d9ba8f9eSMugunthan V N { 531d9ba8f9eSMugunthan V N return slave_num + 1; 532d9ba8f9eSMugunthan V N } 533df828598SMugunthan V N 5340cd8f9ccSMugunthan V N static void cpsw_set_promiscious(struct net_device *ndev, bool enable) 5350cd8f9ccSMugunthan V N { 5362a05a622SIvan Khoronzhuk struct cpsw_common *cpsw = ndev_to_cpsw(ndev); 5372a05a622SIvan Khoronzhuk struct cpsw_ale *ale = cpsw->ale; 5380cd8f9ccSMugunthan V N int i; 5390cd8f9ccSMugunthan V N 540606f3993SIvan Khoronzhuk if (cpsw->data.dual_emac) { 5410cd8f9ccSMugunthan V N bool flag = false; 5420cd8f9ccSMugunthan V N 5430cd8f9ccSMugunthan V N /* Enabling promiscuous mode for one interface will be 5440cd8f9ccSMugunthan V N * common for both the interface as the interface shares 5450cd8f9ccSMugunthan V N * the same hardware resource. 5460cd8f9ccSMugunthan V N */ 547606f3993SIvan Khoronzhuk for (i = 0; i < cpsw->data.slaves; i++) 548606f3993SIvan Khoronzhuk if (cpsw->slaves[i].ndev->flags & IFF_PROMISC) 5490cd8f9ccSMugunthan V N flag = true; 5500cd8f9ccSMugunthan V N 5510cd8f9ccSMugunthan V N if (!enable && flag) { 5520cd8f9ccSMugunthan V N enable = true; 5530cd8f9ccSMugunthan V N dev_err(&ndev->dev, "promiscuity not disabled as the other interface is still in promiscuity mode\n"); 5540cd8f9ccSMugunthan V N } 5550cd8f9ccSMugunthan V N 5560cd8f9ccSMugunthan V N if (enable) { 5570cd8f9ccSMugunthan V N /* Enable Bypass */ 5580cd8f9ccSMugunthan V N cpsw_ale_control_set(ale, 0, ALE_BYPASS, 1); 5590cd8f9ccSMugunthan V N 5600cd8f9ccSMugunthan V N dev_dbg(&ndev->dev, "promiscuity enabled\n"); 5610cd8f9ccSMugunthan V N } else { 5620cd8f9ccSMugunthan V N /* Disable Bypass */ 5630cd8f9ccSMugunthan V N cpsw_ale_control_set(ale, 0, ALE_BYPASS, 0); 5640cd8f9ccSMugunthan V N dev_dbg(&ndev->dev, "promiscuity disabled\n"); 5650cd8f9ccSMugunthan V N } 5660cd8f9ccSMugunthan V N } else { 5670cd8f9ccSMugunthan V N if (enable) { 5680cd8f9ccSMugunthan V N unsigned long timeout = jiffies + HZ; 5690cd8f9ccSMugunthan V N 5706f979eb3SLennart Sorensen /* Disable Learn for all ports (host is port 0 and slaves are port 1 and up */ 571606f3993SIvan Khoronzhuk for (i = 0; i <= cpsw->data.slaves; i++) { 5720cd8f9ccSMugunthan V N cpsw_ale_control_set(ale, i, 5730cd8f9ccSMugunthan V N ALE_PORT_NOLEARN, 1); 5740cd8f9ccSMugunthan V N cpsw_ale_control_set(ale, i, 5750cd8f9ccSMugunthan V N ALE_PORT_NO_SA_UPDATE, 1); 5760cd8f9ccSMugunthan V N } 5770cd8f9ccSMugunthan V N 5780cd8f9ccSMugunthan V N /* Clear All Untouched entries */ 5790cd8f9ccSMugunthan V N cpsw_ale_control_set(ale, 0, ALE_AGEOUT, 1); 5800cd8f9ccSMugunthan V N do { 5810cd8f9ccSMugunthan V N cpu_relax(); 5820cd8f9ccSMugunthan V N if (cpsw_ale_control_get(ale, 0, ALE_AGEOUT)) 5830cd8f9ccSMugunthan V N break; 5840cd8f9ccSMugunthan V N } while (time_after(timeout, jiffies)); 5850cd8f9ccSMugunthan V N cpsw_ale_control_set(ale, 0, ALE_AGEOUT, 1); 5860cd8f9ccSMugunthan V N 5870cd8f9ccSMugunthan V N /* Clear all mcast from ALE */ 58861f1cef9SGrygorii Strashko cpsw_ale_flush_multicast(ale, ALE_ALL_PORTS, -1); 5890cd8f9ccSMugunthan V N 5900cd8f9ccSMugunthan V N /* Flood All Unicast Packets to Host port */ 5910cd8f9ccSMugunthan V N cpsw_ale_control_set(ale, 0, ALE_P0_UNI_FLOOD, 1); 5920cd8f9ccSMugunthan V N dev_dbg(&ndev->dev, "promiscuity enabled\n"); 5930cd8f9ccSMugunthan V N } else { 5946f979eb3SLennart Sorensen /* Don't Flood All Unicast Packets to Host port */ 5950cd8f9ccSMugunthan V N cpsw_ale_control_set(ale, 0, ALE_P0_UNI_FLOOD, 0); 5960cd8f9ccSMugunthan V N 5976f979eb3SLennart Sorensen /* Enable Learn for all ports (host is port 0 and slaves are port 1 and up */ 598606f3993SIvan Khoronzhuk for (i = 0; i <= cpsw->data.slaves; i++) { 5990cd8f9ccSMugunthan V N cpsw_ale_control_set(ale, i, 6000cd8f9ccSMugunthan V N ALE_PORT_NOLEARN, 0); 6010cd8f9ccSMugunthan V N cpsw_ale_control_set(ale, i, 6020cd8f9ccSMugunthan V N ALE_PORT_NO_SA_UPDATE, 0); 6030cd8f9ccSMugunthan V N } 6040cd8f9ccSMugunthan V N dev_dbg(&ndev->dev, "promiscuity disabled\n"); 6050cd8f9ccSMugunthan V N } 6060cd8f9ccSMugunthan V N } 6070cd8f9ccSMugunthan V N } 6080cd8f9ccSMugunthan V N 6095c50a856SMugunthan V N static void cpsw_ndo_set_rx_mode(struct net_device *ndev) 6105c50a856SMugunthan V N { 6115c50a856SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 612606f3993SIvan Khoronzhuk struct cpsw_common *cpsw = priv->cpsw; 61325906052SMugunthan V N int vid; 61425906052SMugunthan V N 615606f3993SIvan Khoronzhuk if (cpsw->data.dual_emac) 616606f3993SIvan Khoronzhuk vid = cpsw->slaves[priv->emac_port].port_vlan; 61725906052SMugunthan V N else 618606f3993SIvan Khoronzhuk vid = cpsw->data.default_vlan; 6195c50a856SMugunthan V N 6205c50a856SMugunthan V N if (ndev->flags & IFF_PROMISC) { 6215c50a856SMugunthan V N /* Enable promiscuous mode */ 6220cd8f9ccSMugunthan V N cpsw_set_promiscious(ndev, true); 6232a05a622SIvan Khoronzhuk cpsw_ale_set_allmulti(cpsw->ale, IFF_ALLMULTI); 6245c50a856SMugunthan V N return; 6250cd8f9ccSMugunthan V N } else { 6260cd8f9ccSMugunthan V N /* Disable promiscuous mode */ 6270cd8f9ccSMugunthan V N cpsw_set_promiscious(ndev, false); 6285c50a856SMugunthan V N } 6295c50a856SMugunthan V N 6301e5c4bc4SLennart Sorensen /* Restore allmulti on vlans if necessary */ 6312a05a622SIvan Khoronzhuk cpsw_ale_set_allmulti(cpsw->ale, priv->ndev->flags & IFF_ALLMULTI); 6321e5c4bc4SLennart Sorensen 6335c50a856SMugunthan V N /* Clear all mcast from ALE */ 6342a05a622SIvan Khoronzhuk cpsw_ale_flush_multicast(cpsw->ale, ALE_ALL_PORTS, vid); 6355c50a856SMugunthan V N 6365c50a856SMugunthan V N if (!netdev_mc_empty(ndev)) { 6375c50a856SMugunthan V N struct netdev_hw_addr *ha; 6385c50a856SMugunthan V N 6395c50a856SMugunthan V N /* program multicast address list into ALE register */ 6405c50a856SMugunthan V N netdev_for_each_mc_addr(ha, ndev) { 641606f3993SIvan Khoronzhuk cpsw_add_mcast(cpsw, priv, (u8 *)ha->addr); 6425c50a856SMugunthan V N } 6435c50a856SMugunthan V N } 6445c50a856SMugunthan V N } 6455c50a856SMugunthan V N 6462c836bd9SIvan Khoronzhuk static void cpsw_intr_enable(struct cpsw_common *cpsw) 647df828598SMugunthan V N { 6485d8d0d4dSIvan Khoronzhuk __raw_writel(0xFF, &cpsw->wr_regs->tx_en); 6495d8d0d4dSIvan Khoronzhuk __raw_writel(0xFF, &cpsw->wr_regs->rx_en); 650df828598SMugunthan V N 6512c836bd9SIvan Khoronzhuk cpdma_ctlr_int_ctrl(cpsw->dma, true); 652df828598SMugunthan V N return; 653df828598SMugunthan V N } 654df828598SMugunthan V N 6552c836bd9SIvan Khoronzhuk static void cpsw_intr_disable(struct cpsw_common *cpsw) 656df828598SMugunthan V N { 6575d8d0d4dSIvan Khoronzhuk __raw_writel(0, &cpsw->wr_regs->tx_en); 6585d8d0d4dSIvan Khoronzhuk __raw_writel(0, &cpsw->wr_regs->rx_en); 659df828598SMugunthan V N 6602c836bd9SIvan Khoronzhuk cpdma_ctlr_int_ctrl(cpsw->dma, false); 661df828598SMugunthan V N return; 662df828598SMugunthan V N } 663df828598SMugunthan V N 6641a3b5056SOlof Johansson static void cpsw_tx_handler(void *token, int len, int status) 665df828598SMugunthan V N { 666e05107e6SIvan Khoronzhuk struct netdev_queue *txq; 667df828598SMugunthan V N struct sk_buff *skb = token; 668df828598SMugunthan V N struct net_device *ndev = skb->dev; 6692a05a622SIvan Khoronzhuk struct cpsw_common *cpsw = ndev_to_cpsw(ndev); 670df828598SMugunthan V N 671fae50823SMugunthan V N /* Check whether the queue is stopped due to stalled tx dma, if the 672fae50823SMugunthan V N * queue is stopped then start the queue as we have free desc for tx 673fae50823SMugunthan V N */ 674e05107e6SIvan Khoronzhuk txq = netdev_get_tx_queue(ndev, skb_get_queue_mapping(skb)); 675e05107e6SIvan Khoronzhuk if (unlikely(netif_tx_queue_stopped(txq))) 676e05107e6SIvan Khoronzhuk netif_tx_wake_queue(txq); 677e05107e6SIvan Khoronzhuk 6782a05a622SIvan Khoronzhuk cpts_tx_timestamp(cpsw->cpts, skb); 6798dc43ddcSTobias Klauser ndev->stats.tx_packets++; 6808dc43ddcSTobias Klauser ndev->stats.tx_bytes += len; 681df828598SMugunthan V N dev_kfree_skb_any(skb); 682df828598SMugunthan V N } 683df828598SMugunthan V N 6841a3b5056SOlof Johansson static void cpsw_rx_handler(void *token, int len, int status) 685df828598SMugunthan V N { 686e05107e6SIvan Khoronzhuk struct cpdma_chan *ch; 687df828598SMugunthan V N struct sk_buff *skb = token; 688b4727e69SSebastian Siewior struct sk_buff *new_skb; 689df828598SMugunthan V N struct net_device *ndev = skb->dev; 690df828598SMugunthan V N int ret = 0; 6912a05a622SIvan Khoronzhuk struct cpsw_common *cpsw = ndev_to_cpsw(ndev); 692df828598SMugunthan V N 6932a05a622SIvan Khoronzhuk cpsw_dual_emac_src_port_detect(cpsw, status, ndev, skb); 694d9ba8f9eSMugunthan V N 69516e5c57dSMugunthan V N if (unlikely(status < 0) || unlikely(!netif_running(ndev))) { 696a0e2c822SMugunthan V N bool ndev_status = false; 697606f3993SIvan Khoronzhuk struct cpsw_slave *slave = cpsw->slaves; 698a0e2c822SMugunthan V N int n; 699a0e2c822SMugunthan V N 700606f3993SIvan Khoronzhuk if (cpsw->data.dual_emac) { 701a0e2c822SMugunthan V N /* In dual emac mode check for all interfaces */ 702606f3993SIvan Khoronzhuk for (n = cpsw->data.slaves; n; n--, slave++) 703a0e2c822SMugunthan V N if (netif_running(slave->ndev)) 704a0e2c822SMugunthan V N ndev_status = true; 705a0e2c822SMugunthan V N } 706a0e2c822SMugunthan V N 707a0e2c822SMugunthan V N if (ndev_status && (status >= 0)) { 708a0e2c822SMugunthan V N /* The packet received is for the interface which 709a0e2c822SMugunthan V N * is already down and the other interface is up 710dbedd44eSJoe Perches * and running, instead of freeing which results 711a0e2c822SMugunthan V N * in reducing of the number of rx descriptor in 712a0e2c822SMugunthan V N * DMA engine, requeue skb back to cpdma. 713a0e2c822SMugunthan V N */ 714a0e2c822SMugunthan V N new_skb = skb; 715a0e2c822SMugunthan V N goto requeue; 716a0e2c822SMugunthan V N } 717a0e2c822SMugunthan V N 718b4727e69SSebastian Siewior /* the interface is going down, skbs are purged */ 719df828598SMugunthan V N dev_kfree_skb_any(skb); 720df828598SMugunthan V N return; 721df828598SMugunthan V N } 722b4727e69SSebastian Siewior 7232a05a622SIvan Khoronzhuk new_skb = netdev_alloc_skb_ip_align(ndev, cpsw->rx_packet_max); 724b4727e69SSebastian Siewior if (new_skb) { 725e05107e6SIvan Khoronzhuk skb_copy_queue_mapping(new_skb, skb); 726df828598SMugunthan V N skb_put(skb, len); 7272a05a622SIvan Khoronzhuk cpts_rx_timestamp(cpsw->cpts, skb); 728df828598SMugunthan V N skb->protocol = eth_type_trans(skb, ndev); 729df828598SMugunthan V N netif_receive_skb(skb); 7308dc43ddcSTobias Klauser ndev->stats.rx_bytes += len; 7318dc43ddcSTobias Klauser ndev->stats.rx_packets++; 732254a49d5SGrygorii Strashko kmemleak_not_leak(new_skb); 733b4727e69SSebastian Siewior } else { 7348dc43ddcSTobias Klauser ndev->stats.rx_dropped++; 735b4727e69SSebastian Siewior new_skb = skb; 736df828598SMugunthan V N } 737df828598SMugunthan V N 738a0e2c822SMugunthan V N requeue: 739e05107e6SIvan Khoronzhuk ch = cpsw->rxch[skb_get_queue_mapping(new_skb)]; 740e05107e6SIvan Khoronzhuk ret = cpdma_chan_submit(ch, new_skb, new_skb->data, 741b4727e69SSebastian Siewior skb_tailroom(new_skb), 0); 742b4727e69SSebastian Siewior if (WARN_ON(ret < 0)) 743b4727e69SSebastian Siewior dev_kfree_skb_any(new_skb); 744df828598SMugunthan V N } 745df828598SMugunthan V N 746c03abd84SFelipe Balbi static irqreturn_t cpsw_tx_interrupt(int irq, void *dev_id) 747df828598SMugunthan V N { 748dbc4ec52SIvan Khoronzhuk struct cpsw_common *cpsw = dev_id; 7497ce67a38SFelipe Balbi 7505d8d0d4dSIvan Khoronzhuk writel(0, &cpsw->wr_regs->tx_en); 7512c836bd9SIvan Khoronzhuk cpdma_ctlr_eoi(cpsw->dma, CPDMA_EOI_TX); 752c03abd84SFelipe Balbi 753e38b5a3dSIvan Khoronzhuk if (cpsw->quirk_irq) { 754e38b5a3dSIvan Khoronzhuk disable_irq_nosync(cpsw->irqs_table[1]); 755e38b5a3dSIvan Khoronzhuk cpsw->tx_irq_disabled = true; 7567da11600SMugunthan V N } 7577da11600SMugunthan V N 758dbc4ec52SIvan Khoronzhuk napi_schedule(&cpsw->napi_tx); 759c03abd84SFelipe Balbi return IRQ_HANDLED; 760c03abd84SFelipe Balbi } 761c03abd84SFelipe Balbi 762c03abd84SFelipe Balbi static irqreturn_t cpsw_rx_interrupt(int irq, void *dev_id) 763c03abd84SFelipe Balbi { 764dbc4ec52SIvan Khoronzhuk struct cpsw_common *cpsw = dev_id; 765c03abd84SFelipe Balbi 7662c836bd9SIvan Khoronzhuk cpdma_ctlr_eoi(cpsw->dma, CPDMA_EOI_RX); 7675d8d0d4dSIvan Khoronzhuk writel(0, &cpsw->wr_regs->rx_en); 768fd51cf19SSebastian Siewior 769e38b5a3dSIvan Khoronzhuk if (cpsw->quirk_irq) { 770e38b5a3dSIvan Khoronzhuk disable_irq_nosync(cpsw->irqs_table[0]); 771e38b5a3dSIvan Khoronzhuk cpsw->rx_irq_disabled = true; 7727da11600SMugunthan V N } 7737da11600SMugunthan V N 774dbc4ec52SIvan Khoronzhuk napi_schedule(&cpsw->napi_rx); 775df828598SMugunthan V N return IRQ_HANDLED; 776df828598SMugunthan V N } 777df828598SMugunthan V N 77832a7432cSMugunthan V N static int cpsw_tx_poll(struct napi_struct *napi_tx, int budget) 779df828598SMugunthan V N { 780e05107e6SIvan Khoronzhuk u32 ch_map; 781e05107e6SIvan Khoronzhuk int num_tx, ch; 782dbc4ec52SIvan Khoronzhuk struct cpsw_common *cpsw = napi_to_cpsw(napi_tx); 78332a7432cSMugunthan V N 784e05107e6SIvan Khoronzhuk /* process every unprocessed channel */ 785e05107e6SIvan Khoronzhuk ch_map = cpdma_ctrl_txchs_state(cpsw->dma); 786e05107e6SIvan Khoronzhuk for (ch = 0, num_tx = 0; num_tx < budget; ch_map >>= 1, ch++) { 787e05107e6SIvan Khoronzhuk if (!ch_map) { 788e05107e6SIvan Khoronzhuk ch_map = cpdma_ctrl_txchs_state(cpsw->dma); 789e05107e6SIvan Khoronzhuk if (!ch_map) 790e05107e6SIvan Khoronzhuk break; 791e05107e6SIvan Khoronzhuk 792e05107e6SIvan Khoronzhuk ch = 0; 793e05107e6SIvan Khoronzhuk } 794e05107e6SIvan Khoronzhuk 795e05107e6SIvan Khoronzhuk if (!(ch_map & 0x01)) 796e05107e6SIvan Khoronzhuk continue; 797e05107e6SIvan Khoronzhuk 798e05107e6SIvan Khoronzhuk num_tx += cpdma_chan_process(cpsw->txch[ch], budget - num_tx); 799e05107e6SIvan Khoronzhuk } 800e05107e6SIvan Khoronzhuk 80132a7432cSMugunthan V N if (num_tx < budget) { 80232a7432cSMugunthan V N napi_complete(napi_tx); 8035d8d0d4dSIvan Khoronzhuk writel(0xff, &cpsw->wr_regs->tx_en); 804e38b5a3dSIvan Khoronzhuk if (cpsw->quirk_irq && cpsw->tx_irq_disabled) { 805e38b5a3dSIvan Khoronzhuk cpsw->tx_irq_disabled = false; 806e38b5a3dSIvan Khoronzhuk enable_irq(cpsw->irqs_table[1]); 8077da11600SMugunthan V N } 80832a7432cSMugunthan V N } 80932a7432cSMugunthan V N 81032a7432cSMugunthan V N return num_tx; 81132a7432cSMugunthan V N } 81232a7432cSMugunthan V N 81332a7432cSMugunthan V N static int cpsw_rx_poll(struct napi_struct *napi_rx, int budget) 81432a7432cSMugunthan V N { 815e05107e6SIvan Khoronzhuk u32 ch_map; 816e05107e6SIvan Khoronzhuk int num_rx, ch; 817dbc4ec52SIvan Khoronzhuk struct cpsw_common *cpsw = napi_to_cpsw(napi_rx); 818510a1e72SMugunthan V N 819e05107e6SIvan Khoronzhuk /* process every unprocessed channel */ 820e05107e6SIvan Khoronzhuk ch_map = cpdma_ctrl_rxchs_state(cpsw->dma); 821e05107e6SIvan Khoronzhuk for (ch = 0, num_rx = 0; num_rx < budget; ch_map >>= 1, ch++) { 822e05107e6SIvan Khoronzhuk if (!ch_map) { 823e05107e6SIvan Khoronzhuk ch_map = cpdma_ctrl_rxchs_state(cpsw->dma); 824e05107e6SIvan Khoronzhuk if (!ch_map) 825e05107e6SIvan Khoronzhuk break; 826e05107e6SIvan Khoronzhuk 827e05107e6SIvan Khoronzhuk ch = 0; 828e05107e6SIvan Khoronzhuk } 829e05107e6SIvan Khoronzhuk 830e05107e6SIvan Khoronzhuk if (!(ch_map & 0x01)) 831e05107e6SIvan Khoronzhuk continue; 832e05107e6SIvan Khoronzhuk 833e05107e6SIvan Khoronzhuk num_rx += cpdma_chan_process(cpsw->rxch[ch], budget - num_rx); 834e05107e6SIvan Khoronzhuk } 835e05107e6SIvan Khoronzhuk 836510a1e72SMugunthan V N if (num_rx < budget) { 83732a7432cSMugunthan V N napi_complete(napi_rx); 8385d8d0d4dSIvan Khoronzhuk writel(0xff, &cpsw->wr_regs->rx_en); 839e38b5a3dSIvan Khoronzhuk if (cpsw->quirk_irq && cpsw->rx_irq_disabled) { 840e38b5a3dSIvan Khoronzhuk cpsw->rx_irq_disabled = false; 841e38b5a3dSIvan Khoronzhuk enable_irq(cpsw->irqs_table[0]); 8427da11600SMugunthan V N } 843510a1e72SMugunthan V N } 844df828598SMugunthan V N 845df828598SMugunthan V N return num_rx; 846df828598SMugunthan V N } 847df828598SMugunthan V N 848df828598SMugunthan V N static inline void soft_reset(const char *module, void __iomem *reg) 849df828598SMugunthan V N { 850df828598SMugunthan V N unsigned long timeout = jiffies + HZ; 851df828598SMugunthan V N 852df828598SMugunthan V N __raw_writel(1, reg); 853df828598SMugunthan V N do { 854df828598SMugunthan V N cpu_relax(); 855df828598SMugunthan V N } while ((__raw_readl(reg) & 1) && time_after(timeout, jiffies)); 856df828598SMugunthan V N 857df828598SMugunthan V N WARN(__raw_readl(reg) & 1, "failed to soft-reset %s\n", module); 858df828598SMugunthan V N } 859df828598SMugunthan V N 860df828598SMugunthan V N #define mac_hi(mac) (((mac)[0] << 0) | ((mac)[1] << 8) | \ 861df828598SMugunthan V N ((mac)[2] << 16) | ((mac)[3] << 24)) 862df828598SMugunthan V N #define mac_lo(mac) (((mac)[4] << 0) | ((mac)[5] << 8)) 863df828598SMugunthan V N 864df828598SMugunthan V N static void cpsw_set_slave_mac(struct cpsw_slave *slave, 865df828598SMugunthan V N struct cpsw_priv *priv) 866df828598SMugunthan V N { 8679750a3adSRichard Cochran slave_write(slave, mac_hi(priv->mac_addr), SA_HI); 8689750a3adSRichard Cochran slave_write(slave, mac_lo(priv->mac_addr), SA_LO); 869df828598SMugunthan V N } 870df828598SMugunthan V N 871df828598SMugunthan V N static void _cpsw_adjust_link(struct cpsw_slave *slave, 872df828598SMugunthan V N struct cpsw_priv *priv, bool *link) 873df828598SMugunthan V N { 874df828598SMugunthan V N struct phy_device *phy = slave->phy; 875df828598SMugunthan V N u32 mac_control = 0; 876df828598SMugunthan V N u32 slave_port; 877606f3993SIvan Khoronzhuk struct cpsw_common *cpsw = priv->cpsw; 878df828598SMugunthan V N 879df828598SMugunthan V N if (!phy) 880df828598SMugunthan V N return; 881df828598SMugunthan V N 8826f1f5836SIvan Khoronzhuk slave_port = cpsw_get_slave_port(slave->slave_num); 883df828598SMugunthan V N 884df828598SMugunthan V N if (phy->link) { 885606f3993SIvan Khoronzhuk mac_control = cpsw->data.mac_control; 886df828598SMugunthan V N 887df828598SMugunthan V N /* enable forwarding */ 8882a05a622SIvan Khoronzhuk cpsw_ale_control_set(cpsw->ale, slave_port, 889df828598SMugunthan V N ALE_PORT_STATE, ALE_PORT_STATE_FORWARD); 890df828598SMugunthan V N 891df828598SMugunthan V N if (phy->speed == 1000) 892df828598SMugunthan V N mac_control |= BIT(7); /* GIGABITEN */ 893df828598SMugunthan V N if (phy->duplex) 894df828598SMugunthan V N mac_control |= BIT(0); /* FULLDUPLEXEN */ 895342b7b74SDaniel Mack 896342b7b74SDaniel Mack /* set speed_in input in case RMII mode is used in 100Mbps */ 897342b7b74SDaniel Mack if (phy->speed == 100) 898342b7b74SDaniel Mack mac_control |= BIT(15); 899a81d8762SMugunthan V N else if (phy->speed == 10) 900a81d8762SMugunthan V N mac_control |= BIT(18); /* In Band mode */ 901342b7b74SDaniel Mack 9021923d6e4SMugunthan V N if (priv->rx_pause) 9031923d6e4SMugunthan V N mac_control |= BIT(3); 9041923d6e4SMugunthan V N 9051923d6e4SMugunthan V N if (priv->tx_pause) 9061923d6e4SMugunthan V N mac_control |= BIT(4); 9071923d6e4SMugunthan V N 908df828598SMugunthan V N *link = true; 909df828598SMugunthan V N } else { 910df828598SMugunthan V N mac_control = 0; 911df828598SMugunthan V N /* disable forwarding */ 9122a05a622SIvan Khoronzhuk cpsw_ale_control_set(cpsw->ale, slave_port, 913df828598SMugunthan V N ALE_PORT_STATE, ALE_PORT_STATE_DISABLE); 914df828598SMugunthan V N } 915df828598SMugunthan V N 916df828598SMugunthan V N if (mac_control != slave->mac_control) { 917df828598SMugunthan V N phy_print_status(phy); 918df828598SMugunthan V N __raw_writel(mac_control, &slave->sliver->mac_control); 919df828598SMugunthan V N } 920df828598SMugunthan V N 921df828598SMugunthan V N slave->mac_control = mac_control; 922df828598SMugunthan V N } 923df828598SMugunthan V N 924df828598SMugunthan V N static void cpsw_adjust_link(struct net_device *ndev) 925df828598SMugunthan V N { 926df828598SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 927df828598SMugunthan V N bool link = false; 928df828598SMugunthan V N 929df828598SMugunthan V N for_each_slave(priv, _cpsw_adjust_link, priv, &link); 930df828598SMugunthan V N 931df828598SMugunthan V N if (link) { 932df828598SMugunthan V N netif_carrier_on(ndev); 933df828598SMugunthan V N if (netif_running(ndev)) 934e05107e6SIvan Khoronzhuk netif_tx_wake_all_queues(ndev); 935df828598SMugunthan V N } else { 936df828598SMugunthan V N netif_carrier_off(ndev); 937e05107e6SIvan Khoronzhuk netif_tx_stop_all_queues(ndev); 938df828598SMugunthan V N } 939df828598SMugunthan V N } 940df828598SMugunthan V N 941ff5b8ef2SMugunthan V N static int cpsw_get_coalesce(struct net_device *ndev, 942ff5b8ef2SMugunthan V N struct ethtool_coalesce *coal) 943ff5b8ef2SMugunthan V N { 9442a05a622SIvan Khoronzhuk struct cpsw_common *cpsw = ndev_to_cpsw(ndev); 945ff5b8ef2SMugunthan V N 9462a05a622SIvan Khoronzhuk coal->rx_coalesce_usecs = cpsw->coal_intvl; 947ff5b8ef2SMugunthan V N return 0; 948ff5b8ef2SMugunthan V N } 949ff5b8ef2SMugunthan V N 950ff5b8ef2SMugunthan V N static int cpsw_set_coalesce(struct net_device *ndev, 951ff5b8ef2SMugunthan V N struct ethtool_coalesce *coal) 952ff5b8ef2SMugunthan V N { 953ff5b8ef2SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 954ff5b8ef2SMugunthan V N u32 int_ctrl; 955ff5b8ef2SMugunthan V N u32 num_interrupts = 0; 956ff5b8ef2SMugunthan V N u32 prescale = 0; 957ff5b8ef2SMugunthan V N u32 addnl_dvdr = 1; 958ff5b8ef2SMugunthan V N u32 coal_intvl = 0; 9595d8d0d4dSIvan Khoronzhuk struct cpsw_common *cpsw = priv->cpsw; 960ff5b8ef2SMugunthan V N 961ff5b8ef2SMugunthan V N coal_intvl = coal->rx_coalesce_usecs; 962ff5b8ef2SMugunthan V N 9635d8d0d4dSIvan Khoronzhuk int_ctrl = readl(&cpsw->wr_regs->int_control); 9642a05a622SIvan Khoronzhuk prescale = cpsw->bus_freq_mhz * 4; 965ff5b8ef2SMugunthan V N 966a84bc2a9SMugunthan V N if (!coal->rx_coalesce_usecs) { 967a84bc2a9SMugunthan V N int_ctrl &= ~(CPSW_INTPRESCALE_MASK | CPSW_INTPACEEN); 968a84bc2a9SMugunthan V N goto update_return; 969a84bc2a9SMugunthan V N } 970a84bc2a9SMugunthan V N 971ff5b8ef2SMugunthan V N if (coal_intvl < CPSW_CMINTMIN_INTVL) 972ff5b8ef2SMugunthan V N coal_intvl = CPSW_CMINTMIN_INTVL; 973ff5b8ef2SMugunthan V N 974ff5b8ef2SMugunthan V N if (coal_intvl > CPSW_CMINTMAX_INTVL) { 975ff5b8ef2SMugunthan V N /* Interrupt pacer works with 4us Pulse, we can 976ff5b8ef2SMugunthan V N * throttle further by dilating the 4us pulse. 977ff5b8ef2SMugunthan V N */ 978ff5b8ef2SMugunthan V N addnl_dvdr = CPSW_INTPRESCALE_MASK / prescale; 979ff5b8ef2SMugunthan V N 980ff5b8ef2SMugunthan V N if (addnl_dvdr > 1) { 981ff5b8ef2SMugunthan V N prescale *= addnl_dvdr; 982ff5b8ef2SMugunthan V N if (coal_intvl > (CPSW_CMINTMAX_INTVL * addnl_dvdr)) 983ff5b8ef2SMugunthan V N coal_intvl = (CPSW_CMINTMAX_INTVL 984ff5b8ef2SMugunthan V N * addnl_dvdr); 985ff5b8ef2SMugunthan V N } else { 986ff5b8ef2SMugunthan V N addnl_dvdr = 1; 987ff5b8ef2SMugunthan V N coal_intvl = CPSW_CMINTMAX_INTVL; 988ff5b8ef2SMugunthan V N } 989ff5b8ef2SMugunthan V N } 990ff5b8ef2SMugunthan V N 991ff5b8ef2SMugunthan V N num_interrupts = (1000 * addnl_dvdr) / coal_intvl; 9925d8d0d4dSIvan Khoronzhuk writel(num_interrupts, &cpsw->wr_regs->rx_imax); 9935d8d0d4dSIvan Khoronzhuk writel(num_interrupts, &cpsw->wr_regs->tx_imax); 994ff5b8ef2SMugunthan V N 995ff5b8ef2SMugunthan V N int_ctrl |= CPSW_INTPACEEN; 996ff5b8ef2SMugunthan V N int_ctrl &= (~CPSW_INTPRESCALE_MASK); 997ff5b8ef2SMugunthan V N int_ctrl |= (prescale & CPSW_INTPRESCALE_MASK); 998a84bc2a9SMugunthan V N 999a84bc2a9SMugunthan V N update_return: 10005d8d0d4dSIvan Khoronzhuk writel(int_ctrl, &cpsw->wr_regs->int_control); 1001ff5b8ef2SMugunthan V N 1002ff5b8ef2SMugunthan V N cpsw_notice(priv, timer, "Set coalesce to %d usecs.\n", coal_intvl); 10032a05a622SIvan Khoronzhuk cpsw->coal_intvl = coal_intvl; 1004ff5b8ef2SMugunthan V N 1005ff5b8ef2SMugunthan V N return 0; 1006ff5b8ef2SMugunthan V N } 1007ff5b8ef2SMugunthan V N 1008d9718546SMugunthan V N static int cpsw_get_sset_count(struct net_device *ndev, int sset) 1009d9718546SMugunthan V N { 1010e05107e6SIvan Khoronzhuk struct cpsw_common *cpsw = ndev_to_cpsw(ndev); 1011e05107e6SIvan Khoronzhuk 1012d9718546SMugunthan V N switch (sset) { 1013d9718546SMugunthan V N case ETH_SS_STATS: 1014e05107e6SIvan Khoronzhuk return (CPSW_STATS_COMMON_LEN + 1015e05107e6SIvan Khoronzhuk (cpsw->rx_ch_num + cpsw->tx_ch_num) * 1016e05107e6SIvan Khoronzhuk CPSW_STATS_CH_LEN); 1017d9718546SMugunthan V N default: 1018d9718546SMugunthan V N return -EOPNOTSUPP; 1019d9718546SMugunthan V N } 1020d9718546SMugunthan V N } 1021d9718546SMugunthan V N 1022e05107e6SIvan Khoronzhuk static void cpsw_add_ch_strings(u8 **p, int ch_num, int rx_dir) 1023e05107e6SIvan Khoronzhuk { 1024e05107e6SIvan Khoronzhuk int ch_stats_len; 1025e05107e6SIvan Khoronzhuk int line; 1026e05107e6SIvan Khoronzhuk int i; 1027e05107e6SIvan Khoronzhuk 1028e05107e6SIvan Khoronzhuk ch_stats_len = CPSW_STATS_CH_LEN * ch_num; 1029e05107e6SIvan Khoronzhuk for (i = 0; i < ch_stats_len; i++) { 1030e05107e6SIvan Khoronzhuk line = i % CPSW_STATS_CH_LEN; 1031e05107e6SIvan Khoronzhuk snprintf(*p, ETH_GSTRING_LEN, 1032e05107e6SIvan Khoronzhuk "%s DMA chan %d: %s", rx_dir ? "Rx" : "Tx", 1033e05107e6SIvan Khoronzhuk i / CPSW_STATS_CH_LEN, 1034e05107e6SIvan Khoronzhuk cpsw_gstrings_ch_stats[line].stat_string); 1035e05107e6SIvan Khoronzhuk *p += ETH_GSTRING_LEN; 1036e05107e6SIvan Khoronzhuk } 1037e05107e6SIvan Khoronzhuk } 1038e05107e6SIvan Khoronzhuk 1039d9718546SMugunthan V N static void cpsw_get_strings(struct net_device *ndev, u32 stringset, u8 *data) 1040d9718546SMugunthan V N { 1041e05107e6SIvan Khoronzhuk struct cpsw_common *cpsw = ndev_to_cpsw(ndev); 1042d9718546SMugunthan V N u8 *p = data; 1043d9718546SMugunthan V N int i; 1044d9718546SMugunthan V N 1045d9718546SMugunthan V N switch (stringset) { 1046d9718546SMugunthan V N case ETH_SS_STATS: 1047e05107e6SIvan Khoronzhuk for (i = 0; i < CPSW_STATS_COMMON_LEN; i++) { 1048d9718546SMugunthan V N memcpy(p, cpsw_gstrings_stats[i].stat_string, 1049d9718546SMugunthan V N ETH_GSTRING_LEN); 1050d9718546SMugunthan V N p += ETH_GSTRING_LEN; 1051d9718546SMugunthan V N } 1052e05107e6SIvan Khoronzhuk 1053e05107e6SIvan Khoronzhuk cpsw_add_ch_strings(&p, cpsw->rx_ch_num, 1); 1054e05107e6SIvan Khoronzhuk cpsw_add_ch_strings(&p, cpsw->tx_ch_num, 0); 1055d9718546SMugunthan V N break; 1056d9718546SMugunthan V N } 1057d9718546SMugunthan V N } 1058d9718546SMugunthan V N 1059d9718546SMugunthan V N static void cpsw_get_ethtool_stats(struct net_device *ndev, 1060d9718546SMugunthan V N struct ethtool_stats *stats, u64 *data) 1061d9718546SMugunthan V N { 1062d9718546SMugunthan V N u8 *p; 10632c836bd9SIvan Khoronzhuk struct cpsw_common *cpsw = ndev_to_cpsw(ndev); 1064e05107e6SIvan Khoronzhuk struct cpdma_chan_stats ch_stats; 1065e05107e6SIvan Khoronzhuk int i, l, ch; 1066d9718546SMugunthan V N 1067d9718546SMugunthan V N /* Collect Davinci CPDMA stats for Rx and Tx Channel */ 1068e05107e6SIvan Khoronzhuk for (l = 0; l < CPSW_STATS_COMMON_LEN; l++) 1069e05107e6SIvan Khoronzhuk data[l] = readl(cpsw->hw_stats + 1070e05107e6SIvan Khoronzhuk cpsw_gstrings_stats[l].stat_offset); 1071d9718546SMugunthan V N 1072e05107e6SIvan Khoronzhuk for (ch = 0; ch < cpsw->rx_ch_num; ch++) { 1073e05107e6SIvan Khoronzhuk cpdma_chan_get_stats(cpsw->rxch[ch], &ch_stats); 1074e05107e6SIvan Khoronzhuk for (i = 0; i < CPSW_STATS_CH_LEN; i++, l++) { 1075e05107e6SIvan Khoronzhuk p = (u8 *)&ch_stats + 1076e05107e6SIvan Khoronzhuk cpsw_gstrings_ch_stats[i].stat_offset; 1077e05107e6SIvan Khoronzhuk data[l] = *(u32 *)p; 1078e05107e6SIvan Khoronzhuk } 1079e05107e6SIvan Khoronzhuk } 1080d9718546SMugunthan V N 1081e05107e6SIvan Khoronzhuk for (ch = 0; ch < cpsw->tx_ch_num; ch++) { 1082e05107e6SIvan Khoronzhuk cpdma_chan_get_stats(cpsw->txch[ch], &ch_stats); 1083e05107e6SIvan Khoronzhuk for (i = 0; i < CPSW_STATS_CH_LEN; i++, l++) { 1084e05107e6SIvan Khoronzhuk p = (u8 *)&ch_stats + 1085e05107e6SIvan Khoronzhuk cpsw_gstrings_ch_stats[i].stat_offset; 1086e05107e6SIvan Khoronzhuk data[l] = *(u32 *)p; 1087d9718546SMugunthan V N } 1088d9718546SMugunthan V N } 1089d9718546SMugunthan V N } 1090d9718546SMugunthan V N 1091606f3993SIvan Khoronzhuk static int cpsw_common_res_usage_state(struct cpsw_common *cpsw) 1092d9ba8f9eSMugunthan V N { 1093d9ba8f9eSMugunthan V N u32 i; 1094d9ba8f9eSMugunthan V N u32 usage_count = 0; 1095d9ba8f9eSMugunthan V N 1096606f3993SIvan Khoronzhuk if (!cpsw->data.dual_emac) 1097d9ba8f9eSMugunthan V N return 0; 1098d9ba8f9eSMugunthan V N 1099606f3993SIvan Khoronzhuk for (i = 0; i < cpsw->data.slaves; i++) 1100606f3993SIvan Khoronzhuk if (cpsw->slaves[i].open_stat) 1101d9ba8f9eSMugunthan V N usage_count++; 1102d9ba8f9eSMugunthan V N 1103d9ba8f9eSMugunthan V N return usage_count; 1104d9ba8f9eSMugunthan V N } 1105d9ba8f9eSMugunthan V N 110627e9e103SIvan Khoronzhuk static inline int cpsw_tx_packet_submit(struct cpsw_priv *priv, 1107e05107e6SIvan Khoronzhuk struct sk_buff *skb, 1108e05107e6SIvan Khoronzhuk struct cpdma_chan *txch) 1109d9ba8f9eSMugunthan V N { 11102c836bd9SIvan Khoronzhuk struct cpsw_common *cpsw = priv->cpsw; 11112c836bd9SIvan Khoronzhuk 1112e05107e6SIvan Khoronzhuk return cpdma_chan_submit(txch, skb, skb->data, skb->len, 1113606f3993SIvan Khoronzhuk priv->emac_port + cpsw->data.dual_emac); 1114d9ba8f9eSMugunthan V N } 1115d9ba8f9eSMugunthan V N 1116d9ba8f9eSMugunthan V N static inline void cpsw_add_dual_emac_def_ale_entries( 1117d9ba8f9eSMugunthan V N struct cpsw_priv *priv, struct cpsw_slave *slave, 1118d9ba8f9eSMugunthan V N u32 slave_port) 1119d9ba8f9eSMugunthan V N { 11202a05a622SIvan Khoronzhuk struct cpsw_common *cpsw = priv->cpsw; 112171a2cbb7SGrygorii Strashko u32 port_mask = 1 << slave_port | ALE_PORT_HOST; 1122d9ba8f9eSMugunthan V N 11232a05a622SIvan Khoronzhuk if (cpsw->version == CPSW_VERSION_1) 1124d9ba8f9eSMugunthan V N slave_write(slave, slave->port_vlan, CPSW1_PORT_VLAN); 1125d9ba8f9eSMugunthan V N else 1126d9ba8f9eSMugunthan V N slave_write(slave, slave->port_vlan, CPSW2_PORT_VLAN); 11272a05a622SIvan Khoronzhuk cpsw_ale_add_vlan(cpsw->ale, slave->port_vlan, port_mask, 1128d9ba8f9eSMugunthan V N port_mask, port_mask, 0); 11292a05a622SIvan Khoronzhuk cpsw_ale_add_mcast(cpsw->ale, priv->ndev->broadcast, 1130d9ba8f9eSMugunthan V N port_mask, ALE_VLAN, slave->port_vlan, 0); 11312a05a622SIvan Khoronzhuk cpsw_ale_add_ucast(cpsw->ale, priv->mac_addr, 11322a05a622SIvan Khoronzhuk HOST_PORT_NUM, ALE_VLAN | 11332a05a622SIvan Khoronzhuk ALE_SECURE, slave->port_vlan); 1134d9ba8f9eSMugunthan V N } 1135d9ba8f9eSMugunthan V N 11361e7a2e21SDaniel Mack static void soft_reset_slave(struct cpsw_slave *slave) 1137df828598SMugunthan V N { 1138df828598SMugunthan V N char name[32]; 11391e7a2e21SDaniel Mack 11401e7a2e21SDaniel Mack snprintf(name, sizeof(name), "slave-%d", slave->slave_num); 11411e7a2e21SDaniel Mack soft_reset(name, &slave->sliver->soft_reset); 11421e7a2e21SDaniel Mack } 11431e7a2e21SDaniel Mack 11441e7a2e21SDaniel Mack static void cpsw_slave_open(struct cpsw_slave *slave, struct cpsw_priv *priv) 11451e7a2e21SDaniel Mack { 1146df828598SMugunthan V N u32 slave_port; 1147649a1688SIvan Khoronzhuk struct cpsw_common *cpsw = priv->cpsw; 1148df828598SMugunthan V N 11491e7a2e21SDaniel Mack soft_reset_slave(slave); 1150df828598SMugunthan V N 1151df828598SMugunthan V N /* setup priority mapping */ 1152df828598SMugunthan V N __raw_writel(RX_PRIORITY_MAPPING, &slave->sliver->rx_pri_map); 11539750a3adSRichard Cochran 11542a05a622SIvan Khoronzhuk switch (cpsw->version) { 11559750a3adSRichard Cochran case CPSW_VERSION_1: 11569750a3adSRichard Cochran slave_write(slave, TX_PRIORITY_MAPPING, CPSW1_TX_PRI_MAP); 11579750a3adSRichard Cochran break; 11589750a3adSRichard Cochran case CPSW_VERSION_2: 1159c193f365SMugunthan V N case CPSW_VERSION_3: 1160926489beSMugunthan V N case CPSW_VERSION_4: 11619750a3adSRichard Cochran slave_write(slave, TX_PRIORITY_MAPPING, CPSW2_TX_PRI_MAP); 11629750a3adSRichard Cochran break; 11639750a3adSRichard Cochran } 1164df828598SMugunthan V N 1165df828598SMugunthan V N /* setup max packet size, and mac address */ 11662a05a622SIvan Khoronzhuk __raw_writel(cpsw->rx_packet_max, &slave->sliver->rx_maxlen); 1167df828598SMugunthan V N cpsw_set_slave_mac(slave, priv); 1168df828598SMugunthan V N 1169df828598SMugunthan V N slave->mac_control = 0; /* no link yet */ 1170df828598SMugunthan V N 11716f1f5836SIvan Khoronzhuk slave_port = cpsw_get_slave_port(slave->slave_num); 1172df828598SMugunthan V N 1173606f3993SIvan Khoronzhuk if (cpsw->data.dual_emac) 1174d9ba8f9eSMugunthan V N cpsw_add_dual_emac_def_ale_entries(priv, slave, slave_port); 1175d9ba8f9eSMugunthan V N else 11762a05a622SIvan Khoronzhuk cpsw_ale_add_mcast(cpsw->ale, priv->ndev->broadcast, 1177e11b220fSMugunthan V N 1 << slave_port, 0, 0, ALE_MCAST_FWD_2); 1178df828598SMugunthan V N 1179d733f754SDavid Rivshin if (slave->data->phy_node) { 1180552165bcSDavid Rivshin slave->phy = of_phy_connect(priv->ndev, slave->data->phy_node, 11819e42f715SHeiko Schocher &cpsw_adjust_link, 0, slave->data->phy_if); 1182d733f754SDavid Rivshin if (!slave->phy) { 1183d733f754SDavid Rivshin dev_err(priv->dev, "phy \"%s\" not found on slave %d\n", 1184d733f754SDavid Rivshin slave->data->phy_node->full_name, 1185d733f754SDavid Rivshin slave->slave_num); 1186d733f754SDavid Rivshin return; 1187d733f754SDavid Rivshin } 1188d733f754SDavid Rivshin } else { 1189df828598SMugunthan V N slave->phy = phy_connect(priv->ndev, slave->data->phy_id, 1190f9a8f83bSFlorian Fainelli &cpsw_adjust_link, slave->data->phy_if); 1191df828598SMugunthan V N if (IS_ERR(slave->phy)) { 1192d733f754SDavid Rivshin dev_err(priv->dev, 1193d733f754SDavid Rivshin "phy \"%s\" not found on slave %d, err %ld\n", 1194d733f754SDavid Rivshin slave->data->phy_id, slave->slave_num, 1195d733f754SDavid Rivshin PTR_ERR(slave->phy)); 1196df828598SMugunthan V N slave->phy = NULL; 1197d733f754SDavid Rivshin return; 1198d733f754SDavid Rivshin } 1199d733f754SDavid Rivshin } 1200d733f754SDavid Rivshin 12012220943aSAndrew Lunn phy_attached_info(slave->phy); 12022220943aSAndrew Lunn 1203df828598SMugunthan V N phy_start(slave->phy); 1204388367a5SMugunthan V N 1205388367a5SMugunthan V N /* Configure GMII_SEL register */ 120656e31bd8SIvan Khoronzhuk cpsw_phy_sel(cpsw->dev, slave->phy->interface, slave->slave_num); 1207df828598SMugunthan V N } 1208df828598SMugunthan V N 12093b72c2feSMugunthan V N static inline void cpsw_add_default_vlan(struct cpsw_priv *priv) 12103b72c2feSMugunthan V N { 1211606f3993SIvan Khoronzhuk struct cpsw_common *cpsw = priv->cpsw; 1212606f3993SIvan Khoronzhuk const int vlan = cpsw->data.default_vlan; 12133b72c2feSMugunthan V N u32 reg; 12143b72c2feSMugunthan V N int i; 12151e5c4bc4SLennart Sorensen int unreg_mcast_mask; 12163b72c2feSMugunthan V N 12172a05a622SIvan Khoronzhuk reg = (cpsw->version == CPSW_VERSION_1) ? CPSW1_PORT_VLAN : 12183b72c2feSMugunthan V N CPSW2_PORT_VLAN; 12193b72c2feSMugunthan V N 12205d8d0d4dSIvan Khoronzhuk writel(vlan, &cpsw->host_port_regs->port_vlan); 12213b72c2feSMugunthan V N 1222606f3993SIvan Khoronzhuk for (i = 0; i < cpsw->data.slaves; i++) 1223606f3993SIvan Khoronzhuk slave_write(cpsw->slaves + i, vlan, reg); 12243b72c2feSMugunthan V N 12251e5c4bc4SLennart Sorensen if (priv->ndev->flags & IFF_ALLMULTI) 12261e5c4bc4SLennart Sorensen unreg_mcast_mask = ALE_ALL_PORTS; 12271e5c4bc4SLennart Sorensen else 12281e5c4bc4SLennart Sorensen unreg_mcast_mask = ALE_PORT_1 | ALE_PORT_2; 12291e5c4bc4SLennart Sorensen 12302a05a622SIvan Khoronzhuk cpsw_ale_add_vlan(cpsw->ale, vlan, ALE_ALL_PORTS, 123161f1cef9SGrygorii Strashko ALE_ALL_PORTS, ALE_ALL_PORTS, 123261f1cef9SGrygorii Strashko unreg_mcast_mask); 12333b72c2feSMugunthan V N } 12343b72c2feSMugunthan V N 1235df828598SMugunthan V N static void cpsw_init_host_port(struct cpsw_priv *priv) 1236df828598SMugunthan V N { 1237d9ba8f9eSMugunthan V N u32 fifo_mode; 12385d8d0d4dSIvan Khoronzhuk u32 control_reg; 12395d8d0d4dSIvan Khoronzhuk struct cpsw_common *cpsw = priv->cpsw; 12403b72c2feSMugunthan V N 1241df828598SMugunthan V N /* soft reset the controller and initialize ale */ 12425d8d0d4dSIvan Khoronzhuk soft_reset("cpsw", &cpsw->regs->soft_reset); 12432a05a622SIvan Khoronzhuk cpsw_ale_start(cpsw->ale); 1244df828598SMugunthan V N 1245df828598SMugunthan V N /* switch to vlan unaware mode */ 12462a05a622SIvan Khoronzhuk cpsw_ale_control_set(cpsw->ale, HOST_PORT_NUM, ALE_VLAN_AWARE, 12473b72c2feSMugunthan V N CPSW_ALE_VLAN_AWARE); 12485d8d0d4dSIvan Khoronzhuk control_reg = readl(&cpsw->regs->control); 12493b72c2feSMugunthan V N control_reg |= CPSW_VLAN_AWARE; 12505d8d0d4dSIvan Khoronzhuk writel(control_reg, &cpsw->regs->control); 1251606f3993SIvan Khoronzhuk fifo_mode = (cpsw->data.dual_emac) ? CPSW_FIFO_DUAL_MAC_MODE : 1252d9ba8f9eSMugunthan V N CPSW_FIFO_NORMAL_MODE; 12535d8d0d4dSIvan Khoronzhuk writel(fifo_mode, &cpsw->host_port_regs->tx_in_ctl); 1254df828598SMugunthan V N 1255df828598SMugunthan V N /* setup host port priority mapping */ 1256df828598SMugunthan V N __raw_writel(CPDMA_TX_PRIORITY_MAP, 12575d8d0d4dSIvan Khoronzhuk &cpsw->host_port_regs->cpdma_tx_pri_map); 12585d8d0d4dSIvan Khoronzhuk __raw_writel(0, &cpsw->host_port_regs->cpdma_rx_chan_map); 1259df828598SMugunthan V N 12602a05a622SIvan Khoronzhuk cpsw_ale_control_set(cpsw->ale, HOST_PORT_NUM, 1261df828598SMugunthan V N ALE_PORT_STATE, ALE_PORT_STATE_FORWARD); 1262df828598SMugunthan V N 1263606f3993SIvan Khoronzhuk if (!cpsw->data.dual_emac) { 12642a05a622SIvan Khoronzhuk cpsw_ale_add_ucast(cpsw->ale, priv->mac_addr, HOST_PORT_NUM, 1265d9ba8f9eSMugunthan V N 0, 0); 12662a05a622SIvan Khoronzhuk cpsw_ale_add_mcast(cpsw->ale, priv->ndev->broadcast, 126771a2cbb7SGrygorii Strashko ALE_PORT_HOST, 0, 0, ALE_MCAST_FWD_2); 1268df828598SMugunthan V N } 1269d9ba8f9eSMugunthan V N } 1270df828598SMugunthan V N 12713802dce1SIvan Khoronzhuk static int cpsw_fill_rx_channels(struct cpsw_priv *priv) 12723802dce1SIvan Khoronzhuk { 12733802dce1SIvan Khoronzhuk struct cpsw_common *cpsw = priv->cpsw; 12743802dce1SIvan Khoronzhuk struct sk_buff *skb; 12753802dce1SIvan Khoronzhuk int ch_buf_num; 1276e05107e6SIvan Khoronzhuk int ch, i, ret; 12773802dce1SIvan Khoronzhuk 1278e05107e6SIvan Khoronzhuk for (ch = 0; ch < cpsw->rx_ch_num; ch++) { 1279e05107e6SIvan Khoronzhuk ch_buf_num = cpdma_chan_get_rx_buf_num(cpsw->rxch[ch]); 12803802dce1SIvan Khoronzhuk for (i = 0; i < ch_buf_num; i++) { 12813802dce1SIvan Khoronzhuk skb = __netdev_alloc_skb_ip_align(priv->ndev, 12823802dce1SIvan Khoronzhuk cpsw->rx_packet_max, 12833802dce1SIvan Khoronzhuk GFP_KERNEL); 12843802dce1SIvan Khoronzhuk if (!skb) { 12853802dce1SIvan Khoronzhuk cpsw_err(priv, ifup, "cannot allocate skb\n"); 12863802dce1SIvan Khoronzhuk return -ENOMEM; 12873802dce1SIvan Khoronzhuk } 12883802dce1SIvan Khoronzhuk 1289e05107e6SIvan Khoronzhuk skb_set_queue_mapping(skb, ch); 1290e05107e6SIvan Khoronzhuk ret = cpdma_chan_submit(cpsw->rxch[ch], skb, skb->data, 12913802dce1SIvan Khoronzhuk skb_tailroom(skb), 0); 12923802dce1SIvan Khoronzhuk if (ret < 0) { 12933802dce1SIvan Khoronzhuk cpsw_err(priv, ifup, 1294e05107e6SIvan Khoronzhuk "cannot submit skb to channel %d rx, error %d\n", 1295e05107e6SIvan Khoronzhuk ch, ret); 12963802dce1SIvan Khoronzhuk kfree_skb(skb); 12973802dce1SIvan Khoronzhuk return ret; 12983802dce1SIvan Khoronzhuk } 12993802dce1SIvan Khoronzhuk kmemleak_not_leak(skb); 13003802dce1SIvan Khoronzhuk } 13013802dce1SIvan Khoronzhuk 1302e05107e6SIvan Khoronzhuk cpsw_info(priv, ifup, "ch %d rx, submitted %d descriptors\n", 1303e05107e6SIvan Khoronzhuk ch, ch_buf_num); 1304e05107e6SIvan Khoronzhuk } 13053802dce1SIvan Khoronzhuk 1306e05107e6SIvan Khoronzhuk return 0; 13073802dce1SIvan Khoronzhuk } 13083802dce1SIvan Khoronzhuk 13092a05a622SIvan Khoronzhuk static void cpsw_slave_stop(struct cpsw_slave *slave, struct cpsw_common *cpsw) 1310aacebbf8SSebastian Siewior { 13113995d265SSchuyler Patton u32 slave_port; 13123995d265SSchuyler Patton 13136f1f5836SIvan Khoronzhuk slave_port = cpsw_get_slave_port(slave->slave_num); 13143995d265SSchuyler Patton 1315aacebbf8SSebastian Siewior if (!slave->phy) 1316aacebbf8SSebastian Siewior return; 1317aacebbf8SSebastian Siewior phy_stop(slave->phy); 1318aacebbf8SSebastian Siewior phy_disconnect(slave->phy); 1319aacebbf8SSebastian Siewior slave->phy = NULL; 13202a05a622SIvan Khoronzhuk cpsw_ale_control_set(cpsw->ale, slave_port, 13213995d265SSchuyler Patton ALE_PORT_STATE, ALE_PORT_STATE_DISABLE); 13221f95ba00SGrygorii Strashko soft_reset_slave(slave); 1323aacebbf8SSebastian Siewior } 1324aacebbf8SSebastian Siewior 1325df828598SMugunthan V N static int cpsw_ndo_open(struct net_device *ndev) 1326df828598SMugunthan V N { 1327df828598SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 1328649a1688SIvan Khoronzhuk struct cpsw_common *cpsw = priv->cpsw; 13293802dce1SIvan Khoronzhuk int ret; 1330df828598SMugunthan V N u32 reg; 1331df828598SMugunthan V N 133256e31bd8SIvan Khoronzhuk ret = pm_runtime_get_sync(cpsw->dev); 1333108a6537SGrygorii Strashko if (ret < 0) { 133456e31bd8SIvan Khoronzhuk pm_runtime_put_noidle(cpsw->dev); 1335108a6537SGrygorii Strashko return ret; 1336108a6537SGrygorii Strashko } 13373fa88c51SGrygorii Strashko 1338606f3993SIvan Khoronzhuk if (!cpsw_common_res_usage_state(cpsw)) 13392c836bd9SIvan Khoronzhuk cpsw_intr_disable(cpsw); 1340df828598SMugunthan V N netif_carrier_off(ndev); 1341df828598SMugunthan V N 1342e05107e6SIvan Khoronzhuk /* Notify the stack of the actual queue counts. */ 1343e05107e6SIvan Khoronzhuk ret = netif_set_real_num_tx_queues(ndev, cpsw->tx_ch_num); 1344e05107e6SIvan Khoronzhuk if (ret) { 1345e05107e6SIvan Khoronzhuk dev_err(priv->dev, "cannot set real number of tx queues\n"); 1346e05107e6SIvan Khoronzhuk goto err_cleanup; 1347e05107e6SIvan Khoronzhuk } 1348e05107e6SIvan Khoronzhuk 1349e05107e6SIvan Khoronzhuk ret = netif_set_real_num_rx_queues(ndev, cpsw->rx_ch_num); 1350e05107e6SIvan Khoronzhuk if (ret) { 1351e05107e6SIvan Khoronzhuk dev_err(priv->dev, "cannot set real number of rx queues\n"); 1352e05107e6SIvan Khoronzhuk goto err_cleanup; 1353e05107e6SIvan Khoronzhuk } 1354e05107e6SIvan Khoronzhuk 13552a05a622SIvan Khoronzhuk reg = cpsw->version; 1356df828598SMugunthan V N 1357df828598SMugunthan V N dev_info(priv->dev, "initializing cpsw version %d.%d (%d)\n", 1358df828598SMugunthan V N CPSW_MAJOR_VERSION(reg), CPSW_MINOR_VERSION(reg), 1359df828598SMugunthan V N CPSW_RTL_VERSION(reg)); 1360df828598SMugunthan V N 1361df828598SMugunthan V N /* initialize host and slave ports */ 1362606f3993SIvan Khoronzhuk if (!cpsw_common_res_usage_state(cpsw)) 1363df828598SMugunthan V N cpsw_init_host_port(priv); 1364df828598SMugunthan V N for_each_slave(priv, cpsw_slave_open, priv); 1365df828598SMugunthan V N 13663b72c2feSMugunthan V N /* Add default VLAN */ 1367606f3993SIvan Khoronzhuk if (!cpsw->data.dual_emac) 13683b72c2feSMugunthan V N cpsw_add_default_vlan(priv); 1369e6afea0bSMugunthan V N else 13702a05a622SIvan Khoronzhuk cpsw_ale_add_vlan(cpsw->ale, cpsw->data.default_vlan, 137161f1cef9SGrygorii Strashko ALE_ALL_PORTS, ALE_ALL_PORTS, 0, 0); 13723b72c2feSMugunthan V N 1373606f3993SIvan Khoronzhuk if (!cpsw_common_res_usage_state(cpsw)) { 1374df828598SMugunthan V N /* setup tx dma to fixed prio and zero offset */ 13752c836bd9SIvan Khoronzhuk cpdma_control_set(cpsw->dma, CPDMA_TX_PRIO_FIXED, 1); 13762c836bd9SIvan Khoronzhuk cpdma_control_set(cpsw->dma, CPDMA_RX_BUFFER_OFFSET, 0); 1377df828598SMugunthan V N 1378d9ba8f9eSMugunthan V N /* disable priority elevation */ 13795d8d0d4dSIvan Khoronzhuk __raw_writel(0, &cpsw->regs->ptype); 1380df828598SMugunthan V N 1381d9ba8f9eSMugunthan V N /* enable statistics collection only on all ports */ 13825d8d0d4dSIvan Khoronzhuk __raw_writel(0x7, &cpsw->regs->stat_port_en); 1383df828598SMugunthan V N 13841923d6e4SMugunthan V N /* Enable internal fifo flow control */ 13855d8d0d4dSIvan Khoronzhuk writel(0x7, &cpsw->regs->flow_control); 13861923d6e4SMugunthan V N 1387dbc4ec52SIvan Khoronzhuk napi_enable(&cpsw->napi_rx); 1388dbc4ec52SIvan Khoronzhuk napi_enable(&cpsw->napi_tx); 1389d354eb85SMugunthan V N 1390e38b5a3dSIvan Khoronzhuk if (cpsw->tx_irq_disabled) { 1391e38b5a3dSIvan Khoronzhuk cpsw->tx_irq_disabled = false; 1392e38b5a3dSIvan Khoronzhuk enable_irq(cpsw->irqs_table[1]); 13937da11600SMugunthan V N } 13947da11600SMugunthan V N 1395e38b5a3dSIvan Khoronzhuk if (cpsw->rx_irq_disabled) { 1396e38b5a3dSIvan Khoronzhuk cpsw->rx_irq_disabled = false; 1397e38b5a3dSIvan Khoronzhuk enable_irq(cpsw->irqs_table[0]); 13987da11600SMugunthan V N } 13997da11600SMugunthan V N 14003802dce1SIvan Khoronzhuk ret = cpsw_fill_rx_channels(priv); 14013802dce1SIvan Khoronzhuk if (ret < 0) 1402aacebbf8SSebastian Siewior goto err_cleanup; 1403f280e89aSMugunthan V N 14042a05a622SIvan Khoronzhuk if (cpts_register(cpsw->dev, cpsw->cpts, 1405606f3993SIvan Khoronzhuk cpsw->data.cpts_clock_mult, 1406606f3993SIvan Khoronzhuk cpsw->data.cpts_clock_shift)) 1407f280e89aSMugunthan V N dev_err(priv->dev, "error registering cpts device\n"); 1408f280e89aSMugunthan V N 1409d9ba8f9eSMugunthan V N } 1410df828598SMugunthan V N 1411ff5b8ef2SMugunthan V N /* Enable Interrupt pacing if configured */ 14122a05a622SIvan Khoronzhuk if (cpsw->coal_intvl != 0) { 1413ff5b8ef2SMugunthan V N struct ethtool_coalesce coal; 1414ff5b8ef2SMugunthan V N 14152a05a622SIvan Khoronzhuk coal.rx_coalesce_usecs = cpsw->coal_intvl; 1416ff5b8ef2SMugunthan V N cpsw_set_coalesce(ndev, &coal); 1417ff5b8ef2SMugunthan V N } 1418ff5b8ef2SMugunthan V N 14192c836bd9SIvan Khoronzhuk cpdma_ctlr_start(cpsw->dma); 14202c836bd9SIvan Khoronzhuk cpsw_intr_enable(cpsw); 1421f63a975eSMugunthan V N 1422606f3993SIvan Khoronzhuk if (cpsw->data.dual_emac) 1423606f3993SIvan Khoronzhuk cpsw->slaves[priv->emac_port].open_stat = true; 1424e05107e6SIvan Khoronzhuk 1425e05107e6SIvan Khoronzhuk netif_tx_start_all_queues(ndev); 1426e05107e6SIvan Khoronzhuk 1427df828598SMugunthan V N return 0; 1428df828598SMugunthan V N 1429aacebbf8SSebastian Siewior err_cleanup: 14302c836bd9SIvan Khoronzhuk cpdma_ctlr_stop(cpsw->dma); 14312a05a622SIvan Khoronzhuk for_each_slave(priv, cpsw_slave_stop, cpsw); 143256e31bd8SIvan Khoronzhuk pm_runtime_put_sync(cpsw->dev); 1433aacebbf8SSebastian Siewior netif_carrier_off(priv->ndev); 1434aacebbf8SSebastian Siewior return ret; 1435df828598SMugunthan V N } 1436df828598SMugunthan V N 1437df828598SMugunthan V N static int cpsw_ndo_stop(struct net_device *ndev) 1438df828598SMugunthan V N { 1439df828598SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 1440649a1688SIvan Khoronzhuk struct cpsw_common *cpsw = priv->cpsw; 1441df828598SMugunthan V N 1442df828598SMugunthan V N cpsw_info(priv, ifdown, "shutting down cpsw device\n"); 1443e05107e6SIvan Khoronzhuk netif_tx_stop_all_queues(priv->ndev); 1444df828598SMugunthan V N netif_carrier_off(priv->ndev); 1445d9ba8f9eSMugunthan V N 1446606f3993SIvan Khoronzhuk if (cpsw_common_res_usage_state(cpsw) <= 1) { 1447dbc4ec52SIvan Khoronzhuk napi_disable(&cpsw->napi_rx); 1448dbc4ec52SIvan Khoronzhuk napi_disable(&cpsw->napi_tx); 14492a05a622SIvan Khoronzhuk cpts_unregister(cpsw->cpts); 14502c836bd9SIvan Khoronzhuk cpsw_intr_disable(cpsw); 14512c836bd9SIvan Khoronzhuk cpdma_ctlr_stop(cpsw->dma); 14522a05a622SIvan Khoronzhuk cpsw_ale_stop(cpsw->ale); 1453d9ba8f9eSMugunthan V N } 14542a05a622SIvan Khoronzhuk for_each_slave(priv, cpsw_slave_stop, cpsw); 145556e31bd8SIvan Khoronzhuk pm_runtime_put_sync(cpsw->dev); 1456606f3993SIvan Khoronzhuk if (cpsw->data.dual_emac) 1457606f3993SIvan Khoronzhuk cpsw->slaves[priv->emac_port].open_stat = false; 1458df828598SMugunthan V N return 0; 1459df828598SMugunthan V N } 1460df828598SMugunthan V N 1461df828598SMugunthan V N static netdev_tx_t cpsw_ndo_start_xmit(struct sk_buff *skb, 1462df828598SMugunthan V N struct net_device *ndev) 1463df828598SMugunthan V N { 1464df828598SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 14652c836bd9SIvan Khoronzhuk struct cpsw_common *cpsw = priv->cpsw; 1466e05107e6SIvan Khoronzhuk struct netdev_queue *txq; 1467e05107e6SIvan Khoronzhuk struct cpdma_chan *txch; 1468e05107e6SIvan Khoronzhuk int ret, q_idx; 1469df828598SMugunthan V N 1470860e9538SFlorian Westphal netif_trans_update(ndev); 1471df828598SMugunthan V N 1472df828598SMugunthan V N if (skb_padto(skb, CPSW_MIN_PACKET_SIZE)) { 1473df828598SMugunthan V N cpsw_err(priv, tx_err, "packet pad failed\n"); 14748dc43ddcSTobias Klauser ndev->stats.tx_dropped++; 1475df828598SMugunthan V N return NETDEV_TX_OK; 1476df828598SMugunthan V N } 1477df828598SMugunthan V N 14789232b16dSMugunthan V N if (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP && 14792a05a622SIvan Khoronzhuk cpsw->cpts->tx_enable) 14802e5b38abSRichard Cochran skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 14812e5b38abSRichard Cochran 14822e5b38abSRichard Cochran skb_tx_timestamp(skb); 14832e5b38abSRichard Cochran 1484e05107e6SIvan Khoronzhuk q_idx = skb_get_queue_mapping(skb); 1485e05107e6SIvan Khoronzhuk if (q_idx >= cpsw->tx_ch_num) 1486e05107e6SIvan Khoronzhuk q_idx = q_idx % cpsw->tx_ch_num; 1487e05107e6SIvan Khoronzhuk 1488e05107e6SIvan Khoronzhuk txch = cpsw->txch[q_idx]; 1489e05107e6SIvan Khoronzhuk ret = cpsw_tx_packet_submit(priv, skb, txch); 1490df828598SMugunthan V N if (unlikely(ret != 0)) { 1491df828598SMugunthan V N cpsw_err(priv, tx_err, "desc submit failed\n"); 1492df828598SMugunthan V N goto fail; 1493df828598SMugunthan V N } 1494df828598SMugunthan V N 1495fae50823SMugunthan V N /* If there is no more tx desc left free then we need to 1496fae50823SMugunthan V N * tell the kernel to stop sending us tx frames. 1497fae50823SMugunthan V N */ 1498e05107e6SIvan Khoronzhuk if (unlikely(!cpdma_check_free_tx_desc(txch))) { 1499e05107e6SIvan Khoronzhuk txq = netdev_get_tx_queue(ndev, q_idx); 1500e05107e6SIvan Khoronzhuk netif_tx_stop_queue(txq); 1501e05107e6SIvan Khoronzhuk } 1502fae50823SMugunthan V N 1503df828598SMugunthan V N return NETDEV_TX_OK; 1504df828598SMugunthan V N fail: 15058dc43ddcSTobias Klauser ndev->stats.tx_dropped++; 1506e05107e6SIvan Khoronzhuk txq = netdev_get_tx_queue(ndev, skb_get_queue_mapping(skb)); 1507e05107e6SIvan Khoronzhuk netif_tx_stop_queue(txq); 1508df828598SMugunthan V N return NETDEV_TX_BUSY; 1509df828598SMugunthan V N } 1510df828598SMugunthan V N 15112e5b38abSRichard Cochran #ifdef CONFIG_TI_CPTS 15122e5b38abSRichard Cochran 15132a05a622SIvan Khoronzhuk static void cpsw_hwtstamp_v1(struct cpsw_common *cpsw) 15142e5b38abSRichard Cochran { 1515606f3993SIvan Khoronzhuk struct cpsw_slave *slave = &cpsw->slaves[cpsw->data.active_slave]; 15162e5b38abSRichard Cochran u32 ts_en, seq_id; 15172e5b38abSRichard Cochran 15182a05a622SIvan Khoronzhuk if (!cpsw->cpts->tx_enable && !cpsw->cpts->rx_enable) { 15192e5b38abSRichard Cochran slave_write(slave, 0, CPSW1_TS_CTL); 15202e5b38abSRichard Cochran return; 15212e5b38abSRichard Cochran } 15222e5b38abSRichard Cochran 15232e5b38abSRichard Cochran seq_id = (30 << CPSW_V1_SEQ_ID_OFS_SHIFT) | ETH_P_1588; 15242e5b38abSRichard Cochran ts_en = EVENT_MSG_BITS << CPSW_V1_MSG_TYPE_OFS; 15252e5b38abSRichard Cochran 15262a05a622SIvan Khoronzhuk if (cpsw->cpts->tx_enable) 15272e5b38abSRichard Cochran ts_en |= CPSW_V1_TS_TX_EN; 15282e5b38abSRichard Cochran 15292a05a622SIvan Khoronzhuk if (cpsw->cpts->rx_enable) 15302e5b38abSRichard Cochran ts_en |= CPSW_V1_TS_RX_EN; 15312e5b38abSRichard Cochran 15322e5b38abSRichard Cochran slave_write(slave, ts_en, CPSW1_TS_CTL); 15332e5b38abSRichard Cochran slave_write(slave, seq_id, CPSW1_TS_SEQ_LTYPE); 15342e5b38abSRichard Cochran } 15352e5b38abSRichard Cochran 15362e5b38abSRichard Cochran static void cpsw_hwtstamp_v2(struct cpsw_priv *priv) 15372e5b38abSRichard Cochran { 1538d9ba8f9eSMugunthan V N struct cpsw_slave *slave; 15395d8d0d4dSIvan Khoronzhuk struct cpsw_common *cpsw = priv->cpsw; 15402e5b38abSRichard Cochran u32 ctrl, mtype; 15412e5b38abSRichard Cochran 1542606f3993SIvan Khoronzhuk if (cpsw->data.dual_emac) 1543606f3993SIvan Khoronzhuk slave = &cpsw->slaves[priv->emac_port]; 1544d9ba8f9eSMugunthan V N else 1545606f3993SIvan Khoronzhuk slave = &cpsw->slaves[cpsw->data.active_slave]; 1546d9ba8f9eSMugunthan V N 15472e5b38abSRichard Cochran ctrl = slave_read(slave, CPSW2_CONTROL); 15482a05a622SIvan Khoronzhuk switch (cpsw->version) { 154909c55372SGeorge Cherian case CPSW_VERSION_2: 155009c55372SGeorge Cherian ctrl &= ~CTRL_V2_ALL_TS_MASK; 15512e5b38abSRichard Cochran 15522a05a622SIvan Khoronzhuk if (cpsw->cpts->tx_enable) 155309c55372SGeorge Cherian ctrl |= CTRL_V2_TX_TS_BITS; 15542e5b38abSRichard Cochran 15552a05a622SIvan Khoronzhuk if (cpsw->cpts->rx_enable) 155609c55372SGeorge Cherian ctrl |= CTRL_V2_RX_TS_BITS; 155709c55372SGeorge Cherian break; 155809c55372SGeorge Cherian case CPSW_VERSION_3: 155909c55372SGeorge Cherian default: 156009c55372SGeorge Cherian ctrl &= ~CTRL_V3_ALL_TS_MASK; 156109c55372SGeorge Cherian 15622a05a622SIvan Khoronzhuk if (cpsw->cpts->tx_enable) 156309c55372SGeorge Cherian ctrl |= CTRL_V3_TX_TS_BITS; 156409c55372SGeorge Cherian 15652a05a622SIvan Khoronzhuk if (cpsw->cpts->rx_enable) 156609c55372SGeorge Cherian ctrl |= CTRL_V3_RX_TS_BITS; 156709c55372SGeorge Cherian break; 156809c55372SGeorge Cherian } 15692e5b38abSRichard Cochran 15702e5b38abSRichard Cochran mtype = (30 << TS_SEQ_ID_OFFSET_SHIFT) | EVENT_MSG_BITS; 15712e5b38abSRichard Cochran 15722e5b38abSRichard Cochran slave_write(slave, mtype, CPSW2_TS_SEQ_MTYPE); 15732e5b38abSRichard Cochran slave_write(slave, ctrl, CPSW2_CONTROL); 15745d8d0d4dSIvan Khoronzhuk __raw_writel(ETH_P_1588, &cpsw->regs->ts_ltype); 15752e5b38abSRichard Cochran } 15762e5b38abSRichard Cochran 1577a5b4145bSBen Hutchings static int cpsw_hwtstamp_set(struct net_device *dev, struct ifreq *ifr) 15782e5b38abSRichard Cochran { 15793177bf6fSMugunthan V N struct cpsw_priv *priv = netdev_priv(dev); 15802e5b38abSRichard Cochran struct hwtstamp_config cfg; 15812a05a622SIvan Khoronzhuk struct cpsw_common *cpsw = priv->cpsw; 15822a05a622SIvan Khoronzhuk struct cpts *cpts = cpsw->cpts; 15832e5b38abSRichard Cochran 15842a05a622SIvan Khoronzhuk if (cpsw->version != CPSW_VERSION_1 && 15852a05a622SIvan Khoronzhuk cpsw->version != CPSW_VERSION_2 && 15862a05a622SIvan Khoronzhuk cpsw->version != CPSW_VERSION_3) 15872ee91e54SBen Hutchings return -EOPNOTSUPP; 15882ee91e54SBen Hutchings 15892e5b38abSRichard Cochran if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg))) 15902e5b38abSRichard Cochran return -EFAULT; 15912e5b38abSRichard Cochran 15922e5b38abSRichard Cochran /* reserved for future extensions */ 15932e5b38abSRichard Cochran if (cfg.flags) 15942e5b38abSRichard Cochran return -EINVAL; 15952e5b38abSRichard Cochran 15962ee91e54SBen Hutchings if (cfg.tx_type != HWTSTAMP_TX_OFF && cfg.tx_type != HWTSTAMP_TX_ON) 15972e5b38abSRichard Cochran return -ERANGE; 15982e5b38abSRichard Cochran 15992e5b38abSRichard Cochran switch (cfg.rx_filter) { 16002e5b38abSRichard Cochran case HWTSTAMP_FILTER_NONE: 16012e5b38abSRichard Cochran cpts->rx_enable = 0; 16022e5b38abSRichard Cochran break; 16032e5b38abSRichard Cochran case HWTSTAMP_FILTER_ALL: 16042e5b38abSRichard Cochran case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: 16052e5b38abSRichard Cochran case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: 16062e5b38abSRichard Cochran case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: 16072e5b38abSRichard Cochran return -ERANGE; 16082e5b38abSRichard Cochran case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: 16092e5b38abSRichard Cochran case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 16102e5b38abSRichard Cochran case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 16112e5b38abSRichard Cochran case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: 16122e5b38abSRichard Cochran case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: 16132e5b38abSRichard Cochran case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: 16142e5b38abSRichard Cochran case HWTSTAMP_FILTER_PTP_V2_EVENT: 16152e5b38abSRichard Cochran case HWTSTAMP_FILTER_PTP_V2_SYNC: 16162e5b38abSRichard Cochran case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 16172e5b38abSRichard Cochran cpts->rx_enable = 1; 16182e5b38abSRichard Cochran cfg.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT; 16192e5b38abSRichard Cochran break; 16202e5b38abSRichard Cochran default: 16212e5b38abSRichard Cochran return -ERANGE; 16222e5b38abSRichard Cochran } 16232e5b38abSRichard Cochran 16242ee91e54SBen Hutchings cpts->tx_enable = cfg.tx_type == HWTSTAMP_TX_ON; 16252ee91e54SBen Hutchings 16262a05a622SIvan Khoronzhuk switch (cpsw->version) { 16272e5b38abSRichard Cochran case CPSW_VERSION_1: 16282a05a622SIvan Khoronzhuk cpsw_hwtstamp_v1(cpsw); 16292e5b38abSRichard Cochran break; 16302e5b38abSRichard Cochran case CPSW_VERSION_2: 1631f7d403cbSGeorge Cherian case CPSW_VERSION_3: 16322e5b38abSRichard Cochran cpsw_hwtstamp_v2(priv); 16332e5b38abSRichard Cochran break; 16342e5b38abSRichard Cochran default: 16352ee91e54SBen Hutchings WARN_ON(1); 16362e5b38abSRichard Cochran } 16372e5b38abSRichard Cochran 16382e5b38abSRichard Cochran return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0; 16392e5b38abSRichard Cochran } 16402e5b38abSRichard Cochran 1641a5b4145bSBen Hutchings static int cpsw_hwtstamp_get(struct net_device *dev, struct ifreq *ifr) 1642a5b4145bSBen Hutchings { 16432a05a622SIvan Khoronzhuk struct cpsw_common *cpsw = ndev_to_cpsw(dev); 16442a05a622SIvan Khoronzhuk struct cpts *cpts = cpsw->cpts; 1645a5b4145bSBen Hutchings struct hwtstamp_config cfg; 1646a5b4145bSBen Hutchings 16472a05a622SIvan Khoronzhuk if (cpsw->version != CPSW_VERSION_1 && 16482a05a622SIvan Khoronzhuk cpsw->version != CPSW_VERSION_2 && 16492a05a622SIvan Khoronzhuk cpsw->version != CPSW_VERSION_3) 1650a5b4145bSBen Hutchings return -EOPNOTSUPP; 1651a5b4145bSBen Hutchings 1652a5b4145bSBen Hutchings cfg.flags = 0; 1653a5b4145bSBen Hutchings cfg.tx_type = cpts->tx_enable ? HWTSTAMP_TX_ON : HWTSTAMP_TX_OFF; 1654a5b4145bSBen Hutchings cfg.rx_filter = (cpts->rx_enable ? 1655a5b4145bSBen Hutchings HWTSTAMP_FILTER_PTP_V2_EVENT : HWTSTAMP_FILTER_NONE); 1656a5b4145bSBen Hutchings 1657a5b4145bSBen Hutchings return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0; 1658a5b4145bSBen Hutchings } 1659a5b4145bSBen Hutchings 16602e5b38abSRichard Cochran #endif /*CONFIG_TI_CPTS*/ 16612e5b38abSRichard Cochran 16622e5b38abSRichard Cochran static int cpsw_ndo_ioctl(struct net_device *dev, struct ifreq *req, int cmd) 16632e5b38abSRichard Cochran { 166411f2c988SMugunthan V N struct cpsw_priv *priv = netdev_priv(dev); 1665606f3993SIvan Khoronzhuk struct cpsw_common *cpsw = priv->cpsw; 1666606f3993SIvan Khoronzhuk int slave_no = cpsw_slave_index(cpsw, priv); 166711f2c988SMugunthan V N 16682e5b38abSRichard Cochran if (!netif_running(dev)) 16692e5b38abSRichard Cochran return -EINVAL; 16702e5b38abSRichard Cochran 167111f2c988SMugunthan V N switch (cmd) { 16722e5b38abSRichard Cochran #ifdef CONFIG_TI_CPTS 167311f2c988SMugunthan V N case SIOCSHWTSTAMP: 1674a5b4145bSBen Hutchings return cpsw_hwtstamp_set(dev, req); 1675a5b4145bSBen Hutchings case SIOCGHWTSTAMP: 1676a5b4145bSBen Hutchings return cpsw_hwtstamp_get(dev, req); 16772e5b38abSRichard Cochran #endif 16782e5b38abSRichard Cochran } 16792e5b38abSRichard Cochran 1680606f3993SIvan Khoronzhuk if (!cpsw->slaves[slave_no].phy) 1681c1b59947SStefan Sørensen return -EOPNOTSUPP; 1682606f3993SIvan Khoronzhuk return phy_mii_ioctl(cpsw->slaves[slave_no].phy, req, cmd); 168311f2c988SMugunthan V N } 168411f2c988SMugunthan V N 1685df828598SMugunthan V N static void cpsw_ndo_tx_timeout(struct net_device *ndev) 1686df828598SMugunthan V N { 1687df828598SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 16882c836bd9SIvan Khoronzhuk struct cpsw_common *cpsw = priv->cpsw; 1689e05107e6SIvan Khoronzhuk int ch; 1690df828598SMugunthan V N 1691df828598SMugunthan V N cpsw_err(priv, tx_err, "transmit timeout, restarting dma\n"); 16928dc43ddcSTobias Klauser ndev->stats.tx_errors++; 16932c836bd9SIvan Khoronzhuk cpsw_intr_disable(cpsw); 1694e05107e6SIvan Khoronzhuk for (ch = 0; ch < cpsw->tx_ch_num; ch++) { 1695e05107e6SIvan Khoronzhuk cpdma_chan_stop(cpsw->txch[ch]); 1696e05107e6SIvan Khoronzhuk cpdma_chan_start(cpsw->txch[ch]); 1697e05107e6SIvan Khoronzhuk } 1698e05107e6SIvan Khoronzhuk 16992c836bd9SIvan Khoronzhuk cpsw_intr_enable(cpsw); 1700df828598SMugunthan V N } 1701df828598SMugunthan V N 1702dcfd8d58SMugunthan V N static int cpsw_ndo_set_mac_address(struct net_device *ndev, void *p) 1703dcfd8d58SMugunthan V N { 1704dcfd8d58SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 1705dcfd8d58SMugunthan V N struct sockaddr *addr = (struct sockaddr *)p; 1706649a1688SIvan Khoronzhuk struct cpsw_common *cpsw = priv->cpsw; 1707dcfd8d58SMugunthan V N int flags = 0; 1708dcfd8d58SMugunthan V N u16 vid = 0; 1709a6c5d14fSGrygorii Strashko int ret; 1710dcfd8d58SMugunthan V N 1711dcfd8d58SMugunthan V N if (!is_valid_ether_addr(addr->sa_data)) 1712dcfd8d58SMugunthan V N return -EADDRNOTAVAIL; 1713dcfd8d58SMugunthan V N 171456e31bd8SIvan Khoronzhuk ret = pm_runtime_get_sync(cpsw->dev); 1715a6c5d14fSGrygorii Strashko if (ret < 0) { 171656e31bd8SIvan Khoronzhuk pm_runtime_put_noidle(cpsw->dev); 1717a6c5d14fSGrygorii Strashko return ret; 1718a6c5d14fSGrygorii Strashko } 1719a6c5d14fSGrygorii Strashko 1720606f3993SIvan Khoronzhuk if (cpsw->data.dual_emac) { 1721606f3993SIvan Khoronzhuk vid = cpsw->slaves[priv->emac_port].port_vlan; 1722dcfd8d58SMugunthan V N flags = ALE_VLAN; 1723dcfd8d58SMugunthan V N } 1724dcfd8d58SMugunthan V N 17252a05a622SIvan Khoronzhuk cpsw_ale_del_ucast(cpsw->ale, priv->mac_addr, HOST_PORT_NUM, 1726dcfd8d58SMugunthan V N flags, vid); 17272a05a622SIvan Khoronzhuk cpsw_ale_add_ucast(cpsw->ale, addr->sa_data, HOST_PORT_NUM, 1728dcfd8d58SMugunthan V N flags, vid); 1729dcfd8d58SMugunthan V N 1730dcfd8d58SMugunthan V N memcpy(priv->mac_addr, addr->sa_data, ETH_ALEN); 1731dcfd8d58SMugunthan V N memcpy(ndev->dev_addr, priv->mac_addr, ETH_ALEN); 1732dcfd8d58SMugunthan V N for_each_slave(priv, cpsw_set_slave_mac, priv); 1733dcfd8d58SMugunthan V N 173456e31bd8SIvan Khoronzhuk pm_runtime_put(cpsw->dev); 1735a6c5d14fSGrygorii Strashko 1736dcfd8d58SMugunthan V N return 0; 1737dcfd8d58SMugunthan V N } 1738dcfd8d58SMugunthan V N 1739df828598SMugunthan V N #ifdef CONFIG_NET_POLL_CONTROLLER 1740df828598SMugunthan V N static void cpsw_ndo_poll_controller(struct net_device *ndev) 1741df828598SMugunthan V N { 1742dbc4ec52SIvan Khoronzhuk struct cpsw_common *cpsw = ndev_to_cpsw(ndev); 1743df828598SMugunthan V N 1744dbc4ec52SIvan Khoronzhuk cpsw_intr_disable(cpsw); 1745dbc4ec52SIvan Khoronzhuk cpsw_rx_interrupt(cpsw->irqs_table[0], cpsw); 1746dbc4ec52SIvan Khoronzhuk cpsw_tx_interrupt(cpsw->irqs_table[1], cpsw); 1747dbc4ec52SIvan Khoronzhuk cpsw_intr_enable(cpsw); 1748df828598SMugunthan V N } 1749df828598SMugunthan V N #endif 1750df828598SMugunthan V N 17513b72c2feSMugunthan V N static inline int cpsw_add_vlan_ale_entry(struct cpsw_priv *priv, 17523b72c2feSMugunthan V N unsigned short vid) 17533b72c2feSMugunthan V N { 17543b72c2feSMugunthan V N int ret; 17559f6bd8faSMugunthan V N int unreg_mcast_mask = 0; 17569f6bd8faSMugunthan V N u32 port_mask; 1757606f3993SIvan Khoronzhuk struct cpsw_common *cpsw = priv->cpsw; 17589f6bd8faSMugunthan V N 1759606f3993SIvan Khoronzhuk if (cpsw->data.dual_emac) { 17609f6bd8faSMugunthan V N port_mask = (1 << (priv->emac_port + 1)) | ALE_PORT_HOST; 17619f6bd8faSMugunthan V N 17629f6bd8faSMugunthan V N if (priv->ndev->flags & IFF_ALLMULTI) 17639f6bd8faSMugunthan V N unreg_mcast_mask = port_mask; 17649f6bd8faSMugunthan V N } else { 17659f6bd8faSMugunthan V N port_mask = ALE_ALL_PORTS; 17661e5c4bc4SLennart Sorensen 17671e5c4bc4SLennart Sorensen if (priv->ndev->flags & IFF_ALLMULTI) 17681e5c4bc4SLennart Sorensen unreg_mcast_mask = ALE_ALL_PORTS; 17691e5c4bc4SLennart Sorensen else 17701e5c4bc4SLennart Sorensen unreg_mcast_mask = ALE_PORT_1 | ALE_PORT_2; 17719f6bd8faSMugunthan V N } 17723b72c2feSMugunthan V N 17732a05a622SIvan Khoronzhuk ret = cpsw_ale_add_vlan(cpsw->ale, vid, port_mask, 0, port_mask, 177461f1cef9SGrygorii Strashko unreg_mcast_mask); 17753b72c2feSMugunthan V N if (ret != 0) 17763b72c2feSMugunthan V N return ret; 17773b72c2feSMugunthan V N 17782a05a622SIvan Khoronzhuk ret = cpsw_ale_add_ucast(cpsw->ale, priv->mac_addr, 177971a2cbb7SGrygorii Strashko HOST_PORT_NUM, ALE_VLAN, vid); 17803b72c2feSMugunthan V N if (ret != 0) 17813b72c2feSMugunthan V N goto clean_vid; 17823b72c2feSMugunthan V N 17832a05a622SIvan Khoronzhuk ret = cpsw_ale_add_mcast(cpsw->ale, priv->ndev->broadcast, 17849f6bd8faSMugunthan V N port_mask, ALE_VLAN, vid, 0); 17853b72c2feSMugunthan V N if (ret != 0) 17863b72c2feSMugunthan V N goto clean_vlan_ucast; 17873b72c2feSMugunthan V N return 0; 17883b72c2feSMugunthan V N 17893b72c2feSMugunthan V N clean_vlan_ucast: 17902a05a622SIvan Khoronzhuk cpsw_ale_del_ucast(cpsw->ale, priv->mac_addr, 179171a2cbb7SGrygorii Strashko HOST_PORT_NUM, ALE_VLAN, vid); 17923b72c2feSMugunthan V N clean_vid: 17932a05a622SIvan Khoronzhuk cpsw_ale_del_vlan(cpsw->ale, vid, 0); 17943b72c2feSMugunthan V N return ret; 17953b72c2feSMugunthan V N } 17963b72c2feSMugunthan V N 17973b72c2feSMugunthan V N static int cpsw_ndo_vlan_rx_add_vid(struct net_device *ndev, 179880d5c368SPatrick McHardy __be16 proto, u16 vid) 17993b72c2feSMugunthan V N { 18003b72c2feSMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 1801649a1688SIvan Khoronzhuk struct cpsw_common *cpsw = priv->cpsw; 1802a6c5d14fSGrygorii Strashko int ret; 18033b72c2feSMugunthan V N 1804606f3993SIvan Khoronzhuk if (vid == cpsw->data.default_vlan) 18053b72c2feSMugunthan V N return 0; 18063b72c2feSMugunthan V N 180756e31bd8SIvan Khoronzhuk ret = pm_runtime_get_sync(cpsw->dev); 1808a6c5d14fSGrygorii Strashko if (ret < 0) { 180956e31bd8SIvan Khoronzhuk pm_runtime_put_noidle(cpsw->dev); 1810a6c5d14fSGrygorii Strashko return ret; 1811a6c5d14fSGrygorii Strashko } 1812a6c5d14fSGrygorii Strashko 1813606f3993SIvan Khoronzhuk if (cpsw->data.dual_emac) { 181402a54164SMugunthan V N /* In dual EMAC, reserved VLAN id should not be used for 181502a54164SMugunthan V N * creating VLAN interfaces as this can break the dual 181602a54164SMugunthan V N * EMAC port separation 181702a54164SMugunthan V N */ 181802a54164SMugunthan V N int i; 181902a54164SMugunthan V N 1820606f3993SIvan Khoronzhuk for (i = 0; i < cpsw->data.slaves; i++) { 1821606f3993SIvan Khoronzhuk if (vid == cpsw->slaves[i].port_vlan) 182202a54164SMugunthan V N return -EINVAL; 182302a54164SMugunthan V N } 182402a54164SMugunthan V N } 182502a54164SMugunthan V N 18263b72c2feSMugunthan V N dev_info(priv->dev, "Adding vlanid %d to vlan filter\n", vid); 1827a6c5d14fSGrygorii Strashko ret = cpsw_add_vlan_ale_entry(priv, vid); 1828a6c5d14fSGrygorii Strashko 182956e31bd8SIvan Khoronzhuk pm_runtime_put(cpsw->dev); 1830a6c5d14fSGrygorii Strashko return ret; 18313b72c2feSMugunthan V N } 18323b72c2feSMugunthan V N 18333b72c2feSMugunthan V N static int cpsw_ndo_vlan_rx_kill_vid(struct net_device *ndev, 183480d5c368SPatrick McHardy __be16 proto, u16 vid) 18353b72c2feSMugunthan V N { 18363b72c2feSMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 1837649a1688SIvan Khoronzhuk struct cpsw_common *cpsw = priv->cpsw; 18383b72c2feSMugunthan V N int ret; 18393b72c2feSMugunthan V N 1840606f3993SIvan Khoronzhuk if (vid == cpsw->data.default_vlan) 18413b72c2feSMugunthan V N return 0; 18423b72c2feSMugunthan V N 184356e31bd8SIvan Khoronzhuk ret = pm_runtime_get_sync(cpsw->dev); 1844a6c5d14fSGrygorii Strashko if (ret < 0) { 184556e31bd8SIvan Khoronzhuk pm_runtime_put_noidle(cpsw->dev); 1846a6c5d14fSGrygorii Strashko return ret; 1847a6c5d14fSGrygorii Strashko } 1848a6c5d14fSGrygorii Strashko 1849606f3993SIvan Khoronzhuk if (cpsw->data.dual_emac) { 185002a54164SMugunthan V N int i; 185102a54164SMugunthan V N 1852606f3993SIvan Khoronzhuk for (i = 0; i < cpsw->data.slaves; i++) { 1853606f3993SIvan Khoronzhuk if (vid == cpsw->slaves[i].port_vlan) 185402a54164SMugunthan V N return -EINVAL; 185502a54164SMugunthan V N } 185602a54164SMugunthan V N } 185702a54164SMugunthan V N 18583b72c2feSMugunthan V N dev_info(priv->dev, "removing vlanid %d from vlan filter\n", vid); 18592a05a622SIvan Khoronzhuk ret = cpsw_ale_del_vlan(cpsw->ale, vid, 0); 18603b72c2feSMugunthan V N if (ret != 0) 18613b72c2feSMugunthan V N return ret; 18623b72c2feSMugunthan V N 18632a05a622SIvan Khoronzhuk ret = cpsw_ale_del_ucast(cpsw->ale, priv->mac_addr, 186461f1cef9SGrygorii Strashko HOST_PORT_NUM, ALE_VLAN, vid); 18653b72c2feSMugunthan V N if (ret != 0) 18663b72c2feSMugunthan V N return ret; 18673b72c2feSMugunthan V N 18682a05a622SIvan Khoronzhuk ret = cpsw_ale_del_mcast(cpsw->ale, priv->ndev->broadcast, 18693b72c2feSMugunthan V N 0, ALE_VLAN, vid); 187056e31bd8SIvan Khoronzhuk pm_runtime_put(cpsw->dev); 1871a6c5d14fSGrygorii Strashko return ret; 18723b72c2feSMugunthan V N } 18733b72c2feSMugunthan V N 1874df828598SMugunthan V N static const struct net_device_ops cpsw_netdev_ops = { 1875df828598SMugunthan V N .ndo_open = cpsw_ndo_open, 1876df828598SMugunthan V N .ndo_stop = cpsw_ndo_stop, 1877df828598SMugunthan V N .ndo_start_xmit = cpsw_ndo_start_xmit, 1878dcfd8d58SMugunthan V N .ndo_set_mac_address = cpsw_ndo_set_mac_address, 18792e5b38abSRichard Cochran .ndo_do_ioctl = cpsw_ndo_ioctl, 1880df828598SMugunthan V N .ndo_validate_addr = eth_validate_addr, 18815c473ed2SDavid S. Miller .ndo_change_mtu = eth_change_mtu, 1882df828598SMugunthan V N .ndo_tx_timeout = cpsw_ndo_tx_timeout, 18835c50a856SMugunthan V N .ndo_set_rx_mode = cpsw_ndo_set_rx_mode, 1884df828598SMugunthan V N #ifdef CONFIG_NET_POLL_CONTROLLER 1885df828598SMugunthan V N .ndo_poll_controller = cpsw_ndo_poll_controller, 1886df828598SMugunthan V N #endif 18873b72c2feSMugunthan V N .ndo_vlan_rx_add_vid = cpsw_ndo_vlan_rx_add_vid, 18883b72c2feSMugunthan V N .ndo_vlan_rx_kill_vid = cpsw_ndo_vlan_rx_kill_vid, 1889df828598SMugunthan V N }; 1890df828598SMugunthan V N 189152c4f0ecSMugunthan V N static int cpsw_get_regs_len(struct net_device *ndev) 189252c4f0ecSMugunthan V N { 1893606f3993SIvan Khoronzhuk struct cpsw_common *cpsw = ndev_to_cpsw(ndev); 189452c4f0ecSMugunthan V N 1895606f3993SIvan Khoronzhuk return cpsw->data.ale_entries * ALE_ENTRY_WORDS * sizeof(u32); 189652c4f0ecSMugunthan V N } 189752c4f0ecSMugunthan V N 189852c4f0ecSMugunthan V N static void cpsw_get_regs(struct net_device *ndev, 189952c4f0ecSMugunthan V N struct ethtool_regs *regs, void *p) 190052c4f0ecSMugunthan V N { 190152c4f0ecSMugunthan V N u32 *reg = p; 19022a05a622SIvan Khoronzhuk struct cpsw_common *cpsw = ndev_to_cpsw(ndev); 190352c4f0ecSMugunthan V N 190452c4f0ecSMugunthan V N /* update CPSW IP version */ 19052a05a622SIvan Khoronzhuk regs->version = cpsw->version; 190652c4f0ecSMugunthan V N 19072a05a622SIvan Khoronzhuk cpsw_ale_dump(cpsw->ale, reg); 190852c4f0ecSMugunthan V N } 190952c4f0ecSMugunthan V N 1910df828598SMugunthan V N static void cpsw_get_drvinfo(struct net_device *ndev, 1911df828598SMugunthan V N struct ethtool_drvinfo *info) 1912df828598SMugunthan V N { 1913649a1688SIvan Khoronzhuk struct cpsw_common *cpsw = ndev_to_cpsw(ndev); 191456e31bd8SIvan Khoronzhuk struct platform_device *pdev = to_platform_device(cpsw->dev); 19157826d43fSJiri Pirko 191652c4f0ecSMugunthan V N strlcpy(info->driver, "cpsw", sizeof(info->driver)); 19177826d43fSJiri Pirko strlcpy(info->version, "1.0", sizeof(info->version)); 191856e31bd8SIvan Khoronzhuk strlcpy(info->bus_info, pdev->name, sizeof(info->bus_info)); 1919df828598SMugunthan V N } 1920df828598SMugunthan V N 1921df828598SMugunthan V N static u32 cpsw_get_msglevel(struct net_device *ndev) 1922df828598SMugunthan V N { 1923df828598SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 1924df828598SMugunthan V N return priv->msg_enable; 1925df828598SMugunthan V N } 1926df828598SMugunthan V N 1927df828598SMugunthan V N static void cpsw_set_msglevel(struct net_device *ndev, u32 value) 1928df828598SMugunthan V N { 1929df828598SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 1930df828598SMugunthan V N priv->msg_enable = value; 1931df828598SMugunthan V N } 1932df828598SMugunthan V N 19332e5b38abSRichard Cochran static int cpsw_get_ts_info(struct net_device *ndev, 19342e5b38abSRichard Cochran struct ethtool_ts_info *info) 19352e5b38abSRichard Cochran { 19362e5b38abSRichard Cochran #ifdef CONFIG_TI_CPTS 19372a05a622SIvan Khoronzhuk struct cpsw_common *cpsw = ndev_to_cpsw(ndev); 19382e5b38abSRichard Cochran 19392e5b38abSRichard Cochran info->so_timestamping = 19402e5b38abSRichard Cochran SOF_TIMESTAMPING_TX_HARDWARE | 19412e5b38abSRichard Cochran SOF_TIMESTAMPING_TX_SOFTWARE | 19422e5b38abSRichard Cochran SOF_TIMESTAMPING_RX_HARDWARE | 19432e5b38abSRichard Cochran SOF_TIMESTAMPING_RX_SOFTWARE | 19442e5b38abSRichard Cochran SOF_TIMESTAMPING_SOFTWARE | 19452e5b38abSRichard Cochran SOF_TIMESTAMPING_RAW_HARDWARE; 19462a05a622SIvan Khoronzhuk info->phc_index = cpsw->cpts->phc_index; 19472e5b38abSRichard Cochran info->tx_types = 19482e5b38abSRichard Cochran (1 << HWTSTAMP_TX_OFF) | 19492e5b38abSRichard Cochran (1 << HWTSTAMP_TX_ON); 19502e5b38abSRichard Cochran info->rx_filters = 19512e5b38abSRichard Cochran (1 << HWTSTAMP_FILTER_NONE) | 19522e5b38abSRichard Cochran (1 << HWTSTAMP_FILTER_PTP_V2_EVENT); 19532e5b38abSRichard Cochran #else 19542e5b38abSRichard Cochran info->so_timestamping = 19552e5b38abSRichard Cochran SOF_TIMESTAMPING_TX_SOFTWARE | 19562e5b38abSRichard Cochran SOF_TIMESTAMPING_RX_SOFTWARE | 19572e5b38abSRichard Cochran SOF_TIMESTAMPING_SOFTWARE; 19582e5b38abSRichard Cochran info->phc_index = -1; 19592e5b38abSRichard Cochran info->tx_types = 0; 19602e5b38abSRichard Cochran info->rx_filters = 0; 19612e5b38abSRichard Cochran #endif 19622e5b38abSRichard Cochran return 0; 19632e5b38abSRichard Cochran } 19642e5b38abSRichard Cochran 1965d3bb9c58SMugunthan V N static int cpsw_get_settings(struct net_device *ndev, 1966d3bb9c58SMugunthan V N struct ethtool_cmd *ecmd) 1967d3bb9c58SMugunthan V N { 1968d3bb9c58SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 1969606f3993SIvan Khoronzhuk struct cpsw_common *cpsw = priv->cpsw; 1970606f3993SIvan Khoronzhuk int slave_no = cpsw_slave_index(cpsw, priv); 1971d3bb9c58SMugunthan V N 1972606f3993SIvan Khoronzhuk if (cpsw->slaves[slave_no].phy) 1973606f3993SIvan Khoronzhuk return phy_ethtool_gset(cpsw->slaves[slave_no].phy, ecmd); 1974d3bb9c58SMugunthan V N else 1975d3bb9c58SMugunthan V N return -EOPNOTSUPP; 1976d3bb9c58SMugunthan V N } 1977d3bb9c58SMugunthan V N 1978d3bb9c58SMugunthan V N static int cpsw_set_settings(struct net_device *ndev, struct ethtool_cmd *ecmd) 1979d3bb9c58SMugunthan V N { 1980d3bb9c58SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 1981606f3993SIvan Khoronzhuk struct cpsw_common *cpsw = priv->cpsw; 1982606f3993SIvan Khoronzhuk int slave_no = cpsw_slave_index(cpsw, priv); 1983d3bb9c58SMugunthan V N 1984606f3993SIvan Khoronzhuk if (cpsw->slaves[slave_no].phy) 1985606f3993SIvan Khoronzhuk return phy_ethtool_sset(cpsw->slaves[slave_no].phy, ecmd); 1986d3bb9c58SMugunthan V N else 1987d3bb9c58SMugunthan V N return -EOPNOTSUPP; 1988d3bb9c58SMugunthan V N } 1989d3bb9c58SMugunthan V N 1990d8a64420SMatus Ujhelyi static void cpsw_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol) 1991d8a64420SMatus Ujhelyi { 1992d8a64420SMatus Ujhelyi struct cpsw_priv *priv = netdev_priv(ndev); 1993606f3993SIvan Khoronzhuk struct cpsw_common *cpsw = priv->cpsw; 1994606f3993SIvan Khoronzhuk int slave_no = cpsw_slave_index(cpsw, priv); 1995d8a64420SMatus Ujhelyi 1996d8a64420SMatus Ujhelyi wol->supported = 0; 1997d8a64420SMatus Ujhelyi wol->wolopts = 0; 1998d8a64420SMatus Ujhelyi 1999606f3993SIvan Khoronzhuk if (cpsw->slaves[slave_no].phy) 2000606f3993SIvan Khoronzhuk phy_ethtool_get_wol(cpsw->slaves[slave_no].phy, wol); 2001d8a64420SMatus Ujhelyi } 2002d8a64420SMatus Ujhelyi 2003d8a64420SMatus Ujhelyi static int cpsw_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol) 2004d8a64420SMatus Ujhelyi { 2005d8a64420SMatus Ujhelyi struct cpsw_priv *priv = netdev_priv(ndev); 2006606f3993SIvan Khoronzhuk struct cpsw_common *cpsw = priv->cpsw; 2007606f3993SIvan Khoronzhuk int slave_no = cpsw_slave_index(cpsw, priv); 2008d8a64420SMatus Ujhelyi 2009606f3993SIvan Khoronzhuk if (cpsw->slaves[slave_no].phy) 2010606f3993SIvan Khoronzhuk return phy_ethtool_set_wol(cpsw->slaves[slave_no].phy, wol); 2011d8a64420SMatus Ujhelyi else 2012d8a64420SMatus Ujhelyi return -EOPNOTSUPP; 2013d8a64420SMatus Ujhelyi } 2014d8a64420SMatus Ujhelyi 20151923d6e4SMugunthan V N static void cpsw_get_pauseparam(struct net_device *ndev, 20161923d6e4SMugunthan V N struct ethtool_pauseparam *pause) 20171923d6e4SMugunthan V N { 20181923d6e4SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 20191923d6e4SMugunthan V N 20201923d6e4SMugunthan V N pause->autoneg = AUTONEG_DISABLE; 20211923d6e4SMugunthan V N pause->rx_pause = priv->rx_pause ? true : false; 20221923d6e4SMugunthan V N pause->tx_pause = priv->tx_pause ? true : false; 20231923d6e4SMugunthan V N } 20241923d6e4SMugunthan V N 20251923d6e4SMugunthan V N static int cpsw_set_pauseparam(struct net_device *ndev, 20261923d6e4SMugunthan V N struct ethtool_pauseparam *pause) 20271923d6e4SMugunthan V N { 20281923d6e4SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 20291923d6e4SMugunthan V N bool link; 20301923d6e4SMugunthan V N 20311923d6e4SMugunthan V N priv->rx_pause = pause->rx_pause ? true : false; 20321923d6e4SMugunthan V N priv->tx_pause = pause->tx_pause ? true : false; 20331923d6e4SMugunthan V N 20341923d6e4SMugunthan V N for_each_slave(priv, _cpsw_adjust_link, priv, &link); 20351923d6e4SMugunthan V N return 0; 20361923d6e4SMugunthan V N } 20371923d6e4SMugunthan V N 20387898b1daSGrygorii Strashko static int cpsw_ethtool_op_begin(struct net_device *ndev) 20397898b1daSGrygorii Strashko { 20407898b1daSGrygorii Strashko struct cpsw_priv *priv = netdev_priv(ndev); 2041649a1688SIvan Khoronzhuk struct cpsw_common *cpsw = priv->cpsw; 20427898b1daSGrygorii Strashko int ret; 20437898b1daSGrygorii Strashko 204456e31bd8SIvan Khoronzhuk ret = pm_runtime_get_sync(cpsw->dev); 20457898b1daSGrygorii Strashko if (ret < 0) { 20467898b1daSGrygorii Strashko cpsw_err(priv, drv, "ethtool begin failed %d\n", ret); 204756e31bd8SIvan Khoronzhuk pm_runtime_put_noidle(cpsw->dev); 20487898b1daSGrygorii Strashko } 20497898b1daSGrygorii Strashko 20507898b1daSGrygorii Strashko return ret; 20517898b1daSGrygorii Strashko } 20527898b1daSGrygorii Strashko 20537898b1daSGrygorii Strashko static void cpsw_ethtool_op_complete(struct net_device *ndev) 20547898b1daSGrygorii Strashko { 20557898b1daSGrygorii Strashko struct cpsw_priv *priv = netdev_priv(ndev); 20567898b1daSGrygorii Strashko int ret; 20577898b1daSGrygorii Strashko 205856e31bd8SIvan Khoronzhuk ret = pm_runtime_put(priv->cpsw->dev); 20597898b1daSGrygorii Strashko if (ret < 0) 20607898b1daSGrygorii Strashko cpsw_err(priv, drv, "ethtool complete failed %d\n", ret); 20617898b1daSGrygorii Strashko } 20627898b1daSGrygorii Strashko 2063df828598SMugunthan V N static const struct ethtool_ops cpsw_ethtool_ops = { 2064df828598SMugunthan V N .get_drvinfo = cpsw_get_drvinfo, 2065df828598SMugunthan V N .get_msglevel = cpsw_get_msglevel, 2066df828598SMugunthan V N .set_msglevel = cpsw_set_msglevel, 2067df828598SMugunthan V N .get_link = ethtool_op_get_link, 20682e5b38abSRichard Cochran .get_ts_info = cpsw_get_ts_info, 2069d3bb9c58SMugunthan V N .get_settings = cpsw_get_settings, 2070d3bb9c58SMugunthan V N .set_settings = cpsw_set_settings, 2071ff5b8ef2SMugunthan V N .get_coalesce = cpsw_get_coalesce, 2072ff5b8ef2SMugunthan V N .set_coalesce = cpsw_set_coalesce, 2073d9718546SMugunthan V N .get_sset_count = cpsw_get_sset_count, 2074d9718546SMugunthan V N .get_strings = cpsw_get_strings, 2075d9718546SMugunthan V N .get_ethtool_stats = cpsw_get_ethtool_stats, 20761923d6e4SMugunthan V N .get_pauseparam = cpsw_get_pauseparam, 20771923d6e4SMugunthan V N .set_pauseparam = cpsw_set_pauseparam, 2078d8a64420SMatus Ujhelyi .get_wol = cpsw_get_wol, 2079d8a64420SMatus Ujhelyi .set_wol = cpsw_set_wol, 208052c4f0ecSMugunthan V N .get_regs_len = cpsw_get_regs_len, 208152c4f0ecSMugunthan V N .get_regs = cpsw_get_regs, 20827898b1daSGrygorii Strashko .begin = cpsw_ethtool_op_begin, 20837898b1daSGrygorii Strashko .complete = cpsw_ethtool_op_complete, 2084df828598SMugunthan V N }; 2085df828598SMugunthan V N 2086606f3993SIvan Khoronzhuk static void cpsw_slave_init(struct cpsw_slave *slave, struct cpsw_common *cpsw, 2087549985eeSRichard Cochran u32 slave_reg_ofs, u32 sliver_reg_ofs) 2088df828598SMugunthan V N { 20895d8d0d4dSIvan Khoronzhuk void __iomem *regs = cpsw->regs; 2090df828598SMugunthan V N int slave_num = slave->slave_num; 2091606f3993SIvan Khoronzhuk struct cpsw_slave_data *data = cpsw->data.slave_data + slave_num; 2092df828598SMugunthan V N 2093df828598SMugunthan V N slave->data = data; 2094549985eeSRichard Cochran slave->regs = regs + slave_reg_ofs; 2095549985eeSRichard Cochran slave->sliver = regs + sliver_reg_ofs; 2096d9ba8f9eSMugunthan V N slave->port_vlan = data->dual_emac_res_vlan; 2097df828598SMugunthan V N } 2098df828598SMugunthan V N 2099552165bcSDavid Rivshin static int cpsw_probe_dt(struct cpsw_platform_data *data, 21002eb32b0aSMugunthan V N struct platform_device *pdev) 21012eb32b0aSMugunthan V N { 21022eb32b0aSMugunthan V N struct device_node *node = pdev->dev.of_node; 21032eb32b0aSMugunthan V N struct device_node *slave_node; 21042eb32b0aSMugunthan V N int i = 0, ret; 21052eb32b0aSMugunthan V N u32 prop; 21062eb32b0aSMugunthan V N 21072eb32b0aSMugunthan V N if (!node) 21082eb32b0aSMugunthan V N return -EINVAL; 21092eb32b0aSMugunthan V N 21102eb32b0aSMugunthan V N if (of_property_read_u32(node, "slaves", &prop)) { 211188c99ff6SGeorge Cherian dev_err(&pdev->dev, "Missing slaves property in the DT.\n"); 21122eb32b0aSMugunthan V N return -EINVAL; 21132eb32b0aSMugunthan V N } 21142eb32b0aSMugunthan V N data->slaves = prop; 21152eb32b0aSMugunthan V N 2116e86ac13bSMugunthan V N if (of_property_read_u32(node, "active_slave", &prop)) { 211788c99ff6SGeorge Cherian dev_err(&pdev->dev, "Missing active_slave property in the DT.\n"); 2118aa1a15e2SDaniel Mack return -EINVAL; 211978ca0b28SRichard Cochran } 2120e86ac13bSMugunthan V N data->active_slave = prop; 212178ca0b28SRichard Cochran 212200ab94eeSRichard Cochran if (of_property_read_u32(node, "cpts_clock_mult", &prop)) { 212388c99ff6SGeorge Cherian dev_err(&pdev->dev, "Missing cpts_clock_mult property in the DT.\n"); 2124aa1a15e2SDaniel Mack return -EINVAL; 212500ab94eeSRichard Cochran } 212600ab94eeSRichard Cochran data->cpts_clock_mult = prop; 212700ab94eeSRichard Cochran 212800ab94eeSRichard Cochran if (of_property_read_u32(node, "cpts_clock_shift", &prop)) { 212988c99ff6SGeorge Cherian dev_err(&pdev->dev, "Missing cpts_clock_shift property in the DT.\n"); 2130aa1a15e2SDaniel Mack return -EINVAL; 213100ab94eeSRichard Cochran } 213200ab94eeSRichard Cochran data->cpts_clock_shift = prop; 213300ab94eeSRichard Cochran 2134aa1a15e2SDaniel Mack data->slave_data = devm_kzalloc(&pdev->dev, data->slaves 2135aa1a15e2SDaniel Mack * sizeof(struct cpsw_slave_data), 2136b2adaca9SJoe Perches GFP_KERNEL); 2137b2adaca9SJoe Perches if (!data->slave_data) 2138aa1a15e2SDaniel Mack return -ENOMEM; 21392eb32b0aSMugunthan V N 21402eb32b0aSMugunthan V N if (of_property_read_u32(node, "cpdma_channels", &prop)) { 214188c99ff6SGeorge Cherian dev_err(&pdev->dev, "Missing cpdma_channels property in the DT.\n"); 2142aa1a15e2SDaniel Mack return -EINVAL; 21432eb32b0aSMugunthan V N } 21442eb32b0aSMugunthan V N data->channels = prop; 21452eb32b0aSMugunthan V N 21462eb32b0aSMugunthan V N if (of_property_read_u32(node, "ale_entries", &prop)) { 214788c99ff6SGeorge Cherian dev_err(&pdev->dev, "Missing ale_entries property in the DT.\n"); 2148aa1a15e2SDaniel Mack return -EINVAL; 21492eb32b0aSMugunthan V N } 21502eb32b0aSMugunthan V N data->ale_entries = prop; 21512eb32b0aSMugunthan V N 21522eb32b0aSMugunthan V N if (of_property_read_u32(node, "bd_ram_size", &prop)) { 215388c99ff6SGeorge Cherian dev_err(&pdev->dev, "Missing bd_ram_size property in the DT.\n"); 2154aa1a15e2SDaniel Mack return -EINVAL; 21552eb32b0aSMugunthan V N } 21562eb32b0aSMugunthan V N data->bd_ram_size = prop; 21572eb32b0aSMugunthan V N 21582eb32b0aSMugunthan V N if (of_property_read_u32(node, "mac_control", &prop)) { 215988c99ff6SGeorge Cherian dev_err(&pdev->dev, "Missing mac_control property in the DT.\n"); 2160aa1a15e2SDaniel Mack return -EINVAL; 21612eb32b0aSMugunthan V N } 21622eb32b0aSMugunthan V N data->mac_control = prop; 21632eb32b0aSMugunthan V N 2164281abd96SMarkus Pargmann if (of_property_read_bool(node, "dual_emac")) 2165281abd96SMarkus Pargmann data->dual_emac = 1; 2166d9ba8f9eSMugunthan V N 21671fb19aa7SVaibhav Hiremath /* 21681fb19aa7SVaibhav Hiremath * Populate all the child nodes here... 21691fb19aa7SVaibhav Hiremath */ 21701fb19aa7SVaibhav Hiremath ret = of_platform_populate(node, NULL, NULL, &pdev->dev); 21711fb19aa7SVaibhav Hiremath /* We do not want to force this, as in some cases may not have child */ 21721fb19aa7SVaibhav Hiremath if (ret) 217388c99ff6SGeorge Cherian dev_warn(&pdev->dev, "Doesn't have any child node\n"); 21741fb19aa7SVaibhav Hiremath 21758658aaf2SBen Hutchings for_each_available_child_of_node(node, slave_node) { 2176549985eeSRichard Cochran struct cpsw_slave_data *slave_data = data->slave_data + i; 2177549985eeSRichard Cochran const void *mac_addr = NULL; 2178549985eeSRichard Cochran int lenp; 2179549985eeSRichard Cochran const __be32 *parp; 2180549985eeSRichard Cochran 2181f468b10eSMarkus Pargmann /* This is no slave child node, continue */ 2182f468b10eSMarkus Pargmann if (strcmp(slave_node->name, "slave")) 2183f468b10eSMarkus Pargmann continue; 2184f468b10eSMarkus Pargmann 2185552165bcSDavid Rivshin slave_data->phy_node = of_parse_phandle(slave_node, 2186552165bcSDavid Rivshin "phy-handle", 0); 2187f1eea5c1SDavid Rivshin parp = of_get_property(slave_node, "phy_id", &lenp); 2188ae092b5bSDavid Rivshin if (slave_data->phy_node) { 2189ae092b5bSDavid Rivshin dev_dbg(&pdev->dev, 2190ae092b5bSDavid Rivshin "slave[%d] using phy-handle=\"%s\"\n", 2191ae092b5bSDavid Rivshin i, slave_data->phy_node->full_name); 2192ae092b5bSDavid Rivshin } else if (of_phy_is_fixed_link(slave_node)) { 2193dfc0a6d3SDavid Rivshin /* In the case of a fixed PHY, the DT node associated 2194dfc0a6d3SDavid Rivshin * to the PHY is the Ethernet MAC DT node. 2195dfc0a6d3SDavid Rivshin */ 21961f71e8c9SMarkus Brunner ret = of_phy_register_fixed_link(slave_node); 21971f71e8c9SMarkus Brunner if (ret) 21981f71e8c9SMarkus Brunner return ret; 219906cd6d6eSDavid Rivshin slave_data->phy_node = of_node_get(slave_node); 2200f1eea5c1SDavid Rivshin } else if (parp) { 2201f1eea5c1SDavid Rivshin u32 phyid; 2202f1eea5c1SDavid Rivshin struct device_node *mdio_node; 2203f1eea5c1SDavid Rivshin struct platform_device *mdio; 2204f1eea5c1SDavid Rivshin 2205f1eea5c1SDavid Rivshin if (lenp != (sizeof(__be32) * 2)) { 2206f1eea5c1SDavid Rivshin dev_err(&pdev->dev, "Invalid slave[%d] phy_id property\n", i); 220747276fccSMugunthan V N goto no_phy_slave; 2208549985eeSRichard Cochran } 2209549985eeSRichard Cochran mdio_node = of_find_node_by_phandle(be32_to_cpup(parp)); 2210549985eeSRichard Cochran phyid = be32_to_cpup(parp+1); 2211549985eeSRichard Cochran mdio = of_find_device_by_node(mdio_node); 221260e71ab5SJohan Hovold of_node_put(mdio_node); 22136954cc1fSJohan Hovold if (!mdio) { 221456fdb2e0SMarkus Pargmann dev_err(&pdev->dev, "Missing mdio platform device\n"); 22156954cc1fSJohan Hovold return -EINVAL; 22166954cc1fSJohan Hovold } 2217549985eeSRichard Cochran snprintf(slave_data->phy_id, sizeof(slave_data->phy_id), 2218549985eeSRichard Cochran PHY_ID_FMT, mdio->name, phyid); 2219f1eea5c1SDavid Rivshin } else { 2220ae092b5bSDavid Rivshin dev_err(&pdev->dev, 2221ae092b5bSDavid Rivshin "No slave[%d] phy_id, phy-handle, or fixed-link property\n", 2222ae092b5bSDavid Rivshin i); 2223f1eea5c1SDavid Rivshin goto no_phy_slave; 2224f1eea5c1SDavid Rivshin } 222547276fccSMugunthan V N slave_data->phy_if = of_get_phy_mode(slave_node); 222647276fccSMugunthan V N if (slave_data->phy_if < 0) { 222747276fccSMugunthan V N dev_err(&pdev->dev, "Missing or malformed slave[%d] phy-mode property\n", 222847276fccSMugunthan V N i); 222947276fccSMugunthan V N return slave_data->phy_if; 223047276fccSMugunthan V N } 223147276fccSMugunthan V N 223247276fccSMugunthan V N no_phy_slave: 2233549985eeSRichard Cochran mac_addr = of_get_mac_address(slave_node); 22340ba517b1SMarkus Pargmann if (mac_addr) { 2235549985eeSRichard Cochran memcpy(slave_data->mac_addr, mac_addr, ETH_ALEN); 22360ba517b1SMarkus Pargmann } else { 2237b6745f6eSMugunthan V N ret = ti_cm_get_macid(&pdev->dev, i, 22380ba517b1SMarkus Pargmann slave_data->mac_addr); 22390ba517b1SMarkus Pargmann if (ret) 22400ba517b1SMarkus Pargmann return ret; 22410ba517b1SMarkus Pargmann } 2242d9ba8f9eSMugunthan V N if (data->dual_emac) { 224391c4166cSMugunthan V N if (of_property_read_u32(slave_node, "dual_emac_res_vlan", 2244d9ba8f9eSMugunthan V N &prop)) { 224588c99ff6SGeorge Cherian dev_err(&pdev->dev, "Missing dual_emac_res_vlan in DT.\n"); 2246d9ba8f9eSMugunthan V N slave_data->dual_emac_res_vlan = i+1; 224788c99ff6SGeorge Cherian dev_err(&pdev->dev, "Using %d as Reserved VLAN for %d slave\n", 2248d9ba8f9eSMugunthan V N slave_data->dual_emac_res_vlan, i); 2249d9ba8f9eSMugunthan V N } else { 2250d9ba8f9eSMugunthan V N slave_data->dual_emac_res_vlan = prop; 2251d9ba8f9eSMugunthan V N } 2252d9ba8f9eSMugunthan V N } 2253d9ba8f9eSMugunthan V N 2254549985eeSRichard Cochran i++; 22553a27bfacSMugunthan V N if (i == data->slaves) 22563a27bfacSMugunthan V N break; 2257549985eeSRichard Cochran } 2258549985eeSRichard Cochran 22592eb32b0aSMugunthan V N return 0; 22602eb32b0aSMugunthan V N } 22612eb32b0aSMugunthan V N 226256e31bd8SIvan Khoronzhuk static int cpsw_probe_dual_emac(struct cpsw_priv *priv) 2263d9ba8f9eSMugunthan V N { 2264606f3993SIvan Khoronzhuk struct cpsw_common *cpsw = priv->cpsw; 2265606f3993SIvan Khoronzhuk struct cpsw_platform_data *data = &cpsw->data; 2266d9ba8f9eSMugunthan V N struct net_device *ndev; 2267d9ba8f9eSMugunthan V N struct cpsw_priv *priv_sl2; 2268e38b5a3dSIvan Khoronzhuk int ret = 0; 2269d9ba8f9eSMugunthan V N 2270e05107e6SIvan Khoronzhuk ndev = alloc_etherdev_mq(sizeof(struct cpsw_priv), CPSW_MAX_QUEUES); 2271d9ba8f9eSMugunthan V N if (!ndev) { 227256e31bd8SIvan Khoronzhuk dev_err(cpsw->dev, "cpsw: error allocating net_device\n"); 2273d9ba8f9eSMugunthan V N return -ENOMEM; 2274d9ba8f9eSMugunthan V N } 2275d9ba8f9eSMugunthan V N 2276d9ba8f9eSMugunthan V N priv_sl2 = netdev_priv(ndev); 2277606f3993SIvan Khoronzhuk priv_sl2->cpsw = cpsw; 2278d9ba8f9eSMugunthan V N priv_sl2->ndev = ndev; 2279d9ba8f9eSMugunthan V N priv_sl2->dev = &ndev->dev; 2280d9ba8f9eSMugunthan V N priv_sl2->msg_enable = netif_msg_init(debug_level, CPSW_DEBUG); 2281d9ba8f9eSMugunthan V N 2282d9ba8f9eSMugunthan V N if (is_valid_ether_addr(data->slave_data[1].mac_addr)) { 2283d9ba8f9eSMugunthan V N memcpy(priv_sl2->mac_addr, data->slave_data[1].mac_addr, 2284d9ba8f9eSMugunthan V N ETH_ALEN); 228556e31bd8SIvan Khoronzhuk dev_info(cpsw->dev, "cpsw: Detected MACID = %pM\n", 228656e31bd8SIvan Khoronzhuk priv_sl2->mac_addr); 2287d9ba8f9eSMugunthan V N } else { 2288d9ba8f9eSMugunthan V N random_ether_addr(priv_sl2->mac_addr); 228956e31bd8SIvan Khoronzhuk dev_info(cpsw->dev, "cpsw: Random MACID = %pM\n", 229056e31bd8SIvan Khoronzhuk priv_sl2->mac_addr); 2291d9ba8f9eSMugunthan V N } 2292d9ba8f9eSMugunthan V N memcpy(ndev->dev_addr, priv_sl2->mac_addr, ETH_ALEN); 2293d9ba8f9eSMugunthan V N 2294d9ba8f9eSMugunthan V N priv_sl2->emac_port = 1; 2295606f3993SIvan Khoronzhuk cpsw->slaves[1].ndev = ndev; 2296f646968fSPatrick McHardy ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER; 2297d9ba8f9eSMugunthan V N 2298d9ba8f9eSMugunthan V N ndev->netdev_ops = &cpsw_netdev_ops; 22997ad24ea4SWilfried Klaebe ndev->ethtool_ops = &cpsw_ethtool_ops; 2300d9ba8f9eSMugunthan V N 2301d9ba8f9eSMugunthan V N /* register the network device */ 230256e31bd8SIvan Khoronzhuk SET_NETDEV_DEV(ndev, cpsw->dev); 2303d9ba8f9eSMugunthan V N ret = register_netdev(ndev); 2304d9ba8f9eSMugunthan V N if (ret) { 230556e31bd8SIvan Khoronzhuk dev_err(cpsw->dev, "cpsw: error registering net device\n"); 2306d9ba8f9eSMugunthan V N free_netdev(ndev); 2307d9ba8f9eSMugunthan V N ret = -ENODEV; 2308d9ba8f9eSMugunthan V N } 2309d9ba8f9eSMugunthan V N 2310d9ba8f9eSMugunthan V N return ret; 2311d9ba8f9eSMugunthan V N } 2312d9ba8f9eSMugunthan V N 23137da11600SMugunthan V N #define CPSW_QUIRK_IRQ BIT(0) 23147da11600SMugunthan V N 23157da11600SMugunthan V N static struct platform_device_id cpsw_devtype[] = { 23167da11600SMugunthan V N { 23177da11600SMugunthan V N /* keep it for existing comaptibles */ 23187da11600SMugunthan V N .name = "cpsw", 23197da11600SMugunthan V N .driver_data = CPSW_QUIRK_IRQ, 23207da11600SMugunthan V N }, { 23217da11600SMugunthan V N .name = "am335x-cpsw", 23227da11600SMugunthan V N .driver_data = CPSW_QUIRK_IRQ, 23237da11600SMugunthan V N }, { 23247da11600SMugunthan V N .name = "am4372-cpsw", 23257da11600SMugunthan V N .driver_data = 0, 23267da11600SMugunthan V N }, { 23277da11600SMugunthan V N .name = "dra7-cpsw", 23287da11600SMugunthan V N .driver_data = 0, 23297da11600SMugunthan V N }, { 23307da11600SMugunthan V N /* sentinel */ 23317da11600SMugunthan V N } 23327da11600SMugunthan V N }; 23337da11600SMugunthan V N MODULE_DEVICE_TABLE(platform, cpsw_devtype); 23347da11600SMugunthan V N 23357da11600SMugunthan V N enum ti_cpsw_type { 23367da11600SMugunthan V N CPSW = 0, 23377da11600SMugunthan V N AM335X_CPSW, 23387da11600SMugunthan V N AM4372_CPSW, 23397da11600SMugunthan V N DRA7_CPSW, 23407da11600SMugunthan V N }; 23417da11600SMugunthan V N 23427da11600SMugunthan V N static const struct of_device_id cpsw_of_mtable[] = { 23437da11600SMugunthan V N { .compatible = "ti,cpsw", .data = &cpsw_devtype[CPSW], }, 23447da11600SMugunthan V N { .compatible = "ti,am335x-cpsw", .data = &cpsw_devtype[AM335X_CPSW], }, 23457da11600SMugunthan V N { .compatible = "ti,am4372-cpsw", .data = &cpsw_devtype[AM4372_CPSW], }, 23467da11600SMugunthan V N { .compatible = "ti,dra7-cpsw", .data = &cpsw_devtype[DRA7_CPSW], }, 23477da11600SMugunthan V N { /* sentinel */ }, 23487da11600SMugunthan V N }; 23497da11600SMugunthan V N MODULE_DEVICE_TABLE(of, cpsw_of_mtable); 23507da11600SMugunthan V N 2351663e12e6SBill Pemberton static int cpsw_probe(struct platform_device *pdev) 2352df828598SMugunthan V N { 2353ef4183a1SIvan Khoronzhuk struct clk *clk; 2354d1bd9acfSSebastian Siewior struct cpsw_platform_data *data; 2355df828598SMugunthan V N struct net_device *ndev; 2356df828598SMugunthan V N struct cpsw_priv *priv; 2357df828598SMugunthan V N struct cpdma_params dma_params; 2358df828598SMugunthan V N struct cpsw_ale_params ale_params; 2359aa1a15e2SDaniel Mack void __iomem *ss_regs; 2360aa1a15e2SDaniel Mack struct resource *res, *ss_res; 23617da11600SMugunthan V N const struct of_device_id *of_id; 23621d147ccbSMugunthan V N struct gpio_descs *mode; 2363549985eeSRichard Cochran u32 slave_offset, sliver_offset, slave_size; 2364649a1688SIvan Khoronzhuk struct cpsw_common *cpsw; 23655087b915SFelipe Balbi int ret = 0, i; 23665087b915SFelipe Balbi int irq; 2367df828598SMugunthan V N 2368649a1688SIvan Khoronzhuk cpsw = devm_kzalloc(&pdev->dev, sizeof(struct cpsw_common), GFP_KERNEL); 236956e31bd8SIvan Khoronzhuk cpsw->dev = &pdev->dev; 2370649a1688SIvan Khoronzhuk 2371e05107e6SIvan Khoronzhuk ndev = alloc_etherdev_mq(sizeof(struct cpsw_priv), CPSW_MAX_QUEUES); 2372df828598SMugunthan V N if (!ndev) { 237388c99ff6SGeorge Cherian dev_err(&pdev->dev, "error allocating net_device\n"); 2374df828598SMugunthan V N return -ENOMEM; 2375df828598SMugunthan V N } 2376df828598SMugunthan V N 2377df828598SMugunthan V N platform_set_drvdata(pdev, ndev); 2378df828598SMugunthan V N priv = netdev_priv(ndev); 2379649a1688SIvan Khoronzhuk priv->cpsw = cpsw; 2380df828598SMugunthan V N priv->ndev = ndev; 2381df828598SMugunthan V N priv->dev = &ndev->dev; 2382df828598SMugunthan V N priv->msg_enable = netif_msg_init(debug_level, CPSW_DEBUG); 23832a05a622SIvan Khoronzhuk cpsw->rx_packet_max = max(rx_packet_max, 128); 23842a05a622SIvan Khoronzhuk cpsw->cpts = devm_kzalloc(&pdev->dev, sizeof(struct cpts), GFP_KERNEL); 23852a05a622SIvan Khoronzhuk if (!cpsw->cpts) { 238688c99ff6SGeorge Cherian dev_err(&pdev->dev, "error allocating cpts\n"); 23874d507dffSMarkus Pargmann ret = -ENOMEM; 23889232b16dSMugunthan V N goto clean_ndev_ret; 23899232b16dSMugunthan V N } 2390df828598SMugunthan V N 23911d147ccbSMugunthan V N mode = devm_gpiod_get_array_optional(&pdev->dev, "mode", GPIOD_OUT_LOW); 23921d147ccbSMugunthan V N if (IS_ERR(mode)) { 23931d147ccbSMugunthan V N ret = PTR_ERR(mode); 23941d147ccbSMugunthan V N dev_err(&pdev->dev, "gpio request failed, ret %d\n", ret); 23951d147ccbSMugunthan V N goto clean_ndev_ret; 23961d147ccbSMugunthan V N } 23971d147ccbSMugunthan V N 23981fb19aa7SVaibhav Hiremath /* 23991fb19aa7SVaibhav Hiremath * This may be required here for child devices. 24001fb19aa7SVaibhav Hiremath */ 24011fb19aa7SVaibhav Hiremath pm_runtime_enable(&pdev->dev); 24021fb19aa7SVaibhav Hiremath 2403739683b4SMugunthan V N /* Select default pin state */ 2404739683b4SMugunthan V N pinctrl_pm_select_default_state(&pdev->dev); 2405739683b4SMugunthan V N 2406606f3993SIvan Khoronzhuk if (cpsw_probe_dt(&cpsw->data, pdev)) { 240788c99ff6SGeorge Cherian dev_err(&pdev->dev, "cpsw: platform data missing\n"); 24082eb32b0aSMugunthan V N ret = -ENODEV; 2409aa1a15e2SDaniel Mack goto clean_runtime_disable_ret; 24102eb32b0aSMugunthan V N } 2411606f3993SIvan Khoronzhuk data = &cpsw->data; 2412e05107e6SIvan Khoronzhuk cpsw->rx_ch_num = 1; 2413e05107e6SIvan Khoronzhuk cpsw->tx_ch_num = 1; 24142eb32b0aSMugunthan V N 2415df828598SMugunthan V N if (is_valid_ether_addr(data->slave_data[0].mac_addr)) { 2416df828598SMugunthan V N memcpy(priv->mac_addr, data->slave_data[0].mac_addr, ETH_ALEN); 241788c99ff6SGeorge Cherian dev_info(&pdev->dev, "Detected MACID = %pM\n", priv->mac_addr); 2418df828598SMugunthan V N } else { 24197efd26d0SJoe Perches eth_random_addr(priv->mac_addr); 242088c99ff6SGeorge Cherian dev_info(&pdev->dev, "Random MACID = %pM\n", priv->mac_addr); 2421df828598SMugunthan V N } 2422df828598SMugunthan V N 2423df828598SMugunthan V N memcpy(ndev->dev_addr, priv->mac_addr, ETH_ALEN); 2424df828598SMugunthan V N 2425606f3993SIvan Khoronzhuk cpsw->slaves = devm_kzalloc(&pdev->dev, 2426aa1a15e2SDaniel Mack sizeof(struct cpsw_slave) * data->slaves, 2427df828598SMugunthan V N GFP_KERNEL); 2428606f3993SIvan Khoronzhuk if (!cpsw->slaves) { 2429aa1a15e2SDaniel Mack ret = -ENOMEM; 2430aa1a15e2SDaniel Mack goto clean_runtime_disable_ret; 2431df828598SMugunthan V N } 2432df828598SMugunthan V N for (i = 0; i < data->slaves; i++) 2433606f3993SIvan Khoronzhuk cpsw->slaves[i].slave_num = i; 2434df828598SMugunthan V N 2435606f3993SIvan Khoronzhuk cpsw->slaves[0].ndev = ndev; 2436d9ba8f9eSMugunthan V N priv->emac_port = 0; 2437d9ba8f9eSMugunthan V N 2438ef4183a1SIvan Khoronzhuk clk = devm_clk_get(&pdev->dev, "fck"); 2439ef4183a1SIvan Khoronzhuk if (IS_ERR(clk)) { 2440aa1a15e2SDaniel Mack dev_err(priv->dev, "fck is not found\n"); 2441f150bd7fSMugunthan V N ret = -ENODEV; 2442aa1a15e2SDaniel Mack goto clean_runtime_disable_ret; 2443df828598SMugunthan V N } 24442a05a622SIvan Khoronzhuk cpsw->bus_freq_mhz = clk_get_rate(clk) / 1000000; 2445df828598SMugunthan V N 2446aa1a15e2SDaniel Mack ss_res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2447aa1a15e2SDaniel Mack ss_regs = devm_ioremap_resource(&pdev->dev, ss_res); 2448aa1a15e2SDaniel Mack if (IS_ERR(ss_regs)) { 2449aa1a15e2SDaniel Mack ret = PTR_ERR(ss_regs); 2450aa1a15e2SDaniel Mack goto clean_runtime_disable_ret; 2451df828598SMugunthan V N } 24525d8d0d4dSIvan Khoronzhuk cpsw->regs = ss_regs; 2453df828598SMugunthan V N 2454f280e89aSMugunthan V N /* Need to enable clocks with runtime PM api to access module 2455f280e89aSMugunthan V N * registers 2456f280e89aSMugunthan V N */ 2457108a6537SGrygorii Strashko ret = pm_runtime_get_sync(&pdev->dev); 2458108a6537SGrygorii Strashko if (ret < 0) { 2459108a6537SGrygorii Strashko pm_runtime_put_noidle(&pdev->dev); 2460108a6537SGrygorii Strashko goto clean_runtime_disable_ret; 2461108a6537SGrygorii Strashko } 24622a05a622SIvan Khoronzhuk cpsw->version = readl(&cpsw->regs->id_ver); 2463f280e89aSMugunthan V N pm_runtime_put_sync(&pdev->dev); 2464f280e89aSMugunthan V N 2465aa1a15e2SDaniel Mack res = platform_get_resource(pdev, IORESOURCE_MEM, 1); 24665d8d0d4dSIvan Khoronzhuk cpsw->wr_regs = devm_ioremap_resource(&pdev->dev, res); 24675d8d0d4dSIvan Khoronzhuk if (IS_ERR(cpsw->wr_regs)) { 24685d8d0d4dSIvan Khoronzhuk ret = PTR_ERR(cpsw->wr_regs); 2469aa1a15e2SDaniel Mack goto clean_runtime_disable_ret; 2470df828598SMugunthan V N } 2471df828598SMugunthan V N 2472df828598SMugunthan V N memset(&dma_params, 0, sizeof(dma_params)); 2473549985eeSRichard Cochran memset(&ale_params, 0, sizeof(ale_params)); 2474549985eeSRichard Cochran 24752a05a622SIvan Khoronzhuk switch (cpsw->version) { 2476549985eeSRichard Cochran case CPSW_VERSION_1: 24775d8d0d4dSIvan Khoronzhuk cpsw->host_port_regs = ss_regs + CPSW1_HOST_PORT_OFFSET; 24782a05a622SIvan Khoronzhuk cpsw->cpts->reg = ss_regs + CPSW1_CPTS_OFFSET; 24795d8d0d4dSIvan Khoronzhuk cpsw->hw_stats = ss_regs + CPSW1_HW_STATS; 2480549985eeSRichard Cochran dma_params.dmaregs = ss_regs + CPSW1_CPDMA_OFFSET; 2481549985eeSRichard Cochran dma_params.txhdp = ss_regs + CPSW1_STATERAM_OFFSET; 2482549985eeSRichard Cochran ale_params.ale_regs = ss_regs + CPSW1_ALE_OFFSET; 2483549985eeSRichard Cochran slave_offset = CPSW1_SLAVE_OFFSET; 2484549985eeSRichard Cochran slave_size = CPSW1_SLAVE_SIZE; 2485549985eeSRichard Cochran sliver_offset = CPSW1_SLIVER_OFFSET; 2486549985eeSRichard Cochran dma_params.desc_mem_phys = 0; 2487549985eeSRichard Cochran break; 2488549985eeSRichard Cochran case CPSW_VERSION_2: 2489c193f365SMugunthan V N case CPSW_VERSION_3: 2490926489beSMugunthan V N case CPSW_VERSION_4: 24915d8d0d4dSIvan Khoronzhuk cpsw->host_port_regs = ss_regs + CPSW2_HOST_PORT_OFFSET; 24922a05a622SIvan Khoronzhuk cpsw->cpts->reg = ss_regs + CPSW2_CPTS_OFFSET; 24935d8d0d4dSIvan Khoronzhuk cpsw->hw_stats = ss_regs + CPSW2_HW_STATS; 2494549985eeSRichard Cochran dma_params.dmaregs = ss_regs + CPSW2_CPDMA_OFFSET; 2495549985eeSRichard Cochran dma_params.txhdp = ss_regs + CPSW2_STATERAM_OFFSET; 2496549985eeSRichard Cochran ale_params.ale_regs = ss_regs + CPSW2_ALE_OFFSET; 2497549985eeSRichard Cochran slave_offset = CPSW2_SLAVE_OFFSET; 2498549985eeSRichard Cochran slave_size = CPSW2_SLAVE_SIZE; 2499549985eeSRichard Cochran sliver_offset = CPSW2_SLIVER_OFFSET; 2500549985eeSRichard Cochran dma_params.desc_mem_phys = 2501aa1a15e2SDaniel Mack (u32 __force) ss_res->start + CPSW2_BD_OFFSET; 2502549985eeSRichard Cochran break; 2503549985eeSRichard Cochran default: 25042a05a622SIvan Khoronzhuk dev_err(priv->dev, "unknown version 0x%08x\n", cpsw->version); 2505549985eeSRichard Cochran ret = -ENODEV; 2506aa1a15e2SDaniel Mack goto clean_runtime_disable_ret; 2507549985eeSRichard Cochran } 2508606f3993SIvan Khoronzhuk for (i = 0; i < cpsw->data.slaves; i++) { 2509606f3993SIvan Khoronzhuk struct cpsw_slave *slave = &cpsw->slaves[i]; 2510606f3993SIvan Khoronzhuk 2511606f3993SIvan Khoronzhuk cpsw_slave_init(slave, cpsw, slave_offset, sliver_offset); 2512549985eeSRichard Cochran slave_offset += slave_size; 2513549985eeSRichard Cochran sliver_offset += SLIVER_SIZE; 2514549985eeSRichard Cochran } 2515549985eeSRichard Cochran 2516df828598SMugunthan V N dma_params.dev = &pdev->dev; 2517549985eeSRichard Cochran dma_params.rxthresh = dma_params.dmaregs + CPDMA_RXTHRESH; 2518549985eeSRichard Cochran dma_params.rxfree = dma_params.dmaregs + CPDMA_RXFREE; 2519549985eeSRichard Cochran dma_params.rxhdp = dma_params.txhdp + CPDMA_RXHDP; 2520549985eeSRichard Cochran dma_params.txcp = dma_params.txhdp + CPDMA_TXCP; 2521549985eeSRichard Cochran dma_params.rxcp = dma_params.txhdp + CPDMA_RXCP; 2522df828598SMugunthan V N 2523df828598SMugunthan V N dma_params.num_chan = data->channels; 2524df828598SMugunthan V N dma_params.has_soft_reset = true; 2525df828598SMugunthan V N dma_params.min_packet_size = CPSW_MIN_PACKET_SIZE; 2526df828598SMugunthan V N dma_params.desc_mem_size = data->bd_ram_size; 2527df828598SMugunthan V N dma_params.desc_align = 16; 2528df828598SMugunthan V N dma_params.has_ext_regs = true; 2529549985eeSRichard Cochran dma_params.desc_hw_addr = dma_params.desc_mem_phys; 2530df828598SMugunthan V N 25312c836bd9SIvan Khoronzhuk cpsw->dma = cpdma_ctlr_create(&dma_params); 25322c836bd9SIvan Khoronzhuk if (!cpsw->dma) { 2533df828598SMugunthan V N dev_err(priv->dev, "error initializing dma\n"); 2534df828598SMugunthan V N ret = -ENOMEM; 2535aa1a15e2SDaniel Mack goto clean_runtime_disable_ret; 2536df828598SMugunthan V N } 2537df828598SMugunthan V N 2538925d65e6SIvan Khoronzhuk cpsw->txch[0] = cpdma_chan_create(cpsw->dma, 0, cpsw_tx_handler, 0); 2539925d65e6SIvan Khoronzhuk cpsw->rxch[0] = cpdma_chan_create(cpsw->dma, 0, cpsw_rx_handler, 1); 2540e05107e6SIvan Khoronzhuk if (WARN_ON(!cpsw->rxch[0] || !cpsw->txch[0])) { 2541df828598SMugunthan V N dev_err(priv->dev, "error initializing dma channels\n"); 2542df828598SMugunthan V N ret = -ENOMEM; 2543df828598SMugunthan V N goto clean_dma_ret; 2544df828598SMugunthan V N } 2545df828598SMugunthan V N 2546df828598SMugunthan V N ale_params.dev = &ndev->dev; 2547df828598SMugunthan V N ale_params.ale_ageout = ale_ageout; 2548df828598SMugunthan V N ale_params.ale_entries = data->ale_entries; 2549df828598SMugunthan V N ale_params.ale_ports = data->slaves; 2550df828598SMugunthan V N 25512a05a622SIvan Khoronzhuk cpsw->ale = cpsw_ale_create(&ale_params); 25522a05a622SIvan Khoronzhuk if (!cpsw->ale) { 2553df828598SMugunthan V N dev_err(priv->dev, "error initializing ale engine\n"); 2554df828598SMugunthan V N ret = -ENODEV; 2555df828598SMugunthan V N goto clean_dma_ret; 2556df828598SMugunthan V N } 2557df828598SMugunthan V N 2558c03abd84SFelipe Balbi ndev->irq = platform_get_irq(pdev, 1); 2559df828598SMugunthan V N if (ndev->irq < 0) { 2560df828598SMugunthan V N dev_err(priv->dev, "error getting irq resource\n"); 2561c1e3334fSJulia Lawall ret = ndev->irq; 2562df828598SMugunthan V N goto clean_ale_ret; 2563df828598SMugunthan V N } 2564df828598SMugunthan V N 25657da11600SMugunthan V N of_id = of_match_device(cpsw_of_mtable, &pdev->dev); 25667da11600SMugunthan V N if (of_id) { 25677da11600SMugunthan V N pdev->id_entry = of_id->data; 25687da11600SMugunthan V N if (pdev->id_entry->driver_data) 2569e38b5a3dSIvan Khoronzhuk cpsw->quirk_irq = true; 25707da11600SMugunthan V N } 25717da11600SMugunthan V N 2572c03abd84SFelipe Balbi /* Grab RX and TX IRQs. Note that we also have RX_THRESHOLD and 2573c03abd84SFelipe Balbi * MISC IRQs which are always kept disabled with this driver so 2574c03abd84SFelipe Balbi * we will not request them. 2575c03abd84SFelipe Balbi * 2576c03abd84SFelipe Balbi * If anyone wants to implement support for those, make sure to 2577c03abd84SFelipe Balbi * first request and append them to irqs_table array. 2578c03abd84SFelipe Balbi */ 2579c2b32e58SDaniel Mack 2580c03abd84SFelipe Balbi /* RX IRQ */ 25815087b915SFelipe Balbi irq = platform_get_irq(pdev, 1); 2582c1e3334fSJulia Lawall if (irq < 0) { 2583c1e3334fSJulia Lawall ret = irq; 25845087b915SFelipe Balbi goto clean_ale_ret; 2585c1e3334fSJulia Lawall } 25865087b915SFelipe Balbi 2587e38b5a3dSIvan Khoronzhuk cpsw->irqs_table[0] = irq; 2588c03abd84SFelipe Balbi ret = devm_request_irq(&pdev->dev, irq, cpsw_rx_interrupt, 2589dbc4ec52SIvan Khoronzhuk 0, dev_name(&pdev->dev), cpsw); 25905087b915SFelipe Balbi if (ret < 0) { 25915087b915SFelipe Balbi dev_err(priv->dev, "error attaching irq (%d)\n", ret); 25925087b915SFelipe Balbi goto clean_ale_ret; 2593df828598SMugunthan V N } 2594df828598SMugunthan V N 2595c03abd84SFelipe Balbi /* TX IRQ */ 25965087b915SFelipe Balbi irq = platform_get_irq(pdev, 2); 2597c1e3334fSJulia Lawall if (irq < 0) { 2598c1e3334fSJulia Lawall ret = irq; 25995087b915SFelipe Balbi goto clean_ale_ret; 2600c1e3334fSJulia Lawall } 26015087b915SFelipe Balbi 2602e38b5a3dSIvan Khoronzhuk cpsw->irqs_table[1] = irq; 2603c03abd84SFelipe Balbi ret = devm_request_irq(&pdev->dev, irq, cpsw_tx_interrupt, 2604dbc4ec52SIvan Khoronzhuk 0, dev_name(&pdev->dev), cpsw); 26055087b915SFelipe Balbi if (ret < 0) { 26065087b915SFelipe Balbi dev_err(priv->dev, "error attaching irq (%d)\n", ret); 26075087b915SFelipe Balbi goto clean_ale_ret; 26085087b915SFelipe Balbi } 2609c2b32e58SDaniel Mack 2610f646968fSPatrick McHardy ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER; 2611df828598SMugunthan V N 2612df828598SMugunthan V N ndev->netdev_ops = &cpsw_netdev_ops; 26137ad24ea4SWilfried Klaebe ndev->ethtool_ops = &cpsw_ethtool_ops; 2614dbc4ec52SIvan Khoronzhuk netif_napi_add(ndev, &cpsw->napi_rx, cpsw_rx_poll, CPSW_POLL_WEIGHT); 2615dbc4ec52SIvan Khoronzhuk netif_tx_napi_add(ndev, &cpsw->napi_tx, cpsw_tx_poll, CPSW_POLL_WEIGHT); 2616df828598SMugunthan V N 2617df828598SMugunthan V N /* register the network device */ 2618df828598SMugunthan V N SET_NETDEV_DEV(ndev, &pdev->dev); 2619df828598SMugunthan V N ret = register_netdev(ndev); 2620df828598SMugunthan V N if (ret) { 2621df828598SMugunthan V N dev_err(priv->dev, "error registering net device\n"); 2622df828598SMugunthan V N ret = -ENODEV; 2623aa1a15e2SDaniel Mack goto clean_ale_ret; 2624df828598SMugunthan V N } 2625df828598SMugunthan V N 26261a3b5056SOlof Johansson cpsw_notice(priv, probe, "initialized device (regs %pa, irq %d)\n", 26271a3b5056SOlof Johansson &ss_res->start, ndev->irq); 2628df828598SMugunthan V N 2629606f3993SIvan Khoronzhuk if (cpsw->data.dual_emac) { 263056e31bd8SIvan Khoronzhuk ret = cpsw_probe_dual_emac(priv); 2631d9ba8f9eSMugunthan V N if (ret) { 2632d9ba8f9eSMugunthan V N cpsw_err(priv, probe, "error probe slave 2 emac interface\n"); 2633aa1a15e2SDaniel Mack goto clean_ale_ret; 2634d9ba8f9eSMugunthan V N } 2635d9ba8f9eSMugunthan V N } 2636d9ba8f9eSMugunthan V N 2637df828598SMugunthan V N return 0; 2638df828598SMugunthan V N 2639df828598SMugunthan V N clean_ale_ret: 26402a05a622SIvan Khoronzhuk cpsw_ale_destroy(cpsw->ale); 2641df828598SMugunthan V N clean_dma_ret: 26422c836bd9SIvan Khoronzhuk cpdma_ctlr_destroy(cpsw->dma); 2643aa1a15e2SDaniel Mack clean_runtime_disable_ret: 2644f150bd7fSMugunthan V N pm_runtime_disable(&pdev->dev); 2645df828598SMugunthan V N clean_ndev_ret: 2646d1bd9acfSSebastian Siewior free_netdev(priv->ndev); 2647df828598SMugunthan V N return ret; 2648df828598SMugunthan V N } 2649df828598SMugunthan V N 2650663e12e6SBill Pemberton static int cpsw_remove(struct platform_device *pdev) 2651df828598SMugunthan V N { 2652df828598SMugunthan V N struct net_device *ndev = platform_get_drvdata(pdev); 26532a05a622SIvan Khoronzhuk struct cpsw_common *cpsw = ndev_to_cpsw(ndev); 26548a0b6dc9SGrygorii Strashko int ret; 26558a0b6dc9SGrygorii Strashko 26568a0b6dc9SGrygorii Strashko ret = pm_runtime_get_sync(&pdev->dev); 26578a0b6dc9SGrygorii Strashko if (ret < 0) { 26588a0b6dc9SGrygorii Strashko pm_runtime_put_noidle(&pdev->dev); 26598a0b6dc9SGrygorii Strashko return ret; 26608a0b6dc9SGrygorii Strashko } 2661df828598SMugunthan V N 2662606f3993SIvan Khoronzhuk if (cpsw->data.dual_emac) 2663606f3993SIvan Khoronzhuk unregister_netdev(cpsw->slaves[1].ndev); 2664d1bd9acfSSebastian Siewior unregister_netdev(ndev); 2665df828598SMugunthan V N 26662a05a622SIvan Khoronzhuk cpsw_ale_destroy(cpsw->ale); 26672c836bd9SIvan Khoronzhuk cpdma_ctlr_destroy(cpsw->dma); 26683bf2cb3aSGrygorii Strashko of_platform_depopulate(&pdev->dev); 26698a0b6dc9SGrygorii Strashko pm_runtime_put_sync(&pdev->dev); 26708a0b6dc9SGrygorii Strashko pm_runtime_disable(&pdev->dev); 2671606f3993SIvan Khoronzhuk if (cpsw->data.dual_emac) 2672606f3993SIvan Khoronzhuk free_netdev(cpsw->slaves[1].ndev); 2673df828598SMugunthan V N free_netdev(ndev); 2674df828598SMugunthan V N return 0; 2675df828598SMugunthan V N } 2676df828598SMugunthan V N 26778963a504SGrygorii Strashko #ifdef CONFIG_PM_SLEEP 2678df828598SMugunthan V N static int cpsw_suspend(struct device *dev) 2679df828598SMugunthan V N { 2680df828598SMugunthan V N struct platform_device *pdev = to_platform_device(dev); 2681df828598SMugunthan V N struct net_device *ndev = platform_get_drvdata(pdev); 2682606f3993SIvan Khoronzhuk struct cpsw_common *cpsw = ndev_to_cpsw(ndev); 2683df828598SMugunthan V N 2684606f3993SIvan Khoronzhuk if (cpsw->data.dual_emac) { 2685618073e3SMugunthan V N int i; 2686618073e3SMugunthan V N 2687606f3993SIvan Khoronzhuk for (i = 0; i < cpsw->data.slaves; i++) { 2688606f3993SIvan Khoronzhuk if (netif_running(cpsw->slaves[i].ndev)) 2689606f3993SIvan Khoronzhuk cpsw_ndo_stop(cpsw->slaves[i].ndev); 2690618073e3SMugunthan V N } 2691618073e3SMugunthan V N } else { 2692df828598SMugunthan V N if (netif_running(ndev)) 2693df828598SMugunthan V N cpsw_ndo_stop(ndev); 2694618073e3SMugunthan V N } 26951e7a2e21SDaniel Mack 2696739683b4SMugunthan V N /* Select sleep pin state */ 269756e31bd8SIvan Khoronzhuk pinctrl_pm_select_sleep_state(dev); 2698739683b4SMugunthan V N 2699df828598SMugunthan V N return 0; 2700df828598SMugunthan V N } 2701df828598SMugunthan V N 2702df828598SMugunthan V N static int cpsw_resume(struct device *dev) 2703df828598SMugunthan V N { 2704df828598SMugunthan V N struct platform_device *pdev = to_platform_device(dev); 2705df828598SMugunthan V N struct net_device *ndev = platform_get_drvdata(pdev); 2706606f3993SIvan Khoronzhuk struct cpsw_common *cpsw = netdev_priv(ndev); 2707df828598SMugunthan V N 2708739683b4SMugunthan V N /* Select default pin state */ 270956e31bd8SIvan Khoronzhuk pinctrl_pm_select_default_state(dev); 2710739683b4SMugunthan V N 2711606f3993SIvan Khoronzhuk if (cpsw->data.dual_emac) { 2712618073e3SMugunthan V N int i; 2713618073e3SMugunthan V N 2714606f3993SIvan Khoronzhuk for (i = 0; i < cpsw->data.slaves; i++) { 2715606f3993SIvan Khoronzhuk if (netif_running(cpsw->slaves[i].ndev)) 2716606f3993SIvan Khoronzhuk cpsw_ndo_open(cpsw->slaves[i].ndev); 2717618073e3SMugunthan V N } 2718618073e3SMugunthan V N } else { 2719df828598SMugunthan V N if (netif_running(ndev)) 2720df828598SMugunthan V N cpsw_ndo_open(ndev); 2721618073e3SMugunthan V N } 2722df828598SMugunthan V N return 0; 2723df828598SMugunthan V N } 27248963a504SGrygorii Strashko #endif 2725df828598SMugunthan V N 27268963a504SGrygorii Strashko static SIMPLE_DEV_PM_OPS(cpsw_pm_ops, cpsw_suspend, cpsw_resume); 2727df828598SMugunthan V N 2728df828598SMugunthan V N static struct platform_driver cpsw_driver = { 2729df828598SMugunthan V N .driver = { 2730df828598SMugunthan V N .name = "cpsw", 2731df828598SMugunthan V N .pm = &cpsw_pm_ops, 27321e5c76d4SSachin Kamat .of_match_table = cpsw_of_mtable, 2733df828598SMugunthan V N }, 2734df828598SMugunthan V N .probe = cpsw_probe, 2735663e12e6SBill Pemberton .remove = cpsw_remove, 2736df828598SMugunthan V N }; 2737df828598SMugunthan V N 27386fb3b6b5SGrygorii Strashko module_platform_driver(cpsw_driver); 2739df828598SMugunthan V N 2740df828598SMugunthan V N MODULE_LICENSE("GPL"); 2741df828598SMugunthan V N MODULE_AUTHOR("Cyril Chemparathy <cyril@ti.com>"); 2742df828598SMugunthan V N MODULE_AUTHOR("Mugunthan V N <mugunthanvnm@ti.com>"); 2743df828598SMugunthan V N MODULE_DESCRIPTION("TI CPSW Ethernet driver"); 2744