1df828598SMugunthan V N /* 2df828598SMugunthan V N * Texas Instruments Ethernet Switch Driver 3df828598SMugunthan V N * 4df828598SMugunthan V N * Copyright (C) 2012 Texas Instruments 5df828598SMugunthan V N * 6df828598SMugunthan V N * This program is free software; you can redistribute it and/or 7df828598SMugunthan V N * modify it under the terms of the GNU General Public License as 8df828598SMugunthan V N * published by the Free Software Foundation version 2. 9df828598SMugunthan V N * 10df828598SMugunthan V N * This program is distributed "as is" WITHOUT ANY WARRANTY of any 11df828598SMugunthan V N * kind, whether express or implied; without even the implied warranty 12df828598SMugunthan V N * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13df828598SMugunthan V N * GNU General Public License for more details. 14df828598SMugunthan V N */ 15df828598SMugunthan V N 16df828598SMugunthan V N #include <linux/kernel.h> 17df828598SMugunthan V N #include <linux/io.h> 18df828598SMugunthan V N #include <linux/clk.h> 19df828598SMugunthan V N #include <linux/timer.h> 20df828598SMugunthan V N #include <linux/module.h> 21df828598SMugunthan V N #include <linux/platform_device.h> 22df828598SMugunthan V N #include <linux/irqreturn.h> 23df828598SMugunthan V N #include <linux/interrupt.h> 24df828598SMugunthan V N #include <linux/if_ether.h> 25df828598SMugunthan V N #include <linux/etherdevice.h> 26df828598SMugunthan V N #include <linux/netdevice.h> 272e5b38abSRichard Cochran #include <linux/net_tstamp.h> 28df828598SMugunthan V N #include <linux/phy.h> 29df828598SMugunthan V N #include <linux/workqueue.h> 30df828598SMugunthan V N #include <linux/delay.h> 31f150bd7fSMugunthan V N #include <linux/pm_runtime.h> 321d147ccbSMugunthan V N #include <linux/gpio.h> 332eb32b0aSMugunthan V N #include <linux/of.h> 349e42f715SHeiko Schocher #include <linux/of_mdio.h> 352eb32b0aSMugunthan V N #include <linux/of_net.h> 362eb32b0aSMugunthan V N #include <linux/of_device.h> 373b72c2feSMugunthan V N #include <linux/if_vlan.h> 38df828598SMugunthan V N 39739683b4SMugunthan V N #include <linux/pinctrl/consumer.h> 40df828598SMugunthan V N 41dbe34724SMugunthan V N #include "cpsw.h" 42df828598SMugunthan V N #include "cpsw_ale.h" 432e5b38abSRichard Cochran #include "cpts.h" 44df828598SMugunthan V N #include "davinci_cpdma.h" 45df828598SMugunthan V N 46df828598SMugunthan V N #define CPSW_DEBUG (NETIF_MSG_HW | NETIF_MSG_WOL | \ 47df828598SMugunthan V N NETIF_MSG_DRV | NETIF_MSG_LINK | \ 48df828598SMugunthan V N NETIF_MSG_IFUP | NETIF_MSG_INTR | \ 49df828598SMugunthan V N NETIF_MSG_PROBE | NETIF_MSG_TIMER | \ 50df828598SMugunthan V N NETIF_MSG_IFDOWN | NETIF_MSG_RX_ERR | \ 51df828598SMugunthan V N NETIF_MSG_TX_ERR | NETIF_MSG_TX_DONE | \ 52df828598SMugunthan V N NETIF_MSG_PKTDATA | NETIF_MSG_TX_QUEUED | \ 53df828598SMugunthan V N NETIF_MSG_RX_STATUS) 54df828598SMugunthan V N 55df828598SMugunthan V N #define cpsw_info(priv, type, format, ...) \ 56df828598SMugunthan V N do { \ 57df828598SMugunthan V N if (netif_msg_##type(priv) && net_ratelimit()) \ 58df828598SMugunthan V N dev_info(priv->dev, format, ## __VA_ARGS__); \ 59df828598SMugunthan V N } while (0) 60df828598SMugunthan V N 61df828598SMugunthan V N #define cpsw_err(priv, type, format, ...) \ 62df828598SMugunthan V N do { \ 63df828598SMugunthan V N if (netif_msg_##type(priv) && net_ratelimit()) \ 64df828598SMugunthan V N dev_err(priv->dev, format, ## __VA_ARGS__); \ 65df828598SMugunthan V N } while (0) 66df828598SMugunthan V N 67df828598SMugunthan V N #define cpsw_dbg(priv, type, format, ...) \ 68df828598SMugunthan V N do { \ 69df828598SMugunthan V N if (netif_msg_##type(priv) && net_ratelimit()) \ 70df828598SMugunthan V N dev_dbg(priv->dev, format, ## __VA_ARGS__); \ 71df828598SMugunthan V N } while (0) 72df828598SMugunthan V N 73df828598SMugunthan V N #define cpsw_notice(priv, type, format, ...) \ 74df828598SMugunthan V N do { \ 75df828598SMugunthan V N if (netif_msg_##type(priv) && net_ratelimit()) \ 76df828598SMugunthan V N dev_notice(priv->dev, format, ## __VA_ARGS__); \ 77df828598SMugunthan V N } while (0) 78df828598SMugunthan V N 795c50a856SMugunthan V N #define ALE_ALL_PORTS 0x7 805c50a856SMugunthan V N 81df828598SMugunthan V N #define CPSW_MAJOR_VERSION(reg) (reg >> 8 & 0x7) 82df828598SMugunthan V N #define CPSW_MINOR_VERSION(reg) (reg & 0xff) 83df828598SMugunthan V N #define CPSW_RTL_VERSION(reg) ((reg >> 11) & 0x1f) 84df828598SMugunthan V N 85e90cfac6SRichard Cochran #define CPSW_VERSION_1 0x19010a 86e90cfac6SRichard Cochran #define CPSW_VERSION_2 0x19010c 87c193f365SMugunthan V N #define CPSW_VERSION_3 0x19010f 88926489beSMugunthan V N #define CPSW_VERSION_4 0x190112 89549985eeSRichard Cochran 90549985eeSRichard Cochran #define HOST_PORT_NUM 0 91549985eeSRichard Cochran #define SLIVER_SIZE 0x40 92549985eeSRichard Cochran 93549985eeSRichard Cochran #define CPSW1_HOST_PORT_OFFSET 0x028 94549985eeSRichard Cochran #define CPSW1_SLAVE_OFFSET 0x050 95549985eeSRichard Cochran #define CPSW1_SLAVE_SIZE 0x040 96549985eeSRichard Cochran #define CPSW1_CPDMA_OFFSET 0x100 97549985eeSRichard Cochran #define CPSW1_STATERAM_OFFSET 0x200 98d9718546SMugunthan V N #define CPSW1_HW_STATS 0x400 99549985eeSRichard Cochran #define CPSW1_CPTS_OFFSET 0x500 100549985eeSRichard Cochran #define CPSW1_ALE_OFFSET 0x600 101549985eeSRichard Cochran #define CPSW1_SLIVER_OFFSET 0x700 102549985eeSRichard Cochran 103549985eeSRichard Cochran #define CPSW2_HOST_PORT_OFFSET 0x108 104549985eeSRichard Cochran #define CPSW2_SLAVE_OFFSET 0x200 105549985eeSRichard Cochran #define CPSW2_SLAVE_SIZE 0x100 106549985eeSRichard Cochran #define CPSW2_CPDMA_OFFSET 0x800 107d9718546SMugunthan V N #define CPSW2_HW_STATS 0x900 108549985eeSRichard Cochran #define CPSW2_STATERAM_OFFSET 0xa00 109549985eeSRichard Cochran #define CPSW2_CPTS_OFFSET 0xc00 110549985eeSRichard Cochran #define CPSW2_ALE_OFFSET 0xd00 111549985eeSRichard Cochran #define CPSW2_SLIVER_OFFSET 0xd80 112549985eeSRichard Cochran #define CPSW2_BD_OFFSET 0x2000 113549985eeSRichard Cochran 114df828598SMugunthan V N #define CPDMA_RXTHRESH 0x0c0 115df828598SMugunthan V N #define CPDMA_RXFREE 0x0e0 116df828598SMugunthan V N #define CPDMA_TXHDP 0x00 117df828598SMugunthan V N #define CPDMA_RXHDP 0x20 118df828598SMugunthan V N #define CPDMA_TXCP 0x40 119df828598SMugunthan V N #define CPDMA_RXCP 0x60 120df828598SMugunthan V N 121df828598SMugunthan V N #define CPSW_POLL_WEIGHT 64 122df828598SMugunthan V N #define CPSW_MIN_PACKET_SIZE 60 123df828598SMugunthan V N #define CPSW_MAX_PACKET_SIZE (1500 + 14 + 4 + 4) 124df828598SMugunthan V N 125df828598SMugunthan V N #define RX_PRIORITY_MAPPING 0x76543210 126df828598SMugunthan V N #define TX_PRIORITY_MAPPING 0x33221100 127df828598SMugunthan V N #define CPDMA_TX_PRIORITY_MAP 0x76543210 128df828598SMugunthan V N 1293b72c2feSMugunthan V N #define CPSW_VLAN_AWARE BIT(1) 1303b72c2feSMugunthan V N #define CPSW_ALE_VLAN_AWARE 1 1313b72c2feSMugunthan V N 13235717d8dSJohn Ogness #define CPSW_FIFO_NORMAL_MODE (0 << 16) 13335717d8dSJohn Ogness #define CPSW_FIFO_DUAL_MAC_MODE (1 << 16) 13435717d8dSJohn Ogness #define CPSW_FIFO_RATE_LIMIT_MODE (2 << 16) 135d9ba8f9eSMugunthan V N 136ff5b8ef2SMugunthan V N #define CPSW_INTPACEEN (0x3f << 16) 137ff5b8ef2SMugunthan V N #define CPSW_INTPRESCALE_MASK (0x7FF << 0) 138ff5b8ef2SMugunthan V N #define CPSW_CMINTMAX_CNT 63 139ff5b8ef2SMugunthan V N #define CPSW_CMINTMIN_CNT 2 140ff5b8ef2SMugunthan V N #define CPSW_CMINTMAX_INTVL (1000 / CPSW_CMINTMIN_CNT) 141ff5b8ef2SMugunthan V N #define CPSW_CMINTMIN_INTVL ((1000 / CPSW_CMINTMAX_CNT) + 1) 142ff5b8ef2SMugunthan V N 143d3bb9c58SMugunthan V N #define cpsw_slave_index(priv) \ 144d3bb9c58SMugunthan V N ((priv->data.dual_emac) ? priv->emac_port : \ 145d3bb9c58SMugunthan V N priv->data.active_slave) 146d3bb9c58SMugunthan V N 147df828598SMugunthan V N static int debug_level; 148df828598SMugunthan V N module_param(debug_level, int, 0); 149df828598SMugunthan V N MODULE_PARM_DESC(debug_level, "cpsw debug level (NETIF_MSG bits)"); 150df828598SMugunthan V N 151df828598SMugunthan V N static int ale_ageout = 10; 152df828598SMugunthan V N module_param(ale_ageout, int, 0); 153df828598SMugunthan V N MODULE_PARM_DESC(ale_ageout, "cpsw ale ageout interval (seconds)"); 154df828598SMugunthan V N 155df828598SMugunthan V N static int rx_packet_max = CPSW_MAX_PACKET_SIZE; 156df828598SMugunthan V N module_param(rx_packet_max, int, 0); 157df828598SMugunthan V N MODULE_PARM_DESC(rx_packet_max, "maximum receive packet size (bytes)"); 158df828598SMugunthan V N 159996a5c27SRichard Cochran struct cpsw_wr_regs { 160df828598SMugunthan V N u32 id_ver; 161df828598SMugunthan V N u32 soft_reset; 162df828598SMugunthan V N u32 control; 163df828598SMugunthan V N u32 int_control; 164df828598SMugunthan V N u32 rx_thresh_en; 165df828598SMugunthan V N u32 rx_en; 166df828598SMugunthan V N u32 tx_en; 167df828598SMugunthan V N u32 misc_en; 168ff5b8ef2SMugunthan V N u32 mem_allign1[8]; 169ff5b8ef2SMugunthan V N u32 rx_thresh_stat; 170ff5b8ef2SMugunthan V N u32 rx_stat; 171ff5b8ef2SMugunthan V N u32 tx_stat; 172ff5b8ef2SMugunthan V N u32 misc_stat; 173ff5b8ef2SMugunthan V N u32 mem_allign2[8]; 174ff5b8ef2SMugunthan V N u32 rx_imax; 175ff5b8ef2SMugunthan V N u32 tx_imax; 176ff5b8ef2SMugunthan V N 177df828598SMugunthan V N }; 178df828598SMugunthan V N 179996a5c27SRichard Cochran struct cpsw_ss_regs { 180df828598SMugunthan V N u32 id_ver; 181df828598SMugunthan V N u32 control; 182df828598SMugunthan V N u32 soft_reset; 183df828598SMugunthan V N u32 stat_port_en; 184df828598SMugunthan V N u32 ptype; 185bd357af2SRichard Cochran u32 soft_idle; 186bd357af2SRichard Cochran u32 thru_rate; 187bd357af2SRichard Cochran u32 gap_thresh; 188bd357af2SRichard Cochran u32 tx_start_wds; 189bd357af2SRichard Cochran u32 flow_control; 190bd357af2SRichard Cochran u32 vlan_ltype; 191bd357af2SRichard Cochran u32 ts_ltype; 192bd357af2SRichard Cochran u32 dlr_ltype; 193df828598SMugunthan V N }; 194df828598SMugunthan V N 1959750a3adSRichard Cochran /* CPSW_PORT_V1 */ 1969750a3adSRichard Cochran #define CPSW1_MAX_BLKS 0x00 /* Maximum FIFO Blocks */ 1979750a3adSRichard Cochran #define CPSW1_BLK_CNT 0x04 /* FIFO Block Usage Count (Read Only) */ 1989750a3adSRichard Cochran #define CPSW1_TX_IN_CTL 0x08 /* Transmit FIFO Control */ 1999750a3adSRichard Cochran #define CPSW1_PORT_VLAN 0x0c /* VLAN Register */ 2009750a3adSRichard Cochran #define CPSW1_TX_PRI_MAP 0x10 /* Tx Header Priority to Switch Pri Mapping */ 2019750a3adSRichard Cochran #define CPSW1_TS_CTL 0x14 /* Time Sync Control */ 2029750a3adSRichard Cochran #define CPSW1_TS_SEQ_LTYPE 0x18 /* Time Sync Sequence ID Offset and Msg Type */ 2039750a3adSRichard Cochran #define CPSW1_TS_VLAN 0x1c /* Time Sync VLAN1 and VLAN2 */ 2049750a3adSRichard Cochran 2059750a3adSRichard Cochran /* CPSW_PORT_V2 */ 2069750a3adSRichard Cochran #define CPSW2_CONTROL 0x00 /* Control Register */ 2079750a3adSRichard Cochran #define CPSW2_MAX_BLKS 0x08 /* Maximum FIFO Blocks */ 2089750a3adSRichard Cochran #define CPSW2_BLK_CNT 0x0c /* FIFO Block Usage Count (Read Only) */ 2099750a3adSRichard Cochran #define CPSW2_TX_IN_CTL 0x10 /* Transmit FIFO Control */ 2109750a3adSRichard Cochran #define CPSW2_PORT_VLAN 0x14 /* VLAN Register */ 2119750a3adSRichard Cochran #define CPSW2_TX_PRI_MAP 0x18 /* Tx Header Priority to Switch Pri Mapping */ 2129750a3adSRichard Cochran #define CPSW2_TS_SEQ_MTYPE 0x1c /* Time Sync Sequence ID Offset and Msg Type */ 2139750a3adSRichard Cochran 2149750a3adSRichard Cochran /* CPSW_PORT_V1 and V2 */ 2159750a3adSRichard Cochran #define SA_LO 0x20 /* CPGMAC_SL Source Address Low */ 2169750a3adSRichard Cochran #define SA_HI 0x24 /* CPGMAC_SL Source Address High */ 2179750a3adSRichard Cochran #define SEND_PERCENT 0x28 /* Transmit Queue Send Percentages */ 2189750a3adSRichard Cochran 2199750a3adSRichard Cochran /* CPSW_PORT_V2 only */ 2209750a3adSRichard Cochran #define RX_DSCP_PRI_MAP0 0x30 /* Rx DSCP Priority to Rx Packet Mapping */ 2219750a3adSRichard Cochran #define RX_DSCP_PRI_MAP1 0x34 /* Rx DSCP Priority to Rx Packet Mapping */ 2229750a3adSRichard Cochran #define RX_DSCP_PRI_MAP2 0x38 /* Rx DSCP Priority to Rx Packet Mapping */ 2239750a3adSRichard Cochran #define RX_DSCP_PRI_MAP3 0x3c /* Rx DSCP Priority to Rx Packet Mapping */ 2249750a3adSRichard Cochran #define RX_DSCP_PRI_MAP4 0x40 /* Rx DSCP Priority to Rx Packet Mapping */ 2259750a3adSRichard Cochran #define RX_DSCP_PRI_MAP5 0x44 /* Rx DSCP Priority to Rx Packet Mapping */ 2269750a3adSRichard Cochran #define RX_DSCP_PRI_MAP6 0x48 /* Rx DSCP Priority to Rx Packet Mapping */ 2279750a3adSRichard Cochran #define RX_DSCP_PRI_MAP7 0x4c /* Rx DSCP Priority to Rx Packet Mapping */ 2289750a3adSRichard Cochran 2299750a3adSRichard Cochran /* Bit definitions for the CPSW2_CONTROL register */ 2309750a3adSRichard Cochran #define PASS_PRI_TAGGED (1<<24) /* Pass Priority Tagged */ 2319750a3adSRichard Cochran #define VLAN_LTYPE2_EN (1<<21) /* VLAN LTYPE 2 enable */ 2329750a3adSRichard Cochran #define VLAN_LTYPE1_EN (1<<20) /* VLAN LTYPE 1 enable */ 2339750a3adSRichard Cochran #define DSCP_PRI_EN (1<<16) /* DSCP Priority Enable */ 2349750a3adSRichard Cochran #define TS_320 (1<<14) /* Time Sync Dest Port 320 enable */ 2359750a3adSRichard Cochran #define TS_319 (1<<13) /* Time Sync Dest Port 319 enable */ 2369750a3adSRichard Cochran #define TS_132 (1<<12) /* Time Sync Dest IP Addr 132 enable */ 2379750a3adSRichard Cochran #define TS_131 (1<<11) /* Time Sync Dest IP Addr 131 enable */ 2389750a3adSRichard Cochran #define TS_130 (1<<10) /* Time Sync Dest IP Addr 130 enable */ 2399750a3adSRichard Cochran #define TS_129 (1<<9) /* Time Sync Dest IP Addr 129 enable */ 24009c55372SGeorge Cherian #define TS_TTL_NONZERO (1<<8) /* Time Sync Time To Live Non-zero enable */ 24109c55372SGeorge Cherian #define TS_ANNEX_F_EN (1<<6) /* Time Sync Annex F enable */ 2429750a3adSRichard Cochran #define TS_ANNEX_D_EN (1<<4) /* Time Sync Annex D enable */ 2439750a3adSRichard Cochran #define TS_LTYPE2_EN (1<<3) /* Time Sync LTYPE 2 enable */ 2449750a3adSRichard Cochran #define TS_LTYPE1_EN (1<<2) /* Time Sync LTYPE 1 enable */ 2459750a3adSRichard Cochran #define TS_TX_EN (1<<1) /* Time Sync Transmit Enable */ 2469750a3adSRichard Cochran #define TS_RX_EN (1<<0) /* Time Sync Receive Enable */ 2479750a3adSRichard Cochran 24809c55372SGeorge Cherian #define CTRL_V2_TS_BITS \ 24909c55372SGeorge Cherian (TS_320 | TS_319 | TS_132 | TS_131 | TS_130 | TS_129 |\ 25009c55372SGeorge Cherian TS_TTL_NONZERO | TS_ANNEX_D_EN | TS_LTYPE1_EN) 2519750a3adSRichard Cochran 25209c55372SGeorge Cherian #define CTRL_V2_ALL_TS_MASK (CTRL_V2_TS_BITS | TS_TX_EN | TS_RX_EN) 25309c55372SGeorge Cherian #define CTRL_V2_TX_TS_BITS (CTRL_V2_TS_BITS | TS_TX_EN) 25409c55372SGeorge Cherian #define CTRL_V2_RX_TS_BITS (CTRL_V2_TS_BITS | TS_RX_EN) 25509c55372SGeorge Cherian 25609c55372SGeorge Cherian 25709c55372SGeorge Cherian #define CTRL_V3_TS_BITS \ 25809c55372SGeorge Cherian (TS_320 | TS_319 | TS_132 | TS_131 | TS_130 | TS_129 |\ 25909c55372SGeorge Cherian TS_TTL_NONZERO | TS_ANNEX_F_EN | TS_ANNEX_D_EN |\ 26009c55372SGeorge Cherian TS_LTYPE1_EN) 26109c55372SGeorge Cherian 26209c55372SGeorge Cherian #define CTRL_V3_ALL_TS_MASK (CTRL_V3_TS_BITS | TS_TX_EN | TS_RX_EN) 26309c55372SGeorge Cherian #define CTRL_V3_TX_TS_BITS (CTRL_V3_TS_BITS | TS_TX_EN) 26409c55372SGeorge Cherian #define CTRL_V3_RX_TS_BITS (CTRL_V3_TS_BITS | TS_RX_EN) 2659750a3adSRichard Cochran 2669750a3adSRichard Cochran /* Bit definitions for the CPSW2_TS_SEQ_MTYPE register */ 2679750a3adSRichard Cochran #define TS_SEQ_ID_OFFSET_SHIFT (16) /* Time Sync Sequence ID Offset */ 2689750a3adSRichard Cochran #define TS_SEQ_ID_OFFSET_MASK (0x3f) 2699750a3adSRichard Cochran #define TS_MSG_TYPE_EN_SHIFT (0) /* Time Sync Message Type Enable */ 2709750a3adSRichard Cochran #define TS_MSG_TYPE_EN_MASK (0xffff) 2719750a3adSRichard Cochran 2729750a3adSRichard Cochran /* The PTP event messages - Sync, Delay_Req, Pdelay_Req, and Pdelay_Resp. */ 2739750a3adSRichard Cochran #define EVENT_MSG_BITS ((1<<0) | (1<<1) | (1<<2) | (1<<3)) 274df828598SMugunthan V N 2752e5b38abSRichard Cochran /* Bit definitions for the CPSW1_TS_CTL register */ 2762e5b38abSRichard Cochran #define CPSW_V1_TS_RX_EN BIT(0) 2772e5b38abSRichard Cochran #define CPSW_V1_TS_TX_EN BIT(4) 2782e5b38abSRichard Cochran #define CPSW_V1_MSG_TYPE_OFS 16 2792e5b38abSRichard Cochran 2802e5b38abSRichard Cochran /* Bit definitions for the CPSW1_TS_SEQ_LTYPE register */ 2812e5b38abSRichard Cochran #define CPSW_V1_SEQ_ID_OFS_SHIFT 16 2822e5b38abSRichard Cochran 283df828598SMugunthan V N struct cpsw_host_regs { 284df828598SMugunthan V N u32 max_blks; 285df828598SMugunthan V N u32 blk_cnt; 286d9ba8f9eSMugunthan V N u32 tx_in_ctl; 287df828598SMugunthan V N u32 port_vlan; 288df828598SMugunthan V N u32 tx_pri_map; 289df828598SMugunthan V N u32 cpdma_tx_pri_map; 290df828598SMugunthan V N u32 cpdma_rx_chan_map; 291df828598SMugunthan V N }; 292df828598SMugunthan V N 293df828598SMugunthan V N struct cpsw_sliver_regs { 294df828598SMugunthan V N u32 id_ver; 295df828598SMugunthan V N u32 mac_control; 296df828598SMugunthan V N u32 mac_status; 297df828598SMugunthan V N u32 soft_reset; 298df828598SMugunthan V N u32 rx_maxlen; 299df828598SMugunthan V N u32 __reserved_0; 300df828598SMugunthan V N u32 rx_pause; 301df828598SMugunthan V N u32 tx_pause; 302df828598SMugunthan V N u32 __reserved_1; 303df828598SMugunthan V N u32 rx_pri_map; 304df828598SMugunthan V N }; 305df828598SMugunthan V N 306d9718546SMugunthan V N struct cpsw_hw_stats { 307d9718546SMugunthan V N u32 rxgoodframes; 308d9718546SMugunthan V N u32 rxbroadcastframes; 309d9718546SMugunthan V N u32 rxmulticastframes; 310d9718546SMugunthan V N u32 rxpauseframes; 311d9718546SMugunthan V N u32 rxcrcerrors; 312d9718546SMugunthan V N u32 rxaligncodeerrors; 313d9718546SMugunthan V N u32 rxoversizedframes; 314d9718546SMugunthan V N u32 rxjabberframes; 315d9718546SMugunthan V N u32 rxundersizedframes; 316d9718546SMugunthan V N u32 rxfragments; 317d9718546SMugunthan V N u32 __pad_0[2]; 318d9718546SMugunthan V N u32 rxoctets; 319d9718546SMugunthan V N u32 txgoodframes; 320d9718546SMugunthan V N u32 txbroadcastframes; 321d9718546SMugunthan V N u32 txmulticastframes; 322d9718546SMugunthan V N u32 txpauseframes; 323d9718546SMugunthan V N u32 txdeferredframes; 324d9718546SMugunthan V N u32 txcollisionframes; 325d9718546SMugunthan V N u32 txsinglecollframes; 326d9718546SMugunthan V N u32 txmultcollframes; 327d9718546SMugunthan V N u32 txexcessivecollisions; 328d9718546SMugunthan V N u32 txlatecollisions; 329d9718546SMugunthan V N u32 txunderrun; 330d9718546SMugunthan V N u32 txcarriersenseerrors; 331d9718546SMugunthan V N u32 txoctets; 332d9718546SMugunthan V N u32 octetframes64; 333d9718546SMugunthan V N u32 octetframes65t127; 334d9718546SMugunthan V N u32 octetframes128t255; 335d9718546SMugunthan V N u32 octetframes256t511; 336d9718546SMugunthan V N u32 octetframes512t1023; 337d9718546SMugunthan V N u32 octetframes1024tup; 338d9718546SMugunthan V N u32 netoctets; 339d9718546SMugunthan V N u32 rxsofoverruns; 340d9718546SMugunthan V N u32 rxmofoverruns; 341d9718546SMugunthan V N u32 rxdmaoverruns; 342d9718546SMugunthan V N }; 343d9718546SMugunthan V N 344df828598SMugunthan V N struct cpsw_slave { 3459750a3adSRichard Cochran void __iomem *regs; 346df828598SMugunthan V N struct cpsw_sliver_regs __iomem *sliver; 347df828598SMugunthan V N int slave_num; 348df828598SMugunthan V N u32 mac_control; 349df828598SMugunthan V N struct cpsw_slave_data *data; 350df828598SMugunthan V N struct phy_device *phy; 351d9ba8f9eSMugunthan V N struct net_device *ndev; 352d9ba8f9eSMugunthan V N u32 port_vlan; 353d9ba8f9eSMugunthan V N u32 open_stat; 354df828598SMugunthan V N }; 355df828598SMugunthan V N 3569750a3adSRichard Cochran static inline u32 slave_read(struct cpsw_slave *slave, u32 offset) 3579750a3adSRichard Cochran { 3589750a3adSRichard Cochran return __raw_readl(slave->regs + offset); 3599750a3adSRichard Cochran } 3609750a3adSRichard Cochran 3619750a3adSRichard Cochran static inline void slave_write(struct cpsw_slave *slave, u32 val, u32 offset) 3629750a3adSRichard Cochran { 3639750a3adSRichard Cochran __raw_writel(val, slave->regs + offset); 3649750a3adSRichard Cochran } 3659750a3adSRichard Cochran 366df828598SMugunthan V N struct cpsw_priv { 367df828598SMugunthan V N spinlock_t lock; 368df828598SMugunthan V N struct platform_device *pdev; 369df828598SMugunthan V N struct net_device *ndev; 3709e42f715SHeiko Schocher struct device_node *phy_node; 37132a7432cSMugunthan V N struct napi_struct napi_rx; 37232a7432cSMugunthan V N struct napi_struct napi_tx; 373df828598SMugunthan V N struct device *dev; 374df828598SMugunthan V N struct cpsw_platform_data data; 375996a5c27SRichard Cochran struct cpsw_ss_regs __iomem *regs; 376996a5c27SRichard Cochran struct cpsw_wr_regs __iomem *wr_regs; 377d9718546SMugunthan V N u8 __iomem *hw_stats; 378df828598SMugunthan V N struct cpsw_host_regs __iomem *host_port_regs; 379df828598SMugunthan V N u32 msg_enable; 380e90cfac6SRichard Cochran u32 version; 381ff5b8ef2SMugunthan V N u32 coal_intvl; 382ff5b8ef2SMugunthan V N u32 bus_freq_mhz; 383df828598SMugunthan V N int rx_packet_max; 384df828598SMugunthan V N struct clk *clk; 385df828598SMugunthan V N u8 mac_addr[ETH_ALEN]; 386df828598SMugunthan V N struct cpsw_slave *slaves; 387df828598SMugunthan V N struct cpdma_ctlr *dma; 388df828598SMugunthan V N struct cpdma_chan *txch, *rxch; 389df828598SMugunthan V N struct cpsw_ale *ale; 3901923d6e4SMugunthan V N bool rx_pause; 3911923d6e4SMugunthan V N bool tx_pause; 3927da11600SMugunthan V N bool quirk_irq; 3937da11600SMugunthan V N bool rx_irq_disabled; 3947da11600SMugunthan V N bool tx_irq_disabled; 395df828598SMugunthan V N /* snapshot of IRQ numbers */ 396df828598SMugunthan V N u32 irqs_table[4]; 397df828598SMugunthan V N u32 num_irqs; 3989232b16dSMugunthan V N struct cpts *cpts; 399d9ba8f9eSMugunthan V N u32 emac_port; 400df828598SMugunthan V N }; 401df828598SMugunthan V N 402d9718546SMugunthan V N struct cpsw_stats { 403d9718546SMugunthan V N char stat_string[ETH_GSTRING_LEN]; 404d9718546SMugunthan V N int type; 405d9718546SMugunthan V N int sizeof_stat; 406d9718546SMugunthan V N int stat_offset; 407d9718546SMugunthan V N }; 408d9718546SMugunthan V N 409d9718546SMugunthan V N enum { 410d9718546SMugunthan V N CPSW_STATS, 411d9718546SMugunthan V N CPDMA_RX_STATS, 412d9718546SMugunthan V N CPDMA_TX_STATS, 413d9718546SMugunthan V N }; 414d9718546SMugunthan V N 415d9718546SMugunthan V N #define CPSW_STAT(m) CPSW_STATS, \ 416d9718546SMugunthan V N sizeof(((struct cpsw_hw_stats *)0)->m), \ 417d9718546SMugunthan V N offsetof(struct cpsw_hw_stats, m) 418d9718546SMugunthan V N #define CPDMA_RX_STAT(m) CPDMA_RX_STATS, \ 419d9718546SMugunthan V N sizeof(((struct cpdma_chan_stats *)0)->m), \ 420d9718546SMugunthan V N offsetof(struct cpdma_chan_stats, m) 421d9718546SMugunthan V N #define CPDMA_TX_STAT(m) CPDMA_TX_STATS, \ 422d9718546SMugunthan V N sizeof(((struct cpdma_chan_stats *)0)->m), \ 423d9718546SMugunthan V N offsetof(struct cpdma_chan_stats, m) 424d9718546SMugunthan V N 425d9718546SMugunthan V N static const struct cpsw_stats cpsw_gstrings_stats[] = { 426d9718546SMugunthan V N { "Good Rx Frames", CPSW_STAT(rxgoodframes) }, 427d9718546SMugunthan V N { "Broadcast Rx Frames", CPSW_STAT(rxbroadcastframes) }, 428d9718546SMugunthan V N { "Multicast Rx Frames", CPSW_STAT(rxmulticastframes) }, 429d9718546SMugunthan V N { "Pause Rx Frames", CPSW_STAT(rxpauseframes) }, 430d9718546SMugunthan V N { "Rx CRC Errors", CPSW_STAT(rxcrcerrors) }, 431d9718546SMugunthan V N { "Rx Align/Code Errors", CPSW_STAT(rxaligncodeerrors) }, 432d9718546SMugunthan V N { "Oversize Rx Frames", CPSW_STAT(rxoversizedframes) }, 433d9718546SMugunthan V N { "Rx Jabbers", CPSW_STAT(rxjabberframes) }, 434d9718546SMugunthan V N { "Undersize (Short) Rx Frames", CPSW_STAT(rxundersizedframes) }, 435d9718546SMugunthan V N { "Rx Fragments", CPSW_STAT(rxfragments) }, 436d9718546SMugunthan V N { "Rx Octets", CPSW_STAT(rxoctets) }, 437d9718546SMugunthan V N { "Good Tx Frames", CPSW_STAT(txgoodframes) }, 438d9718546SMugunthan V N { "Broadcast Tx Frames", CPSW_STAT(txbroadcastframes) }, 439d9718546SMugunthan V N { "Multicast Tx Frames", CPSW_STAT(txmulticastframes) }, 440d9718546SMugunthan V N { "Pause Tx Frames", CPSW_STAT(txpauseframes) }, 441d9718546SMugunthan V N { "Deferred Tx Frames", CPSW_STAT(txdeferredframes) }, 442d9718546SMugunthan V N { "Collisions", CPSW_STAT(txcollisionframes) }, 443d9718546SMugunthan V N { "Single Collision Tx Frames", CPSW_STAT(txsinglecollframes) }, 444d9718546SMugunthan V N { "Multiple Collision Tx Frames", CPSW_STAT(txmultcollframes) }, 445d9718546SMugunthan V N { "Excessive Collisions", CPSW_STAT(txexcessivecollisions) }, 446d9718546SMugunthan V N { "Late Collisions", CPSW_STAT(txlatecollisions) }, 447d9718546SMugunthan V N { "Tx Underrun", CPSW_STAT(txunderrun) }, 448d9718546SMugunthan V N { "Carrier Sense Errors", CPSW_STAT(txcarriersenseerrors) }, 449d9718546SMugunthan V N { "Tx Octets", CPSW_STAT(txoctets) }, 450d9718546SMugunthan V N { "Rx + Tx 64 Octet Frames", CPSW_STAT(octetframes64) }, 451d9718546SMugunthan V N { "Rx + Tx 65-127 Octet Frames", CPSW_STAT(octetframes65t127) }, 452d9718546SMugunthan V N { "Rx + Tx 128-255 Octet Frames", CPSW_STAT(octetframes128t255) }, 453d9718546SMugunthan V N { "Rx + Tx 256-511 Octet Frames", CPSW_STAT(octetframes256t511) }, 454d9718546SMugunthan V N { "Rx + Tx 512-1023 Octet Frames", CPSW_STAT(octetframes512t1023) }, 455d9718546SMugunthan V N { "Rx + Tx 1024-Up Octet Frames", CPSW_STAT(octetframes1024tup) }, 456d9718546SMugunthan V N { "Net Octets", CPSW_STAT(netoctets) }, 457d9718546SMugunthan V N { "Rx Start of Frame Overruns", CPSW_STAT(rxsofoverruns) }, 458d9718546SMugunthan V N { "Rx Middle of Frame Overruns", CPSW_STAT(rxmofoverruns) }, 459d9718546SMugunthan V N { "Rx DMA Overruns", CPSW_STAT(rxdmaoverruns) }, 460d9718546SMugunthan V N { "Rx DMA chan: head_enqueue", CPDMA_RX_STAT(head_enqueue) }, 461d9718546SMugunthan V N { "Rx DMA chan: tail_enqueue", CPDMA_RX_STAT(tail_enqueue) }, 462d9718546SMugunthan V N { "Rx DMA chan: pad_enqueue", CPDMA_RX_STAT(pad_enqueue) }, 463d9718546SMugunthan V N { "Rx DMA chan: misqueued", CPDMA_RX_STAT(misqueued) }, 464d9718546SMugunthan V N { "Rx DMA chan: desc_alloc_fail", CPDMA_RX_STAT(desc_alloc_fail) }, 465d9718546SMugunthan V N { "Rx DMA chan: pad_alloc_fail", CPDMA_RX_STAT(pad_alloc_fail) }, 466d9718546SMugunthan V N { "Rx DMA chan: runt_receive_buf", CPDMA_RX_STAT(runt_receive_buff) }, 467d9718546SMugunthan V N { "Rx DMA chan: runt_transmit_buf", CPDMA_RX_STAT(runt_transmit_buff) }, 468d9718546SMugunthan V N { "Rx DMA chan: empty_dequeue", CPDMA_RX_STAT(empty_dequeue) }, 469d9718546SMugunthan V N { "Rx DMA chan: busy_dequeue", CPDMA_RX_STAT(busy_dequeue) }, 470d9718546SMugunthan V N { "Rx DMA chan: good_dequeue", CPDMA_RX_STAT(good_dequeue) }, 471d9718546SMugunthan V N { "Rx DMA chan: requeue", CPDMA_RX_STAT(requeue) }, 472d9718546SMugunthan V N { "Rx DMA chan: teardown_dequeue", CPDMA_RX_STAT(teardown_dequeue) }, 473d9718546SMugunthan V N { "Tx DMA chan: head_enqueue", CPDMA_TX_STAT(head_enqueue) }, 474d9718546SMugunthan V N { "Tx DMA chan: tail_enqueue", CPDMA_TX_STAT(tail_enqueue) }, 475d9718546SMugunthan V N { "Tx DMA chan: pad_enqueue", CPDMA_TX_STAT(pad_enqueue) }, 476d9718546SMugunthan V N { "Tx DMA chan: misqueued", CPDMA_TX_STAT(misqueued) }, 477d9718546SMugunthan V N { "Tx DMA chan: desc_alloc_fail", CPDMA_TX_STAT(desc_alloc_fail) }, 478d9718546SMugunthan V N { "Tx DMA chan: pad_alloc_fail", CPDMA_TX_STAT(pad_alloc_fail) }, 479d9718546SMugunthan V N { "Tx DMA chan: runt_receive_buf", CPDMA_TX_STAT(runt_receive_buff) }, 480d9718546SMugunthan V N { "Tx DMA chan: runt_transmit_buf", CPDMA_TX_STAT(runt_transmit_buff) }, 481d9718546SMugunthan V N { "Tx DMA chan: empty_dequeue", CPDMA_TX_STAT(empty_dequeue) }, 482d9718546SMugunthan V N { "Tx DMA chan: busy_dequeue", CPDMA_TX_STAT(busy_dequeue) }, 483d9718546SMugunthan V N { "Tx DMA chan: good_dequeue", CPDMA_TX_STAT(good_dequeue) }, 484d9718546SMugunthan V N { "Tx DMA chan: requeue", CPDMA_TX_STAT(requeue) }, 485d9718546SMugunthan V N { "Tx DMA chan: teardown_dequeue", CPDMA_TX_STAT(teardown_dequeue) }, 486d9718546SMugunthan V N }; 487d9718546SMugunthan V N 488d9718546SMugunthan V N #define CPSW_STATS_LEN ARRAY_SIZE(cpsw_gstrings_stats) 489d9718546SMugunthan V N 490df828598SMugunthan V N #define napi_to_priv(napi) container_of(napi, struct cpsw_priv, napi) 491df828598SMugunthan V N #define for_each_slave(priv, func, arg...) \ 492df828598SMugunthan V N do { \ 4936e6ceaedSSebastian Siewior struct cpsw_slave *slave; \ 4946e6ceaedSSebastian Siewior int n; \ 495d9ba8f9eSMugunthan V N if (priv->data.dual_emac) \ 496d9ba8f9eSMugunthan V N (func)((priv)->slaves + priv->emac_port, ##arg);\ 497d9ba8f9eSMugunthan V N else \ 4986e6ceaedSSebastian Siewior for (n = (priv)->data.slaves, \ 4996e6ceaedSSebastian Siewior slave = (priv)->slaves; \ 5006e6ceaedSSebastian Siewior n; n--) \ 5016e6ceaedSSebastian Siewior (func)(slave++, ##arg); \ 502df828598SMugunthan V N } while (0) 503d9ba8f9eSMugunthan V N #define cpsw_get_slave_ndev(priv, __slave_no__) \ 5041973db0dSMugunthan V N ((__slave_no__ < priv->data.slaves) ? \ 5051973db0dSMugunthan V N priv->slaves[__slave_no__].ndev : NULL) 506d9ba8f9eSMugunthan V N #define cpsw_get_slave_priv(priv, __slave_no__) \ 5071973db0dSMugunthan V N (((__slave_no__ < priv->data.slaves) && \ 5081973db0dSMugunthan V N (priv->slaves[__slave_no__].ndev)) ? \ 509d9ba8f9eSMugunthan V N netdev_priv(priv->slaves[__slave_no__].ndev) : NULL) \ 510d9ba8f9eSMugunthan V N 511d9ba8f9eSMugunthan V N #define cpsw_dual_emac_src_port_detect(status, priv, ndev, skb) \ 512d9ba8f9eSMugunthan V N do { \ 513d9ba8f9eSMugunthan V N if (!priv->data.dual_emac) \ 514d9ba8f9eSMugunthan V N break; \ 515d9ba8f9eSMugunthan V N if (CPDMA_RX_SOURCE_PORT(status) == 1) { \ 516d9ba8f9eSMugunthan V N ndev = cpsw_get_slave_ndev(priv, 0); \ 517d9ba8f9eSMugunthan V N priv = netdev_priv(ndev); \ 518d9ba8f9eSMugunthan V N skb->dev = ndev; \ 519d9ba8f9eSMugunthan V N } else if (CPDMA_RX_SOURCE_PORT(status) == 2) { \ 520d9ba8f9eSMugunthan V N ndev = cpsw_get_slave_ndev(priv, 1); \ 521d9ba8f9eSMugunthan V N priv = netdev_priv(ndev); \ 522d9ba8f9eSMugunthan V N skb->dev = ndev; \ 523d9ba8f9eSMugunthan V N } \ 524d9ba8f9eSMugunthan V N } while (0) 525d9ba8f9eSMugunthan V N #define cpsw_add_mcast(priv, addr) \ 526d9ba8f9eSMugunthan V N do { \ 527d9ba8f9eSMugunthan V N if (priv->data.dual_emac) { \ 528d9ba8f9eSMugunthan V N struct cpsw_slave *slave = priv->slaves + \ 529d9ba8f9eSMugunthan V N priv->emac_port; \ 530d9ba8f9eSMugunthan V N int slave_port = cpsw_get_slave_port(priv, \ 531d9ba8f9eSMugunthan V N slave->slave_num); \ 532d9ba8f9eSMugunthan V N cpsw_ale_add_mcast(priv->ale, addr, \ 53371a2cbb7SGrygorii Strashko 1 << slave_port | ALE_PORT_HOST, \ 534d9ba8f9eSMugunthan V N ALE_VLAN, slave->port_vlan, 0); \ 535d9ba8f9eSMugunthan V N } else { \ 536d9ba8f9eSMugunthan V N cpsw_ale_add_mcast(priv->ale, addr, \ 53761f1cef9SGrygorii Strashko ALE_ALL_PORTS, \ 538d9ba8f9eSMugunthan V N 0, 0, 0); \ 539d9ba8f9eSMugunthan V N } \ 540d9ba8f9eSMugunthan V N } while (0) 541d9ba8f9eSMugunthan V N 542d9ba8f9eSMugunthan V N static inline int cpsw_get_slave_port(struct cpsw_priv *priv, u32 slave_num) 543d9ba8f9eSMugunthan V N { 544d9ba8f9eSMugunthan V N return slave_num + 1; 545d9ba8f9eSMugunthan V N } 546df828598SMugunthan V N 5470cd8f9ccSMugunthan V N static void cpsw_set_promiscious(struct net_device *ndev, bool enable) 5480cd8f9ccSMugunthan V N { 5490cd8f9ccSMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 5500cd8f9ccSMugunthan V N struct cpsw_ale *ale = priv->ale; 5510cd8f9ccSMugunthan V N int i; 5520cd8f9ccSMugunthan V N 5530cd8f9ccSMugunthan V N if (priv->data.dual_emac) { 5540cd8f9ccSMugunthan V N bool flag = false; 5550cd8f9ccSMugunthan V N 5560cd8f9ccSMugunthan V N /* Enabling promiscuous mode for one interface will be 5570cd8f9ccSMugunthan V N * common for both the interface as the interface shares 5580cd8f9ccSMugunthan V N * the same hardware resource. 5590cd8f9ccSMugunthan V N */ 5600d961b3bSHeiko Schocher for (i = 0; i < priv->data.slaves; i++) 5610cd8f9ccSMugunthan V N if (priv->slaves[i].ndev->flags & IFF_PROMISC) 5620cd8f9ccSMugunthan V N flag = true; 5630cd8f9ccSMugunthan V N 5640cd8f9ccSMugunthan V N if (!enable && flag) { 5650cd8f9ccSMugunthan V N enable = true; 5660cd8f9ccSMugunthan V N dev_err(&ndev->dev, "promiscuity not disabled as the other interface is still in promiscuity mode\n"); 5670cd8f9ccSMugunthan V N } 5680cd8f9ccSMugunthan V N 5690cd8f9ccSMugunthan V N if (enable) { 5700cd8f9ccSMugunthan V N /* Enable Bypass */ 5710cd8f9ccSMugunthan V N cpsw_ale_control_set(ale, 0, ALE_BYPASS, 1); 5720cd8f9ccSMugunthan V N 5730cd8f9ccSMugunthan V N dev_dbg(&ndev->dev, "promiscuity enabled\n"); 5740cd8f9ccSMugunthan V N } else { 5750cd8f9ccSMugunthan V N /* Disable Bypass */ 5760cd8f9ccSMugunthan V N cpsw_ale_control_set(ale, 0, ALE_BYPASS, 0); 5770cd8f9ccSMugunthan V N dev_dbg(&ndev->dev, "promiscuity disabled\n"); 5780cd8f9ccSMugunthan V N } 5790cd8f9ccSMugunthan V N } else { 5800cd8f9ccSMugunthan V N if (enable) { 5810cd8f9ccSMugunthan V N unsigned long timeout = jiffies + HZ; 5820cd8f9ccSMugunthan V N 5836f979eb3SLennart Sorensen /* Disable Learn for all ports (host is port 0 and slaves are port 1 and up */ 5846f979eb3SLennart Sorensen for (i = 0; i <= priv->data.slaves; i++) { 5850cd8f9ccSMugunthan V N cpsw_ale_control_set(ale, i, 5860cd8f9ccSMugunthan V N ALE_PORT_NOLEARN, 1); 5870cd8f9ccSMugunthan V N cpsw_ale_control_set(ale, i, 5880cd8f9ccSMugunthan V N ALE_PORT_NO_SA_UPDATE, 1); 5890cd8f9ccSMugunthan V N } 5900cd8f9ccSMugunthan V N 5910cd8f9ccSMugunthan V N /* Clear All Untouched entries */ 5920cd8f9ccSMugunthan V N cpsw_ale_control_set(ale, 0, ALE_AGEOUT, 1); 5930cd8f9ccSMugunthan V N do { 5940cd8f9ccSMugunthan V N cpu_relax(); 5950cd8f9ccSMugunthan V N if (cpsw_ale_control_get(ale, 0, ALE_AGEOUT)) 5960cd8f9ccSMugunthan V N break; 5970cd8f9ccSMugunthan V N } while (time_after(timeout, jiffies)); 5980cd8f9ccSMugunthan V N cpsw_ale_control_set(ale, 0, ALE_AGEOUT, 1); 5990cd8f9ccSMugunthan V N 6000cd8f9ccSMugunthan V N /* Clear all mcast from ALE */ 60161f1cef9SGrygorii Strashko cpsw_ale_flush_multicast(ale, ALE_ALL_PORTS, -1); 6020cd8f9ccSMugunthan V N 6030cd8f9ccSMugunthan V N /* Flood All Unicast Packets to Host port */ 6040cd8f9ccSMugunthan V N cpsw_ale_control_set(ale, 0, ALE_P0_UNI_FLOOD, 1); 6050cd8f9ccSMugunthan V N dev_dbg(&ndev->dev, "promiscuity enabled\n"); 6060cd8f9ccSMugunthan V N } else { 6076f979eb3SLennart Sorensen /* Don't Flood All Unicast Packets to Host port */ 6080cd8f9ccSMugunthan V N cpsw_ale_control_set(ale, 0, ALE_P0_UNI_FLOOD, 0); 6090cd8f9ccSMugunthan V N 6106f979eb3SLennart Sorensen /* Enable Learn for all ports (host is port 0 and slaves are port 1 and up */ 6116f979eb3SLennart Sorensen for (i = 0; i <= priv->data.slaves; i++) { 6120cd8f9ccSMugunthan V N cpsw_ale_control_set(ale, i, 6130cd8f9ccSMugunthan V N ALE_PORT_NOLEARN, 0); 6140cd8f9ccSMugunthan V N cpsw_ale_control_set(ale, i, 6150cd8f9ccSMugunthan V N ALE_PORT_NO_SA_UPDATE, 0); 6160cd8f9ccSMugunthan V N } 6170cd8f9ccSMugunthan V N dev_dbg(&ndev->dev, "promiscuity disabled\n"); 6180cd8f9ccSMugunthan V N } 6190cd8f9ccSMugunthan V N } 6200cd8f9ccSMugunthan V N } 6210cd8f9ccSMugunthan V N 6225c50a856SMugunthan V N static void cpsw_ndo_set_rx_mode(struct net_device *ndev) 6235c50a856SMugunthan V N { 6245c50a856SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 62525906052SMugunthan V N int vid; 62625906052SMugunthan V N 62725906052SMugunthan V N if (priv->data.dual_emac) 62825906052SMugunthan V N vid = priv->slaves[priv->emac_port].port_vlan; 62925906052SMugunthan V N else 63025906052SMugunthan V N vid = priv->data.default_vlan; 6315c50a856SMugunthan V N 6325c50a856SMugunthan V N if (ndev->flags & IFF_PROMISC) { 6335c50a856SMugunthan V N /* Enable promiscuous mode */ 6340cd8f9ccSMugunthan V N cpsw_set_promiscious(ndev, true); 6351e5c4bc4SLennart Sorensen cpsw_ale_set_allmulti(priv->ale, IFF_ALLMULTI); 6365c50a856SMugunthan V N return; 6370cd8f9ccSMugunthan V N } else { 6380cd8f9ccSMugunthan V N /* Disable promiscuous mode */ 6390cd8f9ccSMugunthan V N cpsw_set_promiscious(ndev, false); 6405c50a856SMugunthan V N } 6415c50a856SMugunthan V N 6421e5c4bc4SLennart Sorensen /* Restore allmulti on vlans if necessary */ 6431e5c4bc4SLennart Sorensen cpsw_ale_set_allmulti(priv->ale, priv->ndev->flags & IFF_ALLMULTI); 6441e5c4bc4SLennart Sorensen 6455c50a856SMugunthan V N /* Clear all mcast from ALE */ 64661f1cef9SGrygorii Strashko cpsw_ale_flush_multicast(priv->ale, ALE_ALL_PORTS, vid); 6475c50a856SMugunthan V N 6485c50a856SMugunthan V N if (!netdev_mc_empty(ndev)) { 6495c50a856SMugunthan V N struct netdev_hw_addr *ha; 6505c50a856SMugunthan V N 6515c50a856SMugunthan V N /* program multicast address list into ALE register */ 6525c50a856SMugunthan V N netdev_for_each_mc_addr(ha, ndev) { 653d9ba8f9eSMugunthan V N cpsw_add_mcast(priv, (u8 *)ha->addr); 6545c50a856SMugunthan V N } 6555c50a856SMugunthan V N } 6565c50a856SMugunthan V N } 6575c50a856SMugunthan V N 658df828598SMugunthan V N static void cpsw_intr_enable(struct cpsw_priv *priv) 659df828598SMugunthan V N { 660996a5c27SRichard Cochran __raw_writel(0xFF, &priv->wr_regs->tx_en); 661996a5c27SRichard Cochran __raw_writel(0xFF, &priv->wr_regs->rx_en); 662df828598SMugunthan V N 663df828598SMugunthan V N cpdma_ctlr_int_ctrl(priv->dma, true); 664df828598SMugunthan V N return; 665df828598SMugunthan V N } 666df828598SMugunthan V N 667df828598SMugunthan V N static void cpsw_intr_disable(struct cpsw_priv *priv) 668df828598SMugunthan V N { 669996a5c27SRichard Cochran __raw_writel(0, &priv->wr_regs->tx_en); 670996a5c27SRichard Cochran __raw_writel(0, &priv->wr_regs->rx_en); 671df828598SMugunthan V N 672df828598SMugunthan V N cpdma_ctlr_int_ctrl(priv->dma, false); 673df828598SMugunthan V N return; 674df828598SMugunthan V N } 675df828598SMugunthan V N 6761a3b5056SOlof Johansson static void cpsw_tx_handler(void *token, int len, int status) 677df828598SMugunthan V N { 678df828598SMugunthan V N struct sk_buff *skb = token; 679df828598SMugunthan V N struct net_device *ndev = skb->dev; 680df828598SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 681df828598SMugunthan V N 682fae50823SMugunthan V N /* Check whether the queue is stopped due to stalled tx dma, if the 683fae50823SMugunthan V N * queue is stopped then start the queue as we have free desc for tx 684fae50823SMugunthan V N */ 685df828598SMugunthan V N if (unlikely(netif_queue_stopped(ndev))) 686b56d6b3fSMugunthan V N netif_wake_queue(ndev); 6879232b16dSMugunthan V N cpts_tx_timestamp(priv->cpts, skb); 6888dc43ddcSTobias Klauser ndev->stats.tx_packets++; 6898dc43ddcSTobias Klauser ndev->stats.tx_bytes += len; 690df828598SMugunthan V N dev_kfree_skb_any(skb); 691df828598SMugunthan V N } 692df828598SMugunthan V N 6931a3b5056SOlof Johansson static void cpsw_rx_handler(void *token, int len, int status) 694df828598SMugunthan V N { 695df828598SMugunthan V N struct sk_buff *skb = token; 696b4727e69SSebastian Siewior struct sk_buff *new_skb; 697df828598SMugunthan V N struct net_device *ndev = skb->dev; 698df828598SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 699df828598SMugunthan V N int ret = 0; 700df828598SMugunthan V N 701d9ba8f9eSMugunthan V N cpsw_dual_emac_src_port_detect(status, priv, ndev, skb); 702d9ba8f9eSMugunthan V N 70316e5c57dSMugunthan V N if (unlikely(status < 0) || unlikely(!netif_running(ndev))) { 704a0e2c822SMugunthan V N bool ndev_status = false; 705a0e2c822SMugunthan V N struct cpsw_slave *slave = priv->slaves; 706a0e2c822SMugunthan V N int n; 707a0e2c822SMugunthan V N 708a0e2c822SMugunthan V N if (priv->data.dual_emac) { 709a0e2c822SMugunthan V N /* In dual emac mode check for all interfaces */ 710a0e2c822SMugunthan V N for (n = priv->data.slaves; n; n--, slave++) 711a0e2c822SMugunthan V N if (netif_running(slave->ndev)) 712a0e2c822SMugunthan V N ndev_status = true; 713a0e2c822SMugunthan V N } 714a0e2c822SMugunthan V N 715a0e2c822SMugunthan V N if (ndev_status && (status >= 0)) { 716a0e2c822SMugunthan V N /* The packet received is for the interface which 717a0e2c822SMugunthan V N * is already down and the other interface is up 718dbedd44eSJoe Perches * and running, instead of freeing which results 719a0e2c822SMugunthan V N * in reducing of the number of rx descriptor in 720a0e2c822SMugunthan V N * DMA engine, requeue skb back to cpdma. 721a0e2c822SMugunthan V N */ 722a0e2c822SMugunthan V N new_skb = skb; 723a0e2c822SMugunthan V N goto requeue; 724a0e2c822SMugunthan V N } 725a0e2c822SMugunthan V N 726b4727e69SSebastian Siewior /* the interface is going down, skbs are purged */ 727df828598SMugunthan V N dev_kfree_skb_any(skb); 728df828598SMugunthan V N return; 729df828598SMugunthan V N } 730b4727e69SSebastian Siewior 731b4727e69SSebastian Siewior new_skb = netdev_alloc_skb_ip_align(ndev, priv->rx_packet_max); 732b4727e69SSebastian Siewior if (new_skb) { 733df828598SMugunthan V N skb_put(skb, len); 7349232b16dSMugunthan V N cpts_rx_timestamp(priv->cpts, skb); 735df828598SMugunthan V N skb->protocol = eth_type_trans(skb, ndev); 736df828598SMugunthan V N netif_receive_skb(skb); 7378dc43ddcSTobias Klauser ndev->stats.rx_bytes += len; 7388dc43ddcSTobias Klauser ndev->stats.rx_packets++; 739b4727e69SSebastian Siewior } else { 7408dc43ddcSTobias Klauser ndev->stats.rx_dropped++; 741b4727e69SSebastian Siewior new_skb = skb; 742df828598SMugunthan V N } 743df828598SMugunthan V N 744a0e2c822SMugunthan V N requeue: 745b4727e69SSebastian Siewior ret = cpdma_chan_submit(priv->rxch, new_skb, new_skb->data, 746b4727e69SSebastian Siewior skb_tailroom(new_skb), 0); 747b4727e69SSebastian Siewior if (WARN_ON(ret < 0)) 748b4727e69SSebastian Siewior dev_kfree_skb_any(new_skb); 749df828598SMugunthan V N } 750df828598SMugunthan V N 751c03abd84SFelipe Balbi static irqreturn_t cpsw_tx_interrupt(int irq, void *dev_id) 752df828598SMugunthan V N { 753df828598SMugunthan V N struct cpsw_priv *priv = dev_id; 7547ce67a38SFelipe Balbi 75532a7432cSMugunthan V N writel(0, &priv->wr_regs->tx_en); 756c03abd84SFelipe Balbi cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_TX); 757c03abd84SFelipe Balbi 7587da11600SMugunthan V N if (priv->quirk_irq) { 7597da11600SMugunthan V N disable_irq_nosync(priv->irqs_table[1]); 7607da11600SMugunthan V N priv->tx_irq_disabled = true; 7617da11600SMugunthan V N } 7627da11600SMugunthan V N 76332a7432cSMugunthan V N napi_schedule(&priv->napi_tx); 764c03abd84SFelipe Balbi return IRQ_HANDLED; 765c03abd84SFelipe Balbi } 766c03abd84SFelipe Balbi 767c03abd84SFelipe Balbi static irqreturn_t cpsw_rx_interrupt(int irq, void *dev_id) 768c03abd84SFelipe Balbi { 769c03abd84SFelipe Balbi struct cpsw_priv *priv = dev_id; 770c03abd84SFelipe Balbi 771c03abd84SFelipe Balbi cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_RX); 772870915feSMugunthan V N writel(0, &priv->wr_regs->rx_en); 773fd51cf19SSebastian Siewior 7747da11600SMugunthan V N if (priv->quirk_irq) { 7757da11600SMugunthan V N disable_irq_nosync(priv->irqs_table[0]); 7767da11600SMugunthan V N priv->rx_irq_disabled = true; 7777da11600SMugunthan V N } 7787da11600SMugunthan V N 77932a7432cSMugunthan V N napi_schedule(&priv->napi_rx); 780df828598SMugunthan V N return IRQ_HANDLED; 781df828598SMugunthan V N } 782df828598SMugunthan V N 78332a7432cSMugunthan V N static int cpsw_tx_poll(struct napi_struct *napi_tx, int budget) 784df828598SMugunthan V N { 78532a7432cSMugunthan V N struct cpsw_priv *priv = napi_to_priv(napi_tx); 78632a7432cSMugunthan V N int num_tx; 78732a7432cSMugunthan V N 78832a7432cSMugunthan V N num_tx = cpdma_chan_process(priv->txch, budget); 78932a7432cSMugunthan V N if (num_tx < budget) { 79032a7432cSMugunthan V N napi_complete(napi_tx); 79132a7432cSMugunthan V N writel(0xff, &priv->wr_regs->tx_en); 7927da11600SMugunthan V N if (priv->quirk_irq && priv->tx_irq_disabled) { 7937da11600SMugunthan V N priv->tx_irq_disabled = false; 7947da11600SMugunthan V N enable_irq(priv->irqs_table[1]); 7957da11600SMugunthan V N } 79632a7432cSMugunthan V N } 79732a7432cSMugunthan V N 79832a7432cSMugunthan V N if (num_tx) 79932a7432cSMugunthan V N cpsw_dbg(priv, intr, "poll %d tx pkts\n", num_tx); 80032a7432cSMugunthan V N 80132a7432cSMugunthan V N return num_tx; 80232a7432cSMugunthan V N } 80332a7432cSMugunthan V N 80432a7432cSMugunthan V N static int cpsw_rx_poll(struct napi_struct *napi_rx, int budget) 80532a7432cSMugunthan V N { 80632a7432cSMugunthan V N struct cpsw_priv *priv = napi_to_priv(napi_rx); 8071e353cddSMugunthan V N int num_rx; 808510a1e72SMugunthan V N 809df828598SMugunthan V N num_rx = cpdma_chan_process(priv->rxch, budget); 810510a1e72SMugunthan V N if (num_rx < budget) { 81132a7432cSMugunthan V N napi_complete(napi_rx); 812870915feSMugunthan V N writel(0xff, &priv->wr_regs->rx_en); 8137da11600SMugunthan V N if (priv->quirk_irq && priv->rx_irq_disabled) { 8147da11600SMugunthan V N priv->rx_irq_disabled = false; 8157da11600SMugunthan V N enable_irq(priv->irqs_table[0]); 8167da11600SMugunthan V N } 817510a1e72SMugunthan V N } 818df828598SMugunthan V N 8191e353cddSMugunthan V N if (num_rx) 8201e353cddSMugunthan V N cpsw_dbg(priv, intr, "poll %d rx pkts\n", num_rx); 821df828598SMugunthan V N 822df828598SMugunthan V N return num_rx; 823df828598SMugunthan V N } 824df828598SMugunthan V N 825df828598SMugunthan V N static inline void soft_reset(const char *module, void __iomem *reg) 826df828598SMugunthan V N { 827df828598SMugunthan V N unsigned long timeout = jiffies + HZ; 828df828598SMugunthan V N 829df828598SMugunthan V N __raw_writel(1, reg); 830df828598SMugunthan V N do { 831df828598SMugunthan V N cpu_relax(); 832df828598SMugunthan V N } while ((__raw_readl(reg) & 1) && time_after(timeout, jiffies)); 833df828598SMugunthan V N 834df828598SMugunthan V N WARN(__raw_readl(reg) & 1, "failed to soft-reset %s\n", module); 835df828598SMugunthan V N } 836df828598SMugunthan V N 837df828598SMugunthan V N #define mac_hi(mac) (((mac)[0] << 0) | ((mac)[1] << 8) | \ 838df828598SMugunthan V N ((mac)[2] << 16) | ((mac)[3] << 24)) 839df828598SMugunthan V N #define mac_lo(mac) (((mac)[4] << 0) | ((mac)[5] << 8)) 840df828598SMugunthan V N 841df828598SMugunthan V N static void cpsw_set_slave_mac(struct cpsw_slave *slave, 842df828598SMugunthan V N struct cpsw_priv *priv) 843df828598SMugunthan V N { 8449750a3adSRichard Cochran slave_write(slave, mac_hi(priv->mac_addr), SA_HI); 8459750a3adSRichard Cochran slave_write(slave, mac_lo(priv->mac_addr), SA_LO); 846df828598SMugunthan V N } 847df828598SMugunthan V N 848df828598SMugunthan V N static void _cpsw_adjust_link(struct cpsw_slave *slave, 849df828598SMugunthan V N struct cpsw_priv *priv, bool *link) 850df828598SMugunthan V N { 851df828598SMugunthan V N struct phy_device *phy = slave->phy; 852df828598SMugunthan V N u32 mac_control = 0; 853df828598SMugunthan V N u32 slave_port; 854df828598SMugunthan V N 855df828598SMugunthan V N if (!phy) 856df828598SMugunthan V N return; 857df828598SMugunthan V N 858df828598SMugunthan V N slave_port = cpsw_get_slave_port(priv, slave->slave_num); 859df828598SMugunthan V N 860df828598SMugunthan V N if (phy->link) { 861df828598SMugunthan V N mac_control = priv->data.mac_control; 862df828598SMugunthan V N 863df828598SMugunthan V N /* enable forwarding */ 864df828598SMugunthan V N cpsw_ale_control_set(priv->ale, slave_port, 865df828598SMugunthan V N ALE_PORT_STATE, ALE_PORT_STATE_FORWARD); 866df828598SMugunthan V N 867df828598SMugunthan V N if (phy->speed == 1000) 868df828598SMugunthan V N mac_control |= BIT(7); /* GIGABITEN */ 869df828598SMugunthan V N if (phy->duplex) 870df828598SMugunthan V N mac_control |= BIT(0); /* FULLDUPLEXEN */ 871342b7b74SDaniel Mack 872342b7b74SDaniel Mack /* set speed_in input in case RMII mode is used in 100Mbps */ 873342b7b74SDaniel Mack if (phy->speed == 100) 874342b7b74SDaniel Mack mac_control |= BIT(15); 875a81d8762SMugunthan V N else if (phy->speed == 10) 876a81d8762SMugunthan V N mac_control |= BIT(18); /* In Band mode */ 877342b7b74SDaniel Mack 8781923d6e4SMugunthan V N if (priv->rx_pause) 8791923d6e4SMugunthan V N mac_control |= BIT(3); 8801923d6e4SMugunthan V N 8811923d6e4SMugunthan V N if (priv->tx_pause) 8821923d6e4SMugunthan V N mac_control |= BIT(4); 8831923d6e4SMugunthan V N 884df828598SMugunthan V N *link = true; 885df828598SMugunthan V N } else { 886df828598SMugunthan V N mac_control = 0; 887df828598SMugunthan V N /* disable forwarding */ 888df828598SMugunthan V N cpsw_ale_control_set(priv->ale, slave_port, 889df828598SMugunthan V N ALE_PORT_STATE, ALE_PORT_STATE_DISABLE); 890df828598SMugunthan V N } 891df828598SMugunthan V N 892df828598SMugunthan V N if (mac_control != slave->mac_control) { 893df828598SMugunthan V N phy_print_status(phy); 894df828598SMugunthan V N __raw_writel(mac_control, &slave->sliver->mac_control); 895df828598SMugunthan V N } 896df828598SMugunthan V N 897df828598SMugunthan V N slave->mac_control = mac_control; 898df828598SMugunthan V N } 899df828598SMugunthan V N 900df828598SMugunthan V N static void cpsw_adjust_link(struct net_device *ndev) 901df828598SMugunthan V N { 902df828598SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 903df828598SMugunthan V N bool link = false; 904df828598SMugunthan V N 905df828598SMugunthan V N for_each_slave(priv, _cpsw_adjust_link, priv, &link); 906df828598SMugunthan V N 907df828598SMugunthan V N if (link) { 908df828598SMugunthan V N netif_carrier_on(ndev); 909df828598SMugunthan V N if (netif_running(ndev)) 910df828598SMugunthan V N netif_wake_queue(ndev); 911df828598SMugunthan V N } else { 912df828598SMugunthan V N netif_carrier_off(ndev); 913df828598SMugunthan V N netif_stop_queue(ndev); 914df828598SMugunthan V N } 915df828598SMugunthan V N } 916df828598SMugunthan V N 917ff5b8ef2SMugunthan V N static int cpsw_get_coalesce(struct net_device *ndev, 918ff5b8ef2SMugunthan V N struct ethtool_coalesce *coal) 919ff5b8ef2SMugunthan V N { 920ff5b8ef2SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 921ff5b8ef2SMugunthan V N 922ff5b8ef2SMugunthan V N coal->rx_coalesce_usecs = priv->coal_intvl; 923ff5b8ef2SMugunthan V N return 0; 924ff5b8ef2SMugunthan V N } 925ff5b8ef2SMugunthan V N 926ff5b8ef2SMugunthan V N static int cpsw_set_coalesce(struct net_device *ndev, 927ff5b8ef2SMugunthan V N struct ethtool_coalesce *coal) 928ff5b8ef2SMugunthan V N { 929ff5b8ef2SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 930ff5b8ef2SMugunthan V N u32 int_ctrl; 931ff5b8ef2SMugunthan V N u32 num_interrupts = 0; 932ff5b8ef2SMugunthan V N u32 prescale = 0; 933ff5b8ef2SMugunthan V N u32 addnl_dvdr = 1; 934ff5b8ef2SMugunthan V N u32 coal_intvl = 0; 935ff5b8ef2SMugunthan V N 936ff5b8ef2SMugunthan V N coal_intvl = coal->rx_coalesce_usecs; 937ff5b8ef2SMugunthan V N 938ff5b8ef2SMugunthan V N int_ctrl = readl(&priv->wr_regs->int_control); 939ff5b8ef2SMugunthan V N prescale = priv->bus_freq_mhz * 4; 940ff5b8ef2SMugunthan V N 941a84bc2a9SMugunthan V N if (!coal->rx_coalesce_usecs) { 942a84bc2a9SMugunthan V N int_ctrl &= ~(CPSW_INTPRESCALE_MASK | CPSW_INTPACEEN); 943a84bc2a9SMugunthan V N goto update_return; 944a84bc2a9SMugunthan V N } 945a84bc2a9SMugunthan V N 946ff5b8ef2SMugunthan V N if (coal_intvl < CPSW_CMINTMIN_INTVL) 947ff5b8ef2SMugunthan V N coal_intvl = CPSW_CMINTMIN_INTVL; 948ff5b8ef2SMugunthan V N 949ff5b8ef2SMugunthan V N if (coal_intvl > CPSW_CMINTMAX_INTVL) { 950ff5b8ef2SMugunthan V N /* Interrupt pacer works with 4us Pulse, we can 951ff5b8ef2SMugunthan V N * throttle further by dilating the 4us pulse. 952ff5b8ef2SMugunthan V N */ 953ff5b8ef2SMugunthan V N addnl_dvdr = CPSW_INTPRESCALE_MASK / prescale; 954ff5b8ef2SMugunthan V N 955ff5b8ef2SMugunthan V N if (addnl_dvdr > 1) { 956ff5b8ef2SMugunthan V N prescale *= addnl_dvdr; 957ff5b8ef2SMugunthan V N if (coal_intvl > (CPSW_CMINTMAX_INTVL * addnl_dvdr)) 958ff5b8ef2SMugunthan V N coal_intvl = (CPSW_CMINTMAX_INTVL 959ff5b8ef2SMugunthan V N * addnl_dvdr); 960ff5b8ef2SMugunthan V N } else { 961ff5b8ef2SMugunthan V N addnl_dvdr = 1; 962ff5b8ef2SMugunthan V N coal_intvl = CPSW_CMINTMAX_INTVL; 963ff5b8ef2SMugunthan V N } 964ff5b8ef2SMugunthan V N } 965ff5b8ef2SMugunthan V N 966ff5b8ef2SMugunthan V N num_interrupts = (1000 * addnl_dvdr) / coal_intvl; 967ff5b8ef2SMugunthan V N writel(num_interrupts, &priv->wr_regs->rx_imax); 968ff5b8ef2SMugunthan V N writel(num_interrupts, &priv->wr_regs->tx_imax); 969ff5b8ef2SMugunthan V N 970ff5b8ef2SMugunthan V N int_ctrl |= CPSW_INTPACEEN; 971ff5b8ef2SMugunthan V N int_ctrl &= (~CPSW_INTPRESCALE_MASK); 972ff5b8ef2SMugunthan V N int_ctrl |= (prescale & CPSW_INTPRESCALE_MASK); 973a84bc2a9SMugunthan V N 974a84bc2a9SMugunthan V N update_return: 975ff5b8ef2SMugunthan V N writel(int_ctrl, &priv->wr_regs->int_control); 976ff5b8ef2SMugunthan V N 977ff5b8ef2SMugunthan V N cpsw_notice(priv, timer, "Set coalesce to %d usecs.\n", coal_intvl); 978ff5b8ef2SMugunthan V N if (priv->data.dual_emac) { 979ff5b8ef2SMugunthan V N int i; 980ff5b8ef2SMugunthan V N 981ff5b8ef2SMugunthan V N for (i = 0; i < priv->data.slaves; i++) { 982ff5b8ef2SMugunthan V N priv = netdev_priv(priv->slaves[i].ndev); 983ff5b8ef2SMugunthan V N priv->coal_intvl = coal_intvl; 984ff5b8ef2SMugunthan V N } 985ff5b8ef2SMugunthan V N } else { 986ff5b8ef2SMugunthan V N priv->coal_intvl = coal_intvl; 987ff5b8ef2SMugunthan V N } 988ff5b8ef2SMugunthan V N 989ff5b8ef2SMugunthan V N return 0; 990ff5b8ef2SMugunthan V N } 991ff5b8ef2SMugunthan V N 992d9718546SMugunthan V N static int cpsw_get_sset_count(struct net_device *ndev, int sset) 993d9718546SMugunthan V N { 994d9718546SMugunthan V N switch (sset) { 995d9718546SMugunthan V N case ETH_SS_STATS: 996d9718546SMugunthan V N return CPSW_STATS_LEN; 997d9718546SMugunthan V N default: 998d9718546SMugunthan V N return -EOPNOTSUPP; 999d9718546SMugunthan V N } 1000d9718546SMugunthan V N } 1001d9718546SMugunthan V N 1002d9718546SMugunthan V N static void cpsw_get_strings(struct net_device *ndev, u32 stringset, u8 *data) 1003d9718546SMugunthan V N { 1004d9718546SMugunthan V N u8 *p = data; 1005d9718546SMugunthan V N int i; 1006d9718546SMugunthan V N 1007d9718546SMugunthan V N switch (stringset) { 1008d9718546SMugunthan V N case ETH_SS_STATS: 1009d9718546SMugunthan V N for (i = 0; i < CPSW_STATS_LEN; i++) { 1010d9718546SMugunthan V N memcpy(p, cpsw_gstrings_stats[i].stat_string, 1011d9718546SMugunthan V N ETH_GSTRING_LEN); 1012d9718546SMugunthan V N p += ETH_GSTRING_LEN; 1013d9718546SMugunthan V N } 1014d9718546SMugunthan V N break; 1015d9718546SMugunthan V N } 1016d9718546SMugunthan V N } 1017d9718546SMugunthan V N 1018d9718546SMugunthan V N static void cpsw_get_ethtool_stats(struct net_device *ndev, 1019d9718546SMugunthan V N struct ethtool_stats *stats, u64 *data) 1020d9718546SMugunthan V N { 1021d9718546SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 1022d9718546SMugunthan V N struct cpdma_chan_stats rx_stats; 1023d9718546SMugunthan V N struct cpdma_chan_stats tx_stats; 1024d9718546SMugunthan V N u32 val; 1025d9718546SMugunthan V N u8 *p; 1026d9718546SMugunthan V N int i; 1027d9718546SMugunthan V N 1028d9718546SMugunthan V N /* Collect Davinci CPDMA stats for Rx and Tx Channel */ 1029d9718546SMugunthan V N cpdma_chan_get_stats(priv->rxch, &rx_stats); 1030d9718546SMugunthan V N cpdma_chan_get_stats(priv->txch, &tx_stats); 1031d9718546SMugunthan V N 1032d9718546SMugunthan V N for (i = 0; i < CPSW_STATS_LEN; i++) { 1033d9718546SMugunthan V N switch (cpsw_gstrings_stats[i].type) { 1034d9718546SMugunthan V N case CPSW_STATS: 1035d9718546SMugunthan V N val = readl(priv->hw_stats + 1036d9718546SMugunthan V N cpsw_gstrings_stats[i].stat_offset); 1037d9718546SMugunthan V N data[i] = val; 1038d9718546SMugunthan V N break; 1039d9718546SMugunthan V N 1040d9718546SMugunthan V N case CPDMA_RX_STATS: 1041d9718546SMugunthan V N p = (u8 *)&rx_stats + 1042d9718546SMugunthan V N cpsw_gstrings_stats[i].stat_offset; 1043d9718546SMugunthan V N data[i] = *(u32 *)p; 1044d9718546SMugunthan V N break; 1045d9718546SMugunthan V N 1046d9718546SMugunthan V N case CPDMA_TX_STATS: 1047d9718546SMugunthan V N p = (u8 *)&tx_stats + 1048d9718546SMugunthan V N cpsw_gstrings_stats[i].stat_offset; 1049d9718546SMugunthan V N data[i] = *(u32 *)p; 1050d9718546SMugunthan V N break; 1051d9718546SMugunthan V N } 1052d9718546SMugunthan V N } 1053d9718546SMugunthan V N } 1054d9718546SMugunthan V N 1055d9ba8f9eSMugunthan V N static int cpsw_common_res_usage_state(struct cpsw_priv *priv) 1056d9ba8f9eSMugunthan V N { 1057d9ba8f9eSMugunthan V N u32 i; 1058d9ba8f9eSMugunthan V N u32 usage_count = 0; 1059d9ba8f9eSMugunthan V N 1060d9ba8f9eSMugunthan V N if (!priv->data.dual_emac) 1061d9ba8f9eSMugunthan V N return 0; 1062d9ba8f9eSMugunthan V N 1063d9ba8f9eSMugunthan V N for (i = 0; i < priv->data.slaves; i++) 1064d9ba8f9eSMugunthan V N if (priv->slaves[i].open_stat) 1065d9ba8f9eSMugunthan V N usage_count++; 1066d9ba8f9eSMugunthan V N 1067d9ba8f9eSMugunthan V N return usage_count; 1068d9ba8f9eSMugunthan V N } 1069d9ba8f9eSMugunthan V N 1070d9ba8f9eSMugunthan V N static inline int cpsw_tx_packet_submit(struct net_device *ndev, 1071d9ba8f9eSMugunthan V N struct cpsw_priv *priv, struct sk_buff *skb) 1072d9ba8f9eSMugunthan V N { 1073d9ba8f9eSMugunthan V N if (!priv->data.dual_emac) 1074d9ba8f9eSMugunthan V N return cpdma_chan_submit(priv->txch, skb, skb->data, 1075aef614e1SSebastian Siewior skb->len, 0); 1076d9ba8f9eSMugunthan V N 1077d9ba8f9eSMugunthan V N if (ndev == cpsw_get_slave_ndev(priv, 0)) 1078d9ba8f9eSMugunthan V N return cpdma_chan_submit(priv->txch, skb, skb->data, 1079aef614e1SSebastian Siewior skb->len, 1); 1080d9ba8f9eSMugunthan V N else 1081d9ba8f9eSMugunthan V N return cpdma_chan_submit(priv->txch, skb, skb->data, 1082aef614e1SSebastian Siewior skb->len, 2); 1083d9ba8f9eSMugunthan V N } 1084d9ba8f9eSMugunthan V N 1085d9ba8f9eSMugunthan V N static inline void cpsw_add_dual_emac_def_ale_entries( 1086d9ba8f9eSMugunthan V N struct cpsw_priv *priv, struct cpsw_slave *slave, 1087d9ba8f9eSMugunthan V N u32 slave_port) 1088d9ba8f9eSMugunthan V N { 108971a2cbb7SGrygorii Strashko u32 port_mask = 1 << slave_port | ALE_PORT_HOST; 1090d9ba8f9eSMugunthan V N 1091d9ba8f9eSMugunthan V N if (priv->version == CPSW_VERSION_1) 1092d9ba8f9eSMugunthan V N slave_write(slave, slave->port_vlan, CPSW1_PORT_VLAN); 1093d9ba8f9eSMugunthan V N else 1094d9ba8f9eSMugunthan V N slave_write(slave, slave->port_vlan, CPSW2_PORT_VLAN); 1095d9ba8f9eSMugunthan V N cpsw_ale_add_vlan(priv->ale, slave->port_vlan, port_mask, 1096d9ba8f9eSMugunthan V N port_mask, port_mask, 0); 1097d9ba8f9eSMugunthan V N cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast, 1098d9ba8f9eSMugunthan V N port_mask, ALE_VLAN, slave->port_vlan, 0); 1099d9ba8f9eSMugunthan V N cpsw_ale_add_ucast(priv->ale, priv->mac_addr, 110071a2cbb7SGrygorii Strashko HOST_PORT_NUM, ALE_VLAN | ALE_SECURE, slave->port_vlan); 1101d9ba8f9eSMugunthan V N } 1102d9ba8f9eSMugunthan V N 11031e7a2e21SDaniel Mack static void soft_reset_slave(struct cpsw_slave *slave) 1104df828598SMugunthan V N { 1105df828598SMugunthan V N char name[32]; 11061e7a2e21SDaniel Mack 11071e7a2e21SDaniel Mack snprintf(name, sizeof(name), "slave-%d", slave->slave_num); 11081e7a2e21SDaniel Mack soft_reset(name, &slave->sliver->soft_reset); 11091e7a2e21SDaniel Mack } 11101e7a2e21SDaniel Mack 11111e7a2e21SDaniel Mack static void cpsw_slave_open(struct cpsw_slave *slave, struct cpsw_priv *priv) 11121e7a2e21SDaniel Mack { 1113df828598SMugunthan V N u32 slave_port; 1114df828598SMugunthan V N 11151e7a2e21SDaniel Mack soft_reset_slave(slave); 1116df828598SMugunthan V N 1117df828598SMugunthan V N /* setup priority mapping */ 1118df828598SMugunthan V N __raw_writel(RX_PRIORITY_MAPPING, &slave->sliver->rx_pri_map); 11199750a3adSRichard Cochran 11209750a3adSRichard Cochran switch (priv->version) { 11219750a3adSRichard Cochran case CPSW_VERSION_1: 11229750a3adSRichard Cochran slave_write(slave, TX_PRIORITY_MAPPING, CPSW1_TX_PRI_MAP); 11239750a3adSRichard Cochran break; 11249750a3adSRichard Cochran case CPSW_VERSION_2: 1125c193f365SMugunthan V N case CPSW_VERSION_3: 1126926489beSMugunthan V N case CPSW_VERSION_4: 11279750a3adSRichard Cochran slave_write(slave, TX_PRIORITY_MAPPING, CPSW2_TX_PRI_MAP); 11289750a3adSRichard Cochran break; 11299750a3adSRichard Cochran } 1130df828598SMugunthan V N 1131df828598SMugunthan V N /* setup max packet size, and mac address */ 1132df828598SMugunthan V N __raw_writel(priv->rx_packet_max, &slave->sliver->rx_maxlen); 1133df828598SMugunthan V N cpsw_set_slave_mac(slave, priv); 1134df828598SMugunthan V N 1135df828598SMugunthan V N slave->mac_control = 0; /* no link yet */ 1136df828598SMugunthan V N 1137df828598SMugunthan V N slave_port = cpsw_get_slave_port(priv, slave->slave_num); 1138df828598SMugunthan V N 1139d9ba8f9eSMugunthan V N if (priv->data.dual_emac) 1140d9ba8f9eSMugunthan V N cpsw_add_dual_emac_def_ale_entries(priv, slave, slave_port); 1141d9ba8f9eSMugunthan V N else 1142df828598SMugunthan V N cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast, 1143e11b220fSMugunthan V N 1 << slave_port, 0, 0, ALE_MCAST_FWD_2); 1144df828598SMugunthan V N 11459e42f715SHeiko Schocher if (priv->phy_node) 11469e42f715SHeiko Schocher slave->phy = of_phy_connect(priv->ndev, priv->phy_node, 11479e42f715SHeiko Schocher &cpsw_adjust_link, 0, slave->data->phy_if); 11489e42f715SHeiko Schocher else 1149df828598SMugunthan V N slave->phy = phy_connect(priv->ndev, slave->data->phy_id, 1150f9a8f83bSFlorian Fainelli &cpsw_adjust_link, slave->data->phy_if); 1151df828598SMugunthan V N if (IS_ERR(slave->phy)) { 1152df828598SMugunthan V N dev_err(priv->dev, "phy %s not found on slave %d\n", 1153df828598SMugunthan V N slave->data->phy_id, slave->slave_num); 1154df828598SMugunthan V N slave->phy = NULL; 1155df828598SMugunthan V N } else { 11562220943aSAndrew Lunn phy_attached_info(slave->phy); 11572220943aSAndrew Lunn 1158df828598SMugunthan V N phy_start(slave->phy); 1159388367a5SMugunthan V N 1160388367a5SMugunthan V N /* Configure GMII_SEL register */ 1161388367a5SMugunthan V N cpsw_phy_sel(&priv->pdev->dev, slave->phy->interface, 1162388367a5SMugunthan V N slave->slave_num); 1163df828598SMugunthan V N } 1164df828598SMugunthan V N } 1165df828598SMugunthan V N 11663b72c2feSMugunthan V N static inline void cpsw_add_default_vlan(struct cpsw_priv *priv) 11673b72c2feSMugunthan V N { 11683b72c2feSMugunthan V N const int vlan = priv->data.default_vlan; 11693b72c2feSMugunthan V N u32 reg; 11703b72c2feSMugunthan V N int i; 11711e5c4bc4SLennart Sorensen int unreg_mcast_mask; 11723b72c2feSMugunthan V N 11733b72c2feSMugunthan V N reg = (priv->version == CPSW_VERSION_1) ? CPSW1_PORT_VLAN : 11743b72c2feSMugunthan V N CPSW2_PORT_VLAN; 11753b72c2feSMugunthan V N 11763b72c2feSMugunthan V N writel(vlan, &priv->host_port_regs->port_vlan); 11773b72c2feSMugunthan V N 11780237c110SDaniel Mack for (i = 0; i < priv->data.slaves; i++) 11793b72c2feSMugunthan V N slave_write(priv->slaves + i, vlan, reg); 11803b72c2feSMugunthan V N 11811e5c4bc4SLennart Sorensen if (priv->ndev->flags & IFF_ALLMULTI) 11821e5c4bc4SLennart Sorensen unreg_mcast_mask = ALE_ALL_PORTS; 11831e5c4bc4SLennart Sorensen else 11841e5c4bc4SLennart Sorensen unreg_mcast_mask = ALE_PORT_1 | ALE_PORT_2; 11851e5c4bc4SLennart Sorensen 118661f1cef9SGrygorii Strashko cpsw_ale_add_vlan(priv->ale, vlan, ALE_ALL_PORTS, 118761f1cef9SGrygorii Strashko ALE_ALL_PORTS, ALE_ALL_PORTS, 118861f1cef9SGrygorii Strashko unreg_mcast_mask); 11893b72c2feSMugunthan V N } 11903b72c2feSMugunthan V N 1191df828598SMugunthan V N static void cpsw_init_host_port(struct cpsw_priv *priv) 1192df828598SMugunthan V N { 11933b72c2feSMugunthan V N u32 control_reg; 1194d9ba8f9eSMugunthan V N u32 fifo_mode; 11953b72c2feSMugunthan V N 1196df828598SMugunthan V N /* soft reset the controller and initialize ale */ 1197df828598SMugunthan V N soft_reset("cpsw", &priv->regs->soft_reset); 1198df828598SMugunthan V N cpsw_ale_start(priv->ale); 1199df828598SMugunthan V N 1200df828598SMugunthan V N /* switch to vlan unaware mode */ 120171a2cbb7SGrygorii Strashko cpsw_ale_control_set(priv->ale, HOST_PORT_NUM, ALE_VLAN_AWARE, 12023b72c2feSMugunthan V N CPSW_ALE_VLAN_AWARE); 12033b72c2feSMugunthan V N control_reg = readl(&priv->regs->control); 12043b72c2feSMugunthan V N control_reg |= CPSW_VLAN_AWARE; 12053b72c2feSMugunthan V N writel(control_reg, &priv->regs->control); 1206d9ba8f9eSMugunthan V N fifo_mode = (priv->data.dual_emac) ? CPSW_FIFO_DUAL_MAC_MODE : 1207d9ba8f9eSMugunthan V N CPSW_FIFO_NORMAL_MODE; 1208d9ba8f9eSMugunthan V N writel(fifo_mode, &priv->host_port_regs->tx_in_ctl); 1209df828598SMugunthan V N 1210df828598SMugunthan V N /* setup host port priority mapping */ 1211df828598SMugunthan V N __raw_writel(CPDMA_TX_PRIORITY_MAP, 1212df828598SMugunthan V N &priv->host_port_regs->cpdma_tx_pri_map); 1213df828598SMugunthan V N __raw_writel(0, &priv->host_port_regs->cpdma_rx_chan_map); 1214df828598SMugunthan V N 121571a2cbb7SGrygorii Strashko cpsw_ale_control_set(priv->ale, HOST_PORT_NUM, 1216df828598SMugunthan V N ALE_PORT_STATE, ALE_PORT_STATE_FORWARD); 1217df828598SMugunthan V N 1218d9ba8f9eSMugunthan V N if (!priv->data.dual_emac) { 121971a2cbb7SGrygorii Strashko cpsw_ale_add_ucast(priv->ale, priv->mac_addr, HOST_PORT_NUM, 1220d9ba8f9eSMugunthan V N 0, 0); 1221df828598SMugunthan V N cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast, 122271a2cbb7SGrygorii Strashko ALE_PORT_HOST, 0, 0, ALE_MCAST_FWD_2); 1223df828598SMugunthan V N } 1224d9ba8f9eSMugunthan V N } 1225df828598SMugunthan V N 1226aacebbf8SSebastian Siewior static void cpsw_slave_stop(struct cpsw_slave *slave, struct cpsw_priv *priv) 1227aacebbf8SSebastian Siewior { 12283995d265SSchuyler Patton u32 slave_port; 12293995d265SSchuyler Patton 12303995d265SSchuyler Patton slave_port = cpsw_get_slave_port(priv, slave->slave_num); 12313995d265SSchuyler Patton 1232aacebbf8SSebastian Siewior if (!slave->phy) 1233aacebbf8SSebastian Siewior return; 1234aacebbf8SSebastian Siewior phy_stop(slave->phy); 1235aacebbf8SSebastian Siewior phy_disconnect(slave->phy); 1236aacebbf8SSebastian Siewior slave->phy = NULL; 12373995d265SSchuyler Patton cpsw_ale_control_set(priv->ale, slave_port, 12383995d265SSchuyler Patton ALE_PORT_STATE, ALE_PORT_STATE_DISABLE); 1239aacebbf8SSebastian Siewior } 1240aacebbf8SSebastian Siewior 1241df828598SMugunthan V N static int cpsw_ndo_open(struct net_device *ndev) 1242df828598SMugunthan V N { 1243df828598SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 1244df828598SMugunthan V N int i, ret; 1245df828598SMugunthan V N u32 reg; 1246df828598SMugunthan V N 1247d9ba8f9eSMugunthan V N if (!cpsw_common_res_usage_state(priv)) 1248df828598SMugunthan V N cpsw_intr_disable(priv); 1249df828598SMugunthan V N netif_carrier_off(ndev); 1250df828598SMugunthan V N 1251f150bd7fSMugunthan V N pm_runtime_get_sync(&priv->pdev->dev); 1252df828598SMugunthan V N 1253549985eeSRichard Cochran reg = priv->version; 1254df828598SMugunthan V N 1255df828598SMugunthan V N dev_info(priv->dev, "initializing cpsw version %d.%d (%d)\n", 1256df828598SMugunthan V N CPSW_MAJOR_VERSION(reg), CPSW_MINOR_VERSION(reg), 1257df828598SMugunthan V N CPSW_RTL_VERSION(reg)); 1258df828598SMugunthan V N 1259df828598SMugunthan V N /* initialize host and slave ports */ 1260d9ba8f9eSMugunthan V N if (!cpsw_common_res_usage_state(priv)) 1261df828598SMugunthan V N cpsw_init_host_port(priv); 1262df828598SMugunthan V N for_each_slave(priv, cpsw_slave_open, priv); 1263df828598SMugunthan V N 12643b72c2feSMugunthan V N /* Add default VLAN */ 1265e6afea0bSMugunthan V N if (!priv->data.dual_emac) 12663b72c2feSMugunthan V N cpsw_add_default_vlan(priv); 1267e6afea0bSMugunthan V N else 1268e6afea0bSMugunthan V N cpsw_ale_add_vlan(priv->ale, priv->data.default_vlan, 126961f1cef9SGrygorii Strashko ALE_ALL_PORTS, ALE_ALL_PORTS, 0, 0); 12703b72c2feSMugunthan V N 1271d9ba8f9eSMugunthan V N if (!cpsw_common_res_usage_state(priv)) { 1272d354eb85SMugunthan V N struct cpsw_priv *priv_sl0 = cpsw_get_slave_priv(priv, 0); 1273d354eb85SMugunthan V N 1274df828598SMugunthan V N /* setup tx dma to fixed prio and zero offset */ 1275df828598SMugunthan V N cpdma_control_set(priv->dma, CPDMA_TX_PRIO_FIXED, 1); 1276df828598SMugunthan V N cpdma_control_set(priv->dma, CPDMA_RX_BUFFER_OFFSET, 0); 1277df828598SMugunthan V N 1278d9ba8f9eSMugunthan V N /* disable priority elevation */ 1279df828598SMugunthan V N __raw_writel(0, &priv->regs->ptype); 1280df828598SMugunthan V N 1281d9ba8f9eSMugunthan V N /* enable statistics collection only on all ports */ 1282df828598SMugunthan V N __raw_writel(0x7, &priv->regs->stat_port_en); 1283df828598SMugunthan V N 12841923d6e4SMugunthan V N /* Enable internal fifo flow control */ 12851923d6e4SMugunthan V N writel(0x7, &priv->regs->flow_control); 12861923d6e4SMugunthan V N 128732a7432cSMugunthan V N napi_enable(&priv_sl0->napi_rx); 128832a7432cSMugunthan V N napi_enable(&priv_sl0->napi_tx); 1289d354eb85SMugunthan V N 12907da11600SMugunthan V N if (priv_sl0->tx_irq_disabled) { 12917da11600SMugunthan V N priv_sl0->tx_irq_disabled = false; 12927da11600SMugunthan V N enable_irq(priv->irqs_table[1]); 12937da11600SMugunthan V N } 12947da11600SMugunthan V N 12957da11600SMugunthan V N if (priv_sl0->rx_irq_disabled) { 12967da11600SMugunthan V N priv_sl0->rx_irq_disabled = false; 12977da11600SMugunthan V N enable_irq(priv->irqs_table[0]); 12987da11600SMugunthan V N } 12997da11600SMugunthan V N 1300df828598SMugunthan V N if (WARN_ON(!priv->data.rx_descs)) 1301df828598SMugunthan V N priv->data.rx_descs = 128; 1302df828598SMugunthan V N 1303df828598SMugunthan V N for (i = 0; i < priv->data.rx_descs; i++) { 1304df828598SMugunthan V N struct sk_buff *skb; 1305df828598SMugunthan V N 1306df828598SMugunthan V N ret = -ENOMEM; 1307aacebbf8SSebastian Siewior skb = __netdev_alloc_skb_ip_align(priv->ndev, 1308aacebbf8SSebastian Siewior priv->rx_packet_max, GFP_KERNEL); 1309df828598SMugunthan V N if (!skb) 1310aacebbf8SSebastian Siewior goto err_cleanup; 1311df828598SMugunthan V N ret = cpdma_chan_submit(priv->rxch, skb, skb->data, 1312aef614e1SSebastian Siewior skb_tailroom(skb), 0); 1313aacebbf8SSebastian Siewior if (ret < 0) { 1314aacebbf8SSebastian Siewior kfree_skb(skb); 1315aacebbf8SSebastian Siewior goto err_cleanup; 1316aacebbf8SSebastian Siewior } 1317df828598SMugunthan V N } 1318d9ba8f9eSMugunthan V N /* continue even if we didn't manage to submit all 1319d9ba8f9eSMugunthan V N * receive descs 1320d9ba8f9eSMugunthan V N */ 1321df828598SMugunthan V N cpsw_info(priv, ifup, "submitted %d rx descriptors\n", i); 1322f280e89aSMugunthan V N 1323f280e89aSMugunthan V N if (cpts_register(&priv->pdev->dev, priv->cpts, 1324f280e89aSMugunthan V N priv->data.cpts_clock_mult, 1325f280e89aSMugunthan V N priv->data.cpts_clock_shift)) 1326f280e89aSMugunthan V N dev_err(priv->dev, "error registering cpts device\n"); 1327f280e89aSMugunthan V N 1328d9ba8f9eSMugunthan V N } 1329df828598SMugunthan V N 1330ff5b8ef2SMugunthan V N /* Enable Interrupt pacing if configured */ 1331ff5b8ef2SMugunthan V N if (priv->coal_intvl != 0) { 1332ff5b8ef2SMugunthan V N struct ethtool_coalesce coal; 1333ff5b8ef2SMugunthan V N 1334ff5b8ef2SMugunthan V N coal.rx_coalesce_usecs = (priv->coal_intvl << 4); 1335ff5b8ef2SMugunthan V N cpsw_set_coalesce(ndev, &coal); 1336ff5b8ef2SMugunthan V N } 1337ff5b8ef2SMugunthan V N 1338f63a975eSMugunthan V N cpdma_ctlr_start(priv->dma); 1339f63a975eSMugunthan V N cpsw_intr_enable(priv); 1340f63a975eSMugunthan V N 1341d9ba8f9eSMugunthan V N if (priv->data.dual_emac) 1342d9ba8f9eSMugunthan V N priv->slaves[priv->emac_port].open_stat = true; 1343df828598SMugunthan V N return 0; 1344df828598SMugunthan V N 1345aacebbf8SSebastian Siewior err_cleanup: 1346aacebbf8SSebastian Siewior cpdma_ctlr_stop(priv->dma); 1347aacebbf8SSebastian Siewior for_each_slave(priv, cpsw_slave_stop, priv); 1348aacebbf8SSebastian Siewior pm_runtime_put_sync(&priv->pdev->dev); 1349aacebbf8SSebastian Siewior netif_carrier_off(priv->ndev); 1350aacebbf8SSebastian Siewior return ret; 1351df828598SMugunthan V N } 1352df828598SMugunthan V N 1353df828598SMugunthan V N static int cpsw_ndo_stop(struct net_device *ndev) 1354df828598SMugunthan V N { 1355df828598SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 1356df828598SMugunthan V N 1357df828598SMugunthan V N cpsw_info(priv, ifdown, "shutting down cpsw device\n"); 1358df828598SMugunthan V N netif_stop_queue(priv->ndev); 1359df828598SMugunthan V N netif_carrier_off(priv->ndev); 1360d9ba8f9eSMugunthan V N 1361d9ba8f9eSMugunthan V N if (cpsw_common_res_usage_state(priv) <= 1) { 1362d354eb85SMugunthan V N struct cpsw_priv *priv_sl0 = cpsw_get_slave_priv(priv, 0); 1363d354eb85SMugunthan V N 136432a7432cSMugunthan V N napi_disable(&priv_sl0->napi_rx); 136532a7432cSMugunthan V N napi_disable(&priv_sl0->napi_tx); 1366f280e89aSMugunthan V N cpts_unregister(priv->cpts); 136771380f9bSMugunthan V N cpsw_intr_disable(priv); 136871380f9bSMugunthan V N cpdma_ctlr_stop(priv->dma); 1369df828598SMugunthan V N cpsw_ale_stop(priv->ale); 1370d9ba8f9eSMugunthan V N } 1371df828598SMugunthan V N for_each_slave(priv, cpsw_slave_stop, priv); 1372f150bd7fSMugunthan V N pm_runtime_put_sync(&priv->pdev->dev); 1373d9ba8f9eSMugunthan V N if (priv->data.dual_emac) 1374d9ba8f9eSMugunthan V N priv->slaves[priv->emac_port].open_stat = false; 1375df828598SMugunthan V N return 0; 1376df828598SMugunthan V N } 1377df828598SMugunthan V N 1378df828598SMugunthan V N static netdev_tx_t cpsw_ndo_start_xmit(struct sk_buff *skb, 1379df828598SMugunthan V N struct net_device *ndev) 1380df828598SMugunthan V N { 1381df828598SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 1382df828598SMugunthan V N int ret; 1383df828598SMugunthan V N 1384df828598SMugunthan V N ndev->trans_start = jiffies; 1385df828598SMugunthan V N 1386df828598SMugunthan V N if (skb_padto(skb, CPSW_MIN_PACKET_SIZE)) { 1387df828598SMugunthan V N cpsw_err(priv, tx_err, "packet pad failed\n"); 13888dc43ddcSTobias Klauser ndev->stats.tx_dropped++; 1389df828598SMugunthan V N return NETDEV_TX_OK; 1390df828598SMugunthan V N } 1391df828598SMugunthan V N 13929232b16dSMugunthan V N if (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP && 13939232b16dSMugunthan V N priv->cpts->tx_enable) 13942e5b38abSRichard Cochran skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 13952e5b38abSRichard Cochran 13962e5b38abSRichard Cochran skb_tx_timestamp(skb); 13972e5b38abSRichard Cochran 1398d9ba8f9eSMugunthan V N ret = cpsw_tx_packet_submit(ndev, priv, skb); 1399df828598SMugunthan V N if (unlikely(ret != 0)) { 1400df828598SMugunthan V N cpsw_err(priv, tx_err, "desc submit failed\n"); 1401df828598SMugunthan V N goto fail; 1402df828598SMugunthan V N } 1403df828598SMugunthan V N 1404fae50823SMugunthan V N /* If there is no more tx desc left free then we need to 1405fae50823SMugunthan V N * tell the kernel to stop sending us tx frames. 1406fae50823SMugunthan V N */ 1407d35162f8SDaniel Mack if (unlikely(!cpdma_check_free_tx_desc(priv->txch))) 1408fae50823SMugunthan V N netif_stop_queue(ndev); 1409fae50823SMugunthan V N 1410df828598SMugunthan V N return NETDEV_TX_OK; 1411df828598SMugunthan V N fail: 14128dc43ddcSTobias Klauser ndev->stats.tx_dropped++; 1413df828598SMugunthan V N netif_stop_queue(ndev); 1414df828598SMugunthan V N return NETDEV_TX_BUSY; 1415df828598SMugunthan V N } 1416df828598SMugunthan V N 14172e5b38abSRichard Cochran #ifdef CONFIG_TI_CPTS 14182e5b38abSRichard Cochran 14192e5b38abSRichard Cochran static void cpsw_hwtstamp_v1(struct cpsw_priv *priv) 14202e5b38abSRichard Cochran { 1421e86ac13bSMugunthan V N struct cpsw_slave *slave = &priv->slaves[priv->data.active_slave]; 14222e5b38abSRichard Cochran u32 ts_en, seq_id; 14232e5b38abSRichard Cochran 14249232b16dSMugunthan V N if (!priv->cpts->tx_enable && !priv->cpts->rx_enable) { 14252e5b38abSRichard Cochran slave_write(slave, 0, CPSW1_TS_CTL); 14262e5b38abSRichard Cochran return; 14272e5b38abSRichard Cochran } 14282e5b38abSRichard Cochran 14292e5b38abSRichard Cochran seq_id = (30 << CPSW_V1_SEQ_ID_OFS_SHIFT) | ETH_P_1588; 14302e5b38abSRichard Cochran ts_en = EVENT_MSG_BITS << CPSW_V1_MSG_TYPE_OFS; 14312e5b38abSRichard Cochran 14329232b16dSMugunthan V N if (priv->cpts->tx_enable) 14332e5b38abSRichard Cochran ts_en |= CPSW_V1_TS_TX_EN; 14342e5b38abSRichard Cochran 14359232b16dSMugunthan V N if (priv->cpts->rx_enable) 14362e5b38abSRichard Cochran ts_en |= CPSW_V1_TS_RX_EN; 14372e5b38abSRichard Cochran 14382e5b38abSRichard Cochran slave_write(slave, ts_en, CPSW1_TS_CTL); 14392e5b38abSRichard Cochran slave_write(slave, seq_id, CPSW1_TS_SEQ_LTYPE); 14402e5b38abSRichard Cochran } 14412e5b38abSRichard Cochran 14422e5b38abSRichard Cochran static void cpsw_hwtstamp_v2(struct cpsw_priv *priv) 14432e5b38abSRichard Cochran { 1444d9ba8f9eSMugunthan V N struct cpsw_slave *slave; 14452e5b38abSRichard Cochran u32 ctrl, mtype; 14462e5b38abSRichard Cochran 1447d9ba8f9eSMugunthan V N if (priv->data.dual_emac) 1448d9ba8f9eSMugunthan V N slave = &priv->slaves[priv->emac_port]; 1449d9ba8f9eSMugunthan V N else 1450e86ac13bSMugunthan V N slave = &priv->slaves[priv->data.active_slave]; 1451d9ba8f9eSMugunthan V N 14522e5b38abSRichard Cochran ctrl = slave_read(slave, CPSW2_CONTROL); 145309c55372SGeorge Cherian switch (priv->version) { 145409c55372SGeorge Cherian case CPSW_VERSION_2: 145509c55372SGeorge Cherian ctrl &= ~CTRL_V2_ALL_TS_MASK; 14562e5b38abSRichard Cochran 14579232b16dSMugunthan V N if (priv->cpts->tx_enable) 145809c55372SGeorge Cherian ctrl |= CTRL_V2_TX_TS_BITS; 14592e5b38abSRichard Cochran 14609232b16dSMugunthan V N if (priv->cpts->rx_enable) 146109c55372SGeorge Cherian ctrl |= CTRL_V2_RX_TS_BITS; 146209c55372SGeorge Cherian break; 146309c55372SGeorge Cherian case CPSW_VERSION_3: 146409c55372SGeorge Cherian default: 146509c55372SGeorge Cherian ctrl &= ~CTRL_V3_ALL_TS_MASK; 146609c55372SGeorge Cherian 146709c55372SGeorge Cherian if (priv->cpts->tx_enable) 146809c55372SGeorge Cherian ctrl |= CTRL_V3_TX_TS_BITS; 146909c55372SGeorge Cherian 147009c55372SGeorge Cherian if (priv->cpts->rx_enable) 147109c55372SGeorge Cherian ctrl |= CTRL_V3_RX_TS_BITS; 147209c55372SGeorge Cherian break; 147309c55372SGeorge Cherian } 14742e5b38abSRichard Cochran 14752e5b38abSRichard Cochran mtype = (30 << TS_SEQ_ID_OFFSET_SHIFT) | EVENT_MSG_BITS; 14762e5b38abSRichard Cochran 14772e5b38abSRichard Cochran slave_write(slave, mtype, CPSW2_TS_SEQ_MTYPE); 14782e5b38abSRichard Cochran slave_write(slave, ctrl, CPSW2_CONTROL); 14792e5b38abSRichard Cochran __raw_writel(ETH_P_1588, &priv->regs->ts_ltype); 14802e5b38abSRichard Cochran } 14812e5b38abSRichard Cochran 1482a5b4145bSBen Hutchings static int cpsw_hwtstamp_set(struct net_device *dev, struct ifreq *ifr) 14832e5b38abSRichard Cochran { 14843177bf6fSMugunthan V N struct cpsw_priv *priv = netdev_priv(dev); 14859232b16dSMugunthan V N struct cpts *cpts = priv->cpts; 14862e5b38abSRichard Cochran struct hwtstamp_config cfg; 14872e5b38abSRichard Cochran 14882ee91e54SBen Hutchings if (priv->version != CPSW_VERSION_1 && 1489f7d403cbSGeorge Cherian priv->version != CPSW_VERSION_2 && 1490f7d403cbSGeorge Cherian priv->version != CPSW_VERSION_3) 14912ee91e54SBen Hutchings return -EOPNOTSUPP; 14922ee91e54SBen Hutchings 14932e5b38abSRichard Cochran if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg))) 14942e5b38abSRichard Cochran return -EFAULT; 14952e5b38abSRichard Cochran 14962e5b38abSRichard Cochran /* reserved for future extensions */ 14972e5b38abSRichard Cochran if (cfg.flags) 14982e5b38abSRichard Cochran return -EINVAL; 14992e5b38abSRichard Cochran 15002ee91e54SBen Hutchings if (cfg.tx_type != HWTSTAMP_TX_OFF && cfg.tx_type != HWTSTAMP_TX_ON) 15012e5b38abSRichard Cochran return -ERANGE; 15022e5b38abSRichard Cochran 15032e5b38abSRichard Cochran switch (cfg.rx_filter) { 15042e5b38abSRichard Cochran case HWTSTAMP_FILTER_NONE: 15052e5b38abSRichard Cochran cpts->rx_enable = 0; 15062e5b38abSRichard Cochran break; 15072e5b38abSRichard Cochran case HWTSTAMP_FILTER_ALL: 15082e5b38abSRichard Cochran case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: 15092e5b38abSRichard Cochran case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: 15102e5b38abSRichard Cochran case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: 15112e5b38abSRichard Cochran return -ERANGE; 15122e5b38abSRichard Cochran case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: 15132e5b38abSRichard Cochran case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 15142e5b38abSRichard Cochran case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 15152e5b38abSRichard Cochran case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: 15162e5b38abSRichard Cochran case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: 15172e5b38abSRichard Cochran case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: 15182e5b38abSRichard Cochran case HWTSTAMP_FILTER_PTP_V2_EVENT: 15192e5b38abSRichard Cochran case HWTSTAMP_FILTER_PTP_V2_SYNC: 15202e5b38abSRichard Cochran case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 15212e5b38abSRichard Cochran cpts->rx_enable = 1; 15222e5b38abSRichard Cochran cfg.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT; 15232e5b38abSRichard Cochran break; 15242e5b38abSRichard Cochran default: 15252e5b38abSRichard Cochran return -ERANGE; 15262e5b38abSRichard Cochran } 15272e5b38abSRichard Cochran 15282ee91e54SBen Hutchings cpts->tx_enable = cfg.tx_type == HWTSTAMP_TX_ON; 15292ee91e54SBen Hutchings 15302e5b38abSRichard Cochran switch (priv->version) { 15312e5b38abSRichard Cochran case CPSW_VERSION_1: 15322e5b38abSRichard Cochran cpsw_hwtstamp_v1(priv); 15332e5b38abSRichard Cochran break; 15342e5b38abSRichard Cochran case CPSW_VERSION_2: 1535f7d403cbSGeorge Cherian case CPSW_VERSION_3: 15362e5b38abSRichard Cochran cpsw_hwtstamp_v2(priv); 15372e5b38abSRichard Cochran break; 15382e5b38abSRichard Cochran default: 15392ee91e54SBen Hutchings WARN_ON(1); 15402e5b38abSRichard Cochran } 15412e5b38abSRichard Cochran 15422e5b38abSRichard Cochran return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0; 15432e5b38abSRichard Cochran } 15442e5b38abSRichard Cochran 1545a5b4145bSBen Hutchings static int cpsw_hwtstamp_get(struct net_device *dev, struct ifreq *ifr) 1546a5b4145bSBen Hutchings { 1547a5b4145bSBen Hutchings struct cpsw_priv *priv = netdev_priv(dev); 1548a5b4145bSBen Hutchings struct cpts *cpts = priv->cpts; 1549a5b4145bSBen Hutchings struct hwtstamp_config cfg; 1550a5b4145bSBen Hutchings 1551a5b4145bSBen Hutchings if (priv->version != CPSW_VERSION_1 && 1552f7d403cbSGeorge Cherian priv->version != CPSW_VERSION_2 && 1553f7d403cbSGeorge Cherian priv->version != CPSW_VERSION_3) 1554a5b4145bSBen Hutchings return -EOPNOTSUPP; 1555a5b4145bSBen Hutchings 1556a5b4145bSBen Hutchings cfg.flags = 0; 1557a5b4145bSBen Hutchings cfg.tx_type = cpts->tx_enable ? HWTSTAMP_TX_ON : HWTSTAMP_TX_OFF; 1558a5b4145bSBen Hutchings cfg.rx_filter = (cpts->rx_enable ? 1559a5b4145bSBen Hutchings HWTSTAMP_FILTER_PTP_V2_EVENT : HWTSTAMP_FILTER_NONE); 1560a5b4145bSBen Hutchings 1561a5b4145bSBen Hutchings return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0; 1562a5b4145bSBen Hutchings } 1563a5b4145bSBen Hutchings 15642e5b38abSRichard Cochran #endif /*CONFIG_TI_CPTS*/ 15652e5b38abSRichard Cochran 15662e5b38abSRichard Cochran static int cpsw_ndo_ioctl(struct net_device *dev, struct ifreq *req, int cmd) 15672e5b38abSRichard Cochran { 156811f2c988SMugunthan V N struct cpsw_priv *priv = netdev_priv(dev); 156911f2c988SMugunthan V N int slave_no = cpsw_slave_index(priv); 157011f2c988SMugunthan V N 15712e5b38abSRichard Cochran if (!netif_running(dev)) 15722e5b38abSRichard Cochran return -EINVAL; 15732e5b38abSRichard Cochran 157411f2c988SMugunthan V N switch (cmd) { 15752e5b38abSRichard Cochran #ifdef CONFIG_TI_CPTS 157611f2c988SMugunthan V N case SIOCSHWTSTAMP: 1577a5b4145bSBen Hutchings return cpsw_hwtstamp_set(dev, req); 1578a5b4145bSBen Hutchings case SIOCGHWTSTAMP: 1579a5b4145bSBen Hutchings return cpsw_hwtstamp_get(dev, req); 15802e5b38abSRichard Cochran #endif 15812e5b38abSRichard Cochran } 15822e5b38abSRichard Cochran 1583c1b59947SStefan Sørensen if (!priv->slaves[slave_no].phy) 1584c1b59947SStefan Sørensen return -EOPNOTSUPP; 1585c1b59947SStefan Sørensen return phy_mii_ioctl(priv->slaves[slave_no].phy, req, cmd); 158611f2c988SMugunthan V N } 158711f2c988SMugunthan V N 1588df828598SMugunthan V N static void cpsw_ndo_tx_timeout(struct net_device *ndev) 1589df828598SMugunthan V N { 1590df828598SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 1591df828598SMugunthan V N 1592df828598SMugunthan V N cpsw_err(priv, tx_err, "transmit timeout, restarting dma\n"); 15938dc43ddcSTobias Klauser ndev->stats.tx_errors++; 1594df828598SMugunthan V N cpsw_intr_disable(priv); 1595df828598SMugunthan V N cpdma_chan_stop(priv->txch); 1596df828598SMugunthan V N cpdma_chan_start(priv->txch); 1597df828598SMugunthan V N cpsw_intr_enable(priv); 1598df828598SMugunthan V N } 1599df828598SMugunthan V N 1600dcfd8d58SMugunthan V N static int cpsw_ndo_set_mac_address(struct net_device *ndev, void *p) 1601dcfd8d58SMugunthan V N { 1602dcfd8d58SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 1603dcfd8d58SMugunthan V N struct sockaddr *addr = (struct sockaddr *)p; 1604dcfd8d58SMugunthan V N int flags = 0; 1605dcfd8d58SMugunthan V N u16 vid = 0; 1606dcfd8d58SMugunthan V N 1607dcfd8d58SMugunthan V N if (!is_valid_ether_addr(addr->sa_data)) 1608dcfd8d58SMugunthan V N return -EADDRNOTAVAIL; 1609dcfd8d58SMugunthan V N 1610dcfd8d58SMugunthan V N if (priv->data.dual_emac) { 1611dcfd8d58SMugunthan V N vid = priv->slaves[priv->emac_port].port_vlan; 1612dcfd8d58SMugunthan V N flags = ALE_VLAN; 1613dcfd8d58SMugunthan V N } 1614dcfd8d58SMugunthan V N 161571a2cbb7SGrygorii Strashko cpsw_ale_del_ucast(priv->ale, priv->mac_addr, HOST_PORT_NUM, 1616dcfd8d58SMugunthan V N flags, vid); 161771a2cbb7SGrygorii Strashko cpsw_ale_add_ucast(priv->ale, addr->sa_data, HOST_PORT_NUM, 1618dcfd8d58SMugunthan V N flags, vid); 1619dcfd8d58SMugunthan V N 1620dcfd8d58SMugunthan V N memcpy(priv->mac_addr, addr->sa_data, ETH_ALEN); 1621dcfd8d58SMugunthan V N memcpy(ndev->dev_addr, priv->mac_addr, ETH_ALEN); 1622dcfd8d58SMugunthan V N for_each_slave(priv, cpsw_set_slave_mac, priv); 1623dcfd8d58SMugunthan V N 1624dcfd8d58SMugunthan V N return 0; 1625dcfd8d58SMugunthan V N } 1626dcfd8d58SMugunthan V N 1627df828598SMugunthan V N #ifdef CONFIG_NET_POLL_CONTROLLER 1628df828598SMugunthan V N static void cpsw_ndo_poll_controller(struct net_device *ndev) 1629df828598SMugunthan V N { 1630df828598SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 1631df828598SMugunthan V N 1632df828598SMugunthan V N cpsw_intr_disable(priv); 163392cb13fbSFelipe Balbi cpsw_rx_interrupt(priv->irqs_table[0], priv); 163492cb13fbSFelipe Balbi cpsw_tx_interrupt(priv->irqs_table[1], priv); 1635df828598SMugunthan V N cpsw_intr_enable(priv); 1636df828598SMugunthan V N } 1637df828598SMugunthan V N #endif 1638df828598SMugunthan V N 16393b72c2feSMugunthan V N static inline int cpsw_add_vlan_ale_entry(struct cpsw_priv *priv, 16403b72c2feSMugunthan V N unsigned short vid) 16413b72c2feSMugunthan V N { 16423b72c2feSMugunthan V N int ret; 16439f6bd8faSMugunthan V N int unreg_mcast_mask = 0; 16449f6bd8faSMugunthan V N u32 port_mask; 16459f6bd8faSMugunthan V N 16469f6bd8faSMugunthan V N if (priv->data.dual_emac) { 16479f6bd8faSMugunthan V N port_mask = (1 << (priv->emac_port + 1)) | ALE_PORT_HOST; 16489f6bd8faSMugunthan V N 16499f6bd8faSMugunthan V N if (priv->ndev->flags & IFF_ALLMULTI) 16509f6bd8faSMugunthan V N unreg_mcast_mask = port_mask; 16519f6bd8faSMugunthan V N } else { 16529f6bd8faSMugunthan V N port_mask = ALE_ALL_PORTS; 16531e5c4bc4SLennart Sorensen 16541e5c4bc4SLennart Sorensen if (priv->ndev->flags & IFF_ALLMULTI) 16551e5c4bc4SLennart Sorensen unreg_mcast_mask = ALE_ALL_PORTS; 16561e5c4bc4SLennart Sorensen else 16571e5c4bc4SLennart Sorensen unreg_mcast_mask = ALE_PORT_1 | ALE_PORT_2; 16589f6bd8faSMugunthan V N } 16593b72c2feSMugunthan V N 16609f6bd8faSMugunthan V N ret = cpsw_ale_add_vlan(priv->ale, vid, port_mask, 0, port_mask, 166161f1cef9SGrygorii Strashko unreg_mcast_mask); 16623b72c2feSMugunthan V N if (ret != 0) 16633b72c2feSMugunthan V N return ret; 16643b72c2feSMugunthan V N 16653b72c2feSMugunthan V N ret = cpsw_ale_add_ucast(priv->ale, priv->mac_addr, 166671a2cbb7SGrygorii Strashko HOST_PORT_NUM, ALE_VLAN, vid); 16673b72c2feSMugunthan V N if (ret != 0) 16683b72c2feSMugunthan V N goto clean_vid; 16693b72c2feSMugunthan V N 16703b72c2feSMugunthan V N ret = cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast, 16719f6bd8faSMugunthan V N port_mask, ALE_VLAN, vid, 0); 16723b72c2feSMugunthan V N if (ret != 0) 16733b72c2feSMugunthan V N goto clean_vlan_ucast; 16743b72c2feSMugunthan V N return 0; 16753b72c2feSMugunthan V N 16763b72c2feSMugunthan V N clean_vlan_ucast: 16773b72c2feSMugunthan V N cpsw_ale_del_ucast(priv->ale, priv->mac_addr, 167871a2cbb7SGrygorii Strashko HOST_PORT_NUM, ALE_VLAN, vid); 16793b72c2feSMugunthan V N clean_vid: 16803b72c2feSMugunthan V N cpsw_ale_del_vlan(priv->ale, vid, 0); 16813b72c2feSMugunthan V N return ret; 16823b72c2feSMugunthan V N } 16833b72c2feSMugunthan V N 16843b72c2feSMugunthan V N static int cpsw_ndo_vlan_rx_add_vid(struct net_device *ndev, 168580d5c368SPatrick McHardy __be16 proto, u16 vid) 16863b72c2feSMugunthan V N { 16873b72c2feSMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 16883b72c2feSMugunthan V N 16893b72c2feSMugunthan V N if (vid == priv->data.default_vlan) 16903b72c2feSMugunthan V N return 0; 16913b72c2feSMugunthan V N 169202a54164SMugunthan V N if (priv->data.dual_emac) { 169302a54164SMugunthan V N /* In dual EMAC, reserved VLAN id should not be used for 169402a54164SMugunthan V N * creating VLAN interfaces as this can break the dual 169502a54164SMugunthan V N * EMAC port separation 169602a54164SMugunthan V N */ 169702a54164SMugunthan V N int i; 169802a54164SMugunthan V N 169902a54164SMugunthan V N for (i = 0; i < priv->data.slaves; i++) { 170002a54164SMugunthan V N if (vid == priv->slaves[i].port_vlan) 170102a54164SMugunthan V N return -EINVAL; 170202a54164SMugunthan V N } 170302a54164SMugunthan V N } 170402a54164SMugunthan V N 17053b72c2feSMugunthan V N dev_info(priv->dev, "Adding vlanid %d to vlan filter\n", vid); 17063b72c2feSMugunthan V N return cpsw_add_vlan_ale_entry(priv, vid); 17073b72c2feSMugunthan V N } 17083b72c2feSMugunthan V N 17093b72c2feSMugunthan V N static int cpsw_ndo_vlan_rx_kill_vid(struct net_device *ndev, 171080d5c368SPatrick McHardy __be16 proto, u16 vid) 17113b72c2feSMugunthan V N { 17123b72c2feSMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 17133b72c2feSMugunthan V N int ret; 17143b72c2feSMugunthan V N 17153b72c2feSMugunthan V N if (vid == priv->data.default_vlan) 17163b72c2feSMugunthan V N return 0; 17173b72c2feSMugunthan V N 171802a54164SMugunthan V N if (priv->data.dual_emac) { 171902a54164SMugunthan V N int i; 172002a54164SMugunthan V N 172102a54164SMugunthan V N for (i = 0; i < priv->data.slaves; i++) { 172202a54164SMugunthan V N if (vid == priv->slaves[i].port_vlan) 172302a54164SMugunthan V N return -EINVAL; 172402a54164SMugunthan V N } 172502a54164SMugunthan V N } 172602a54164SMugunthan V N 17273b72c2feSMugunthan V N dev_info(priv->dev, "removing vlanid %d from vlan filter\n", vid); 17283b72c2feSMugunthan V N ret = cpsw_ale_del_vlan(priv->ale, vid, 0); 17293b72c2feSMugunthan V N if (ret != 0) 17303b72c2feSMugunthan V N return ret; 17313b72c2feSMugunthan V N 17323b72c2feSMugunthan V N ret = cpsw_ale_del_ucast(priv->ale, priv->mac_addr, 173361f1cef9SGrygorii Strashko HOST_PORT_NUM, ALE_VLAN, vid); 17343b72c2feSMugunthan V N if (ret != 0) 17353b72c2feSMugunthan V N return ret; 17363b72c2feSMugunthan V N 17373b72c2feSMugunthan V N return cpsw_ale_del_mcast(priv->ale, priv->ndev->broadcast, 17383b72c2feSMugunthan V N 0, ALE_VLAN, vid); 17393b72c2feSMugunthan V N } 17403b72c2feSMugunthan V N 1741df828598SMugunthan V N static const struct net_device_ops cpsw_netdev_ops = { 1742df828598SMugunthan V N .ndo_open = cpsw_ndo_open, 1743df828598SMugunthan V N .ndo_stop = cpsw_ndo_stop, 1744df828598SMugunthan V N .ndo_start_xmit = cpsw_ndo_start_xmit, 1745dcfd8d58SMugunthan V N .ndo_set_mac_address = cpsw_ndo_set_mac_address, 17462e5b38abSRichard Cochran .ndo_do_ioctl = cpsw_ndo_ioctl, 1747df828598SMugunthan V N .ndo_validate_addr = eth_validate_addr, 17485c473ed2SDavid S. Miller .ndo_change_mtu = eth_change_mtu, 1749df828598SMugunthan V N .ndo_tx_timeout = cpsw_ndo_tx_timeout, 17505c50a856SMugunthan V N .ndo_set_rx_mode = cpsw_ndo_set_rx_mode, 1751df828598SMugunthan V N #ifdef CONFIG_NET_POLL_CONTROLLER 1752df828598SMugunthan V N .ndo_poll_controller = cpsw_ndo_poll_controller, 1753df828598SMugunthan V N #endif 17543b72c2feSMugunthan V N .ndo_vlan_rx_add_vid = cpsw_ndo_vlan_rx_add_vid, 17553b72c2feSMugunthan V N .ndo_vlan_rx_kill_vid = cpsw_ndo_vlan_rx_kill_vid, 1756df828598SMugunthan V N }; 1757df828598SMugunthan V N 175852c4f0ecSMugunthan V N static int cpsw_get_regs_len(struct net_device *ndev) 175952c4f0ecSMugunthan V N { 176052c4f0ecSMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 176152c4f0ecSMugunthan V N 176252c4f0ecSMugunthan V N return priv->data.ale_entries * ALE_ENTRY_WORDS * sizeof(u32); 176352c4f0ecSMugunthan V N } 176452c4f0ecSMugunthan V N 176552c4f0ecSMugunthan V N static void cpsw_get_regs(struct net_device *ndev, 176652c4f0ecSMugunthan V N struct ethtool_regs *regs, void *p) 176752c4f0ecSMugunthan V N { 176852c4f0ecSMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 176952c4f0ecSMugunthan V N u32 *reg = p; 177052c4f0ecSMugunthan V N 177152c4f0ecSMugunthan V N /* update CPSW IP version */ 177252c4f0ecSMugunthan V N regs->version = priv->version; 177352c4f0ecSMugunthan V N 177452c4f0ecSMugunthan V N cpsw_ale_dump(priv->ale, reg); 177552c4f0ecSMugunthan V N } 177652c4f0ecSMugunthan V N 1777df828598SMugunthan V N static void cpsw_get_drvinfo(struct net_device *ndev, 1778df828598SMugunthan V N struct ethtool_drvinfo *info) 1779df828598SMugunthan V N { 1780df828598SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 17817826d43fSJiri Pirko 178252c4f0ecSMugunthan V N strlcpy(info->driver, "cpsw", sizeof(info->driver)); 17837826d43fSJiri Pirko strlcpy(info->version, "1.0", sizeof(info->version)); 17847826d43fSJiri Pirko strlcpy(info->bus_info, priv->pdev->name, sizeof(info->bus_info)); 1785df828598SMugunthan V N } 1786df828598SMugunthan V N 1787df828598SMugunthan V N static u32 cpsw_get_msglevel(struct net_device *ndev) 1788df828598SMugunthan V N { 1789df828598SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 1790df828598SMugunthan V N return priv->msg_enable; 1791df828598SMugunthan V N } 1792df828598SMugunthan V N 1793df828598SMugunthan V N static void cpsw_set_msglevel(struct net_device *ndev, u32 value) 1794df828598SMugunthan V N { 1795df828598SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 1796df828598SMugunthan V N priv->msg_enable = value; 1797df828598SMugunthan V N } 1798df828598SMugunthan V N 17992e5b38abSRichard Cochran static int cpsw_get_ts_info(struct net_device *ndev, 18002e5b38abSRichard Cochran struct ethtool_ts_info *info) 18012e5b38abSRichard Cochran { 18022e5b38abSRichard Cochran #ifdef CONFIG_TI_CPTS 18032e5b38abSRichard Cochran struct cpsw_priv *priv = netdev_priv(ndev); 18042e5b38abSRichard Cochran 18052e5b38abSRichard Cochran info->so_timestamping = 18062e5b38abSRichard Cochran SOF_TIMESTAMPING_TX_HARDWARE | 18072e5b38abSRichard Cochran SOF_TIMESTAMPING_TX_SOFTWARE | 18082e5b38abSRichard Cochran SOF_TIMESTAMPING_RX_HARDWARE | 18092e5b38abSRichard Cochran SOF_TIMESTAMPING_RX_SOFTWARE | 18102e5b38abSRichard Cochran SOF_TIMESTAMPING_SOFTWARE | 18112e5b38abSRichard Cochran SOF_TIMESTAMPING_RAW_HARDWARE; 18129232b16dSMugunthan V N info->phc_index = priv->cpts->phc_index; 18132e5b38abSRichard Cochran info->tx_types = 18142e5b38abSRichard Cochran (1 << HWTSTAMP_TX_OFF) | 18152e5b38abSRichard Cochran (1 << HWTSTAMP_TX_ON); 18162e5b38abSRichard Cochran info->rx_filters = 18172e5b38abSRichard Cochran (1 << HWTSTAMP_FILTER_NONE) | 18182e5b38abSRichard Cochran (1 << HWTSTAMP_FILTER_PTP_V2_EVENT); 18192e5b38abSRichard Cochran #else 18202e5b38abSRichard Cochran info->so_timestamping = 18212e5b38abSRichard Cochran SOF_TIMESTAMPING_TX_SOFTWARE | 18222e5b38abSRichard Cochran SOF_TIMESTAMPING_RX_SOFTWARE | 18232e5b38abSRichard Cochran SOF_TIMESTAMPING_SOFTWARE; 18242e5b38abSRichard Cochran info->phc_index = -1; 18252e5b38abSRichard Cochran info->tx_types = 0; 18262e5b38abSRichard Cochran info->rx_filters = 0; 18272e5b38abSRichard Cochran #endif 18282e5b38abSRichard Cochran return 0; 18292e5b38abSRichard Cochran } 18302e5b38abSRichard Cochran 1831d3bb9c58SMugunthan V N static int cpsw_get_settings(struct net_device *ndev, 1832d3bb9c58SMugunthan V N struct ethtool_cmd *ecmd) 1833d3bb9c58SMugunthan V N { 1834d3bb9c58SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 1835d3bb9c58SMugunthan V N int slave_no = cpsw_slave_index(priv); 1836d3bb9c58SMugunthan V N 1837d3bb9c58SMugunthan V N if (priv->slaves[slave_no].phy) 1838d3bb9c58SMugunthan V N return phy_ethtool_gset(priv->slaves[slave_no].phy, ecmd); 1839d3bb9c58SMugunthan V N else 1840d3bb9c58SMugunthan V N return -EOPNOTSUPP; 1841d3bb9c58SMugunthan V N } 1842d3bb9c58SMugunthan V N 1843d3bb9c58SMugunthan V N static int cpsw_set_settings(struct net_device *ndev, struct ethtool_cmd *ecmd) 1844d3bb9c58SMugunthan V N { 1845d3bb9c58SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 1846d3bb9c58SMugunthan V N int slave_no = cpsw_slave_index(priv); 1847d3bb9c58SMugunthan V N 1848d3bb9c58SMugunthan V N if (priv->slaves[slave_no].phy) 1849d3bb9c58SMugunthan V N return phy_ethtool_sset(priv->slaves[slave_no].phy, ecmd); 1850d3bb9c58SMugunthan V N else 1851d3bb9c58SMugunthan V N return -EOPNOTSUPP; 1852d3bb9c58SMugunthan V N } 1853d3bb9c58SMugunthan V N 1854d8a64420SMatus Ujhelyi static void cpsw_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol) 1855d8a64420SMatus Ujhelyi { 1856d8a64420SMatus Ujhelyi struct cpsw_priv *priv = netdev_priv(ndev); 1857d8a64420SMatus Ujhelyi int slave_no = cpsw_slave_index(priv); 1858d8a64420SMatus Ujhelyi 1859d8a64420SMatus Ujhelyi wol->supported = 0; 1860d8a64420SMatus Ujhelyi wol->wolopts = 0; 1861d8a64420SMatus Ujhelyi 1862d8a64420SMatus Ujhelyi if (priv->slaves[slave_no].phy) 1863d8a64420SMatus Ujhelyi phy_ethtool_get_wol(priv->slaves[slave_no].phy, wol); 1864d8a64420SMatus Ujhelyi } 1865d8a64420SMatus Ujhelyi 1866d8a64420SMatus Ujhelyi static int cpsw_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol) 1867d8a64420SMatus Ujhelyi { 1868d8a64420SMatus Ujhelyi struct cpsw_priv *priv = netdev_priv(ndev); 1869d8a64420SMatus Ujhelyi int slave_no = cpsw_slave_index(priv); 1870d8a64420SMatus Ujhelyi 1871d8a64420SMatus Ujhelyi if (priv->slaves[slave_no].phy) 1872d8a64420SMatus Ujhelyi return phy_ethtool_set_wol(priv->slaves[slave_no].phy, wol); 1873d8a64420SMatus Ujhelyi else 1874d8a64420SMatus Ujhelyi return -EOPNOTSUPP; 1875d8a64420SMatus Ujhelyi } 1876d8a64420SMatus Ujhelyi 18771923d6e4SMugunthan V N static void cpsw_get_pauseparam(struct net_device *ndev, 18781923d6e4SMugunthan V N struct ethtool_pauseparam *pause) 18791923d6e4SMugunthan V N { 18801923d6e4SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 18811923d6e4SMugunthan V N 18821923d6e4SMugunthan V N pause->autoneg = AUTONEG_DISABLE; 18831923d6e4SMugunthan V N pause->rx_pause = priv->rx_pause ? true : false; 18841923d6e4SMugunthan V N pause->tx_pause = priv->tx_pause ? true : false; 18851923d6e4SMugunthan V N } 18861923d6e4SMugunthan V N 18871923d6e4SMugunthan V N static int cpsw_set_pauseparam(struct net_device *ndev, 18881923d6e4SMugunthan V N struct ethtool_pauseparam *pause) 18891923d6e4SMugunthan V N { 18901923d6e4SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 18911923d6e4SMugunthan V N bool link; 18921923d6e4SMugunthan V N 18931923d6e4SMugunthan V N priv->rx_pause = pause->rx_pause ? true : false; 18941923d6e4SMugunthan V N priv->tx_pause = pause->tx_pause ? true : false; 18951923d6e4SMugunthan V N 18961923d6e4SMugunthan V N for_each_slave(priv, _cpsw_adjust_link, priv, &link); 18971923d6e4SMugunthan V N 18981923d6e4SMugunthan V N return 0; 18991923d6e4SMugunthan V N } 19001923d6e4SMugunthan V N 1901df828598SMugunthan V N static const struct ethtool_ops cpsw_ethtool_ops = { 1902df828598SMugunthan V N .get_drvinfo = cpsw_get_drvinfo, 1903df828598SMugunthan V N .get_msglevel = cpsw_get_msglevel, 1904df828598SMugunthan V N .set_msglevel = cpsw_set_msglevel, 1905df828598SMugunthan V N .get_link = ethtool_op_get_link, 19062e5b38abSRichard Cochran .get_ts_info = cpsw_get_ts_info, 1907d3bb9c58SMugunthan V N .get_settings = cpsw_get_settings, 1908d3bb9c58SMugunthan V N .set_settings = cpsw_set_settings, 1909ff5b8ef2SMugunthan V N .get_coalesce = cpsw_get_coalesce, 1910ff5b8ef2SMugunthan V N .set_coalesce = cpsw_set_coalesce, 1911d9718546SMugunthan V N .get_sset_count = cpsw_get_sset_count, 1912d9718546SMugunthan V N .get_strings = cpsw_get_strings, 1913d9718546SMugunthan V N .get_ethtool_stats = cpsw_get_ethtool_stats, 19141923d6e4SMugunthan V N .get_pauseparam = cpsw_get_pauseparam, 19151923d6e4SMugunthan V N .set_pauseparam = cpsw_set_pauseparam, 1916d8a64420SMatus Ujhelyi .get_wol = cpsw_get_wol, 1917d8a64420SMatus Ujhelyi .set_wol = cpsw_set_wol, 191852c4f0ecSMugunthan V N .get_regs_len = cpsw_get_regs_len, 191952c4f0ecSMugunthan V N .get_regs = cpsw_get_regs, 1920df828598SMugunthan V N }; 1921df828598SMugunthan V N 1922549985eeSRichard Cochran static void cpsw_slave_init(struct cpsw_slave *slave, struct cpsw_priv *priv, 1923549985eeSRichard Cochran u32 slave_reg_ofs, u32 sliver_reg_ofs) 1924df828598SMugunthan V N { 1925df828598SMugunthan V N void __iomem *regs = priv->regs; 1926df828598SMugunthan V N int slave_num = slave->slave_num; 1927df828598SMugunthan V N struct cpsw_slave_data *data = priv->data.slave_data + slave_num; 1928df828598SMugunthan V N 1929df828598SMugunthan V N slave->data = data; 1930549985eeSRichard Cochran slave->regs = regs + slave_reg_ofs; 1931549985eeSRichard Cochran slave->sliver = regs + sliver_reg_ofs; 1932d9ba8f9eSMugunthan V N slave->port_vlan = data->dual_emac_res_vlan; 1933df828598SMugunthan V N } 1934df828598SMugunthan V N 19359e42f715SHeiko Schocher static int cpsw_probe_dt(struct cpsw_priv *priv, 19362eb32b0aSMugunthan V N struct platform_device *pdev) 19372eb32b0aSMugunthan V N { 19382eb32b0aSMugunthan V N struct device_node *node = pdev->dev.of_node; 19392eb32b0aSMugunthan V N struct device_node *slave_node; 19409e42f715SHeiko Schocher struct cpsw_platform_data *data = &priv->data; 19412eb32b0aSMugunthan V N int i = 0, ret; 19422eb32b0aSMugunthan V N u32 prop; 19432eb32b0aSMugunthan V N 19442eb32b0aSMugunthan V N if (!node) 19452eb32b0aSMugunthan V N return -EINVAL; 19462eb32b0aSMugunthan V N 19472eb32b0aSMugunthan V N if (of_property_read_u32(node, "slaves", &prop)) { 194888c99ff6SGeorge Cherian dev_err(&pdev->dev, "Missing slaves property in the DT.\n"); 19492eb32b0aSMugunthan V N return -EINVAL; 19502eb32b0aSMugunthan V N } 19512eb32b0aSMugunthan V N data->slaves = prop; 19522eb32b0aSMugunthan V N 1953e86ac13bSMugunthan V N if (of_property_read_u32(node, "active_slave", &prop)) { 195488c99ff6SGeorge Cherian dev_err(&pdev->dev, "Missing active_slave property in the DT.\n"); 1955aa1a15e2SDaniel Mack return -EINVAL; 195678ca0b28SRichard Cochran } 1957e86ac13bSMugunthan V N data->active_slave = prop; 195878ca0b28SRichard Cochran 195900ab94eeSRichard Cochran if (of_property_read_u32(node, "cpts_clock_mult", &prop)) { 196088c99ff6SGeorge Cherian dev_err(&pdev->dev, "Missing cpts_clock_mult property in the DT.\n"); 1961aa1a15e2SDaniel Mack return -EINVAL; 196200ab94eeSRichard Cochran } 196300ab94eeSRichard Cochran data->cpts_clock_mult = prop; 196400ab94eeSRichard Cochran 196500ab94eeSRichard Cochran if (of_property_read_u32(node, "cpts_clock_shift", &prop)) { 196688c99ff6SGeorge Cherian dev_err(&pdev->dev, "Missing cpts_clock_shift property in the DT.\n"); 1967aa1a15e2SDaniel Mack return -EINVAL; 196800ab94eeSRichard Cochran } 196900ab94eeSRichard Cochran data->cpts_clock_shift = prop; 197000ab94eeSRichard Cochran 1971aa1a15e2SDaniel Mack data->slave_data = devm_kzalloc(&pdev->dev, data->slaves 1972aa1a15e2SDaniel Mack * sizeof(struct cpsw_slave_data), 1973b2adaca9SJoe Perches GFP_KERNEL); 1974b2adaca9SJoe Perches if (!data->slave_data) 1975aa1a15e2SDaniel Mack return -ENOMEM; 19762eb32b0aSMugunthan V N 19772eb32b0aSMugunthan V N if (of_property_read_u32(node, "cpdma_channels", &prop)) { 197888c99ff6SGeorge Cherian dev_err(&pdev->dev, "Missing cpdma_channels property in the DT.\n"); 1979aa1a15e2SDaniel Mack return -EINVAL; 19802eb32b0aSMugunthan V N } 19812eb32b0aSMugunthan V N data->channels = prop; 19822eb32b0aSMugunthan V N 19832eb32b0aSMugunthan V N if (of_property_read_u32(node, "ale_entries", &prop)) { 198488c99ff6SGeorge Cherian dev_err(&pdev->dev, "Missing ale_entries property in the DT.\n"); 1985aa1a15e2SDaniel Mack return -EINVAL; 19862eb32b0aSMugunthan V N } 19872eb32b0aSMugunthan V N data->ale_entries = prop; 19882eb32b0aSMugunthan V N 19892eb32b0aSMugunthan V N if (of_property_read_u32(node, "bd_ram_size", &prop)) { 199088c99ff6SGeorge Cherian dev_err(&pdev->dev, "Missing bd_ram_size property in the DT.\n"); 1991aa1a15e2SDaniel Mack return -EINVAL; 19922eb32b0aSMugunthan V N } 19932eb32b0aSMugunthan V N data->bd_ram_size = prop; 19942eb32b0aSMugunthan V N 19952eb32b0aSMugunthan V N if (of_property_read_u32(node, "rx_descs", &prop)) { 199688c99ff6SGeorge Cherian dev_err(&pdev->dev, "Missing rx_descs property in the DT.\n"); 1997aa1a15e2SDaniel Mack return -EINVAL; 19982eb32b0aSMugunthan V N } 19992eb32b0aSMugunthan V N data->rx_descs = prop; 20002eb32b0aSMugunthan V N 20012eb32b0aSMugunthan V N if (of_property_read_u32(node, "mac_control", &prop)) { 200288c99ff6SGeorge Cherian dev_err(&pdev->dev, "Missing mac_control property in the DT.\n"); 2003aa1a15e2SDaniel Mack return -EINVAL; 20042eb32b0aSMugunthan V N } 20052eb32b0aSMugunthan V N data->mac_control = prop; 20062eb32b0aSMugunthan V N 2007281abd96SMarkus Pargmann if (of_property_read_bool(node, "dual_emac")) 2008281abd96SMarkus Pargmann data->dual_emac = 1; 2009d9ba8f9eSMugunthan V N 20101fb19aa7SVaibhav Hiremath /* 20111fb19aa7SVaibhav Hiremath * Populate all the child nodes here... 20121fb19aa7SVaibhav Hiremath */ 20131fb19aa7SVaibhav Hiremath ret = of_platform_populate(node, NULL, NULL, &pdev->dev); 20141fb19aa7SVaibhav Hiremath /* We do not want to force this, as in some cases may not have child */ 20151fb19aa7SVaibhav Hiremath if (ret) 201688c99ff6SGeorge Cherian dev_warn(&pdev->dev, "Doesn't have any child node\n"); 20171fb19aa7SVaibhav Hiremath 2018f468b10eSMarkus Pargmann for_each_child_of_node(node, slave_node) { 2019549985eeSRichard Cochran struct cpsw_slave_data *slave_data = data->slave_data + i; 2020549985eeSRichard Cochran const void *mac_addr = NULL; 2021549985eeSRichard Cochran int lenp; 2022549985eeSRichard Cochran const __be32 *parp; 2023549985eeSRichard Cochran 2024f468b10eSMarkus Pargmann /* This is no slave child node, continue */ 2025f468b10eSMarkus Pargmann if (strcmp(slave_node->name, "slave")) 2026f468b10eSMarkus Pargmann continue; 2027f468b10eSMarkus Pargmann 20289e42f715SHeiko Schocher priv->phy_node = of_parse_phandle(slave_node, "phy-handle", 0); 2029f1eea5c1SDavid Rivshin parp = of_get_property(slave_node, "phy_id", &lenp); 20301f71e8c9SMarkus Brunner if (of_phy_is_fixed_link(slave_node)) { 2031dfc0a6d3SDavid Rivshin struct device_node *phy_node; 2032dfc0a6d3SDavid Rivshin struct phy_device *phy_dev; 20331f71e8c9SMarkus Brunner 2034dfc0a6d3SDavid Rivshin /* In the case of a fixed PHY, the DT node associated 2035dfc0a6d3SDavid Rivshin * to the PHY is the Ethernet MAC DT node. 2036dfc0a6d3SDavid Rivshin */ 20371f71e8c9SMarkus Brunner ret = of_phy_register_fixed_link(slave_node); 20381f71e8c9SMarkus Brunner if (ret) 20391f71e8c9SMarkus Brunner return ret; 2040dfc0a6d3SDavid Rivshin phy_node = of_node_get(slave_node); 2041dfc0a6d3SDavid Rivshin phy_dev = of_phy_find_device(phy_node); 2042dfc0a6d3SDavid Rivshin if (!phy_dev) 20431f71e8c9SMarkus Brunner return -ENODEV; 20441f71e8c9SMarkus Brunner snprintf(slave_data->phy_id, sizeof(slave_data->phy_id), 2045e5a03bfdSAndrew Lunn PHY_ID_FMT, phy_dev->mdio.bus->id, 2046e5a03bfdSAndrew Lunn phy_dev->mdio.addr); 2047f1eea5c1SDavid Rivshin } else if (parp) { 2048f1eea5c1SDavid Rivshin u32 phyid; 2049f1eea5c1SDavid Rivshin struct device_node *mdio_node; 2050f1eea5c1SDavid Rivshin struct platform_device *mdio; 2051f1eea5c1SDavid Rivshin 2052f1eea5c1SDavid Rivshin if (lenp != (sizeof(__be32) * 2)) { 2053f1eea5c1SDavid Rivshin dev_err(&pdev->dev, "Invalid slave[%d] phy_id property\n", i); 205447276fccSMugunthan V N goto no_phy_slave; 2055549985eeSRichard Cochran } 2056549985eeSRichard Cochran mdio_node = of_find_node_by_phandle(be32_to_cpup(parp)); 2057549985eeSRichard Cochran phyid = be32_to_cpup(parp+1); 2058549985eeSRichard Cochran mdio = of_find_device_by_node(mdio_node); 205960e71ab5SJohan Hovold of_node_put(mdio_node); 20606954cc1fSJohan Hovold if (!mdio) { 206156fdb2e0SMarkus Pargmann dev_err(&pdev->dev, "Missing mdio platform device\n"); 20626954cc1fSJohan Hovold return -EINVAL; 20636954cc1fSJohan Hovold } 2064549985eeSRichard Cochran snprintf(slave_data->phy_id, sizeof(slave_data->phy_id), 2065549985eeSRichard Cochran PHY_ID_FMT, mdio->name, phyid); 2066f1eea5c1SDavid Rivshin } else { 2067f1eea5c1SDavid Rivshin dev_err(&pdev->dev, "No slave[%d] phy_id or fixed-link property\n", i); 2068f1eea5c1SDavid Rivshin goto no_phy_slave; 2069f1eea5c1SDavid Rivshin } 207047276fccSMugunthan V N slave_data->phy_if = of_get_phy_mode(slave_node); 207147276fccSMugunthan V N if (slave_data->phy_if < 0) { 207247276fccSMugunthan V N dev_err(&pdev->dev, "Missing or malformed slave[%d] phy-mode property\n", 207347276fccSMugunthan V N i); 207447276fccSMugunthan V N return slave_data->phy_if; 207547276fccSMugunthan V N } 207647276fccSMugunthan V N 207747276fccSMugunthan V N no_phy_slave: 2078549985eeSRichard Cochran mac_addr = of_get_mac_address(slave_node); 20790ba517b1SMarkus Pargmann if (mac_addr) { 2080549985eeSRichard Cochran memcpy(slave_data->mac_addr, mac_addr, ETH_ALEN); 20810ba517b1SMarkus Pargmann } else { 2082b6745f6eSMugunthan V N ret = ti_cm_get_macid(&pdev->dev, i, 20830ba517b1SMarkus Pargmann slave_data->mac_addr); 20840ba517b1SMarkus Pargmann if (ret) 20850ba517b1SMarkus Pargmann return ret; 20860ba517b1SMarkus Pargmann } 2087d9ba8f9eSMugunthan V N if (data->dual_emac) { 208891c4166cSMugunthan V N if (of_property_read_u32(slave_node, "dual_emac_res_vlan", 2089d9ba8f9eSMugunthan V N &prop)) { 209088c99ff6SGeorge Cherian dev_err(&pdev->dev, "Missing dual_emac_res_vlan in DT.\n"); 2091d9ba8f9eSMugunthan V N slave_data->dual_emac_res_vlan = i+1; 209288c99ff6SGeorge Cherian dev_err(&pdev->dev, "Using %d as Reserved VLAN for %d slave\n", 2093d9ba8f9eSMugunthan V N slave_data->dual_emac_res_vlan, i); 2094d9ba8f9eSMugunthan V N } else { 2095d9ba8f9eSMugunthan V N slave_data->dual_emac_res_vlan = prop; 2096d9ba8f9eSMugunthan V N } 2097d9ba8f9eSMugunthan V N } 2098d9ba8f9eSMugunthan V N 2099549985eeSRichard Cochran i++; 21003a27bfacSMugunthan V N if (i == data->slaves) 21013a27bfacSMugunthan V N break; 2102549985eeSRichard Cochran } 2103549985eeSRichard Cochran 21042eb32b0aSMugunthan V N return 0; 21052eb32b0aSMugunthan V N } 21062eb32b0aSMugunthan V N 2107d9ba8f9eSMugunthan V N static int cpsw_probe_dual_emac(struct platform_device *pdev, 2108d9ba8f9eSMugunthan V N struct cpsw_priv *priv) 2109d9ba8f9eSMugunthan V N { 2110d9ba8f9eSMugunthan V N struct cpsw_platform_data *data = &priv->data; 2111d9ba8f9eSMugunthan V N struct net_device *ndev; 2112d9ba8f9eSMugunthan V N struct cpsw_priv *priv_sl2; 2113d9ba8f9eSMugunthan V N int ret = 0, i; 2114d9ba8f9eSMugunthan V N 2115d9ba8f9eSMugunthan V N ndev = alloc_etherdev(sizeof(struct cpsw_priv)); 2116d9ba8f9eSMugunthan V N if (!ndev) { 211788c99ff6SGeorge Cherian dev_err(&pdev->dev, "cpsw: error allocating net_device\n"); 2118d9ba8f9eSMugunthan V N return -ENOMEM; 2119d9ba8f9eSMugunthan V N } 2120d9ba8f9eSMugunthan V N 2121d9ba8f9eSMugunthan V N priv_sl2 = netdev_priv(ndev); 2122d9ba8f9eSMugunthan V N spin_lock_init(&priv_sl2->lock); 2123d9ba8f9eSMugunthan V N priv_sl2->data = *data; 2124d9ba8f9eSMugunthan V N priv_sl2->pdev = pdev; 2125d9ba8f9eSMugunthan V N priv_sl2->ndev = ndev; 2126d9ba8f9eSMugunthan V N priv_sl2->dev = &ndev->dev; 2127d9ba8f9eSMugunthan V N priv_sl2->msg_enable = netif_msg_init(debug_level, CPSW_DEBUG); 2128d9ba8f9eSMugunthan V N priv_sl2->rx_packet_max = max(rx_packet_max, 128); 2129d9ba8f9eSMugunthan V N 2130d9ba8f9eSMugunthan V N if (is_valid_ether_addr(data->slave_data[1].mac_addr)) { 2131d9ba8f9eSMugunthan V N memcpy(priv_sl2->mac_addr, data->slave_data[1].mac_addr, 2132d9ba8f9eSMugunthan V N ETH_ALEN); 213388c99ff6SGeorge Cherian dev_info(&pdev->dev, "cpsw: Detected MACID = %pM\n", priv_sl2->mac_addr); 2134d9ba8f9eSMugunthan V N } else { 2135d9ba8f9eSMugunthan V N random_ether_addr(priv_sl2->mac_addr); 213688c99ff6SGeorge Cherian dev_info(&pdev->dev, "cpsw: Random MACID = %pM\n", priv_sl2->mac_addr); 2137d9ba8f9eSMugunthan V N } 2138d9ba8f9eSMugunthan V N memcpy(ndev->dev_addr, priv_sl2->mac_addr, ETH_ALEN); 2139d9ba8f9eSMugunthan V N 2140d9ba8f9eSMugunthan V N priv_sl2->slaves = priv->slaves; 2141d9ba8f9eSMugunthan V N priv_sl2->clk = priv->clk; 2142d9ba8f9eSMugunthan V N 2143ff5b8ef2SMugunthan V N priv_sl2->coal_intvl = 0; 2144ff5b8ef2SMugunthan V N priv_sl2->bus_freq_mhz = priv->bus_freq_mhz; 2145ff5b8ef2SMugunthan V N 2146d9ba8f9eSMugunthan V N priv_sl2->regs = priv->regs; 2147d9ba8f9eSMugunthan V N priv_sl2->host_port_regs = priv->host_port_regs; 2148d9ba8f9eSMugunthan V N priv_sl2->wr_regs = priv->wr_regs; 2149d9718546SMugunthan V N priv_sl2->hw_stats = priv->hw_stats; 2150d9ba8f9eSMugunthan V N priv_sl2->dma = priv->dma; 2151d9ba8f9eSMugunthan V N priv_sl2->txch = priv->txch; 2152d9ba8f9eSMugunthan V N priv_sl2->rxch = priv->rxch; 2153d9ba8f9eSMugunthan V N priv_sl2->ale = priv->ale; 2154d9ba8f9eSMugunthan V N priv_sl2->emac_port = 1; 2155d9ba8f9eSMugunthan V N priv->slaves[1].ndev = ndev; 2156d9ba8f9eSMugunthan V N priv_sl2->cpts = priv->cpts; 2157d9ba8f9eSMugunthan V N priv_sl2->version = priv->version; 2158d9ba8f9eSMugunthan V N 2159d9ba8f9eSMugunthan V N for (i = 0; i < priv->num_irqs; i++) { 2160d9ba8f9eSMugunthan V N priv_sl2->irqs_table[i] = priv->irqs_table[i]; 2161d9ba8f9eSMugunthan V N priv_sl2->num_irqs = priv->num_irqs; 2162d9ba8f9eSMugunthan V N } 2163f646968fSPatrick McHardy ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER; 2164d9ba8f9eSMugunthan V N 2165d9ba8f9eSMugunthan V N ndev->netdev_ops = &cpsw_netdev_ops; 21667ad24ea4SWilfried Klaebe ndev->ethtool_ops = &cpsw_ethtool_ops; 2167d9ba8f9eSMugunthan V N 2168d9ba8f9eSMugunthan V N /* register the network device */ 2169d9ba8f9eSMugunthan V N SET_NETDEV_DEV(ndev, &pdev->dev); 2170d9ba8f9eSMugunthan V N ret = register_netdev(ndev); 2171d9ba8f9eSMugunthan V N if (ret) { 217288c99ff6SGeorge Cherian dev_err(&pdev->dev, "cpsw: error registering net device\n"); 2173d9ba8f9eSMugunthan V N free_netdev(ndev); 2174d9ba8f9eSMugunthan V N ret = -ENODEV; 2175d9ba8f9eSMugunthan V N } 2176d9ba8f9eSMugunthan V N 2177d9ba8f9eSMugunthan V N return ret; 2178d9ba8f9eSMugunthan V N } 2179d9ba8f9eSMugunthan V N 21807da11600SMugunthan V N #define CPSW_QUIRK_IRQ BIT(0) 21817da11600SMugunthan V N 21827da11600SMugunthan V N static struct platform_device_id cpsw_devtype[] = { 21837da11600SMugunthan V N { 21847da11600SMugunthan V N /* keep it for existing comaptibles */ 21857da11600SMugunthan V N .name = "cpsw", 21867da11600SMugunthan V N .driver_data = CPSW_QUIRK_IRQ, 21877da11600SMugunthan V N }, { 21887da11600SMugunthan V N .name = "am335x-cpsw", 21897da11600SMugunthan V N .driver_data = CPSW_QUIRK_IRQ, 21907da11600SMugunthan V N }, { 21917da11600SMugunthan V N .name = "am4372-cpsw", 21927da11600SMugunthan V N .driver_data = 0, 21937da11600SMugunthan V N }, { 21947da11600SMugunthan V N .name = "dra7-cpsw", 21957da11600SMugunthan V N .driver_data = 0, 21967da11600SMugunthan V N }, { 21977da11600SMugunthan V N /* sentinel */ 21987da11600SMugunthan V N } 21997da11600SMugunthan V N }; 22007da11600SMugunthan V N MODULE_DEVICE_TABLE(platform, cpsw_devtype); 22017da11600SMugunthan V N 22027da11600SMugunthan V N enum ti_cpsw_type { 22037da11600SMugunthan V N CPSW = 0, 22047da11600SMugunthan V N AM335X_CPSW, 22057da11600SMugunthan V N AM4372_CPSW, 22067da11600SMugunthan V N DRA7_CPSW, 22077da11600SMugunthan V N }; 22087da11600SMugunthan V N 22097da11600SMugunthan V N static const struct of_device_id cpsw_of_mtable[] = { 22107da11600SMugunthan V N { .compatible = "ti,cpsw", .data = &cpsw_devtype[CPSW], }, 22117da11600SMugunthan V N { .compatible = "ti,am335x-cpsw", .data = &cpsw_devtype[AM335X_CPSW], }, 22127da11600SMugunthan V N { .compatible = "ti,am4372-cpsw", .data = &cpsw_devtype[AM4372_CPSW], }, 22137da11600SMugunthan V N { .compatible = "ti,dra7-cpsw", .data = &cpsw_devtype[DRA7_CPSW], }, 22147da11600SMugunthan V N { /* sentinel */ }, 22157da11600SMugunthan V N }; 22167da11600SMugunthan V N MODULE_DEVICE_TABLE(of, cpsw_of_mtable); 22177da11600SMugunthan V N 2218663e12e6SBill Pemberton static int cpsw_probe(struct platform_device *pdev) 2219df828598SMugunthan V N { 2220d1bd9acfSSebastian Siewior struct cpsw_platform_data *data; 2221df828598SMugunthan V N struct net_device *ndev; 2222df828598SMugunthan V N struct cpsw_priv *priv; 2223df828598SMugunthan V N struct cpdma_params dma_params; 2224df828598SMugunthan V N struct cpsw_ale_params ale_params; 2225aa1a15e2SDaniel Mack void __iomem *ss_regs; 2226aa1a15e2SDaniel Mack struct resource *res, *ss_res; 22277da11600SMugunthan V N const struct of_device_id *of_id; 22281d147ccbSMugunthan V N struct gpio_descs *mode; 2229549985eeSRichard Cochran u32 slave_offset, sliver_offset, slave_size; 22305087b915SFelipe Balbi int ret = 0, i; 22315087b915SFelipe Balbi int irq; 2232df828598SMugunthan V N 2233df828598SMugunthan V N ndev = alloc_etherdev(sizeof(struct cpsw_priv)); 2234df828598SMugunthan V N if (!ndev) { 223588c99ff6SGeorge Cherian dev_err(&pdev->dev, "error allocating net_device\n"); 2236df828598SMugunthan V N return -ENOMEM; 2237df828598SMugunthan V N } 2238df828598SMugunthan V N 2239df828598SMugunthan V N platform_set_drvdata(pdev, ndev); 2240df828598SMugunthan V N priv = netdev_priv(ndev); 2241df828598SMugunthan V N spin_lock_init(&priv->lock); 2242df828598SMugunthan V N priv->pdev = pdev; 2243df828598SMugunthan V N priv->ndev = ndev; 2244df828598SMugunthan V N priv->dev = &ndev->dev; 2245df828598SMugunthan V N priv->msg_enable = netif_msg_init(debug_level, CPSW_DEBUG); 2246df828598SMugunthan V N priv->rx_packet_max = max(rx_packet_max, 128); 22479232b16dSMugunthan V N priv->cpts = devm_kzalloc(&pdev->dev, sizeof(struct cpts), GFP_KERNEL); 2248ab8e99d2SSebastian Siewior if (!priv->cpts) { 224988c99ff6SGeorge Cherian dev_err(&pdev->dev, "error allocating cpts\n"); 22504d507dffSMarkus Pargmann ret = -ENOMEM; 22519232b16dSMugunthan V N goto clean_ndev_ret; 22529232b16dSMugunthan V N } 2253df828598SMugunthan V N 22541d147ccbSMugunthan V N mode = devm_gpiod_get_array_optional(&pdev->dev, "mode", GPIOD_OUT_LOW); 22551d147ccbSMugunthan V N if (IS_ERR(mode)) { 22561d147ccbSMugunthan V N ret = PTR_ERR(mode); 22571d147ccbSMugunthan V N dev_err(&pdev->dev, "gpio request failed, ret %d\n", ret); 22581d147ccbSMugunthan V N goto clean_ndev_ret; 22591d147ccbSMugunthan V N } 22601d147ccbSMugunthan V N 22611fb19aa7SVaibhav Hiremath /* 22621fb19aa7SVaibhav Hiremath * This may be required here for child devices. 22631fb19aa7SVaibhav Hiremath */ 22641fb19aa7SVaibhav Hiremath pm_runtime_enable(&pdev->dev); 22651fb19aa7SVaibhav Hiremath 2266739683b4SMugunthan V N /* Select default pin state */ 2267739683b4SMugunthan V N pinctrl_pm_select_default_state(&pdev->dev); 2268739683b4SMugunthan V N 22699e42f715SHeiko Schocher if (cpsw_probe_dt(priv, pdev)) { 227088c99ff6SGeorge Cherian dev_err(&pdev->dev, "cpsw: platform data missing\n"); 22712eb32b0aSMugunthan V N ret = -ENODEV; 2272aa1a15e2SDaniel Mack goto clean_runtime_disable_ret; 22732eb32b0aSMugunthan V N } 22742eb32b0aSMugunthan V N data = &priv->data; 22752eb32b0aSMugunthan V N 2276df828598SMugunthan V N if (is_valid_ether_addr(data->slave_data[0].mac_addr)) { 2277df828598SMugunthan V N memcpy(priv->mac_addr, data->slave_data[0].mac_addr, ETH_ALEN); 227888c99ff6SGeorge Cherian dev_info(&pdev->dev, "Detected MACID = %pM\n", priv->mac_addr); 2279df828598SMugunthan V N } else { 22807efd26d0SJoe Perches eth_random_addr(priv->mac_addr); 228188c99ff6SGeorge Cherian dev_info(&pdev->dev, "Random MACID = %pM\n", priv->mac_addr); 2282df828598SMugunthan V N } 2283df828598SMugunthan V N 2284df828598SMugunthan V N memcpy(ndev->dev_addr, priv->mac_addr, ETH_ALEN); 2285df828598SMugunthan V N 2286aa1a15e2SDaniel Mack priv->slaves = devm_kzalloc(&pdev->dev, 2287aa1a15e2SDaniel Mack sizeof(struct cpsw_slave) * data->slaves, 2288df828598SMugunthan V N GFP_KERNEL); 2289df828598SMugunthan V N if (!priv->slaves) { 2290aa1a15e2SDaniel Mack ret = -ENOMEM; 2291aa1a15e2SDaniel Mack goto clean_runtime_disable_ret; 2292df828598SMugunthan V N } 2293df828598SMugunthan V N for (i = 0; i < data->slaves; i++) 2294df828598SMugunthan V N priv->slaves[i].slave_num = i; 2295df828598SMugunthan V N 2296d9ba8f9eSMugunthan V N priv->slaves[0].ndev = ndev; 2297d9ba8f9eSMugunthan V N priv->emac_port = 0; 2298d9ba8f9eSMugunthan V N 2299aa1a15e2SDaniel Mack priv->clk = devm_clk_get(&pdev->dev, "fck"); 2300df828598SMugunthan V N if (IS_ERR(priv->clk)) { 2301aa1a15e2SDaniel Mack dev_err(priv->dev, "fck is not found\n"); 2302f150bd7fSMugunthan V N ret = -ENODEV; 2303aa1a15e2SDaniel Mack goto clean_runtime_disable_ret; 2304df828598SMugunthan V N } 2305ff5b8ef2SMugunthan V N priv->coal_intvl = 0; 2306ff5b8ef2SMugunthan V N priv->bus_freq_mhz = clk_get_rate(priv->clk) / 1000000; 2307df828598SMugunthan V N 2308aa1a15e2SDaniel Mack ss_res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2309aa1a15e2SDaniel Mack ss_regs = devm_ioremap_resource(&pdev->dev, ss_res); 2310aa1a15e2SDaniel Mack if (IS_ERR(ss_regs)) { 2311aa1a15e2SDaniel Mack ret = PTR_ERR(ss_regs); 2312aa1a15e2SDaniel Mack goto clean_runtime_disable_ret; 2313df828598SMugunthan V N } 2314549985eeSRichard Cochran priv->regs = ss_regs; 2315df828598SMugunthan V N 2316f280e89aSMugunthan V N /* Need to enable clocks with runtime PM api to access module 2317f280e89aSMugunthan V N * registers 2318f280e89aSMugunthan V N */ 2319f280e89aSMugunthan V N pm_runtime_get_sync(&pdev->dev); 2320f280e89aSMugunthan V N priv->version = readl(&priv->regs->id_ver); 2321f280e89aSMugunthan V N pm_runtime_put_sync(&pdev->dev); 2322f280e89aSMugunthan V N 2323aa1a15e2SDaniel Mack res = platform_get_resource(pdev, IORESOURCE_MEM, 1); 2324aa1a15e2SDaniel Mack priv->wr_regs = devm_ioremap_resource(&pdev->dev, res); 2325aa1a15e2SDaniel Mack if (IS_ERR(priv->wr_regs)) { 2326aa1a15e2SDaniel Mack ret = PTR_ERR(priv->wr_regs); 2327aa1a15e2SDaniel Mack goto clean_runtime_disable_ret; 2328df828598SMugunthan V N } 2329df828598SMugunthan V N 2330df828598SMugunthan V N memset(&dma_params, 0, sizeof(dma_params)); 2331549985eeSRichard Cochran memset(&ale_params, 0, sizeof(ale_params)); 2332549985eeSRichard Cochran 2333549985eeSRichard Cochran switch (priv->version) { 2334549985eeSRichard Cochran case CPSW_VERSION_1: 2335549985eeSRichard Cochran priv->host_port_regs = ss_regs + CPSW1_HOST_PORT_OFFSET; 23369232b16dSMugunthan V N priv->cpts->reg = ss_regs + CPSW1_CPTS_OFFSET; 2337d9718546SMugunthan V N priv->hw_stats = ss_regs + CPSW1_HW_STATS; 2338549985eeSRichard Cochran dma_params.dmaregs = ss_regs + CPSW1_CPDMA_OFFSET; 2339549985eeSRichard Cochran dma_params.txhdp = ss_regs + CPSW1_STATERAM_OFFSET; 2340549985eeSRichard Cochran ale_params.ale_regs = ss_regs + CPSW1_ALE_OFFSET; 2341549985eeSRichard Cochran slave_offset = CPSW1_SLAVE_OFFSET; 2342549985eeSRichard Cochran slave_size = CPSW1_SLAVE_SIZE; 2343549985eeSRichard Cochran sliver_offset = CPSW1_SLIVER_OFFSET; 2344549985eeSRichard Cochran dma_params.desc_mem_phys = 0; 2345549985eeSRichard Cochran break; 2346549985eeSRichard Cochran case CPSW_VERSION_2: 2347c193f365SMugunthan V N case CPSW_VERSION_3: 2348926489beSMugunthan V N case CPSW_VERSION_4: 2349549985eeSRichard Cochran priv->host_port_regs = ss_regs + CPSW2_HOST_PORT_OFFSET; 23509232b16dSMugunthan V N priv->cpts->reg = ss_regs + CPSW2_CPTS_OFFSET; 2351d9718546SMugunthan V N priv->hw_stats = ss_regs + CPSW2_HW_STATS; 2352549985eeSRichard Cochran dma_params.dmaregs = ss_regs + CPSW2_CPDMA_OFFSET; 2353549985eeSRichard Cochran dma_params.txhdp = ss_regs + CPSW2_STATERAM_OFFSET; 2354549985eeSRichard Cochran ale_params.ale_regs = ss_regs + CPSW2_ALE_OFFSET; 2355549985eeSRichard Cochran slave_offset = CPSW2_SLAVE_OFFSET; 2356549985eeSRichard Cochran slave_size = CPSW2_SLAVE_SIZE; 2357549985eeSRichard Cochran sliver_offset = CPSW2_SLIVER_OFFSET; 2358549985eeSRichard Cochran dma_params.desc_mem_phys = 2359aa1a15e2SDaniel Mack (u32 __force) ss_res->start + CPSW2_BD_OFFSET; 2360549985eeSRichard Cochran break; 2361549985eeSRichard Cochran default: 2362549985eeSRichard Cochran dev_err(priv->dev, "unknown version 0x%08x\n", priv->version); 2363549985eeSRichard Cochran ret = -ENODEV; 2364aa1a15e2SDaniel Mack goto clean_runtime_disable_ret; 2365549985eeSRichard Cochran } 2366549985eeSRichard Cochran for (i = 0; i < priv->data.slaves; i++) { 2367549985eeSRichard Cochran struct cpsw_slave *slave = &priv->slaves[i]; 2368549985eeSRichard Cochran cpsw_slave_init(slave, priv, slave_offset, sliver_offset); 2369549985eeSRichard Cochran slave_offset += slave_size; 2370549985eeSRichard Cochran sliver_offset += SLIVER_SIZE; 2371549985eeSRichard Cochran } 2372549985eeSRichard Cochran 2373df828598SMugunthan V N dma_params.dev = &pdev->dev; 2374549985eeSRichard Cochran dma_params.rxthresh = dma_params.dmaregs + CPDMA_RXTHRESH; 2375549985eeSRichard Cochran dma_params.rxfree = dma_params.dmaregs + CPDMA_RXFREE; 2376549985eeSRichard Cochran dma_params.rxhdp = dma_params.txhdp + CPDMA_RXHDP; 2377549985eeSRichard Cochran dma_params.txcp = dma_params.txhdp + CPDMA_TXCP; 2378549985eeSRichard Cochran dma_params.rxcp = dma_params.txhdp + CPDMA_RXCP; 2379df828598SMugunthan V N 2380df828598SMugunthan V N dma_params.num_chan = data->channels; 2381df828598SMugunthan V N dma_params.has_soft_reset = true; 2382df828598SMugunthan V N dma_params.min_packet_size = CPSW_MIN_PACKET_SIZE; 2383df828598SMugunthan V N dma_params.desc_mem_size = data->bd_ram_size; 2384df828598SMugunthan V N dma_params.desc_align = 16; 2385df828598SMugunthan V N dma_params.has_ext_regs = true; 2386549985eeSRichard Cochran dma_params.desc_hw_addr = dma_params.desc_mem_phys; 2387df828598SMugunthan V N 2388df828598SMugunthan V N priv->dma = cpdma_ctlr_create(&dma_params); 2389df828598SMugunthan V N if (!priv->dma) { 2390df828598SMugunthan V N dev_err(priv->dev, "error initializing dma\n"); 2391df828598SMugunthan V N ret = -ENOMEM; 2392aa1a15e2SDaniel Mack goto clean_runtime_disable_ret; 2393df828598SMugunthan V N } 2394df828598SMugunthan V N 2395df828598SMugunthan V N priv->txch = cpdma_chan_create(priv->dma, tx_chan_num(0), 2396df828598SMugunthan V N cpsw_tx_handler); 2397df828598SMugunthan V N priv->rxch = cpdma_chan_create(priv->dma, rx_chan_num(0), 2398df828598SMugunthan V N cpsw_rx_handler); 2399df828598SMugunthan V N 2400df828598SMugunthan V N if (WARN_ON(!priv->txch || !priv->rxch)) { 2401df828598SMugunthan V N dev_err(priv->dev, "error initializing dma channels\n"); 2402df828598SMugunthan V N ret = -ENOMEM; 2403df828598SMugunthan V N goto clean_dma_ret; 2404df828598SMugunthan V N } 2405df828598SMugunthan V N 2406df828598SMugunthan V N ale_params.dev = &ndev->dev; 2407df828598SMugunthan V N ale_params.ale_ageout = ale_ageout; 2408df828598SMugunthan V N ale_params.ale_entries = data->ale_entries; 2409df828598SMugunthan V N ale_params.ale_ports = data->slaves; 2410df828598SMugunthan V N 2411df828598SMugunthan V N priv->ale = cpsw_ale_create(&ale_params); 2412df828598SMugunthan V N if (!priv->ale) { 2413df828598SMugunthan V N dev_err(priv->dev, "error initializing ale engine\n"); 2414df828598SMugunthan V N ret = -ENODEV; 2415df828598SMugunthan V N goto clean_dma_ret; 2416df828598SMugunthan V N } 2417df828598SMugunthan V N 2418c03abd84SFelipe Balbi ndev->irq = platform_get_irq(pdev, 1); 2419df828598SMugunthan V N if (ndev->irq < 0) { 2420df828598SMugunthan V N dev_err(priv->dev, "error getting irq resource\n"); 2421c1e3334fSJulia Lawall ret = ndev->irq; 2422df828598SMugunthan V N goto clean_ale_ret; 2423df828598SMugunthan V N } 2424df828598SMugunthan V N 24257da11600SMugunthan V N of_id = of_match_device(cpsw_of_mtable, &pdev->dev); 24267da11600SMugunthan V N if (of_id) { 24277da11600SMugunthan V N pdev->id_entry = of_id->data; 24287da11600SMugunthan V N if (pdev->id_entry->driver_data) 24297da11600SMugunthan V N priv->quirk_irq = true; 24307da11600SMugunthan V N } 24317da11600SMugunthan V N 2432c03abd84SFelipe Balbi /* Grab RX and TX IRQs. Note that we also have RX_THRESHOLD and 2433c03abd84SFelipe Balbi * MISC IRQs which are always kept disabled with this driver so 2434c03abd84SFelipe Balbi * we will not request them. 2435c03abd84SFelipe Balbi * 2436c03abd84SFelipe Balbi * If anyone wants to implement support for those, make sure to 2437c03abd84SFelipe Balbi * first request and append them to irqs_table array. 2438c03abd84SFelipe Balbi */ 2439c2b32e58SDaniel Mack 2440c03abd84SFelipe Balbi /* RX IRQ */ 24415087b915SFelipe Balbi irq = platform_get_irq(pdev, 1); 2442c1e3334fSJulia Lawall if (irq < 0) { 2443c1e3334fSJulia Lawall ret = irq; 24445087b915SFelipe Balbi goto clean_ale_ret; 2445c1e3334fSJulia Lawall } 24465087b915SFelipe Balbi 2447c03abd84SFelipe Balbi priv->irqs_table[0] = irq; 2448c03abd84SFelipe Balbi ret = devm_request_irq(&pdev->dev, irq, cpsw_rx_interrupt, 24495087b915SFelipe Balbi 0, dev_name(&pdev->dev), priv); 24505087b915SFelipe Balbi if (ret < 0) { 24515087b915SFelipe Balbi dev_err(priv->dev, "error attaching irq (%d)\n", ret); 24525087b915SFelipe Balbi goto clean_ale_ret; 2453df828598SMugunthan V N } 2454df828598SMugunthan V N 2455c03abd84SFelipe Balbi /* TX IRQ */ 24565087b915SFelipe Balbi irq = platform_get_irq(pdev, 2); 2457c1e3334fSJulia Lawall if (irq < 0) { 2458c1e3334fSJulia Lawall ret = irq; 24595087b915SFelipe Balbi goto clean_ale_ret; 2460c1e3334fSJulia Lawall } 24615087b915SFelipe Balbi 2462c03abd84SFelipe Balbi priv->irqs_table[1] = irq; 2463c03abd84SFelipe Balbi ret = devm_request_irq(&pdev->dev, irq, cpsw_tx_interrupt, 24645087b915SFelipe Balbi 0, dev_name(&pdev->dev), priv); 24655087b915SFelipe Balbi if (ret < 0) { 24665087b915SFelipe Balbi dev_err(priv->dev, "error attaching irq (%d)\n", ret); 24675087b915SFelipe Balbi goto clean_ale_ret; 24685087b915SFelipe Balbi } 2469c03abd84SFelipe Balbi priv->num_irqs = 2; 2470c2b32e58SDaniel Mack 2471f646968fSPatrick McHardy ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER; 2472df828598SMugunthan V N 2473df828598SMugunthan V N ndev->netdev_ops = &cpsw_netdev_ops; 24747ad24ea4SWilfried Klaebe ndev->ethtool_ops = &cpsw_ethtool_ops; 247532a7432cSMugunthan V N netif_napi_add(ndev, &priv->napi_rx, cpsw_rx_poll, CPSW_POLL_WEIGHT); 2476d64b5e85SEric Dumazet netif_tx_napi_add(ndev, &priv->napi_tx, cpsw_tx_poll, CPSW_POLL_WEIGHT); 2477df828598SMugunthan V N 2478df828598SMugunthan V N /* register the network device */ 2479df828598SMugunthan V N SET_NETDEV_DEV(ndev, &pdev->dev); 2480df828598SMugunthan V N ret = register_netdev(ndev); 2481df828598SMugunthan V N if (ret) { 2482df828598SMugunthan V N dev_err(priv->dev, "error registering net device\n"); 2483df828598SMugunthan V N ret = -ENODEV; 2484aa1a15e2SDaniel Mack goto clean_ale_ret; 2485df828598SMugunthan V N } 2486df828598SMugunthan V N 24871a3b5056SOlof Johansson cpsw_notice(priv, probe, "initialized device (regs %pa, irq %d)\n", 24881a3b5056SOlof Johansson &ss_res->start, ndev->irq); 2489df828598SMugunthan V N 2490d9ba8f9eSMugunthan V N if (priv->data.dual_emac) { 2491d9ba8f9eSMugunthan V N ret = cpsw_probe_dual_emac(pdev, priv); 2492d9ba8f9eSMugunthan V N if (ret) { 2493d9ba8f9eSMugunthan V N cpsw_err(priv, probe, "error probe slave 2 emac interface\n"); 2494aa1a15e2SDaniel Mack goto clean_ale_ret; 2495d9ba8f9eSMugunthan V N } 2496d9ba8f9eSMugunthan V N } 2497d9ba8f9eSMugunthan V N 2498df828598SMugunthan V N return 0; 2499df828598SMugunthan V N 2500df828598SMugunthan V N clean_ale_ret: 2501df828598SMugunthan V N cpsw_ale_destroy(priv->ale); 2502df828598SMugunthan V N clean_dma_ret: 2503df828598SMugunthan V N cpdma_chan_destroy(priv->txch); 2504df828598SMugunthan V N cpdma_chan_destroy(priv->rxch); 2505df828598SMugunthan V N cpdma_ctlr_destroy(priv->dma); 2506aa1a15e2SDaniel Mack clean_runtime_disable_ret: 2507f150bd7fSMugunthan V N pm_runtime_disable(&pdev->dev); 2508df828598SMugunthan V N clean_ndev_ret: 2509d1bd9acfSSebastian Siewior free_netdev(priv->ndev); 2510df828598SMugunthan V N return ret; 2511df828598SMugunthan V N } 2512df828598SMugunthan V N 2513030b16a0SMugunthan V N static int cpsw_remove_child_device(struct device *dev, void *c) 2514030b16a0SMugunthan V N { 2515030b16a0SMugunthan V N struct platform_device *pdev = to_platform_device(dev); 2516030b16a0SMugunthan V N 2517030b16a0SMugunthan V N of_device_unregister(pdev); 2518030b16a0SMugunthan V N 2519030b16a0SMugunthan V N return 0; 2520030b16a0SMugunthan V N } 2521030b16a0SMugunthan V N 2522663e12e6SBill Pemberton static int cpsw_remove(struct platform_device *pdev) 2523df828598SMugunthan V N { 2524df828598SMugunthan V N struct net_device *ndev = platform_get_drvdata(pdev); 2525df828598SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 2526df828598SMugunthan V N 2527d1bd9acfSSebastian Siewior if (priv->data.dual_emac) 2528d1bd9acfSSebastian Siewior unregister_netdev(cpsw_get_slave_ndev(priv, 1)); 2529d1bd9acfSSebastian Siewior unregister_netdev(ndev); 2530df828598SMugunthan V N 2531df828598SMugunthan V N cpsw_ale_destroy(priv->ale); 2532df828598SMugunthan V N cpdma_chan_destroy(priv->txch); 2533df828598SMugunthan V N cpdma_chan_destroy(priv->rxch); 2534df828598SMugunthan V N cpdma_ctlr_destroy(priv->dma); 2535f150bd7fSMugunthan V N pm_runtime_disable(&pdev->dev); 2536030b16a0SMugunthan V N device_for_each_child(&pdev->dev, NULL, cpsw_remove_child_device); 2537d1bd9acfSSebastian Siewior if (priv->data.dual_emac) 2538d1bd9acfSSebastian Siewior free_netdev(cpsw_get_slave_ndev(priv, 1)); 2539df828598SMugunthan V N free_netdev(ndev); 2540df828598SMugunthan V N return 0; 2541df828598SMugunthan V N } 2542df828598SMugunthan V N 25438963a504SGrygorii Strashko #ifdef CONFIG_PM_SLEEP 2544df828598SMugunthan V N static int cpsw_suspend(struct device *dev) 2545df828598SMugunthan V N { 2546df828598SMugunthan V N struct platform_device *pdev = to_platform_device(dev); 2547df828598SMugunthan V N struct net_device *ndev = platform_get_drvdata(pdev); 2548b90fc27aSMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 2549df828598SMugunthan V N 2550618073e3SMugunthan V N if (priv->data.dual_emac) { 2551618073e3SMugunthan V N int i; 2552618073e3SMugunthan V N 2553618073e3SMugunthan V N for (i = 0; i < priv->data.slaves; i++) { 2554618073e3SMugunthan V N if (netif_running(priv->slaves[i].ndev)) 2555618073e3SMugunthan V N cpsw_ndo_stop(priv->slaves[i].ndev); 2556618073e3SMugunthan V N soft_reset_slave(priv->slaves + i); 2557618073e3SMugunthan V N } 2558618073e3SMugunthan V N } else { 2559df828598SMugunthan V N if (netif_running(ndev)) 2560df828598SMugunthan V N cpsw_ndo_stop(ndev); 25611e7a2e21SDaniel Mack for_each_slave(priv, soft_reset_slave); 2562618073e3SMugunthan V N } 25631e7a2e21SDaniel Mack 2564f150bd7fSMugunthan V N pm_runtime_put_sync(&pdev->dev); 2565f150bd7fSMugunthan V N 2566739683b4SMugunthan V N /* Select sleep pin state */ 2567739683b4SMugunthan V N pinctrl_pm_select_sleep_state(&pdev->dev); 2568739683b4SMugunthan V N 2569df828598SMugunthan V N return 0; 2570df828598SMugunthan V N } 2571df828598SMugunthan V N 2572df828598SMugunthan V N static int cpsw_resume(struct device *dev) 2573df828598SMugunthan V N { 2574df828598SMugunthan V N struct platform_device *pdev = to_platform_device(dev); 2575df828598SMugunthan V N struct net_device *ndev = platform_get_drvdata(pdev); 2576618073e3SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 2577df828598SMugunthan V N 2578f150bd7fSMugunthan V N pm_runtime_get_sync(&pdev->dev); 2579739683b4SMugunthan V N 2580739683b4SMugunthan V N /* Select default pin state */ 2581739683b4SMugunthan V N pinctrl_pm_select_default_state(&pdev->dev); 2582739683b4SMugunthan V N 2583618073e3SMugunthan V N if (priv->data.dual_emac) { 2584618073e3SMugunthan V N int i; 2585618073e3SMugunthan V N 2586618073e3SMugunthan V N for (i = 0; i < priv->data.slaves; i++) { 2587618073e3SMugunthan V N if (netif_running(priv->slaves[i].ndev)) 2588618073e3SMugunthan V N cpsw_ndo_open(priv->slaves[i].ndev); 2589618073e3SMugunthan V N } 2590618073e3SMugunthan V N } else { 2591df828598SMugunthan V N if (netif_running(ndev)) 2592df828598SMugunthan V N cpsw_ndo_open(ndev); 2593618073e3SMugunthan V N } 2594df828598SMugunthan V N return 0; 2595df828598SMugunthan V N } 25968963a504SGrygorii Strashko #endif 2597df828598SMugunthan V N 25988963a504SGrygorii Strashko static SIMPLE_DEV_PM_OPS(cpsw_pm_ops, cpsw_suspend, cpsw_resume); 2599df828598SMugunthan V N 2600df828598SMugunthan V N static struct platform_driver cpsw_driver = { 2601df828598SMugunthan V N .driver = { 2602df828598SMugunthan V N .name = "cpsw", 2603df828598SMugunthan V N .pm = &cpsw_pm_ops, 26041e5c76d4SSachin Kamat .of_match_table = cpsw_of_mtable, 2605df828598SMugunthan V N }, 2606df828598SMugunthan V N .probe = cpsw_probe, 2607663e12e6SBill Pemberton .remove = cpsw_remove, 2608df828598SMugunthan V N }; 2609df828598SMugunthan V N 26106fb3b6b5SGrygorii Strashko module_platform_driver(cpsw_driver); 2611df828598SMugunthan V N 2612df828598SMugunthan V N MODULE_LICENSE("GPL"); 2613df828598SMugunthan V N MODULE_AUTHOR("Cyril Chemparathy <cyril@ti.com>"); 2614df828598SMugunthan V N MODULE_AUTHOR("Mugunthan V N <mugunthanvnm@ti.com>"); 2615df828598SMugunthan V N MODULE_DESCRIPTION("TI CPSW Ethernet driver"); 2616