1df828598SMugunthan V N /* 2df828598SMugunthan V N * Texas Instruments Ethernet Switch Driver 3df828598SMugunthan V N * 4df828598SMugunthan V N * Copyright (C) 2012 Texas Instruments 5df828598SMugunthan V N * 6df828598SMugunthan V N * This program is free software; you can redistribute it and/or 7df828598SMugunthan V N * modify it under the terms of the GNU General Public License as 8df828598SMugunthan V N * published by the Free Software Foundation version 2. 9df828598SMugunthan V N * 10df828598SMugunthan V N * This program is distributed "as is" WITHOUT ANY WARRANTY of any 11df828598SMugunthan V N * kind, whether express or implied; without even the implied warranty 12df828598SMugunthan V N * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13df828598SMugunthan V N * GNU General Public License for more details. 14df828598SMugunthan V N */ 15df828598SMugunthan V N 16df828598SMugunthan V N #include <linux/kernel.h> 17df828598SMugunthan V N #include <linux/io.h> 18df828598SMugunthan V N #include <linux/clk.h> 19df828598SMugunthan V N #include <linux/timer.h> 20df828598SMugunthan V N #include <linux/module.h> 21df828598SMugunthan V N #include <linux/platform_device.h> 22df828598SMugunthan V N #include <linux/irqreturn.h> 23df828598SMugunthan V N #include <linux/interrupt.h> 24df828598SMugunthan V N #include <linux/if_ether.h> 25df828598SMugunthan V N #include <linux/etherdevice.h> 26df828598SMugunthan V N #include <linux/netdevice.h> 27df828598SMugunthan V N #include <linux/phy.h> 28df828598SMugunthan V N #include <linux/workqueue.h> 29df828598SMugunthan V N #include <linux/delay.h> 30f150bd7fSMugunthan V N #include <linux/pm_runtime.h> 312eb32b0aSMugunthan V N #include <linux/of.h> 322eb32b0aSMugunthan V N #include <linux/of_net.h> 332eb32b0aSMugunthan V N #include <linux/of_device.h> 34df828598SMugunthan V N 35df828598SMugunthan V N #include <linux/platform_data/cpsw.h> 36df828598SMugunthan V N 37df828598SMugunthan V N #include "cpsw_ale.h" 38df828598SMugunthan V N #include "davinci_cpdma.h" 39df828598SMugunthan V N 40df828598SMugunthan V N #define CPSW_DEBUG (NETIF_MSG_HW | NETIF_MSG_WOL | \ 41df828598SMugunthan V N NETIF_MSG_DRV | NETIF_MSG_LINK | \ 42df828598SMugunthan V N NETIF_MSG_IFUP | NETIF_MSG_INTR | \ 43df828598SMugunthan V N NETIF_MSG_PROBE | NETIF_MSG_TIMER | \ 44df828598SMugunthan V N NETIF_MSG_IFDOWN | NETIF_MSG_RX_ERR | \ 45df828598SMugunthan V N NETIF_MSG_TX_ERR | NETIF_MSG_TX_DONE | \ 46df828598SMugunthan V N NETIF_MSG_PKTDATA | NETIF_MSG_TX_QUEUED | \ 47df828598SMugunthan V N NETIF_MSG_RX_STATUS) 48df828598SMugunthan V N 49df828598SMugunthan V N #define cpsw_info(priv, type, format, ...) \ 50df828598SMugunthan V N do { \ 51df828598SMugunthan V N if (netif_msg_##type(priv) && net_ratelimit()) \ 52df828598SMugunthan V N dev_info(priv->dev, format, ## __VA_ARGS__); \ 53df828598SMugunthan V N } while (0) 54df828598SMugunthan V N 55df828598SMugunthan V N #define cpsw_err(priv, type, format, ...) \ 56df828598SMugunthan V N do { \ 57df828598SMugunthan V N if (netif_msg_##type(priv) && net_ratelimit()) \ 58df828598SMugunthan V N dev_err(priv->dev, format, ## __VA_ARGS__); \ 59df828598SMugunthan V N } while (0) 60df828598SMugunthan V N 61df828598SMugunthan V N #define cpsw_dbg(priv, type, format, ...) \ 62df828598SMugunthan V N do { \ 63df828598SMugunthan V N if (netif_msg_##type(priv) && net_ratelimit()) \ 64df828598SMugunthan V N dev_dbg(priv->dev, format, ## __VA_ARGS__); \ 65df828598SMugunthan V N } while (0) 66df828598SMugunthan V N 67df828598SMugunthan V N #define cpsw_notice(priv, type, format, ...) \ 68df828598SMugunthan V N do { \ 69df828598SMugunthan V N if (netif_msg_##type(priv) && net_ratelimit()) \ 70df828598SMugunthan V N dev_notice(priv->dev, format, ## __VA_ARGS__); \ 71df828598SMugunthan V N } while (0) 72df828598SMugunthan V N 735c50a856SMugunthan V N #define ALE_ALL_PORTS 0x7 745c50a856SMugunthan V N 75df828598SMugunthan V N #define CPSW_MAJOR_VERSION(reg) (reg >> 8 & 0x7) 76df828598SMugunthan V N #define CPSW_MINOR_VERSION(reg) (reg & 0xff) 77df828598SMugunthan V N #define CPSW_RTL_VERSION(reg) ((reg >> 11) & 0x1f) 78df828598SMugunthan V N 79e90cfac6SRichard Cochran #define CPSW_VERSION_1 0x19010a 80e90cfac6SRichard Cochran #define CPSW_VERSION_2 0x19010c 81df828598SMugunthan V N #define CPDMA_RXTHRESH 0x0c0 82df828598SMugunthan V N #define CPDMA_RXFREE 0x0e0 83df828598SMugunthan V N #define CPDMA_TXHDP 0x00 84df828598SMugunthan V N #define CPDMA_RXHDP 0x20 85df828598SMugunthan V N #define CPDMA_TXCP 0x40 86df828598SMugunthan V N #define CPDMA_RXCP 0x60 87df828598SMugunthan V N 88df828598SMugunthan V N #define cpsw_dma_regs(base, offset) \ 89df828598SMugunthan V N (void __iomem *)((base) + (offset)) 90df828598SMugunthan V N #define cpsw_dma_rxthresh(base, offset) \ 91df828598SMugunthan V N (void __iomem *)((base) + (offset) + CPDMA_RXTHRESH) 92df828598SMugunthan V N #define cpsw_dma_rxfree(base, offset) \ 93df828598SMugunthan V N (void __iomem *)((base) + (offset) + CPDMA_RXFREE) 94df828598SMugunthan V N #define cpsw_dma_txhdp(base, offset) \ 95df828598SMugunthan V N (void __iomem *)((base) + (offset) + CPDMA_TXHDP) 96df828598SMugunthan V N #define cpsw_dma_rxhdp(base, offset) \ 97df828598SMugunthan V N (void __iomem *)((base) + (offset) + CPDMA_RXHDP) 98df828598SMugunthan V N #define cpsw_dma_txcp(base, offset) \ 99df828598SMugunthan V N (void __iomem *)((base) + (offset) + CPDMA_TXCP) 100df828598SMugunthan V N #define cpsw_dma_rxcp(base, offset) \ 101df828598SMugunthan V N (void __iomem *)((base) + (offset) + CPDMA_RXCP) 102df828598SMugunthan V N 103df828598SMugunthan V N #define CPSW_POLL_WEIGHT 64 104df828598SMugunthan V N #define CPSW_MIN_PACKET_SIZE 60 105df828598SMugunthan V N #define CPSW_MAX_PACKET_SIZE (1500 + 14 + 4 + 4) 106df828598SMugunthan V N 107df828598SMugunthan V N #define RX_PRIORITY_MAPPING 0x76543210 108df828598SMugunthan V N #define TX_PRIORITY_MAPPING 0x33221100 109df828598SMugunthan V N #define CPDMA_TX_PRIORITY_MAP 0x76543210 110df828598SMugunthan V N 111df828598SMugunthan V N #define cpsw_enable_irq(priv) \ 112df828598SMugunthan V N do { \ 113df828598SMugunthan V N u32 i; \ 114df828598SMugunthan V N for (i = 0; i < priv->num_irqs; i++) \ 115df828598SMugunthan V N enable_irq(priv->irqs_table[i]); \ 116df828598SMugunthan V N } while (0); 117df828598SMugunthan V N #define cpsw_disable_irq(priv) \ 118df828598SMugunthan V N do { \ 119df828598SMugunthan V N u32 i; \ 120df828598SMugunthan V N for (i = 0; i < priv->num_irqs; i++) \ 121df828598SMugunthan V N disable_irq_nosync(priv->irqs_table[i]); \ 122df828598SMugunthan V N } while (0); 123df828598SMugunthan V N 124df828598SMugunthan V N static int debug_level; 125df828598SMugunthan V N module_param(debug_level, int, 0); 126df828598SMugunthan V N MODULE_PARM_DESC(debug_level, "cpsw debug level (NETIF_MSG bits)"); 127df828598SMugunthan V N 128df828598SMugunthan V N static int ale_ageout = 10; 129df828598SMugunthan V N module_param(ale_ageout, int, 0); 130df828598SMugunthan V N MODULE_PARM_DESC(ale_ageout, "cpsw ale ageout interval (seconds)"); 131df828598SMugunthan V N 132df828598SMugunthan V N static int rx_packet_max = CPSW_MAX_PACKET_SIZE; 133df828598SMugunthan V N module_param(rx_packet_max, int, 0); 134df828598SMugunthan V N MODULE_PARM_DESC(rx_packet_max, "maximum receive packet size (bytes)"); 135df828598SMugunthan V N 136996a5c27SRichard Cochran struct cpsw_wr_regs { 137df828598SMugunthan V N u32 id_ver; 138df828598SMugunthan V N u32 soft_reset; 139df828598SMugunthan V N u32 control; 140df828598SMugunthan V N u32 int_control; 141df828598SMugunthan V N u32 rx_thresh_en; 142df828598SMugunthan V N u32 rx_en; 143df828598SMugunthan V N u32 tx_en; 144df828598SMugunthan V N u32 misc_en; 145df828598SMugunthan V N }; 146df828598SMugunthan V N 147996a5c27SRichard Cochran struct cpsw_ss_regs { 148df828598SMugunthan V N u32 id_ver; 149df828598SMugunthan V N u32 control; 150df828598SMugunthan V N u32 soft_reset; 151df828598SMugunthan V N u32 stat_port_en; 152df828598SMugunthan V N u32 ptype; 153bd357af2SRichard Cochran u32 soft_idle; 154bd357af2SRichard Cochran u32 thru_rate; 155bd357af2SRichard Cochran u32 gap_thresh; 156bd357af2SRichard Cochran u32 tx_start_wds; 157bd357af2SRichard Cochran u32 flow_control; 158bd357af2SRichard Cochran u32 vlan_ltype; 159bd357af2SRichard Cochran u32 ts_ltype; 160bd357af2SRichard Cochran u32 dlr_ltype; 161df828598SMugunthan V N }; 162df828598SMugunthan V N 1639750a3adSRichard Cochran /* CPSW_PORT_V1 */ 1649750a3adSRichard Cochran #define CPSW1_MAX_BLKS 0x00 /* Maximum FIFO Blocks */ 1659750a3adSRichard Cochran #define CPSW1_BLK_CNT 0x04 /* FIFO Block Usage Count (Read Only) */ 1669750a3adSRichard Cochran #define CPSW1_TX_IN_CTL 0x08 /* Transmit FIFO Control */ 1679750a3adSRichard Cochran #define CPSW1_PORT_VLAN 0x0c /* VLAN Register */ 1689750a3adSRichard Cochran #define CPSW1_TX_PRI_MAP 0x10 /* Tx Header Priority to Switch Pri Mapping */ 1699750a3adSRichard Cochran #define CPSW1_TS_CTL 0x14 /* Time Sync Control */ 1709750a3adSRichard Cochran #define CPSW1_TS_SEQ_LTYPE 0x18 /* Time Sync Sequence ID Offset and Msg Type */ 1719750a3adSRichard Cochran #define CPSW1_TS_VLAN 0x1c /* Time Sync VLAN1 and VLAN2 */ 1729750a3adSRichard Cochran 1739750a3adSRichard Cochran /* CPSW_PORT_V2 */ 1749750a3adSRichard Cochran #define CPSW2_CONTROL 0x00 /* Control Register */ 1759750a3adSRichard Cochran #define CPSW2_MAX_BLKS 0x08 /* Maximum FIFO Blocks */ 1769750a3adSRichard Cochran #define CPSW2_BLK_CNT 0x0c /* FIFO Block Usage Count (Read Only) */ 1779750a3adSRichard Cochran #define CPSW2_TX_IN_CTL 0x10 /* Transmit FIFO Control */ 1789750a3adSRichard Cochran #define CPSW2_PORT_VLAN 0x14 /* VLAN Register */ 1799750a3adSRichard Cochran #define CPSW2_TX_PRI_MAP 0x18 /* Tx Header Priority to Switch Pri Mapping */ 1809750a3adSRichard Cochran #define CPSW2_TS_SEQ_MTYPE 0x1c /* Time Sync Sequence ID Offset and Msg Type */ 1819750a3adSRichard Cochran 1829750a3adSRichard Cochran /* CPSW_PORT_V1 and V2 */ 1839750a3adSRichard Cochran #define SA_LO 0x20 /* CPGMAC_SL Source Address Low */ 1849750a3adSRichard Cochran #define SA_HI 0x24 /* CPGMAC_SL Source Address High */ 1859750a3adSRichard Cochran #define SEND_PERCENT 0x28 /* Transmit Queue Send Percentages */ 1869750a3adSRichard Cochran 1879750a3adSRichard Cochran /* CPSW_PORT_V2 only */ 1889750a3adSRichard Cochran #define RX_DSCP_PRI_MAP0 0x30 /* Rx DSCP Priority to Rx Packet Mapping */ 1899750a3adSRichard Cochran #define RX_DSCP_PRI_MAP1 0x34 /* Rx DSCP Priority to Rx Packet Mapping */ 1909750a3adSRichard Cochran #define RX_DSCP_PRI_MAP2 0x38 /* Rx DSCP Priority to Rx Packet Mapping */ 1919750a3adSRichard Cochran #define RX_DSCP_PRI_MAP3 0x3c /* Rx DSCP Priority to Rx Packet Mapping */ 1929750a3adSRichard Cochran #define RX_DSCP_PRI_MAP4 0x40 /* Rx DSCP Priority to Rx Packet Mapping */ 1939750a3adSRichard Cochran #define RX_DSCP_PRI_MAP5 0x44 /* Rx DSCP Priority to Rx Packet Mapping */ 1949750a3adSRichard Cochran #define RX_DSCP_PRI_MAP6 0x48 /* Rx DSCP Priority to Rx Packet Mapping */ 1959750a3adSRichard Cochran #define RX_DSCP_PRI_MAP7 0x4c /* Rx DSCP Priority to Rx Packet Mapping */ 1969750a3adSRichard Cochran 1979750a3adSRichard Cochran /* Bit definitions for the CPSW2_CONTROL register */ 1989750a3adSRichard Cochran #define PASS_PRI_TAGGED (1<<24) /* Pass Priority Tagged */ 1999750a3adSRichard Cochran #define VLAN_LTYPE2_EN (1<<21) /* VLAN LTYPE 2 enable */ 2009750a3adSRichard Cochran #define VLAN_LTYPE1_EN (1<<20) /* VLAN LTYPE 1 enable */ 2019750a3adSRichard Cochran #define DSCP_PRI_EN (1<<16) /* DSCP Priority Enable */ 2029750a3adSRichard Cochran #define TS_320 (1<<14) /* Time Sync Dest Port 320 enable */ 2039750a3adSRichard Cochran #define TS_319 (1<<13) /* Time Sync Dest Port 319 enable */ 2049750a3adSRichard Cochran #define TS_132 (1<<12) /* Time Sync Dest IP Addr 132 enable */ 2059750a3adSRichard Cochran #define TS_131 (1<<11) /* Time Sync Dest IP Addr 131 enable */ 2069750a3adSRichard Cochran #define TS_130 (1<<10) /* Time Sync Dest IP Addr 130 enable */ 2079750a3adSRichard Cochran #define TS_129 (1<<9) /* Time Sync Dest IP Addr 129 enable */ 2089750a3adSRichard Cochran #define TS_BIT8 (1<<8) /* ts_ttl_nonzero? */ 2099750a3adSRichard Cochran #define TS_ANNEX_D_EN (1<<4) /* Time Sync Annex D enable */ 2109750a3adSRichard Cochran #define TS_LTYPE2_EN (1<<3) /* Time Sync LTYPE 2 enable */ 2119750a3adSRichard Cochran #define TS_LTYPE1_EN (1<<2) /* Time Sync LTYPE 1 enable */ 2129750a3adSRichard Cochran #define TS_TX_EN (1<<1) /* Time Sync Transmit Enable */ 2139750a3adSRichard Cochran #define TS_RX_EN (1<<0) /* Time Sync Receive Enable */ 2149750a3adSRichard Cochran 2159750a3adSRichard Cochran #define CTRL_TS_BITS \ 2169750a3adSRichard Cochran (TS_320 | TS_319 | TS_132 | TS_131 | TS_130 | TS_129 | TS_BIT8 | \ 2179750a3adSRichard Cochran TS_ANNEX_D_EN | TS_LTYPE1_EN) 2189750a3adSRichard Cochran 2199750a3adSRichard Cochran #define CTRL_ALL_TS_MASK (CTRL_TS_BITS | TS_TX_EN | TS_RX_EN) 2209750a3adSRichard Cochran #define CTRL_TX_TS_BITS (CTRL_TS_BITS | TS_TX_EN) 2219750a3adSRichard Cochran #define CTRL_RX_TS_BITS (CTRL_TS_BITS | TS_RX_EN) 2229750a3adSRichard Cochran 2239750a3adSRichard Cochran /* Bit definitions for the CPSW2_TS_SEQ_MTYPE register */ 2249750a3adSRichard Cochran #define TS_SEQ_ID_OFFSET_SHIFT (16) /* Time Sync Sequence ID Offset */ 2259750a3adSRichard Cochran #define TS_SEQ_ID_OFFSET_MASK (0x3f) 2269750a3adSRichard Cochran #define TS_MSG_TYPE_EN_SHIFT (0) /* Time Sync Message Type Enable */ 2279750a3adSRichard Cochran #define TS_MSG_TYPE_EN_MASK (0xffff) 2289750a3adSRichard Cochran 2299750a3adSRichard Cochran /* The PTP event messages - Sync, Delay_Req, Pdelay_Req, and Pdelay_Resp. */ 2309750a3adSRichard Cochran #define EVENT_MSG_BITS ((1<<0) | (1<<1) | (1<<2) | (1<<3)) 231df828598SMugunthan V N 232df828598SMugunthan V N struct cpsw_host_regs { 233df828598SMugunthan V N u32 max_blks; 234df828598SMugunthan V N u32 blk_cnt; 235df828598SMugunthan V N u32 flow_thresh; 236df828598SMugunthan V N u32 port_vlan; 237df828598SMugunthan V N u32 tx_pri_map; 238df828598SMugunthan V N u32 cpdma_tx_pri_map; 239df828598SMugunthan V N u32 cpdma_rx_chan_map; 240df828598SMugunthan V N }; 241df828598SMugunthan V N 242df828598SMugunthan V N struct cpsw_sliver_regs { 243df828598SMugunthan V N u32 id_ver; 244df828598SMugunthan V N u32 mac_control; 245df828598SMugunthan V N u32 mac_status; 246df828598SMugunthan V N u32 soft_reset; 247df828598SMugunthan V N u32 rx_maxlen; 248df828598SMugunthan V N u32 __reserved_0; 249df828598SMugunthan V N u32 rx_pause; 250df828598SMugunthan V N u32 tx_pause; 251df828598SMugunthan V N u32 __reserved_1; 252df828598SMugunthan V N u32 rx_pri_map; 253df828598SMugunthan V N }; 254df828598SMugunthan V N 255df828598SMugunthan V N struct cpsw_slave { 2569750a3adSRichard Cochran void __iomem *regs; 257df828598SMugunthan V N struct cpsw_sliver_regs __iomem *sliver; 258df828598SMugunthan V N int slave_num; 259df828598SMugunthan V N u32 mac_control; 260df828598SMugunthan V N struct cpsw_slave_data *data; 261df828598SMugunthan V N struct phy_device *phy; 262df828598SMugunthan V N }; 263df828598SMugunthan V N 2649750a3adSRichard Cochran static inline u32 slave_read(struct cpsw_slave *slave, u32 offset) 2659750a3adSRichard Cochran { 2669750a3adSRichard Cochran return __raw_readl(slave->regs + offset); 2679750a3adSRichard Cochran } 2689750a3adSRichard Cochran 2699750a3adSRichard Cochran static inline void slave_write(struct cpsw_slave *slave, u32 val, u32 offset) 2709750a3adSRichard Cochran { 2719750a3adSRichard Cochran __raw_writel(val, slave->regs + offset); 2729750a3adSRichard Cochran } 2739750a3adSRichard Cochran 274df828598SMugunthan V N struct cpsw_priv { 275df828598SMugunthan V N spinlock_t lock; 276df828598SMugunthan V N struct platform_device *pdev; 277df828598SMugunthan V N struct net_device *ndev; 278df828598SMugunthan V N struct resource *cpsw_res; 279df828598SMugunthan V N struct resource *cpsw_ss_res; 280df828598SMugunthan V N struct napi_struct napi; 281df828598SMugunthan V N struct device *dev; 282df828598SMugunthan V N struct cpsw_platform_data data; 283996a5c27SRichard Cochran struct cpsw_ss_regs __iomem *regs; 284996a5c27SRichard Cochran struct cpsw_wr_regs __iomem *wr_regs; 285df828598SMugunthan V N struct cpsw_host_regs __iomem *host_port_regs; 286df828598SMugunthan V N u32 msg_enable; 287e90cfac6SRichard Cochran u32 version; 288df828598SMugunthan V N struct net_device_stats stats; 289df828598SMugunthan V N int rx_packet_max; 290df828598SMugunthan V N int host_port; 291df828598SMugunthan V N struct clk *clk; 292df828598SMugunthan V N u8 mac_addr[ETH_ALEN]; 293df828598SMugunthan V N struct cpsw_slave *slaves; 294df828598SMugunthan V N struct cpdma_ctlr *dma; 295df828598SMugunthan V N struct cpdma_chan *txch, *rxch; 296df828598SMugunthan V N struct cpsw_ale *ale; 297df828598SMugunthan V N /* snapshot of IRQ numbers */ 298df828598SMugunthan V N u32 irqs_table[4]; 299df828598SMugunthan V N u32 num_irqs; 300df828598SMugunthan V N }; 301df828598SMugunthan V N 302df828598SMugunthan V N #define napi_to_priv(napi) container_of(napi, struct cpsw_priv, napi) 303df828598SMugunthan V N #define for_each_slave(priv, func, arg...) \ 304df828598SMugunthan V N do { \ 305df828598SMugunthan V N int idx; \ 306df828598SMugunthan V N for (idx = 0; idx < (priv)->data.slaves; idx++) \ 307df828598SMugunthan V N (func)((priv)->slaves + idx, ##arg); \ 308df828598SMugunthan V N } while (0) 309df828598SMugunthan V N 3105c50a856SMugunthan V N static void cpsw_ndo_set_rx_mode(struct net_device *ndev) 3115c50a856SMugunthan V N { 3125c50a856SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 3135c50a856SMugunthan V N 3145c50a856SMugunthan V N if (ndev->flags & IFF_PROMISC) { 3155c50a856SMugunthan V N /* Enable promiscuous mode */ 3165c50a856SMugunthan V N dev_err(priv->dev, "Ignoring Promiscuous mode\n"); 3175c50a856SMugunthan V N return; 3185c50a856SMugunthan V N } 3195c50a856SMugunthan V N 3205c50a856SMugunthan V N /* Clear all mcast from ALE */ 3215c50a856SMugunthan V N cpsw_ale_flush_multicast(priv->ale, ALE_ALL_PORTS << priv->host_port); 3225c50a856SMugunthan V N 3235c50a856SMugunthan V N if (!netdev_mc_empty(ndev)) { 3245c50a856SMugunthan V N struct netdev_hw_addr *ha; 3255c50a856SMugunthan V N 3265c50a856SMugunthan V N /* program multicast address list into ALE register */ 3275c50a856SMugunthan V N netdev_for_each_mc_addr(ha, ndev) { 3285c50a856SMugunthan V N cpsw_ale_add_mcast(priv->ale, (u8 *)ha->addr, 3295c50a856SMugunthan V N ALE_ALL_PORTS << priv->host_port, 0, 0); 3305c50a856SMugunthan V N } 3315c50a856SMugunthan V N } 3325c50a856SMugunthan V N } 3335c50a856SMugunthan V N 334df828598SMugunthan V N static void cpsw_intr_enable(struct cpsw_priv *priv) 335df828598SMugunthan V N { 336996a5c27SRichard Cochran __raw_writel(0xFF, &priv->wr_regs->tx_en); 337996a5c27SRichard Cochran __raw_writel(0xFF, &priv->wr_regs->rx_en); 338df828598SMugunthan V N 339df828598SMugunthan V N cpdma_ctlr_int_ctrl(priv->dma, true); 340df828598SMugunthan V N return; 341df828598SMugunthan V N } 342df828598SMugunthan V N 343df828598SMugunthan V N static void cpsw_intr_disable(struct cpsw_priv *priv) 344df828598SMugunthan V N { 345996a5c27SRichard Cochran __raw_writel(0, &priv->wr_regs->tx_en); 346996a5c27SRichard Cochran __raw_writel(0, &priv->wr_regs->rx_en); 347df828598SMugunthan V N 348df828598SMugunthan V N cpdma_ctlr_int_ctrl(priv->dma, false); 349df828598SMugunthan V N return; 350df828598SMugunthan V N } 351df828598SMugunthan V N 352df828598SMugunthan V N void cpsw_tx_handler(void *token, int len, int status) 353df828598SMugunthan V N { 354df828598SMugunthan V N struct sk_buff *skb = token; 355df828598SMugunthan V N struct net_device *ndev = skb->dev; 356df828598SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 357df828598SMugunthan V N 358df828598SMugunthan V N if (unlikely(netif_queue_stopped(ndev))) 359df828598SMugunthan V N netif_start_queue(ndev); 360df828598SMugunthan V N priv->stats.tx_packets++; 361df828598SMugunthan V N priv->stats.tx_bytes += len; 362df828598SMugunthan V N dev_kfree_skb_any(skb); 363df828598SMugunthan V N } 364df828598SMugunthan V N 365df828598SMugunthan V N void cpsw_rx_handler(void *token, int len, int status) 366df828598SMugunthan V N { 367df828598SMugunthan V N struct sk_buff *skb = token; 368df828598SMugunthan V N struct net_device *ndev = skb->dev; 369df828598SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 370df828598SMugunthan V N int ret = 0; 371df828598SMugunthan V N 372df828598SMugunthan V N /* free and bail if we are shutting down */ 373df828598SMugunthan V N if (unlikely(!netif_running(ndev)) || 374df828598SMugunthan V N unlikely(!netif_carrier_ok(ndev))) { 375df828598SMugunthan V N dev_kfree_skb_any(skb); 376df828598SMugunthan V N return; 377df828598SMugunthan V N } 378df828598SMugunthan V N if (likely(status >= 0)) { 379df828598SMugunthan V N skb_put(skb, len); 380df828598SMugunthan V N skb->protocol = eth_type_trans(skb, ndev); 381df828598SMugunthan V N netif_receive_skb(skb); 382df828598SMugunthan V N priv->stats.rx_bytes += len; 383df828598SMugunthan V N priv->stats.rx_packets++; 384df828598SMugunthan V N skb = NULL; 385df828598SMugunthan V N } 386df828598SMugunthan V N 387df828598SMugunthan V N if (unlikely(!netif_running(ndev))) { 388df828598SMugunthan V N if (skb) 389df828598SMugunthan V N dev_kfree_skb_any(skb); 390df828598SMugunthan V N return; 391df828598SMugunthan V N } 392df828598SMugunthan V N 393df828598SMugunthan V N if (likely(!skb)) { 394df828598SMugunthan V N skb = netdev_alloc_skb_ip_align(ndev, priv->rx_packet_max); 395df828598SMugunthan V N if (WARN_ON(!skb)) 396df828598SMugunthan V N return; 397df828598SMugunthan V N 398df828598SMugunthan V N ret = cpdma_chan_submit(priv->rxch, skb, skb->data, 399df828598SMugunthan V N skb_tailroom(skb), GFP_KERNEL); 400df828598SMugunthan V N } 401df828598SMugunthan V N WARN_ON(ret < 0); 402df828598SMugunthan V N } 403df828598SMugunthan V N 404df828598SMugunthan V N static irqreturn_t cpsw_interrupt(int irq, void *dev_id) 405df828598SMugunthan V N { 406df828598SMugunthan V N struct cpsw_priv *priv = dev_id; 407df828598SMugunthan V N 408df828598SMugunthan V N if (likely(netif_running(priv->ndev))) { 409df828598SMugunthan V N cpsw_intr_disable(priv); 410df828598SMugunthan V N cpsw_disable_irq(priv); 411df828598SMugunthan V N napi_schedule(&priv->napi); 412df828598SMugunthan V N } 413df828598SMugunthan V N return IRQ_HANDLED; 414df828598SMugunthan V N } 415df828598SMugunthan V N 416df828598SMugunthan V N static inline int cpsw_get_slave_port(struct cpsw_priv *priv, u32 slave_num) 417df828598SMugunthan V N { 418df828598SMugunthan V N if (priv->host_port == 0) 419df828598SMugunthan V N return slave_num + 1; 420df828598SMugunthan V N else 421df828598SMugunthan V N return slave_num; 422df828598SMugunthan V N } 423df828598SMugunthan V N 424df828598SMugunthan V N static int cpsw_poll(struct napi_struct *napi, int budget) 425df828598SMugunthan V N { 426df828598SMugunthan V N struct cpsw_priv *priv = napi_to_priv(napi); 427df828598SMugunthan V N int num_tx, num_rx; 428df828598SMugunthan V N 429df828598SMugunthan V N num_tx = cpdma_chan_process(priv->txch, 128); 430df828598SMugunthan V N num_rx = cpdma_chan_process(priv->rxch, budget); 431df828598SMugunthan V N 432df828598SMugunthan V N if (num_rx || num_tx) 433df828598SMugunthan V N cpsw_dbg(priv, intr, "poll %d rx, %d tx pkts\n", 434df828598SMugunthan V N num_rx, num_tx); 435df828598SMugunthan V N 436df828598SMugunthan V N if (num_rx < budget) { 437df828598SMugunthan V N napi_complete(napi); 438df828598SMugunthan V N cpsw_intr_enable(priv); 439df828598SMugunthan V N cpdma_ctlr_eoi(priv->dma); 440df828598SMugunthan V N cpsw_enable_irq(priv); 441df828598SMugunthan V N } 442df828598SMugunthan V N 443df828598SMugunthan V N return num_rx; 444df828598SMugunthan V N } 445df828598SMugunthan V N 446df828598SMugunthan V N static inline void soft_reset(const char *module, void __iomem *reg) 447df828598SMugunthan V N { 448df828598SMugunthan V N unsigned long timeout = jiffies + HZ; 449df828598SMugunthan V N 450df828598SMugunthan V N __raw_writel(1, reg); 451df828598SMugunthan V N do { 452df828598SMugunthan V N cpu_relax(); 453df828598SMugunthan V N } while ((__raw_readl(reg) & 1) && time_after(timeout, jiffies)); 454df828598SMugunthan V N 455df828598SMugunthan V N WARN(__raw_readl(reg) & 1, "failed to soft-reset %s\n", module); 456df828598SMugunthan V N } 457df828598SMugunthan V N 458df828598SMugunthan V N #define mac_hi(mac) (((mac)[0] << 0) | ((mac)[1] << 8) | \ 459df828598SMugunthan V N ((mac)[2] << 16) | ((mac)[3] << 24)) 460df828598SMugunthan V N #define mac_lo(mac) (((mac)[4] << 0) | ((mac)[5] << 8)) 461df828598SMugunthan V N 462df828598SMugunthan V N static void cpsw_set_slave_mac(struct cpsw_slave *slave, 463df828598SMugunthan V N struct cpsw_priv *priv) 464df828598SMugunthan V N { 4659750a3adSRichard Cochran slave_write(slave, mac_hi(priv->mac_addr), SA_HI); 4669750a3adSRichard Cochran slave_write(slave, mac_lo(priv->mac_addr), SA_LO); 467df828598SMugunthan V N } 468df828598SMugunthan V N 469df828598SMugunthan V N static void _cpsw_adjust_link(struct cpsw_slave *slave, 470df828598SMugunthan V N struct cpsw_priv *priv, bool *link) 471df828598SMugunthan V N { 472df828598SMugunthan V N struct phy_device *phy = slave->phy; 473df828598SMugunthan V N u32 mac_control = 0; 474df828598SMugunthan V N u32 slave_port; 475df828598SMugunthan V N 476df828598SMugunthan V N if (!phy) 477df828598SMugunthan V N return; 478df828598SMugunthan V N 479df828598SMugunthan V N slave_port = cpsw_get_slave_port(priv, slave->slave_num); 480df828598SMugunthan V N 481df828598SMugunthan V N if (phy->link) { 482df828598SMugunthan V N mac_control = priv->data.mac_control; 483df828598SMugunthan V N 484df828598SMugunthan V N /* enable forwarding */ 485df828598SMugunthan V N cpsw_ale_control_set(priv->ale, slave_port, 486df828598SMugunthan V N ALE_PORT_STATE, ALE_PORT_STATE_FORWARD); 487df828598SMugunthan V N 488df828598SMugunthan V N if (phy->speed == 1000) 489df828598SMugunthan V N mac_control |= BIT(7); /* GIGABITEN */ 490df828598SMugunthan V N if (phy->duplex) 491df828598SMugunthan V N mac_control |= BIT(0); /* FULLDUPLEXEN */ 492342b7b74SDaniel Mack 493342b7b74SDaniel Mack /* set speed_in input in case RMII mode is used in 100Mbps */ 494342b7b74SDaniel Mack if (phy->speed == 100) 495342b7b74SDaniel Mack mac_control |= BIT(15); 496342b7b74SDaniel Mack 497df828598SMugunthan V N *link = true; 498df828598SMugunthan V N } else { 499df828598SMugunthan V N mac_control = 0; 500df828598SMugunthan V N /* disable forwarding */ 501df828598SMugunthan V N cpsw_ale_control_set(priv->ale, slave_port, 502df828598SMugunthan V N ALE_PORT_STATE, ALE_PORT_STATE_DISABLE); 503df828598SMugunthan V N } 504df828598SMugunthan V N 505df828598SMugunthan V N if (mac_control != slave->mac_control) { 506df828598SMugunthan V N phy_print_status(phy); 507df828598SMugunthan V N __raw_writel(mac_control, &slave->sliver->mac_control); 508df828598SMugunthan V N } 509df828598SMugunthan V N 510df828598SMugunthan V N slave->mac_control = mac_control; 511df828598SMugunthan V N } 512df828598SMugunthan V N 513df828598SMugunthan V N static void cpsw_adjust_link(struct net_device *ndev) 514df828598SMugunthan V N { 515df828598SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 516df828598SMugunthan V N bool link = false; 517df828598SMugunthan V N 518df828598SMugunthan V N for_each_slave(priv, _cpsw_adjust_link, priv, &link); 519df828598SMugunthan V N 520df828598SMugunthan V N if (link) { 521df828598SMugunthan V N netif_carrier_on(ndev); 522df828598SMugunthan V N if (netif_running(ndev)) 523df828598SMugunthan V N netif_wake_queue(ndev); 524df828598SMugunthan V N } else { 525df828598SMugunthan V N netif_carrier_off(ndev); 526df828598SMugunthan V N netif_stop_queue(ndev); 527df828598SMugunthan V N } 528df828598SMugunthan V N } 529df828598SMugunthan V N 530df828598SMugunthan V N static inline int __show_stat(char *buf, int maxlen, const char *name, u32 val) 531df828598SMugunthan V N { 532df828598SMugunthan V N static char *leader = "........................................"; 533df828598SMugunthan V N 534df828598SMugunthan V N if (!val) 535df828598SMugunthan V N return 0; 536df828598SMugunthan V N else 537df828598SMugunthan V N return snprintf(buf, maxlen, "%s %s %10d\n", name, 538df828598SMugunthan V N leader + strlen(name), val); 539df828598SMugunthan V N } 540df828598SMugunthan V N 541df828598SMugunthan V N static void cpsw_slave_open(struct cpsw_slave *slave, struct cpsw_priv *priv) 542df828598SMugunthan V N { 543df828598SMugunthan V N char name[32]; 544df828598SMugunthan V N u32 slave_port; 545df828598SMugunthan V N 546df828598SMugunthan V N sprintf(name, "slave-%d", slave->slave_num); 547df828598SMugunthan V N 548df828598SMugunthan V N soft_reset(name, &slave->sliver->soft_reset); 549df828598SMugunthan V N 550df828598SMugunthan V N /* setup priority mapping */ 551df828598SMugunthan V N __raw_writel(RX_PRIORITY_MAPPING, &slave->sliver->rx_pri_map); 5529750a3adSRichard Cochran 5539750a3adSRichard Cochran switch (priv->version) { 5549750a3adSRichard Cochran case CPSW_VERSION_1: 5559750a3adSRichard Cochran slave_write(slave, TX_PRIORITY_MAPPING, CPSW1_TX_PRI_MAP); 5569750a3adSRichard Cochran break; 5579750a3adSRichard Cochran case CPSW_VERSION_2: 5589750a3adSRichard Cochran slave_write(slave, TX_PRIORITY_MAPPING, CPSW2_TX_PRI_MAP); 5599750a3adSRichard Cochran break; 5609750a3adSRichard Cochran } 561df828598SMugunthan V N 562df828598SMugunthan V N /* setup max packet size, and mac address */ 563df828598SMugunthan V N __raw_writel(priv->rx_packet_max, &slave->sliver->rx_maxlen); 564df828598SMugunthan V N cpsw_set_slave_mac(slave, priv); 565df828598SMugunthan V N 566df828598SMugunthan V N slave->mac_control = 0; /* no link yet */ 567df828598SMugunthan V N 568df828598SMugunthan V N slave_port = cpsw_get_slave_port(priv, slave->slave_num); 569df828598SMugunthan V N 570df828598SMugunthan V N cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast, 571df828598SMugunthan V N 1 << slave_port, 0, ALE_MCAST_FWD_2); 572df828598SMugunthan V N 573df828598SMugunthan V N slave->phy = phy_connect(priv->ndev, slave->data->phy_id, 574df828598SMugunthan V N &cpsw_adjust_link, 0, slave->data->phy_if); 575df828598SMugunthan V N if (IS_ERR(slave->phy)) { 576df828598SMugunthan V N dev_err(priv->dev, "phy %s not found on slave %d\n", 577df828598SMugunthan V N slave->data->phy_id, slave->slave_num); 578df828598SMugunthan V N slave->phy = NULL; 579df828598SMugunthan V N } else { 580df828598SMugunthan V N dev_info(priv->dev, "phy found : id is : 0x%x\n", 581df828598SMugunthan V N slave->phy->phy_id); 582df828598SMugunthan V N phy_start(slave->phy); 583df828598SMugunthan V N } 584df828598SMugunthan V N } 585df828598SMugunthan V N 586df828598SMugunthan V N static void cpsw_init_host_port(struct cpsw_priv *priv) 587df828598SMugunthan V N { 588df828598SMugunthan V N /* soft reset the controller and initialize ale */ 589df828598SMugunthan V N soft_reset("cpsw", &priv->regs->soft_reset); 590df828598SMugunthan V N cpsw_ale_start(priv->ale); 591df828598SMugunthan V N 592df828598SMugunthan V N /* switch to vlan unaware mode */ 593df828598SMugunthan V N cpsw_ale_control_set(priv->ale, 0, ALE_VLAN_AWARE, 0); 594df828598SMugunthan V N 595df828598SMugunthan V N /* setup host port priority mapping */ 596df828598SMugunthan V N __raw_writel(CPDMA_TX_PRIORITY_MAP, 597df828598SMugunthan V N &priv->host_port_regs->cpdma_tx_pri_map); 598df828598SMugunthan V N __raw_writel(0, &priv->host_port_regs->cpdma_rx_chan_map); 599df828598SMugunthan V N 600df828598SMugunthan V N cpsw_ale_control_set(priv->ale, priv->host_port, 601df828598SMugunthan V N ALE_PORT_STATE, ALE_PORT_STATE_FORWARD); 602df828598SMugunthan V N 603df828598SMugunthan V N cpsw_ale_add_ucast(priv->ale, priv->mac_addr, priv->host_port, 0); 604df828598SMugunthan V N cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast, 605df828598SMugunthan V N 1 << priv->host_port, 0, ALE_MCAST_FWD_2); 606df828598SMugunthan V N } 607df828598SMugunthan V N 608df828598SMugunthan V N static int cpsw_ndo_open(struct net_device *ndev) 609df828598SMugunthan V N { 610df828598SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 611df828598SMugunthan V N int i, ret; 612df828598SMugunthan V N u32 reg; 613df828598SMugunthan V N 614df828598SMugunthan V N cpsw_intr_disable(priv); 615df828598SMugunthan V N netif_carrier_off(ndev); 616df828598SMugunthan V N 617f150bd7fSMugunthan V N pm_runtime_get_sync(&priv->pdev->dev); 618df828598SMugunthan V N 619df828598SMugunthan V N reg = __raw_readl(&priv->regs->id_ver); 620e90cfac6SRichard Cochran priv->version = reg; 621df828598SMugunthan V N 622df828598SMugunthan V N dev_info(priv->dev, "initializing cpsw version %d.%d (%d)\n", 623df828598SMugunthan V N CPSW_MAJOR_VERSION(reg), CPSW_MINOR_VERSION(reg), 624df828598SMugunthan V N CPSW_RTL_VERSION(reg)); 625df828598SMugunthan V N 626df828598SMugunthan V N /* initialize host and slave ports */ 627df828598SMugunthan V N cpsw_init_host_port(priv); 628df828598SMugunthan V N for_each_slave(priv, cpsw_slave_open, priv); 629df828598SMugunthan V N 630df828598SMugunthan V N /* setup tx dma to fixed prio and zero offset */ 631df828598SMugunthan V N cpdma_control_set(priv->dma, CPDMA_TX_PRIO_FIXED, 1); 632df828598SMugunthan V N cpdma_control_set(priv->dma, CPDMA_RX_BUFFER_OFFSET, 0); 633df828598SMugunthan V N 634df828598SMugunthan V N /* disable priority elevation and enable statistics on all ports */ 635df828598SMugunthan V N __raw_writel(0, &priv->regs->ptype); 636df828598SMugunthan V N 637df828598SMugunthan V N /* enable statistics collection only on the host port */ 638df828598SMugunthan V N __raw_writel(0x7, &priv->regs->stat_port_en); 639df828598SMugunthan V N 640df828598SMugunthan V N if (WARN_ON(!priv->data.rx_descs)) 641df828598SMugunthan V N priv->data.rx_descs = 128; 642df828598SMugunthan V N 643df828598SMugunthan V N for (i = 0; i < priv->data.rx_descs; i++) { 644df828598SMugunthan V N struct sk_buff *skb; 645df828598SMugunthan V N 646df828598SMugunthan V N ret = -ENOMEM; 647df828598SMugunthan V N skb = netdev_alloc_skb_ip_align(priv->ndev, 648df828598SMugunthan V N priv->rx_packet_max); 649df828598SMugunthan V N if (!skb) 650df828598SMugunthan V N break; 651df828598SMugunthan V N ret = cpdma_chan_submit(priv->rxch, skb, skb->data, 652df828598SMugunthan V N skb_tailroom(skb), GFP_KERNEL); 653df828598SMugunthan V N if (WARN_ON(ret < 0)) 654df828598SMugunthan V N break; 655df828598SMugunthan V N } 656df828598SMugunthan V N /* continue even if we didn't manage to submit all receive descs */ 657df828598SMugunthan V N cpsw_info(priv, ifup, "submitted %d rx descriptors\n", i); 658df828598SMugunthan V N 659df828598SMugunthan V N cpdma_ctlr_start(priv->dma); 660df828598SMugunthan V N cpsw_intr_enable(priv); 661df828598SMugunthan V N napi_enable(&priv->napi); 662df828598SMugunthan V N cpdma_ctlr_eoi(priv->dma); 663df828598SMugunthan V N 664df828598SMugunthan V N return 0; 665df828598SMugunthan V N } 666df828598SMugunthan V N 667df828598SMugunthan V N static void cpsw_slave_stop(struct cpsw_slave *slave, struct cpsw_priv *priv) 668df828598SMugunthan V N { 669df828598SMugunthan V N if (!slave->phy) 670df828598SMugunthan V N return; 671df828598SMugunthan V N phy_stop(slave->phy); 672df828598SMugunthan V N phy_disconnect(slave->phy); 673df828598SMugunthan V N slave->phy = NULL; 674df828598SMugunthan V N } 675df828598SMugunthan V N 676df828598SMugunthan V N static int cpsw_ndo_stop(struct net_device *ndev) 677df828598SMugunthan V N { 678df828598SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 679df828598SMugunthan V N 680df828598SMugunthan V N cpsw_info(priv, ifdown, "shutting down cpsw device\n"); 681df828598SMugunthan V N cpsw_intr_disable(priv); 682df828598SMugunthan V N cpdma_ctlr_int_ctrl(priv->dma, false); 683df828598SMugunthan V N cpdma_ctlr_stop(priv->dma); 684df828598SMugunthan V N netif_stop_queue(priv->ndev); 685df828598SMugunthan V N napi_disable(&priv->napi); 686df828598SMugunthan V N netif_carrier_off(priv->ndev); 687df828598SMugunthan V N cpsw_ale_stop(priv->ale); 688df828598SMugunthan V N for_each_slave(priv, cpsw_slave_stop, priv); 689f150bd7fSMugunthan V N pm_runtime_put_sync(&priv->pdev->dev); 690df828598SMugunthan V N return 0; 691df828598SMugunthan V N } 692df828598SMugunthan V N 693df828598SMugunthan V N static netdev_tx_t cpsw_ndo_start_xmit(struct sk_buff *skb, 694df828598SMugunthan V N struct net_device *ndev) 695df828598SMugunthan V N { 696df828598SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 697df828598SMugunthan V N int ret; 698df828598SMugunthan V N 699df828598SMugunthan V N ndev->trans_start = jiffies; 700df828598SMugunthan V N 701df828598SMugunthan V N if (skb_padto(skb, CPSW_MIN_PACKET_SIZE)) { 702df828598SMugunthan V N cpsw_err(priv, tx_err, "packet pad failed\n"); 703df828598SMugunthan V N priv->stats.tx_dropped++; 704df828598SMugunthan V N return NETDEV_TX_OK; 705df828598SMugunthan V N } 706df828598SMugunthan V N 707df828598SMugunthan V N ret = cpdma_chan_submit(priv->txch, skb, skb->data, 708df828598SMugunthan V N skb->len, GFP_KERNEL); 709df828598SMugunthan V N if (unlikely(ret != 0)) { 710df828598SMugunthan V N cpsw_err(priv, tx_err, "desc submit failed\n"); 711df828598SMugunthan V N goto fail; 712df828598SMugunthan V N } 713df828598SMugunthan V N 714df828598SMugunthan V N return NETDEV_TX_OK; 715df828598SMugunthan V N fail: 716df828598SMugunthan V N priv->stats.tx_dropped++; 717df828598SMugunthan V N netif_stop_queue(ndev); 718df828598SMugunthan V N return NETDEV_TX_BUSY; 719df828598SMugunthan V N } 720df828598SMugunthan V N 721df828598SMugunthan V N static void cpsw_ndo_change_rx_flags(struct net_device *ndev, int flags) 722df828598SMugunthan V N { 723df828598SMugunthan V N /* 724df828598SMugunthan V N * The switch cannot operate in promiscuous mode without substantial 725df828598SMugunthan V N * headache. For promiscuous mode to work, we would need to put the 726df828598SMugunthan V N * ALE in bypass mode and route all traffic to the host port. 727df828598SMugunthan V N * Subsequently, the host will need to operate as a "bridge", learn, 728df828598SMugunthan V N * and flood as needed. For now, we simply complain here and 729df828598SMugunthan V N * do nothing about it :-) 730df828598SMugunthan V N */ 731df828598SMugunthan V N if ((flags & IFF_PROMISC) && (ndev->flags & IFF_PROMISC)) 732df828598SMugunthan V N dev_err(&ndev->dev, "promiscuity ignored!\n"); 733df828598SMugunthan V N 734df828598SMugunthan V N /* 735df828598SMugunthan V N * The switch cannot filter multicast traffic unless it is configured 736df828598SMugunthan V N * in "VLAN Aware" mode. Unfortunately, VLAN awareness requires a 737df828598SMugunthan V N * whole bunch of additional logic that this driver does not implement 738df828598SMugunthan V N * at present. 739df828598SMugunthan V N */ 740df828598SMugunthan V N if ((flags & IFF_ALLMULTI) && !(ndev->flags & IFF_ALLMULTI)) 741df828598SMugunthan V N dev_err(&ndev->dev, "multicast traffic cannot be filtered!\n"); 742df828598SMugunthan V N } 743df828598SMugunthan V N 744df828598SMugunthan V N static void cpsw_ndo_tx_timeout(struct net_device *ndev) 745df828598SMugunthan V N { 746df828598SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 747df828598SMugunthan V N 748df828598SMugunthan V N cpsw_err(priv, tx_err, "transmit timeout, restarting dma\n"); 749df828598SMugunthan V N priv->stats.tx_errors++; 750df828598SMugunthan V N cpsw_intr_disable(priv); 751df828598SMugunthan V N cpdma_ctlr_int_ctrl(priv->dma, false); 752df828598SMugunthan V N cpdma_chan_stop(priv->txch); 753df828598SMugunthan V N cpdma_chan_start(priv->txch); 754df828598SMugunthan V N cpdma_ctlr_int_ctrl(priv->dma, true); 755df828598SMugunthan V N cpsw_intr_enable(priv); 756df828598SMugunthan V N cpdma_ctlr_eoi(priv->dma); 757df828598SMugunthan V N } 758df828598SMugunthan V N 759df828598SMugunthan V N static struct net_device_stats *cpsw_ndo_get_stats(struct net_device *ndev) 760df828598SMugunthan V N { 761df828598SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 762df828598SMugunthan V N return &priv->stats; 763df828598SMugunthan V N } 764df828598SMugunthan V N 765df828598SMugunthan V N #ifdef CONFIG_NET_POLL_CONTROLLER 766df828598SMugunthan V N static void cpsw_ndo_poll_controller(struct net_device *ndev) 767df828598SMugunthan V N { 768df828598SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 769df828598SMugunthan V N 770df828598SMugunthan V N cpsw_intr_disable(priv); 771df828598SMugunthan V N cpdma_ctlr_int_ctrl(priv->dma, false); 772df828598SMugunthan V N cpsw_interrupt(ndev->irq, priv); 773df828598SMugunthan V N cpdma_ctlr_int_ctrl(priv->dma, true); 774df828598SMugunthan V N cpsw_intr_enable(priv); 775df828598SMugunthan V N cpdma_ctlr_eoi(priv->dma); 776df828598SMugunthan V N } 777df828598SMugunthan V N #endif 778df828598SMugunthan V N 779df828598SMugunthan V N static const struct net_device_ops cpsw_netdev_ops = { 780df828598SMugunthan V N .ndo_open = cpsw_ndo_open, 781df828598SMugunthan V N .ndo_stop = cpsw_ndo_stop, 782df828598SMugunthan V N .ndo_start_xmit = cpsw_ndo_start_xmit, 783df828598SMugunthan V N .ndo_change_rx_flags = cpsw_ndo_change_rx_flags, 784df828598SMugunthan V N .ndo_validate_addr = eth_validate_addr, 7855c473ed2SDavid S. Miller .ndo_change_mtu = eth_change_mtu, 786df828598SMugunthan V N .ndo_tx_timeout = cpsw_ndo_tx_timeout, 787df828598SMugunthan V N .ndo_get_stats = cpsw_ndo_get_stats, 7885c50a856SMugunthan V N .ndo_set_rx_mode = cpsw_ndo_set_rx_mode, 789df828598SMugunthan V N #ifdef CONFIG_NET_POLL_CONTROLLER 790df828598SMugunthan V N .ndo_poll_controller = cpsw_ndo_poll_controller, 791df828598SMugunthan V N #endif 792df828598SMugunthan V N }; 793df828598SMugunthan V N 794df828598SMugunthan V N static void cpsw_get_drvinfo(struct net_device *ndev, 795df828598SMugunthan V N struct ethtool_drvinfo *info) 796df828598SMugunthan V N { 797df828598SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 798df828598SMugunthan V N strcpy(info->driver, "TI CPSW Driver v1.0"); 799df828598SMugunthan V N strcpy(info->version, "1.0"); 800df828598SMugunthan V N strcpy(info->bus_info, priv->pdev->name); 801df828598SMugunthan V N } 802df828598SMugunthan V N 803df828598SMugunthan V N static u32 cpsw_get_msglevel(struct net_device *ndev) 804df828598SMugunthan V N { 805df828598SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 806df828598SMugunthan V N return priv->msg_enable; 807df828598SMugunthan V N } 808df828598SMugunthan V N 809df828598SMugunthan V N static void cpsw_set_msglevel(struct net_device *ndev, u32 value) 810df828598SMugunthan V N { 811df828598SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 812df828598SMugunthan V N priv->msg_enable = value; 813df828598SMugunthan V N } 814df828598SMugunthan V N 815df828598SMugunthan V N static const struct ethtool_ops cpsw_ethtool_ops = { 816df828598SMugunthan V N .get_drvinfo = cpsw_get_drvinfo, 817df828598SMugunthan V N .get_msglevel = cpsw_get_msglevel, 818df828598SMugunthan V N .set_msglevel = cpsw_set_msglevel, 819df828598SMugunthan V N .get_link = ethtool_op_get_link, 820df828598SMugunthan V N }; 821df828598SMugunthan V N 822df828598SMugunthan V N static void cpsw_slave_init(struct cpsw_slave *slave, struct cpsw_priv *priv) 823df828598SMugunthan V N { 824df828598SMugunthan V N void __iomem *regs = priv->regs; 825df828598SMugunthan V N int slave_num = slave->slave_num; 826df828598SMugunthan V N struct cpsw_slave_data *data = priv->data.slave_data + slave_num; 827df828598SMugunthan V N 828df828598SMugunthan V N slave->data = data; 829df828598SMugunthan V N slave->regs = regs + data->slave_reg_ofs; 830df828598SMugunthan V N slave->sliver = regs + data->sliver_reg_ofs; 831df828598SMugunthan V N } 832df828598SMugunthan V N 8332eb32b0aSMugunthan V N static int cpsw_probe_dt(struct cpsw_platform_data *data, 8342eb32b0aSMugunthan V N struct platform_device *pdev) 8352eb32b0aSMugunthan V N { 8362eb32b0aSMugunthan V N struct device_node *node = pdev->dev.of_node; 8372eb32b0aSMugunthan V N struct device_node *slave_node; 8382eb32b0aSMugunthan V N int i = 0, ret; 8392eb32b0aSMugunthan V N u32 prop; 8402eb32b0aSMugunthan V N 8412eb32b0aSMugunthan V N if (!node) 8422eb32b0aSMugunthan V N return -EINVAL; 8432eb32b0aSMugunthan V N 8442eb32b0aSMugunthan V N if (of_property_read_u32(node, "slaves", &prop)) { 8452eb32b0aSMugunthan V N pr_err("Missing slaves property in the DT.\n"); 8462eb32b0aSMugunthan V N return -EINVAL; 8472eb32b0aSMugunthan V N } 8482eb32b0aSMugunthan V N data->slaves = prop; 8492eb32b0aSMugunthan V N 8502eb32b0aSMugunthan V N data->slave_data = kzalloc(sizeof(struct cpsw_slave_data) * 8512eb32b0aSMugunthan V N data->slaves, GFP_KERNEL); 8522eb32b0aSMugunthan V N if (!data->slave_data) { 8532eb32b0aSMugunthan V N pr_err("Could not allocate slave memory.\n"); 8542eb32b0aSMugunthan V N return -EINVAL; 8552eb32b0aSMugunthan V N } 8562eb32b0aSMugunthan V N 8572eb32b0aSMugunthan V N data->no_bd_ram = of_property_read_bool(node, "no_bd_ram"); 8582eb32b0aSMugunthan V N 8592eb32b0aSMugunthan V N if (of_property_read_u32(node, "cpdma_channels", &prop)) { 8602eb32b0aSMugunthan V N pr_err("Missing cpdma_channels property in the DT.\n"); 8612eb32b0aSMugunthan V N ret = -EINVAL; 8622eb32b0aSMugunthan V N goto error_ret; 8632eb32b0aSMugunthan V N } 8642eb32b0aSMugunthan V N data->channels = prop; 8652eb32b0aSMugunthan V N 8662eb32b0aSMugunthan V N if (of_property_read_u32(node, "host_port_no", &prop)) { 8672eb32b0aSMugunthan V N pr_err("Missing host_port_no property in the DT.\n"); 8682eb32b0aSMugunthan V N ret = -EINVAL; 8692eb32b0aSMugunthan V N goto error_ret; 8702eb32b0aSMugunthan V N } 8712eb32b0aSMugunthan V N data->host_port_num = prop; 8722eb32b0aSMugunthan V N 8732eb32b0aSMugunthan V N if (of_property_read_u32(node, "cpdma_reg_ofs", &prop)) { 8742eb32b0aSMugunthan V N pr_err("Missing cpdma_reg_ofs property in the DT.\n"); 8752eb32b0aSMugunthan V N ret = -EINVAL; 8762eb32b0aSMugunthan V N goto error_ret; 8772eb32b0aSMugunthan V N } 8782eb32b0aSMugunthan V N data->cpdma_reg_ofs = prop; 8792eb32b0aSMugunthan V N 8802eb32b0aSMugunthan V N if (of_property_read_u32(node, "cpdma_sram_ofs", &prop)) { 8812eb32b0aSMugunthan V N pr_err("Missing cpdma_sram_ofs property in the DT.\n"); 8822eb32b0aSMugunthan V N ret = -EINVAL; 8832eb32b0aSMugunthan V N goto error_ret; 8842eb32b0aSMugunthan V N } 8852eb32b0aSMugunthan V N data->cpdma_sram_ofs = prop; 8862eb32b0aSMugunthan V N 8872eb32b0aSMugunthan V N if (of_property_read_u32(node, "ale_reg_ofs", &prop)) { 8882eb32b0aSMugunthan V N pr_err("Missing ale_reg_ofs property in the DT.\n"); 8892eb32b0aSMugunthan V N ret = -EINVAL; 8902eb32b0aSMugunthan V N goto error_ret; 8912eb32b0aSMugunthan V N } 8922eb32b0aSMugunthan V N data->ale_reg_ofs = prop; 8932eb32b0aSMugunthan V N 8942eb32b0aSMugunthan V N if (of_property_read_u32(node, "ale_entries", &prop)) { 8952eb32b0aSMugunthan V N pr_err("Missing ale_entries property in the DT.\n"); 8962eb32b0aSMugunthan V N ret = -EINVAL; 8972eb32b0aSMugunthan V N goto error_ret; 8982eb32b0aSMugunthan V N } 8992eb32b0aSMugunthan V N data->ale_entries = prop; 9002eb32b0aSMugunthan V N 9012eb32b0aSMugunthan V N if (of_property_read_u32(node, "host_port_reg_ofs", &prop)) { 9022eb32b0aSMugunthan V N pr_err("Missing host_port_reg_ofs property in the DT.\n"); 9032eb32b0aSMugunthan V N ret = -EINVAL; 9042eb32b0aSMugunthan V N goto error_ret; 9052eb32b0aSMugunthan V N } 9062eb32b0aSMugunthan V N data->host_port_reg_ofs = prop; 9072eb32b0aSMugunthan V N 9082eb32b0aSMugunthan V N if (of_property_read_u32(node, "hw_stats_reg_ofs", &prop)) { 9092eb32b0aSMugunthan V N pr_err("Missing hw_stats_reg_ofs property in the DT.\n"); 9102eb32b0aSMugunthan V N ret = -EINVAL; 9112eb32b0aSMugunthan V N goto error_ret; 9122eb32b0aSMugunthan V N } 9132eb32b0aSMugunthan V N data->hw_stats_reg_ofs = prop; 9142eb32b0aSMugunthan V N 9156b60393eSRichard Cochran if (of_property_read_u32(node, "cpts_reg_ofs", &prop)) { 9166b60393eSRichard Cochran pr_err("Missing cpts_reg_ofs property in the DT.\n"); 9176b60393eSRichard Cochran ret = -EINVAL; 9186b60393eSRichard Cochran goto error_ret; 9196b60393eSRichard Cochran } 9206b60393eSRichard Cochran data->cpts_reg_ofs = prop; 9216b60393eSRichard Cochran 9222eb32b0aSMugunthan V N if (of_property_read_u32(node, "bd_ram_ofs", &prop)) { 9232eb32b0aSMugunthan V N pr_err("Missing bd_ram_ofs property in the DT.\n"); 9242eb32b0aSMugunthan V N ret = -EINVAL; 9252eb32b0aSMugunthan V N goto error_ret; 9262eb32b0aSMugunthan V N } 9272eb32b0aSMugunthan V N data->bd_ram_ofs = prop; 9282eb32b0aSMugunthan V N 9292eb32b0aSMugunthan V N if (of_property_read_u32(node, "bd_ram_size", &prop)) { 9302eb32b0aSMugunthan V N pr_err("Missing bd_ram_size property in the DT.\n"); 9312eb32b0aSMugunthan V N ret = -EINVAL; 9322eb32b0aSMugunthan V N goto error_ret; 9332eb32b0aSMugunthan V N } 9342eb32b0aSMugunthan V N data->bd_ram_size = prop; 9352eb32b0aSMugunthan V N 9362eb32b0aSMugunthan V N if (of_property_read_u32(node, "rx_descs", &prop)) { 9372eb32b0aSMugunthan V N pr_err("Missing rx_descs property in the DT.\n"); 9382eb32b0aSMugunthan V N ret = -EINVAL; 9392eb32b0aSMugunthan V N goto error_ret; 9402eb32b0aSMugunthan V N } 9412eb32b0aSMugunthan V N data->rx_descs = prop; 9422eb32b0aSMugunthan V N 9432eb32b0aSMugunthan V N if (of_property_read_u32(node, "mac_control", &prop)) { 9442eb32b0aSMugunthan V N pr_err("Missing mac_control property in the DT.\n"); 9452eb32b0aSMugunthan V N ret = -EINVAL; 9462eb32b0aSMugunthan V N goto error_ret; 9472eb32b0aSMugunthan V N } 9482eb32b0aSMugunthan V N data->mac_control = prop; 9492eb32b0aSMugunthan V N 9502eb32b0aSMugunthan V N for_each_child_of_node(node, slave_node) { 9512eb32b0aSMugunthan V N struct cpsw_slave_data *slave_data = data->slave_data + i; 9522eb32b0aSMugunthan V N const char *phy_id = NULL; 9532eb32b0aSMugunthan V N const void *mac_addr = NULL; 9542eb32b0aSMugunthan V N 9552eb32b0aSMugunthan V N if (of_property_read_string(slave_node, "phy_id", &phy_id)) { 9562eb32b0aSMugunthan V N pr_err("Missing slave[%d] phy_id property\n", i); 9572eb32b0aSMugunthan V N ret = -EINVAL; 9582eb32b0aSMugunthan V N goto error_ret; 9592eb32b0aSMugunthan V N } 9602eb32b0aSMugunthan V N slave_data->phy_id = phy_id; 9612eb32b0aSMugunthan V N 9622eb32b0aSMugunthan V N if (of_property_read_u32(slave_node, "slave_reg_ofs", &prop)) { 9632eb32b0aSMugunthan V N pr_err("Missing slave[%d] slave_reg_ofs property\n", i); 9642eb32b0aSMugunthan V N ret = -EINVAL; 9652eb32b0aSMugunthan V N goto error_ret; 9662eb32b0aSMugunthan V N } 9672eb32b0aSMugunthan V N slave_data->slave_reg_ofs = prop; 9682eb32b0aSMugunthan V N 9692eb32b0aSMugunthan V N if (of_property_read_u32(slave_node, "sliver_reg_ofs", 9702eb32b0aSMugunthan V N &prop)) { 9712eb32b0aSMugunthan V N pr_err("Missing slave[%d] sliver_reg_ofs property\n", 9722eb32b0aSMugunthan V N i); 9732eb32b0aSMugunthan V N ret = -EINVAL; 9742eb32b0aSMugunthan V N goto error_ret; 9752eb32b0aSMugunthan V N } 9762eb32b0aSMugunthan V N slave_data->sliver_reg_ofs = prop; 9772eb32b0aSMugunthan V N 9782eb32b0aSMugunthan V N mac_addr = of_get_mac_address(slave_node); 9792eb32b0aSMugunthan V N if (mac_addr) 9802eb32b0aSMugunthan V N memcpy(slave_data->mac_addr, mac_addr, ETH_ALEN); 9812eb32b0aSMugunthan V N 9822eb32b0aSMugunthan V N i++; 9832eb32b0aSMugunthan V N } 9842eb32b0aSMugunthan V N 9852eb32b0aSMugunthan V N return 0; 9862eb32b0aSMugunthan V N 9872eb32b0aSMugunthan V N error_ret: 9882eb32b0aSMugunthan V N kfree(data->slave_data); 9892eb32b0aSMugunthan V N return ret; 9902eb32b0aSMugunthan V N } 9912eb32b0aSMugunthan V N 992df828598SMugunthan V N static int __devinit cpsw_probe(struct platform_device *pdev) 993df828598SMugunthan V N { 994df828598SMugunthan V N struct cpsw_platform_data *data = pdev->dev.platform_data; 995df828598SMugunthan V N struct net_device *ndev; 996df828598SMugunthan V N struct cpsw_priv *priv; 997df828598SMugunthan V N struct cpdma_params dma_params; 998df828598SMugunthan V N struct cpsw_ale_params ale_params; 999df828598SMugunthan V N void __iomem *regs; 1000df828598SMugunthan V N struct resource *res; 1001df828598SMugunthan V N int ret = 0, i, k = 0; 1002df828598SMugunthan V N 1003df828598SMugunthan V N ndev = alloc_etherdev(sizeof(struct cpsw_priv)); 1004df828598SMugunthan V N if (!ndev) { 1005df828598SMugunthan V N pr_err("error allocating net_device\n"); 1006df828598SMugunthan V N return -ENOMEM; 1007df828598SMugunthan V N } 1008df828598SMugunthan V N 1009df828598SMugunthan V N platform_set_drvdata(pdev, ndev); 1010df828598SMugunthan V N priv = netdev_priv(ndev); 1011df828598SMugunthan V N spin_lock_init(&priv->lock); 1012df828598SMugunthan V N priv->pdev = pdev; 1013df828598SMugunthan V N priv->ndev = ndev; 1014df828598SMugunthan V N priv->dev = &ndev->dev; 1015df828598SMugunthan V N priv->msg_enable = netif_msg_init(debug_level, CPSW_DEBUG); 1016df828598SMugunthan V N priv->rx_packet_max = max(rx_packet_max, 128); 1017df828598SMugunthan V N 10182eb32b0aSMugunthan V N if (cpsw_probe_dt(&priv->data, pdev)) { 10192eb32b0aSMugunthan V N pr_err("cpsw: platform data missing\n"); 10202eb32b0aSMugunthan V N ret = -ENODEV; 10212eb32b0aSMugunthan V N goto clean_ndev_ret; 10222eb32b0aSMugunthan V N } 10232eb32b0aSMugunthan V N data = &priv->data; 10242eb32b0aSMugunthan V N 1025df828598SMugunthan V N if (is_valid_ether_addr(data->slave_data[0].mac_addr)) { 1026df828598SMugunthan V N memcpy(priv->mac_addr, data->slave_data[0].mac_addr, ETH_ALEN); 1027df828598SMugunthan V N pr_info("Detected MACID = %pM", priv->mac_addr); 1028df828598SMugunthan V N } else { 10297efd26d0SJoe Perches eth_random_addr(priv->mac_addr); 1030df828598SMugunthan V N pr_info("Random MACID = %pM", priv->mac_addr); 1031df828598SMugunthan V N } 1032df828598SMugunthan V N 1033df828598SMugunthan V N memcpy(ndev->dev_addr, priv->mac_addr, ETH_ALEN); 1034df828598SMugunthan V N 1035df828598SMugunthan V N priv->slaves = kzalloc(sizeof(struct cpsw_slave) * data->slaves, 1036df828598SMugunthan V N GFP_KERNEL); 1037df828598SMugunthan V N if (!priv->slaves) { 1038df828598SMugunthan V N ret = -EBUSY; 1039df828598SMugunthan V N goto clean_ndev_ret; 1040df828598SMugunthan V N } 1041df828598SMugunthan V N for (i = 0; i < data->slaves; i++) 1042df828598SMugunthan V N priv->slaves[i].slave_num = i; 1043df828598SMugunthan V N 1044f150bd7fSMugunthan V N pm_runtime_enable(&pdev->dev); 1045f150bd7fSMugunthan V N priv->clk = clk_get(&pdev->dev, "fck"); 1046df828598SMugunthan V N if (IS_ERR(priv->clk)) { 1047f150bd7fSMugunthan V N dev_err(&pdev->dev, "fck is not found\n"); 1048f150bd7fSMugunthan V N ret = -ENODEV; 1049f150bd7fSMugunthan V N goto clean_slave_ret; 1050df828598SMugunthan V N } 1051df828598SMugunthan V N 1052df828598SMugunthan V N priv->cpsw_res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1053df828598SMugunthan V N if (!priv->cpsw_res) { 1054df828598SMugunthan V N dev_err(priv->dev, "error getting i/o resource\n"); 1055df828598SMugunthan V N ret = -ENOENT; 1056df828598SMugunthan V N goto clean_clk_ret; 1057df828598SMugunthan V N } 1058df828598SMugunthan V N 1059df828598SMugunthan V N if (!request_mem_region(priv->cpsw_res->start, 1060df828598SMugunthan V N resource_size(priv->cpsw_res), ndev->name)) { 1061df828598SMugunthan V N dev_err(priv->dev, "failed request i/o region\n"); 1062df828598SMugunthan V N ret = -ENXIO; 1063df828598SMugunthan V N goto clean_clk_ret; 1064df828598SMugunthan V N } 1065df828598SMugunthan V N 1066df828598SMugunthan V N regs = ioremap(priv->cpsw_res->start, resource_size(priv->cpsw_res)); 1067df828598SMugunthan V N if (!regs) { 1068df828598SMugunthan V N dev_err(priv->dev, "unable to map i/o region\n"); 1069df828598SMugunthan V N goto clean_cpsw_iores_ret; 1070df828598SMugunthan V N } 1071df828598SMugunthan V N priv->regs = regs; 1072df828598SMugunthan V N priv->host_port = data->host_port_num; 1073df828598SMugunthan V N priv->host_port_regs = regs + data->host_port_reg_ofs; 1074df828598SMugunthan V N 1075df828598SMugunthan V N priv->cpsw_ss_res = platform_get_resource(pdev, IORESOURCE_MEM, 1); 1076df828598SMugunthan V N if (!priv->cpsw_ss_res) { 1077df828598SMugunthan V N dev_err(priv->dev, "error getting i/o resource\n"); 1078df828598SMugunthan V N ret = -ENOENT; 1079df828598SMugunthan V N goto clean_clk_ret; 1080df828598SMugunthan V N } 1081df828598SMugunthan V N 1082df828598SMugunthan V N if (!request_mem_region(priv->cpsw_ss_res->start, 1083df828598SMugunthan V N resource_size(priv->cpsw_ss_res), ndev->name)) { 1084df828598SMugunthan V N dev_err(priv->dev, "failed request i/o region\n"); 1085df828598SMugunthan V N ret = -ENXIO; 1086df828598SMugunthan V N goto clean_clk_ret; 1087df828598SMugunthan V N } 1088df828598SMugunthan V N 1089df828598SMugunthan V N regs = ioremap(priv->cpsw_ss_res->start, 1090df828598SMugunthan V N resource_size(priv->cpsw_ss_res)); 1091df828598SMugunthan V N if (!regs) { 1092df828598SMugunthan V N dev_err(priv->dev, "unable to map i/o region\n"); 1093df828598SMugunthan V N goto clean_cpsw_ss_iores_ret; 1094df828598SMugunthan V N } 1095996a5c27SRichard Cochran priv->wr_regs = regs; 1096df828598SMugunthan V N 1097df828598SMugunthan V N for_each_slave(priv, cpsw_slave_init, priv); 1098df828598SMugunthan V N 1099df828598SMugunthan V N memset(&dma_params, 0, sizeof(dma_params)); 1100df828598SMugunthan V N dma_params.dev = &pdev->dev; 1101df828598SMugunthan V N dma_params.dmaregs = cpsw_dma_regs((u32)priv->regs, 1102df828598SMugunthan V N data->cpdma_reg_ofs); 1103df828598SMugunthan V N dma_params.rxthresh = cpsw_dma_rxthresh((u32)priv->regs, 1104df828598SMugunthan V N data->cpdma_reg_ofs); 1105df828598SMugunthan V N dma_params.rxfree = cpsw_dma_rxfree((u32)priv->regs, 1106df828598SMugunthan V N data->cpdma_reg_ofs); 1107df828598SMugunthan V N dma_params.txhdp = cpsw_dma_txhdp((u32)priv->regs, 1108df828598SMugunthan V N data->cpdma_sram_ofs); 1109df828598SMugunthan V N dma_params.rxhdp = cpsw_dma_rxhdp((u32)priv->regs, 1110df828598SMugunthan V N data->cpdma_sram_ofs); 1111df828598SMugunthan V N dma_params.txcp = cpsw_dma_txcp((u32)priv->regs, 1112df828598SMugunthan V N data->cpdma_sram_ofs); 1113df828598SMugunthan V N dma_params.rxcp = cpsw_dma_rxcp((u32)priv->regs, 1114df828598SMugunthan V N data->cpdma_sram_ofs); 1115df828598SMugunthan V N 1116df828598SMugunthan V N dma_params.num_chan = data->channels; 1117df828598SMugunthan V N dma_params.has_soft_reset = true; 1118df828598SMugunthan V N dma_params.min_packet_size = CPSW_MIN_PACKET_SIZE; 1119df828598SMugunthan V N dma_params.desc_mem_size = data->bd_ram_size; 1120df828598SMugunthan V N dma_params.desc_align = 16; 1121df828598SMugunthan V N dma_params.has_ext_regs = true; 1122df828598SMugunthan V N dma_params.desc_mem_phys = data->no_bd_ram ? 0 : 1123df828598SMugunthan V N (u32 __force)priv->cpsw_res->start + data->bd_ram_ofs; 1124df828598SMugunthan V N dma_params.desc_hw_addr = data->hw_ram_addr ? 1125df828598SMugunthan V N data->hw_ram_addr : dma_params.desc_mem_phys ; 1126df828598SMugunthan V N 1127df828598SMugunthan V N priv->dma = cpdma_ctlr_create(&dma_params); 1128df828598SMugunthan V N if (!priv->dma) { 1129df828598SMugunthan V N dev_err(priv->dev, "error initializing dma\n"); 1130df828598SMugunthan V N ret = -ENOMEM; 1131df828598SMugunthan V N goto clean_iomap_ret; 1132df828598SMugunthan V N } 1133df828598SMugunthan V N 1134df828598SMugunthan V N priv->txch = cpdma_chan_create(priv->dma, tx_chan_num(0), 1135df828598SMugunthan V N cpsw_tx_handler); 1136df828598SMugunthan V N priv->rxch = cpdma_chan_create(priv->dma, rx_chan_num(0), 1137df828598SMugunthan V N cpsw_rx_handler); 1138df828598SMugunthan V N 1139df828598SMugunthan V N if (WARN_ON(!priv->txch || !priv->rxch)) { 1140df828598SMugunthan V N dev_err(priv->dev, "error initializing dma channels\n"); 1141df828598SMugunthan V N ret = -ENOMEM; 1142df828598SMugunthan V N goto clean_dma_ret; 1143df828598SMugunthan V N } 1144df828598SMugunthan V N 1145df828598SMugunthan V N memset(&ale_params, 0, sizeof(ale_params)); 1146df828598SMugunthan V N ale_params.dev = &ndev->dev; 1147df828598SMugunthan V N ale_params.ale_regs = (void *)((u32)priv->regs) + 1148df828598SMugunthan V N ((u32)data->ale_reg_ofs); 1149df828598SMugunthan V N ale_params.ale_ageout = ale_ageout; 1150df828598SMugunthan V N ale_params.ale_entries = data->ale_entries; 1151df828598SMugunthan V N ale_params.ale_ports = data->slaves; 1152df828598SMugunthan V N 1153df828598SMugunthan V N priv->ale = cpsw_ale_create(&ale_params); 1154df828598SMugunthan V N if (!priv->ale) { 1155df828598SMugunthan V N dev_err(priv->dev, "error initializing ale engine\n"); 1156df828598SMugunthan V N ret = -ENODEV; 1157df828598SMugunthan V N goto clean_dma_ret; 1158df828598SMugunthan V N } 1159df828598SMugunthan V N 1160df828598SMugunthan V N ndev->irq = platform_get_irq(pdev, 0); 1161df828598SMugunthan V N if (ndev->irq < 0) { 1162df828598SMugunthan V N dev_err(priv->dev, "error getting irq resource\n"); 1163df828598SMugunthan V N ret = -ENOENT; 1164df828598SMugunthan V N goto clean_ale_ret; 1165df828598SMugunthan V N } 1166df828598SMugunthan V N 1167df828598SMugunthan V N while ((res = platform_get_resource(priv->pdev, IORESOURCE_IRQ, k))) { 1168df828598SMugunthan V N for (i = res->start; i <= res->end; i++) { 1169df828598SMugunthan V N if (request_irq(i, cpsw_interrupt, IRQF_DISABLED, 1170df828598SMugunthan V N dev_name(&pdev->dev), priv)) { 1171df828598SMugunthan V N dev_err(priv->dev, "error attaching irq\n"); 1172df828598SMugunthan V N goto clean_ale_ret; 1173df828598SMugunthan V N } 1174df828598SMugunthan V N priv->irqs_table[k] = i; 1175df828598SMugunthan V N priv->num_irqs = k; 1176df828598SMugunthan V N } 1177df828598SMugunthan V N k++; 1178df828598SMugunthan V N } 1179df828598SMugunthan V N 1180df828598SMugunthan V N ndev->flags |= IFF_ALLMULTI; /* see cpsw_ndo_change_rx_flags() */ 1181df828598SMugunthan V N 1182df828598SMugunthan V N ndev->netdev_ops = &cpsw_netdev_ops; 1183df828598SMugunthan V N SET_ETHTOOL_OPS(ndev, &cpsw_ethtool_ops); 1184df828598SMugunthan V N netif_napi_add(ndev, &priv->napi, cpsw_poll, CPSW_POLL_WEIGHT); 1185df828598SMugunthan V N 1186df828598SMugunthan V N /* register the network device */ 1187df828598SMugunthan V N SET_NETDEV_DEV(ndev, &pdev->dev); 1188df828598SMugunthan V N ret = register_netdev(ndev); 1189df828598SMugunthan V N if (ret) { 1190df828598SMugunthan V N dev_err(priv->dev, "error registering net device\n"); 1191df828598SMugunthan V N ret = -ENODEV; 1192df828598SMugunthan V N goto clean_irq_ret; 1193df828598SMugunthan V N } 1194df828598SMugunthan V N 1195df828598SMugunthan V N cpsw_notice(priv, probe, "initialized device (regs %x, irq %d)\n", 1196df828598SMugunthan V N priv->cpsw_res->start, ndev->irq); 1197df828598SMugunthan V N 1198df828598SMugunthan V N return 0; 1199df828598SMugunthan V N 1200df828598SMugunthan V N clean_irq_ret: 1201df828598SMugunthan V N free_irq(ndev->irq, priv); 1202df828598SMugunthan V N clean_ale_ret: 1203df828598SMugunthan V N cpsw_ale_destroy(priv->ale); 1204df828598SMugunthan V N clean_dma_ret: 1205df828598SMugunthan V N cpdma_chan_destroy(priv->txch); 1206df828598SMugunthan V N cpdma_chan_destroy(priv->rxch); 1207df828598SMugunthan V N cpdma_ctlr_destroy(priv->dma); 1208df828598SMugunthan V N clean_iomap_ret: 1209df828598SMugunthan V N iounmap(priv->regs); 1210df828598SMugunthan V N clean_cpsw_ss_iores_ret: 1211df828598SMugunthan V N release_mem_region(priv->cpsw_ss_res->start, 1212df828598SMugunthan V N resource_size(priv->cpsw_ss_res)); 1213df828598SMugunthan V N clean_cpsw_iores_ret: 1214df828598SMugunthan V N release_mem_region(priv->cpsw_res->start, 1215df828598SMugunthan V N resource_size(priv->cpsw_res)); 1216df828598SMugunthan V N clean_clk_ret: 1217df828598SMugunthan V N clk_put(priv->clk); 1218f150bd7fSMugunthan V N clean_slave_ret: 1219f150bd7fSMugunthan V N pm_runtime_disable(&pdev->dev); 1220df828598SMugunthan V N kfree(priv->slaves); 1221df828598SMugunthan V N clean_ndev_ret: 1222df828598SMugunthan V N free_netdev(ndev); 1223df828598SMugunthan V N return ret; 1224df828598SMugunthan V N } 1225df828598SMugunthan V N 1226df828598SMugunthan V N static int __devexit cpsw_remove(struct platform_device *pdev) 1227df828598SMugunthan V N { 1228df828598SMugunthan V N struct net_device *ndev = platform_get_drvdata(pdev); 1229df828598SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 1230df828598SMugunthan V N 1231df828598SMugunthan V N pr_info("removing device"); 1232df828598SMugunthan V N platform_set_drvdata(pdev, NULL); 1233df828598SMugunthan V N 1234df828598SMugunthan V N free_irq(ndev->irq, priv); 1235df828598SMugunthan V N cpsw_ale_destroy(priv->ale); 1236df828598SMugunthan V N cpdma_chan_destroy(priv->txch); 1237df828598SMugunthan V N cpdma_chan_destroy(priv->rxch); 1238df828598SMugunthan V N cpdma_ctlr_destroy(priv->dma); 1239df828598SMugunthan V N iounmap(priv->regs); 1240df828598SMugunthan V N release_mem_region(priv->cpsw_res->start, 1241df828598SMugunthan V N resource_size(priv->cpsw_res)); 1242df828598SMugunthan V N release_mem_region(priv->cpsw_ss_res->start, 1243df828598SMugunthan V N resource_size(priv->cpsw_ss_res)); 1244f150bd7fSMugunthan V N pm_runtime_disable(&pdev->dev); 1245df828598SMugunthan V N clk_put(priv->clk); 1246df828598SMugunthan V N kfree(priv->slaves); 1247df828598SMugunthan V N free_netdev(ndev); 1248df828598SMugunthan V N 1249df828598SMugunthan V N return 0; 1250df828598SMugunthan V N } 1251df828598SMugunthan V N 1252df828598SMugunthan V N static int cpsw_suspend(struct device *dev) 1253df828598SMugunthan V N { 1254df828598SMugunthan V N struct platform_device *pdev = to_platform_device(dev); 1255df828598SMugunthan V N struct net_device *ndev = platform_get_drvdata(pdev); 1256df828598SMugunthan V N 1257df828598SMugunthan V N if (netif_running(ndev)) 1258df828598SMugunthan V N cpsw_ndo_stop(ndev); 1259f150bd7fSMugunthan V N pm_runtime_put_sync(&pdev->dev); 1260f150bd7fSMugunthan V N 1261df828598SMugunthan V N return 0; 1262df828598SMugunthan V N } 1263df828598SMugunthan V N 1264df828598SMugunthan V N static int cpsw_resume(struct device *dev) 1265df828598SMugunthan V N { 1266df828598SMugunthan V N struct platform_device *pdev = to_platform_device(dev); 1267df828598SMugunthan V N struct net_device *ndev = platform_get_drvdata(pdev); 1268df828598SMugunthan V N 1269f150bd7fSMugunthan V N pm_runtime_get_sync(&pdev->dev); 1270df828598SMugunthan V N if (netif_running(ndev)) 1271df828598SMugunthan V N cpsw_ndo_open(ndev); 1272df828598SMugunthan V N return 0; 1273df828598SMugunthan V N } 1274df828598SMugunthan V N 1275df828598SMugunthan V N static const struct dev_pm_ops cpsw_pm_ops = { 1276df828598SMugunthan V N .suspend = cpsw_suspend, 1277df828598SMugunthan V N .resume = cpsw_resume, 1278df828598SMugunthan V N }; 1279df828598SMugunthan V N 12802eb32b0aSMugunthan V N static const struct of_device_id cpsw_of_mtable[] = { 12812eb32b0aSMugunthan V N { .compatible = "ti,cpsw", }, 12822eb32b0aSMugunthan V N { /* sentinel */ }, 12832eb32b0aSMugunthan V N }; 12842eb32b0aSMugunthan V N 1285df828598SMugunthan V N static struct platform_driver cpsw_driver = { 1286df828598SMugunthan V N .driver = { 1287df828598SMugunthan V N .name = "cpsw", 1288df828598SMugunthan V N .owner = THIS_MODULE, 1289df828598SMugunthan V N .pm = &cpsw_pm_ops, 12902eb32b0aSMugunthan V N .of_match_table = of_match_ptr(cpsw_of_mtable), 1291df828598SMugunthan V N }, 1292df828598SMugunthan V N .probe = cpsw_probe, 1293df828598SMugunthan V N .remove = __devexit_p(cpsw_remove), 1294df828598SMugunthan V N }; 1295df828598SMugunthan V N 1296df828598SMugunthan V N static int __init cpsw_init(void) 1297df828598SMugunthan V N { 1298df828598SMugunthan V N return platform_driver_register(&cpsw_driver); 1299df828598SMugunthan V N } 1300df828598SMugunthan V N late_initcall(cpsw_init); 1301df828598SMugunthan V N 1302df828598SMugunthan V N static void __exit cpsw_exit(void) 1303df828598SMugunthan V N { 1304df828598SMugunthan V N platform_driver_unregister(&cpsw_driver); 1305df828598SMugunthan V N } 1306df828598SMugunthan V N module_exit(cpsw_exit); 1307df828598SMugunthan V N 1308df828598SMugunthan V N MODULE_LICENSE("GPL"); 1309df828598SMugunthan V N MODULE_AUTHOR("Cyril Chemparathy <cyril@ti.com>"); 1310df828598SMugunthan V N MODULE_AUTHOR("Mugunthan V N <mugunthanvnm@ti.com>"); 1311df828598SMugunthan V N MODULE_DESCRIPTION("TI CPSW Ethernet driver"); 1312