1df828598SMugunthan V N /* 2df828598SMugunthan V N * Texas Instruments Ethernet Switch Driver 3df828598SMugunthan V N * 4df828598SMugunthan V N * Copyright (C) 2012 Texas Instruments 5df828598SMugunthan V N * 6df828598SMugunthan V N * This program is free software; you can redistribute it and/or 7df828598SMugunthan V N * modify it under the terms of the GNU General Public License as 8df828598SMugunthan V N * published by the Free Software Foundation version 2. 9df828598SMugunthan V N * 10df828598SMugunthan V N * This program is distributed "as is" WITHOUT ANY WARRANTY of any 11df828598SMugunthan V N * kind, whether express or implied; without even the implied warranty 12df828598SMugunthan V N * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13df828598SMugunthan V N * GNU General Public License for more details. 14df828598SMugunthan V N */ 15df828598SMugunthan V N 16df828598SMugunthan V N #include <linux/kernel.h> 17df828598SMugunthan V N #include <linux/io.h> 18df828598SMugunthan V N #include <linux/clk.h> 19df828598SMugunthan V N #include <linux/timer.h> 20df828598SMugunthan V N #include <linux/module.h> 21df828598SMugunthan V N #include <linux/platform_device.h> 22df828598SMugunthan V N #include <linux/irqreturn.h> 23df828598SMugunthan V N #include <linux/interrupt.h> 24df828598SMugunthan V N #include <linux/if_ether.h> 25df828598SMugunthan V N #include <linux/etherdevice.h> 26df828598SMugunthan V N #include <linux/netdevice.h> 272e5b38abSRichard Cochran #include <linux/net_tstamp.h> 28df828598SMugunthan V N #include <linux/phy.h> 29df828598SMugunthan V N #include <linux/workqueue.h> 30df828598SMugunthan V N #include <linux/delay.h> 31f150bd7fSMugunthan V N #include <linux/pm_runtime.h> 322eb32b0aSMugunthan V N #include <linux/of.h> 332eb32b0aSMugunthan V N #include <linux/of_net.h> 342eb32b0aSMugunthan V N #include <linux/of_device.h> 353b72c2feSMugunthan V N #include <linux/if_vlan.h> 36df828598SMugunthan V N 37739683b4SMugunthan V N #include <linux/pinctrl/consumer.h> 38df828598SMugunthan V N 39dbe34724SMugunthan V N #include "cpsw.h" 40df828598SMugunthan V N #include "cpsw_ale.h" 412e5b38abSRichard Cochran #include "cpts.h" 42df828598SMugunthan V N #include "davinci_cpdma.h" 43df828598SMugunthan V N 44df828598SMugunthan V N #define CPSW_DEBUG (NETIF_MSG_HW | NETIF_MSG_WOL | \ 45df828598SMugunthan V N NETIF_MSG_DRV | NETIF_MSG_LINK | \ 46df828598SMugunthan V N NETIF_MSG_IFUP | NETIF_MSG_INTR | \ 47df828598SMugunthan V N NETIF_MSG_PROBE | NETIF_MSG_TIMER | \ 48df828598SMugunthan V N NETIF_MSG_IFDOWN | NETIF_MSG_RX_ERR | \ 49df828598SMugunthan V N NETIF_MSG_TX_ERR | NETIF_MSG_TX_DONE | \ 50df828598SMugunthan V N NETIF_MSG_PKTDATA | NETIF_MSG_TX_QUEUED | \ 51df828598SMugunthan V N NETIF_MSG_RX_STATUS) 52df828598SMugunthan V N 53df828598SMugunthan V N #define cpsw_info(priv, type, format, ...) \ 54df828598SMugunthan V N do { \ 55df828598SMugunthan V N if (netif_msg_##type(priv) && net_ratelimit()) \ 56df828598SMugunthan V N dev_info(priv->dev, format, ## __VA_ARGS__); \ 57df828598SMugunthan V N } while (0) 58df828598SMugunthan V N 59df828598SMugunthan V N #define cpsw_err(priv, type, format, ...) \ 60df828598SMugunthan V N do { \ 61df828598SMugunthan V N if (netif_msg_##type(priv) && net_ratelimit()) \ 62df828598SMugunthan V N dev_err(priv->dev, format, ## __VA_ARGS__); \ 63df828598SMugunthan V N } while (0) 64df828598SMugunthan V N 65df828598SMugunthan V N #define cpsw_dbg(priv, type, format, ...) \ 66df828598SMugunthan V N do { \ 67df828598SMugunthan V N if (netif_msg_##type(priv) && net_ratelimit()) \ 68df828598SMugunthan V N dev_dbg(priv->dev, format, ## __VA_ARGS__); \ 69df828598SMugunthan V N } while (0) 70df828598SMugunthan V N 71df828598SMugunthan V N #define cpsw_notice(priv, type, format, ...) \ 72df828598SMugunthan V N do { \ 73df828598SMugunthan V N if (netif_msg_##type(priv) && net_ratelimit()) \ 74df828598SMugunthan V N dev_notice(priv->dev, format, ## __VA_ARGS__); \ 75df828598SMugunthan V N } while (0) 76df828598SMugunthan V N 775c50a856SMugunthan V N #define ALE_ALL_PORTS 0x7 785c50a856SMugunthan V N 79df828598SMugunthan V N #define CPSW_MAJOR_VERSION(reg) (reg >> 8 & 0x7) 80df828598SMugunthan V N #define CPSW_MINOR_VERSION(reg) (reg & 0xff) 81df828598SMugunthan V N #define CPSW_RTL_VERSION(reg) ((reg >> 11) & 0x1f) 82df828598SMugunthan V N 83e90cfac6SRichard Cochran #define CPSW_VERSION_1 0x19010a 84e90cfac6SRichard Cochran #define CPSW_VERSION_2 0x19010c 85c193f365SMugunthan V N #define CPSW_VERSION_3 0x19010f 86926489beSMugunthan V N #define CPSW_VERSION_4 0x190112 87549985eeSRichard Cochran 88549985eeSRichard Cochran #define HOST_PORT_NUM 0 89549985eeSRichard Cochran #define SLIVER_SIZE 0x40 90549985eeSRichard Cochran 91549985eeSRichard Cochran #define CPSW1_HOST_PORT_OFFSET 0x028 92549985eeSRichard Cochran #define CPSW1_SLAVE_OFFSET 0x050 93549985eeSRichard Cochran #define CPSW1_SLAVE_SIZE 0x040 94549985eeSRichard Cochran #define CPSW1_CPDMA_OFFSET 0x100 95549985eeSRichard Cochran #define CPSW1_STATERAM_OFFSET 0x200 96d9718546SMugunthan V N #define CPSW1_HW_STATS 0x400 97549985eeSRichard Cochran #define CPSW1_CPTS_OFFSET 0x500 98549985eeSRichard Cochran #define CPSW1_ALE_OFFSET 0x600 99549985eeSRichard Cochran #define CPSW1_SLIVER_OFFSET 0x700 100549985eeSRichard Cochran 101549985eeSRichard Cochran #define CPSW2_HOST_PORT_OFFSET 0x108 102549985eeSRichard Cochran #define CPSW2_SLAVE_OFFSET 0x200 103549985eeSRichard Cochran #define CPSW2_SLAVE_SIZE 0x100 104549985eeSRichard Cochran #define CPSW2_CPDMA_OFFSET 0x800 105d9718546SMugunthan V N #define CPSW2_HW_STATS 0x900 106549985eeSRichard Cochran #define CPSW2_STATERAM_OFFSET 0xa00 107549985eeSRichard Cochran #define CPSW2_CPTS_OFFSET 0xc00 108549985eeSRichard Cochran #define CPSW2_ALE_OFFSET 0xd00 109549985eeSRichard Cochran #define CPSW2_SLIVER_OFFSET 0xd80 110549985eeSRichard Cochran #define CPSW2_BD_OFFSET 0x2000 111549985eeSRichard Cochran 112df828598SMugunthan V N #define CPDMA_RXTHRESH 0x0c0 113df828598SMugunthan V N #define CPDMA_RXFREE 0x0e0 114df828598SMugunthan V N #define CPDMA_TXHDP 0x00 115df828598SMugunthan V N #define CPDMA_RXHDP 0x20 116df828598SMugunthan V N #define CPDMA_TXCP 0x40 117df828598SMugunthan V N #define CPDMA_RXCP 0x60 118df828598SMugunthan V N 119df828598SMugunthan V N #define CPSW_POLL_WEIGHT 64 120df828598SMugunthan V N #define CPSW_MIN_PACKET_SIZE 60 121df828598SMugunthan V N #define CPSW_MAX_PACKET_SIZE (1500 + 14 + 4 + 4) 122df828598SMugunthan V N 123df828598SMugunthan V N #define RX_PRIORITY_MAPPING 0x76543210 124df828598SMugunthan V N #define TX_PRIORITY_MAPPING 0x33221100 125df828598SMugunthan V N #define CPDMA_TX_PRIORITY_MAP 0x76543210 126df828598SMugunthan V N 1273b72c2feSMugunthan V N #define CPSW_VLAN_AWARE BIT(1) 1283b72c2feSMugunthan V N #define CPSW_ALE_VLAN_AWARE 1 1293b72c2feSMugunthan V N 130d9ba8f9eSMugunthan V N #define CPSW_FIFO_NORMAL_MODE (0 << 15) 131d9ba8f9eSMugunthan V N #define CPSW_FIFO_DUAL_MAC_MODE (1 << 15) 132d9ba8f9eSMugunthan V N #define CPSW_FIFO_RATE_LIMIT_MODE (2 << 15) 133d9ba8f9eSMugunthan V N 134ff5b8ef2SMugunthan V N #define CPSW_INTPACEEN (0x3f << 16) 135ff5b8ef2SMugunthan V N #define CPSW_INTPRESCALE_MASK (0x7FF << 0) 136ff5b8ef2SMugunthan V N #define CPSW_CMINTMAX_CNT 63 137ff5b8ef2SMugunthan V N #define CPSW_CMINTMIN_CNT 2 138ff5b8ef2SMugunthan V N #define CPSW_CMINTMAX_INTVL (1000 / CPSW_CMINTMIN_CNT) 139ff5b8ef2SMugunthan V N #define CPSW_CMINTMIN_INTVL ((1000 / CPSW_CMINTMAX_CNT) + 1) 140ff5b8ef2SMugunthan V N 141df828598SMugunthan V N #define cpsw_enable_irq(priv) \ 142df828598SMugunthan V N do { \ 143df828598SMugunthan V N u32 i; \ 144df828598SMugunthan V N for (i = 0; i < priv->num_irqs; i++) \ 145df828598SMugunthan V N enable_irq(priv->irqs_table[i]); \ 1465f47dfb4SJoe Perches } while (0) 147df828598SMugunthan V N #define cpsw_disable_irq(priv) \ 148df828598SMugunthan V N do { \ 149df828598SMugunthan V N u32 i; \ 150df828598SMugunthan V N for (i = 0; i < priv->num_irqs; i++) \ 151df828598SMugunthan V N disable_irq_nosync(priv->irqs_table[i]); \ 1525f47dfb4SJoe Perches } while (0) 153df828598SMugunthan V N 154d3bb9c58SMugunthan V N #define cpsw_slave_index(priv) \ 155d3bb9c58SMugunthan V N ((priv->data.dual_emac) ? priv->emac_port : \ 156d3bb9c58SMugunthan V N priv->data.active_slave) 157d3bb9c58SMugunthan V N 158df828598SMugunthan V N static int debug_level; 159df828598SMugunthan V N module_param(debug_level, int, 0); 160df828598SMugunthan V N MODULE_PARM_DESC(debug_level, "cpsw debug level (NETIF_MSG bits)"); 161df828598SMugunthan V N 162df828598SMugunthan V N static int ale_ageout = 10; 163df828598SMugunthan V N module_param(ale_ageout, int, 0); 164df828598SMugunthan V N MODULE_PARM_DESC(ale_ageout, "cpsw ale ageout interval (seconds)"); 165df828598SMugunthan V N 166df828598SMugunthan V N static int rx_packet_max = CPSW_MAX_PACKET_SIZE; 167df828598SMugunthan V N module_param(rx_packet_max, int, 0); 168df828598SMugunthan V N MODULE_PARM_DESC(rx_packet_max, "maximum receive packet size (bytes)"); 169df828598SMugunthan V N 170996a5c27SRichard Cochran struct cpsw_wr_regs { 171df828598SMugunthan V N u32 id_ver; 172df828598SMugunthan V N u32 soft_reset; 173df828598SMugunthan V N u32 control; 174df828598SMugunthan V N u32 int_control; 175df828598SMugunthan V N u32 rx_thresh_en; 176df828598SMugunthan V N u32 rx_en; 177df828598SMugunthan V N u32 tx_en; 178df828598SMugunthan V N u32 misc_en; 179ff5b8ef2SMugunthan V N u32 mem_allign1[8]; 180ff5b8ef2SMugunthan V N u32 rx_thresh_stat; 181ff5b8ef2SMugunthan V N u32 rx_stat; 182ff5b8ef2SMugunthan V N u32 tx_stat; 183ff5b8ef2SMugunthan V N u32 misc_stat; 184ff5b8ef2SMugunthan V N u32 mem_allign2[8]; 185ff5b8ef2SMugunthan V N u32 rx_imax; 186ff5b8ef2SMugunthan V N u32 tx_imax; 187ff5b8ef2SMugunthan V N 188df828598SMugunthan V N }; 189df828598SMugunthan V N 190996a5c27SRichard Cochran struct cpsw_ss_regs { 191df828598SMugunthan V N u32 id_ver; 192df828598SMugunthan V N u32 control; 193df828598SMugunthan V N u32 soft_reset; 194df828598SMugunthan V N u32 stat_port_en; 195df828598SMugunthan V N u32 ptype; 196bd357af2SRichard Cochran u32 soft_idle; 197bd357af2SRichard Cochran u32 thru_rate; 198bd357af2SRichard Cochran u32 gap_thresh; 199bd357af2SRichard Cochran u32 tx_start_wds; 200bd357af2SRichard Cochran u32 flow_control; 201bd357af2SRichard Cochran u32 vlan_ltype; 202bd357af2SRichard Cochran u32 ts_ltype; 203bd357af2SRichard Cochran u32 dlr_ltype; 204df828598SMugunthan V N }; 205df828598SMugunthan V N 2069750a3adSRichard Cochran /* CPSW_PORT_V1 */ 2079750a3adSRichard Cochran #define CPSW1_MAX_BLKS 0x00 /* Maximum FIFO Blocks */ 2089750a3adSRichard Cochran #define CPSW1_BLK_CNT 0x04 /* FIFO Block Usage Count (Read Only) */ 2099750a3adSRichard Cochran #define CPSW1_TX_IN_CTL 0x08 /* Transmit FIFO Control */ 2109750a3adSRichard Cochran #define CPSW1_PORT_VLAN 0x0c /* VLAN Register */ 2119750a3adSRichard Cochran #define CPSW1_TX_PRI_MAP 0x10 /* Tx Header Priority to Switch Pri Mapping */ 2129750a3adSRichard Cochran #define CPSW1_TS_CTL 0x14 /* Time Sync Control */ 2139750a3adSRichard Cochran #define CPSW1_TS_SEQ_LTYPE 0x18 /* Time Sync Sequence ID Offset and Msg Type */ 2149750a3adSRichard Cochran #define CPSW1_TS_VLAN 0x1c /* Time Sync VLAN1 and VLAN2 */ 2159750a3adSRichard Cochran 2169750a3adSRichard Cochran /* CPSW_PORT_V2 */ 2179750a3adSRichard Cochran #define CPSW2_CONTROL 0x00 /* Control Register */ 2189750a3adSRichard Cochran #define CPSW2_MAX_BLKS 0x08 /* Maximum FIFO Blocks */ 2199750a3adSRichard Cochran #define CPSW2_BLK_CNT 0x0c /* FIFO Block Usage Count (Read Only) */ 2209750a3adSRichard Cochran #define CPSW2_TX_IN_CTL 0x10 /* Transmit FIFO Control */ 2219750a3adSRichard Cochran #define CPSW2_PORT_VLAN 0x14 /* VLAN Register */ 2229750a3adSRichard Cochran #define CPSW2_TX_PRI_MAP 0x18 /* Tx Header Priority to Switch Pri Mapping */ 2239750a3adSRichard Cochran #define CPSW2_TS_SEQ_MTYPE 0x1c /* Time Sync Sequence ID Offset and Msg Type */ 2249750a3adSRichard Cochran 2259750a3adSRichard Cochran /* CPSW_PORT_V1 and V2 */ 2269750a3adSRichard Cochran #define SA_LO 0x20 /* CPGMAC_SL Source Address Low */ 2279750a3adSRichard Cochran #define SA_HI 0x24 /* CPGMAC_SL Source Address High */ 2289750a3adSRichard Cochran #define SEND_PERCENT 0x28 /* Transmit Queue Send Percentages */ 2299750a3adSRichard Cochran 2309750a3adSRichard Cochran /* CPSW_PORT_V2 only */ 2319750a3adSRichard Cochran #define RX_DSCP_PRI_MAP0 0x30 /* Rx DSCP Priority to Rx Packet Mapping */ 2329750a3adSRichard Cochran #define RX_DSCP_PRI_MAP1 0x34 /* Rx DSCP Priority to Rx Packet Mapping */ 2339750a3adSRichard Cochran #define RX_DSCP_PRI_MAP2 0x38 /* Rx DSCP Priority to Rx Packet Mapping */ 2349750a3adSRichard Cochran #define RX_DSCP_PRI_MAP3 0x3c /* Rx DSCP Priority to Rx Packet Mapping */ 2359750a3adSRichard Cochran #define RX_DSCP_PRI_MAP4 0x40 /* Rx DSCP Priority to Rx Packet Mapping */ 2369750a3adSRichard Cochran #define RX_DSCP_PRI_MAP5 0x44 /* Rx DSCP Priority to Rx Packet Mapping */ 2379750a3adSRichard Cochran #define RX_DSCP_PRI_MAP6 0x48 /* Rx DSCP Priority to Rx Packet Mapping */ 2389750a3adSRichard Cochran #define RX_DSCP_PRI_MAP7 0x4c /* Rx DSCP Priority to Rx Packet Mapping */ 2399750a3adSRichard Cochran 2409750a3adSRichard Cochran /* Bit definitions for the CPSW2_CONTROL register */ 2419750a3adSRichard Cochran #define PASS_PRI_TAGGED (1<<24) /* Pass Priority Tagged */ 2429750a3adSRichard Cochran #define VLAN_LTYPE2_EN (1<<21) /* VLAN LTYPE 2 enable */ 2439750a3adSRichard Cochran #define VLAN_LTYPE1_EN (1<<20) /* VLAN LTYPE 1 enable */ 2449750a3adSRichard Cochran #define DSCP_PRI_EN (1<<16) /* DSCP Priority Enable */ 2459750a3adSRichard Cochran #define TS_320 (1<<14) /* Time Sync Dest Port 320 enable */ 2469750a3adSRichard Cochran #define TS_319 (1<<13) /* Time Sync Dest Port 319 enable */ 2479750a3adSRichard Cochran #define TS_132 (1<<12) /* Time Sync Dest IP Addr 132 enable */ 2489750a3adSRichard Cochran #define TS_131 (1<<11) /* Time Sync Dest IP Addr 131 enable */ 2499750a3adSRichard Cochran #define TS_130 (1<<10) /* Time Sync Dest IP Addr 130 enable */ 2509750a3adSRichard Cochran #define TS_129 (1<<9) /* Time Sync Dest IP Addr 129 enable */ 25109c55372SGeorge Cherian #define TS_TTL_NONZERO (1<<8) /* Time Sync Time To Live Non-zero enable */ 25209c55372SGeorge Cherian #define TS_ANNEX_F_EN (1<<6) /* Time Sync Annex F enable */ 2539750a3adSRichard Cochran #define TS_ANNEX_D_EN (1<<4) /* Time Sync Annex D enable */ 2549750a3adSRichard Cochran #define TS_LTYPE2_EN (1<<3) /* Time Sync LTYPE 2 enable */ 2559750a3adSRichard Cochran #define TS_LTYPE1_EN (1<<2) /* Time Sync LTYPE 1 enable */ 2569750a3adSRichard Cochran #define TS_TX_EN (1<<1) /* Time Sync Transmit Enable */ 2579750a3adSRichard Cochran #define TS_RX_EN (1<<0) /* Time Sync Receive Enable */ 2589750a3adSRichard Cochran 25909c55372SGeorge Cherian #define CTRL_V2_TS_BITS \ 26009c55372SGeorge Cherian (TS_320 | TS_319 | TS_132 | TS_131 | TS_130 | TS_129 |\ 26109c55372SGeorge Cherian TS_TTL_NONZERO | TS_ANNEX_D_EN | TS_LTYPE1_EN) 2629750a3adSRichard Cochran 26309c55372SGeorge Cherian #define CTRL_V2_ALL_TS_MASK (CTRL_V2_TS_BITS | TS_TX_EN | TS_RX_EN) 26409c55372SGeorge Cherian #define CTRL_V2_TX_TS_BITS (CTRL_V2_TS_BITS | TS_TX_EN) 26509c55372SGeorge Cherian #define CTRL_V2_RX_TS_BITS (CTRL_V2_TS_BITS | TS_RX_EN) 26609c55372SGeorge Cherian 26709c55372SGeorge Cherian 26809c55372SGeorge Cherian #define CTRL_V3_TS_BITS \ 26909c55372SGeorge Cherian (TS_320 | TS_319 | TS_132 | TS_131 | TS_130 | TS_129 |\ 27009c55372SGeorge Cherian TS_TTL_NONZERO | TS_ANNEX_F_EN | TS_ANNEX_D_EN |\ 27109c55372SGeorge Cherian TS_LTYPE1_EN) 27209c55372SGeorge Cherian 27309c55372SGeorge Cherian #define CTRL_V3_ALL_TS_MASK (CTRL_V3_TS_BITS | TS_TX_EN | TS_RX_EN) 27409c55372SGeorge Cherian #define CTRL_V3_TX_TS_BITS (CTRL_V3_TS_BITS | TS_TX_EN) 27509c55372SGeorge Cherian #define CTRL_V3_RX_TS_BITS (CTRL_V3_TS_BITS | TS_RX_EN) 2769750a3adSRichard Cochran 2779750a3adSRichard Cochran /* Bit definitions for the CPSW2_TS_SEQ_MTYPE register */ 2789750a3adSRichard Cochran #define TS_SEQ_ID_OFFSET_SHIFT (16) /* Time Sync Sequence ID Offset */ 2799750a3adSRichard Cochran #define TS_SEQ_ID_OFFSET_MASK (0x3f) 2809750a3adSRichard Cochran #define TS_MSG_TYPE_EN_SHIFT (0) /* Time Sync Message Type Enable */ 2819750a3adSRichard Cochran #define TS_MSG_TYPE_EN_MASK (0xffff) 2829750a3adSRichard Cochran 2839750a3adSRichard Cochran /* The PTP event messages - Sync, Delay_Req, Pdelay_Req, and Pdelay_Resp. */ 2849750a3adSRichard Cochran #define EVENT_MSG_BITS ((1<<0) | (1<<1) | (1<<2) | (1<<3)) 285df828598SMugunthan V N 2862e5b38abSRichard Cochran /* Bit definitions for the CPSW1_TS_CTL register */ 2872e5b38abSRichard Cochran #define CPSW_V1_TS_RX_EN BIT(0) 2882e5b38abSRichard Cochran #define CPSW_V1_TS_TX_EN BIT(4) 2892e5b38abSRichard Cochran #define CPSW_V1_MSG_TYPE_OFS 16 2902e5b38abSRichard Cochran 2912e5b38abSRichard Cochran /* Bit definitions for the CPSW1_TS_SEQ_LTYPE register */ 2922e5b38abSRichard Cochran #define CPSW_V1_SEQ_ID_OFS_SHIFT 16 2932e5b38abSRichard Cochran 294df828598SMugunthan V N struct cpsw_host_regs { 295df828598SMugunthan V N u32 max_blks; 296df828598SMugunthan V N u32 blk_cnt; 297d9ba8f9eSMugunthan V N u32 tx_in_ctl; 298df828598SMugunthan V N u32 port_vlan; 299df828598SMugunthan V N u32 tx_pri_map; 300df828598SMugunthan V N u32 cpdma_tx_pri_map; 301df828598SMugunthan V N u32 cpdma_rx_chan_map; 302df828598SMugunthan V N }; 303df828598SMugunthan V N 304df828598SMugunthan V N struct cpsw_sliver_regs { 305df828598SMugunthan V N u32 id_ver; 306df828598SMugunthan V N u32 mac_control; 307df828598SMugunthan V N u32 mac_status; 308df828598SMugunthan V N u32 soft_reset; 309df828598SMugunthan V N u32 rx_maxlen; 310df828598SMugunthan V N u32 __reserved_0; 311df828598SMugunthan V N u32 rx_pause; 312df828598SMugunthan V N u32 tx_pause; 313df828598SMugunthan V N u32 __reserved_1; 314df828598SMugunthan V N u32 rx_pri_map; 315df828598SMugunthan V N }; 316df828598SMugunthan V N 317d9718546SMugunthan V N struct cpsw_hw_stats { 318d9718546SMugunthan V N u32 rxgoodframes; 319d9718546SMugunthan V N u32 rxbroadcastframes; 320d9718546SMugunthan V N u32 rxmulticastframes; 321d9718546SMugunthan V N u32 rxpauseframes; 322d9718546SMugunthan V N u32 rxcrcerrors; 323d9718546SMugunthan V N u32 rxaligncodeerrors; 324d9718546SMugunthan V N u32 rxoversizedframes; 325d9718546SMugunthan V N u32 rxjabberframes; 326d9718546SMugunthan V N u32 rxundersizedframes; 327d9718546SMugunthan V N u32 rxfragments; 328d9718546SMugunthan V N u32 __pad_0[2]; 329d9718546SMugunthan V N u32 rxoctets; 330d9718546SMugunthan V N u32 txgoodframes; 331d9718546SMugunthan V N u32 txbroadcastframes; 332d9718546SMugunthan V N u32 txmulticastframes; 333d9718546SMugunthan V N u32 txpauseframes; 334d9718546SMugunthan V N u32 txdeferredframes; 335d9718546SMugunthan V N u32 txcollisionframes; 336d9718546SMugunthan V N u32 txsinglecollframes; 337d9718546SMugunthan V N u32 txmultcollframes; 338d9718546SMugunthan V N u32 txexcessivecollisions; 339d9718546SMugunthan V N u32 txlatecollisions; 340d9718546SMugunthan V N u32 txunderrun; 341d9718546SMugunthan V N u32 txcarriersenseerrors; 342d9718546SMugunthan V N u32 txoctets; 343d9718546SMugunthan V N u32 octetframes64; 344d9718546SMugunthan V N u32 octetframes65t127; 345d9718546SMugunthan V N u32 octetframes128t255; 346d9718546SMugunthan V N u32 octetframes256t511; 347d9718546SMugunthan V N u32 octetframes512t1023; 348d9718546SMugunthan V N u32 octetframes1024tup; 349d9718546SMugunthan V N u32 netoctets; 350d9718546SMugunthan V N u32 rxsofoverruns; 351d9718546SMugunthan V N u32 rxmofoverruns; 352d9718546SMugunthan V N u32 rxdmaoverruns; 353d9718546SMugunthan V N }; 354d9718546SMugunthan V N 355df828598SMugunthan V N struct cpsw_slave { 3569750a3adSRichard Cochran void __iomem *regs; 357df828598SMugunthan V N struct cpsw_sliver_regs __iomem *sliver; 358df828598SMugunthan V N int slave_num; 359df828598SMugunthan V N u32 mac_control; 360df828598SMugunthan V N struct cpsw_slave_data *data; 361df828598SMugunthan V N struct phy_device *phy; 362d9ba8f9eSMugunthan V N struct net_device *ndev; 363d9ba8f9eSMugunthan V N u32 port_vlan; 364d9ba8f9eSMugunthan V N u32 open_stat; 365df828598SMugunthan V N }; 366df828598SMugunthan V N 3679750a3adSRichard Cochran static inline u32 slave_read(struct cpsw_slave *slave, u32 offset) 3689750a3adSRichard Cochran { 3699750a3adSRichard Cochran return __raw_readl(slave->regs + offset); 3709750a3adSRichard Cochran } 3719750a3adSRichard Cochran 3729750a3adSRichard Cochran static inline void slave_write(struct cpsw_slave *slave, u32 val, u32 offset) 3739750a3adSRichard Cochran { 3749750a3adSRichard Cochran __raw_writel(val, slave->regs + offset); 3759750a3adSRichard Cochran } 3769750a3adSRichard Cochran 377df828598SMugunthan V N struct cpsw_priv { 378df828598SMugunthan V N spinlock_t lock; 379df828598SMugunthan V N struct platform_device *pdev; 380df828598SMugunthan V N struct net_device *ndev; 381df828598SMugunthan V N struct napi_struct napi; 382df828598SMugunthan V N struct device *dev; 383df828598SMugunthan V N struct cpsw_platform_data data; 384996a5c27SRichard Cochran struct cpsw_ss_regs __iomem *regs; 385996a5c27SRichard Cochran struct cpsw_wr_regs __iomem *wr_regs; 386d9718546SMugunthan V N u8 __iomem *hw_stats; 387df828598SMugunthan V N struct cpsw_host_regs __iomem *host_port_regs; 388df828598SMugunthan V N u32 msg_enable; 389e90cfac6SRichard Cochran u32 version; 390ff5b8ef2SMugunthan V N u32 coal_intvl; 391ff5b8ef2SMugunthan V N u32 bus_freq_mhz; 392df828598SMugunthan V N int rx_packet_max; 393df828598SMugunthan V N int host_port; 394df828598SMugunthan V N struct clk *clk; 395df828598SMugunthan V N u8 mac_addr[ETH_ALEN]; 396df828598SMugunthan V N struct cpsw_slave *slaves; 397df828598SMugunthan V N struct cpdma_ctlr *dma; 398df828598SMugunthan V N struct cpdma_chan *txch, *rxch; 399df828598SMugunthan V N struct cpsw_ale *ale; 400df828598SMugunthan V N /* snapshot of IRQ numbers */ 401df828598SMugunthan V N u32 irqs_table[4]; 402df828598SMugunthan V N u32 num_irqs; 403a11fbba9SSebastian Siewior bool irq_enabled; 4049232b16dSMugunthan V N struct cpts *cpts; 405d9ba8f9eSMugunthan V N u32 emac_port; 406df828598SMugunthan V N }; 407df828598SMugunthan V N 408d9718546SMugunthan V N struct cpsw_stats { 409d9718546SMugunthan V N char stat_string[ETH_GSTRING_LEN]; 410d9718546SMugunthan V N int type; 411d9718546SMugunthan V N int sizeof_stat; 412d9718546SMugunthan V N int stat_offset; 413d9718546SMugunthan V N }; 414d9718546SMugunthan V N 415d9718546SMugunthan V N enum { 416d9718546SMugunthan V N CPSW_STATS, 417d9718546SMugunthan V N CPDMA_RX_STATS, 418d9718546SMugunthan V N CPDMA_TX_STATS, 419d9718546SMugunthan V N }; 420d9718546SMugunthan V N 421d9718546SMugunthan V N #define CPSW_STAT(m) CPSW_STATS, \ 422d9718546SMugunthan V N sizeof(((struct cpsw_hw_stats *)0)->m), \ 423d9718546SMugunthan V N offsetof(struct cpsw_hw_stats, m) 424d9718546SMugunthan V N #define CPDMA_RX_STAT(m) CPDMA_RX_STATS, \ 425d9718546SMugunthan V N sizeof(((struct cpdma_chan_stats *)0)->m), \ 426d9718546SMugunthan V N offsetof(struct cpdma_chan_stats, m) 427d9718546SMugunthan V N #define CPDMA_TX_STAT(m) CPDMA_TX_STATS, \ 428d9718546SMugunthan V N sizeof(((struct cpdma_chan_stats *)0)->m), \ 429d9718546SMugunthan V N offsetof(struct cpdma_chan_stats, m) 430d9718546SMugunthan V N 431d9718546SMugunthan V N static const struct cpsw_stats cpsw_gstrings_stats[] = { 432d9718546SMugunthan V N { "Good Rx Frames", CPSW_STAT(rxgoodframes) }, 433d9718546SMugunthan V N { "Broadcast Rx Frames", CPSW_STAT(rxbroadcastframes) }, 434d9718546SMugunthan V N { "Multicast Rx Frames", CPSW_STAT(rxmulticastframes) }, 435d9718546SMugunthan V N { "Pause Rx Frames", CPSW_STAT(rxpauseframes) }, 436d9718546SMugunthan V N { "Rx CRC Errors", CPSW_STAT(rxcrcerrors) }, 437d9718546SMugunthan V N { "Rx Align/Code Errors", CPSW_STAT(rxaligncodeerrors) }, 438d9718546SMugunthan V N { "Oversize Rx Frames", CPSW_STAT(rxoversizedframes) }, 439d9718546SMugunthan V N { "Rx Jabbers", CPSW_STAT(rxjabberframes) }, 440d9718546SMugunthan V N { "Undersize (Short) Rx Frames", CPSW_STAT(rxundersizedframes) }, 441d9718546SMugunthan V N { "Rx Fragments", CPSW_STAT(rxfragments) }, 442d9718546SMugunthan V N { "Rx Octets", CPSW_STAT(rxoctets) }, 443d9718546SMugunthan V N { "Good Tx Frames", CPSW_STAT(txgoodframes) }, 444d9718546SMugunthan V N { "Broadcast Tx Frames", CPSW_STAT(txbroadcastframes) }, 445d9718546SMugunthan V N { "Multicast Tx Frames", CPSW_STAT(txmulticastframes) }, 446d9718546SMugunthan V N { "Pause Tx Frames", CPSW_STAT(txpauseframes) }, 447d9718546SMugunthan V N { "Deferred Tx Frames", CPSW_STAT(txdeferredframes) }, 448d9718546SMugunthan V N { "Collisions", CPSW_STAT(txcollisionframes) }, 449d9718546SMugunthan V N { "Single Collision Tx Frames", CPSW_STAT(txsinglecollframes) }, 450d9718546SMugunthan V N { "Multiple Collision Tx Frames", CPSW_STAT(txmultcollframes) }, 451d9718546SMugunthan V N { "Excessive Collisions", CPSW_STAT(txexcessivecollisions) }, 452d9718546SMugunthan V N { "Late Collisions", CPSW_STAT(txlatecollisions) }, 453d9718546SMugunthan V N { "Tx Underrun", CPSW_STAT(txunderrun) }, 454d9718546SMugunthan V N { "Carrier Sense Errors", CPSW_STAT(txcarriersenseerrors) }, 455d9718546SMugunthan V N { "Tx Octets", CPSW_STAT(txoctets) }, 456d9718546SMugunthan V N { "Rx + Tx 64 Octet Frames", CPSW_STAT(octetframes64) }, 457d9718546SMugunthan V N { "Rx + Tx 65-127 Octet Frames", CPSW_STAT(octetframes65t127) }, 458d9718546SMugunthan V N { "Rx + Tx 128-255 Octet Frames", CPSW_STAT(octetframes128t255) }, 459d9718546SMugunthan V N { "Rx + Tx 256-511 Octet Frames", CPSW_STAT(octetframes256t511) }, 460d9718546SMugunthan V N { "Rx + Tx 512-1023 Octet Frames", CPSW_STAT(octetframes512t1023) }, 461d9718546SMugunthan V N { "Rx + Tx 1024-Up Octet Frames", CPSW_STAT(octetframes1024tup) }, 462d9718546SMugunthan V N { "Net Octets", CPSW_STAT(netoctets) }, 463d9718546SMugunthan V N { "Rx Start of Frame Overruns", CPSW_STAT(rxsofoverruns) }, 464d9718546SMugunthan V N { "Rx Middle of Frame Overruns", CPSW_STAT(rxmofoverruns) }, 465d9718546SMugunthan V N { "Rx DMA Overruns", CPSW_STAT(rxdmaoverruns) }, 466d9718546SMugunthan V N { "Rx DMA chan: head_enqueue", CPDMA_RX_STAT(head_enqueue) }, 467d9718546SMugunthan V N { "Rx DMA chan: tail_enqueue", CPDMA_RX_STAT(tail_enqueue) }, 468d9718546SMugunthan V N { "Rx DMA chan: pad_enqueue", CPDMA_RX_STAT(pad_enqueue) }, 469d9718546SMugunthan V N { "Rx DMA chan: misqueued", CPDMA_RX_STAT(misqueued) }, 470d9718546SMugunthan V N { "Rx DMA chan: desc_alloc_fail", CPDMA_RX_STAT(desc_alloc_fail) }, 471d9718546SMugunthan V N { "Rx DMA chan: pad_alloc_fail", CPDMA_RX_STAT(pad_alloc_fail) }, 472d9718546SMugunthan V N { "Rx DMA chan: runt_receive_buf", CPDMA_RX_STAT(runt_receive_buff) }, 473d9718546SMugunthan V N { "Rx DMA chan: runt_transmit_buf", CPDMA_RX_STAT(runt_transmit_buff) }, 474d9718546SMugunthan V N { "Rx DMA chan: empty_dequeue", CPDMA_RX_STAT(empty_dequeue) }, 475d9718546SMugunthan V N { "Rx DMA chan: busy_dequeue", CPDMA_RX_STAT(busy_dequeue) }, 476d9718546SMugunthan V N { "Rx DMA chan: good_dequeue", CPDMA_RX_STAT(good_dequeue) }, 477d9718546SMugunthan V N { "Rx DMA chan: requeue", CPDMA_RX_STAT(requeue) }, 478d9718546SMugunthan V N { "Rx DMA chan: teardown_dequeue", CPDMA_RX_STAT(teardown_dequeue) }, 479d9718546SMugunthan V N { "Tx DMA chan: head_enqueue", CPDMA_TX_STAT(head_enqueue) }, 480d9718546SMugunthan V N { "Tx DMA chan: tail_enqueue", CPDMA_TX_STAT(tail_enqueue) }, 481d9718546SMugunthan V N { "Tx DMA chan: pad_enqueue", CPDMA_TX_STAT(pad_enqueue) }, 482d9718546SMugunthan V N { "Tx DMA chan: misqueued", CPDMA_TX_STAT(misqueued) }, 483d9718546SMugunthan V N { "Tx DMA chan: desc_alloc_fail", CPDMA_TX_STAT(desc_alloc_fail) }, 484d9718546SMugunthan V N { "Tx DMA chan: pad_alloc_fail", CPDMA_TX_STAT(pad_alloc_fail) }, 485d9718546SMugunthan V N { "Tx DMA chan: runt_receive_buf", CPDMA_TX_STAT(runt_receive_buff) }, 486d9718546SMugunthan V N { "Tx DMA chan: runt_transmit_buf", CPDMA_TX_STAT(runt_transmit_buff) }, 487d9718546SMugunthan V N { "Tx DMA chan: empty_dequeue", CPDMA_TX_STAT(empty_dequeue) }, 488d9718546SMugunthan V N { "Tx DMA chan: busy_dequeue", CPDMA_TX_STAT(busy_dequeue) }, 489d9718546SMugunthan V N { "Tx DMA chan: good_dequeue", CPDMA_TX_STAT(good_dequeue) }, 490d9718546SMugunthan V N { "Tx DMA chan: requeue", CPDMA_TX_STAT(requeue) }, 491d9718546SMugunthan V N { "Tx DMA chan: teardown_dequeue", CPDMA_TX_STAT(teardown_dequeue) }, 492d9718546SMugunthan V N }; 493d9718546SMugunthan V N 494d9718546SMugunthan V N #define CPSW_STATS_LEN ARRAY_SIZE(cpsw_gstrings_stats) 495d9718546SMugunthan V N 496df828598SMugunthan V N #define napi_to_priv(napi) container_of(napi, struct cpsw_priv, napi) 497df828598SMugunthan V N #define for_each_slave(priv, func, arg...) \ 498df828598SMugunthan V N do { \ 4996e6ceaedSSebastian Siewior struct cpsw_slave *slave; \ 5006e6ceaedSSebastian Siewior int n; \ 501d9ba8f9eSMugunthan V N if (priv->data.dual_emac) \ 502d9ba8f9eSMugunthan V N (func)((priv)->slaves + priv->emac_port, ##arg);\ 503d9ba8f9eSMugunthan V N else \ 5046e6ceaedSSebastian Siewior for (n = (priv)->data.slaves, \ 5056e6ceaedSSebastian Siewior slave = (priv)->slaves; \ 5066e6ceaedSSebastian Siewior n; n--) \ 5076e6ceaedSSebastian Siewior (func)(slave++, ##arg); \ 508df828598SMugunthan V N } while (0) 509d9ba8f9eSMugunthan V N #define cpsw_get_slave_ndev(priv, __slave_no__) \ 510d9ba8f9eSMugunthan V N (priv->slaves[__slave_no__].ndev) 511d9ba8f9eSMugunthan V N #define cpsw_get_slave_priv(priv, __slave_no__) \ 512d9ba8f9eSMugunthan V N ((priv->slaves[__slave_no__].ndev) ? \ 513d9ba8f9eSMugunthan V N netdev_priv(priv->slaves[__slave_no__].ndev) : NULL) \ 514d9ba8f9eSMugunthan V N 515d9ba8f9eSMugunthan V N #define cpsw_dual_emac_src_port_detect(status, priv, ndev, skb) \ 516d9ba8f9eSMugunthan V N do { \ 517d9ba8f9eSMugunthan V N if (!priv->data.dual_emac) \ 518d9ba8f9eSMugunthan V N break; \ 519d9ba8f9eSMugunthan V N if (CPDMA_RX_SOURCE_PORT(status) == 1) { \ 520d9ba8f9eSMugunthan V N ndev = cpsw_get_slave_ndev(priv, 0); \ 521d9ba8f9eSMugunthan V N priv = netdev_priv(ndev); \ 522d9ba8f9eSMugunthan V N skb->dev = ndev; \ 523d9ba8f9eSMugunthan V N } else if (CPDMA_RX_SOURCE_PORT(status) == 2) { \ 524d9ba8f9eSMugunthan V N ndev = cpsw_get_slave_ndev(priv, 1); \ 525d9ba8f9eSMugunthan V N priv = netdev_priv(ndev); \ 526d9ba8f9eSMugunthan V N skb->dev = ndev; \ 527d9ba8f9eSMugunthan V N } \ 528d9ba8f9eSMugunthan V N } while (0) 529d9ba8f9eSMugunthan V N #define cpsw_add_mcast(priv, addr) \ 530d9ba8f9eSMugunthan V N do { \ 531d9ba8f9eSMugunthan V N if (priv->data.dual_emac) { \ 532d9ba8f9eSMugunthan V N struct cpsw_slave *slave = priv->slaves + \ 533d9ba8f9eSMugunthan V N priv->emac_port; \ 534d9ba8f9eSMugunthan V N int slave_port = cpsw_get_slave_port(priv, \ 535d9ba8f9eSMugunthan V N slave->slave_num); \ 536d9ba8f9eSMugunthan V N cpsw_ale_add_mcast(priv->ale, addr, \ 537d9ba8f9eSMugunthan V N 1 << slave_port | 1 << priv->host_port, \ 538d9ba8f9eSMugunthan V N ALE_VLAN, slave->port_vlan, 0); \ 539d9ba8f9eSMugunthan V N } else { \ 540d9ba8f9eSMugunthan V N cpsw_ale_add_mcast(priv->ale, addr, \ 541d9ba8f9eSMugunthan V N ALE_ALL_PORTS << priv->host_port, \ 542d9ba8f9eSMugunthan V N 0, 0, 0); \ 543d9ba8f9eSMugunthan V N } \ 544d9ba8f9eSMugunthan V N } while (0) 545d9ba8f9eSMugunthan V N 546d9ba8f9eSMugunthan V N static inline int cpsw_get_slave_port(struct cpsw_priv *priv, u32 slave_num) 547d9ba8f9eSMugunthan V N { 548d9ba8f9eSMugunthan V N if (priv->host_port == 0) 549d9ba8f9eSMugunthan V N return slave_num + 1; 550d9ba8f9eSMugunthan V N else 551d9ba8f9eSMugunthan V N return slave_num; 552d9ba8f9eSMugunthan V N } 553df828598SMugunthan V N 5540cd8f9ccSMugunthan V N static void cpsw_set_promiscious(struct net_device *ndev, bool enable) 5550cd8f9ccSMugunthan V N { 5560cd8f9ccSMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 5570cd8f9ccSMugunthan V N struct cpsw_ale *ale = priv->ale; 5580cd8f9ccSMugunthan V N int i; 5590cd8f9ccSMugunthan V N 5600cd8f9ccSMugunthan V N if (priv->data.dual_emac) { 5610cd8f9ccSMugunthan V N bool flag = false; 5620cd8f9ccSMugunthan V N 5630cd8f9ccSMugunthan V N /* Enabling promiscuous mode for one interface will be 5640cd8f9ccSMugunthan V N * common for both the interface as the interface shares 5650cd8f9ccSMugunthan V N * the same hardware resource. 5660cd8f9ccSMugunthan V N */ 5670d961b3bSHeiko Schocher for (i = 0; i < priv->data.slaves; i++) 5680cd8f9ccSMugunthan V N if (priv->slaves[i].ndev->flags & IFF_PROMISC) 5690cd8f9ccSMugunthan V N flag = true; 5700cd8f9ccSMugunthan V N 5710cd8f9ccSMugunthan V N if (!enable && flag) { 5720cd8f9ccSMugunthan V N enable = true; 5730cd8f9ccSMugunthan V N dev_err(&ndev->dev, "promiscuity not disabled as the other interface is still in promiscuity mode\n"); 5740cd8f9ccSMugunthan V N } 5750cd8f9ccSMugunthan V N 5760cd8f9ccSMugunthan V N if (enable) { 5770cd8f9ccSMugunthan V N /* Enable Bypass */ 5780cd8f9ccSMugunthan V N cpsw_ale_control_set(ale, 0, ALE_BYPASS, 1); 5790cd8f9ccSMugunthan V N 5800cd8f9ccSMugunthan V N dev_dbg(&ndev->dev, "promiscuity enabled\n"); 5810cd8f9ccSMugunthan V N } else { 5820cd8f9ccSMugunthan V N /* Disable Bypass */ 5830cd8f9ccSMugunthan V N cpsw_ale_control_set(ale, 0, ALE_BYPASS, 0); 5840cd8f9ccSMugunthan V N dev_dbg(&ndev->dev, "promiscuity disabled\n"); 5850cd8f9ccSMugunthan V N } 5860cd8f9ccSMugunthan V N } else { 5870cd8f9ccSMugunthan V N if (enable) { 5880cd8f9ccSMugunthan V N unsigned long timeout = jiffies + HZ; 5890cd8f9ccSMugunthan V N 5900cd8f9ccSMugunthan V N /* Disable Learn for all ports */ 5910d961b3bSHeiko Schocher for (i = 0; i < priv->data.slaves; i++) { 5920cd8f9ccSMugunthan V N cpsw_ale_control_set(ale, i, 5930cd8f9ccSMugunthan V N ALE_PORT_NOLEARN, 1); 5940cd8f9ccSMugunthan V N cpsw_ale_control_set(ale, i, 5950cd8f9ccSMugunthan V N ALE_PORT_NO_SA_UPDATE, 1); 5960cd8f9ccSMugunthan V N } 5970cd8f9ccSMugunthan V N 5980cd8f9ccSMugunthan V N /* Clear All Untouched entries */ 5990cd8f9ccSMugunthan V N cpsw_ale_control_set(ale, 0, ALE_AGEOUT, 1); 6000cd8f9ccSMugunthan V N do { 6010cd8f9ccSMugunthan V N cpu_relax(); 6020cd8f9ccSMugunthan V N if (cpsw_ale_control_get(ale, 0, ALE_AGEOUT)) 6030cd8f9ccSMugunthan V N break; 6040cd8f9ccSMugunthan V N } while (time_after(timeout, jiffies)); 6050cd8f9ccSMugunthan V N cpsw_ale_control_set(ale, 0, ALE_AGEOUT, 1); 6060cd8f9ccSMugunthan V N 6070cd8f9ccSMugunthan V N /* Clear all mcast from ALE */ 6080cd8f9ccSMugunthan V N cpsw_ale_flush_multicast(ale, ALE_ALL_PORTS << 6090cd8f9ccSMugunthan V N priv->host_port); 6100cd8f9ccSMugunthan V N 6110cd8f9ccSMugunthan V N /* Flood All Unicast Packets to Host port */ 6120cd8f9ccSMugunthan V N cpsw_ale_control_set(ale, 0, ALE_P0_UNI_FLOOD, 1); 6130cd8f9ccSMugunthan V N dev_dbg(&ndev->dev, "promiscuity enabled\n"); 6140cd8f9ccSMugunthan V N } else { 6150cd8f9ccSMugunthan V N /* Flood All Unicast Packets to Host port */ 6160cd8f9ccSMugunthan V N cpsw_ale_control_set(ale, 0, ALE_P0_UNI_FLOOD, 0); 6170cd8f9ccSMugunthan V N 6180cd8f9ccSMugunthan V N /* Enable Learn for all ports */ 6190d961b3bSHeiko Schocher for (i = 0; i < priv->data.slaves; i++) { 6200cd8f9ccSMugunthan V N cpsw_ale_control_set(ale, i, 6210cd8f9ccSMugunthan V N ALE_PORT_NOLEARN, 0); 6220cd8f9ccSMugunthan V N cpsw_ale_control_set(ale, i, 6230cd8f9ccSMugunthan V N ALE_PORT_NO_SA_UPDATE, 0); 6240cd8f9ccSMugunthan V N } 6250cd8f9ccSMugunthan V N dev_dbg(&ndev->dev, "promiscuity disabled\n"); 6260cd8f9ccSMugunthan V N } 6270cd8f9ccSMugunthan V N } 6280cd8f9ccSMugunthan V N } 6290cd8f9ccSMugunthan V N 6305c50a856SMugunthan V N static void cpsw_ndo_set_rx_mode(struct net_device *ndev) 6315c50a856SMugunthan V N { 6325c50a856SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 6335c50a856SMugunthan V N 6345c50a856SMugunthan V N if (ndev->flags & IFF_PROMISC) { 6355c50a856SMugunthan V N /* Enable promiscuous mode */ 6360cd8f9ccSMugunthan V N cpsw_set_promiscious(ndev, true); 6375c50a856SMugunthan V N return; 6380cd8f9ccSMugunthan V N } else { 6390cd8f9ccSMugunthan V N /* Disable promiscuous mode */ 6400cd8f9ccSMugunthan V N cpsw_set_promiscious(ndev, false); 6415c50a856SMugunthan V N } 6425c50a856SMugunthan V N 6435c50a856SMugunthan V N /* Clear all mcast from ALE */ 6445c50a856SMugunthan V N cpsw_ale_flush_multicast(priv->ale, ALE_ALL_PORTS << priv->host_port); 6455c50a856SMugunthan V N 6465c50a856SMugunthan V N if (!netdev_mc_empty(ndev)) { 6475c50a856SMugunthan V N struct netdev_hw_addr *ha; 6485c50a856SMugunthan V N 6495c50a856SMugunthan V N /* program multicast address list into ALE register */ 6505c50a856SMugunthan V N netdev_for_each_mc_addr(ha, ndev) { 651d9ba8f9eSMugunthan V N cpsw_add_mcast(priv, (u8 *)ha->addr); 6525c50a856SMugunthan V N } 6535c50a856SMugunthan V N } 6545c50a856SMugunthan V N } 6555c50a856SMugunthan V N 656df828598SMugunthan V N static void cpsw_intr_enable(struct cpsw_priv *priv) 657df828598SMugunthan V N { 658996a5c27SRichard Cochran __raw_writel(0xFF, &priv->wr_regs->tx_en); 659996a5c27SRichard Cochran __raw_writel(0xFF, &priv->wr_regs->rx_en); 660df828598SMugunthan V N 661df828598SMugunthan V N cpdma_ctlr_int_ctrl(priv->dma, true); 662df828598SMugunthan V N return; 663df828598SMugunthan V N } 664df828598SMugunthan V N 665df828598SMugunthan V N static void cpsw_intr_disable(struct cpsw_priv *priv) 666df828598SMugunthan V N { 667996a5c27SRichard Cochran __raw_writel(0, &priv->wr_regs->tx_en); 668996a5c27SRichard Cochran __raw_writel(0, &priv->wr_regs->rx_en); 669df828598SMugunthan V N 670df828598SMugunthan V N cpdma_ctlr_int_ctrl(priv->dma, false); 671df828598SMugunthan V N return; 672df828598SMugunthan V N } 673df828598SMugunthan V N 6741a3b5056SOlof Johansson static void cpsw_tx_handler(void *token, int len, int status) 675df828598SMugunthan V N { 676df828598SMugunthan V N struct sk_buff *skb = token; 677df828598SMugunthan V N struct net_device *ndev = skb->dev; 678df828598SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 679df828598SMugunthan V N 680fae50823SMugunthan V N /* Check whether the queue is stopped due to stalled tx dma, if the 681fae50823SMugunthan V N * queue is stopped then start the queue as we have free desc for tx 682fae50823SMugunthan V N */ 683df828598SMugunthan V N if (unlikely(netif_queue_stopped(ndev))) 684b56d6b3fSMugunthan V N netif_wake_queue(ndev); 6859232b16dSMugunthan V N cpts_tx_timestamp(priv->cpts, skb); 6868dc43ddcSTobias Klauser ndev->stats.tx_packets++; 6878dc43ddcSTobias Klauser ndev->stats.tx_bytes += len; 688df828598SMugunthan V N dev_kfree_skb_any(skb); 689df828598SMugunthan V N } 690df828598SMugunthan V N 6911a3b5056SOlof Johansson static void cpsw_rx_handler(void *token, int len, int status) 692df828598SMugunthan V N { 693df828598SMugunthan V N struct sk_buff *skb = token; 694b4727e69SSebastian Siewior struct sk_buff *new_skb; 695df828598SMugunthan V N struct net_device *ndev = skb->dev; 696df828598SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 697df828598SMugunthan V N int ret = 0; 698df828598SMugunthan V N 699d9ba8f9eSMugunthan V N cpsw_dual_emac_src_port_detect(status, priv, ndev, skb); 700d9ba8f9eSMugunthan V N 70116e5c57dSMugunthan V N if (unlikely(status < 0) || unlikely(!netif_running(ndev))) { 702b4727e69SSebastian Siewior /* the interface is going down, skbs are purged */ 703df828598SMugunthan V N dev_kfree_skb_any(skb); 704df828598SMugunthan V N return; 705df828598SMugunthan V N } 706b4727e69SSebastian Siewior 707b4727e69SSebastian Siewior new_skb = netdev_alloc_skb_ip_align(ndev, priv->rx_packet_max); 708b4727e69SSebastian Siewior if (new_skb) { 709df828598SMugunthan V N skb_put(skb, len); 7109232b16dSMugunthan V N cpts_rx_timestamp(priv->cpts, skb); 711df828598SMugunthan V N skb->protocol = eth_type_trans(skb, ndev); 712df828598SMugunthan V N netif_receive_skb(skb); 7138dc43ddcSTobias Klauser ndev->stats.rx_bytes += len; 7148dc43ddcSTobias Klauser ndev->stats.rx_packets++; 715b4727e69SSebastian Siewior } else { 7168dc43ddcSTobias Klauser ndev->stats.rx_dropped++; 717b4727e69SSebastian Siewior new_skb = skb; 718df828598SMugunthan V N } 719df828598SMugunthan V N 720b4727e69SSebastian Siewior ret = cpdma_chan_submit(priv->rxch, new_skb, new_skb->data, 721b4727e69SSebastian Siewior skb_tailroom(new_skb), 0); 722b4727e69SSebastian Siewior if (WARN_ON(ret < 0)) 723b4727e69SSebastian Siewior dev_kfree_skb_any(new_skb); 724df828598SMugunthan V N } 725df828598SMugunthan V N 726df828598SMugunthan V N static irqreturn_t cpsw_interrupt(int irq, void *dev_id) 727df828598SMugunthan V N { 728df828598SMugunthan V N struct cpsw_priv *priv = dev_id; 729fd51cf19SSebastian Siewior 730df828598SMugunthan V N cpsw_intr_disable(priv); 731a11fbba9SSebastian Siewior if (priv->irq_enabled == true) { 732df828598SMugunthan V N cpsw_disable_irq(priv); 733a11fbba9SSebastian Siewior priv->irq_enabled = false; 734a11fbba9SSebastian Siewior } 735fd51cf19SSebastian Siewior 736fd51cf19SSebastian Siewior if (netif_running(priv->ndev)) { 737df828598SMugunthan V N napi_schedule(&priv->napi); 738df828598SMugunthan V N return IRQ_HANDLED; 739df828598SMugunthan V N } 740df828598SMugunthan V N 741fd51cf19SSebastian Siewior priv = cpsw_get_slave_priv(priv, 1); 742fd51cf19SSebastian Siewior if (!priv) 743fd51cf19SSebastian Siewior return IRQ_NONE; 744fd51cf19SSebastian Siewior 745fd51cf19SSebastian Siewior if (netif_running(priv->ndev)) { 746fd51cf19SSebastian Siewior napi_schedule(&priv->napi); 747fd51cf19SSebastian Siewior return IRQ_HANDLED; 748fd51cf19SSebastian Siewior } 749fd51cf19SSebastian Siewior return IRQ_NONE; 750fd51cf19SSebastian Siewior } 751fd51cf19SSebastian Siewior 752df828598SMugunthan V N static int cpsw_poll(struct napi_struct *napi, int budget) 753df828598SMugunthan V N { 754df828598SMugunthan V N struct cpsw_priv *priv = napi_to_priv(napi); 755df828598SMugunthan V N int num_tx, num_rx; 756df828598SMugunthan V N 757df828598SMugunthan V N num_tx = cpdma_chan_process(priv->txch, 128); 758510a1e72SMugunthan V N if (num_tx) 759510a1e72SMugunthan V N cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_TX); 760510a1e72SMugunthan V N 761df828598SMugunthan V N num_rx = cpdma_chan_process(priv->rxch, budget); 762510a1e72SMugunthan V N if (num_rx < budget) { 763a11fbba9SSebastian Siewior struct cpsw_priv *prim_cpsw; 764a11fbba9SSebastian Siewior 765510a1e72SMugunthan V N napi_complete(napi); 766510a1e72SMugunthan V N cpsw_intr_enable(priv); 767510a1e72SMugunthan V N cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_RX); 768a11fbba9SSebastian Siewior prim_cpsw = cpsw_get_slave_priv(priv, 0); 769a11fbba9SSebastian Siewior if (prim_cpsw->irq_enabled == false) { 770a11fbba9SSebastian Siewior prim_cpsw->irq_enabled = true; 771af5c6df7SMugunthan V N cpsw_enable_irq(priv); 772a11fbba9SSebastian Siewior } 773510a1e72SMugunthan V N } 774df828598SMugunthan V N 775df828598SMugunthan V N if (num_rx || num_tx) 776df828598SMugunthan V N cpsw_dbg(priv, intr, "poll %d rx, %d tx pkts\n", 777df828598SMugunthan V N num_rx, num_tx); 778df828598SMugunthan V N 779df828598SMugunthan V N return num_rx; 780df828598SMugunthan V N } 781df828598SMugunthan V N 782df828598SMugunthan V N static inline void soft_reset(const char *module, void __iomem *reg) 783df828598SMugunthan V N { 784df828598SMugunthan V N unsigned long timeout = jiffies + HZ; 785df828598SMugunthan V N 786df828598SMugunthan V N __raw_writel(1, reg); 787df828598SMugunthan V N do { 788df828598SMugunthan V N cpu_relax(); 789df828598SMugunthan V N } while ((__raw_readl(reg) & 1) && time_after(timeout, jiffies)); 790df828598SMugunthan V N 791df828598SMugunthan V N WARN(__raw_readl(reg) & 1, "failed to soft-reset %s\n", module); 792df828598SMugunthan V N } 793df828598SMugunthan V N 794df828598SMugunthan V N #define mac_hi(mac) (((mac)[0] << 0) | ((mac)[1] << 8) | \ 795df828598SMugunthan V N ((mac)[2] << 16) | ((mac)[3] << 24)) 796df828598SMugunthan V N #define mac_lo(mac) (((mac)[4] << 0) | ((mac)[5] << 8)) 797df828598SMugunthan V N 798df828598SMugunthan V N static void cpsw_set_slave_mac(struct cpsw_slave *slave, 799df828598SMugunthan V N struct cpsw_priv *priv) 800df828598SMugunthan V N { 8019750a3adSRichard Cochran slave_write(slave, mac_hi(priv->mac_addr), SA_HI); 8029750a3adSRichard Cochran slave_write(slave, mac_lo(priv->mac_addr), SA_LO); 803df828598SMugunthan V N } 804df828598SMugunthan V N 805df828598SMugunthan V N static void _cpsw_adjust_link(struct cpsw_slave *slave, 806df828598SMugunthan V N struct cpsw_priv *priv, bool *link) 807df828598SMugunthan V N { 808df828598SMugunthan V N struct phy_device *phy = slave->phy; 809df828598SMugunthan V N u32 mac_control = 0; 810df828598SMugunthan V N u32 slave_port; 811df828598SMugunthan V N 812df828598SMugunthan V N if (!phy) 813df828598SMugunthan V N return; 814df828598SMugunthan V N 815df828598SMugunthan V N slave_port = cpsw_get_slave_port(priv, slave->slave_num); 816df828598SMugunthan V N 817df828598SMugunthan V N if (phy->link) { 818df828598SMugunthan V N mac_control = priv->data.mac_control; 819df828598SMugunthan V N 820df828598SMugunthan V N /* enable forwarding */ 821df828598SMugunthan V N cpsw_ale_control_set(priv->ale, slave_port, 822df828598SMugunthan V N ALE_PORT_STATE, ALE_PORT_STATE_FORWARD); 823df828598SMugunthan V N 824df828598SMugunthan V N if (phy->speed == 1000) 825df828598SMugunthan V N mac_control |= BIT(7); /* GIGABITEN */ 826df828598SMugunthan V N if (phy->duplex) 827df828598SMugunthan V N mac_control |= BIT(0); /* FULLDUPLEXEN */ 828342b7b74SDaniel Mack 829342b7b74SDaniel Mack /* set speed_in input in case RMII mode is used in 100Mbps */ 830342b7b74SDaniel Mack if (phy->speed == 100) 831342b7b74SDaniel Mack mac_control |= BIT(15); 832a81d8762SMugunthan V N else if (phy->speed == 10) 833a81d8762SMugunthan V N mac_control |= BIT(18); /* In Band mode */ 834342b7b74SDaniel Mack 835df828598SMugunthan V N *link = true; 836df828598SMugunthan V N } else { 837df828598SMugunthan V N mac_control = 0; 838df828598SMugunthan V N /* disable forwarding */ 839df828598SMugunthan V N cpsw_ale_control_set(priv->ale, slave_port, 840df828598SMugunthan V N ALE_PORT_STATE, ALE_PORT_STATE_DISABLE); 841df828598SMugunthan V N } 842df828598SMugunthan V N 843df828598SMugunthan V N if (mac_control != slave->mac_control) { 844df828598SMugunthan V N phy_print_status(phy); 845df828598SMugunthan V N __raw_writel(mac_control, &slave->sliver->mac_control); 846df828598SMugunthan V N } 847df828598SMugunthan V N 848df828598SMugunthan V N slave->mac_control = mac_control; 849df828598SMugunthan V N } 850df828598SMugunthan V N 851df828598SMugunthan V N static void cpsw_adjust_link(struct net_device *ndev) 852df828598SMugunthan V N { 853df828598SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 854df828598SMugunthan V N bool link = false; 855df828598SMugunthan V N 856df828598SMugunthan V N for_each_slave(priv, _cpsw_adjust_link, priv, &link); 857df828598SMugunthan V N 858df828598SMugunthan V N if (link) { 859df828598SMugunthan V N netif_carrier_on(ndev); 860df828598SMugunthan V N if (netif_running(ndev)) 861df828598SMugunthan V N netif_wake_queue(ndev); 862df828598SMugunthan V N } else { 863df828598SMugunthan V N netif_carrier_off(ndev); 864df828598SMugunthan V N netif_stop_queue(ndev); 865df828598SMugunthan V N } 866df828598SMugunthan V N } 867df828598SMugunthan V N 868ff5b8ef2SMugunthan V N static int cpsw_get_coalesce(struct net_device *ndev, 869ff5b8ef2SMugunthan V N struct ethtool_coalesce *coal) 870ff5b8ef2SMugunthan V N { 871ff5b8ef2SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 872ff5b8ef2SMugunthan V N 873ff5b8ef2SMugunthan V N coal->rx_coalesce_usecs = priv->coal_intvl; 874ff5b8ef2SMugunthan V N return 0; 875ff5b8ef2SMugunthan V N } 876ff5b8ef2SMugunthan V N 877ff5b8ef2SMugunthan V N static int cpsw_set_coalesce(struct net_device *ndev, 878ff5b8ef2SMugunthan V N struct ethtool_coalesce *coal) 879ff5b8ef2SMugunthan V N { 880ff5b8ef2SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 881ff5b8ef2SMugunthan V N u32 int_ctrl; 882ff5b8ef2SMugunthan V N u32 num_interrupts = 0; 883ff5b8ef2SMugunthan V N u32 prescale = 0; 884ff5b8ef2SMugunthan V N u32 addnl_dvdr = 1; 885ff5b8ef2SMugunthan V N u32 coal_intvl = 0; 886ff5b8ef2SMugunthan V N 887ff5b8ef2SMugunthan V N if (!coal->rx_coalesce_usecs) 888ff5b8ef2SMugunthan V N return -EINVAL; 889ff5b8ef2SMugunthan V N 890ff5b8ef2SMugunthan V N coal_intvl = coal->rx_coalesce_usecs; 891ff5b8ef2SMugunthan V N 892ff5b8ef2SMugunthan V N int_ctrl = readl(&priv->wr_regs->int_control); 893ff5b8ef2SMugunthan V N prescale = priv->bus_freq_mhz * 4; 894ff5b8ef2SMugunthan V N 895ff5b8ef2SMugunthan V N if (coal_intvl < CPSW_CMINTMIN_INTVL) 896ff5b8ef2SMugunthan V N coal_intvl = CPSW_CMINTMIN_INTVL; 897ff5b8ef2SMugunthan V N 898ff5b8ef2SMugunthan V N if (coal_intvl > CPSW_CMINTMAX_INTVL) { 899ff5b8ef2SMugunthan V N /* Interrupt pacer works with 4us Pulse, we can 900ff5b8ef2SMugunthan V N * throttle further by dilating the 4us pulse. 901ff5b8ef2SMugunthan V N */ 902ff5b8ef2SMugunthan V N addnl_dvdr = CPSW_INTPRESCALE_MASK / prescale; 903ff5b8ef2SMugunthan V N 904ff5b8ef2SMugunthan V N if (addnl_dvdr > 1) { 905ff5b8ef2SMugunthan V N prescale *= addnl_dvdr; 906ff5b8ef2SMugunthan V N if (coal_intvl > (CPSW_CMINTMAX_INTVL * addnl_dvdr)) 907ff5b8ef2SMugunthan V N coal_intvl = (CPSW_CMINTMAX_INTVL 908ff5b8ef2SMugunthan V N * addnl_dvdr); 909ff5b8ef2SMugunthan V N } else { 910ff5b8ef2SMugunthan V N addnl_dvdr = 1; 911ff5b8ef2SMugunthan V N coal_intvl = CPSW_CMINTMAX_INTVL; 912ff5b8ef2SMugunthan V N } 913ff5b8ef2SMugunthan V N } 914ff5b8ef2SMugunthan V N 915ff5b8ef2SMugunthan V N num_interrupts = (1000 * addnl_dvdr) / coal_intvl; 916ff5b8ef2SMugunthan V N writel(num_interrupts, &priv->wr_regs->rx_imax); 917ff5b8ef2SMugunthan V N writel(num_interrupts, &priv->wr_regs->tx_imax); 918ff5b8ef2SMugunthan V N 919ff5b8ef2SMugunthan V N int_ctrl |= CPSW_INTPACEEN; 920ff5b8ef2SMugunthan V N int_ctrl &= (~CPSW_INTPRESCALE_MASK); 921ff5b8ef2SMugunthan V N int_ctrl |= (prescale & CPSW_INTPRESCALE_MASK); 922ff5b8ef2SMugunthan V N writel(int_ctrl, &priv->wr_regs->int_control); 923ff5b8ef2SMugunthan V N 924ff5b8ef2SMugunthan V N cpsw_notice(priv, timer, "Set coalesce to %d usecs.\n", coal_intvl); 925ff5b8ef2SMugunthan V N if (priv->data.dual_emac) { 926ff5b8ef2SMugunthan V N int i; 927ff5b8ef2SMugunthan V N 928ff5b8ef2SMugunthan V N for (i = 0; i < priv->data.slaves; i++) { 929ff5b8ef2SMugunthan V N priv = netdev_priv(priv->slaves[i].ndev); 930ff5b8ef2SMugunthan V N priv->coal_intvl = coal_intvl; 931ff5b8ef2SMugunthan V N } 932ff5b8ef2SMugunthan V N } else { 933ff5b8ef2SMugunthan V N priv->coal_intvl = coal_intvl; 934ff5b8ef2SMugunthan V N } 935ff5b8ef2SMugunthan V N 936ff5b8ef2SMugunthan V N return 0; 937ff5b8ef2SMugunthan V N } 938ff5b8ef2SMugunthan V N 939d9718546SMugunthan V N static int cpsw_get_sset_count(struct net_device *ndev, int sset) 940d9718546SMugunthan V N { 941d9718546SMugunthan V N switch (sset) { 942d9718546SMugunthan V N case ETH_SS_STATS: 943d9718546SMugunthan V N return CPSW_STATS_LEN; 944d9718546SMugunthan V N default: 945d9718546SMugunthan V N return -EOPNOTSUPP; 946d9718546SMugunthan V N } 947d9718546SMugunthan V N } 948d9718546SMugunthan V N 949d9718546SMugunthan V N static void cpsw_get_strings(struct net_device *ndev, u32 stringset, u8 *data) 950d9718546SMugunthan V N { 951d9718546SMugunthan V N u8 *p = data; 952d9718546SMugunthan V N int i; 953d9718546SMugunthan V N 954d9718546SMugunthan V N switch (stringset) { 955d9718546SMugunthan V N case ETH_SS_STATS: 956d9718546SMugunthan V N for (i = 0; i < CPSW_STATS_LEN; i++) { 957d9718546SMugunthan V N memcpy(p, cpsw_gstrings_stats[i].stat_string, 958d9718546SMugunthan V N ETH_GSTRING_LEN); 959d9718546SMugunthan V N p += ETH_GSTRING_LEN; 960d9718546SMugunthan V N } 961d9718546SMugunthan V N break; 962d9718546SMugunthan V N } 963d9718546SMugunthan V N } 964d9718546SMugunthan V N 965d9718546SMugunthan V N static void cpsw_get_ethtool_stats(struct net_device *ndev, 966d9718546SMugunthan V N struct ethtool_stats *stats, u64 *data) 967d9718546SMugunthan V N { 968d9718546SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 969d9718546SMugunthan V N struct cpdma_chan_stats rx_stats; 970d9718546SMugunthan V N struct cpdma_chan_stats tx_stats; 971d9718546SMugunthan V N u32 val; 972d9718546SMugunthan V N u8 *p; 973d9718546SMugunthan V N int i; 974d9718546SMugunthan V N 975d9718546SMugunthan V N /* Collect Davinci CPDMA stats for Rx and Tx Channel */ 976d9718546SMugunthan V N cpdma_chan_get_stats(priv->rxch, &rx_stats); 977d9718546SMugunthan V N cpdma_chan_get_stats(priv->txch, &tx_stats); 978d9718546SMugunthan V N 979d9718546SMugunthan V N for (i = 0; i < CPSW_STATS_LEN; i++) { 980d9718546SMugunthan V N switch (cpsw_gstrings_stats[i].type) { 981d9718546SMugunthan V N case CPSW_STATS: 982d9718546SMugunthan V N val = readl(priv->hw_stats + 983d9718546SMugunthan V N cpsw_gstrings_stats[i].stat_offset); 984d9718546SMugunthan V N data[i] = val; 985d9718546SMugunthan V N break; 986d9718546SMugunthan V N 987d9718546SMugunthan V N case CPDMA_RX_STATS: 988d9718546SMugunthan V N p = (u8 *)&rx_stats + 989d9718546SMugunthan V N cpsw_gstrings_stats[i].stat_offset; 990d9718546SMugunthan V N data[i] = *(u32 *)p; 991d9718546SMugunthan V N break; 992d9718546SMugunthan V N 993d9718546SMugunthan V N case CPDMA_TX_STATS: 994d9718546SMugunthan V N p = (u8 *)&tx_stats + 995d9718546SMugunthan V N cpsw_gstrings_stats[i].stat_offset; 996d9718546SMugunthan V N data[i] = *(u32 *)p; 997d9718546SMugunthan V N break; 998d9718546SMugunthan V N } 999d9718546SMugunthan V N } 1000d9718546SMugunthan V N } 1001d9718546SMugunthan V N 1002df828598SMugunthan V N static inline int __show_stat(char *buf, int maxlen, const char *name, u32 val) 1003df828598SMugunthan V N { 1004df828598SMugunthan V N static char *leader = "........................................"; 1005df828598SMugunthan V N 1006df828598SMugunthan V N if (!val) 1007df828598SMugunthan V N return 0; 1008df828598SMugunthan V N else 1009df828598SMugunthan V N return snprintf(buf, maxlen, "%s %s %10d\n", name, 1010df828598SMugunthan V N leader + strlen(name), val); 1011df828598SMugunthan V N } 1012df828598SMugunthan V N 1013d9ba8f9eSMugunthan V N static int cpsw_common_res_usage_state(struct cpsw_priv *priv) 1014d9ba8f9eSMugunthan V N { 1015d9ba8f9eSMugunthan V N u32 i; 1016d9ba8f9eSMugunthan V N u32 usage_count = 0; 1017d9ba8f9eSMugunthan V N 1018d9ba8f9eSMugunthan V N if (!priv->data.dual_emac) 1019d9ba8f9eSMugunthan V N return 0; 1020d9ba8f9eSMugunthan V N 1021d9ba8f9eSMugunthan V N for (i = 0; i < priv->data.slaves; i++) 1022d9ba8f9eSMugunthan V N if (priv->slaves[i].open_stat) 1023d9ba8f9eSMugunthan V N usage_count++; 1024d9ba8f9eSMugunthan V N 1025d9ba8f9eSMugunthan V N return usage_count; 1026d9ba8f9eSMugunthan V N } 1027d9ba8f9eSMugunthan V N 1028d9ba8f9eSMugunthan V N static inline int cpsw_tx_packet_submit(struct net_device *ndev, 1029d9ba8f9eSMugunthan V N struct cpsw_priv *priv, struct sk_buff *skb) 1030d9ba8f9eSMugunthan V N { 1031d9ba8f9eSMugunthan V N if (!priv->data.dual_emac) 1032d9ba8f9eSMugunthan V N return cpdma_chan_submit(priv->txch, skb, skb->data, 1033aef614e1SSebastian Siewior skb->len, 0); 1034d9ba8f9eSMugunthan V N 1035d9ba8f9eSMugunthan V N if (ndev == cpsw_get_slave_ndev(priv, 0)) 1036d9ba8f9eSMugunthan V N return cpdma_chan_submit(priv->txch, skb, skb->data, 1037aef614e1SSebastian Siewior skb->len, 1); 1038d9ba8f9eSMugunthan V N else 1039d9ba8f9eSMugunthan V N return cpdma_chan_submit(priv->txch, skb, skb->data, 1040aef614e1SSebastian Siewior skb->len, 2); 1041d9ba8f9eSMugunthan V N } 1042d9ba8f9eSMugunthan V N 1043d9ba8f9eSMugunthan V N static inline void cpsw_add_dual_emac_def_ale_entries( 1044d9ba8f9eSMugunthan V N struct cpsw_priv *priv, struct cpsw_slave *slave, 1045d9ba8f9eSMugunthan V N u32 slave_port) 1046d9ba8f9eSMugunthan V N { 1047d9ba8f9eSMugunthan V N u32 port_mask = 1 << slave_port | 1 << priv->host_port; 1048d9ba8f9eSMugunthan V N 1049d9ba8f9eSMugunthan V N if (priv->version == CPSW_VERSION_1) 1050d9ba8f9eSMugunthan V N slave_write(slave, slave->port_vlan, CPSW1_PORT_VLAN); 1051d9ba8f9eSMugunthan V N else 1052d9ba8f9eSMugunthan V N slave_write(slave, slave->port_vlan, CPSW2_PORT_VLAN); 1053d9ba8f9eSMugunthan V N cpsw_ale_add_vlan(priv->ale, slave->port_vlan, port_mask, 1054d9ba8f9eSMugunthan V N port_mask, port_mask, 0); 1055d9ba8f9eSMugunthan V N cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast, 1056d9ba8f9eSMugunthan V N port_mask, ALE_VLAN, slave->port_vlan, 0); 1057d9ba8f9eSMugunthan V N cpsw_ale_add_ucast(priv->ale, priv->mac_addr, 1058d9ba8f9eSMugunthan V N priv->host_port, ALE_VLAN, slave->port_vlan); 1059d9ba8f9eSMugunthan V N } 1060d9ba8f9eSMugunthan V N 10611e7a2e21SDaniel Mack static void soft_reset_slave(struct cpsw_slave *slave) 1062df828598SMugunthan V N { 1063df828598SMugunthan V N char name[32]; 10641e7a2e21SDaniel Mack 10651e7a2e21SDaniel Mack snprintf(name, sizeof(name), "slave-%d", slave->slave_num); 10661e7a2e21SDaniel Mack soft_reset(name, &slave->sliver->soft_reset); 10671e7a2e21SDaniel Mack } 10681e7a2e21SDaniel Mack 10691e7a2e21SDaniel Mack static void cpsw_slave_open(struct cpsw_slave *slave, struct cpsw_priv *priv) 10701e7a2e21SDaniel Mack { 1071df828598SMugunthan V N u32 slave_port; 1072df828598SMugunthan V N 10731e7a2e21SDaniel Mack soft_reset_slave(slave); 1074df828598SMugunthan V N 1075df828598SMugunthan V N /* setup priority mapping */ 1076df828598SMugunthan V N __raw_writel(RX_PRIORITY_MAPPING, &slave->sliver->rx_pri_map); 10779750a3adSRichard Cochran 10789750a3adSRichard Cochran switch (priv->version) { 10799750a3adSRichard Cochran case CPSW_VERSION_1: 10809750a3adSRichard Cochran slave_write(slave, TX_PRIORITY_MAPPING, CPSW1_TX_PRI_MAP); 10819750a3adSRichard Cochran break; 10829750a3adSRichard Cochran case CPSW_VERSION_2: 1083c193f365SMugunthan V N case CPSW_VERSION_3: 1084926489beSMugunthan V N case CPSW_VERSION_4: 10859750a3adSRichard Cochran slave_write(slave, TX_PRIORITY_MAPPING, CPSW2_TX_PRI_MAP); 10869750a3adSRichard Cochran break; 10879750a3adSRichard Cochran } 1088df828598SMugunthan V N 1089df828598SMugunthan V N /* setup max packet size, and mac address */ 1090df828598SMugunthan V N __raw_writel(priv->rx_packet_max, &slave->sliver->rx_maxlen); 1091df828598SMugunthan V N cpsw_set_slave_mac(slave, priv); 1092df828598SMugunthan V N 1093df828598SMugunthan V N slave->mac_control = 0; /* no link yet */ 1094df828598SMugunthan V N 1095df828598SMugunthan V N slave_port = cpsw_get_slave_port(priv, slave->slave_num); 1096df828598SMugunthan V N 1097d9ba8f9eSMugunthan V N if (priv->data.dual_emac) 1098d9ba8f9eSMugunthan V N cpsw_add_dual_emac_def_ale_entries(priv, slave, slave_port); 1099d9ba8f9eSMugunthan V N else 1100df828598SMugunthan V N cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast, 1101e11b220fSMugunthan V N 1 << slave_port, 0, 0, ALE_MCAST_FWD_2); 1102df828598SMugunthan V N 1103df828598SMugunthan V N slave->phy = phy_connect(priv->ndev, slave->data->phy_id, 1104f9a8f83bSFlorian Fainelli &cpsw_adjust_link, slave->data->phy_if); 1105df828598SMugunthan V N if (IS_ERR(slave->phy)) { 1106df828598SMugunthan V N dev_err(priv->dev, "phy %s not found on slave %d\n", 1107df828598SMugunthan V N slave->data->phy_id, slave->slave_num); 1108df828598SMugunthan V N slave->phy = NULL; 1109df828598SMugunthan V N } else { 1110df828598SMugunthan V N dev_info(priv->dev, "phy found : id is : 0x%x\n", 1111df828598SMugunthan V N slave->phy->phy_id); 1112df828598SMugunthan V N phy_start(slave->phy); 1113388367a5SMugunthan V N 1114388367a5SMugunthan V N /* Configure GMII_SEL register */ 1115388367a5SMugunthan V N cpsw_phy_sel(&priv->pdev->dev, slave->phy->interface, 1116388367a5SMugunthan V N slave->slave_num); 1117df828598SMugunthan V N } 1118df828598SMugunthan V N } 1119df828598SMugunthan V N 11203b72c2feSMugunthan V N static inline void cpsw_add_default_vlan(struct cpsw_priv *priv) 11213b72c2feSMugunthan V N { 11223b72c2feSMugunthan V N const int vlan = priv->data.default_vlan; 11233b72c2feSMugunthan V N const int port = priv->host_port; 11243b72c2feSMugunthan V N u32 reg; 11253b72c2feSMugunthan V N int i; 11263b72c2feSMugunthan V N 11273b72c2feSMugunthan V N reg = (priv->version == CPSW_VERSION_1) ? CPSW1_PORT_VLAN : 11283b72c2feSMugunthan V N CPSW2_PORT_VLAN; 11293b72c2feSMugunthan V N 11303b72c2feSMugunthan V N writel(vlan, &priv->host_port_regs->port_vlan); 11313b72c2feSMugunthan V N 11320237c110SDaniel Mack for (i = 0; i < priv->data.slaves; i++) 11333b72c2feSMugunthan V N slave_write(priv->slaves + i, vlan, reg); 11343b72c2feSMugunthan V N 11353b72c2feSMugunthan V N cpsw_ale_add_vlan(priv->ale, vlan, ALE_ALL_PORTS << port, 11363b72c2feSMugunthan V N ALE_ALL_PORTS << port, ALE_ALL_PORTS << port, 11373b72c2feSMugunthan V N (ALE_PORT_1 | ALE_PORT_2) << port); 11383b72c2feSMugunthan V N } 11393b72c2feSMugunthan V N 1140df828598SMugunthan V N static void cpsw_init_host_port(struct cpsw_priv *priv) 1141df828598SMugunthan V N { 11423b72c2feSMugunthan V N u32 control_reg; 1143d9ba8f9eSMugunthan V N u32 fifo_mode; 11443b72c2feSMugunthan V N 1145df828598SMugunthan V N /* soft reset the controller and initialize ale */ 1146df828598SMugunthan V N soft_reset("cpsw", &priv->regs->soft_reset); 1147df828598SMugunthan V N cpsw_ale_start(priv->ale); 1148df828598SMugunthan V N 1149df828598SMugunthan V N /* switch to vlan unaware mode */ 11503b72c2feSMugunthan V N cpsw_ale_control_set(priv->ale, priv->host_port, ALE_VLAN_AWARE, 11513b72c2feSMugunthan V N CPSW_ALE_VLAN_AWARE); 11523b72c2feSMugunthan V N control_reg = readl(&priv->regs->control); 11533b72c2feSMugunthan V N control_reg |= CPSW_VLAN_AWARE; 11543b72c2feSMugunthan V N writel(control_reg, &priv->regs->control); 1155d9ba8f9eSMugunthan V N fifo_mode = (priv->data.dual_emac) ? CPSW_FIFO_DUAL_MAC_MODE : 1156d9ba8f9eSMugunthan V N CPSW_FIFO_NORMAL_MODE; 1157d9ba8f9eSMugunthan V N writel(fifo_mode, &priv->host_port_regs->tx_in_ctl); 1158df828598SMugunthan V N 1159df828598SMugunthan V N /* setup host port priority mapping */ 1160df828598SMugunthan V N __raw_writel(CPDMA_TX_PRIORITY_MAP, 1161df828598SMugunthan V N &priv->host_port_regs->cpdma_tx_pri_map); 1162df828598SMugunthan V N __raw_writel(0, &priv->host_port_regs->cpdma_rx_chan_map); 1163df828598SMugunthan V N 1164df828598SMugunthan V N cpsw_ale_control_set(priv->ale, priv->host_port, 1165df828598SMugunthan V N ALE_PORT_STATE, ALE_PORT_STATE_FORWARD); 1166df828598SMugunthan V N 1167d9ba8f9eSMugunthan V N if (!priv->data.dual_emac) { 1168d9ba8f9eSMugunthan V N cpsw_ale_add_ucast(priv->ale, priv->mac_addr, priv->host_port, 1169d9ba8f9eSMugunthan V N 0, 0); 1170df828598SMugunthan V N cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast, 1171e11b220fSMugunthan V N 1 << priv->host_port, 0, 0, ALE_MCAST_FWD_2); 1172df828598SMugunthan V N } 1173d9ba8f9eSMugunthan V N } 1174df828598SMugunthan V N 1175aacebbf8SSebastian Siewior static void cpsw_slave_stop(struct cpsw_slave *slave, struct cpsw_priv *priv) 1176aacebbf8SSebastian Siewior { 11773995d265SSchuyler Patton u32 slave_port; 11783995d265SSchuyler Patton 11793995d265SSchuyler Patton slave_port = cpsw_get_slave_port(priv, slave->slave_num); 11803995d265SSchuyler Patton 1181aacebbf8SSebastian Siewior if (!slave->phy) 1182aacebbf8SSebastian Siewior return; 1183aacebbf8SSebastian Siewior phy_stop(slave->phy); 1184aacebbf8SSebastian Siewior phy_disconnect(slave->phy); 1185aacebbf8SSebastian Siewior slave->phy = NULL; 11863995d265SSchuyler Patton cpsw_ale_control_set(priv->ale, slave_port, 11873995d265SSchuyler Patton ALE_PORT_STATE, ALE_PORT_STATE_DISABLE); 1188aacebbf8SSebastian Siewior } 1189aacebbf8SSebastian Siewior 1190df828598SMugunthan V N static int cpsw_ndo_open(struct net_device *ndev) 1191df828598SMugunthan V N { 1192df828598SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 1193a11fbba9SSebastian Siewior struct cpsw_priv *prim_cpsw; 1194df828598SMugunthan V N int i, ret; 1195df828598SMugunthan V N u32 reg; 1196df828598SMugunthan V N 1197d9ba8f9eSMugunthan V N if (!cpsw_common_res_usage_state(priv)) 1198df828598SMugunthan V N cpsw_intr_disable(priv); 1199df828598SMugunthan V N netif_carrier_off(ndev); 1200df828598SMugunthan V N 1201f150bd7fSMugunthan V N pm_runtime_get_sync(&priv->pdev->dev); 1202df828598SMugunthan V N 1203549985eeSRichard Cochran reg = priv->version; 1204df828598SMugunthan V N 1205df828598SMugunthan V N dev_info(priv->dev, "initializing cpsw version %d.%d (%d)\n", 1206df828598SMugunthan V N CPSW_MAJOR_VERSION(reg), CPSW_MINOR_VERSION(reg), 1207df828598SMugunthan V N CPSW_RTL_VERSION(reg)); 1208df828598SMugunthan V N 1209df828598SMugunthan V N /* initialize host and slave ports */ 1210d9ba8f9eSMugunthan V N if (!cpsw_common_res_usage_state(priv)) 1211df828598SMugunthan V N cpsw_init_host_port(priv); 1212df828598SMugunthan V N for_each_slave(priv, cpsw_slave_open, priv); 1213df828598SMugunthan V N 12143b72c2feSMugunthan V N /* Add default VLAN */ 12153b72c2feSMugunthan V N cpsw_add_default_vlan(priv); 12163b72c2feSMugunthan V N 1217d9ba8f9eSMugunthan V N if (!cpsw_common_res_usage_state(priv)) { 1218df828598SMugunthan V N /* setup tx dma to fixed prio and zero offset */ 1219df828598SMugunthan V N cpdma_control_set(priv->dma, CPDMA_TX_PRIO_FIXED, 1); 1220df828598SMugunthan V N cpdma_control_set(priv->dma, CPDMA_RX_BUFFER_OFFSET, 0); 1221df828598SMugunthan V N 1222d9ba8f9eSMugunthan V N /* disable priority elevation */ 1223df828598SMugunthan V N __raw_writel(0, &priv->regs->ptype); 1224df828598SMugunthan V N 1225d9ba8f9eSMugunthan V N /* enable statistics collection only on all ports */ 1226df828598SMugunthan V N __raw_writel(0x7, &priv->regs->stat_port_en); 1227df828598SMugunthan V N 1228df828598SMugunthan V N if (WARN_ON(!priv->data.rx_descs)) 1229df828598SMugunthan V N priv->data.rx_descs = 128; 1230df828598SMugunthan V N 1231df828598SMugunthan V N for (i = 0; i < priv->data.rx_descs; i++) { 1232df828598SMugunthan V N struct sk_buff *skb; 1233df828598SMugunthan V N 1234df828598SMugunthan V N ret = -ENOMEM; 1235aacebbf8SSebastian Siewior skb = __netdev_alloc_skb_ip_align(priv->ndev, 1236aacebbf8SSebastian Siewior priv->rx_packet_max, GFP_KERNEL); 1237df828598SMugunthan V N if (!skb) 1238aacebbf8SSebastian Siewior goto err_cleanup; 1239df828598SMugunthan V N ret = cpdma_chan_submit(priv->rxch, skb, skb->data, 1240aef614e1SSebastian Siewior skb_tailroom(skb), 0); 1241aacebbf8SSebastian Siewior if (ret < 0) { 1242aacebbf8SSebastian Siewior kfree_skb(skb); 1243aacebbf8SSebastian Siewior goto err_cleanup; 1244aacebbf8SSebastian Siewior } 1245df828598SMugunthan V N } 1246d9ba8f9eSMugunthan V N /* continue even if we didn't manage to submit all 1247d9ba8f9eSMugunthan V N * receive descs 1248d9ba8f9eSMugunthan V N */ 1249df828598SMugunthan V N cpsw_info(priv, ifup, "submitted %d rx descriptors\n", i); 1250f280e89aSMugunthan V N 1251f280e89aSMugunthan V N if (cpts_register(&priv->pdev->dev, priv->cpts, 1252f280e89aSMugunthan V N priv->data.cpts_clock_mult, 1253f280e89aSMugunthan V N priv->data.cpts_clock_shift)) 1254f280e89aSMugunthan V N dev_err(priv->dev, "error registering cpts device\n"); 1255f280e89aSMugunthan V N 1256d9ba8f9eSMugunthan V N } 1257df828598SMugunthan V N 1258ff5b8ef2SMugunthan V N /* Enable Interrupt pacing if configured */ 1259ff5b8ef2SMugunthan V N if (priv->coal_intvl != 0) { 1260ff5b8ef2SMugunthan V N struct ethtool_coalesce coal; 1261ff5b8ef2SMugunthan V N 1262ff5b8ef2SMugunthan V N coal.rx_coalesce_usecs = (priv->coal_intvl << 4); 1263ff5b8ef2SMugunthan V N cpsw_set_coalesce(ndev, &coal); 1264ff5b8ef2SMugunthan V N } 1265ff5b8ef2SMugunthan V N 1266f63a975eSMugunthan V N napi_enable(&priv->napi); 1267f63a975eSMugunthan V N cpdma_ctlr_start(priv->dma); 1268f63a975eSMugunthan V N cpsw_intr_enable(priv); 1269f63a975eSMugunthan V N cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_RX); 1270f63a975eSMugunthan V N cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_TX); 1271f63a975eSMugunthan V N 1272a11fbba9SSebastian Siewior prim_cpsw = cpsw_get_slave_priv(priv, 0); 1273a11fbba9SSebastian Siewior if (prim_cpsw->irq_enabled == false) { 1274a11fbba9SSebastian Siewior if ((priv == prim_cpsw) || !netif_running(prim_cpsw->ndev)) { 1275a11fbba9SSebastian Siewior prim_cpsw->irq_enabled = true; 1276a11fbba9SSebastian Siewior cpsw_enable_irq(prim_cpsw); 1277a11fbba9SSebastian Siewior } 1278a11fbba9SSebastian Siewior } 1279a11fbba9SSebastian Siewior 1280d9ba8f9eSMugunthan V N if (priv->data.dual_emac) 1281d9ba8f9eSMugunthan V N priv->slaves[priv->emac_port].open_stat = true; 1282df828598SMugunthan V N return 0; 1283df828598SMugunthan V N 1284aacebbf8SSebastian Siewior err_cleanup: 1285aacebbf8SSebastian Siewior cpdma_ctlr_stop(priv->dma); 1286aacebbf8SSebastian Siewior for_each_slave(priv, cpsw_slave_stop, priv); 1287aacebbf8SSebastian Siewior pm_runtime_put_sync(&priv->pdev->dev); 1288aacebbf8SSebastian Siewior netif_carrier_off(priv->ndev); 1289aacebbf8SSebastian Siewior return ret; 1290df828598SMugunthan V N } 1291df828598SMugunthan V N 1292df828598SMugunthan V N static int cpsw_ndo_stop(struct net_device *ndev) 1293df828598SMugunthan V N { 1294df828598SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 1295df828598SMugunthan V N 1296df828598SMugunthan V N cpsw_info(priv, ifdown, "shutting down cpsw device\n"); 1297df828598SMugunthan V N netif_stop_queue(priv->ndev); 1298df828598SMugunthan V N napi_disable(&priv->napi); 1299df828598SMugunthan V N netif_carrier_off(priv->ndev); 1300d9ba8f9eSMugunthan V N 1301d9ba8f9eSMugunthan V N if (cpsw_common_res_usage_state(priv) <= 1) { 1302f280e89aSMugunthan V N cpts_unregister(priv->cpts); 130371380f9bSMugunthan V N cpsw_intr_disable(priv); 130471380f9bSMugunthan V N cpdma_ctlr_int_ctrl(priv->dma, false); 130571380f9bSMugunthan V N cpdma_ctlr_stop(priv->dma); 1306df828598SMugunthan V N cpsw_ale_stop(priv->ale); 1307d9ba8f9eSMugunthan V N } 1308df828598SMugunthan V N for_each_slave(priv, cpsw_slave_stop, priv); 1309f150bd7fSMugunthan V N pm_runtime_put_sync(&priv->pdev->dev); 1310d9ba8f9eSMugunthan V N if (priv->data.dual_emac) 1311d9ba8f9eSMugunthan V N priv->slaves[priv->emac_port].open_stat = false; 1312df828598SMugunthan V N return 0; 1313df828598SMugunthan V N } 1314df828598SMugunthan V N 1315df828598SMugunthan V N static netdev_tx_t cpsw_ndo_start_xmit(struct sk_buff *skb, 1316df828598SMugunthan V N struct net_device *ndev) 1317df828598SMugunthan V N { 1318df828598SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 1319df828598SMugunthan V N int ret; 1320df828598SMugunthan V N 1321df828598SMugunthan V N ndev->trans_start = jiffies; 1322df828598SMugunthan V N 1323df828598SMugunthan V N if (skb_padto(skb, CPSW_MIN_PACKET_SIZE)) { 1324df828598SMugunthan V N cpsw_err(priv, tx_err, "packet pad failed\n"); 13258dc43ddcSTobias Klauser ndev->stats.tx_dropped++; 1326df828598SMugunthan V N return NETDEV_TX_OK; 1327df828598SMugunthan V N } 1328df828598SMugunthan V N 13299232b16dSMugunthan V N if (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP && 13309232b16dSMugunthan V N priv->cpts->tx_enable) 13312e5b38abSRichard Cochran skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 13322e5b38abSRichard Cochran 13332e5b38abSRichard Cochran skb_tx_timestamp(skb); 13342e5b38abSRichard Cochran 1335d9ba8f9eSMugunthan V N ret = cpsw_tx_packet_submit(ndev, priv, skb); 1336df828598SMugunthan V N if (unlikely(ret != 0)) { 1337df828598SMugunthan V N cpsw_err(priv, tx_err, "desc submit failed\n"); 1338df828598SMugunthan V N goto fail; 1339df828598SMugunthan V N } 1340df828598SMugunthan V N 1341fae50823SMugunthan V N /* If there is no more tx desc left free then we need to 1342fae50823SMugunthan V N * tell the kernel to stop sending us tx frames. 1343fae50823SMugunthan V N */ 1344d35162f8SDaniel Mack if (unlikely(!cpdma_check_free_tx_desc(priv->txch))) 1345fae50823SMugunthan V N netif_stop_queue(ndev); 1346fae50823SMugunthan V N 1347df828598SMugunthan V N return NETDEV_TX_OK; 1348df828598SMugunthan V N fail: 13498dc43ddcSTobias Klauser ndev->stats.tx_dropped++; 1350df828598SMugunthan V N netif_stop_queue(ndev); 1351df828598SMugunthan V N return NETDEV_TX_BUSY; 1352df828598SMugunthan V N } 1353df828598SMugunthan V N 13542e5b38abSRichard Cochran #ifdef CONFIG_TI_CPTS 13552e5b38abSRichard Cochran 13562e5b38abSRichard Cochran static void cpsw_hwtstamp_v1(struct cpsw_priv *priv) 13572e5b38abSRichard Cochran { 1358e86ac13bSMugunthan V N struct cpsw_slave *slave = &priv->slaves[priv->data.active_slave]; 13592e5b38abSRichard Cochran u32 ts_en, seq_id; 13602e5b38abSRichard Cochran 13619232b16dSMugunthan V N if (!priv->cpts->tx_enable && !priv->cpts->rx_enable) { 13622e5b38abSRichard Cochran slave_write(slave, 0, CPSW1_TS_CTL); 13632e5b38abSRichard Cochran return; 13642e5b38abSRichard Cochran } 13652e5b38abSRichard Cochran 13662e5b38abSRichard Cochran seq_id = (30 << CPSW_V1_SEQ_ID_OFS_SHIFT) | ETH_P_1588; 13672e5b38abSRichard Cochran ts_en = EVENT_MSG_BITS << CPSW_V1_MSG_TYPE_OFS; 13682e5b38abSRichard Cochran 13699232b16dSMugunthan V N if (priv->cpts->tx_enable) 13702e5b38abSRichard Cochran ts_en |= CPSW_V1_TS_TX_EN; 13712e5b38abSRichard Cochran 13729232b16dSMugunthan V N if (priv->cpts->rx_enable) 13732e5b38abSRichard Cochran ts_en |= CPSW_V1_TS_RX_EN; 13742e5b38abSRichard Cochran 13752e5b38abSRichard Cochran slave_write(slave, ts_en, CPSW1_TS_CTL); 13762e5b38abSRichard Cochran slave_write(slave, seq_id, CPSW1_TS_SEQ_LTYPE); 13772e5b38abSRichard Cochran } 13782e5b38abSRichard Cochran 13792e5b38abSRichard Cochran static void cpsw_hwtstamp_v2(struct cpsw_priv *priv) 13802e5b38abSRichard Cochran { 1381d9ba8f9eSMugunthan V N struct cpsw_slave *slave; 13822e5b38abSRichard Cochran u32 ctrl, mtype; 13832e5b38abSRichard Cochran 1384d9ba8f9eSMugunthan V N if (priv->data.dual_emac) 1385d9ba8f9eSMugunthan V N slave = &priv->slaves[priv->emac_port]; 1386d9ba8f9eSMugunthan V N else 1387e86ac13bSMugunthan V N slave = &priv->slaves[priv->data.active_slave]; 1388d9ba8f9eSMugunthan V N 13892e5b38abSRichard Cochran ctrl = slave_read(slave, CPSW2_CONTROL); 139009c55372SGeorge Cherian switch (priv->version) { 139109c55372SGeorge Cherian case CPSW_VERSION_2: 139209c55372SGeorge Cherian ctrl &= ~CTRL_V2_ALL_TS_MASK; 13932e5b38abSRichard Cochran 13949232b16dSMugunthan V N if (priv->cpts->tx_enable) 139509c55372SGeorge Cherian ctrl |= CTRL_V2_TX_TS_BITS; 13962e5b38abSRichard Cochran 13979232b16dSMugunthan V N if (priv->cpts->rx_enable) 139809c55372SGeorge Cherian ctrl |= CTRL_V2_RX_TS_BITS; 139909c55372SGeorge Cherian break; 140009c55372SGeorge Cherian case CPSW_VERSION_3: 140109c55372SGeorge Cherian default: 140209c55372SGeorge Cherian ctrl &= ~CTRL_V3_ALL_TS_MASK; 140309c55372SGeorge Cherian 140409c55372SGeorge Cherian if (priv->cpts->tx_enable) 140509c55372SGeorge Cherian ctrl |= CTRL_V3_TX_TS_BITS; 140609c55372SGeorge Cherian 140709c55372SGeorge Cherian if (priv->cpts->rx_enable) 140809c55372SGeorge Cherian ctrl |= CTRL_V3_RX_TS_BITS; 140909c55372SGeorge Cherian break; 141009c55372SGeorge Cherian } 14112e5b38abSRichard Cochran 14122e5b38abSRichard Cochran mtype = (30 << TS_SEQ_ID_OFFSET_SHIFT) | EVENT_MSG_BITS; 14132e5b38abSRichard Cochran 14142e5b38abSRichard Cochran slave_write(slave, mtype, CPSW2_TS_SEQ_MTYPE); 14152e5b38abSRichard Cochran slave_write(slave, ctrl, CPSW2_CONTROL); 14162e5b38abSRichard Cochran __raw_writel(ETH_P_1588, &priv->regs->ts_ltype); 14172e5b38abSRichard Cochran } 14182e5b38abSRichard Cochran 1419a5b4145bSBen Hutchings static int cpsw_hwtstamp_set(struct net_device *dev, struct ifreq *ifr) 14202e5b38abSRichard Cochran { 14213177bf6fSMugunthan V N struct cpsw_priv *priv = netdev_priv(dev); 14229232b16dSMugunthan V N struct cpts *cpts = priv->cpts; 14232e5b38abSRichard Cochran struct hwtstamp_config cfg; 14242e5b38abSRichard Cochran 14252ee91e54SBen Hutchings if (priv->version != CPSW_VERSION_1 && 1426f7d403cbSGeorge Cherian priv->version != CPSW_VERSION_2 && 1427f7d403cbSGeorge Cherian priv->version != CPSW_VERSION_3) 14282ee91e54SBen Hutchings return -EOPNOTSUPP; 14292ee91e54SBen Hutchings 14302e5b38abSRichard Cochran if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg))) 14312e5b38abSRichard Cochran return -EFAULT; 14322e5b38abSRichard Cochran 14332e5b38abSRichard Cochran /* reserved for future extensions */ 14342e5b38abSRichard Cochran if (cfg.flags) 14352e5b38abSRichard Cochran return -EINVAL; 14362e5b38abSRichard Cochran 14372ee91e54SBen Hutchings if (cfg.tx_type != HWTSTAMP_TX_OFF && cfg.tx_type != HWTSTAMP_TX_ON) 14382e5b38abSRichard Cochran return -ERANGE; 14392e5b38abSRichard Cochran 14402e5b38abSRichard Cochran switch (cfg.rx_filter) { 14412e5b38abSRichard Cochran case HWTSTAMP_FILTER_NONE: 14422e5b38abSRichard Cochran cpts->rx_enable = 0; 14432e5b38abSRichard Cochran break; 14442e5b38abSRichard Cochran case HWTSTAMP_FILTER_ALL: 14452e5b38abSRichard Cochran case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: 14462e5b38abSRichard Cochran case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: 14472e5b38abSRichard Cochran case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: 14482e5b38abSRichard Cochran return -ERANGE; 14492e5b38abSRichard Cochran case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: 14502e5b38abSRichard Cochran case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 14512e5b38abSRichard Cochran case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 14522e5b38abSRichard Cochran case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: 14532e5b38abSRichard Cochran case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: 14542e5b38abSRichard Cochran case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: 14552e5b38abSRichard Cochran case HWTSTAMP_FILTER_PTP_V2_EVENT: 14562e5b38abSRichard Cochran case HWTSTAMP_FILTER_PTP_V2_SYNC: 14572e5b38abSRichard Cochran case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 14582e5b38abSRichard Cochran cpts->rx_enable = 1; 14592e5b38abSRichard Cochran cfg.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT; 14602e5b38abSRichard Cochran break; 14612e5b38abSRichard Cochran default: 14622e5b38abSRichard Cochran return -ERANGE; 14632e5b38abSRichard Cochran } 14642e5b38abSRichard Cochran 14652ee91e54SBen Hutchings cpts->tx_enable = cfg.tx_type == HWTSTAMP_TX_ON; 14662ee91e54SBen Hutchings 14672e5b38abSRichard Cochran switch (priv->version) { 14682e5b38abSRichard Cochran case CPSW_VERSION_1: 14692e5b38abSRichard Cochran cpsw_hwtstamp_v1(priv); 14702e5b38abSRichard Cochran break; 14712e5b38abSRichard Cochran case CPSW_VERSION_2: 1472f7d403cbSGeorge Cherian case CPSW_VERSION_3: 14732e5b38abSRichard Cochran cpsw_hwtstamp_v2(priv); 14742e5b38abSRichard Cochran break; 14752e5b38abSRichard Cochran default: 14762ee91e54SBen Hutchings WARN_ON(1); 14772e5b38abSRichard Cochran } 14782e5b38abSRichard Cochran 14792e5b38abSRichard Cochran return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0; 14802e5b38abSRichard Cochran } 14812e5b38abSRichard Cochran 1482a5b4145bSBen Hutchings static int cpsw_hwtstamp_get(struct net_device *dev, struct ifreq *ifr) 1483a5b4145bSBen Hutchings { 1484a5b4145bSBen Hutchings struct cpsw_priv *priv = netdev_priv(dev); 1485a5b4145bSBen Hutchings struct cpts *cpts = priv->cpts; 1486a5b4145bSBen Hutchings struct hwtstamp_config cfg; 1487a5b4145bSBen Hutchings 1488a5b4145bSBen Hutchings if (priv->version != CPSW_VERSION_1 && 1489f7d403cbSGeorge Cherian priv->version != CPSW_VERSION_2 && 1490f7d403cbSGeorge Cherian priv->version != CPSW_VERSION_3) 1491a5b4145bSBen Hutchings return -EOPNOTSUPP; 1492a5b4145bSBen Hutchings 1493a5b4145bSBen Hutchings cfg.flags = 0; 1494a5b4145bSBen Hutchings cfg.tx_type = cpts->tx_enable ? HWTSTAMP_TX_ON : HWTSTAMP_TX_OFF; 1495a5b4145bSBen Hutchings cfg.rx_filter = (cpts->rx_enable ? 1496a5b4145bSBen Hutchings HWTSTAMP_FILTER_PTP_V2_EVENT : HWTSTAMP_FILTER_NONE); 1497a5b4145bSBen Hutchings 1498a5b4145bSBen Hutchings return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0; 1499a5b4145bSBen Hutchings } 1500a5b4145bSBen Hutchings 15012e5b38abSRichard Cochran #endif /*CONFIG_TI_CPTS*/ 15022e5b38abSRichard Cochran 15032e5b38abSRichard Cochran static int cpsw_ndo_ioctl(struct net_device *dev, struct ifreq *req, int cmd) 15042e5b38abSRichard Cochran { 150511f2c988SMugunthan V N struct cpsw_priv *priv = netdev_priv(dev); 150611f2c988SMugunthan V N int slave_no = cpsw_slave_index(priv); 150711f2c988SMugunthan V N 15082e5b38abSRichard Cochran if (!netif_running(dev)) 15092e5b38abSRichard Cochran return -EINVAL; 15102e5b38abSRichard Cochran 151111f2c988SMugunthan V N switch (cmd) { 15122e5b38abSRichard Cochran #ifdef CONFIG_TI_CPTS 151311f2c988SMugunthan V N case SIOCSHWTSTAMP: 1514a5b4145bSBen Hutchings return cpsw_hwtstamp_set(dev, req); 1515a5b4145bSBen Hutchings case SIOCGHWTSTAMP: 1516a5b4145bSBen Hutchings return cpsw_hwtstamp_get(dev, req); 15172e5b38abSRichard Cochran #endif 15182e5b38abSRichard Cochran } 15192e5b38abSRichard Cochran 1520c1b59947SStefan Sørensen if (!priv->slaves[slave_no].phy) 1521c1b59947SStefan Sørensen return -EOPNOTSUPP; 1522c1b59947SStefan Sørensen return phy_mii_ioctl(priv->slaves[slave_no].phy, req, cmd); 152311f2c988SMugunthan V N } 152411f2c988SMugunthan V N 1525df828598SMugunthan V N static void cpsw_ndo_tx_timeout(struct net_device *ndev) 1526df828598SMugunthan V N { 1527df828598SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 1528df828598SMugunthan V N 1529df828598SMugunthan V N cpsw_err(priv, tx_err, "transmit timeout, restarting dma\n"); 15308dc43ddcSTobias Klauser ndev->stats.tx_errors++; 1531df828598SMugunthan V N cpsw_intr_disable(priv); 1532df828598SMugunthan V N cpdma_ctlr_int_ctrl(priv->dma, false); 1533df828598SMugunthan V N cpdma_chan_stop(priv->txch); 1534df828598SMugunthan V N cpdma_chan_start(priv->txch); 1535df828598SMugunthan V N cpdma_ctlr_int_ctrl(priv->dma, true); 1536df828598SMugunthan V N cpsw_intr_enable(priv); 1537510a1e72SMugunthan V N cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_RX); 1538510a1e72SMugunthan V N cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_TX); 1539510a1e72SMugunthan V N 1540df828598SMugunthan V N } 1541df828598SMugunthan V N 1542dcfd8d58SMugunthan V N static int cpsw_ndo_set_mac_address(struct net_device *ndev, void *p) 1543dcfd8d58SMugunthan V N { 1544dcfd8d58SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 1545dcfd8d58SMugunthan V N struct sockaddr *addr = (struct sockaddr *)p; 1546dcfd8d58SMugunthan V N int flags = 0; 1547dcfd8d58SMugunthan V N u16 vid = 0; 1548dcfd8d58SMugunthan V N 1549dcfd8d58SMugunthan V N if (!is_valid_ether_addr(addr->sa_data)) 1550dcfd8d58SMugunthan V N return -EADDRNOTAVAIL; 1551dcfd8d58SMugunthan V N 1552dcfd8d58SMugunthan V N if (priv->data.dual_emac) { 1553dcfd8d58SMugunthan V N vid = priv->slaves[priv->emac_port].port_vlan; 1554dcfd8d58SMugunthan V N flags = ALE_VLAN; 1555dcfd8d58SMugunthan V N } 1556dcfd8d58SMugunthan V N 1557dcfd8d58SMugunthan V N cpsw_ale_del_ucast(priv->ale, priv->mac_addr, priv->host_port, 1558dcfd8d58SMugunthan V N flags, vid); 1559dcfd8d58SMugunthan V N cpsw_ale_add_ucast(priv->ale, addr->sa_data, priv->host_port, 1560dcfd8d58SMugunthan V N flags, vid); 1561dcfd8d58SMugunthan V N 1562dcfd8d58SMugunthan V N memcpy(priv->mac_addr, addr->sa_data, ETH_ALEN); 1563dcfd8d58SMugunthan V N memcpy(ndev->dev_addr, priv->mac_addr, ETH_ALEN); 1564dcfd8d58SMugunthan V N for_each_slave(priv, cpsw_set_slave_mac, priv); 1565dcfd8d58SMugunthan V N 1566dcfd8d58SMugunthan V N return 0; 1567dcfd8d58SMugunthan V N } 1568dcfd8d58SMugunthan V N 1569df828598SMugunthan V N #ifdef CONFIG_NET_POLL_CONTROLLER 1570df828598SMugunthan V N static void cpsw_ndo_poll_controller(struct net_device *ndev) 1571df828598SMugunthan V N { 1572df828598SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 1573df828598SMugunthan V N 1574df828598SMugunthan V N cpsw_intr_disable(priv); 1575df828598SMugunthan V N cpdma_ctlr_int_ctrl(priv->dma, false); 1576df828598SMugunthan V N cpsw_interrupt(ndev->irq, priv); 1577df828598SMugunthan V N cpdma_ctlr_int_ctrl(priv->dma, true); 1578df828598SMugunthan V N cpsw_intr_enable(priv); 1579510a1e72SMugunthan V N cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_RX); 1580510a1e72SMugunthan V N cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_TX); 1581510a1e72SMugunthan V N 1582df828598SMugunthan V N } 1583df828598SMugunthan V N #endif 1584df828598SMugunthan V N 15853b72c2feSMugunthan V N static inline int cpsw_add_vlan_ale_entry(struct cpsw_priv *priv, 15863b72c2feSMugunthan V N unsigned short vid) 15873b72c2feSMugunthan V N { 15883b72c2feSMugunthan V N int ret; 15893b72c2feSMugunthan V N 15903b72c2feSMugunthan V N ret = cpsw_ale_add_vlan(priv->ale, vid, 15913b72c2feSMugunthan V N ALE_ALL_PORTS << priv->host_port, 15923b72c2feSMugunthan V N 0, ALE_ALL_PORTS << priv->host_port, 15933b72c2feSMugunthan V N (ALE_PORT_1 | ALE_PORT_2) << priv->host_port); 15943b72c2feSMugunthan V N if (ret != 0) 15953b72c2feSMugunthan V N return ret; 15963b72c2feSMugunthan V N 15973b72c2feSMugunthan V N ret = cpsw_ale_add_ucast(priv->ale, priv->mac_addr, 15983b72c2feSMugunthan V N priv->host_port, ALE_VLAN, vid); 15993b72c2feSMugunthan V N if (ret != 0) 16003b72c2feSMugunthan V N goto clean_vid; 16013b72c2feSMugunthan V N 16023b72c2feSMugunthan V N ret = cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast, 16033b72c2feSMugunthan V N ALE_ALL_PORTS << priv->host_port, 16043b72c2feSMugunthan V N ALE_VLAN, vid, 0); 16053b72c2feSMugunthan V N if (ret != 0) 16063b72c2feSMugunthan V N goto clean_vlan_ucast; 16073b72c2feSMugunthan V N return 0; 16083b72c2feSMugunthan V N 16093b72c2feSMugunthan V N clean_vlan_ucast: 16103b72c2feSMugunthan V N cpsw_ale_del_ucast(priv->ale, priv->mac_addr, 16113b72c2feSMugunthan V N priv->host_port, ALE_VLAN, vid); 16123b72c2feSMugunthan V N clean_vid: 16133b72c2feSMugunthan V N cpsw_ale_del_vlan(priv->ale, vid, 0); 16143b72c2feSMugunthan V N return ret; 16153b72c2feSMugunthan V N } 16163b72c2feSMugunthan V N 16173b72c2feSMugunthan V N static int cpsw_ndo_vlan_rx_add_vid(struct net_device *ndev, 161880d5c368SPatrick McHardy __be16 proto, u16 vid) 16193b72c2feSMugunthan V N { 16203b72c2feSMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 16213b72c2feSMugunthan V N 16223b72c2feSMugunthan V N if (vid == priv->data.default_vlan) 16233b72c2feSMugunthan V N return 0; 16243b72c2feSMugunthan V N 16253b72c2feSMugunthan V N dev_info(priv->dev, "Adding vlanid %d to vlan filter\n", vid); 16263b72c2feSMugunthan V N return cpsw_add_vlan_ale_entry(priv, vid); 16273b72c2feSMugunthan V N } 16283b72c2feSMugunthan V N 16293b72c2feSMugunthan V N static int cpsw_ndo_vlan_rx_kill_vid(struct net_device *ndev, 163080d5c368SPatrick McHardy __be16 proto, u16 vid) 16313b72c2feSMugunthan V N { 16323b72c2feSMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 16333b72c2feSMugunthan V N int ret; 16343b72c2feSMugunthan V N 16353b72c2feSMugunthan V N if (vid == priv->data.default_vlan) 16363b72c2feSMugunthan V N return 0; 16373b72c2feSMugunthan V N 16383b72c2feSMugunthan V N dev_info(priv->dev, "removing vlanid %d from vlan filter\n", vid); 16393b72c2feSMugunthan V N ret = cpsw_ale_del_vlan(priv->ale, vid, 0); 16403b72c2feSMugunthan V N if (ret != 0) 16413b72c2feSMugunthan V N return ret; 16423b72c2feSMugunthan V N 16433b72c2feSMugunthan V N ret = cpsw_ale_del_ucast(priv->ale, priv->mac_addr, 16443b72c2feSMugunthan V N priv->host_port, ALE_VLAN, vid); 16453b72c2feSMugunthan V N if (ret != 0) 16463b72c2feSMugunthan V N return ret; 16473b72c2feSMugunthan V N 16483b72c2feSMugunthan V N return cpsw_ale_del_mcast(priv->ale, priv->ndev->broadcast, 16493b72c2feSMugunthan V N 0, ALE_VLAN, vid); 16503b72c2feSMugunthan V N } 16513b72c2feSMugunthan V N 1652df828598SMugunthan V N static const struct net_device_ops cpsw_netdev_ops = { 1653df828598SMugunthan V N .ndo_open = cpsw_ndo_open, 1654df828598SMugunthan V N .ndo_stop = cpsw_ndo_stop, 1655df828598SMugunthan V N .ndo_start_xmit = cpsw_ndo_start_xmit, 1656dcfd8d58SMugunthan V N .ndo_set_mac_address = cpsw_ndo_set_mac_address, 16572e5b38abSRichard Cochran .ndo_do_ioctl = cpsw_ndo_ioctl, 1658df828598SMugunthan V N .ndo_validate_addr = eth_validate_addr, 16595c473ed2SDavid S. Miller .ndo_change_mtu = eth_change_mtu, 1660df828598SMugunthan V N .ndo_tx_timeout = cpsw_ndo_tx_timeout, 16615c50a856SMugunthan V N .ndo_set_rx_mode = cpsw_ndo_set_rx_mode, 1662df828598SMugunthan V N #ifdef CONFIG_NET_POLL_CONTROLLER 1663df828598SMugunthan V N .ndo_poll_controller = cpsw_ndo_poll_controller, 1664df828598SMugunthan V N #endif 16653b72c2feSMugunthan V N .ndo_vlan_rx_add_vid = cpsw_ndo_vlan_rx_add_vid, 16663b72c2feSMugunthan V N .ndo_vlan_rx_kill_vid = cpsw_ndo_vlan_rx_kill_vid, 1667df828598SMugunthan V N }; 1668df828598SMugunthan V N 1669df828598SMugunthan V N static void cpsw_get_drvinfo(struct net_device *ndev, 1670df828598SMugunthan V N struct ethtool_drvinfo *info) 1671df828598SMugunthan V N { 1672df828598SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 16737826d43fSJiri Pirko 16747826d43fSJiri Pirko strlcpy(info->driver, "TI CPSW Driver v1.0", sizeof(info->driver)); 16757826d43fSJiri Pirko strlcpy(info->version, "1.0", sizeof(info->version)); 16767826d43fSJiri Pirko strlcpy(info->bus_info, priv->pdev->name, sizeof(info->bus_info)); 1677df828598SMugunthan V N } 1678df828598SMugunthan V N 1679df828598SMugunthan V N static u32 cpsw_get_msglevel(struct net_device *ndev) 1680df828598SMugunthan V N { 1681df828598SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 1682df828598SMugunthan V N return priv->msg_enable; 1683df828598SMugunthan V N } 1684df828598SMugunthan V N 1685df828598SMugunthan V N static void cpsw_set_msglevel(struct net_device *ndev, u32 value) 1686df828598SMugunthan V N { 1687df828598SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 1688df828598SMugunthan V N priv->msg_enable = value; 1689df828598SMugunthan V N } 1690df828598SMugunthan V N 16912e5b38abSRichard Cochran static int cpsw_get_ts_info(struct net_device *ndev, 16922e5b38abSRichard Cochran struct ethtool_ts_info *info) 16932e5b38abSRichard Cochran { 16942e5b38abSRichard Cochran #ifdef CONFIG_TI_CPTS 16952e5b38abSRichard Cochran struct cpsw_priv *priv = netdev_priv(ndev); 16962e5b38abSRichard Cochran 16972e5b38abSRichard Cochran info->so_timestamping = 16982e5b38abSRichard Cochran SOF_TIMESTAMPING_TX_HARDWARE | 16992e5b38abSRichard Cochran SOF_TIMESTAMPING_TX_SOFTWARE | 17002e5b38abSRichard Cochran SOF_TIMESTAMPING_RX_HARDWARE | 17012e5b38abSRichard Cochran SOF_TIMESTAMPING_RX_SOFTWARE | 17022e5b38abSRichard Cochran SOF_TIMESTAMPING_SOFTWARE | 17032e5b38abSRichard Cochran SOF_TIMESTAMPING_RAW_HARDWARE; 17049232b16dSMugunthan V N info->phc_index = priv->cpts->phc_index; 17052e5b38abSRichard Cochran info->tx_types = 17062e5b38abSRichard Cochran (1 << HWTSTAMP_TX_OFF) | 17072e5b38abSRichard Cochran (1 << HWTSTAMP_TX_ON); 17082e5b38abSRichard Cochran info->rx_filters = 17092e5b38abSRichard Cochran (1 << HWTSTAMP_FILTER_NONE) | 17102e5b38abSRichard Cochran (1 << HWTSTAMP_FILTER_PTP_V2_EVENT); 17112e5b38abSRichard Cochran #else 17122e5b38abSRichard Cochran info->so_timestamping = 17132e5b38abSRichard Cochran SOF_TIMESTAMPING_TX_SOFTWARE | 17142e5b38abSRichard Cochran SOF_TIMESTAMPING_RX_SOFTWARE | 17152e5b38abSRichard Cochran SOF_TIMESTAMPING_SOFTWARE; 17162e5b38abSRichard Cochran info->phc_index = -1; 17172e5b38abSRichard Cochran info->tx_types = 0; 17182e5b38abSRichard Cochran info->rx_filters = 0; 17192e5b38abSRichard Cochran #endif 17202e5b38abSRichard Cochran return 0; 17212e5b38abSRichard Cochran } 17222e5b38abSRichard Cochran 1723d3bb9c58SMugunthan V N static int cpsw_get_settings(struct net_device *ndev, 1724d3bb9c58SMugunthan V N struct ethtool_cmd *ecmd) 1725d3bb9c58SMugunthan V N { 1726d3bb9c58SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 1727d3bb9c58SMugunthan V N int slave_no = cpsw_slave_index(priv); 1728d3bb9c58SMugunthan V N 1729d3bb9c58SMugunthan V N if (priv->slaves[slave_no].phy) 1730d3bb9c58SMugunthan V N return phy_ethtool_gset(priv->slaves[slave_no].phy, ecmd); 1731d3bb9c58SMugunthan V N else 1732d3bb9c58SMugunthan V N return -EOPNOTSUPP; 1733d3bb9c58SMugunthan V N } 1734d3bb9c58SMugunthan V N 1735d3bb9c58SMugunthan V N static int cpsw_set_settings(struct net_device *ndev, struct ethtool_cmd *ecmd) 1736d3bb9c58SMugunthan V N { 1737d3bb9c58SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 1738d3bb9c58SMugunthan V N int slave_no = cpsw_slave_index(priv); 1739d3bb9c58SMugunthan V N 1740d3bb9c58SMugunthan V N if (priv->slaves[slave_no].phy) 1741d3bb9c58SMugunthan V N return phy_ethtool_sset(priv->slaves[slave_no].phy, ecmd); 1742d3bb9c58SMugunthan V N else 1743d3bb9c58SMugunthan V N return -EOPNOTSUPP; 1744d3bb9c58SMugunthan V N } 1745d3bb9c58SMugunthan V N 1746d8a64420SMatus Ujhelyi static void cpsw_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol) 1747d8a64420SMatus Ujhelyi { 1748d8a64420SMatus Ujhelyi struct cpsw_priv *priv = netdev_priv(ndev); 1749d8a64420SMatus Ujhelyi int slave_no = cpsw_slave_index(priv); 1750d8a64420SMatus Ujhelyi 1751d8a64420SMatus Ujhelyi wol->supported = 0; 1752d8a64420SMatus Ujhelyi wol->wolopts = 0; 1753d8a64420SMatus Ujhelyi 1754d8a64420SMatus Ujhelyi if (priv->slaves[slave_no].phy) 1755d8a64420SMatus Ujhelyi phy_ethtool_get_wol(priv->slaves[slave_no].phy, wol); 1756d8a64420SMatus Ujhelyi } 1757d8a64420SMatus Ujhelyi 1758d8a64420SMatus Ujhelyi static int cpsw_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol) 1759d8a64420SMatus Ujhelyi { 1760d8a64420SMatus Ujhelyi struct cpsw_priv *priv = netdev_priv(ndev); 1761d8a64420SMatus Ujhelyi int slave_no = cpsw_slave_index(priv); 1762d8a64420SMatus Ujhelyi 1763d8a64420SMatus Ujhelyi if (priv->slaves[slave_no].phy) 1764d8a64420SMatus Ujhelyi return phy_ethtool_set_wol(priv->slaves[slave_no].phy, wol); 1765d8a64420SMatus Ujhelyi else 1766d8a64420SMatus Ujhelyi return -EOPNOTSUPP; 1767d8a64420SMatus Ujhelyi } 1768d8a64420SMatus Ujhelyi 1769df828598SMugunthan V N static const struct ethtool_ops cpsw_ethtool_ops = { 1770df828598SMugunthan V N .get_drvinfo = cpsw_get_drvinfo, 1771df828598SMugunthan V N .get_msglevel = cpsw_get_msglevel, 1772df828598SMugunthan V N .set_msglevel = cpsw_set_msglevel, 1773df828598SMugunthan V N .get_link = ethtool_op_get_link, 17742e5b38abSRichard Cochran .get_ts_info = cpsw_get_ts_info, 1775d3bb9c58SMugunthan V N .get_settings = cpsw_get_settings, 1776d3bb9c58SMugunthan V N .set_settings = cpsw_set_settings, 1777ff5b8ef2SMugunthan V N .get_coalesce = cpsw_get_coalesce, 1778ff5b8ef2SMugunthan V N .set_coalesce = cpsw_set_coalesce, 1779d9718546SMugunthan V N .get_sset_count = cpsw_get_sset_count, 1780d9718546SMugunthan V N .get_strings = cpsw_get_strings, 1781d9718546SMugunthan V N .get_ethtool_stats = cpsw_get_ethtool_stats, 1782d8a64420SMatus Ujhelyi .get_wol = cpsw_get_wol, 1783d8a64420SMatus Ujhelyi .set_wol = cpsw_set_wol, 1784df828598SMugunthan V N }; 1785df828598SMugunthan V N 1786549985eeSRichard Cochran static void cpsw_slave_init(struct cpsw_slave *slave, struct cpsw_priv *priv, 1787549985eeSRichard Cochran u32 slave_reg_ofs, u32 sliver_reg_ofs) 1788df828598SMugunthan V N { 1789df828598SMugunthan V N void __iomem *regs = priv->regs; 1790df828598SMugunthan V N int slave_num = slave->slave_num; 1791df828598SMugunthan V N struct cpsw_slave_data *data = priv->data.slave_data + slave_num; 1792df828598SMugunthan V N 1793df828598SMugunthan V N slave->data = data; 1794549985eeSRichard Cochran slave->regs = regs + slave_reg_ofs; 1795549985eeSRichard Cochran slave->sliver = regs + sliver_reg_ofs; 1796d9ba8f9eSMugunthan V N slave->port_vlan = data->dual_emac_res_vlan; 1797df828598SMugunthan V N } 1798df828598SMugunthan V N 17992eb32b0aSMugunthan V N static int cpsw_probe_dt(struct cpsw_platform_data *data, 18002eb32b0aSMugunthan V N struct platform_device *pdev) 18012eb32b0aSMugunthan V N { 18022eb32b0aSMugunthan V N struct device_node *node = pdev->dev.of_node; 18032eb32b0aSMugunthan V N struct device_node *slave_node; 18042eb32b0aSMugunthan V N int i = 0, ret; 18052eb32b0aSMugunthan V N u32 prop; 18062eb32b0aSMugunthan V N 18072eb32b0aSMugunthan V N if (!node) 18082eb32b0aSMugunthan V N return -EINVAL; 18092eb32b0aSMugunthan V N 18102eb32b0aSMugunthan V N if (of_property_read_u32(node, "slaves", &prop)) { 181188c99ff6SGeorge Cherian dev_err(&pdev->dev, "Missing slaves property in the DT.\n"); 18122eb32b0aSMugunthan V N return -EINVAL; 18132eb32b0aSMugunthan V N } 18142eb32b0aSMugunthan V N data->slaves = prop; 18152eb32b0aSMugunthan V N 1816e86ac13bSMugunthan V N if (of_property_read_u32(node, "active_slave", &prop)) { 181788c99ff6SGeorge Cherian dev_err(&pdev->dev, "Missing active_slave property in the DT.\n"); 1818aa1a15e2SDaniel Mack return -EINVAL; 181978ca0b28SRichard Cochran } 1820e86ac13bSMugunthan V N data->active_slave = prop; 182178ca0b28SRichard Cochran 182200ab94eeSRichard Cochran if (of_property_read_u32(node, "cpts_clock_mult", &prop)) { 182388c99ff6SGeorge Cherian dev_err(&pdev->dev, "Missing cpts_clock_mult property in the DT.\n"); 1824aa1a15e2SDaniel Mack return -EINVAL; 182500ab94eeSRichard Cochran } 182600ab94eeSRichard Cochran data->cpts_clock_mult = prop; 182700ab94eeSRichard Cochran 182800ab94eeSRichard Cochran if (of_property_read_u32(node, "cpts_clock_shift", &prop)) { 182988c99ff6SGeorge Cherian dev_err(&pdev->dev, "Missing cpts_clock_shift property in the DT.\n"); 1830aa1a15e2SDaniel Mack return -EINVAL; 183100ab94eeSRichard Cochran } 183200ab94eeSRichard Cochran data->cpts_clock_shift = prop; 183300ab94eeSRichard Cochran 1834aa1a15e2SDaniel Mack data->slave_data = devm_kzalloc(&pdev->dev, data->slaves 1835aa1a15e2SDaniel Mack * sizeof(struct cpsw_slave_data), 1836b2adaca9SJoe Perches GFP_KERNEL); 1837b2adaca9SJoe Perches if (!data->slave_data) 1838aa1a15e2SDaniel Mack return -ENOMEM; 18392eb32b0aSMugunthan V N 18402eb32b0aSMugunthan V N if (of_property_read_u32(node, "cpdma_channels", &prop)) { 184188c99ff6SGeorge Cherian dev_err(&pdev->dev, "Missing cpdma_channels property in the DT.\n"); 1842aa1a15e2SDaniel Mack return -EINVAL; 18432eb32b0aSMugunthan V N } 18442eb32b0aSMugunthan V N data->channels = prop; 18452eb32b0aSMugunthan V N 18462eb32b0aSMugunthan V N if (of_property_read_u32(node, "ale_entries", &prop)) { 184788c99ff6SGeorge Cherian dev_err(&pdev->dev, "Missing ale_entries property in the DT.\n"); 1848aa1a15e2SDaniel Mack return -EINVAL; 18492eb32b0aSMugunthan V N } 18502eb32b0aSMugunthan V N data->ale_entries = prop; 18512eb32b0aSMugunthan V N 18522eb32b0aSMugunthan V N if (of_property_read_u32(node, "bd_ram_size", &prop)) { 185388c99ff6SGeorge Cherian dev_err(&pdev->dev, "Missing bd_ram_size property in the DT.\n"); 1854aa1a15e2SDaniel Mack return -EINVAL; 18552eb32b0aSMugunthan V N } 18562eb32b0aSMugunthan V N data->bd_ram_size = prop; 18572eb32b0aSMugunthan V N 18582eb32b0aSMugunthan V N if (of_property_read_u32(node, "rx_descs", &prop)) { 185988c99ff6SGeorge Cherian dev_err(&pdev->dev, "Missing rx_descs property in the DT.\n"); 1860aa1a15e2SDaniel Mack return -EINVAL; 18612eb32b0aSMugunthan V N } 18622eb32b0aSMugunthan V N data->rx_descs = prop; 18632eb32b0aSMugunthan V N 18642eb32b0aSMugunthan V N if (of_property_read_u32(node, "mac_control", &prop)) { 186588c99ff6SGeorge Cherian dev_err(&pdev->dev, "Missing mac_control property in the DT.\n"); 1866aa1a15e2SDaniel Mack return -EINVAL; 18672eb32b0aSMugunthan V N } 18682eb32b0aSMugunthan V N data->mac_control = prop; 18692eb32b0aSMugunthan V N 1870281abd96SMarkus Pargmann if (of_property_read_bool(node, "dual_emac")) 1871281abd96SMarkus Pargmann data->dual_emac = 1; 1872d9ba8f9eSMugunthan V N 18731fb19aa7SVaibhav Hiremath /* 18741fb19aa7SVaibhav Hiremath * Populate all the child nodes here... 18751fb19aa7SVaibhav Hiremath */ 18761fb19aa7SVaibhav Hiremath ret = of_platform_populate(node, NULL, NULL, &pdev->dev); 18771fb19aa7SVaibhav Hiremath /* We do not want to force this, as in some cases may not have child */ 18781fb19aa7SVaibhav Hiremath if (ret) 187988c99ff6SGeorge Cherian dev_warn(&pdev->dev, "Doesn't have any child node\n"); 18801fb19aa7SVaibhav Hiremath 1881f468b10eSMarkus Pargmann for_each_child_of_node(node, slave_node) { 1882549985eeSRichard Cochran struct cpsw_slave_data *slave_data = data->slave_data + i; 1883549985eeSRichard Cochran const void *mac_addr = NULL; 1884549985eeSRichard Cochran u32 phyid; 1885549985eeSRichard Cochran int lenp; 1886549985eeSRichard Cochran const __be32 *parp; 1887549985eeSRichard Cochran struct device_node *mdio_node; 1888549985eeSRichard Cochran struct platform_device *mdio; 1889549985eeSRichard Cochran 1890f468b10eSMarkus Pargmann /* This is no slave child node, continue */ 1891f468b10eSMarkus Pargmann if (strcmp(slave_node->name, "slave")) 1892f468b10eSMarkus Pargmann continue; 1893f468b10eSMarkus Pargmann 1894549985eeSRichard Cochran parp = of_get_property(slave_node, "phy_id", &lenp); 1895ce16294fSLothar Waßmann if ((parp == NULL) || (lenp != (sizeof(void *) * 2))) { 189688c99ff6SGeorge Cherian dev_err(&pdev->dev, "Missing slave[%d] phy_id property\n", i); 1897aa1a15e2SDaniel Mack return -EINVAL; 1898549985eeSRichard Cochran } 1899549985eeSRichard Cochran mdio_node = of_find_node_by_phandle(be32_to_cpup(parp)); 1900549985eeSRichard Cochran phyid = be32_to_cpup(parp+1); 1901549985eeSRichard Cochran mdio = of_find_device_by_node(mdio_node); 190260e71ab5SJohan Hovold of_node_put(mdio_node); 19036954cc1fSJohan Hovold if (!mdio) { 19046954cc1fSJohan Hovold pr_err("Missing mdio platform device\n"); 19056954cc1fSJohan Hovold return -EINVAL; 19066954cc1fSJohan Hovold } 1907549985eeSRichard Cochran snprintf(slave_data->phy_id, sizeof(slave_data->phy_id), 1908549985eeSRichard Cochran PHY_ID_FMT, mdio->name, phyid); 1909549985eeSRichard Cochran 1910549985eeSRichard Cochran mac_addr = of_get_mac_address(slave_node); 1911549985eeSRichard Cochran if (mac_addr) 1912549985eeSRichard Cochran memcpy(slave_data->mac_addr, mac_addr, ETH_ALEN); 1913549985eeSRichard Cochran 1914c5ceea7aSMugunthan V N slave_data->phy_if = of_get_phy_mode(slave_node); 191589e10172SUwe Kleine-König if (slave_data->phy_if < 0) { 191688c99ff6SGeorge Cherian dev_err(&pdev->dev, "Missing or malformed slave[%d] phy-mode property\n", 191789e10172SUwe Kleine-König i); 191889e10172SUwe Kleine-König return slave_data->phy_if; 191989e10172SUwe Kleine-König } 1920c5ceea7aSMugunthan V N 1921d9ba8f9eSMugunthan V N if (data->dual_emac) { 192291c4166cSMugunthan V N if (of_property_read_u32(slave_node, "dual_emac_res_vlan", 1923d9ba8f9eSMugunthan V N &prop)) { 192488c99ff6SGeorge Cherian dev_err(&pdev->dev, "Missing dual_emac_res_vlan in DT.\n"); 1925d9ba8f9eSMugunthan V N slave_data->dual_emac_res_vlan = i+1; 192688c99ff6SGeorge Cherian dev_err(&pdev->dev, "Using %d as Reserved VLAN for %d slave\n", 1927d9ba8f9eSMugunthan V N slave_data->dual_emac_res_vlan, i); 1928d9ba8f9eSMugunthan V N } else { 1929d9ba8f9eSMugunthan V N slave_data->dual_emac_res_vlan = prop; 1930d9ba8f9eSMugunthan V N } 1931d9ba8f9eSMugunthan V N } 1932d9ba8f9eSMugunthan V N 1933549985eeSRichard Cochran i++; 19343a27bfacSMugunthan V N if (i == data->slaves) 19353a27bfacSMugunthan V N break; 1936549985eeSRichard Cochran } 1937549985eeSRichard Cochran 19382eb32b0aSMugunthan V N return 0; 19392eb32b0aSMugunthan V N } 19402eb32b0aSMugunthan V N 1941d9ba8f9eSMugunthan V N static int cpsw_probe_dual_emac(struct platform_device *pdev, 1942d9ba8f9eSMugunthan V N struct cpsw_priv *priv) 1943d9ba8f9eSMugunthan V N { 1944d9ba8f9eSMugunthan V N struct cpsw_platform_data *data = &priv->data; 1945d9ba8f9eSMugunthan V N struct net_device *ndev; 1946d9ba8f9eSMugunthan V N struct cpsw_priv *priv_sl2; 1947d9ba8f9eSMugunthan V N int ret = 0, i; 1948d9ba8f9eSMugunthan V N 1949d9ba8f9eSMugunthan V N ndev = alloc_etherdev(sizeof(struct cpsw_priv)); 1950d9ba8f9eSMugunthan V N if (!ndev) { 195188c99ff6SGeorge Cherian dev_err(&pdev->dev, "cpsw: error allocating net_device\n"); 1952d9ba8f9eSMugunthan V N return -ENOMEM; 1953d9ba8f9eSMugunthan V N } 1954d9ba8f9eSMugunthan V N 1955d9ba8f9eSMugunthan V N priv_sl2 = netdev_priv(ndev); 1956d9ba8f9eSMugunthan V N spin_lock_init(&priv_sl2->lock); 1957d9ba8f9eSMugunthan V N priv_sl2->data = *data; 1958d9ba8f9eSMugunthan V N priv_sl2->pdev = pdev; 1959d9ba8f9eSMugunthan V N priv_sl2->ndev = ndev; 1960d9ba8f9eSMugunthan V N priv_sl2->dev = &ndev->dev; 1961d9ba8f9eSMugunthan V N priv_sl2->msg_enable = netif_msg_init(debug_level, CPSW_DEBUG); 1962d9ba8f9eSMugunthan V N priv_sl2->rx_packet_max = max(rx_packet_max, 128); 1963d9ba8f9eSMugunthan V N 1964d9ba8f9eSMugunthan V N if (is_valid_ether_addr(data->slave_data[1].mac_addr)) { 1965d9ba8f9eSMugunthan V N memcpy(priv_sl2->mac_addr, data->slave_data[1].mac_addr, 1966d9ba8f9eSMugunthan V N ETH_ALEN); 196788c99ff6SGeorge Cherian dev_info(&pdev->dev, "cpsw: Detected MACID = %pM\n", priv_sl2->mac_addr); 1968d9ba8f9eSMugunthan V N } else { 1969d9ba8f9eSMugunthan V N random_ether_addr(priv_sl2->mac_addr); 197088c99ff6SGeorge Cherian dev_info(&pdev->dev, "cpsw: Random MACID = %pM\n", priv_sl2->mac_addr); 1971d9ba8f9eSMugunthan V N } 1972d9ba8f9eSMugunthan V N memcpy(ndev->dev_addr, priv_sl2->mac_addr, ETH_ALEN); 1973d9ba8f9eSMugunthan V N 1974d9ba8f9eSMugunthan V N priv_sl2->slaves = priv->slaves; 1975d9ba8f9eSMugunthan V N priv_sl2->clk = priv->clk; 1976d9ba8f9eSMugunthan V N 1977ff5b8ef2SMugunthan V N priv_sl2->coal_intvl = 0; 1978ff5b8ef2SMugunthan V N priv_sl2->bus_freq_mhz = priv->bus_freq_mhz; 1979ff5b8ef2SMugunthan V N 1980d9ba8f9eSMugunthan V N priv_sl2->regs = priv->regs; 1981d9ba8f9eSMugunthan V N priv_sl2->host_port = priv->host_port; 1982d9ba8f9eSMugunthan V N priv_sl2->host_port_regs = priv->host_port_regs; 1983d9ba8f9eSMugunthan V N priv_sl2->wr_regs = priv->wr_regs; 1984d9718546SMugunthan V N priv_sl2->hw_stats = priv->hw_stats; 1985d9ba8f9eSMugunthan V N priv_sl2->dma = priv->dma; 1986d9ba8f9eSMugunthan V N priv_sl2->txch = priv->txch; 1987d9ba8f9eSMugunthan V N priv_sl2->rxch = priv->rxch; 1988d9ba8f9eSMugunthan V N priv_sl2->ale = priv->ale; 1989d9ba8f9eSMugunthan V N priv_sl2->emac_port = 1; 1990d9ba8f9eSMugunthan V N priv->slaves[1].ndev = ndev; 1991d9ba8f9eSMugunthan V N priv_sl2->cpts = priv->cpts; 1992d9ba8f9eSMugunthan V N priv_sl2->version = priv->version; 1993d9ba8f9eSMugunthan V N 1994d9ba8f9eSMugunthan V N for (i = 0; i < priv->num_irqs; i++) { 1995d9ba8f9eSMugunthan V N priv_sl2->irqs_table[i] = priv->irqs_table[i]; 1996d9ba8f9eSMugunthan V N priv_sl2->num_irqs = priv->num_irqs; 1997d9ba8f9eSMugunthan V N } 1998f646968fSPatrick McHardy ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER; 1999d9ba8f9eSMugunthan V N 2000d9ba8f9eSMugunthan V N ndev->netdev_ops = &cpsw_netdev_ops; 20017ad24ea4SWilfried Klaebe ndev->ethtool_ops = &cpsw_ethtool_ops; 2002d9ba8f9eSMugunthan V N netif_napi_add(ndev, &priv_sl2->napi, cpsw_poll, CPSW_POLL_WEIGHT); 2003d9ba8f9eSMugunthan V N 2004d9ba8f9eSMugunthan V N /* register the network device */ 2005d9ba8f9eSMugunthan V N SET_NETDEV_DEV(ndev, &pdev->dev); 2006d9ba8f9eSMugunthan V N ret = register_netdev(ndev); 2007d9ba8f9eSMugunthan V N if (ret) { 200888c99ff6SGeorge Cherian dev_err(&pdev->dev, "cpsw: error registering net device\n"); 2009d9ba8f9eSMugunthan V N free_netdev(ndev); 2010d9ba8f9eSMugunthan V N ret = -ENODEV; 2011d9ba8f9eSMugunthan V N } 2012d9ba8f9eSMugunthan V N 2013d9ba8f9eSMugunthan V N return ret; 2014d9ba8f9eSMugunthan V N } 2015d9ba8f9eSMugunthan V N 2016663e12e6SBill Pemberton static int cpsw_probe(struct platform_device *pdev) 2017df828598SMugunthan V N { 2018d1bd9acfSSebastian Siewior struct cpsw_platform_data *data; 2019df828598SMugunthan V N struct net_device *ndev; 2020df828598SMugunthan V N struct cpsw_priv *priv; 2021df828598SMugunthan V N struct cpdma_params dma_params; 2022df828598SMugunthan V N struct cpsw_ale_params ale_params; 2023aa1a15e2SDaniel Mack void __iomem *ss_regs; 2024aa1a15e2SDaniel Mack struct resource *res, *ss_res; 2025549985eeSRichard Cochran u32 slave_offset, sliver_offset, slave_size; 2026df828598SMugunthan V N int ret = 0, i, k = 0; 2027df828598SMugunthan V N 2028df828598SMugunthan V N ndev = alloc_etherdev(sizeof(struct cpsw_priv)); 2029df828598SMugunthan V N if (!ndev) { 203088c99ff6SGeorge Cherian dev_err(&pdev->dev, "error allocating net_device\n"); 2031df828598SMugunthan V N return -ENOMEM; 2032df828598SMugunthan V N } 2033df828598SMugunthan V N 2034df828598SMugunthan V N platform_set_drvdata(pdev, ndev); 2035df828598SMugunthan V N priv = netdev_priv(ndev); 2036df828598SMugunthan V N spin_lock_init(&priv->lock); 2037df828598SMugunthan V N priv->pdev = pdev; 2038df828598SMugunthan V N priv->ndev = ndev; 2039df828598SMugunthan V N priv->dev = &ndev->dev; 2040df828598SMugunthan V N priv->msg_enable = netif_msg_init(debug_level, CPSW_DEBUG); 2041df828598SMugunthan V N priv->rx_packet_max = max(rx_packet_max, 128); 20429232b16dSMugunthan V N priv->cpts = devm_kzalloc(&pdev->dev, sizeof(struct cpts), GFP_KERNEL); 20437dcf313aSMugunthan V N priv->irq_enabled = true; 2044ab8e99d2SSebastian Siewior if (!priv->cpts) { 204588c99ff6SGeorge Cherian dev_err(&pdev->dev, "error allocating cpts\n"); 20469232b16dSMugunthan V N goto clean_ndev_ret; 20479232b16dSMugunthan V N } 2048df828598SMugunthan V N 20491fb19aa7SVaibhav Hiremath /* 20501fb19aa7SVaibhav Hiremath * This may be required here for child devices. 20511fb19aa7SVaibhav Hiremath */ 20521fb19aa7SVaibhav Hiremath pm_runtime_enable(&pdev->dev); 20531fb19aa7SVaibhav Hiremath 2054739683b4SMugunthan V N /* Select default pin state */ 2055739683b4SMugunthan V N pinctrl_pm_select_default_state(&pdev->dev); 2056739683b4SMugunthan V N 20572eb32b0aSMugunthan V N if (cpsw_probe_dt(&priv->data, pdev)) { 205888c99ff6SGeorge Cherian dev_err(&pdev->dev, "cpsw: platform data missing\n"); 20592eb32b0aSMugunthan V N ret = -ENODEV; 2060aa1a15e2SDaniel Mack goto clean_runtime_disable_ret; 20612eb32b0aSMugunthan V N } 20622eb32b0aSMugunthan V N data = &priv->data; 20632eb32b0aSMugunthan V N 2064df828598SMugunthan V N if (is_valid_ether_addr(data->slave_data[0].mac_addr)) { 2065df828598SMugunthan V N memcpy(priv->mac_addr, data->slave_data[0].mac_addr, ETH_ALEN); 206688c99ff6SGeorge Cherian dev_info(&pdev->dev, "Detected MACID = %pM\n", priv->mac_addr); 2067df828598SMugunthan V N } else { 20687efd26d0SJoe Perches eth_random_addr(priv->mac_addr); 206988c99ff6SGeorge Cherian dev_info(&pdev->dev, "Random MACID = %pM\n", priv->mac_addr); 2070df828598SMugunthan V N } 2071df828598SMugunthan V N 2072df828598SMugunthan V N memcpy(ndev->dev_addr, priv->mac_addr, ETH_ALEN); 2073df828598SMugunthan V N 2074aa1a15e2SDaniel Mack priv->slaves = devm_kzalloc(&pdev->dev, 2075aa1a15e2SDaniel Mack sizeof(struct cpsw_slave) * data->slaves, 2076df828598SMugunthan V N GFP_KERNEL); 2077df828598SMugunthan V N if (!priv->slaves) { 2078aa1a15e2SDaniel Mack ret = -ENOMEM; 2079aa1a15e2SDaniel Mack goto clean_runtime_disable_ret; 2080df828598SMugunthan V N } 2081df828598SMugunthan V N for (i = 0; i < data->slaves; i++) 2082df828598SMugunthan V N priv->slaves[i].slave_num = i; 2083df828598SMugunthan V N 2084d9ba8f9eSMugunthan V N priv->slaves[0].ndev = ndev; 2085d9ba8f9eSMugunthan V N priv->emac_port = 0; 2086d9ba8f9eSMugunthan V N 2087aa1a15e2SDaniel Mack priv->clk = devm_clk_get(&pdev->dev, "fck"); 2088df828598SMugunthan V N if (IS_ERR(priv->clk)) { 2089aa1a15e2SDaniel Mack dev_err(priv->dev, "fck is not found\n"); 2090f150bd7fSMugunthan V N ret = -ENODEV; 2091aa1a15e2SDaniel Mack goto clean_runtime_disable_ret; 2092df828598SMugunthan V N } 2093ff5b8ef2SMugunthan V N priv->coal_intvl = 0; 2094ff5b8ef2SMugunthan V N priv->bus_freq_mhz = clk_get_rate(priv->clk) / 1000000; 2095df828598SMugunthan V N 2096aa1a15e2SDaniel Mack ss_res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2097aa1a15e2SDaniel Mack ss_regs = devm_ioremap_resource(&pdev->dev, ss_res); 2098aa1a15e2SDaniel Mack if (IS_ERR(ss_regs)) { 2099aa1a15e2SDaniel Mack ret = PTR_ERR(ss_regs); 2100aa1a15e2SDaniel Mack goto clean_runtime_disable_ret; 2101df828598SMugunthan V N } 2102549985eeSRichard Cochran priv->regs = ss_regs; 2103549985eeSRichard Cochran priv->host_port = HOST_PORT_NUM; 2104df828598SMugunthan V N 2105f280e89aSMugunthan V N /* Need to enable clocks with runtime PM api to access module 2106f280e89aSMugunthan V N * registers 2107f280e89aSMugunthan V N */ 2108f280e89aSMugunthan V N pm_runtime_get_sync(&pdev->dev); 2109f280e89aSMugunthan V N priv->version = readl(&priv->regs->id_ver); 2110f280e89aSMugunthan V N pm_runtime_put_sync(&pdev->dev); 2111f280e89aSMugunthan V N 2112aa1a15e2SDaniel Mack res = platform_get_resource(pdev, IORESOURCE_MEM, 1); 2113aa1a15e2SDaniel Mack priv->wr_regs = devm_ioremap_resource(&pdev->dev, res); 2114aa1a15e2SDaniel Mack if (IS_ERR(priv->wr_regs)) { 2115aa1a15e2SDaniel Mack ret = PTR_ERR(priv->wr_regs); 2116aa1a15e2SDaniel Mack goto clean_runtime_disable_ret; 2117df828598SMugunthan V N } 2118df828598SMugunthan V N 2119df828598SMugunthan V N memset(&dma_params, 0, sizeof(dma_params)); 2120549985eeSRichard Cochran memset(&ale_params, 0, sizeof(ale_params)); 2121549985eeSRichard Cochran 2122549985eeSRichard Cochran switch (priv->version) { 2123549985eeSRichard Cochran case CPSW_VERSION_1: 2124549985eeSRichard Cochran priv->host_port_regs = ss_regs + CPSW1_HOST_PORT_OFFSET; 21259232b16dSMugunthan V N priv->cpts->reg = ss_regs + CPSW1_CPTS_OFFSET; 2126d9718546SMugunthan V N priv->hw_stats = ss_regs + CPSW1_HW_STATS; 2127549985eeSRichard Cochran dma_params.dmaregs = ss_regs + CPSW1_CPDMA_OFFSET; 2128549985eeSRichard Cochran dma_params.txhdp = ss_regs + CPSW1_STATERAM_OFFSET; 2129549985eeSRichard Cochran ale_params.ale_regs = ss_regs + CPSW1_ALE_OFFSET; 2130549985eeSRichard Cochran slave_offset = CPSW1_SLAVE_OFFSET; 2131549985eeSRichard Cochran slave_size = CPSW1_SLAVE_SIZE; 2132549985eeSRichard Cochran sliver_offset = CPSW1_SLIVER_OFFSET; 2133549985eeSRichard Cochran dma_params.desc_mem_phys = 0; 2134549985eeSRichard Cochran break; 2135549985eeSRichard Cochran case CPSW_VERSION_2: 2136c193f365SMugunthan V N case CPSW_VERSION_3: 2137926489beSMugunthan V N case CPSW_VERSION_4: 2138549985eeSRichard Cochran priv->host_port_regs = ss_regs + CPSW2_HOST_PORT_OFFSET; 21399232b16dSMugunthan V N priv->cpts->reg = ss_regs + CPSW2_CPTS_OFFSET; 2140d9718546SMugunthan V N priv->hw_stats = ss_regs + CPSW2_HW_STATS; 2141549985eeSRichard Cochran dma_params.dmaregs = ss_regs + CPSW2_CPDMA_OFFSET; 2142549985eeSRichard Cochran dma_params.txhdp = ss_regs + CPSW2_STATERAM_OFFSET; 2143549985eeSRichard Cochran ale_params.ale_regs = ss_regs + CPSW2_ALE_OFFSET; 2144549985eeSRichard Cochran slave_offset = CPSW2_SLAVE_OFFSET; 2145549985eeSRichard Cochran slave_size = CPSW2_SLAVE_SIZE; 2146549985eeSRichard Cochran sliver_offset = CPSW2_SLIVER_OFFSET; 2147549985eeSRichard Cochran dma_params.desc_mem_phys = 2148aa1a15e2SDaniel Mack (u32 __force) ss_res->start + CPSW2_BD_OFFSET; 2149549985eeSRichard Cochran break; 2150549985eeSRichard Cochran default: 2151549985eeSRichard Cochran dev_err(priv->dev, "unknown version 0x%08x\n", priv->version); 2152549985eeSRichard Cochran ret = -ENODEV; 2153aa1a15e2SDaniel Mack goto clean_runtime_disable_ret; 2154549985eeSRichard Cochran } 2155549985eeSRichard Cochran for (i = 0; i < priv->data.slaves; i++) { 2156549985eeSRichard Cochran struct cpsw_slave *slave = &priv->slaves[i]; 2157549985eeSRichard Cochran cpsw_slave_init(slave, priv, slave_offset, sliver_offset); 2158549985eeSRichard Cochran slave_offset += slave_size; 2159549985eeSRichard Cochran sliver_offset += SLIVER_SIZE; 2160549985eeSRichard Cochran } 2161549985eeSRichard Cochran 2162df828598SMugunthan V N dma_params.dev = &pdev->dev; 2163549985eeSRichard Cochran dma_params.rxthresh = dma_params.dmaregs + CPDMA_RXTHRESH; 2164549985eeSRichard Cochran dma_params.rxfree = dma_params.dmaregs + CPDMA_RXFREE; 2165549985eeSRichard Cochran dma_params.rxhdp = dma_params.txhdp + CPDMA_RXHDP; 2166549985eeSRichard Cochran dma_params.txcp = dma_params.txhdp + CPDMA_TXCP; 2167549985eeSRichard Cochran dma_params.rxcp = dma_params.txhdp + CPDMA_RXCP; 2168df828598SMugunthan V N 2169df828598SMugunthan V N dma_params.num_chan = data->channels; 2170df828598SMugunthan V N dma_params.has_soft_reset = true; 2171df828598SMugunthan V N dma_params.min_packet_size = CPSW_MIN_PACKET_SIZE; 2172df828598SMugunthan V N dma_params.desc_mem_size = data->bd_ram_size; 2173df828598SMugunthan V N dma_params.desc_align = 16; 2174df828598SMugunthan V N dma_params.has_ext_regs = true; 2175549985eeSRichard Cochran dma_params.desc_hw_addr = dma_params.desc_mem_phys; 2176df828598SMugunthan V N 2177df828598SMugunthan V N priv->dma = cpdma_ctlr_create(&dma_params); 2178df828598SMugunthan V N if (!priv->dma) { 2179df828598SMugunthan V N dev_err(priv->dev, "error initializing dma\n"); 2180df828598SMugunthan V N ret = -ENOMEM; 2181aa1a15e2SDaniel Mack goto clean_runtime_disable_ret; 2182df828598SMugunthan V N } 2183df828598SMugunthan V N 2184df828598SMugunthan V N priv->txch = cpdma_chan_create(priv->dma, tx_chan_num(0), 2185df828598SMugunthan V N cpsw_tx_handler); 2186df828598SMugunthan V N priv->rxch = cpdma_chan_create(priv->dma, rx_chan_num(0), 2187df828598SMugunthan V N cpsw_rx_handler); 2188df828598SMugunthan V N 2189df828598SMugunthan V N if (WARN_ON(!priv->txch || !priv->rxch)) { 2190df828598SMugunthan V N dev_err(priv->dev, "error initializing dma channels\n"); 2191df828598SMugunthan V N ret = -ENOMEM; 2192df828598SMugunthan V N goto clean_dma_ret; 2193df828598SMugunthan V N } 2194df828598SMugunthan V N 2195df828598SMugunthan V N ale_params.dev = &ndev->dev; 2196df828598SMugunthan V N ale_params.ale_ageout = ale_ageout; 2197df828598SMugunthan V N ale_params.ale_entries = data->ale_entries; 2198df828598SMugunthan V N ale_params.ale_ports = data->slaves; 2199df828598SMugunthan V N 2200df828598SMugunthan V N priv->ale = cpsw_ale_create(&ale_params); 2201df828598SMugunthan V N if (!priv->ale) { 2202df828598SMugunthan V N dev_err(priv->dev, "error initializing ale engine\n"); 2203df828598SMugunthan V N ret = -ENODEV; 2204df828598SMugunthan V N goto clean_dma_ret; 2205df828598SMugunthan V N } 2206df828598SMugunthan V N 2207df828598SMugunthan V N ndev->irq = platform_get_irq(pdev, 0); 2208df828598SMugunthan V N if (ndev->irq < 0) { 2209df828598SMugunthan V N dev_err(priv->dev, "error getting irq resource\n"); 2210df828598SMugunthan V N ret = -ENOENT; 2211df828598SMugunthan V N goto clean_ale_ret; 2212df828598SMugunthan V N } 2213df828598SMugunthan V N 2214df828598SMugunthan V N while ((res = platform_get_resource(priv->pdev, IORESOURCE_IRQ, k))) { 2215df828598SMugunthan V N for (i = res->start; i <= res->end; i++) { 2216aa1a15e2SDaniel Mack if (devm_request_irq(&pdev->dev, i, cpsw_interrupt, 0, 2217db850559SMugunthan V N dev_name(&pdev->dev), priv)) { 2218df828598SMugunthan V N dev_err(priv->dev, "error attaching irq\n"); 2219df828598SMugunthan V N goto clean_ale_ret; 2220df828598SMugunthan V N } 2221df828598SMugunthan V N priv->irqs_table[k] = i; 2222d1bd9acfSSebastian Siewior priv->num_irqs = k + 1; 2223df828598SMugunthan V N } 2224df828598SMugunthan V N k++; 2225df828598SMugunthan V N } 2226df828598SMugunthan V N 2227f646968fSPatrick McHardy ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER; 2228df828598SMugunthan V N 2229df828598SMugunthan V N ndev->netdev_ops = &cpsw_netdev_ops; 22307ad24ea4SWilfried Klaebe ndev->ethtool_ops = &cpsw_ethtool_ops; 2231df828598SMugunthan V N netif_napi_add(ndev, &priv->napi, cpsw_poll, CPSW_POLL_WEIGHT); 2232df828598SMugunthan V N 2233df828598SMugunthan V N /* register the network device */ 2234df828598SMugunthan V N SET_NETDEV_DEV(ndev, &pdev->dev); 2235df828598SMugunthan V N ret = register_netdev(ndev); 2236df828598SMugunthan V N if (ret) { 2237df828598SMugunthan V N dev_err(priv->dev, "error registering net device\n"); 2238df828598SMugunthan V N ret = -ENODEV; 2239aa1a15e2SDaniel Mack goto clean_ale_ret; 2240df828598SMugunthan V N } 2241df828598SMugunthan V N 22421a3b5056SOlof Johansson cpsw_notice(priv, probe, "initialized device (regs %pa, irq %d)\n", 22431a3b5056SOlof Johansson &ss_res->start, ndev->irq); 2244df828598SMugunthan V N 2245d9ba8f9eSMugunthan V N if (priv->data.dual_emac) { 2246d9ba8f9eSMugunthan V N ret = cpsw_probe_dual_emac(pdev, priv); 2247d9ba8f9eSMugunthan V N if (ret) { 2248d9ba8f9eSMugunthan V N cpsw_err(priv, probe, "error probe slave 2 emac interface\n"); 2249aa1a15e2SDaniel Mack goto clean_ale_ret; 2250d9ba8f9eSMugunthan V N } 2251d9ba8f9eSMugunthan V N } 2252d9ba8f9eSMugunthan V N 2253df828598SMugunthan V N return 0; 2254df828598SMugunthan V N 2255df828598SMugunthan V N clean_ale_ret: 2256df828598SMugunthan V N cpsw_ale_destroy(priv->ale); 2257df828598SMugunthan V N clean_dma_ret: 2258df828598SMugunthan V N cpdma_chan_destroy(priv->txch); 2259df828598SMugunthan V N cpdma_chan_destroy(priv->rxch); 2260df828598SMugunthan V N cpdma_ctlr_destroy(priv->dma); 2261aa1a15e2SDaniel Mack clean_runtime_disable_ret: 2262f150bd7fSMugunthan V N pm_runtime_disable(&pdev->dev); 2263df828598SMugunthan V N clean_ndev_ret: 2264d1bd9acfSSebastian Siewior free_netdev(priv->ndev); 2265df828598SMugunthan V N return ret; 2266df828598SMugunthan V N } 2267df828598SMugunthan V N 2268663e12e6SBill Pemberton static int cpsw_remove(struct platform_device *pdev) 2269df828598SMugunthan V N { 2270df828598SMugunthan V N struct net_device *ndev = platform_get_drvdata(pdev); 2271df828598SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 2272df828598SMugunthan V N 2273d1bd9acfSSebastian Siewior if (priv->data.dual_emac) 2274d1bd9acfSSebastian Siewior unregister_netdev(cpsw_get_slave_ndev(priv, 1)); 2275d1bd9acfSSebastian Siewior unregister_netdev(ndev); 2276df828598SMugunthan V N 2277df828598SMugunthan V N cpsw_ale_destroy(priv->ale); 2278df828598SMugunthan V N cpdma_chan_destroy(priv->txch); 2279df828598SMugunthan V N cpdma_chan_destroy(priv->rxch); 2280df828598SMugunthan V N cpdma_ctlr_destroy(priv->dma); 2281f150bd7fSMugunthan V N pm_runtime_disable(&pdev->dev); 2282d1bd9acfSSebastian Siewior if (priv->data.dual_emac) 2283d1bd9acfSSebastian Siewior free_netdev(cpsw_get_slave_ndev(priv, 1)); 2284df828598SMugunthan V N free_netdev(ndev); 2285df828598SMugunthan V N return 0; 2286df828598SMugunthan V N } 2287df828598SMugunthan V N 2288df828598SMugunthan V N static int cpsw_suspend(struct device *dev) 2289df828598SMugunthan V N { 2290df828598SMugunthan V N struct platform_device *pdev = to_platform_device(dev); 2291df828598SMugunthan V N struct net_device *ndev = platform_get_drvdata(pdev); 2292b90fc27aSMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 2293df828598SMugunthan V N 2294df828598SMugunthan V N if (netif_running(ndev)) 2295df828598SMugunthan V N cpsw_ndo_stop(ndev); 22961e7a2e21SDaniel Mack 22971e7a2e21SDaniel Mack for_each_slave(priv, soft_reset_slave); 22981e7a2e21SDaniel Mack 2299f150bd7fSMugunthan V N pm_runtime_put_sync(&pdev->dev); 2300f150bd7fSMugunthan V N 2301739683b4SMugunthan V N /* Select sleep pin state */ 2302739683b4SMugunthan V N pinctrl_pm_select_sleep_state(&pdev->dev); 2303739683b4SMugunthan V N 2304df828598SMugunthan V N return 0; 2305df828598SMugunthan V N } 2306df828598SMugunthan V N 2307df828598SMugunthan V N static int cpsw_resume(struct device *dev) 2308df828598SMugunthan V N { 2309df828598SMugunthan V N struct platform_device *pdev = to_platform_device(dev); 2310df828598SMugunthan V N struct net_device *ndev = platform_get_drvdata(pdev); 2311df828598SMugunthan V N 2312f150bd7fSMugunthan V N pm_runtime_get_sync(&pdev->dev); 2313739683b4SMugunthan V N 2314739683b4SMugunthan V N /* Select default pin state */ 2315739683b4SMugunthan V N pinctrl_pm_select_default_state(&pdev->dev); 2316739683b4SMugunthan V N 2317df828598SMugunthan V N if (netif_running(ndev)) 2318df828598SMugunthan V N cpsw_ndo_open(ndev); 2319df828598SMugunthan V N return 0; 2320df828598SMugunthan V N } 2321df828598SMugunthan V N 2322df828598SMugunthan V N static const struct dev_pm_ops cpsw_pm_ops = { 2323df828598SMugunthan V N .suspend = cpsw_suspend, 2324df828598SMugunthan V N .resume = cpsw_resume, 2325df828598SMugunthan V N }; 2326df828598SMugunthan V N 23272eb32b0aSMugunthan V N static const struct of_device_id cpsw_of_mtable[] = { 23282eb32b0aSMugunthan V N { .compatible = "ti,cpsw", }, 23292eb32b0aSMugunthan V N { /* sentinel */ }, 23302eb32b0aSMugunthan V N }; 23314bc21d41SSebastian Siewior MODULE_DEVICE_TABLE(of, cpsw_of_mtable); 23322eb32b0aSMugunthan V N 2333df828598SMugunthan V N static struct platform_driver cpsw_driver = { 2334df828598SMugunthan V N .driver = { 2335df828598SMugunthan V N .name = "cpsw", 2336df828598SMugunthan V N .owner = THIS_MODULE, 2337df828598SMugunthan V N .pm = &cpsw_pm_ops, 23381e5c76d4SSachin Kamat .of_match_table = cpsw_of_mtable, 2339df828598SMugunthan V N }, 2340df828598SMugunthan V N .probe = cpsw_probe, 2341663e12e6SBill Pemberton .remove = cpsw_remove, 2342df828598SMugunthan V N }; 2343df828598SMugunthan V N 2344df828598SMugunthan V N static int __init cpsw_init(void) 2345df828598SMugunthan V N { 2346df828598SMugunthan V N return platform_driver_register(&cpsw_driver); 2347df828598SMugunthan V N } 2348df828598SMugunthan V N late_initcall(cpsw_init); 2349df828598SMugunthan V N 2350df828598SMugunthan V N static void __exit cpsw_exit(void) 2351df828598SMugunthan V N { 2352df828598SMugunthan V N platform_driver_unregister(&cpsw_driver); 2353df828598SMugunthan V N } 2354df828598SMugunthan V N module_exit(cpsw_exit); 2355df828598SMugunthan V N 2356df828598SMugunthan V N MODULE_LICENSE("GPL"); 2357df828598SMugunthan V N MODULE_AUTHOR("Cyril Chemparathy <cyril@ti.com>"); 2358df828598SMugunthan V N MODULE_AUTHOR("Mugunthan V N <mugunthanvnm@ti.com>"); 2359df828598SMugunthan V N MODULE_DESCRIPTION("TI CPSW Ethernet driver"); 2360