1df828598SMugunthan V N /* 2df828598SMugunthan V N * Texas Instruments Ethernet Switch Driver 3df828598SMugunthan V N * 4df828598SMugunthan V N * Copyright (C) 2012 Texas Instruments 5df828598SMugunthan V N * 6df828598SMugunthan V N * This program is free software; you can redistribute it and/or 7df828598SMugunthan V N * modify it under the terms of the GNU General Public License as 8df828598SMugunthan V N * published by the Free Software Foundation version 2. 9df828598SMugunthan V N * 10df828598SMugunthan V N * This program is distributed "as is" WITHOUT ANY WARRANTY of any 11df828598SMugunthan V N * kind, whether express or implied; without even the implied warranty 12df828598SMugunthan V N * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13df828598SMugunthan V N * GNU General Public License for more details. 14df828598SMugunthan V N */ 15df828598SMugunthan V N 16df828598SMugunthan V N #include <linux/kernel.h> 17df828598SMugunthan V N #include <linux/io.h> 18df828598SMugunthan V N #include <linux/clk.h> 19df828598SMugunthan V N #include <linux/timer.h> 20df828598SMugunthan V N #include <linux/module.h> 21df828598SMugunthan V N #include <linux/platform_device.h> 22df828598SMugunthan V N #include <linux/irqreturn.h> 23df828598SMugunthan V N #include <linux/interrupt.h> 24df828598SMugunthan V N #include <linux/if_ether.h> 25df828598SMugunthan V N #include <linux/etherdevice.h> 26df828598SMugunthan V N #include <linux/netdevice.h> 272e5b38abSRichard Cochran #include <linux/net_tstamp.h> 28df828598SMugunthan V N #include <linux/phy.h> 29df828598SMugunthan V N #include <linux/workqueue.h> 30df828598SMugunthan V N #include <linux/delay.h> 31f150bd7fSMugunthan V N #include <linux/pm_runtime.h> 322eb32b0aSMugunthan V N #include <linux/of.h> 332eb32b0aSMugunthan V N #include <linux/of_net.h> 342eb32b0aSMugunthan V N #include <linux/of_device.h> 353b72c2feSMugunthan V N #include <linux/if_vlan.h> 36df828598SMugunthan V N 37739683b4SMugunthan V N #include <linux/pinctrl/consumer.h> 38df828598SMugunthan V N 39dbe34724SMugunthan V N #include "cpsw.h" 40df828598SMugunthan V N #include "cpsw_ale.h" 412e5b38abSRichard Cochran #include "cpts.h" 42df828598SMugunthan V N #include "davinci_cpdma.h" 43df828598SMugunthan V N 44df828598SMugunthan V N #define CPSW_DEBUG (NETIF_MSG_HW | NETIF_MSG_WOL | \ 45df828598SMugunthan V N NETIF_MSG_DRV | NETIF_MSG_LINK | \ 46df828598SMugunthan V N NETIF_MSG_IFUP | NETIF_MSG_INTR | \ 47df828598SMugunthan V N NETIF_MSG_PROBE | NETIF_MSG_TIMER | \ 48df828598SMugunthan V N NETIF_MSG_IFDOWN | NETIF_MSG_RX_ERR | \ 49df828598SMugunthan V N NETIF_MSG_TX_ERR | NETIF_MSG_TX_DONE | \ 50df828598SMugunthan V N NETIF_MSG_PKTDATA | NETIF_MSG_TX_QUEUED | \ 51df828598SMugunthan V N NETIF_MSG_RX_STATUS) 52df828598SMugunthan V N 53df828598SMugunthan V N #define cpsw_info(priv, type, format, ...) \ 54df828598SMugunthan V N do { \ 55df828598SMugunthan V N if (netif_msg_##type(priv) && net_ratelimit()) \ 56df828598SMugunthan V N dev_info(priv->dev, format, ## __VA_ARGS__); \ 57df828598SMugunthan V N } while (0) 58df828598SMugunthan V N 59df828598SMugunthan V N #define cpsw_err(priv, type, format, ...) \ 60df828598SMugunthan V N do { \ 61df828598SMugunthan V N if (netif_msg_##type(priv) && net_ratelimit()) \ 62df828598SMugunthan V N dev_err(priv->dev, format, ## __VA_ARGS__); \ 63df828598SMugunthan V N } while (0) 64df828598SMugunthan V N 65df828598SMugunthan V N #define cpsw_dbg(priv, type, format, ...) \ 66df828598SMugunthan V N do { \ 67df828598SMugunthan V N if (netif_msg_##type(priv) && net_ratelimit()) \ 68df828598SMugunthan V N dev_dbg(priv->dev, format, ## __VA_ARGS__); \ 69df828598SMugunthan V N } while (0) 70df828598SMugunthan V N 71df828598SMugunthan V N #define cpsw_notice(priv, type, format, ...) \ 72df828598SMugunthan V N do { \ 73df828598SMugunthan V N if (netif_msg_##type(priv) && net_ratelimit()) \ 74df828598SMugunthan V N dev_notice(priv->dev, format, ## __VA_ARGS__); \ 75df828598SMugunthan V N } while (0) 76df828598SMugunthan V N 775c50a856SMugunthan V N #define ALE_ALL_PORTS 0x7 785c50a856SMugunthan V N 79df828598SMugunthan V N #define CPSW_MAJOR_VERSION(reg) (reg >> 8 & 0x7) 80df828598SMugunthan V N #define CPSW_MINOR_VERSION(reg) (reg & 0xff) 81df828598SMugunthan V N #define CPSW_RTL_VERSION(reg) ((reg >> 11) & 0x1f) 82df828598SMugunthan V N 83e90cfac6SRichard Cochran #define CPSW_VERSION_1 0x19010a 84e90cfac6SRichard Cochran #define CPSW_VERSION_2 0x19010c 85c193f365SMugunthan V N #define CPSW_VERSION_3 0x19010f 86926489beSMugunthan V N #define CPSW_VERSION_4 0x190112 87549985eeSRichard Cochran 88549985eeSRichard Cochran #define HOST_PORT_NUM 0 89549985eeSRichard Cochran #define SLIVER_SIZE 0x40 90549985eeSRichard Cochran 91549985eeSRichard Cochran #define CPSW1_HOST_PORT_OFFSET 0x028 92549985eeSRichard Cochran #define CPSW1_SLAVE_OFFSET 0x050 93549985eeSRichard Cochran #define CPSW1_SLAVE_SIZE 0x040 94549985eeSRichard Cochran #define CPSW1_CPDMA_OFFSET 0x100 95549985eeSRichard Cochran #define CPSW1_STATERAM_OFFSET 0x200 96d9718546SMugunthan V N #define CPSW1_HW_STATS 0x400 97549985eeSRichard Cochran #define CPSW1_CPTS_OFFSET 0x500 98549985eeSRichard Cochran #define CPSW1_ALE_OFFSET 0x600 99549985eeSRichard Cochran #define CPSW1_SLIVER_OFFSET 0x700 100549985eeSRichard Cochran 101549985eeSRichard Cochran #define CPSW2_HOST_PORT_OFFSET 0x108 102549985eeSRichard Cochran #define CPSW2_SLAVE_OFFSET 0x200 103549985eeSRichard Cochran #define CPSW2_SLAVE_SIZE 0x100 104549985eeSRichard Cochran #define CPSW2_CPDMA_OFFSET 0x800 105d9718546SMugunthan V N #define CPSW2_HW_STATS 0x900 106549985eeSRichard Cochran #define CPSW2_STATERAM_OFFSET 0xa00 107549985eeSRichard Cochran #define CPSW2_CPTS_OFFSET 0xc00 108549985eeSRichard Cochran #define CPSW2_ALE_OFFSET 0xd00 109549985eeSRichard Cochran #define CPSW2_SLIVER_OFFSET 0xd80 110549985eeSRichard Cochran #define CPSW2_BD_OFFSET 0x2000 111549985eeSRichard Cochran 112df828598SMugunthan V N #define CPDMA_RXTHRESH 0x0c0 113df828598SMugunthan V N #define CPDMA_RXFREE 0x0e0 114df828598SMugunthan V N #define CPDMA_TXHDP 0x00 115df828598SMugunthan V N #define CPDMA_RXHDP 0x20 116df828598SMugunthan V N #define CPDMA_TXCP 0x40 117df828598SMugunthan V N #define CPDMA_RXCP 0x60 118df828598SMugunthan V N 119df828598SMugunthan V N #define CPSW_POLL_WEIGHT 64 120df828598SMugunthan V N #define CPSW_MIN_PACKET_SIZE 60 121df828598SMugunthan V N #define CPSW_MAX_PACKET_SIZE (1500 + 14 + 4 + 4) 122df828598SMugunthan V N 123df828598SMugunthan V N #define RX_PRIORITY_MAPPING 0x76543210 124df828598SMugunthan V N #define TX_PRIORITY_MAPPING 0x33221100 125df828598SMugunthan V N #define CPDMA_TX_PRIORITY_MAP 0x76543210 126df828598SMugunthan V N 1273b72c2feSMugunthan V N #define CPSW_VLAN_AWARE BIT(1) 1283b72c2feSMugunthan V N #define CPSW_ALE_VLAN_AWARE 1 1293b72c2feSMugunthan V N 130d9ba8f9eSMugunthan V N #define CPSW_FIFO_NORMAL_MODE (0 << 15) 131d9ba8f9eSMugunthan V N #define CPSW_FIFO_DUAL_MAC_MODE (1 << 15) 132d9ba8f9eSMugunthan V N #define CPSW_FIFO_RATE_LIMIT_MODE (2 << 15) 133d9ba8f9eSMugunthan V N 134ff5b8ef2SMugunthan V N #define CPSW_INTPACEEN (0x3f << 16) 135ff5b8ef2SMugunthan V N #define CPSW_INTPRESCALE_MASK (0x7FF << 0) 136ff5b8ef2SMugunthan V N #define CPSW_CMINTMAX_CNT 63 137ff5b8ef2SMugunthan V N #define CPSW_CMINTMIN_CNT 2 138ff5b8ef2SMugunthan V N #define CPSW_CMINTMAX_INTVL (1000 / CPSW_CMINTMIN_CNT) 139ff5b8ef2SMugunthan V N #define CPSW_CMINTMIN_INTVL ((1000 / CPSW_CMINTMAX_CNT) + 1) 140ff5b8ef2SMugunthan V N 141df828598SMugunthan V N #define cpsw_enable_irq(priv) \ 142df828598SMugunthan V N do { \ 143df828598SMugunthan V N u32 i; \ 144df828598SMugunthan V N for (i = 0; i < priv->num_irqs; i++) \ 145df828598SMugunthan V N enable_irq(priv->irqs_table[i]); \ 1465f47dfb4SJoe Perches } while (0) 147df828598SMugunthan V N #define cpsw_disable_irq(priv) \ 148df828598SMugunthan V N do { \ 149df828598SMugunthan V N u32 i; \ 150df828598SMugunthan V N for (i = 0; i < priv->num_irqs; i++) \ 151df828598SMugunthan V N disable_irq_nosync(priv->irqs_table[i]); \ 1525f47dfb4SJoe Perches } while (0) 153df828598SMugunthan V N 154d3bb9c58SMugunthan V N #define cpsw_slave_index(priv) \ 155d3bb9c58SMugunthan V N ((priv->data.dual_emac) ? priv->emac_port : \ 156d3bb9c58SMugunthan V N priv->data.active_slave) 157d3bb9c58SMugunthan V N 158df828598SMugunthan V N static int debug_level; 159df828598SMugunthan V N module_param(debug_level, int, 0); 160df828598SMugunthan V N MODULE_PARM_DESC(debug_level, "cpsw debug level (NETIF_MSG bits)"); 161df828598SMugunthan V N 162df828598SMugunthan V N static int ale_ageout = 10; 163df828598SMugunthan V N module_param(ale_ageout, int, 0); 164df828598SMugunthan V N MODULE_PARM_DESC(ale_ageout, "cpsw ale ageout interval (seconds)"); 165df828598SMugunthan V N 166df828598SMugunthan V N static int rx_packet_max = CPSW_MAX_PACKET_SIZE; 167df828598SMugunthan V N module_param(rx_packet_max, int, 0); 168df828598SMugunthan V N MODULE_PARM_DESC(rx_packet_max, "maximum receive packet size (bytes)"); 169df828598SMugunthan V N 170996a5c27SRichard Cochran struct cpsw_wr_regs { 171df828598SMugunthan V N u32 id_ver; 172df828598SMugunthan V N u32 soft_reset; 173df828598SMugunthan V N u32 control; 174df828598SMugunthan V N u32 int_control; 175df828598SMugunthan V N u32 rx_thresh_en; 176df828598SMugunthan V N u32 rx_en; 177df828598SMugunthan V N u32 tx_en; 178df828598SMugunthan V N u32 misc_en; 179ff5b8ef2SMugunthan V N u32 mem_allign1[8]; 180ff5b8ef2SMugunthan V N u32 rx_thresh_stat; 181ff5b8ef2SMugunthan V N u32 rx_stat; 182ff5b8ef2SMugunthan V N u32 tx_stat; 183ff5b8ef2SMugunthan V N u32 misc_stat; 184ff5b8ef2SMugunthan V N u32 mem_allign2[8]; 185ff5b8ef2SMugunthan V N u32 rx_imax; 186ff5b8ef2SMugunthan V N u32 tx_imax; 187ff5b8ef2SMugunthan V N 188df828598SMugunthan V N }; 189df828598SMugunthan V N 190996a5c27SRichard Cochran struct cpsw_ss_regs { 191df828598SMugunthan V N u32 id_ver; 192df828598SMugunthan V N u32 control; 193df828598SMugunthan V N u32 soft_reset; 194df828598SMugunthan V N u32 stat_port_en; 195df828598SMugunthan V N u32 ptype; 196bd357af2SRichard Cochran u32 soft_idle; 197bd357af2SRichard Cochran u32 thru_rate; 198bd357af2SRichard Cochran u32 gap_thresh; 199bd357af2SRichard Cochran u32 tx_start_wds; 200bd357af2SRichard Cochran u32 flow_control; 201bd357af2SRichard Cochran u32 vlan_ltype; 202bd357af2SRichard Cochran u32 ts_ltype; 203bd357af2SRichard Cochran u32 dlr_ltype; 204df828598SMugunthan V N }; 205df828598SMugunthan V N 2069750a3adSRichard Cochran /* CPSW_PORT_V1 */ 2079750a3adSRichard Cochran #define CPSW1_MAX_BLKS 0x00 /* Maximum FIFO Blocks */ 2089750a3adSRichard Cochran #define CPSW1_BLK_CNT 0x04 /* FIFO Block Usage Count (Read Only) */ 2099750a3adSRichard Cochran #define CPSW1_TX_IN_CTL 0x08 /* Transmit FIFO Control */ 2109750a3adSRichard Cochran #define CPSW1_PORT_VLAN 0x0c /* VLAN Register */ 2119750a3adSRichard Cochran #define CPSW1_TX_PRI_MAP 0x10 /* Tx Header Priority to Switch Pri Mapping */ 2129750a3adSRichard Cochran #define CPSW1_TS_CTL 0x14 /* Time Sync Control */ 2139750a3adSRichard Cochran #define CPSW1_TS_SEQ_LTYPE 0x18 /* Time Sync Sequence ID Offset and Msg Type */ 2149750a3adSRichard Cochran #define CPSW1_TS_VLAN 0x1c /* Time Sync VLAN1 and VLAN2 */ 2159750a3adSRichard Cochran 2169750a3adSRichard Cochran /* CPSW_PORT_V2 */ 2179750a3adSRichard Cochran #define CPSW2_CONTROL 0x00 /* Control Register */ 2189750a3adSRichard Cochran #define CPSW2_MAX_BLKS 0x08 /* Maximum FIFO Blocks */ 2199750a3adSRichard Cochran #define CPSW2_BLK_CNT 0x0c /* FIFO Block Usage Count (Read Only) */ 2209750a3adSRichard Cochran #define CPSW2_TX_IN_CTL 0x10 /* Transmit FIFO Control */ 2219750a3adSRichard Cochran #define CPSW2_PORT_VLAN 0x14 /* VLAN Register */ 2229750a3adSRichard Cochran #define CPSW2_TX_PRI_MAP 0x18 /* Tx Header Priority to Switch Pri Mapping */ 2239750a3adSRichard Cochran #define CPSW2_TS_SEQ_MTYPE 0x1c /* Time Sync Sequence ID Offset and Msg Type */ 2249750a3adSRichard Cochran 2259750a3adSRichard Cochran /* CPSW_PORT_V1 and V2 */ 2269750a3adSRichard Cochran #define SA_LO 0x20 /* CPGMAC_SL Source Address Low */ 2279750a3adSRichard Cochran #define SA_HI 0x24 /* CPGMAC_SL Source Address High */ 2289750a3adSRichard Cochran #define SEND_PERCENT 0x28 /* Transmit Queue Send Percentages */ 2299750a3adSRichard Cochran 2309750a3adSRichard Cochran /* CPSW_PORT_V2 only */ 2319750a3adSRichard Cochran #define RX_DSCP_PRI_MAP0 0x30 /* Rx DSCP Priority to Rx Packet Mapping */ 2329750a3adSRichard Cochran #define RX_DSCP_PRI_MAP1 0x34 /* Rx DSCP Priority to Rx Packet Mapping */ 2339750a3adSRichard Cochran #define RX_DSCP_PRI_MAP2 0x38 /* Rx DSCP Priority to Rx Packet Mapping */ 2349750a3adSRichard Cochran #define RX_DSCP_PRI_MAP3 0x3c /* Rx DSCP Priority to Rx Packet Mapping */ 2359750a3adSRichard Cochran #define RX_DSCP_PRI_MAP4 0x40 /* Rx DSCP Priority to Rx Packet Mapping */ 2369750a3adSRichard Cochran #define RX_DSCP_PRI_MAP5 0x44 /* Rx DSCP Priority to Rx Packet Mapping */ 2379750a3adSRichard Cochran #define RX_DSCP_PRI_MAP6 0x48 /* Rx DSCP Priority to Rx Packet Mapping */ 2389750a3adSRichard Cochran #define RX_DSCP_PRI_MAP7 0x4c /* Rx DSCP Priority to Rx Packet Mapping */ 2399750a3adSRichard Cochran 2409750a3adSRichard Cochran /* Bit definitions for the CPSW2_CONTROL register */ 2419750a3adSRichard Cochran #define PASS_PRI_TAGGED (1<<24) /* Pass Priority Tagged */ 2429750a3adSRichard Cochran #define VLAN_LTYPE2_EN (1<<21) /* VLAN LTYPE 2 enable */ 2439750a3adSRichard Cochran #define VLAN_LTYPE1_EN (1<<20) /* VLAN LTYPE 1 enable */ 2449750a3adSRichard Cochran #define DSCP_PRI_EN (1<<16) /* DSCP Priority Enable */ 2459750a3adSRichard Cochran #define TS_320 (1<<14) /* Time Sync Dest Port 320 enable */ 2469750a3adSRichard Cochran #define TS_319 (1<<13) /* Time Sync Dest Port 319 enable */ 2479750a3adSRichard Cochran #define TS_132 (1<<12) /* Time Sync Dest IP Addr 132 enable */ 2489750a3adSRichard Cochran #define TS_131 (1<<11) /* Time Sync Dest IP Addr 131 enable */ 2499750a3adSRichard Cochran #define TS_130 (1<<10) /* Time Sync Dest IP Addr 130 enable */ 2509750a3adSRichard Cochran #define TS_129 (1<<9) /* Time Sync Dest IP Addr 129 enable */ 25109c55372SGeorge Cherian #define TS_TTL_NONZERO (1<<8) /* Time Sync Time To Live Non-zero enable */ 25209c55372SGeorge Cherian #define TS_ANNEX_F_EN (1<<6) /* Time Sync Annex F enable */ 2539750a3adSRichard Cochran #define TS_ANNEX_D_EN (1<<4) /* Time Sync Annex D enable */ 2549750a3adSRichard Cochran #define TS_LTYPE2_EN (1<<3) /* Time Sync LTYPE 2 enable */ 2559750a3adSRichard Cochran #define TS_LTYPE1_EN (1<<2) /* Time Sync LTYPE 1 enable */ 2569750a3adSRichard Cochran #define TS_TX_EN (1<<1) /* Time Sync Transmit Enable */ 2579750a3adSRichard Cochran #define TS_RX_EN (1<<0) /* Time Sync Receive Enable */ 2589750a3adSRichard Cochran 25909c55372SGeorge Cherian #define CTRL_V2_TS_BITS \ 26009c55372SGeorge Cherian (TS_320 | TS_319 | TS_132 | TS_131 | TS_130 | TS_129 |\ 26109c55372SGeorge Cherian TS_TTL_NONZERO | TS_ANNEX_D_EN | TS_LTYPE1_EN) 2629750a3adSRichard Cochran 26309c55372SGeorge Cherian #define CTRL_V2_ALL_TS_MASK (CTRL_V2_TS_BITS | TS_TX_EN | TS_RX_EN) 26409c55372SGeorge Cherian #define CTRL_V2_TX_TS_BITS (CTRL_V2_TS_BITS | TS_TX_EN) 26509c55372SGeorge Cherian #define CTRL_V2_RX_TS_BITS (CTRL_V2_TS_BITS | TS_RX_EN) 26609c55372SGeorge Cherian 26709c55372SGeorge Cherian 26809c55372SGeorge Cherian #define CTRL_V3_TS_BITS \ 26909c55372SGeorge Cherian (TS_320 | TS_319 | TS_132 | TS_131 | TS_130 | TS_129 |\ 27009c55372SGeorge Cherian TS_TTL_NONZERO | TS_ANNEX_F_EN | TS_ANNEX_D_EN |\ 27109c55372SGeorge Cherian TS_LTYPE1_EN) 27209c55372SGeorge Cherian 27309c55372SGeorge Cherian #define CTRL_V3_ALL_TS_MASK (CTRL_V3_TS_BITS | TS_TX_EN | TS_RX_EN) 27409c55372SGeorge Cherian #define CTRL_V3_TX_TS_BITS (CTRL_V3_TS_BITS | TS_TX_EN) 27509c55372SGeorge Cherian #define CTRL_V3_RX_TS_BITS (CTRL_V3_TS_BITS | TS_RX_EN) 2769750a3adSRichard Cochran 2779750a3adSRichard Cochran /* Bit definitions for the CPSW2_TS_SEQ_MTYPE register */ 2789750a3adSRichard Cochran #define TS_SEQ_ID_OFFSET_SHIFT (16) /* Time Sync Sequence ID Offset */ 2799750a3adSRichard Cochran #define TS_SEQ_ID_OFFSET_MASK (0x3f) 2809750a3adSRichard Cochran #define TS_MSG_TYPE_EN_SHIFT (0) /* Time Sync Message Type Enable */ 2819750a3adSRichard Cochran #define TS_MSG_TYPE_EN_MASK (0xffff) 2829750a3adSRichard Cochran 2839750a3adSRichard Cochran /* The PTP event messages - Sync, Delay_Req, Pdelay_Req, and Pdelay_Resp. */ 2849750a3adSRichard Cochran #define EVENT_MSG_BITS ((1<<0) | (1<<1) | (1<<2) | (1<<3)) 285df828598SMugunthan V N 2862e5b38abSRichard Cochran /* Bit definitions for the CPSW1_TS_CTL register */ 2872e5b38abSRichard Cochran #define CPSW_V1_TS_RX_EN BIT(0) 2882e5b38abSRichard Cochran #define CPSW_V1_TS_TX_EN BIT(4) 2892e5b38abSRichard Cochran #define CPSW_V1_MSG_TYPE_OFS 16 2902e5b38abSRichard Cochran 2912e5b38abSRichard Cochran /* Bit definitions for the CPSW1_TS_SEQ_LTYPE register */ 2922e5b38abSRichard Cochran #define CPSW_V1_SEQ_ID_OFS_SHIFT 16 2932e5b38abSRichard Cochran 294df828598SMugunthan V N struct cpsw_host_regs { 295df828598SMugunthan V N u32 max_blks; 296df828598SMugunthan V N u32 blk_cnt; 297d9ba8f9eSMugunthan V N u32 tx_in_ctl; 298df828598SMugunthan V N u32 port_vlan; 299df828598SMugunthan V N u32 tx_pri_map; 300df828598SMugunthan V N u32 cpdma_tx_pri_map; 301df828598SMugunthan V N u32 cpdma_rx_chan_map; 302df828598SMugunthan V N }; 303df828598SMugunthan V N 304df828598SMugunthan V N struct cpsw_sliver_regs { 305df828598SMugunthan V N u32 id_ver; 306df828598SMugunthan V N u32 mac_control; 307df828598SMugunthan V N u32 mac_status; 308df828598SMugunthan V N u32 soft_reset; 309df828598SMugunthan V N u32 rx_maxlen; 310df828598SMugunthan V N u32 __reserved_0; 311df828598SMugunthan V N u32 rx_pause; 312df828598SMugunthan V N u32 tx_pause; 313df828598SMugunthan V N u32 __reserved_1; 314df828598SMugunthan V N u32 rx_pri_map; 315df828598SMugunthan V N }; 316df828598SMugunthan V N 317d9718546SMugunthan V N struct cpsw_hw_stats { 318d9718546SMugunthan V N u32 rxgoodframes; 319d9718546SMugunthan V N u32 rxbroadcastframes; 320d9718546SMugunthan V N u32 rxmulticastframes; 321d9718546SMugunthan V N u32 rxpauseframes; 322d9718546SMugunthan V N u32 rxcrcerrors; 323d9718546SMugunthan V N u32 rxaligncodeerrors; 324d9718546SMugunthan V N u32 rxoversizedframes; 325d9718546SMugunthan V N u32 rxjabberframes; 326d9718546SMugunthan V N u32 rxundersizedframes; 327d9718546SMugunthan V N u32 rxfragments; 328d9718546SMugunthan V N u32 __pad_0[2]; 329d9718546SMugunthan V N u32 rxoctets; 330d9718546SMugunthan V N u32 txgoodframes; 331d9718546SMugunthan V N u32 txbroadcastframes; 332d9718546SMugunthan V N u32 txmulticastframes; 333d9718546SMugunthan V N u32 txpauseframes; 334d9718546SMugunthan V N u32 txdeferredframes; 335d9718546SMugunthan V N u32 txcollisionframes; 336d9718546SMugunthan V N u32 txsinglecollframes; 337d9718546SMugunthan V N u32 txmultcollframes; 338d9718546SMugunthan V N u32 txexcessivecollisions; 339d9718546SMugunthan V N u32 txlatecollisions; 340d9718546SMugunthan V N u32 txunderrun; 341d9718546SMugunthan V N u32 txcarriersenseerrors; 342d9718546SMugunthan V N u32 txoctets; 343d9718546SMugunthan V N u32 octetframes64; 344d9718546SMugunthan V N u32 octetframes65t127; 345d9718546SMugunthan V N u32 octetframes128t255; 346d9718546SMugunthan V N u32 octetframes256t511; 347d9718546SMugunthan V N u32 octetframes512t1023; 348d9718546SMugunthan V N u32 octetframes1024tup; 349d9718546SMugunthan V N u32 netoctets; 350d9718546SMugunthan V N u32 rxsofoverruns; 351d9718546SMugunthan V N u32 rxmofoverruns; 352d9718546SMugunthan V N u32 rxdmaoverruns; 353d9718546SMugunthan V N }; 354d9718546SMugunthan V N 355df828598SMugunthan V N struct cpsw_slave { 3569750a3adSRichard Cochran void __iomem *regs; 357df828598SMugunthan V N struct cpsw_sliver_regs __iomem *sliver; 358df828598SMugunthan V N int slave_num; 359df828598SMugunthan V N u32 mac_control; 360df828598SMugunthan V N struct cpsw_slave_data *data; 361df828598SMugunthan V N struct phy_device *phy; 362d9ba8f9eSMugunthan V N struct net_device *ndev; 363d9ba8f9eSMugunthan V N u32 port_vlan; 364d9ba8f9eSMugunthan V N u32 open_stat; 365df828598SMugunthan V N }; 366df828598SMugunthan V N 3679750a3adSRichard Cochran static inline u32 slave_read(struct cpsw_slave *slave, u32 offset) 3689750a3adSRichard Cochran { 3699750a3adSRichard Cochran return __raw_readl(slave->regs + offset); 3709750a3adSRichard Cochran } 3719750a3adSRichard Cochran 3729750a3adSRichard Cochran static inline void slave_write(struct cpsw_slave *slave, u32 val, u32 offset) 3739750a3adSRichard Cochran { 3749750a3adSRichard Cochran __raw_writel(val, slave->regs + offset); 3759750a3adSRichard Cochran } 3769750a3adSRichard Cochran 377df828598SMugunthan V N struct cpsw_priv { 378df828598SMugunthan V N spinlock_t lock; 379df828598SMugunthan V N struct platform_device *pdev; 380df828598SMugunthan V N struct net_device *ndev; 381df828598SMugunthan V N struct napi_struct napi; 382df828598SMugunthan V N struct device *dev; 383df828598SMugunthan V N struct cpsw_platform_data data; 384996a5c27SRichard Cochran struct cpsw_ss_regs __iomem *regs; 385996a5c27SRichard Cochran struct cpsw_wr_regs __iomem *wr_regs; 386d9718546SMugunthan V N u8 __iomem *hw_stats; 387df828598SMugunthan V N struct cpsw_host_regs __iomem *host_port_regs; 388df828598SMugunthan V N u32 msg_enable; 389e90cfac6SRichard Cochran u32 version; 390ff5b8ef2SMugunthan V N u32 coal_intvl; 391ff5b8ef2SMugunthan V N u32 bus_freq_mhz; 392df828598SMugunthan V N int rx_packet_max; 393df828598SMugunthan V N int host_port; 394df828598SMugunthan V N struct clk *clk; 395df828598SMugunthan V N u8 mac_addr[ETH_ALEN]; 396df828598SMugunthan V N struct cpsw_slave *slaves; 397df828598SMugunthan V N struct cpdma_ctlr *dma; 398df828598SMugunthan V N struct cpdma_chan *txch, *rxch; 399df828598SMugunthan V N struct cpsw_ale *ale; 4001923d6e4SMugunthan V N bool rx_pause; 4011923d6e4SMugunthan V N bool tx_pause; 402df828598SMugunthan V N /* snapshot of IRQ numbers */ 403df828598SMugunthan V N u32 irqs_table[4]; 404df828598SMugunthan V N u32 num_irqs; 405a11fbba9SSebastian Siewior bool irq_enabled; 4069232b16dSMugunthan V N struct cpts *cpts; 407d9ba8f9eSMugunthan V N u32 emac_port; 408df828598SMugunthan V N }; 409df828598SMugunthan V N 410d9718546SMugunthan V N struct cpsw_stats { 411d9718546SMugunthan V N char stat_string[ETH_GSTRING_LEN]; 412d9718546SMugunthan V N int type; 413d9718546SMugunthan V N int sizeof_stat; 414d9718546SMugunthan V N int stat_offset; 415d9718546SMugunthan V N }; 416d9718546SMugunthan V N 417d9718546SMugunthan V N enum { 418d9718546SMugunthan V N CPSW_STATS, 419d9718546SMugunthan V N CPDMA_RX_STATS, 420d9718546SMugunthan V N CPDMA_TX_STATS, 421d9718546SMugunthan V N }; 422d9718546SMugunthan V N 423d9718546SMugunthan V N #define CPSW_STAT(m) CPSW_STATS, \ 424d9718546SMugunthan V N sizeof(((struct cpsw_hw_stats *)0)->m), \ 425d9718546SMugunthan V N offsetof(struct cpsw_hw_stats, m) 426d9718546SMugunthan V N #define CPDMA_RX_STAT(m) CPDMA_RX_STATS, \ 427d9718546SMugunthan V N sizeof(((struct cpdma_chan_stats *)0)->m), \ 428d9718546SMugunthan V N offsetof(struct cpdma_chan_stats, m) 429d9718546SMugunthan V N #define CPDMA_TX_STAT(m) CPDMA_TX_STATS, \ 430d9718546SMugunthan V N sizeof(((struct cpdma_chan_stats *)0)->m), \ 431d9718546SMugunthan V N offsetof(struct cpdma_chan_stats, m) 432d9718546SMugunthan V N 433d9718546SMugunthan V N static const struct cpsw_stats cpsw_gstrings_stats[] = { 434d9718546SMugunthan V N { "Good Rx Frames", CPSW_STAT(rxgoodframes) }, 435d9718546SMugunthan V N { "Broadcast Rx Frames", CPSW_STAT(rxbroadcastframes) }, 436d9718546SMugunthan V N { "Multicast Rx Frames", CPSW_STAT(rxmulticastframes) }, 437d9718546SMugunthan V N { "Pause Rx Frames", CPSW_STAT(rxpauseframes) }, 438d9718546SMugunthan V N { "Rx CRC Errors", CPSW_STAT(rxcrcerrors) }, 439d9718546SMugunthan V N { "Rx Align/Code Errors", CPSW_STAT(rxaligncodeerrors) }, 440d9718546SMugunthan V N { "Oversize Rx Frames", CPSW_STAT(rxoversizedframes) }, 441d9718546SMugunthan V N { "Rx Jabbers", CPSW_STAT(rxjabberframes) }, 442d9718546SMugunthan V N { "Undersize (Short) Rx Frames", CPSW_STAT(rxundersizedframes) }, 443d9718546SMugunthan V N { "Rx Fragments", CPSW_STAT(rxfragments) }, 444d9718546SMugunthan V N { "Rx Octets", CPSW_STAT(rxoctets) }, 445d9718546SMugunthan V N { "Good Tx Frames", CPSW_STAT(txgoodframes) }, 446d9718546SMugunthan V N { "Broadcast Tx Frames", CPSW_STAT(txbroadcastframes) }, 447d9718546SMugunthan V N { "Multicast Tx Frames", CPSW_STAT(txmulticastframes) }, 448d9718546SMugunthan V N { "Pause Tx Frames", CPSW_STAT(txpauseframes) }, 449d9718546SMugunthan V N { "Deferred Tx Frames", CPSW_STAT(txdeferredframes) }, 450d9718546SMugunthan V N { "Collisions", CPSW_STAT(txcollisionframes) }, 451d9718546SMugunthan V N { "Single Collision Tx Frames", CPSW_STAT(txsinglecollframes) }, 452d9718546SMugunthan V N { "Multiple Collision Tx Frames", CPSW_STAT(txmultcollframes) }, 453d9718546SMugunthan V N { "Excessive Collisions", CPSW_STAT(txexcessivecollisions) }, 454d9718546SMugunthan V N { "Late Collisions", CPSW_STAT(txlatecollisions) }, 455d9718546SMugunthan V N { "Tx Underrun", CPSW_STAT(txunderrun) }, 456d9718546SMugunthan V N { "Carrier Sense Errors", CPSW_STAT(txcarriersenseerrors) }, 457d9718546SMugunthan V N { "Tx Octets", CPSW_STAT(txoctets) }, 458d9718546SMugunthan V N { "Rx + Tx 64 Octet Frames", CPSW_STAT(octetframes64) }, 459d9718546SMugunthan V N { "Rx + Tx 65-127 Octet Frames", CPSW_STAT(octetframes65t127) }, 460d9718546SMugunthan V N { "Rx + Tx 128-255 Octet Frames", CPSW_STAT(octetframes128t255) }, 461d9718546SMugunthan V N { "Rx + Tx 256-511 Octet Frames", CPSW_STAT(octetframes256t511) }, 462d9718546SMugunthan V N { "Rx + Tx 512-1023 Octet Frames", CPSW_STAT(octetframes512t1023) }, 463d9718546SMugunthan V N { "Rx + Tx 1024-Up Octet Frames", CPSW_STAT(octetframes1024tup) }, 464d9718546SMugunthan V N { "Net Octets", CPSW_STAT(netoctets) }, 465d9718546SMugunthan V N { "Rx Start of Frame Overruns", CPSW_STAT(rxsofoverruns) }, 466d9718546SMugunthan V N { "Rx Middle of Frame Overruns", CPSW_STAT(rxmofoverruns) }, 467d9718546SMugunthan V N { "Rx DMA Overruns", CPSW_STAT(rxdmaoverruns) }, 468d9718546SMugunthan V N { "Rx DMA chan: head_enqueue", CPDMA_RX_STAT(head_enqueue) }, 469d9718546SMugunthan V N { "Rx DMA chan: tail_enqueue", CPDMA_RX_STAT(tail_enqueue) }, 470d9718546SMugunthan V N { "Rx DMA chan: pad_enqueue", CPDMA_RX_STAT(pad_enqueue) }, 471d9718546SMugunthan V N { "Rx DMA chan: misqueued", CPDMA_RX_STAT(misqueued) }, 472d9718546SMugunthan V N { "Rx DMA chan: desc_alloc_fail", CPDMA_RX_STAT(desc_alloc_fail) }, 473d9718546SMugunthan V N { "Rx DMA chan: pad_alloc_fail", CPDMA_RX_STAT(pad_alloc_fail) }, 474d9718546SMugunthan V N { "Rx DMA chan: runt_receive_buf", CPDMA_RX_STAT(runt_receive_buff) }, 475d9718546SMugunthan V N { "Rx DMA chan: runt_transmit_buf", CPDMA_RX_STAT(runt_transmit_buff) }, 476d9718546SMugunthan V N { "Rx DMA chan: empty_dequeue", CPDMA_RX_STAT(empty_dequeue) }, 477d9718546SMugunthan V N { "Rx DMA chan: busy_dequeue", CPDMA_RX_STAT(busy_dequeue) }, 478d9718546SMugunthan V N { "Rx DMA chan: good_dequeue", CPDMA_RX_STAT(good_dequeue) }, 479d9718546SMugunthan V N { "Rx DMA chan: requeue", CPDMA_RX_STAT(requeue) }, 480d9718546SMugunthan V N { "Rx DMA chan: teardown_dequeue", CPDMA_RX_STAT(teardown_dequeue) }, 481d9718546SMugunthan V N { "Tx DMA chan: head_enqueue", CPDMA_TX_STAT(head_enqueue) }, 482d9718546SMugunthan V N { "Tx DMA chan: tail_enqueue", CPDMA_TX_STAT(tail_enqueue) }, 483d9718546SMugunthan V N { "Tx DMA chan: pad_enqueue", CPDMA_TX_STAT(pad_enqueue) }, 484d9718546SMugunthan V N { "Tx DMA chan: misqueued", CPDMA_TX_STAT(misqueued) }, 485d9718546SMugunthan V N { "Tx DMA chan: desc_alloc_fail", CPDMA_TX_STAT(desc_alloc_fail) }, 486d9718546SMugunthan V N { "Tx DMA chan: pad_alloc_fail", CPDMA_TX_STAT(pad_alloc_fail) }, 487d9718546SMugunthan V N { "Tx DMA chan: runt_receive_buf", CPDMA_TX_STAT(runt_receive_buff) }, 488d9718546SMugunthan V N { "Tx DMA chan: runt_transmit_buf", CPDMA_TX_STAT(runt_transmit_buff) }, 489d9718546SMugunthan V N { "Tx DMA chan: empty_dequeue", CPDMA_TX_STAT(empty_dequeue) }, 490d9718546SMugunthan V N { "Tx DMA chan: busy_dequeue", CPDMA_TX_STAT(busy_dequeue) }, 491d9718546SMugunthan V N { "Tx DMA chan: good_dequeue", CPDMA_TX_STAT(good_dequeue) }, 492d9718546SMugunthan V N { "Tx DMA chan: requeue", CPDMA_TX_STAT(requeue) }, 493d9718546SMugunthan V N { "Tx DMA chan: teardown_dequeue", CPDMA_TX_STAT(teardown_dequeue) }, 494d9718546SMugunthan V N }; 495d9718546SMugunthan V N 496d9718546SMugunthan V N #define CPSW_STATS_LEN ARRAY_SIZE(cpsw_gstrings_stats) 497d9718546SMugunthan V N 498df828598SMugunthan V N #define napi_to_priv(napi) container_of(napi, struct cpsw_priv, napi) 499df828598SMugunthan V N #define for_each_slave(priv, func, arg...) \ 500df828598SMugunthan V N do { \ 5016e6ceaedSSebastian Siewior struct cpsw_slave *slave; \ 5026e6ceaedSSebastian Siewior int n; \ 503d9ba8f9eSMugunthan V N if (priv->data.dual_emac) \ 504d9ba8f9eSMugunthan V N (func)((priv)->slaves + priv->emac_port, ##arg);\ 505d9ba8f9eSMugunthan V N else \ 5066e6ceaedSSebastian Siewior for (n = (priv)->data.slaves, \ 5076e6ceaedSSebastian Siewior slave = (priv)->slaves; \ 5086e6ceaedSSebastian Siewior n; n--) \ 5096e6ceaedSSebastian Siewior (func)(slave++, ##arg); \ 510df828598SMugunthan V N } while (0) 511d9ba8f9eSMugunthan V N #define cpsw_get_slave_ndev(priv, __slave_no__) \ 512d9ba8f9eSMugunthan V N (priv->slaves[__slave_no__].ndev) 513d9ba8f9eSMugunthan V N #define cpsw_get_slave_priv(priv, __slave_no__) \ 514d9ba8f9eSMugunthan V N ((priv->slaves[__slave_no__].ndev) ? \ 515d9ba8f9eSMugunthan V N netdev_priv(priv->slaves[__slave_no__].ndev) : NULL) \ 516d9ba8f9eSMugunthan V N 517d9ba8f9eSMugunthan V N #define cpsw_dual_emac_src_port_detect(status, priv, ndev, skb) \ 518d9ba8f9eSMugunthan V N do { \ 519d9ba8f9eSMugunthan V N if (!priv->data.dual_emac) \ 520d9ba8f9eSMugunthan V N break; \ 521d9ba8f9eSMugunthan V N if (CPDMA_RX_SOURCE_PORT(status) == 1) { \ 522d9ba8f9eSMugunthan V N ndev = cpsw_get_slave_ndev(priv, 0); \ 523d9ba8f9eSMugunthan V N priv = netdev_priv(ndev); \ 524d9ba8f9eSMugunthan V N skb->dev = ndev; \ 525d9ba8f9eSMugunthan V N } else if (CPDMA_RX_SOURCE_PORT(status) == 2) { \ 526d9ba8f9eSMugunthan V N ndev = cpsw_get_slave_ndev(priv, 1); \ 527d9ba8f9eSMugunthan V N priv = netdev_priv(ndev); \ 528d9ba8f9eSMugunthan V N skb->dev = ndev; \ 529d9ba8f9eSMugunthan V N } \ 530d9ba8f9eSMugunthan V N } while (0) 531d9ba8f9eSMugunthan V N #define cpsw_add_mcast(priv, addr) \ 532d9ba8f9eSMugunthan V N do { \ 533d9ba8f9eSMugunthan V N if (priv->data.dual_emac) { \ 534d9ba8f9eSMugunthan V N struct cpsw_slave *slave = priv->slaves + \ 535d9ba8f9eSMugunthan V N priv->emac_port; \ 536d9ba8f9eSMugunthan V N int slave_port = cpsw_get_slave_port(priv, \ 537d9ba8f9eSMugunthan V N slave->slave_num); \ 538d9ba8f9eSMugunthan V N cpsw_ale_add_mcast(priv->ale, addr, \ 539d9ba8f9eSMugunthan V N 1 << slave_port | 1 << priv->host_port, \ 540d9ba8f9eSMugunthan V N ALE_VLAN, slave->port_vlan, 0); \ 541d9ba8f9eSMugunthan V N } else { \ 542d9ba8f9eSMugunthan V N cpsw_ale_add_mcast(priv->ale, addr, \ 543d9ba8f9eSMugunthan V N ALE_ALL_PORTS << priv->host_port, \ 544d9ba8f9eSMugunthan V N 0, 0, 0); \ 545d9ba8f9eSMugunthan V N } \ 546d9ba8f9eSMugunthan V N } while (0) 547d9ba8f9eSMugunthan V N 548d9ba8f9eSMugunthan V N static inline int cpsw_get_slave_port(struct cpsw_priv *priv, u32 slave_num) 549d9ba8f9eSMugunthan V N { 550d9ba8f9eSMugunthan V N if (priv->host_port == 0) 551d9ba8f9eSMugunthan V N return slave_num + 1; 552d9ba8f9eSMugunthan V N else 553d9ba8f9eSMugunthan V N return slave_num; 554d9ba8f9eSMugunthan V N } 555df828598SMugunthan V N 5560cd8f9ccSMugunthan V N static void cpsw_set_promiscious(struct net_device *ndev, bool enable) 5570cd8f9ccSMugunthan V N { 5580cd8f9ccSMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 5590cd8f9ccSMugunthan V N struct cpsw_ale *ale = priv->ale; 5600cd8f9ccSMugunthan V N int i; 5610cd8f9ccSMugunthan V N 5620cd8f9ccSMugunthan V N if (priv->data.dual_emac) { 5630cd8f9ccSMugunthan V N bool flag = false; 5640cd8f9ccSMugunthan V N 5650cd8f9ccSMugunthan V N /* Enabling promiscuous mode for one interface will be 5660cd8f9ccSMugunthan V N * common for both the interface as the interface shares 5670cd8f9ccSMugunthan V N * the same hardware resource. 5680cd8f9ccSMugunthan V N */ 5690d961b3bSHeiko Schocher for (i = 0; i < priv->data.slaves; i++) 5700cd8f9ccSMugunthan V N if (priv->slaves[i].ndev->flags & IFF_PROMISC) 5710cd8f9ccSMugunthan V N flag = true; 5720cd8f9ccSMugunthan V N 5730cd8f9ccSMugunthan V N if (!enable && flag) { 5740cd8f9ccSMugunthan V N enable = true; 5750cd8f9ccSMugunthan V N dev_err(&ndev->dev, "promiscuity not disabled as the other interface is still in promiscuity mode\n"); 5760cd8f9ccSMugunthan V N } 5770cd8f9ccSMugunthan V N 5780cd8f9ccSMugunthan V N if (enable) { 5790cd8f9ccSMugunthan V N /* Enable Bypass */ 5800cd8f9ccSMugunthan V N cpsw_ale_control_set(ale, 0, ALE_BYPASS, 1); 5810cd8f9ccSMugunthan V N 5820cd8f9ccSMugunthan V N dev_dbg(&ndev->dev, "promiscuity enabled\n"); 5830cd8f9ccSMugunthan V N } else { 5840cd8f9ccSMugunthan V N /* Disable Bypass */ 5850cd8f9ccSMugunthan V N cpsw_ale_control_set(ale, 0, ALE_BYPASS, 0); 5860cd8f9ccSMugunthan V N dev_dbg(&ndev->dev, "promiscuity disabled\n"); 5870cd8f9ccSMugunthan V N } 5880cd8f9ccSMugunthan V N } else { 5890cd8f9ccSMugunthan V N if (enable) { 5900cd8f9ccSMugunthan V N unsigned long timeout = jiffies + HZ; 5910cd8f9ccSMugunthan V N 5920cd8f9ccSMugunthan V N /* Disable Learn for all ports */ 5930d961b3bSHeiko Schocher for (i = 0; i < priv->data.slaves; i++) { 5940cd8f9ccSMugunthan V N cpsw_ale_control_set(ale, i, 5950cd8f9ccSMugunthan V N ALE_PORT_NOLEARN, 1); 5960cd8f9ccSMugunthan V N cpsw_ale_control_set(ale, i, 5970cd8f9ccSMugunthan V N ALE_PORT_NO_SA_UPDATE, 1); 5980cd8f9ccSMugunthan V N } 5990cd8f9ccSMugunthan V N 6000cd8f9ccSMugunthan V N /* Clear All Untouched entries */ 6010cd8f9ccSMugunthan V N cpsw_ale_control_set(ale, 0, ALE_AGEOUT, 1); 6020cd8f9ccSMugunthan V N do { 6030cd8f9ccSMugunthan V N cpu_relax(); 6040cd8f9ccSMugunthan V N if (cpsw_ale_control_get(ale, 0, ALE_AGEOUT)) 6050cd8f9ccSMugunthan V N break; 6060cd8f9ccSMugunthan V N } while (time_after(timeout, jiffies)); 6070cd8f9ccSMugunthan V N cpsw_ale_control_set(ale, 0, ALE_AGEOUT, 1); 6080cd8f9ccSMugunthan V N 6090cd8f9ccSMugunthan V N /* Clear all mcast from ALE */ 6100cd8f9ccSMugunthan V N cpsw_ale_flush_multicast(ale, ALE_ALL_PORTS << 6110cd8f9ccSMugunthan V N priv->host_port); 6120cd8f9ccSMugunthan V N 6130cd8f9ccSMugunthan V N /* Flood All Unicast Packets to Host port */ 6140cd8f9ccSMugunthan V N cpsw_ale_control_set(ale, 0, ALE_P0_UNI_FLOOD, 1); 6150cd8f9ccSMugunthan V N dev_dbg(&ndev->dev, "promiscuity enabled\n"); 6160cd8f9ccSMugunthan V N } else { 6170cd8f9ccSMugunthan V N /* Flood All Unicast Packets to Host port */ 6180cd8f9ccSMugunthan V N cpsw_ale_control_set(ale, 0, ALE_P0_UNI_FLOOD, 0); 6190cd8f9ccSMugunthan V N 6200cd8f9ccSMugunthan V N /* Enable Learn for all ports */ 6210d961b3bSHeiko Schocher for (i = 0; i < priv->data.slaves; i++) { 6220cd8f9ccSMugunthan V N cpsw_ale_control_set(ale, i, 6230cd8f9ccSMugunthan V N ALE_PORT_NOLEARN, 0); 6240cd8f9ccSMugunthan V N cpsw_ale_control_set(ale, i, 6250cd8f9ccSMugunthan V N ALE_PORT_NO_SA_UPDATE, 0); 6260cd8f9ccSMugunthan V N } 6270cd8f9ccSMugunthan V N dev_dbg(&ndev->dev, "promiscuity disabled\n"); 6280cd8f9ccSMugunthan V N } 6290cd8f9ccSMugunthan V N } 6300cd8f9ccSMugunthan V N } 6310cd8f9ccSMugunthan V N 6325c50a856SMugunthan V N static void cpsw_ndo_set_rx_mode(struct net_device *ndev) 6335c50a856SMugunthan V N { 6345c50a856SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 6355c50a856SMugunthan V N 6365c50a856SMugunthan V N if (ndev->flags & IFF_PROMISC) { 6375c50a856SMugunthan V N /* Enable promiscuous mode */ 6380cd8f9ccSMugunthan V N cpsw_set_promiscious(ndev, true); 6395c50a856SMugunthan V N return; 6400cd8f9ccSMugunthan V N } else { 6410cd8f9ccSMugunthan V N /* Disable promiscuous mode */ 6420cd8f9ccSMugunthan V N cpsw_set_promiscious(ndev, false); 6435c50a856SMugunthan V N } 6445c50a856SMugunthan V N 6455c50a856SMugunthan V N /* Clear all mcast from ALE */ 6465c50a856SMugunthan V N cpsw_ale_flush_multicast(priv->ale, ALE_ALL_PORTS << priv->host_port); 6475c50a856SMugunthan V N 6485c50a856SMugunthan V N if (!netdev_mc_empty(ndev)) { 6495c50a856SMugunthan V N struct netdev_hw_addr *ha; 6505c50a856SMugunthan V N 6515c50a856SMugunthan V N /* program multicast address list into ALE register */ 6525c50a856SMugunthan V N netdev_for_each_mc_addr(ha, ndev) { 653d9ba8f9eSMugunthan V N cpsw_add_mcast(priv, (u8 *)ha->addr); 6545c50a856SMugunthan V N } 6555c50a856SMugunthan V N } 6565c50a856SMugunthan V N } 6575c50a856SMugunthan V N 658df828598SMugunthan V N static void cpsw_intr_enable(struct cpsw_priv *priv) 659df828598SMugunthan V N { 660996a5c27SRichard Cochran __raw_writel(0xFF, &priv->wr_regs->tx_en); 661996a5c27SRichard Cochran __raw_writel(0xFF, &priv->wr_regs->rx_en); 662df828598SMugunthan V N 663df828598SMugunthan V N cpdma_ctlr_int_ctrl(priv->dma, true); 664df828598SMugunthan V N return; 665df828598SMugunthan V N } 666df828598SMugunthan V N 667df828598SMugunthan V N static void cpsw_intr_disable(struct cpsw_priv *priv) 668df828598SMugunthan V N { 669996a5c27SRichard Cochran __raw_writel(0, &priv->wr_regs->tx_en); 670996a5c27SRichard Cochran __raw_writel(0, &priv->wr_regs->rx_en); 671df828598SMugunthan V N 672df828598SMugunthan V N cpdma_ctlr_int_ctrl(priv->dma, false); 673df828598SMugunthan V N return; 674df828598SMugunthan V N } 675df828598SMugunthan V N 6761a3b5056SOlof Johansson static void cpsw_tx_handler(void *token, int len, int status) 677df828598SMugunthan V N { 678df828598SMugunthan V N struct sk_buff *skb = token; 679df828598SMugunthan V N struct net_device *ndev = skb->dev; 680df828598SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 681df828598SMugunthan V N 682fae50823SMugunthan V N /* Check whether the queue is stopped due to stalled tx dma, if the 683fae50823SMugunthan V N * queue is stopped then start the queue as we have free desc for tx 684fae50823SMugunthan V N */ 685df828598SMugunthan V N if (unlikely(netif_queue_stopped(ndev))) 686b56d6b3fSMugunthan V N netif_wake_queue(ndev); 6879232b16dSMugunthan V N cpts_tx_timestamp(priv->cpts, skb); 6888dc43ddcSTobias Klauser ndev->stats.tx_packets++; 6898dc43ddcSTobias Klauser ndev->stats.tx_bytes += len; 690df828598SMugunthan V N dev_kfree_skb_any(skb); 691df828598SMugunthan V N } 692df828598SMugunthan V N 6931a3b5056SOlof Johansson static void cpsw_rx_handler(void *token, int len, int status) 694df828598SMugunthan V N { 695df828598SMugunthan V N struct sk_buff *skb = token; 696b4727e69SSebastian Siewior struct sk_buff *new_skb; 697df828598SMugunthan V N struct net_device *ndev = skb->dev; 698df828598SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 699df828598SMugunthan V N int ret = 0; 700df828598SMugunthan V N 701d9ba8f9eSMugunthan V N cpsw_dual_emac_src_port_detect(status, priv, ndev, skb); 702d9ba8f9eSMugunthan V N 70316e5c57dSMugunthan V N if (unlikely(status < 0) || unlikely(!netif_running(ndev))) { 704a0e2c822SMugunthan V N bool ndev_status = false; 705a0e2c822SMugunthan V N struct cpsw_slave *slave = priv->slaves; 706a0e2c822SMugunthan V N int n; 707a0e2c822SMugunthan V N 708a0e2c822SMugunthan V N if (priv->data.dual_emac) { 709a0e2c822SMugunthan V N /* In dual emac mode check for all interfaces */ 710a0e2c822SMugunthan V N for (n = priv->data.slaves; n; n--, slave++) 711a0e2c822SMugunthan V N if (netif_running(slave->ndev)) 712a0e2c822SMugunthan V N ndev_status = true; 713a0e2c822SMugunthan V N } 714a0e2c822SMugunthan V N 715a0e2c822SMugunthan V N if (ndev_status && (status >= 0)) { 716a0e2c822SMugunthan V N /* The packet received is for the interface which 717a0e2c822SMugunthan V N * is already down and the other interface is up 718a0e2c822SMugunthan V N * and running, intead of freeing which results 719a0e2c822SMugunthan V N * in reducing of the number of rx descriptor in 720a0e2c822SMugunthan V N * DMA engine, requeue skb back to cpdma. 721a0e2c822SMugunthan V N */ 722a0e2c822SMugunthan V N new_skb = skb; 723a0e2c822SMugunthan V N goto requeue; 724a0e2c822SMugunthan V N } 725a0e2c822SMugunthan V N 726b4727e69SSebastian Siewior /* the interface is going down, skbs are purged */ 727df828598SMugunthan V N dev_kfree_skb_any(skb); 728df828598SMugunthan V N return; 729df828598SMugunthan V N } 730b4727e69SSebastian Siewior 731b4727e69SSebastian Siewior new_skb = netdev_alloc_skb_ip_align(ndev, priv->rx_packet_max); 732b4727e69SSebastian Siewior if (new_skb) { 733df828598SMugunthan V N skb_put(skb, len); 7349232b16dSMugunthan V N cpts_rx_timestamp(priv->cpts, skb); 735df828598SMugunthan V N skb->protocol = eth_type_trans(skb, ndev); 736df828598SMugunthan V N netif_receive_skb(skb); 7378dc43ddcSTobias Klauser ndev->stats.rx_bytes += len; 7388dc43ddcSTobias Klauser ndev->stats.rx_packets++; 739b4727e69SSebastian Siewior } else { 7408dc43ddcSTobias Klauser ndev->stats.rx_dropped++; 741b4727e69SSebastian Siewior new_skb = skb; 742df828598SMugunthan V N } 743df828598SMugunthan V N 744a0e2c822SMugunthan V N requeue: 745b4727e69SSebastian Siewior ret = cpdma_chan_submit(priv->rxch, new_skb, new_skb->data, 746b4727e69SSebastian Siewior skb_tailroom(new_skb), 0); 747b4727e69SSebastian Siewior if (WARN_ON(ret < 0)) 748b4727e69SSebastian Siewior dev_kfree_skb_any(new_skb); 749df828598SMugunthan V N } 750df828598SMugunthan V N 751df828598SMugunthan V N static irqreturn_t cpsw_interrupt(int irq, void *dev_id) 752df828598SMugunthan V N { 753df828598SMugunthan V N struct cpsw_priv *priv = dev_id; 754fd51cf19SSebastian Siewior 755df828598SMugunthan V N cpsw_intr_disable(priv); 756a11fbba9SSebastian Siewior if (priv->irq_enabled == true) { 757df828598SMugunthan V N cpsw_disable_irq(priv); 758a11fbba9SSebastian Siewior priv->irq_enabled = false; 759a11fbba9SSebastian Siewior } 760fd51cf19SSebastian Siewior 761fd51cf19SSebastian Siewior if (netif_running(priv->ndev)) { 762df828598SMugunthan V N napi_schedule(&priv->napi); 763df828598SMugunthan V N return IRQ_HANDLED; 764df828598SMugunthan V N } 765df828598SMugunthan V N 766fd51cf19SSebastian Siewior priv = cpsw_get_slave_priv(priv, 1); 767fd51cf19SSebastian Siewior if (!priv) 768fd51cf19SSebastian Siewior return IRQ_NONE; 769fd51cf19SSebastian Siewior 770fd51cf19SSebastian Siewior if (netif_running(priv->ndev)) { 771fd51cf19SSebastian Siewior napi_schedule(&priv->napi); 772fd51cf19SSebastian Siewior return IRQ_HANDLED; 773fd51cf19SSebastian Siewior } 774fd51cf19SSebastian Siewior return IRQ_NONE; 775fd51cf19SSebastian Siewior } 776fd51cf19SSebastian Siewior 777df828598SMugunthan V N static int cpsw_poll(struct napi_struct *napi, int budget) 778df828598SMugunthan V N { 779df828598SMugunthan V N struct cpsw_priv *priv = napi_to_priv(napi); 780df828598SMugunthan V N int num_tx, num_rx; 781df828598SMugunthan V N 782df828598SMugunthan V N num_tx = cpdma_chan_process(priv->txch, 128); 783510a1e72SMugunthan V N if (num_tx) 784510a1e72SMugunthan V N cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_TX); 785510a1e72SMugunthan V N 786df828598SMugunthan V N num_rx = cpdma_chan_process(priv->rxch, budget); 787510a1e72SMugunthan V N if (num_rx < budget) { 788a11fbba9SSebastian Siewior struct cpsw_priv *prim_cpsw; 789a11fbba9SSebastian Siewior 790510a1e72SMugunthan V N napi_complete(napi); 791510a1e72SMugunthan V N cpsw_intr_enable(priv); 792510a1e72SMugunthan V N cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_RX); 793a11fbba9SSebastian Siewior prim_cpsw = cpsw_get_slave_priv(priv, 0); 794a11fbba9SSebastian Siewior if (prim_cpsw->irq_enabled == false) { 795a11fbba9SSebastian Siewior prim_cpsw->irq_enabled = true; 796af5c6df7SMugunthan V N cpsw_enable_irq(priv); 797a11fbba9SSebastian Siewior } 798510a1e72SMugunthan V N } 799df828598SMugunthan V N 800df828598SMugunthan V N if (num_rx || num_tx) 801df828598SMugunthan V N cpsw_dbg(priv, intr, "poll %d rx, %d tx pkts\n", 802df828598SMugunthan V N num_rx, num_tx); 803df828598SMugunthan V N 804df828598SMugunthan V N return num_rx; 805df828598SMugunthan V N } 806df828598SMugunthan V N 807df828598SMugunthan V N static inline void soft_reset(const char *module, void __iomem *reg) 808df828598SMugunthan V N { 809df828598SMugunthan V N unsigned long timeout = jiffies + HZ; 810df828598SMugunthan V N 811df828598SMugunthan V N __raw_writel(1, reg); 812df828598SMugunthan V N do { 813df828598SMugunthan V N cpu_relax(); 814df828598SMugunthan V N } while ((__raw_readl(reg) & 1) && time_after(timeout, jiffies)); 815df828598SMugunthan V N 816df828598SMugunthan V N WARN(__raw_readl(reg) & 1, "failed to soft-reset %s\n", module); 817df828598SMugunthan V N } 818df828598SMugunthan V N 819df828598SMugunthan V N #define mac_hi(mac) (((mac)[0] << 0) | ((mac)[1] << 8) | \ 820df828598SMugunthan V N ((mac)[2] << 16) | ((mac)[3] << 24)) 821df828598SMugunthan V N #define mac_lo(mac) (((mac)[4] << 0) | ((mac)[5] << 8)) 822df828598SMugunthan V N 823df828598SMugunthan V N static void cpsw_set_slave_mac(struct cpsw_slave *slave, 824df828598SMugunthan V N struct cpsw_priv *priv) 825df828598SMugunthan V N { 8269750a3adSRichard Cochran slave_write(slave, mac_hi(priv->mac_addr), SA_HI); 8279750a3adSRichard Cochran slave_write(slave, mac_lo(priv->mac_addr), SA_LO); 828df828598SMugunthan V N } 829df828598SMugunthan V N 830df828598SMugunthan V N static void _cpsw_adjust_link(struct cpsw_slave *slave, 831df828598SMugunthan V N struct cpsw_priv *priv, bool *link) 832df828598SMugunthan V N { 833df828598SMugunthan V N struct phy_device *phy = slave->phy; 834df828598SMugunthan V N u32 mac_control = 0; 835df828598SMugunthan V N u32 slave_port; 836df828598SMugunthan V N 837df828598SMugunthan V N if (!phy) 838df828598SMugunthan V N return; 839df828598SMugunthan V N 840df828598SMugunthan V N slave_port = cpsw_get_slave_port(priv, slave->slave_num); 841df828598SMugunthan V N 842df828598SMugunthan V N if (phy->link) { 843df828598SMugunthan V N mac_control = priv->data.mac_control; 844df828598SMugunthan V N 845df828598SMugunthan V N /* enable forwarding */ 846df828598SMugunthan V N cpsw_ale_control_set(priv->ale, slave_port, 847df828598SMugunthan V N ALE_PORT_STATE, ALE_PORT_STATE_FORWARD); 848df828598SMugunthan V N 849df828598SMugunthan V N if (phy->speed == 1000) 850df828598SMugunthan V N mac_control |= BIT(7); /* GIGABITEN */ 851df828598SMugunthan V N if (phy->duplex) 852df828598SMugunthan V N mac_control |= BIT(0); /* FULLDUPLEXEN */ 853342b7b74SDaniel Mack 854342b7b74SDaniel Mack /* set speed_in input in case RMII mode is used in 100Mbps */ 855342b7b74SDaniel Mack if (phy->speed == 100) 856342b7b74SDaniel Mack mac_control |= BIT(15); 857a81d8762SMugunthan V N else if (phy->speed == 10) 858a81d8762SMugunthan V N mac_control |= BIT(18); /* In Band mode */ 859342b7b74SDaniel Mack 8601923d6e4SMugunthan V N if (priv->rx_pause) 8611923d6e4SMugunthan V N mac_control |= BIT(3); 8621923d6e4SMugunthan V N 8631923d6e4SMugunthan V N if (priv->tx_pause) 8641923d6e4SMugunthan V N mac_control |= BIT(4); 8651923d6e4SMugunthan V N 866df828598SMugunthan V N *link = true; 867df828598SMugunthan V N } else { 868df828598SMugunthan V N mac_control = 0; 869df828598SMugunthan V N /* disable forwarding */ 870df828598SMugunthan V N cpsw_ale_control_set(priv->ale, slave_port, 871df828598SMugunthan V N ALE_PORT_STATE, ALE_PORT_STATE_DISABLE); 872df828598SMugunthan V N } 873df828598SMugunthan V N 874df828598SMugunthan V N if (mac_control != slave->mac_control) { 875df828598SMugunthan V N phy_print_status(phy); 876df828598SMugunthan V N __raw_writel(mac_control, &slave->sliver->mac_control); 877df828598SMugunthan V N } 878df828598SMugunthan V N 879df828598SMugunthan V N slave->mac_control = mac_control; 880df828598SMugunthan V N } 881df828598SMugunthan V N 882df828598SMugunthan V N static void cpsw_adjust_link(struct net_device *ndev) 883df828598SMugunthan V N { 884df828598SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 885df828598SMugunthan V N bool link = false; 886df828598SMugunthan V N 887df828598SMugunthan V N for_each_slave(priv, _cpsw_adjust_link, priv, &link); 888df828598SMugunthan V N 889df828598SMugunthan V N if (link) { 890df828598SMugunthan V N netif_carrier_on(ndev); 891df828598SMugunthan V N if (netif_running(ndev)) 892df828598SMugunthan V N netif_wake_queue(ndev); 893df828598SMugunthan V N } else { 894df828598SMugunthan V N netif_carrier_off(ndev); 895df828598SMugunthan V N netif_stop_queue(ndev); 896df828598SMugunthan V N } 897df828598SMugunthan V N } 898df828598SMugunthan V N 899ff5b8ef2SMugunthan V N static int cpsw_get_coalesce(struct net_device *ndev, 900ff5b8ef2SMugunthan V N struct ethtool_coalesce *coal) 901ff5b8ef2SMugunthan V N { 902ff5b8ef2SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 903ff5b8ef2SMugunthan V N 904ff5b8ef2SMugunthan V N coal->rx_coalesce_usecs = priv->coal_intvl; 905ff5b8ef2SMugunthan V N return 0; 906ff5b8ef2SMugunthan V N } 907ff5b8ef2SMugunthan V N 908ff5b8ef2SMugunthan V N static int cpsw_set_coalesce(struct net_device *ndev, 909ff5b8ef2SMugunthan V N struct ethtool_coalesce *coal) 910ff5b8ef2SMugunthan V N { 911ff5b8ef2SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 912ff5b8ef2SMugunthan V N u32 int_ctrl; 913ff5b8ef2SMugunthan V N u32 num_interrupts = 0; 914ff5b8ef2SMugunthan V N u32 prescale = 0; 915ff5b8ef2SMugunthan V N u32 addnl_dvdr = 1; 916ff5b8ef2SMugunthan V N u32 coal_intvl = 0; 917ff5b8ef2SMugunthan V N 918ff5b8ef2SMugunthan V N coal_intvl = coal->rx_coalesce_usecs; 919ff5b8ef2SMugunthan V N 920ff5b8ef2SMugunthan V N int_ctrl = readl(&priv->wr_regs->int_control); 921ff5b8ef2SMugunthan V N prescale = priv->bus_freq_mhz * 4; 922ff5b8ef2SMugunthan V N 923a84bc2a9SMugunthan V N if (!coal->rx_coalesce_usecs) { 924a84bc2a9SMugunthan V N int_ctrl &= ~(CPSW_INTPRESCALE_MASK | CPSW_INTPACEEN); 925a84bc2a9SMugunthan V N goto update_return; 926a84bc2a9SMugunthan V N } 927a84bc2a9SMugunthan V N 928ff5b8ef2SMugunthan V N if (coal_intvl < CPSW_CMINTMIN_INTVL) 929ff5b8ef2SMugunthan V N coal_intvl = CPSW_CMINTMIN_INTVL; 930ff5b8ef2SMugunthan V N 931ff5b8ef2SMugunthan V N if (coal_intvl > CPSW_CMINTMAX_INTVL) { 932ff5b8ef2SMugunthan V N /* Interrupt pacer works with 4us Pulse, we can 933ff5b8ef2SMugunthan V N * throttle further by dilating the 4us pulse. 934ff5b8ef2SMugunthan V N */ 935ff5b8ef2SMugunthan V N addnl_dvdr = CPSW_INTPRESCALE_MASK / prescale; 936ff5b8ef2SMugunthan V N 937ff5b8ef2SMugunthan V N if (addnl_dvdr > 1) { 938ff5b8ef2SMugunthan V N prescale *= addnl_dvdr; 939ff5b8ef2SMugunthan V N if (coal_intvl > (CPSW_CMINTMAX_INTVL * addnl_dvdr)) 940ff5b8ef2SMugunthan V N coal_intvl = (CPSW_CMINTMAX_INTVL 941ff5b8ef2SMugunthan V N * addnl_dvdr); 942ff5b8ef2SMugunthan V N } else { 943ff5b8ef2SMugunthan V N addnl_dvdr = 1; 944ff5b8ef2SMugunthan V N coal_intvl = CPSW_CMINTMAX_INTVL; 945ff5b8ef2SMugunthan V N } 946ff5b8ef2SMugunthan V N } 947ff5b8ef2SMugunthan V N 948ff5b8ef2SMugunthan V N num_interrupts = (1000 * addnl_dvdr) / coal_intvl; 949ff5b8ef2SMugunthan V N writel(num_interrupts, &priv->wr_regs->rx_imax); 950ff5b8ef2SMugunthan V N writel(num_interrupts, &priv->wr_regs->tx_imax); 951ff5b8ef2SMugunthan V N 952ff5b8ef2SMugunthan V N int_ctrl |= CPSW_INTPACEEN; 953ff5b8ef2SMugunthan V N int_ctrl &= (~CPSW_INTPRESCALE_MASK); 954ff5b8ef2SMugunthan V N int_ctrl |= (prescale & CPSW_INTPRESCALE_MASK); 955a84bc2a9SMugunthan V N 956a84bc2a9SMugunthan V N update_return: 957ff5b8ef2SMugunthan V N writel(int_ctrl, &priv->wr_regs->int_control); 958ff5b8ef2SMugunthan V N 959ff5b8ef2SMugunthan V N cpsw_notice(priv, timer, "Set coalesce to %d usecs.\n", coal_intvl); 960ff5b8ef2SMugunthan V N if (priv->data.dual_emac) { 961ff5b8ef2SMugunthan V N int i; 962ff5b8ef2SMugunthan V N 963ff5b8ef2SMugunthan V N for (i = 0; i < priv->data.slaves; i++) { 964ff5b8ef2SMugunthan V N priv = netdev_priv(priv->slaves[i].ndev); 965ff5b8ef2SMugunthan V N priv->coal_intvl = coal_intvl; 966ff5b8ef2SMugunthan V N } 967ff5b8ef2SMugunthan V N } else { 968ff5b8ef2SMugunthan V N priv->coal_intvl = coal_intvl; 969ff5b8ef2SMugunthan V N } 970ff5b8ef2SMugunthan V N 971ff5b8ef2SMugunthan V N return 0; 972ff5b8ef2SMugunthan V N } 973ff5b8ef2SMugunthan V N 974d9718546SMugunthan V N static int cpsw_get_sset_count(struct net_device *ndev, int sset) 975d9718546SMugunthan V N { 976d9718546SMugunthan V N switch (sset) { 977d9718546SMugunthan V N case ETH_SS_STATS: 978d9718546SMugunthan V N return CPSW_STATS_LEN; 979d9718546SMugunthan V N default: 980d9718546SMugunthan V N return -EOPNOTSUPP; 981d9718546SMugunthan V N } 982d9718546SMugunthan V N } 983d9718546SMugunthan V N 984d9718546SMugunthan V N static void cpsw_get_strings(struct net_device *ndev, u32 stringset, u8 *data) 985d9718546SMugunthan V N { 986d9718546SMugunthan V N u8 *p = data; 987d9718546SMugunthan V N int i; 988d9718546SMugunthan V N 989d9718546SMugunthan V N switch (stringset) { 990d9718546SMugunthan V N case ETH_SS_STATS: 991d9718546SMugunthan V N for (i = 0; i < CPSW_STATS_LEN; i++) { 992d9718546SMugunthan V N memcpy(p, cpsw_gstrings_stats[i].stat_string, 993d9718546SMugunthan V N ETH_GSTRING_LEN); 994d9718546SMugunthan V N p += ETH_GSTRING_LEN; 995d9718546SMugunthan V N } 996d9718546SMugunthan V N break; 997d9718546SMugunthan V N } 998d9718546SMugunthan V N } 999d9718546SMugunthan V N 1000d9718546SMugunthan V N static void cpsw_get_ethtool_stats(struct net_device *ndev, 1001d9718546SMugunthan V N struct ethtool_stats *stats, u64 *data) 1002d9718546SMugunthan V N { 1003d9718546SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 1004d9718546SMugunthan V N struct cpdma_chan_stats rx_stats; 1005d9718546SMugunthan V N struct cpdma_chan_stats tx_stats; 1006d9718546SMugunthan V N u32 val; 1007d9718546SMugunthan V N u8 *p; 1008d9718546SMugunthan V N int i; 1009d9718546SMugunthan V N 1010d9718546SMugunthan V N /* Collect Davinci CPDMA stats for Rx and Tx Channel */ 1011d9718546SMugunthan V N cpdma_chan_get_stats(priv->rxch, &rx_stats); 1012d9718546SMugunthan V N cpdma_chan_get_stats(priv->txch, &tx_stats); 1013d9718546SMugunthan V N 1014d9718546SMugunthan V N for (i = 0; i < CPSW_STATS_LEN; i++) { 1015d9718546SMugunthan V N switch (cpsw_gstrings_stats[i].type) { 1016d9718546SMugunthan V N case CPSW_STATS: 1017d9718546SMugunthan V N val = readl(priv->hw_stats + 1018d9718546SMugunthan V N cpsw_gstrings_stats[i].stat_offset); 1019d9718546SMugunthan V N data[i] = val; 1020d9718546SMugunthan V N break; 1021d9718546SMugunthan V N 1022d9718546SMugunthan V N case CPDMA_RX_STATS: 1023d9718546SMugunthan V N p = (u8 *)&rx_stats + 1024d9718546SMugunthan V N cpsw_gstrings_stats[i].stat_offset; 1025d9718546SMugunthan V N data[i] = *(u32 *)p; 1026d9718546SMugunthan V N break; 1027d9718546SMugunthan V N 1028d9718546SMugunthan V N case CPDMA_TX_STATS: 1029d9718546SMugunthan V N p = (u8 *)&tx_stats + 1030d9718546SMugunthan V N cpsw_gstrings_stats[i].stat_offset; 1031d9718546SMugunthan V N data[i] = *(u32 *)p; 1032d9718546SMugunthan V N break; 1033d9718546SMugunthan V N } 1034d9718546SMugunthan V N } 1035d9718546SMugunthan V N } 1036d9718546SMugunthan V N 1037d9ba8f9eSMugunthan V N static int cpsw_common_res_usage_state(struct cpsw_priv *priv) 1038d9ba8f9eSMugunthan V N { 1039d9ba8f9eSMugunthan V N u32 i; 1040d9ba8f9eSMugunthan V N u32 usage_count = 0; 1041d9ba8f9eSMugunthan V N 1042d9ba8f9eSMugunthan V N if (!priv->data.dual_emac) 1043d9ba8f9eSMugunthan V N return 0; 1044d9ba8f9eSMugunthan V N 1045d9ba8f9eSMugunthan V N for (i = 0; i < priv->data.slaves; i++) 1046d9ba8f9eSMugunthan V N if (priv->slaves[i].open_stat) 1047d9ba8f9eSMugunthan V N usage_count++; 1048d9ba8f9eSMugunthan V N 1049d9ba8f9eSMugunthan V N return usage_count; 1050d9ba8f9eSMugunthan V N } 1051d9ba8f9eSMugunthan V N 1052d9ba8f9eSMugunthan V N static inline int cpsw_tx_packet_submit(struct net_device *ndev, 1053d9ba8f9eSMugunthan V N struct cpsw_priv *priv, struct sk_buff *skb) 1054d9ba8f9eSMugunthan V N { 1055d9ba8f9eSMugunthan V N if (!priv->data.dual_emac) 1056d9ba8f9eSMugunthan V N return cpdma_chan_submit(priv->txch, skb, skb->data, 1057aef614e1SSebastian Siewior skb->len, 0); 1058d9ba8f9eSMugunthan V N 1059d9ba8f9eSMugunthan V N if (ndev == cpsw_get_slave_ndev(priv, 0)) 1060d9ba8f9eSMugunthan V N return cpdma_chan_submit(priv->txch, skb, skb->data, 1061aef614e1SSebastian Siewior skb->len, 1); 1062d9ba8f9eSMugunthan V N else 1063d9ba8f9eSMugunthan V N return cpdma_chan_submit(priv->txch, skb, skb->data, 1064aef614e1SSebastian Siewior skb->len, 2); 1065d9ba8f9eSMugunthan V N } 1066d9ba8f9eSMugunthan V N 1067d9ba8f9eSMugunthan V N static inline void cpsw_add_dual_emac_def_ale_entries( 1068d9ba8f9eSMugunthan V N struct cpsw_priv *priv, struct cpsw_slave *slave, 1069d9ba8f9eSMugunthan V N u32 slave_port) 1070d9ba8f9eSMugunthan V N { 1071d9ba8f9eSMugunthan V N u32 port_mask = 1 << slave_port | 1 << priv->host_port; 1072d9ba8f9eSMugunthan V N 1073d9ba8f9eSMugunthan V N if (priv->version == CPSW_VERSION_1) 1074d9ba8f9eSMugunthan V N slave_write(slave, slave->port_vlan, CPSW1_PORT_VLAN); 1075d9ba8f9eSMugunthan V N else 1076d9ba8f9eSMugunthan V N slave_write(slave, slave->port_vlan, CPSW2_PORT_VLAN); 1077d9ba8f9eSMugunthan V N cpsw_ale_add_vlan(priv->ale, slave->port_vlan, port_mask, 1078d9ba8f9eSMugunthan V N port_mask, port_mask, 0); 1079d9ba8f9eSMugunthan V N cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast, 1080d9ba8f9eSMugunthan V N port_mask, ALE_VLAN, slave->port_vlan, 0); 1081d9ba8f9eSMugunthan V N cpsw_ale_add_ucast(priv->ale, priv->mac_addr, 1082d9ba8f9eSMugunthan V N priv->host_port, ALE_VLAN, slave->port_vlan); 1083d9ba8f9eSMugunthan V N } 1084d9ba8f9eSMugunthan V N 10851e7a2e21SDaniel Mack static void soft_reset_slave(struct cpsw_slave *slave) 1086df828598SMugunthan V N { 1087df828598SMugunthan V N char name[32]; 10881e7a2e21SDaniel Mack 10891e7a2e21SDaniel Mack snprintf(name, sizeof(name), "slave-%d", slave->slave_num); 10901e7a2e21SDaniel Mack soft_reset(name, &slave->sliver->soft_reset); 10911e7a2e21SDaniel Mack } 10921e7a2e21SDaniel Mack 10931e7a2e21SDaniel Mack static void cpsw_slave_open(struct cpsw_slave *slave, struct cpsw_priv *priv) 10941e7a2e21SDaniel Mack { 1095df828598SMugunthan V N u32 slave_port; 1096df828598SMugunthan V N 10971e7a2e21SDaniel Mack soft_reset_slave(slave); 1098df828598SMugunthan V N 1099df828598SMugunthan V N /* setup priority mapping */ 1100df828598SMugunthan V N __raw_writel(RX_PRIORITY_MAPPING, &slave->sliver->rx_pri_map); 11019750a3adSRichard Cochran 11029750a3adSRichard Cochran switch (priv->version) { 11039750a3adSRichard Cochran case CPSW_VERSION_1: 11049750a3adSRichard Cochran slave_write(slave, TX_PRIORITY_MAPPING, CPSW1_TX_PRI_MAP); 11059750a3adSRichard Cochran break; 11069750a3adSRichard Cochran case CPSW_VERSION_2: 1107c193f365SMugunthan V N case CPSW_VERSION_3: 1108926489beSMugunthan V N case CPSW_VERSION_4: 11099750a3adSRichard Cochran slave_write(slave, TX_PRIORITY_MAPPING, CPSW2_TX_PRI_MAP); 11109750a3adSRichard Cochran break; 11119750a3adSRichard Cochran } 1112df828598SMugunthan V N 1113df828598SMugunthan V N /* setup max packet size, and mac address */ 1114df828598SMugunthan V N __raw_writel(priv->rx_packet_max, &slave->sliver->rx_maxlen); 1115df828598SMugunthan V N cpsw_set_slave_mac(slave, priv); 1116df828598SMugunthan V N 1117df828598SMugunthan V N slave->mac_control = 0; /* no link yet */ 1118df828598SMugunthan V N 1119df828598SMugunthan V N slave_port = cpsw_get_slave_port(priv, slave->slave_num); 1120df828598SMugunthan V N 1121d9ba8f9eSMugunthan V N if (priv->data.dual_emac) 1122d9ba8f9eSMugunthan V N cpsw_add_dual_emac_def_ale_entries(priv, slave, slave_port); 1123d9ba8f9eSMugunthan V N else 1124df828598SMugunthan V N cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast, 1125e11b220fSMugunthan V N 1 << slave_port, 0, 0, ALE_MCAST_FWD_2); 1126df828598SMugunthan V N 1127df828598SMugunthan V N slave->phy = phy_connect(priv->ndev, slave->data->phy_id, 1128f9a8f83bSFlorian Fainelli &cpsw_adjust_link, slave->data->phy_if); 1129df828598SMugunthan V N if (IS_ERR(slave->phy)) { 1130df828598SMugunthan V N dev_err(priv->dev, "phy %s not found on slave %d\n", 1131df828598SMugunthan V N slave->data->phy_id, slave->slave_num); 1132df828598SMugunthan V N slave->phy = NULL; 1133df828598SMugunthan V N } else { 1134df828598SMugunthan V N dev_info(priv->dev, "phy found : id is : 0x%x\n", 1135df828598SMugunthan V N slave->phy->phy_id); 1136df828598SMugunthan V N phy_start(slave->phy); 1137388367a5SMugunthan V N 1138388367a5SMugunthan V N /* Configure GMII_SEL register */ 1139388367a5SMugunthan V N cpsw_phy_sel(&priv->pdev->dev, slave->phy->interface, 1140388367a5SMugunthan V N slave->slave_num); 1141df828598SMugunthan V N } 1142df828598SMugunthan V N } 1143df828598SMugunthan V N 11443b72c2feSMugunthan V N static inline void cpsw_add_default_vlan(struct cpsw_priv *priv) 11453b72c2feSMugunthan V N { 11463b72c2feSMugunthan V N const int vlan = priv->data.default_vlan; 11473b72c2feSMugunthan V N const int port = priv->host_port; 11483b72c2feSMugunthan V N u32 reg; 11493b72c2feSMugunthan V N int i; 11503b72c2feSMugunthan V N 11513b72c2feSMugunthan V N reg = (priv->version == CPSW_VERSION_1) ? CPSW1_PORT_VLAN : 11523b72c2feSMugunthan V N CPSW2_PORT_VLAN; 11533b72c2feSMugunthan V N 11543b72c2feSMugunthan V N writel(vlan, &priv->host_port_regs->port_vlan); 11553b72c2feSMugunthan V N 11560237c110SDaniel Mack for (i = 0; i < priv->data.slaves; i++) 11573b72c2feSMugunthan V N slave_write(priv->slaves + i, vlan, reg); 11583b72c2feSMugunthan V N 11593b72c2feSMugunthan V N cpsw_ale_add_vlan(priv->ale, vlan, ALE_ALL_PORTS << port, 11603b72c2feSMugunthan V N ALE_ALL_PORTS << port, ALE_ALL_PORTS << port, 11613b72c2feSMugunthan V N (ALE_PORT_1 | ALE_PORT_2) << port); 11623b72c2feSMugunthan V N } 11633b72c2feSMugunthan V N 1164df828598SMugunthan V N static void cpsw_init_host_port(struct cpsw_priv *priv) 1165df828598SMugunthan V N { 11663b72c2feSMugunthan V N u32 control_reg; 1167d9ba8f9eSMugunthan V N u32 fifo_mode; 11683b72c2feSMugunthan V N 1169df828598SMugunthan V N /* soft reset the controller and initialize ale */ 1170df828598SMugunthan V N soft_reset("cpsw", &priv->regs->soft_reset); 1171df828598SMugunthan V N cpsw_ale_start(priv->ale); 1172df828598SMugunthan V N 1173df828598SMugunthan V N /* switch to vlan unaware mode */ 11743b72c2feSMugunthan V N cpsw_ale_control_set(priv->ale, priv->host_port, ALE_VLAN_AWARE, 11753b72c2feSMugunthan V N CPSW_ALE_VLAN_AWARE); 11763b72c2feSMugunthan V N control_reg = readl(&priv->regs->control); 11773b72c2feSMugunthan V N control_reg |= CPSW_VLAN_AWARE; 11783b72c2feSMugunthan V N writel(control_reg, &priv->regs->control); 1179d9ba8f9eSMugunthan V N fifo_mode = (priv->data.dual_emac) ? CPSW_FIFO_DUAL_MAC_MODE : 1180d9ba8f9eSMugunthan V N CPSW_FIFO_NORMAL_MODE; 1181d9ba8f9eSMugunthan V N writel(fifo_mode, &priv->host_port_regs->tx_in_ctl); 1182df828598SMugunthan V N 1183df828598SMugunthan V N /* setup host port priority mapping */ 1184df828598SMugunthan V N __raw_writel(CPDMA_TX_PRIORITY_MAP, 1185df828598SMugunthan V N &priv->host_port_regs->cpdma_tx_pri_map); 1186df828598SMugunthan V N __raw_writel(0, &priv->host_port_regs->cpdma_rx_chan_map); 1187df828598SMugunthan V N 1188df828598SMugunthan V N cpsw_ale_control_set(priv->ale, priv->host_port, 1189df828598SMugunthan V N ALE_PORT_STATE, ALE_PORT_STATE_FORWARD); 1190df828598SMugunthan V N 1191d9ba8f9eSMugunthan V N if (!priv->data.dual_emac) { 1192d9ba8f9eSMugunthan V N cpsw_ale_add_ucast(priv->ale, priv->mac_addr, priv->host_port, 1193d9ba8f9eSMugunthan V N 0, 0); 1194df828598SMugunthan V N cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast, 1195e11b220fSMugunthan V N 1 << priv->host_port, 0, 0, ALE_MCAST_FWD_2); 1196df828598SMugunthan V N } 1197d9ba8f9eSMugunthan V N } 1198df828598SMugunthan V N 1199aacebbf8SSebastian Siewior static void cpsw_slave_stop(struct cpsw_slave *slave, struct cpsw_priv *priv) 1200aacebbf8SSebastian Siewior { 12013995d265SSchuyler Patton u32 slave_port; 12023995d265SSchuyler Patton 12033995d265SSchuyler Patton slave_port = cpsw_get_slave_port(priv, slave->slave_num); 12043995d265SSchuyler Patton 1205aacebbf8SSebastian Siewior if (!slave->phy) 1206aacebbf8SSebastian Siewior return; 1207aacebbf8SSebastian Siewior phy_stop(slave->phy); 1208aacebbf8SSebastian Siewior phy_disconnect(slave->phy); 1209aacebbf8SSebastian Siewior slave->phy = NULL; 12103995d265SSchuyler Patton cpsw_ale_control_set(priv->ale, slave_port, 12113995d265SSchuyler Patton ALE_PORT_STATE, ALE_PORT_STATE_DISABLE); 1212aacebbf8SSebastian Siewior } 1213aacebbf8SSebastian Siewior 1214df828598SMugunthan V N static int cpsw_ndo_open(struct net_device *ndev) 1215df828598SMugunthan V N { 1216df828598SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 1217a11fbba9SSebastian Siewior struct cpsw_priv *prim_cpsw; 1218df828598SMugunthan V N int i, ret; 1219df828598SMugunthan V N u32 reg; 1220df828598SMugunthan V N 1221d9ba8f9eSMugunthan V N if (!cpsw_common_res_usage_state(priv)) 1222df828598SMugunthan V N cpsw_intr_disable(priv); 1223df828598SMugunthan V N netif_carrier_off(ndev); 1224df828598SMugunthan V N 1225f150bd7fSMugunthan V N pm_runtime_get_sync(&priv->pdev->dev); 1226df828598SMugunthan V N 1227549985eeSRichard Cochran reg = priv->version; 1228df828598SMugunthan V N 1229df828598SMugunthan V N dev_info(priv->dev, "initializing cpsw version %d.%d (%d)\n", 1230df828598SMugunthan V N CPSW_MAJOR_VERSION(reg), CPSW_MINOR_VERSION(reg), 1231df828598SMugunthan V N CPSW_RTL_VERSION(reg)); 1232df828598SMugunthan V N 1233df828598SMugunthan V N /* initialize host and slave ports */ 1234d9ba8f9eSMugunthan V N if (!cpsw_common_res_usage_state(priv)) 1235df828598SMugunthan V N cpsw_init_host_port(priv); 1236df828598SMugunthan V N for_each_slave(priv, cpsw_slave_open, priv); 1237df828598SMugunthan V N 12383b72c2feSMugunthan V N /* Add default VLAN */ 1239e6afea0bSMugunthan V N if (!priv->data.dual_emac) 12403b72c2feSMugunthan V N cpsw_add_default_vlan(priv); 1241e6afea0bSMugunthan V N else 1242e6afea0bSMugunthan V N cpsw_ale_add_vlan(priv->ale, priv->data.default_vlan, 1243e6afea0bSMugunthan V N ALE_ALL_PORTS << priv->host_port, 1244e6afea0bSMugunthan V N ALE_ALL_PORTS << priv->host_port, 0, 0); 12453b72c2feSMugunthan V N 1246d9ba8f9eSMugunthan V N if (!cpsw_common_res_usage_state(priv)) { 1247df828598SMugunthan V N /* setup tx dma to fixed prio and zero offset */ 1248df828598SMugunthan V N cpdma_control_set(priv->dma, CPDMA_TX_PRIO_FIXED, 1); 1249df828598SMugunthan V N cpdma_control_set(priv->dma, CPDMA_RX_BUFFER_OFFSET, 0); 1250df828598SMugunthan V N 1251d9ba8f9eSMugunthan V N /* disable priority elevation */ 1252df828598SMugunthan V N __raw_writel(0, &priv->regs->ptype); 1253df828598SMugunthan V N 1254d9ba8f9eSMugunthan V N /* enable statistics collection only on all ports */ 1255df828598SMugunthan V N __raw_writel(0x7, &priv->regs->stat_port_en); 1256df828598SMugunthan V N 12571923d6e4SMugunthan V N /* Enable internal fifo flow control */ 12581923d6e4SMugunthan V N writel(0x7, &priv->regs->flow_control); 12591923d6e4SMugunthan V N 1260df828598SMugunthan V N if (WARN_ON(!priv->data.rx_descs)) 1261df828598SMugunthan V N priv->data.rx_descs = 128; 1262df828598SMugunthan V N 1263df828598SMugunthan V N for (i = 0; i < priv->data.rx_descs; i++) { 1264df828598SMugunthan V N struct sk_buff *skb; 1265df828598SMugunthan V N 1266df828598SMugunthan V N ret = -ENOMEM; 1267aacebbf8SSebastian Siewior skb = __netdev_alloc_skb_ip_align(priv->ndev, 1268aacebbf8SSebastian Siewior priv->rx_packet_max, GFP_KERNEL); 1269df828598SMugunthan V N if (!skb) 1270aacebbf8SSebastian Siewior goto err_cleanup; 1271df828598SMugunthan V N ret = cpdma_chan_submit(priv->rxch, skb, skb->data, 1272aef614e1SSebastian Siewior skb_tailroom(skb), 0); 1273aacebbf8SSebastian Siewior if (ret < 0) { 1274aacebbf8SSebastian Siewior kfree_skb(skb); 1275aacebbf8SSebastian Siewior goto err_cleanup; 1276aacebbf8SSebastian Siewior } 1277df828598SMugunthan V N } 1278d9ba8f9eSMugunthan V N /* continue even if we didn't manage to submit all 1279d9ba8f9eSMugunthan V N * receive descs 1280d9ba8f9eSMugunthan V N */ 1281df828598SMugunthan V N cpsw_info(priv, ifup, "submitted %d rx descriptors\n", i); 1282f280e89aSMugunthan V N 1283f280e89aSMugunthan V N if (cpts_register(&priv->pdev->dev, priv->cpts, 1284f280e89aSMugunthan V N priv->data.cpts_clock_mult, 1285f280e89aSMugunthan V N priv->data.cpts_clock_shift)) 1286f280e89aSMugunthan V N dev_err(priv->dev, "error registering cpts device\n"); 1287f280e89aSMugunthan V N 1288d9ba8f9eSMugunthan V N } 1289df828598SMugunthan V N 1290ff5b8ef2SMugunthan V N /* Enable Interrupt pacing if configured */ 1291ff5b8ef2SMugunthan V N if (priv->coal_intvl != 0) { 1292ff5b8ef2SMugunthan V N struct ethtool_coalesce coal; 1293ff5b8ef2SMugunthan V N 1294ff5b8ef2SMugunthan V N coal.rx_coalesce_usecs = (priv->coal_intvl << 4); 1295ff5b8ef2SMugunthan V N cpsw_set_coalesce(ndev, &coal); 1296ff5b8ef2SMugunthan V N } 1297ff5b8ef2SMugunthan V N 1298f63a975eSMugunthan V N napi_enable(&priv->napi); 1299f63a975eSMugunthan V N cpdma_ctlr_start(priv->dma); 1300f63a975eSMugunthan V N cpsw_intr_enable(priv); 1301f63a975eSMugunthan V N cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_RX); 1302f63a975eSMugunthan V N cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_TX); 1303f63a975eSMugunthan V N 1304a11fbba9SSebastian Siewior prim_cpsw = cpsw_get_slave_priv(priv, 0); 1305a11fbba9SSebastian Siewior if (prim_cpsw->irq_enabled == false) { 1306a11fbba9SSebastian Siewior if ((priv == prim_cpsw) || !netif_running(prim_cpsw->ndev)) { 1307a11fbba9SSebastian Siewior prim_cpsw->irq_enabled = true; 1308a11fbba9SSebastian Siewior cpsw_enable_irq(prim_cpsw); 1309a11fbba9SSebastian Siewior } 1310a11fbba9SSebastian Siewior } 1311a11fbba9SSebastian Siewior 1312d9ba8f9eSMugunthan V N if (priv->data.dual_emac) 1313d9ba8f9eSMugunthan V N priv->slaves[priv->emac_port].open_stat = true; 1314df828598SMugunthan V N return 0; 1315df828598SMugunthan V N 1316aacebbf8SSebastian Siewior err_cleanup: 1317aacebbf8SSebastian Siewior cpdma_ctlr_stop(priv->dma); 1318aacebbf8SSebastian Siewior for_each_slave(priv, cpsw_slave_stop, priv); 1319aacebbf8SSebastian Siewior pm_runtime_put_sync(&priv->pdev->dev); 1320aacebbf8SSebastian Siewior netif_carrier_off(priv->ndev); 1321aacebbf8SSebastian Siewior return ret; 1322df828598SMugunthan V N } 1323df828598SMugunthan V N 1324df828598SMugunthan V N static int cpsw_ndo_stop(struct net_device *ndev) 1325df828598SMugunthan V N { 1326df828598SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 1327df828598SMugunthan V N 1328df828598SMugunthan V N cpsw_info(priv, ifdown, "shutting down cpsw device\n"); 1329df828598SMugunthan V N netif_stop_queue(priv->ndev); 1330df828598SMugunthan V N napi_disable(&priv->napi); 1331df828598SMugunthan V N netif_carrier_off(priv->ndev); 1332d9ba8f9eSMugunthan V N 1333d9ba8f9eSMugunthan V N if (cpsw_common_res_usage_state(priv) <= 1) { 1334f280e89aSMugunthan V N cpts_unregister(priv->cpts); 133571380f9bSMugunthan V N cpsw_intr_disable(priv); 133671380f9bSMugunthan V N cpdma_ctlr_int_ctrl(priv->dma, false); 133771380f9bSMugunthan V N cpdma_ctlr_stop(priv->dma); 1338df828598SMugunthan V N cpsw_ale_stop(priv->ale); 1339d9ba8f9eSMugunthan V N } 1340df828598SMugunthan V N for_each_slave(priv, cpsw_slave_stop, priv); 1341f150bd7fSMugunthan V N pm_runtime_put_sync(&priv->pdev->dev); 1342d9ba8f9eSMugunthan V N if (priv->data.dual_emac) 1343d9ba8f9eSMugunthan V N priv->slaves[priv->emac_port].open_stat = false; 1344df828598SMugunthan V N return 0; 1345df828598SMugunthan V N } 1346df828598SMugunthan V N 1347df828598SMugunthan V N static netdev_tx_t cpsw_ndo_start_xmit(struct sk_buff *skb, 1348df828598SMugunthan V N struct net_device *ndev) 1349df828598SMugunthan V N { 1350df828598SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 1351df828598SMugunthan V N int ret; 1352df828598SMugunthan V N 1353df828598SMugunthan V N ndev->trans_start = jiffies; 1354df828598SMugunthan V N 1355df828598SMugunthan V N if (skb_padto(skb, CPSW_MIN_PACKET_SIZE)) { 1356df828598SMugunthan V N cpsw_err(priv, tx_err, "packet pad failed\n"); 13578dc43ddcSTobias Klauser ndev->stats.tx_dropped++; 1358df828598SMugunthan V N return NETDEV_TX_OK; 1359df828598SMugunthan V N } 1360df828598SMugunthan V N 13619232b16dSMugunthan V N if (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP && 13629232b16dSMugunthan V N priv->cpts->tx_enable) 13632e5b38abSRichard Cochran skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 13642e5b38abSRichard Cochran 13652e5b38abSRichard Cochran skb_tx_timestamp(skb); 13662e5b38abSRichard Cochran 1367d9ba8f9eSMugunthan V N ret = cpsw_tx_packet_submit(ndev, priv, skb); 1368df828598SMugunthan V N if (unlikely(ret != 0)) { 1369df828598SMugunthan V N cpsw_err(priv, tx_err, "desc submit failed\n"); 1370df828598SMugunthan V N goto fail; 1371df828598SMugunthan V N } 1372df828598SMugunthan V N 1373fae50823SMugunthan V N /* If there is no more tx desc left free then we need to 1374fae50823SMugunthan V N * tell the kernel to stop sending us tx frames. 1375fae50823SMugunthan V N */ 1376d35162f8SDaniel Mack if (unlikely(!cpdma_check_free_tx_desc(priv->txch))) 1377fae50823SMugunthan V N netif_stop_queue(ndev); 1378fae50823SMugunthan V N 1379df828598SMugunthan V N return NETDEV_TX_OK; 1380df828598SMugunthan V N fail: 13818dc43ddcSTobias Klauser ndev->stats.tx_dropped++; 1382df828598SMugunthan V N netif_stop_queue(ndev); 1383df828598SMugunthan V N return NETDEV_TX_BUSY; 1384df828598SMugunthan V N } 1385df828598SMugunthan V N 13862e5b38abSRichard Cochran #ifdef CONFIG_TI_CPTS 13872e5b38abSRichard Cochran 13882e5b38abSRichard Cochran static void cpsw_hwtstamp_v1(struct cpsw_priv *priv) 13892e5b38abSRichard Cochran { 1390e86ac13bSMugunthan V N struct cpsw_slave *slave = &priv->slaves[priv->data.active_slave]; 13912e5b38abSRichard Cochran u32 ts_en, seq_id; 13922e5b38abSRichard Cochran 13939232b16dSMugunthan V N if (!priv->cpts->tx_enable && !priv->cpts->rx_enable) { 13942e5b38abSRichard Cochran slave_write(slave, 0, CPSW1_TS_CTL); 13952e5b38abSRichard Cochran return; 13962e5b38abSRichard Cochran } 13972e5b38abSRichard Cochran 13982e5b38abSRichard Cochran seq_id = (30 << CPSW_V1_SEQ_ID_OFS_SHIFT) | ETH_P_1588; 13992e5b38abSRichard Cochran ts_en = EVENT_MSG_BITS << CPSW_V1_MSG_TYPE_OFS; 14002e5b38abSRichard Cochran 14019232b16dSMugunthan V N if (priv->cpts->tx_enable) 14022e5b38abSRichard Cochran ts_en |= CPSW_V1_TS_TX_EN; 14032e5b38abSRichard Cochran 14049232b16dSMugunthan V N if (priv->cpts->rx_enable) 14052e5b38abSRichard Cochran ts_en |= CPSW_V1_TS_RX_EN; 14062e5b38abSRichard Cochran 14072e5b38abSRichard Cochran slave_write(slave, ts_en, CPSW1_TS_CTL); 14082e5b38abSRichard Cochran slave_write(slave, seq_id, CPSW1_TS_SEQ_LTYPE); 14092e5b38abSRichard Cochran } 14102e5b38abSRichard Cochran 14112e5b38abSRichard Cochran static void cpsw_hwtstamp_v2(struct cpsw_priv *priv) 14122e5b38abSRichard Cochran { 1413d9ba8f9eSMugunthan V N struct cpsw_slave *slave; 14142e5b38abSRichard Cochran u32 ctrl, mtype; 14152e5b38abSRichard Cochran 1416d9ba8f9eSMugunthan V N if (priv->data.dual_emac) 1417d9ba8f9eSMugunthan V N slave = &priv->slaves[priv->emac_port]; 1418d9ba8f9eSMugunthan V N else 1419e86ac13bSMugunthan V N slave = &priv->slaves[priv->data.active_slave]; 1420d9ba8f9eSMugunthan V N 14212e5b38abSRichard Cochran ctrl = slave_read(slave, CPSW2_CONTROL); 142209c55372SGeorge Cherian switch (priv->version) { 142309c55372SGeorge Cherian case CPSW_VERSION_2: 142409c55372SGeorge Cherian ctrl &= ~CTRL_V2_ALL_TS_MASK; 14252e5b38abSRichard Cochran 14269232b16dSMugunthan V N if (priv->cpts->tx_enable) 142709c55372SGeorge Cherian ctrl |= CTRL_V2_TX_TS_BITS; 14282e5b38abSRichard Cochran 14299232b16dSMugunthan V N if (priv->cpts->rx_enable) 143009c55372SGeorge Cherian ctrl |= CTRL_V2_RX_TS_BITS; 143109c55372SGeorge Cherian break; 143209c55372SGeorge Cherian case CPSW_VERSION_3: 143309c55372SGeorge Cherian default: 143409c55372SGeorge Cherian ctrl &= ~CTRL_V3_ALL_TS_MASK; 143509c55372SGeorge Cherian 143609c55372SGeorge Cherian if (priv->cpts->tx_enable) 143709c55372SGeorge Cherian ctrl |= CTRL_V3_TX_TS_BITS; 143809c55372SGeorge Cherian 143909c55372SGeorge Cherian if (priv->cpts->rx_enable) 144009c55372SGeorge Cherian ctrl |= CTRL_V3_RX_TS_BITS; 144109c55372SGeorge Cherian break; 144209c55372SGeorge Cherian } 14432e5b38abSRichard Cochran 14442e5b38abSRichard Cochran mtype = (30 << TS_SEQ_ID_OFFSET_SHIFT) | EVENT_MSG_BITS; 14452e5b38abSRichard Cochran 14462e5b38abSRichard Cochran slave_write(slave, mtype, CPSW2_TS_SEQ_MTYPE); 14472e5b38abSRichard Cochran slave_write(slave, ctrl, CPSW2_CONTROL); 14482e5b38abSRichard Cochran __raw_writel(ETH_P_1588, &priv->regs->ts_ltype); 14492e5b38abSRichard Cochran } 14502e5b38abSRichard Cochran 1451a5b4145bSBen Hutchings static int cpsw_hwtstamp_set(struct net_device *dev, struct ifreq *ifr) 14522e5b38abSRichard Cochran { 14533177bf6fSMugunthan V N struct cpsw_priv *priv = netdev_priv(dev); 14549232b16dSMugunthan V N struct cpts *cpts = priv->cpts; 14552e5b38abSRichard Cochran struct hwtstamp_config cfg; 14562e5b38abSRichard Cochran 14572ee91e54SBen Hutchings if (priv->version != CPSW_VERSION_1 && 1458f7d403cbSGeorge Cherian priv->version != CPSW_VERSION_2 && 1459f7d403cbSGeorge Cherian priv->version != CPSW_VERSION_3) 14602ee91e54SBen Hutchings return -EOPNOTSUPP; 14612ee91e54SBen Hutchings 14622e5b38abSRichard Cochran if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg))) 14632e5b38abSRichard Cochran return -EFAULT; 14642e5b38abSRichard Cochran 14652e5b38abSRichard Cochran /* reserved for future extensions */ 14662e5b38abSRichard Cochran if (cfg.flags) 14672e5b38abSRichard Cochran return -EINVAL; 14682e5b38abSRichard Cochran 14692ee91e54SBen Hutchings if (cfg.tx_type != HWTSTAMP_TX_OFF && cfg.tx_type != HWTSTAMP_TX_ON) 14702e5b38abSRichard Cochran return -ERANGE; 14712e5b38abSRichard Cochran 14722e5b38abSRichard Cochran switch (cfg.rx_filter) { 14732e5b38abSRichard Cochran case HWTSTAMP_FILTER_NONE: 14742e5b38abSRichard Cochran cpts->rx_enable = 0; 14752e5b38abSRichard Cochran break; 14762e5b38abSRichard Cochran case HWTSTAMP_FILTER_ALL: 14772e5b38abSRichard Cochran case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: 14782e5b38abSRichard Cochran case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: 14792e5b38abSRichard Cochran case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: 14802e5b38abSRichard Cochran return -ERANGE; 14812e5b38abSRichard Cochran case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: 14822e5b38abSRichard Cochran case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 14832e5b38abSRichard Cochran case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 14842e5b38abSRichard Cochran case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: 14852e5b38abSRichard Cochran case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: 14862e5b38abSRichard Cochran case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: 14872e5b38abSRichard Cochran case HWTSTAMP_FILTER_PTP_V2_EVENT: 14882e5b38abSRichard Cochran case HWTSTAMP_FILTER_PTP_V2_SYNC: 14892e5b38abSRichard Cochran case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 14902e5b38abSRichard Cochran cpts->rx_enable = 1; 14912e5b38abSRichard Cochran cfg.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT; 14922e5b38abSRichard Cochran break; 14932e5b38abSRichard Cochran default: 14942e5b38abSRichard Cochran return -ERANGE; 14952e5b38abSRichard Cochran } 14962e5b38abSRichard Cochran 14972ee91e54SBen Hutchings cpts->tx_enable = cfg.tx_type == HWTSTAMP_TX_ON; 14982ee91e54SBen Hutchings 14992e5b38abSRichard Cochran switch (priv->version) { 15002e5b38abSRichard Cochran case CPSW_VERSION_1: 15012e5b38abSRichard Cochran cpsw_hwtstamp_v1(priv); 15022e5b38abSRichard Cochran break; 15032e5b38abSRichard Cochran case CPSW_VERSION_2: 1504f7d403cbSGeorge Cherian case CPSW_VERSION_3: 15052e5b38abSRichard Cochran cpsw_hwtstamp_v2(priv); 15062e5b38abSRichard Cochran break; 15072e5b38abSRichard Cochran default: 15082ee91e54SBen Hutchings WARN_ON(1); 15092e5b38abSRichard Cochran } 15102e5b38abSRichard Cochran 15112e5b38abSRichard Cochran return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0; 15122e5b38abSRichard Cochran } 15132e5b38abSRichard Cochran 1514a5b4145bSBen Hutchings static int cpsw_hwtstamp_get(struct net_device *dev, struct ifreq *ifr) 1515a5b4145bSBen Hutchings { 1516a5b4145bSBen Hutchings struct cpsw_priv *priv = netdev_priv(dev); 1517a5b4145bSBen Hutchings struct cpts *cpts = priv->cpts; 1518a5b4145bSBen Hutchings struct hwtstamp_config cfg; 1519a5b4145bSBen Hutchings 1520a5b4145bSBen Hutchings if (priv->version != CPSW_VERSION_1 && 1521f7d403cbSGeorge Cherian priv->version != CPSW_VERSION_2 && 1522f7d403cbSGeorge Cherian priv->version != CPSW_VERSION_3) 1523a5b4145bSBen Hutchings return -EOPNOTSUPP; 1524a5b4145bSBen Hutchings 1525a5b4145bSBen Hutchings cfg.flags = 0; 1526a5b4145bSBen Hutchings cfg.tx_type = cpts->tx_enable ? HWTSTAMP_TX_ON : HWTSTAMP_TX_OFF; 1527a5b4145bSBen Hutchings cfg.rx_filter = (cpts->rx_enable ? 1528a5b4145bSBen Hutchings HWTSTAMP_FILTER_PTP_V2_EVENT : HWTSTAMP_FILTER_NONE); 1529a5b4145bSBen Hutchings 1530a5b4145bSBen Hutchings return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0; 1531a5b4145bSBen Hutchings } 1532a5b4145bSBen Hutchings 15332e5b38abSRichard Cochran #endif /*CONFIG_TI_CPTS*/ 15342e5b38abSRichard Cochran 15352e5b38abSRichard Cochran static int cpsw_ndo_ioctl(struct net_device *dev, struct ifreq *req, int cmd) 15362e5b38abSRichard Cochran { 153711f2c988SMugunthan V N struct cpsw_priv *priv = netdev_priv(dev); 153811f2c988SMugunthan V N int slave_no = cpsw_slave_index(priv); 153911f2c988SMugunthan V N 15402e5b38abSRichard Cochran if (!netif_running(dev)) 15412e5b38abSRichard Cochran return -EINVAL; 15422e5b38abSRichard Cochran 154311f2c988SMugunthan V N switch (cmd) { 15442e5b38abSRichard Cochran #ifdef CONFIG_TI_CPTS 154511f2c988SMugunthan V N case SIOCSHWTSTAMP: 1546a5b4145bSBen Hutchings return cpsw_hwtstamp_set(dev, req); 1547a5b4145bSBen Hutchings case SIOCGHWTSTAMP: 1548a5b4145bSBen Hutchings return cpsw_hwtstamp_get(dev, req); 15492e5b38abSRichard Cochran #endif 15502e5b38abSRichard Cochran } 15512e5b38abSRichard Cochran 1552c1b59947SStefan Sørensen if (!priv->slaves[slave_no].phy) 1553c1b59947SStefan Sørensen return -EOPNOTSUPP; 1554c1b59947SStefan Sørensen return phy_mii_ioctl(priv->slaves[slave_no].phy, req, cmd); 155511f2c988SMugunthan V N } 155611f2c988SMugunthan V N 1557df828598SMugunthan V N static void cpsw_ndo_tx_timeout(struct net_device *ndev) 1558df828598SMugunthan V N { 1559df828598SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 1560df828598SMugunthan V N 1561df828598SMugunthan V N cpsw_err(priv, tx_err, "transmit timeout, restarting dma\n"); 15628dc43ddcSTobias Klauser ndev->stats.tx_errors++; 1563df828598SMugunthan V N cpsw_intr_disable(priv); 1564df828598SMugunthan V N cpdma_ctlr_int_ctrl(priv->dma, false); 1565df828598SMugunthan V N cpdma_chan_stop(priv->txch); 1566df828598SMugunthan V N cpdma_chan_start(priv->txch); 1567df828598SMugunthan V N cpdma_ctlr_int_ctrl(priv->dma, true); 1568df828598SMugunthan V N cpsw_intr_enable(priv); 1569510a1e72SMugunthan V N cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_RX); 1570510a1e72SMugunthan V N cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_TX); 1571510a1e72SMugunthan V N 1572df828598SMugunthan V N } 1573df828598SMugunthan V N 1574dcfd8d58SMugunthan V N static int cpsw_ndo_set_mac_address(struct net_device *ndev, void *p) 1575dcfd8d58SMugunthan V N { 1576dcfd8d58SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 1577dcfd8d58SMugunthan V N struct sockaddr *addr = (struct sockaddr *)p; 1578dcfd8d58SMugunthan V N int flags = 0; 1579dcfd8d58SMugunthan V N u16 vid = 0; 1580dcfd8d58SMugunthan V N 1581dcfd8d58SMugunthan V N if (!is_valid_ether_addr(addr->sa_data)) 1582dcfd8d58SMugunthan V N return -EADDRNOTAVAIL; 1583dcfd8d58SMugunthan V N 1584dcfd8d58SMugunthan V N if (priv->data.dual_emac) { 1585dcfd8d58SMugunthan V N vid = priv->slaves[priv->emac_port].port_vlan; 1586dcfd8d58SMugunthan V N flags = ALE_VLAN; 1587dcfd8d58SMugunthan V N } 1588dcfd8d58SMugunthan V N 1589dcfd8d58SMugunthan V N cpsw_ale_del_ucast(priv->ale, priv->mac_addr, priv->host_port, 1590dcfd8d58SMugunthan V N flags, vid); 1591dcfd8d58SMugunthan V N cpsw_ale_add_ucast(priv->ale, addr->sa_data, priv->host_port, 1592dcfd8d58SMugunthan V N flags, vid); 1593dcfd8d58SMugunthan V N 1594dcfd8d58SMugunthan V N memcpy(priv->mac_addr, addr->sa_data, ETH_ALEN); 1595dcfd8d58SMugunthan V N memcpy(ndev->dev_addr, priv->mac_addr, ETH_ALEN); 1596dcfd8d58SMugunthan V N for_each_slave(priv, cpsw_set_slave_mac, priv); 1597dcfd8d58SMugunthan V N 1598dcfd8d58SMugunthan V N return 0; 1599dcfd8d58SMugunthan V N } 1600dcfd8d58SMugunthan V N 1601df828598SMugunthan V N #ifdef CONFIG_NET_POLL_CONTROLLER 1602df828598SMugunthan V N static void cpsw_ndo_poll_controller(struct net_device *ndev) 1603df828598SMugunthan V N { 1604df828598SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 1605df828598SMugunthan V N 1606df828598SMugunthan V N cpsw_intr_disable(priv); 1607df828598SMugunthan V N cpdma_ctlr_int_ctrl(priv->dma, false); 1608df828598SMugunthan V N cpsw_interrupt(ndev->irq, priv); 1609df828598SMugunthan V N cpdma_ctlr_int_ctrl(priv->dma, true); 1610df828598SMugunthan V N cpsw_intr_enable(priv); 1611510a1e72SMugunthan V N cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_RX); 1612510a1e72SMugunthan V N cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_TX); 1613510a1e72SMugunthan V N 1614df828598SMugunthan V N } 1615df828598SMugunthan V N #endif 1616df828598SMugunthan V N 16173b72c2feSMugunthan V N static inline int cpsw_add_vlan_ale_entry(struct cpsw_priv *priv, 16183b72c2feSMugunthan V N unsigned short vid) 16193b72c2feSMugunthan V N { 16203b72c2feSMugunthan V N int ret; 16213b72c2feSMugunthan V N 16223b72c2feSMugunthan V N ret = cpsw_ale_add_vlan(priv->ale, vid, 16233b72c2feSMugunthan V N ALE_ALL_PORTS << priv->host_port, 16243b72c2feSMugunthan V N 0, ALE_ALL_PORTS << priv->host_port, 16253b72c2feSMugunthan V N (ALE_PORT_1 | ALE_PORT_2) << priv->host_port); 16263b72c2feSMugunthan V N if (ret != 0) 16273b72c2feSMugunthan V N return ret; 16283b72c2feSMugunthan V N 16293b72c2feSMugunthan V N ret = cpsw_ale_add_ucast(priv->ale, priv->mac_addr, 16303b72c2feSMugunthan V N priv->host_port, ALE_VLAN, vid); 16313b72c2feSMugunthan V N if (ret != 0) 16323b72c2feSMugunthan V N goto clean_vid; 16333b72c2feSMugunthan V N 16343b72c2feSMugunthan V N ret = cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast, 16353b72c2feSMugunthan V N ALE_ALL_PORTS << priv->host_port, 16363b72c2feSMugunthan V N ALE_VLAN, vid, 0); 16373b72c2feSMugunthan V N if (ret != 0) 16383b72c2feSMugunthan V N goto clean_vlan_ucast; 16393b72c2feSMugunthan V N return 0; 16403b72c2feSMugunthan V N 16413b72c2feSMugunthan V N clean_vlan_ucast: 16423b72c2feSMugunthan V N cpsw_ale_del_ucast(priv->ale, priv->mac_addr, 16433b72c2feSMugunthan V N priv->host_port, ALE_VLAN, vid); 16443b72c2feSMugunthan V N clean_vid: 16453b72c2feSMugunthan V N cpsw_ale_del_vlan(priv->ale, vid, 0); 16463b72c2feSMugunthan V N return ret; 16473b72c2feSMugunthan V N } 16483b72c2feSMugunthan V N 16493b72c2feSMugunthan V N static int cpsw_ndo_vlan_rx_add_vid(struct net_device *ndev, 165080d5c368SPatrick McHardy __be16 proto, u16 vid) 16513b72c2feSMugunthan V N { 16523b72c2feSMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 16533b72c2feSMugunthan V N 16543b72c2feSMugunthan V N if (vid == priv->data.default_vlan) 16553b72c2feSMugunthan V N return 0; 16563b72c2feSMugunthan V N 16573b72c2feSMugunthan V N dev_info(priv->dev, "Adding vlanid %d to vlan filter\n", vid); 16583b72c2feSMugunthan V N return cpsw_add_vlan_ale_entry(priv, vid); 16593b72c2feSMugunthan V N } 16603b72c2feSMugunthan V N 16613b72c2feSMugunthan V N static int cpsw_ndo_vlan_rx_kill_vid(struct net_device *ndev, 166280d5c368SPatrick McHardy __be16 proto, u16 vid) 16633b72c2feSMugunthan V N { 16643b72c2feSMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 16653b72c2feSMugunthan V N int ret; 16663b72c2feSMugunthan V N 16673b72c2feSMugunthan V N if (vid == priv->data.default_vlan) 16683b72c2feSMugunthan V N return 0; 16693b72c2feSMugunthan V N 16703b72c2feSMugunthan V N dev_info(priv->dev, "removing vlanid %d from vlan filter\n", vid); 16713b72c2feSMugunthan V N ret = cpsw_ale_del_vlan(priv->ale, vid, 0); 16723b72c2feSMugunthan V N if (ret != 0) 16733b72c2feSMugunthan V N return ret; 16743b72c2feSMugunthan V N 16753b72c2feSMugunthan V N ret = cpsw_ale_del_ucast(priv->ale, priv->mac_addr, 16763b72c2feSMugunthan V N priv->host_port, ALE_VLAN, vid); 16773b72c2feSMugunthan V N if (ret != 0) 16783b72c2feSMugunthan V N return ret; 16793b72c2feSMugunthan V N 16803b72c2feSMugunthan V N return cpsw_ale_del_mcast(priv->ale, priv->ndev->broadcast, 16813b72c2feSMugunthan V N 0, ALE_VLAN, vid); 16823b72c2feSMugunthan V N } 16833b72c2feSMugunthan V N 1684df828598SMugunthan V N static const struct net_device_ops cpsw_netdev_ops = { 1685df828598SMugunthan V N .ndo_open = cpsw_ndo_open, 1686df828598SMugunthan V N .ndo_stop = cpsw_ndo_stop, 1687df828598SMugunthan V N .ndo_start_xmit = cpsw_ndo_start_xmit, 1688dcfd8d58SMugunthan V N .ndo_set_mac_address = cpsw_ndo_set_mac_address, 16892e5b38abSRichard Cochran .ndo_do_ioctl = cpsw_ndo_ioctl, 1690df828598SMugunthan V N .ndo_validate_addr = eth_validate_addr, 16915c473ed2SDavid S. Miller .ndo_change_mtu = eth_change_mtu, 1692df828598SMugunthan V N .ndo_tx_timeout = cpsw_ndo_tx_timeout, 16935c50a856SMugunthan V N .ndo_set_rx_mode = cpsw_ndo_set_rx_mode, 1694df828598SMugunthan V N #ifdef CONFIG_NET_POLL_CONTROLLER 1695df828598SMugunthan V N .ndo_poll_controller = cpsw_ndo_poll_controller, 1696df828598SMugunthan V N #endif 16973b72c2feSMugunthan V N .ndo_vlan_rx_add_vid = cpsw_ndo_vlan_rx_add_vid, 16983b72c2feSMugunthan V N .ndo_vlan_rx_kill_vid = cpsw_ndo_vlan_rx_kill_vid, 1699df828598SMugunthan V N }; 1700df828598SMugunthan V N 170152c4f0ecSMugunthan V N static int cpsw_get_regs_len(struct net_device *ndev) 170252c4f0ecSMugunthan V N { 170352c4f0ecSMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 170452c4f0ecSMugunthan V N 170552c4f0ecSMugunthan V N return priv->data.ale_entries * ALE_ENTRY_WORDS * sizeof(u32); 170652c4f0ecSMugunthan V N } 170752c4f0ecSMugunthan V N 170852c4f0ecSMugunthan V N static void cpsw_get_regs(struct net_device *ndev, 170952c4f0ecSMugunthan V N struct ethtool_regs *regs, void *p) 171052c4f0ecSMugunthan V N { 171152c4f0ecSMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 171252c4f0ecSMugunthan V N u32 *reg = p; 171352c4f0ecSMugunthan V N 171452c4f0ecSMugunthan V N /* update CPSW IP version */ 171552c4f0ecSMugunthan V N regs->version = priv->version; 171652c4f0ecSMugunthan V N 171752c4f0ecSMugunthan V N cpsw_ale_dump(priv->ale, reg); 171852c4f0ecSMugunthan V N } 171952c4f0ecSMugunthan V N 1720df828598SMugunthan V N static void cpsw_get_drvinfo(struct net_device *ndev, 1721df828598SMugunthan V N struct ethtool_drvinfo *info) 1722df828598SMugunthan V N { 1723df828598SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 17247826d43fSJiri Pirko 172552c4f0ecSMugunthan V N strlcpy(info->driver, "cpsw", sizeof(info->driver)); 17267826d43fSJiri Pirko strlcpy(info->version, "1.0", sizeof(info->version)); 17277826d43fSJiri Pirko strlcpy(info->bus_info, priv->pdev->name, sizeof(info->bus_info)); 172852c4f0ecSMugunthan V N info->regdump_len = cpsw_get_regs_len(ndev); 1729df828598SMugunthan V N } 1730df828598SMugunthan V N 1731df828598SMugunthan V N static u32 cpsw_get_msglevel(struct net_device *ndev) 1732df828598SMugunthan V N { 1733df828598SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 1734df828598SMugunthan V N return priv->msg_enable; 1735df828598SMugunthan V N } 1736df828598SMugunthan V N 1737df828598SMugunthan V N static void cpsw_set_msglevel(struct net_device *ndev, u32 value) 1738df828598SMugunthan V N { 1739df828598SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 1740df828598SMugunthan V N priv->msg_enable = value; 1741df828598SMugunthan V N } 1742df828598SMugunthan V N 17432e5b38abSRichard Cochran static int cpsw_get_ts_info(struct net_device *ndev, 17442e5b38abSRichard Cochran struct ethtool_ts_info *info) 17452e5b38abSRichard Cochran { 17462e5b38abSRichard Cochran #ifdef CONFIG_TI_CPTS 17472e5b38abSRichard Cochran struct cpsw_priv *priv = netdev_priv(ndev); 17482e5b38abSRichard Cochran 17492e5b38abSRichard Cochran info->so_timestamping = 17502e5b38abSRichard Cochran SOF_TIMESTAMPING_TX_HARDWARE | 17512e5b38abSRichard Cochran SOF_TIMESTAMPING_TX_SOFTWARE | 17522e5b38abSRichard Cochran SOF_TIMESTAMPING_RX_HARDWARE | 17532e5b38abSRichard Cochran SOF_TIMESTAMPING_RX_SOFTWARE | 17542e5b38abSRichard Cochran SOF_TIMESTAMPING_SOFTWARE | 17552e5b38abSRichard Cochran SOF_TIMESTAMPING_RAW_HARDWARE; 17569232b16dSMugunthan V N info->phc_index = priv->cpts->phc_index; 17572e5b38abSRichard Cochran info->tx_types = 17582e5b38abSRichard Cochran (1 << HWTSTAMP_TX_OFF) | 17592e5b38abSRichard Cochran (1 << HWTSTAMP_TX_ON); 17602e5b38abSRichard Cochran info->rx_filters = 17612e5b38abSRichard Cochran (1 << HWTSTAMP_FILTER_NONE) | 17622e5b38abSRichard Cochran (1 << HWTSTAMP_FILTER_PTP_V2_EVENT); 17632e5b38abSRichard Cochran #else 17642e5b38abSRichard Cochran info->so_timestamping = 17652e5b38abSRichard Cochran SOF_TIMESTAMPING_TX_SOFTWARE | 17662e5b38abSRichard Cochran SOF_TIMESTAMPING_RX_SOFTWARE | 17672e5b38abSRichard Cochran SOF_TIMESTAMPING_SOFTWARE; 17682e5b38abSRichard Cochran info->phc_index = -1; 17692e5b38abSRichard Cochran info->tx_types = 0; 17702e5b38abSRichard Cochran info->rx_filters = 0; 17712e5b38abSRichard Cochran #endif 17722e5b38abSRichard Cochran return 0; 17732e5b38abSRichard Cochran } 17742e5b38abSRichard Cochran 1775d3bb9c58SMugunthan V N static int cpsw_get_settings(struct net_device *ndev, 1776d3bb9c58SMugunthan V N struct ethtool_cmd *ecmd) 1777d3bb9c58SMugunthan V N { 1778d3bb9c58SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 1779d3bb9c58SMugunthan V N int slave_no = cpsw_slave_index(priv); 1780d3bb9c58SMugunthan V N 1781d3bb9c58SMugunthan V N if (priv->slaves[slave_no].phy) 1782d3bb9c58SMugunthan V N return phy_ethtool_gset(priv->slaves[slave_no].phy, ecmd); 1783d3bb9c58SMugunthan V N else 1784d3bb9c58SMugunthan V N return -EOPNOTSUPP; 1785d3bb9c58SMugunthan V N } 1786d3bb9c58SMugunthan V N 1787d3bb9c58SMugunthan V N static int cpsw_set_settings(struct net_device *ndev, struct ethtool_cmd *ecmd) 1788d3bb9c58SMugunthan V N { 1789d3bb9c58SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 1790d3bb9c58SMugunthan V N int slave_no = cpsw_slave_index(priv); 1791d3bb9c58SMugunthan V N 1792d3bb9c58SMugunthan V N if (priv->slaves[slave_no].phy) 1793d3bb9c58SMugunthan V N return phy_ethtool_sset(priv->slaves[slave_no].phy, ecmd); 1794d3bb9c58SMugunthan V N else 1795d3bb9c58SMugunthan V N return -EOPNOTSUPP; 1796d3bb9c58SMugunthan V N } 1797d3bb9c58SMugunthan V N 1798d8a64420SMatus Ujhelyi static void cpsw_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol) 1799d8a64420SMatus Ujhelyi { 1800d8a64420SMatus Ujhelyi struct cpsw_priv *priv = netdev_priv(ndev); 1801d8a64420SMatus Ujhelyi int slave_no = cpsw_slave_index(priv); 1802d8a64420SMatus Ujhelyi 1803d8a64420SMatus Ujhelyi wol->supported = 0; 1804d8a64420SMatus Ujhelyi wol->wolopts = 0; 1805d8a64420SMatus Ujhelyi 1806d8a64420SMatus Ujhelyi if (priv->slaves[slave_no].phy) 1807d8a64420SMatus Ujhelyi phy_ethtool_get_wol(priv->slaves[slave_no].phy, wol); 1808d8a64420SMatus Ujhelyi } 1809d8a64420SMatus Ujhelyi 1810d8a64420SMatus Ujhelyi static int cpsw_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol) 1811d8a64420SMatus Ujhelyi { 1812d8a64420SMatus Ujhelyi struct cpsw_priv *priv = netdev_priv(ndev); 1813d8a64420SMatus Ujhelyi int slave_no = cpsw_slave_index(priv); 1814d8a64420SMatus Ujhelyi 1815d8a64420SMatus Ujhelyi if (priv->slaves[slave_no].phy) 1816d8a64420SMatus Ujhelyi return phy_ethtool_set_wol(priv->slaves[slave_no].phy, wol); 1817d8a64420SMatus Ujhelyi else 1818d8a64420SMatus Ujhelyi return -EOPNOTSUPP; 1819d8a64420SMatus Ujhelyi } 1820d8a64420SMatus Ujhelyi 18211923d6e4SMugunthan V N static void cpsw_get_pauseparam(struct net_device *ndev, 18221923d6e4SMugunthan V N struct ethtool_pauseparam *pause) 18231923d6e4SMugunthan V N { 18241923d6e4SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 18251923d6e4SMugunthan V N 18261923d6e4SMugunthan V N pause->autoneg = AUTONEG_DISABLE; 18271923d6e4SMugunthan V N pause->rx_pause = priv->rx_pause ? true : false; 18281923d6e4SMugunthan V N pause->tx_pause = priv->tx_pause ? true : false; 18291923d6e4SMugunthan V N } 18301923d6e4SMugunthan V N 18311923d6e4SMugunthan V N static int cpsw_set_pauseparam(struct net_device *ndev, 18321923d6e4SMugunthan V N struct ethtool_pauseparam *pause) 18331923d6e4SMugunthan V N { 18341923d6e4SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 18351923d6e4SMugunthan V N bool link; 18361923d6e4SMugunthan V N 18371923d6e4SMugunthan V N priv->rx_pause = pause->rx_pause ? true : false; 18381923d6e4SMugunthan V N priv->tx_pause = pause->tx_pause ? true : false; 18391923d6e4SMugunthan V N 18401923d6e4SMugunthan V N for_each_slave(priv, _cpsw_adjust_link, priv, &link); 18411923d6e4SMugunthan V N 18421923d6e4SMugunthan V N return 0; 18431923d6e4SMugunthan V N } 18441923d6e4SMugunthan V N 1845df828598SMugunthan V N static const struct ethtool_ops cpsw_ethtool_ops = { 1846df828598SMugunthan V N .get_drvinfo = cpsw_get_drvinfo, 1847df828598SMugunthan V N .get_msglevel = cpsw_get_msglevel, 1848df828598SMugunthan V N .set_msglevel = cpsw_set_msglevel, 1849df828598SMugunthan V N .get_link = ethtool_op_get_link, 18502e5b38abSRichard Cochran .get_ts_info = cpsw_get_ts_info, 1851d3bb9c58SMugunthan V N .get_settings = cpsw_get_settings, 1852d3bb9c58SMugunthan V N .set_settings = cpsw_set_settings, 1853ff5b8ef2SMugunthan V N .get_coalesce = cpsw_get_coalesce, 1854ff5b8ef2SMugunthan V N .set_coalesce = cpsw_set_coalesce, 1855d9718546SMugunthan V N .get_sset_count = cpsw_get_sset_count, 1856d9718546SMugunthan V N .get_strings = cpsw_get_strings, 1857d9718546SMugunthan V N .get_ethtool_stats = cpsw_get_ethtool_stats, 18581923d6e4SMugunthan V N .get_pauseparam = cpsw_get_pauseparam, 18591923d6e4SMugunthan V N .set_pauseparam = cpsw_set_pauseparam, 1860d8a64420SMatus Ujhelyi .get_wol = cpsw_get_wol, 1861d8a64420SMatus Ujhelyi .set_wol = cpsw_set_wol, 186252c4f0ecSMugunthan V N .get_regs_len = cpsw_get_regs_len, 186352c4f0ecSMugunthan V N .get_regs = cpsw_get_regs, 1864df828598SMugunthan V N }; 1865df828598SMugunthan V N 1866549985eeSRichard Cochran static void cpsw_slave_init(struct cpsw_slave *slave, struct cpsw_priv *priv, 1867549985eeSRichard Cochran u32 slave_reg_ofs, u32 sliver_reg_ofs) 1868df828598SMugunthan V N { 1869df828598SMugunthan V N void __iomem *regs = priv->regs; 1870df828598SMugunthan V N int slave_num = slave->slave_num; 1871df828598SMugunthan V N struct cpsw_slave_data *data = priv->data.slave_data + slave_num; 1872df828598SMugunthan V N 1873df828598SMugunthan V N slave->data = data; 1874549985eeSRichard Cochran slave->regs = regs + slave_reg_ofs; 1875549985eeSRichard Cochran slave->sliver = regs + sliver_reg_ofs; 1876d9ba8f9eSMugunthan V N slave->port_vlan = data->dual_emac_res_vlan; 1877df828598SMugunthan V N } 1878df828598SMugunthan V N 18792eb32b0aSMugunthan V N static int cpsw_probe_dt(struct cpsw_platform_data *data, 18802eb32b0aSMugunthan V N struct platform_device *pdev) 18812eb32b0aSMugunthan V N { 18822eb32b0aSMugunthan V N struct device_node *node = pdev->dev.of_node; 18832eb32b0aSMugunthan V N struct device_node *slave_node; 18842eb32b0aSMugunthan V N int i = 0, ret; 18852eb32b0aSMugunthan V N u32 prop; 18862eb32b0aSMugunthan V N 18872eb32b0aSMugunthan V N if (!node) 18882eb32b0aSMugunthan V N return -EINVAL; 18892eb32b0aSMugunthan V N 18902eb32b0aSMugunthan V N if (of_property_read_u32(node, "slaves", &prop)) { 189188c99ff6SGeorge Cherian dev_err(&pdev->dev, "Missing slaves property in the DT.\n"); 18922eb32b0aSMugunthan V N return -EINVAL; 18932eb32b0aSMugunthan V N } 18942eb32b0aSMugunthan V N data->slaves = prop; 18952eb32b0aSMugunthan V N 1896e86ac13bSMugunthan V N if (of_property_read_u32(node, "active_slave", &prop)) { 189788c99ff6SGeorge Cherian dev_err(&pdev->dev, "Missing active_slave property in the DT.\n"); 1898aa1a15e2SDaniel Mack return -EINVAL; 189978ca0b28SRichard Cochran } 1900e86ac13bSMugunthan V N data->active_slave = prop; 190178ca0b28SRichard Cochran 190200ab94eeSRichard Cochran if (of_property_read_u32(node, "cpts_clock_mult", &prop)) { 190388c99ff6SGeorge Cherian dev_err(&pdev->dev, "Missing cpts_clock_mult property in the DT.\n"); 1904aa1a15e2SDaniel Mack return -EINVAL; 190500ab94eeSRichard Cochran } 190600ab94eeSRichard Cochran data->cpts_clock_mult = prop; 190700ab94eeSRichard Cochran 190800ab94eeSRichard Cochran if (of_property_read_u32(node, "cpts_clock_shift", &prop)) { 190988c99ff6SGeorge Cherian dev_err(&pdev->dev, "Missing cpts_clock_shift property in the DT.\n"); 1910aa1a15e2SDaniel Mack return -EINVAL; 191100ab94eeSRichard Cochran } 191200ab94eeSRichard Cochran data->cpts_clock_shift = prop; 191300ab94eeSRichard Cochran 1914aa1a15e2SDaniel Mack data->slave_data = devm_kzalloc(&pdev->dev, data->slaves 1915aa1a15e2SDaniel Mack * sizeof(struct cpsw_slave_data), 1916b2adaca9SJoe Perches GFP_KERNEL); 1917b2adaca9SJoe Perches if (!data->slave_data) 1918aa1a15e2SDaniel Mack return -ENOMEM; 19192eb32b0aSMugunthan V N 19202eb32b0aSMugunthan V N if (of_property_read_u32(node, "cpdma_channels", &prop)) { 192188c99ff6SGeorge Cherian dev_err(&pdev->dev, "Missing cpdma_channels property in the DT.\n"); 1922aa1a15e2SDaniel Mack return -EINVAL; 19232eb32b0aSMugunthan V N } 19242eb32b0aSMugunthan V N data->channels = prop; 19252eb32b0aSMugunthan V N 19262eb32b0aSMugunthan V N if (of_property_read_u32(node, "ale_entries", &prop)) { 192788c99ff6SGeorge Cherian dev_err(&pdev->dev, "Missing ale_entries property in the DT.\n"); 1928aa1a15e2SDaniel Mack return -EINVAL; 19292eb32b0aSMugunthan V N } 19302eb32b0aSMugunthan V N data->ale_entries = prop; 19312eb32b0aSMugunthan V N 19322eb32b0aSMugunthan V N if (of_property_read_u32(node, "bd_ram_size", &prop)) { 193388c99ff6SGeorge Cherian dev_err(&pdev->dev, "Missing bd_ram_size property in the DT.\n"); 1934aa1a15e2SDaniel Mack return -EINVAL; 19352eb32b0aSMugunthan V N } 19362eb32b0aSMugunthan V N data->bd_ram_size = prop; 19372eb32b0aSMugunthan V N 19382eb32b0aSMugunthan V N if (of_property_read_u32(node, "rx_descs", &prop)) { 193988c99ff6SGeorge Cherian dev_err(&pdev->dev, "Missing rx_descs property in the DT.\n"); 1940aa1a15e2SDaniel Mack return -EINVAL; 19412eb32b0aSMugunthan V N } 19422eb32b0aSMugunthan V N data->rx_descs = prop; 19432eb32b0aSMugunthan V N 19442eb32b0aSMugunthan V N if (of_property_read_u32(node, "mac_control", &prop)) { 194588c99ff6SGeorge Cherian dev_err(&pdev->dev, "Missing mac_control property in the DT.\n"); 1946aa1a15e2SDaniel Mack return -EINVAL; 19472eb32b0aSMugunthan V N } 19482eb32b0aSMugunthan V N data->mac_control = prop; 19492eb32b0aSMugunthan V N 1950281abd96SMarkus Pargmann if (of_property_read_bool(node, "dual_emac")) 1951281abd96SMarkus Pargmann data->dual_emac = 1; 1952d9ba8f9eSMugunthan V N 19531fb19aa7SVaibhav Hiremath /* 19541fb19aa7SVaibhav Hiremath * Populate all the child nodes here... 19551fb19aa7SVaibhav Hiremath */ 19561fb19aa7SVaibhav Hiremath ret = of_platform_populate(node, NULL, NULL, &pdev->dev); 19571fb19aa7SVaibhav Hiremath /* We do not want to force this, as in some cases may not have child */ 19581fb19aa7SVaibhav Hiremath if (ret) 195988c99ff6SGeorge Cherian dev_warn(&pdev->dev, "Doesn't have any child node\n"); 19601fb19aa7SVaibhav Hiremath 1961f468b10eSMarkus Pargmann for_each_child_of_node(node, slave_node) { 1962549985eeSRichard Cochran struct cpsw_slave_data *slave_data = data->slave_data + i; 1963549985eeSRichard Cochran const void *mac_addr = NULL; 1964549985eeSRichard Cochran u32 phyid; 1965549985eeSRichard Cochran int lenp; 1966549985eeSRichard Cochran const __be32 *parp; 1967549985eeSRichard Cochran struct device_node *mdio_node; 1968549985eeSRichard Cochran struct platform_device *mdio; 1969549985eeSRichard Cochran 1970f468b10eSMarkus Pargmann /* This is no slave child node, continue */ 1971f468b10eSMarkus Pargmann if (strcmp(slave_node->name, "slave")) 1972f468b10eSMarkus Pargmann continue; 1973f468b10eSMarkus Pargmann 1974549985eeSRichard Cochran parp = of_get_property(slave_node, "phy_id", &lenp); 1975ce16294fSLothar Waßmann if ((parp == NULL) || (lenp != (sizeof(void *) * 2))) { 197688c99ff6SGeorge Cherian dev_err(&pdev->dev, "Missing slave[%d] phy_id property\n", i); 1977aa1a15e2SDaniel Mack return -EINVAL; 1978549985eeSRichard Cochran } 1979549985eeSRichard Cochran mdio_node = of_find_node_by_phandle(be32_to_cpup(parp)); 1980549985eeSRichard Cochran phyid = be32_to_cpup(parp+1); 1981549985eeSRichard Cochran mdio = of_find_device_by_node(mdio_node); 198260e71ab5SJohan Hovold of_node_put(mdio_node); 19836954cc1fSJohan Hovold if (!mdio) { 198456fdb2e0SMarkus Pargmann dev_err(&pdev->dev, "Missing mdio platform device\n"); 19856954cc1fSJohan Hovold return -EINVAL; 19866954cc1fSJohan Hovold } 1987549985eeSRichard Cochran snprintf(slave_data->phy_id, sizeof(slave_data->phy_id), 1988549985eeSRichard Cochran PHY_ID_FMT, mdio->name, phyid); 1989549985eeSRichard Cochran 1990549985eeSRichard Cochran mac_addr = of_get_mac_address(slave_node); 1991549985eeSRichard Cochran if (mac_addr) 1992549985eeSRichard Cochran memcpy(slave_data->mac_addr, mac_addr, ETH_ALEN); 1993549985eeSRichard Cochran 1994c5ceea7aSMugunthan V N slave_data->phy_if = of_get_phy_mode(slave_node); 199589e10172SUwe Kleine-König if (slave_data->phy_if < 0) { 199688c99ff6SGeorge Cherian dev_err(&pdev->dev, "Missing or malformed slave[%d] phy-mode property\n", 199789e10172SUwe Kleine-König i); 199889e10172SUwe Kleine-König return slave_data->phy_if; 199989e10172SUwe Kleine-König } 2000c5ceea7aSMugunthan V N 2001d9ba8f9eSMugunthan V N if (data->dual_emac) { 200291c4166cSMugunthan V N if (of_property_read_u32(slave_node, "dual_emac_res_vlan", 2003d9ba8f9eSMugunthan V N &prop)) { 200488c99ff6SGeorge Cherian dev_err(&pdev->dev, "Missing dual_emac_res_vlan in DT.\n"); 2005d9ba8f9eSMugunthan V N slave_data->dual_emac_res_vlan = i+1; 200688c99ff6SGeorge Cherian dev_err(&pdev->dev, "Using %d as Reserved VLAN for %d slave\n", 2007d9ba8f9eSMugunthan V N slave_data->dual_emac_res_vlan, i); 2008d9ba8f9eSMugunthan V N } else { 2009d9ba8f9eSMugunthan V N slave_data->dual_emac_res_vlan = prop; 2010d9ba8f9eSMugunthan V N } 2011d9ba8f9eSMugunthan V N } 2012d9ba8f9eSMugunthan V N 2013549985eeSRichard Cochran i++; 20143a27bfacSMugunthan V N if (i == data->slaves) 20153a27bfacSMugunthan V N break; 2016549985eeSRichard Cochran } 2017549985eeSRichard Cochran 20182eb32b0aSMugunthan V N return 0; 20192eb32b0aSMugunthan V N } 20202eb32b0aSMugunthan V N 2021d9ba8f9eSMugunthan V N static int cpsw_probe_dual_emac(struct platform_device *pdev, 2022d9ba8f9eSMugunthan V N struct cpsw_priv *priv) 2023d9ba8f9eSMugunthan V N { 2024d9ba8f9eSMugunthan V N struct cpsw_platform_data *data = &priv->data; 2025d9ba8f9eSMugunthan V N struct net_device *ndev; 2026d9ba8f9eSMugunthan V N struct cpsw_priv *priv_sl2; 2027d9ba8f9eSMugunthan V N int ret = 0, i; 2028d9ba8f9eSMugunthan V N 2029d9ba8f9eSMugunthan V N ndev = alloc_etherdev(sizeof(struct cpsw_priv)); 2030d9ba8f9eSMugunthan V N if (!ndev) { 203188c99ff6SGeorge Cherian dev_err(&pdev->dev, "cpsw: error allocating net_device\n"); 2032d9ba8f9eSMugunthan V N return -ENOMEM; 2033d9ba8f9eSMugunthan V N } 2034d9ba8f9eSMugunthan V N 2035d9ba8f9eSMugunthan V N priv_sl2 = netdev_priv(ndev); 2036d9ba8f9eSMugunthan V N spin_lock_init(&priv_sl2->lock); 2037d9ba8f9eSMugunthan V N priv_sl2->data = *data; 2038d9ba8f9eSMugunthan V N priv_sl2->pdev = pdev; 2039d9ba8f9eSMugunthan V N priv_sl2->ndev = ndev; 2040d9ba8f9eSMugunthan V N priv_sl2->dev = &ndev->dev; 2041d9ba8f9eSMugunthan V N priv_sl2->msg_enable = netif_msg_init(debug_level, CPSW_DEBUG); 2042d9ba8f9eSMugunthan V N priv_sl2->rx_packet_max = max(rx_packet_max, 128); 2043d9ba8f9eSMugunthan V N 2044d9ba8f9eSMugunthan V N if (is_valid_ether_addr(data->slave_data[1].mac_addr)) { 2045d9ba8f9eSMugunthan V N memcpy(priv_sl2->mac_addr, data->slave_data[1].mac_addr, 2046d9ba8f9eSMugunthan V N ETH_ALEN); 204788c99ff6SGeorge Cherian dev_info(&pdev->dev, "cpsw: Detected MACID = %pM\n", priv_sl2->mac_addr); 2048d9ba8f9eSMugunthan V N } else { 2049d9ba8f9eSMugunthan V N random_ether_addr(priv_sl2->mac_addr); 205088c99ff6SGeorge Cherian dev_info(&pdev->dev, "cpsw: Random MACID = %pM\n", priv_sl2->mac_addr); 2051d9ba8f9eSMugunthan V N } 2052d9ba8f9eSMugunthan V N memcpy(ndev->dev_addr, priv_sl2->mac_addr, ETH_ALEN); 2053d9ba8f9eSMugunthan V N 2054d9ba8f9eSMugunthan V N priv_sl2->slaves = priv->slaves; 2055d9ba8f9eSMugunthan V N priv_sl2->clk = priv->clk; 2056d9ba8f9eSMugunthan V N 2057ff5b8ef2SMugunthan V N priv_sl2->coal_intvl = 0; 2058ff5b8ef2SMugunthan V N priv_sl2->bus_freq_mhz = priv->bus_freq_mhz; 2059ff5b8ef2SMugunthan V N 2060d9ba8f9eSMugunthan V N priv_sl2->regs = priv->regs; 2061d9ba8f9eSMugunthan V N priv_sl2->host_port = priv->host_port; 2062d9ba8f9eSMugunthan V N priv_sl2->host_port_regs = priv->host_port_regs; 2063d9ba8f9eSMugunthan V N priv_sl2->wr_regs = priv->wr_regs; 2064d9718546SMugunthan V N priv_sl2->hw_stats = priv->hw_stats; 2065d9ba8f9eSMugunthan V N priv_sl2->dma = priv->dma; 2066d9ba8f9eSMugunthan V N priv_sl2->txch = priv->txch; 2067d9ba8f9eSMugunthan V N priv_sl2->rxch = priv->rxch; 2068d9ba8f9eSMugunthan V N priv_sl2->ale = priv->ale; 2069d9ba8f9eSMugunthan V N priv_sl2->emac_port = 1; 2070d9ba8f9eSMugunthan V N priv->slaves[1].ndev = ndev; 2071d9ba8f9eSMugunthan V N priv_sl2->cpts = priv->cpts; 2072d9ba8f9eSMugunthan V N priv_sl2->version = priv->version; 2073d9ba8f9eSMugunthan V N 2074d9ba8f9eSMugunthan V N for (i = 0; i < priv->num_irqs; i++) { 2075d9ba8f9eSMugunthan V N priv_sl2->irqs_table[i] = priv->irqs_table[i]; 2076d9ba8f9eSMugunthan V N priv_sl2->num_irqs = priv->num_irqs; 2077d9ba8f9eSMugunthan V N } 2078f646968fSPatrick McHardy ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER; 2079d9ba8f9eSMugunthan V N 2080d9ba8f9eSMugunthan V N ndev->netdev_ops = &cpsw_netdev_ops; 20817ad24ea4SWilfried Klaebe ndev->ethtool_ops = &cpsw_ethtool_ops; 2082d9ba8f9eSMugunthan V N netif_napi_add(ndev, &priv_sl2->napi, cpsw_poll, CPSW_POLL_WEIGHT); 2083d9ba8f9eSMugunthan V N 2084d9ba8f9eSMugunthan V N /* register the network device */ 2085d9ba8f9eSMugunthan V N SET_NETDEV_DEV(ndev, &pdev->dev); 2086d9ba8f9eSMugunthan V N ret = register_netdev(ndev); 2087d9ba8f9eSMugunthan V N if (ret) { 208888c99ff6SGeorge Cherian dev_err(&pdev->dev, "cpsw: error registering net device\n"); 2089d9ba8f9eSMugunthan V N free_netdev(ndev); 2090d9ba8f9eSMugunthan V N ret = -ENODEV; 2091d9ba8f9eSMugunthan V N } 2092d9ba8f9eSMugunthan V N 2093d9ba8f9eSMugunthan V N return ret; 2094d9ba8f9eSMugunthan V N } 2095d9ba8f9eSMugunthan V N 2096663e12e6SBill Pemberton static int cpsw_probe(struct platform_device *pdev) 2097df828598SMugunthan V N { 2098d1bd9acfSSebastian Siewior struct cpsw_platform_data *data; 2099df828598SMugunthan V N struct net_device *ndev; 2100df828598SMugunthan V N struct cpsw_priv *priv; 2101df828598SMugunthan V N struct cpdma_params dma_params; 2102df828598SMugunthan V N struct cpsw_ale_params ale_params; 2103aa1a15e2SDaniel Mack void __iomem *ss_regs; 2104aa1a15e2SDaniel Mack struct resource *res, *ss_res; 2105549985eeSRichard Cochran u32 slave_offset, sliver_offset, slave_size; 2106df828598SMugunthan V N int ret = 0, i, k = 0; 2107df828598SMugunthan V N 2108df828598SMugunthan V N ndev = alloc_etherdev(sizeof(struct cpsw_priv)); 2109df828598SMugunthan V N if (!ndev) { 211088c99ff6SGeorge Cherian dev_err(&pdev->dev, "error allocating net_device\n"); 2111df828598SMugunthan V N return -ENOMEM; 2112df828598SMugunthan V N } 2113df828598SMugunthan V N 2114df828598SMugunthan V N platform_set_drvdata(pdev, ndev); 2115df828598SMugunthan V N priv = netdev_priv(ndev); 2116df828598SMugunthan V N spin_lock_init(&priv->lock); 2117df828598SMugunthan V N priv->pdev = pdev; 2118df828598SMugunthan V N priv->ndev = ndev; 2119df828598SMugunthan V N priv->dev = &ndev->dev; 2120df828598SMugunthan V N priv->msg_enable = netif_msg_init(debug_level, CPSW_DEBUG); 2121df828598SMugunthan V N priv->rx_packet_max = max(rx_packet_max, 128); 21229232b16dSMugunthan V N priv->cpts = devm_kzalloc(&pdev->dev, sizeof(struct cpts), GFP_KERNEL); 21237dcf313aSMugunthan V N priv->irq_enabled = true; 2124ab8e99d2SSebastian Siewior if (!priv->cpts) { 212588c99ff6SGeorge Cherian dev_err(&pdev->dev, "error allocating cpts\n"); 21264d507dffSMarkus Pargmann ret = -ENOMEM; 21279232b16dSMugunthan V N goto clean_ndev_ret; 21289232b16dSMugunthan V N } 2129df828598SMugunthan V N 21301fb19aa7SVaibhav Hiremath /* 21311fb19aa7SVaibhav Hiremath * This may be required here for child devices. 21321fb19aa7SVaibhav Hiremath */ 21331fb19aa7SVaibhav Hiremath pm_runtime_enable(&pdev->dev); 21341fb19aa7SVaibhav Hiremath 2135739683b4SMugunthan V N /* Select default pin state */ 2136739683b4SMugunthan V N pinctrl_pm_select_default_state(&pdev->dev); 2137739683b4SMugunthan V N 21382eb32b0aSMugunthan V N if (cpsw_probe_dt(&priv->data, pdev)) { 213988c99ff6SGeorge Cherian dev_err(&pdev->dev, "cpsw: platform data missing\n"); 21402eb32b0aSMugunthan V N ret = -ENODEV; 2141aa1a15e2SDaniel Mack goto clean_runtime_disable_ret; 21422eb32b0aSMugunthan V N } 21432eb32b0aSMugunthan V N data = &priv->data; 21442eb32b0aSMugunthan V N 2145df828598SMugunthan V N if (is_valid_ether_addr(data->slave_data[0].mac_addr)) { 2146df828598SMugunthan V N memcpy(priv->mac_addr, data->slave_data[0].mac_addr, ETH_ALEN); 214788c99ff6SGeorge Cherian dev_info(&pdev->dev, "Detected MACID = %pM\n", priv->mac_addr); 2148df828598SMugunthan V N } else { 21497efd26d0SJoe Perches eth_random_addr(priv->mac_addr); 215088c99ff6SGeorge Cherian dev_info(&pdev->dev, "Random MACID = %pM\n", priv->mac_addr); 2151df828598SMugunthan V N } 2152df828598SMugunthan V N 2153df828598SMugunthan V N memcpy(ndev->dev_addr, priv->mac_addr, ETH_ALEN); 2154df828598SMugunthan V N 2155aa1a15e2SDaniel Mack priv->slaves = devm_kzalloc(&pdev->dev, 2156aa1a15e2SDaniel Mack sizeof(struct cpsw_slave) * data->slaves, 2157df828598SMugunthan V N GFP_KERNEL); 2158df828598SMugunthan V N if (!priv->slaves) { 2159aa1a15e2SDaniel Mack ret = -ENOMEM; 2160aa1a15e2SDaniel Mack goto clean_runtime_disable_ret; 2161df828598SMugunthan V N } 2162df828598SMugunthan V N for (i = 0; i < data->slaves; i++) 2163df828598SMugunthan V N priv->slaves[i].slave_num = i; 2164df828598SMugunthan V N 2165d9ba8f9eSMugunthan V N priv->slaves[0].ndev = ndev; 2166d9ba8f9eSMugunthan V N priv->emac_port = 0; 2167d9ba8f9eSMugunthan V N 2168aa1a15e2SDaniel Mack priv->clk = devm_clk_get(&pdev->dev, "fck"); 2169df828598SMugunthan V N if (IS_ERR(priv->clk)) { 2170aa1a15e2SDaniel Mack dev_err(priv->dev, "fck is not found\n"); 2171f150bd7fSMugunthan V N ret = -ENODEV; 2172aa1a15e2SDaniel Mack goto clean_runtime_disable_ret; 2173df828598SMugunthan V N } 2174ff5b8ef2SMugunthan V N priv->coal_intvl = 0; 2175ff5b8ef2SMugunthan V N priv->bus_freq_mhz = clk_get_rate(priv->clk) / 1000000; 2176df828598SMugunthan V N 2177aa1a15e2SDaniel Mack ss_res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2178aa1a15e2SDaniel Mack ss_regs = devm_ioremap_resource(&pdev->dev, ss_res); 2179aa1a15e2SDaniel Mack if (IS_ERR(ss_regs)) { 2180aa1a15e2SDaniel Mack ret = PTR_ERR(ss_regs); 2181aa1a15e2SDaniel Mack goto clean_runtime_disable_ret; 2182df828598SMugunthan V N } 2183549985eeSRichard Cochran priv->regs = ss_regs; 2184549985eeSRichard Cochran priv->host_port = HOST_PORT_NUM; 2185df828598SMugunthan V N 2186f280e89aSMugunthan V N /* Need to enable clocks with runtime PM api to access module 2187f280e89aSMugunthan V N * registers 2188f280e89aSMugunthan V N */ 2189f280e89aSMugunthan V N pm_runtime_get_sync(&pdev->dev); 2190f280e89aSMugunthan V N priv->version = readl(&priv->regs->id_ver); 2191f280e89aSMugunthan V N pm_runtime_put_sync(&pdev->dev); 2192f280e89aSMugunthan V N 2193aa1a15e2SDaniel Mack res = platform_get_resource(pdev, IORESOURCE_MEM, 1); 2194aa1a15e2SDaniel Mack priv->wr_regs = devm_ioremap_resource(&pdev->dev, res); 2195aa1a15e2SDaniel Mack if (IS_ERR(priv->wr_regs)) { 2196aa1a15e2SDaniel Mack ret = PTR_ERR(priv->wr_regs); 2197aa1a15e2SDaniel Mack goto clean_runtime_disable_ret; 2198df828598SMugunthan V N } 2199df828598SMugunthan V N 2200df828598SMugunthan V N memset(&dma_params, 0, sizeof(dma_params)); 2201549985eeSRichard Cochran memset(&ale_params, 0, sizeof(ale_params)); 2202549985eeSRichard Cochran 2203549985eeSRichard Cochran switch (priv->version) { 2204549985eeSRichard Cochran case CPSW_VERSION_1: 2205549985eeSRichard Cochran priv->host_port_regs = ss_regs + CPSW1_HOST_PORT_OFFSET; 22069232b16dSMugunthan V N priv->cpts->reg = ss_regs + CPSW1_CPTS_OFFSET; 2207d9718546SMugunthan V N priv->hw_stats = ss_regs + CPSW1_HW_STATS; 2208549985eeSRichard Cochran dma_params.dmaregs = ss_regs + CPSW1_CPDMA_OFFSET; 2209549985eeSRichard Cochran dma_params.txhdp = ss_regs + CPSW1_STATERAM_OFFSET; 2210549985eeSRichard Cochran ale_params.ale_regs = ss_regs + CPSW1_ALE_OFFSET; 2211549985eeSRichard Cochran slave_offset = CPSW1_SLAVE_OFFSET; 2212549985eeSRichard Cochran slave_size = CPSW1_SLAVE_SIZE; 2213549985eeSRichard Cochran sliver_offset = CPSW1_SLIVER_OFFSET; 2214549985eeSRichard Cochran dma_params.desc_mem_phys = 0; 2215549985eeSRichard Cochran break; 2216549985eeSRichard Cochran case CPSW_VERSION_2: 2217c193f365SMugunthan V N case CPSW_VERSION_3: 2218926489beSMugunthan V N case CPSW_VERSION_4: 2219549985eeSRichard Cochran priv->host_port_regs = ss_regs + CPSW2_HOST_PORT_OFFSET; 22209232b16dSMugunthan V N priv->cpts->reg = ss_regs + CPSW2_CPTS_OFFSET; 2221d9718546SMugunthan V N priv->hw_stats = ss_regs + CPSW2_HW_STATS; 2222549985eeSRichard Cochran dma_params.dmaregs = ss_regs + CPSW2_CPDMA_OFFSET; 2223549985eeSRichard Cochran dma_params.txhdp = ss_regs + CPSW2_STATERAM_OFFSET; 2224549985eeSRichard Cochran ale_params.ale_regs = ss_regs + CPSW2_ALE_OFFSET; 2225549985eeSRichard Cochran slave_offset = CPSW2_SLAVE_OFFSET; 2226549985eeSRichard Cochran slave_size = CPSW2_SLAVE_SIZE; 2227549985eeSRichard Cochran sliver_offset = CPSW2_SLIVER_OFFSET; 2228549985eeSRichard Cochran dma_params.desc_mem_phys = 2229aa1a15e2SDaniel Mack (u32 __force) ss_res->start + CPSW2_BD_OFFSET; 2230549985eeSRichard Cochran break; 2231549985eeSRichard Cochran default: 2232549985eeSRichard Cochran dev_err(priv->dev, "unknown version 0x%08x\n", priv->version); 2233549985eeSRichard Cochran ret = -ENODEV; 2234aa1a15e2SDaniel Mack goto clean_runtime_disable_ret; 2235549985eeSRichard Cochran } 2236549985eeSRichard Cochran for (i = 0; i < priv->data.slaves; i++) { 2237549985eeSRichard Cochran struct cpsw_slave *slave = &priv->slaves[i]; 2238549985eeSRichard Cochran cpsw_slave_init(slave, priv, slave_offset, sliver_offset); 2239549985eeSRichard Cochran slave_offset += slave_size; 2240549985eeSRichard Cochran sliver_offset += SLIVER_SIZE; 2241549985eeSRichard Cochran } 2242549985eeSRichard Cochran 2243df828598SMugunthan V N dma_params.dev = &pdev->dev; 2244549985eeSRichard Cochran dma_params.rxthresh = dma_params.dmaregs + CPDMA_RXTHRESH; 2245549985eeSRichard Cochran dma_params.rxfree = dma_params.dmaregs + CPDMA_RXFREE; 2246549985eeSRichard Cochran dma_params.rxhdp = dma_params.txhdp + CPDMA_RXHDP; 2247549985eeSRichard Cochran dma_params.txcp = dma_params.txhdp + CPDMA_TXCP; 2248549985eeSRichard Cochran dma_params.rxcp = dma_params.txhdp + CPDMA_RXCP; 2249df828598SMugunthan V N 2250df828598SMugunthan V N dma_params.num_chan = data->channels; 2251df828598SMugunthan V N dma_params.has_soft_reset = true; 2252df828598SMugunthan V N dma_params.min_packet_size = CPSW_MIN_PACKET_SIZE; 2253df828598SMugunthan V N dma_params.desc_mem_size = data->bd_ram_size; 2254df828598SMugunthan V N dma_params.desc_align = 16; 2255df828598SMugunthan V N dma_params.has_ext_regs = true; 2256549985eeSRichard Cochran dma_params.desc_hw_addr = dma_params.desc_mem_phys; 2257df828598SMugunthan V N 2258df828598SMugunthan V N priv->dma = cpdma_ctlr_create(&dma_params); 2259df828598SMugunthan V N if (!priv->dma) { 2260df828598SMugunthan V N dev_err(priv->dev, "error initializing dma\n"); 2261df828598SMugunthan V N ret = -ENOMEM; 2262aa1a15e2SDaniel Mack goto clean_runtime_disable_ret; 2263df828598SMugunthan V N } 2264df828598SMugunthan V N 2265df828598SMugunthan V N priv->txch = cpdma_chan_create(priv->dma, tx_chan_num(0), 2266df828598SMugunthan V N cpsw_tx_handler); 2267df828598SMugunthan V N priv->rxch = cpdma_chan_create(priv->dma, rx_chan_num(0), 2268df828598SMugunthan V N cpsw_rx_handler); 2269df828598SMugunthan V N 2270df828598SMugunthan V N if (WARN_ON(!priv->txch || !priv->rxch)) { 2271df828598SMugunthan V N dev_err(priv->dev, "error initializing dma channels\n"); 2272df828598SMugunthan V N ret = -ENOMEM; 2273df828598SMugunthan V N goto clean_dma_ret; 2274df828598SMugunthan V N } 2275df828598SMugunthan V N 2276df828598SMugunthan V N ale_params.dev = &ndev->dev; 2277df828598SMugunthan V N ale_params.ale_ageout = ale_ageout; 2278df828598SMugunthan V N ale_params.ale_entries = data->ale_entries; 2279df828598SMugunthan V N ale_params.ale_ports = data->slaves; 2280df828598SMugunthan V N 2281df828598SMugunthan V N priv->ale = cpsw_ale_create(&ale_params); 2282df828598SMugunthan V N if (!priv->ale) { 2283df828598SMugunthan V N dev_err(priv->dev, "error initializing ale engine\n"); 2284df828598SMugunthan V N ret = -ENODEV; 2285df828598SMugunthan V N goto clean_dma_ret; 2286df828598SMugunthan V N } 2287df828598SMugunthan V N 2288df828598SMugunthan V N ndev->irq = platform_get_irq(pdev, 0); 2289df828598SMugunthan V N if (ndev->irq < 0) { 2290df828598SMugunthan V N dev_err(priv->dev, "error getting irq resource\n"); 2291df828598SMugunthan V N ret = -ENOENT; 2292df828598SMugunthan V N goto clean_ale_ret; 2293df828598SMugunthan V N } 2294df828598SMugunthan V N 2295df828598SMugunthan V N while ((res = platform_get_resource(priv->pdev, IORESOURCE_IRQ, k))) { 2296c2b32e58SDaniel Mack if (k >= ARRAY_SIZE(priv->irqs_table)) { 2297c2b32e58SDaniel Mack ret = -EINVAL; 2298df828598SMugunthan V N goto clean_ale_ret; 2299df828598SMugunthan V N } 2300c2b32e58SDaniel Mack 2301c2b32e58SDaniel Mack ret = devm_request_irq(&pdev->dev, res->start, cpsw_interrupt, 2302c2b32e58SDaniel Mack 0, dev_name(&pdev->dev), priv); 2303c2b32e58SDaniel Mack if (ret < 0) { 2304c2b32e58SDaniel Mack dev_err(priv->dev, "error attaching irq (%d)\n", ret); 2305c2b32e58SDaniel Mack goto clean_ale_ret; 2306df828598SMugunthan V N } 2307c2b32e58SDaniel Mack 2308c2b32e58SDaniel Mack priv->irqs_table[k] = res->start; 2309df828598SMugunthan V N k++; 2310df828598SMugunthan V N } 2311df828598SMugunthan V N 2312c2b32e58SDaniel Mack priv->num_irqs = k; 2313c2b32e58SDaniel Mack 2314f646968fSPatrick McHardy ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER; 2315df828598SMugunthan V N 2316df828598SMugunthan V N ndev->netdev_ops = &cpsw_netdev_ops; 23177ad24ea4SWilfried Klaebe ndev->ethtool_ops = &cpsw_ethtool_ops; 2318df828598SMugunthan V N netif_napi_add(ndev, &priv->napi, cpsw_poll, CPSW_POLL_WEIGHT); 2319df828598SMugunthan V N 2320df828598SMugunthan V N /* register the network device */ 2321df828598SMugunthan V N SET_NETDEV_DEV(ndev, &pdev->dev); 2322df828598SMugunthan V N ret = register_netdev(ndev); 2323df828598SMugunthan V N if (ret) { 2324df828598SMugunthan V N dev_err(priv->dev, "error registering net device\n"); 2325df828598SMugunthan V N ret = -ENODEV; 2326aa1a15e2SDaniel Mack goto clean_ale_ret; 2327df828598SMugunthan V N } 2328df828598SMugunthan V N 23291a3b5056SOlof Johansson cpsw_notice(priv, probe, "initialized device (regs %pa, irq %d)\n", 23301a3b5056SOlof Johansson &ss_res->start, ndev->irq); 2331df828598SMugunthan V N 2332d9ba8f9eSMugunthan V N if (priv->data.dual_emac) { 2333d9ba8f9eSMugunthan V N ret = cpsw_probe_dual_emac(pdev, priv); 2334d9ba8f9eSMugunthan V N if (ret) { 2335d9ba8f9eSMugunthan V N cpsw_err(priv, probe, "error probe slave 2 emac interface\n"); 2336aa1a15e2SDaniel Mack goto clean_ale_ret; 2337d9ba8f9eSMugunthan V N } 2338d9ba8f9eSMugunthan V N } 2339d9ba8f9eSMugunthan V N 2340df828598SMugunthan V N return 0; 2341df828598SMugunthan V N 2342df828598SMugunthan V N clean_ale_ret: 2343df828598SMugunthan V N cpsw_ale_destroy(priv->ale); 2344df828598SMugunthan V N clean_dma_ret: 2345df828598SMugunthan V N cpdma_chan_destroy(priv->txch); 2346df828598SMugunthan V N cpdma_chan_destroy(priv->rxch); 2347df828598SMugunthan V N cpdma_ctlr_destroy(priv->dma); 2348aa1a15e2SDaniel Mack clean_runtime_disable_ret: 2349f150bd7fSMugunthan V N pm_runtime_disable(&pdev->dev); 2350df828598SMugunthan V N clean_ndev_ret: 2351d1bd9acfSSebastian Siewior free_netdev(priv->ndev); 2352df828598SMugunthan V N return ret; 2353df828598SMugunthan V N } 2354df828598SMugunthan V N 2355663e12e6SBill Pemberton static int cpsw_remove(struct platform_device *pdev) 2356df828598SMugunthan V N { 2357df828598SMugunthan V N struct net_device *ndev = platform_get_drvdata(pdev); 2358df828598SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 2359df828598SMugunthan V N 2360d1bd9acfSSebastian Siewior if (priv->data.dual_emac) 2361d1bd9acfSSebastian Siewior unregister_netdev(cpsw_get_slave_ndev(priv, 1)); 2362d1bd9acfSSebastian Siewior unregister_netdev(ndev); 2363df828598SMugunthan V N 2364df828598SMugunthan V N cpsw_ale_destroy(priv->ale); 2365df828598SMugunthan V N cpdma_chan_destroy(priv->txch); 2366df828598SMugunthan V N cpdma_chan_destroy(priv->rxch); 2367df828598SMugunthan V N cpdma_ctlr_destroy(priv->dma); 2368f150bd7fSMugunthan V N pm_runtime_disable(&pdev->dev); 2369d1bd9acfSSebastian Siewior if (priv->data.dual_emac) 2370d1bd9acfSSebastian Siewior free_netdev(cpsw_get_slave_ndev(priv, 1)); 2371df828598SMugunthan V N free_netdev(ndev); 2372df828598SMugunthan V N return 0; 2373df828598SMugunthan V N } 2374df828598SMugunthan V N 2375df828598SMugunthan V N static int cpsw_suspend(struct device *dev) 2376df828598SMugunthan V N { 2377df828598SMugunthan V N struct platform_device *pdev = to_platform_device(dev); 2378df828598SMugunthan V N struct net_device *ndev = platform_get_drvdata(pdev); 2379b90fc27aSMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 2380df828598SMugunthan V N 2381618073e3SMugunthan V N if (priv->data.dual_emac) { 2382618073e3SMugunthan V N int i; 2383618073e3SMugunthan V N 2384618073e3SMugunthan V N for (i = 0; i < priv->data.slaves; i++) { 2385618073e3SMugunthan V N if (netif_running(priv->slaves[i].ndev)) 2386618073e3SMugunthan V N cpsw_ndo_stop(priv->slaves[i].ndev); 2387618073e3SMugunthan V N soft_reset_slave(priv->slaves + i); 2388618073e3SMugunthan V N } 2389618073e3SMugunthan V N } else { 2390df828598SMugunthan V N if (netif_running(ndev)) 2391df828598SMugunthan V N cpsw_ndo_stop(ndev); 23921e7a2e21SDaniel Mack for_each_slave(priv, soft_reset_slave); 2393618073e3SMugunthan V N } 23941e7a2e21SDaniel Mack 2395f150bd7fSMugunthan V N pm_runtime_put_sync(&pdev->dev); 2396f150bd7fSMugunthan V N 2397739683b4SMugunthan V N /* Select sleep pin state */ 2398739683b4SMugunthan V N pinctrl_pm_select_sleep_state(&pdev->dev); 2399739683b4SMugunthan V N 2400df828598SMugunthan V N return 0; 2401df828598SMugunthan V N } 2402df828598SMugunthan V N 2403df828598SMugunthan V N static int cpsw_resume(struct device *dev) 2404df828598SMugunthan V N { 2405df828598SMugunthan V N struct platform_device *pdev = to_platform_device(dev); 2406df828598SMugunthan V N struct net_device *ndev = platform_get_drvdata(pdev); 2407618073e3SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 2408df828598SMugunthan V N 2409f150bd7fSMugunthan V N pm_runtime_get_sync(&pdev->dev); 2410739683b4SMugunthan V N 2411739683b4SMugunthan V N /* Select default pin state */ 2412739683b4SMugunthan V N pinctrl_pm_select_default_state(&pdev->dev); 2413739683b4SMugunthan V N 2414618073e3SMugunthan V N if (priv->data.dual_emac) { 2415618073e3SMugunthan V N int i; 2416618073e3SMugunthan V N 2417618073e3SMugunthan V N for (i = 0; i < priv->data.slaves; i++) { 2418618073e3SMugunthan V N if (netif_running(priv->slaves[i].ndev)) 2419618073e3SMugunthan V N cpsw_ndo_open(priv->slaves[i].ndev); 2420618073e3SMugunthan V N } 2421618073e3SMugunthan V N } else { 2422df828598SMugunthan V N if (netif_running(ndev)) 2423df828598SMugunthan V N cpsw_ndo_open(ndev); 2424618073e3SMugunthan V N } 2425df828598SMugunthan V N return 0; 2426df828598SMugunthan V N } 2427df828598SMugunthan V N 2428df828598SMugunthan V N static const struct dev_pm_ops cpsw_pm_ops = { 2429df828598SMugunthan V N .suspend = cpsw_suspend, 2430df828598SMugunthan V N .resume = cpsw_resume, 2431df828598SMugunthan V N }; 2432df828598SMugunthan V N 24332eb32b0aSMugunthan V N static const struct of_device_id cpsw_of_mtable[] = { 24342eb32b0aSMugunthan V N { .compatible = "ti,cpsw", }, 24352eb32b0aSMugunthan V N { /* sentinel */ }, 24362eb32b0aSMugunthan V N }; 24374bc21d41SSebastian Siewior MODULE_DEVICE_TABLE(of, cpsw_of_mtable); 24382eb32b0aSMugunthan V N 2439df828598SMugunthan V N static struct platform_driver cpsw_driver = { 2440df828598SMugunthan V N .driver = { 2441df828598SMugunthan V N .name = "cpsw", 2442df828598SMugunthan V N .pm = &cpsw_pm_ops, 24431e5c76d4SSachin Kamat .of_match_table = cpsw_of_mtable, 2444df828598SMugunthan V N }, 2445df828598SMugunthan V N .probe = cpsw_probe, 2446663e12e6SBill Pemberton .remove = cpsw_remove, 2447df828598SMugunthan V N }; 2448df828598SMugunthan V N 2449df828598SMugunthan V N static int __init cpsw_init(void) 2450df828598SMugunthan V N { 2451df828598SMugunthan V N return platform_driver_register(&cpsw_driver); 2452df828598SMugunthan V N } 2453df828598SMugunthan V N late_initcall(cpsw_init); 2454df828598SMugunthan V N 2455df828598SMugunthan V N static void __exit cpsw_exit(void) 2456df828598SMugunthan V N { 2457df828598SMugunthan V N platform_driver_unregister(&cpsw_driver); 2458df828598SMugunthan V N } 2459df828598SMugunthan V N module_exit(cpsw_exit); 2460df828598SMugunthan V N 2461df828598SMugunthan V N MODULE_LICENSE("GPL"); 2462df828598SMugunthan V N MODULE_AUTHOR("Cyril Chemparathy <cyril@ti.com>"); 2463df828598SMugunthan V N MODULE_AUTHOR("Mugunthan V N <mugunthanvnm@ti.com>"); 2464df828598SMugunthan V N MODULE_DESCRIPTION("TI CPSW Ethernet driver"); 2465