1df828598SMugunthan V N /* 2df828598SMugunthan V N * Texas Instruments Ethernet Switch Driver 3df828598SMugunthan V N * 4df828598SMugunthan V N * Copyright (C) 2012 Texas Instruments 5df828598SMugunthan V N * 6df828598SMugunthan V N * This program is free software; you can redistribute it and/or 7df828598SMugunthan V N * modify it under the terms of the GNU General Public License as 8df828598SMugunthan V N * published by the Free Software Foundation version 2. 9df828598SMugunthan V N * 10df828598SMugunthan V N * This program is distributed "as is" WITHOUT ANY WARRANTY of any 11df828598SMugunthan V N * kind, whether express or implied; without even the implied warranty 12df828598SMugunthan V N * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13df828598SMugunthan V N * GNU General Public License for more details. 14df828598SMugunthan V N */ 15df828598SMugunthan V N 16df828598SMugunthan V N #include <linux/kernel.h> 17df828598SMugunthan V N #include <linux/io.h> 18df828598SMugunthan V N #include <linux/clk.h> 19df828598SMugunthan V N #include <linux/timer.h> 20df828598SMugunthan V N #include <linux/module.h> 21df828598SMugunthan V N #include <linux/platform_device.h> 22df828598SMugunthan V N #include <linux/irqreturn.h> 23df828598SMugunthan V N #include <linux/interrupt.h> 24df828598SMugunthan V N #include <linux/if_ether.h> 25df828598SMugunthan V N #include <linux/etherdevice.h> 26df828598SMugunthan V N #include <linux/netdevice.h> 272e5b38abSRichard Cochran #include <linux/net_tstamp.h> 28df828598SMugunthan V N #include <linux/phy.h> 29df828598SMugunthan V N #include <linux/workqueue.h> 30df828598SMugunthan V N #include <linux/delay.h> 31f150bd7fSMugunthan V N #include <linux/pm_runtime.h> 321d147ccbSMugunthan V N #include <linux/gpio.h> 332eb32b0aSMugunthan V N #include <linux/of.h> 349e42f715SHeiko Schocher #include <linux/of_mdio.h> 352eb32b0aSMugunthan V N #include <linux/of_net.h> 362eb32b0aSMugunthan V N #include <linux/of_device.h> 373b72c2feSMugunthan V N #include <linux/if_vlan.h> 38df828598SMugunthan V N 39739683b4SMugunthan V N #include <linux/pinctrl/consumer.h> 40df828598SMugunthan V N 41dbe34724SMugunthan V N #include "cpsw.h" 42df828598SMugunthan V N #include "cpsw_ale.h" 432e5b38abSRichard Cochran #include "cpts.h" 44df828598SMugunthan V N #include "davinci_cpdma.h" 45df828598SMugunthan V N 46df828598SMugunthan V N #define CPSW_DEBUG (NETIF_MSG_HW | NETIF_MSG_WOL | \ 47df828598SMugunthan V N NETIF_MSG_DRV | NETIF_MSG_LINK | \ 48df828598SMugunthan V N NETIF_MSG_IFUP | NETIF_MSG_INTR | \ 49df828598SMugunthan V N NETIF_MSG_PROBE | NETIF_MSG_TIMER | \ 50df828598SMugunthan V N NETIF_MSG_IFDOWN | NETIF_MSG_RX_ERR | \ 51df828598SMugunthan V N NETIF_MSG_TX_ERR | NETIF_MSG_TX_DONE | \ 52df828598SMugunthan V N NETIF_MSG_PKTDATA | NETIF_MSG_TX_QUEUED | \ 53df828598SMugunthan V N NETIF_MSG_RX_STATUS) 54df828598SMugunthan V N 55df828598SMugunthan V N #define cpsw_info(priv, type, format, ...) \ 56df828598SMugunthan V N do { \ 57df828598SMugunthan V N if (netif_msg_##type(priv) && net_ratelimit()) \ 58df828598SMugunthan V N dev_info(priv->dev, format, ## __VA_ARGS__); \ 59df828598SMugunthan V N } while (0) 60df828598SMugunthan V N 61df828598SMugunthan V N #define cpsw_err(priv, type, format, ...) \ 62df828598SMugunthan V N do { \ 63df828598SMugunthan V N if (netif_msg_##type(priv) && net_ratelimit()) \ 64df828598SMugunthan V N dev_err(priv->dev, format, ## __VA_ARGS__); \ 65df828598SMugunthan V N } while (0) 66df828598SMugunthan V N 67df828598SMugunthan V N #define cpsw_dbg(priv, type, format, ...) \ 68df828598SMugunthan V N do { \ 69df828598SMugunthan V N if (netif_msg_##type(priv) && net_ratelimit()) \ 70df828598SMugunthan V N dev_dbg(priv->dev, format, ## __VA_ARGS__); \ 71df828598SMugunthan V N } while (0) 72df828598SMugunthan V N 73df828598SMugunthan V N #define cpsw_notice(priv, type, format, ...) \ 74df828598SMugunthan V N do { \ 75df828598SMugunthan V N if (netif_msg_##type(priv) && net_ratelimit()) \ 76df828598SMugunthan V N dev_notice(priv->dev, format, ## __VA_ARGS__); \ 77df828598SMugunthan V N } while (0) 78df828598SMugunthan V N 795c50a856SMugunthan V N #define ALE_ALL_PORTS 0x7 805c50a856SMugunthan V N 81df828598SMugunthan V N #define CPSW_MAJOR_VERSION(reg) (reg >> 8 & 0x7) 82df828598SMugunthan V N #define CPSW_MINOR_VERSION(reg) (reg & 0xff) 83df828598SMugunthan V N #define CPSW_RTL_VERSION(reg) ((reg >> 11) & 0x1f) 84df828598SMugunthan V N 85e90cfac6SRichard Cochran #define CPSW_VERSION_1 0x19010a 86e90cfac6SRichard Cochran #define CPSW_VERSION_2 0x19010c 87c193f365SMugunthan V N #define CPSW_VERSION_3 0x19010f 88926489beSMugunthan V N #define CPSW_VERSION_4 0x190112 89549985eeSRichard Cochran 90549985eeSRichard Cochran #define HOST_PORT_NUM 0 91549985eeSRichard Cochran #define SLIVER_SIZE 0x40 92549985eeSRichard Cochran 93549985eeSRichard Cochran #define CPSW1_HOST_PORT_OFFSET 0x028 94549985eeSRichard Cochran #define CPSW1_SLAVE_OFFSET 0x050 95549985eeSRichard Cochran #define CPSW1_SLAVE_SIZE 0x040 96549985eeSRichard Cochran #define CPSW1_CPDMA_OFFSET 0x100 97549985eeSRichard Cochran #define CPSW1_STATERAM_OFFSET 0x200 98d9718546SMugunthan V N #define CPSW1_HW_STATS 0x400 99549985eeSRichard Cochran #define CPSW1_CPTS_OFFSET 0x500 100549985eeSRichard Cochran #define CPSW1_ALE_OFFSET 0x600 101549985eeSRichard Cochran #define CPSW1_SLIVER_OFFSET 0x700 102549985eeSRichard Cochran 103549985eeSRichard Cochran #define CPSW2_HOST_PORT_OFFSET 0x108 104549985eeSRichard Cochran #define CPSW2_SLAVE_OFFSET 0x200 105549985eeSRichard Cochran #define CPSW2_SLAVE_SIZE 0x100 106549985eeSRichard Cochran #define CPSW2_CPDMA_OFFSET 0x800 107d9718546SMugunthan V N #define CPSW2_HW_STATS 0x900 108549985eeSRichard Cochran #define CPSW2_STATERAM_OFFSET 0xa00 109549985eeSRichard Cochran #define CPSW2_CPTS_OFFSET 0xc00 110549985eeSRichard Cochran #define CPSW2_ALE_OFFSET 0xd00 111549985eeSRichard Cochran #define CPSW2_SLIVER_OFFSET 0xd80 112549985eeSRichard Cochran #define CPSW2_BD_OFFSET 0x2000 113549985eeSRichard Cochran 114df828598SMugunthan V N #define CPDMA_RXTHRESH 0x0c0 115df828598SMugunthan V N #define CPDMA_RXFREE 0x0e0 116df828598SMugunthan V N #define CPDMA_TXHDP 0x00 117df828598SMugunthan V N #define CPDMA_RXHDP 0x20 118df828598SMugunthan V N #define CPDMA_TXCP 0x40 119df828598SMugunthan V N #define CPDMA_RXCP 0x60 120df828598SMugunthan V N 121df828598SMugunthan V N #define CPSW_POLL_WEIGHT 64 122df828598SMugunthan V N #define CPSW_MIN_PACKET_SIZE 60 123df828598SMugunthan V N #define CPSW_MAX_PACKET_SIZE (1500 + 14 + 4 + 4) 124df828598SMugunthan V N 125df828598SMugunthan V N #define RX_PRIORITY_MAPPING 0x76543210 126df828598SMugunthan V N #define TX_PRIORITY_MAPPING 0x33221100 127e05107e6SIvan Khoronzhuk #define CPDMA_TX_PRIORITY_MAP 0x01234567 128df828598SMugunthan V N 1293b72c2feSMugunthan V N #define CPSW_VLAN_AWARE BIT(1) 1303b72c2feSMugunthan V N #define CPSW_ALE_VLAN_AWARE 1 1313b72c2feSMugunthan V N 13235717d8dSJohn Ogness #define CPSW_FIFO_NORMAL_MODE (0 << 16) 13335717d8dSJohn Ogness #define CPSW_FIFO_DUAL_MAC_MODE (1 << 16) 13435717d8dSJohn Ogness #define CPSW_FIFO_RATE_LIMIT_MODE (2 << 16) 135d9ba8f9eSMugunthan V N 136ff5b8ef2SMugunthan V N #define CPSW_INTPACEEN (0x3f << 16) 137ff5b8ef2SMugunthan V N #define CPSW_INTPRESCALE_MASK (0x7FF << 0) 138ff5b8ef2SMugunthan V N #define CPSW_CMINTMAX_CNT 63 139ff5b8ef2SMugunthan V N #define CPSW_CMINTMIN_CNT 2 140ff5b8ef2SMugunthan V N #define CPSW_CMINTMAX_INTVL (1000 / CPSW_CMINTMIN_CNT) 141ff5b8ef2SMugunthan V N #define CPSW_CMINTMIN_INTVL ((1000 / CPSW_CMINTMAX_CNT) + 1) 142ff5b8ef2SMugunthan V N 143606f3993SIvan Khoronzhuk #define cpsw_slave_index(cpsw, priv) \ 144606f3993SIvan Khoronzhuk ((cpsw->data.dual_emac) ? priv->emac_port : \ 145606f3993SIvan Khoronzhuk cpsw->data.active_slave) 146e38b5a3dSIvan Khoronzhuk #define IRQ_NUM 2 147e05107e6SIvan Khoronzhuk #define CPSW_MAX_QUEUES 8 148d3bb9c58SMugunthan V N 149df828598SMugunthan V N static int debug_level; 150df828598SMugunthan V N module_param(debug_level, int, 0); 151df828598SMugunthan V N MODULE_PARM_DESC(debug_level, "cpsw debug level (NETIF_MSG bits)"); 152df828598SMugunthan V N 153df828598SMugunthan V N static int ale_ageout = 10; 154df828598SMugunthan V N module_param(ale_ageout, int, 0); 155df828598SMugunthan V N MODULE_PARM_DESC(ale_ageout, "cpsw ale ageout interval (seconds)"); 156df828598SMugunthan V N 157df828598SMugunthan V N static int rx_packet_max = CPSW_MAX_PACKET_SIZE; 158df828598SMugunthan V N module_param(rx_packet_max, int, 0); 159df828598SMugunthan V N MODULE_PARM_DESC(rx_packet_max, "maximum receive packet size (bytes)"); 160df828598SMugunthan V N 161996a5c27SRichard Cochran struct cpsw_wr_regs { 162df828598SMugunthan V N u32 id_ver; 163df828598SMugunthan V N u32 soft_reset; 164df828598SMugunthan V N u32 control; 165df828598SMugunthan V N u32 int_control; 166df828598SMugunthan V N u32 rx_thresh_en; 167df828598SMugunthan V N u32 rx_en; 168df828598SMugunthan V N u32 tx_en; 169df828598SMugunthan V N u32 misc_en; 170ff5b8ef2SMugunthan V N u32 mem_allign1[8]; 171ff5b8ef2SMugunthan V N u32 rx_thresh_stat; 172ff5b8ef2SMugunthan V N u32 rx_stat; 173ff5b8ef2SMugunthan V N u32 tx_stat; 174ff5b8ef2SMugunthan V N u32 misc_stat; 175ff5b8ef2SMugunthan V N u32 mem_allign2[8]; 176ff5b8ef2SMugunthan V N u32 rx_imax; 177ff5b8ef2SMugunthan V N u32 tx_imax; 178ff5b8ef2SMugunthan V N 179df828598SMugunthan V N }; 180df828598SMugunthan V N 181996a5c27SRichard Cochran struct cpsw_ss_regs { 182df828598SMugunthan V N u32 id_ver; 183df828598SMugunthan V N u32 control; 184df828598SMugunthan V N u32 soft_reset; 185df828598SMugunthan V N u32 stat_port_en; 186df828598SMugunthan V N u32 ptype; 187bd357af2SRichard Cochran u32 soft_idle; 188bd357af2SRichard Cochran u32 thru_rate; 189bd357af2SRichard Cochran u32 gap_thresh; 190bd357af2SRichard Cochran u32 tx_start_wds; 191bd357af2SRichard Cochran u32 flow_control; 192bd357af2SRichard Cochran u32 vlan_ltype; 193bd357af2SRichard Cochran u32 ts_ltype; 194bd357af2SRichard Cochran u32 dlr_ltype; 195df828598SMugunthan V N }; 196df828598SMugunthan V N 1979750a3adSRichard Cochran /* CPSW_PORT_V1 */ 1989750a3adSRichard Cochran #define CPSW1_MAX_BLKS 0x00 /* Maximum FIFO Blocks */ 1999750a3adSRichard Cochran #define CPSW1_BLK_CNT 0x04 /* FIFO Block Usage Count (Read Only) */ 2009750a3adSRichard Cochran #define CPSW1_TX_IN_CTL 0x08 /* Transmit FIFO Control */ 2019750a3adSRichard Cochran #define CPSW1_PORT_VLAN 0x0c /* VLAN Register */ 2029750a3adSRichard Cochran #define CPSW1_TX_PRI_MAP 0x10 /* Tx Header Priority to Switch Pri Mapping */ 2039750a3adSRichard Cochran #define CPSW1_TS_CTL 0x14 /* Time Sync Control */ 2049750a3adSRichard Cochran #define CPSW1_TS_SEQ_LTYPE 0x18 /* Time Sync Sequence ID Offset and Msg Type */ 2059750a3adSRichard Cochran #define CPSW1_TS_VLAN 0x1c /* Time Sync VLAN1 and VLAN2 */ 2069750a3adSRichard Cochran 2079750a3adSRichard Cochran /* CPSW_PORT_V2 */ 2089750a3adSRichard Cochran #define CPSW2_CONTROL 0x00 /* Control Register */ 2099750a3adSRichard Cochran #define CPSW2_MAX_BLKS 0x08 /* Maximum FIFO Blocks */ 2109750a3adSRichard Cochran #define CPSW2_BLK_CNT 0x0c /* FIFO Block Usage Count (Read Only) */ 2119750a3adSRichard Cochran #define CPSW2_TX_IN_CTL 0x10 /* Transmit FIFO Control */ 2129750a3adSRichard Cochran #define CPSW2_PORT_VLAN 0x14 /* VLAN Register */ 2139750a3adSRichard Cochran #define CPSW2_TX_PRI_MAP 0x18 /* Tx Header Priority to Switch Pri Mapping */ 2149750a3adSRichard Cochran #define CPSW2_TS_SEQ_MTYPE 0x1c /* Time Sync Sequence ID Offset and Msg Type */ 2159750a3adSRichard Cochran 2169750a3adSRichard Cochran /* CPSW_PORT_V1 and V2 */ 2179750a3adSRichard Cochran #define SA_LO 0x20 /* CPGMAC_SL Source Address Low */ 2189750a3adSRichard Cochran #define SA_HI 0x24 /* CPGMAC_SL Source Address High */ 2199750a3adSRichard Cochran #define SEND_PERCENT 0x28 /* Transmit Queue Send Percentages */ 2209750a3adSRichard Cochran 2219750a3adSRichard Cochran /* CPSW_PORT_V2 only */ 2229750a3adSRichard Cochran #define RX_DSCP_PRI_MAP0 0x30 /* Rx DSCP Priority to Rx Packet Mapping */ 2239750a3adSRichard Cochran #define RX_DSCP_PRI_MAP1 0x34 /* Rx DSCP Priority to Rx Packet Mapping */ 2249750a3adSRichard Cochran #define RX_DSCP_PRI_MAP2 0x38 /* Rx DSCP Priority to Rx Packet Mapping */ 2259750a3adSRichard Cochran #define RX_DSCP_PRI_MAP3 0x3c /* Rx DSCP Priority to Rx Packet Mapping */ 2269750a3adSRichard Cochran #define RX_DSCP_PRI_MAP4 0x40 /* Rx DSCP Priority to Rx Packet Mapping */ 2279750a3adSRichard Cochran #define RX_DSCP_PRI_MAP5 0x44 /* Rx DSCP Priority to Rx Packet Mapping */ 2289750a3adSRichard Cochran #define RX_DSCP_PRI_MAP6 0x48 /* Rx DSCP Priority to Rx Packet Mapping */ 2299750a3adSRichard Cochran #define RX_DSCP_PRI_MAP7 0x4c /* Rx DSCP Priority to Rx Packet Mapping */ 2309750a3adSRichard Cochran 2319750a3adSRichard Cochran /* Bit definitions for the CPSW2_CONTROL register */ 2329750a3adSRichard Cochran #define PASS_PRI_TAGGED (1<<24) /* Pass Priority Tagged */ 2339750a3adSRichard Cochran #define VLAN_LTYPE2_EN (1<<21) /* VLAN LTYPE 2 enable */ 2349750a3adSRichard Cochran #define VLAN_LTYPE1_EN (1<<20) /* VLAN LTYPE 1 enable */ 2359750a3adSRichard Cochran #define DSCP_PRI_EN (1<<16) /* DSCP Priority Enable */ 2369750a3adSRichard Cochran #define TS_320 (1<<14) /* Time Sync Dest Port 320 enable */ 2379750a3adSRichard Cochran #define TS_319 (1<<13) /* Time Sync Dest Port 319 enable */ 2389750a3adSRichard Cochran #define TS_132 (1<<12) /* Time Sync Dest IP Addr 132 enable */ 2399750a3adSRichard Cochran #define TS_131 (1<<11) /* Time Sync Dest IP Addr 131 enable */ 2409750a3adSRichard Cochran #define TS_130 (1<<10) /* Time Sync Dest IP Addr 130 enable */ 2419750a3adSRichard Cochran #define TS_129 (1<<9) /* Time Sync Dest IP Addr 129 enable */ 24209c55372SGeorge Cherian #define TS_TTL_NONZERO (1<<8) /* Time Sync Time To Live Non-zero enable */ 24309c55372SGeorge Cherian #define TS_ANNEX_F_EN (1<<6) /* Time Sync Annex F enable */ 2449750a3adSRichard Cochran #define TS_ANNEX_D_EN (1<<4) /* Time Sync Annex D enable */ 2459750a3adSRichard Cochran #define TS_LTYPE2_EN (1<<3) /* Time Sync LTYPE 2 enable */ 2469750a3adSRichard Cochran #define TS_LTYPE1_EN (1<<2) /* Time Sync LTYPE 1 enable */ 2479750a3adSRichard Cochran #define TS_TX_EN (1<<1) /* Time Sync Transmit Enable */ 2489750a3adSRichard Cochran #define TS_RX_EN (1<<0) /* Time Sync Receive Enable */ 2499750a3adSRichard Cochran 25009c55372SGeorge Cherian #define CTRL_V2_TS_BITS \ 25109c55372SGeorge Cherian (TS_320 | TS_319 | TS_132 | TS_131 | TS_130 | TS_129 |\ 25209c55372SGeorge Cherian TS_TTL_NONZERO | TS_ANNEX_D_EN | TS_LTYPE1_EN) 2539750a3adSRichard Cochran 25409c55372SGeorge Cherian #define CTRL_V2_ALL_TS_MASK (CTRL_V2_TS_BITS | TS_TX_EN | TS_RX_EN) 25509c55372SGeorge Cherian #define CTRL_V2_TX_TS_BITS (CTRL_V2_TS_BITS | TS_TX_EN) 25609c55372SGeorge Cherian #define CTRL_V2_RX_TS_BITS (CTRL_V2_TS_BITS | TS_RX_EN) 25709c55372SGeorge Cherian 25809c55372SGeorge Cherian 25909c55372SGeorge Cherian #define CTRL_V3_TS_BITS \ 26009c55372SGeorge Cherian (TS_320 | TS_319 | TS_132 | TS_131 | TS_130 | TS_129 |\ 26109c55372SGeorge Cherian TS_TTL_NONZERO | TS_ANNEX_F_EN | TS_ANNEX_D_EN |\ 26209c55372SGeorge Cherian TS_LTYPE1_EN) 26309c55372SGeorge Cherian 26409c55372SGeorge Cherian #define CTRL_V3_ALL_TS_MASK (CTRL_V3_TS_BITS | TS_TX_EN | TS_RX_EN) 26509c55372SGeorge Cherian #define CTRL_V3_TX_TS_BITS (CTRL_V3_TS_BITS | TS_TX_EN) 26609c55372SGeorge Cherian #define CTRL_V3_RX_TS_BITS (CTRL_V3_TS_BITS | TS_RX_EN) 2679750a3adSRichard Cochran 2689750a3adSRichard Cochran /* Bit definitions for the CPSW2_TS_SEQ_MTYPE register */ 2699750a3adSRichard Cochran #define TS_SEQ_ID_OFFSET_SHIFT (16) /* Time Sync Sequence ID Offset */ 2709750a3adSRichard Cochran #define TS_SEQ_ID_OFFSET_MASK (0x3f) 2719750a3adSRichard Cochran #define TS_MSG_TYPE_EN_SHIFT (0) /* Time Sync Message Type Enable */ 2729750a3adSRichard Cochran #define TS_MSG_TYPE_EN_MASK (0xffff) 2739750a3adSRichard Cochran 2749750a3adSRichard Cochran /* The PTP event messages - Sync, Delay_Req, Pdelay_Req, and Pdelay_Resp. */ 2759750a3adSRichard Cochran #define EVENT_MSG_BITS ((1<<0) | (1<<1) | (1<<2) | (1<<3)) 276df828598SMugunthan V N 2772e5b38abSRichard Cochran /* Bit definitions for the CPSW1_TS_CTL register */ 2782e5b38abSRichard Cochran #define CPSW_V1_TS_RX_EN BIT(0) 2792e5b38abSRichard Cochran #define CPSW_V1_TS_TX_EN BIT(4) 2802e5b38abSRichard Cochran #define CPSW_V1_MSG_TYPE_OFS 16 2812e5b38abSRichard Cochran 2822e5b38abSRichard Cochran /* Bit definitions for the CPSW1_TS_SEQ_LTYPE register */ 2832e5b38abSRichard Cochran #define CPSW_V1_SEQ_ID_OFS_SHIFT 16 2842e5b38abSRichard Cochran 285df828598SMugunthan V N struct cpsw_host_regs { 286df828598SMugunthan V N u32 max_blks; 287df828598SMugunthan V N u32 blk_cnt; 288d9ba8f9eSMugunthan V N u32 tx_in_ctl; 289df828598SMugunthan V N u32 port_vlan; 290df828598SMugunthan V N u32 tx_pri_map; 291df828598SMugunthan V N u32 cpdma_tx_pri_map; 292df828598SMugunthan V N u32 cpdma_rx_chan_map; 293df828598SMugunthan V N }; 294df828598SMugunthan V N 295df828598SMugunthan V N struct cpsw_sliver_regs { 296df828598SMugunthan V N u32 id_ver; 297df828598SMugunthan V N u32 mac_control; 298df828598SMugunthan V N u32 mac_status; 299df828598SMugunthan V N u32 soft_reset; 300df828598SMugunthan V N u32 rx_maxlen; 301df828598SMugunthan V N u32 __reserved_0; 302df828598SMugunthan V N u32 rx_pause; 303df828598SMugunthan V N u32 tx_pause; 304df828598SMugunthan V N u32 __reserved_1; 305df828598SMugunthan V N u32 rx_pri_map; 306df828598SMugunthan V N }; 307df828598SMugunthan V N 308d9718546SMugunthan V N struct cpsw_hw_stats { 309d9718546SMugunthan V N u32 rxgoodframes; 310d9718546SMugunthan V N u32 rxbroadcastframes; 311d9718546SMugunthan V N u32 rxmulticastframes; 312d9718546SMugunthan V N u32 rxpauseframes; 313d9718546SMugunthan V N u32 rxcrcerrors; 314d9718546SMugunthan V N u32 rxaligncodeerrors; 315d9718546SMugunthan V N u32 rxoversizedframes; 316d9718546SMugunthan V N u32 rxjabberframes; 317d9718546SMugunthan V N u32 rxundersizedframes; 318d9718546SMugunthan V N u32 rxfragments; 319d9718546SMugunthan V N u32 __pad_0[2]; 320d9718546SMugunthan V N u32 rxoctets; 321d9718546SMugunthan V N u32 txgoodframes; 322d9718546SMugunthan V N u32 txbroadcastframes; 323d9718546SMugunthan V N u32 txmulticastframes; 324d9718546SMugunthan V N u32 txpauseframes; 325d9718546SMugunthan V N u32 txdeferredframes; 326d9718546SMugunthan V N u32 txcollisionframes; 327d9718546SMugunthan V N u32 txsinglecollframes; 328d9718546SMugunthan V N u32 txmultcollframes; 329d9718546SMugunthan V N u32 txexcessivecollisions; 330d9718546SMugunthan V N u32 txlatecollisions; 331d9718546SMugunthan V N u32 txunderrun; 332d9718546SMugunthan V N u32 txcarriersenseerrors; 333d9718546SMugunthan V N u32 txoctets; 334d9718546SMugunthan V N u32 octetframes64; 335d9718546SMugunthan V N u32 octetframes65t127; 336d9718546SMugunthan V N u32 octetframes128t255; 337d9718546SMugunthan V N u32 octetframes256t511; 338d9718546SMugunthan V N u32 octetframes512t1023; 339d9718546SMugunthan V N u32 octetframes1024tup; 340d9718546SMugunthan V N u32 netoctets; 341d9718546SMugunthan V N u32 rxsofoverruns; 342d9718546SMugunthan V N u32 rxmofoverruns; 343d9718546SMugunthan V N u32 rxdmaoverruns; 344d9718546SMugunthan V N }; 345d9718546SMugunthan V N 346df828598SMugunthan V N struct cpsw_slave { 3479750a3adSRichard Cochran void __iomem *regs; 348df828598SMugunthan V N struct cpsw_sliver_regs __iomem *sliver; 349df828598SMugunthan V N int slave_num; 350df828598SMugunthan V N u32 mac_control; 351df828598SMugunthan V N struct cpsw_slave_data *data; 352df828598SMugunthan V N struct phy_device *phy; 353d9ba8f9eSMugunthan V N struct net_device *ndev; 354d9ba8f9eSMugunthan V N u32 port_vlan; 355d9ba8f9eSMugunthan V N u32 open_stat; 356df828598SMugunthan V N }; 357df828598SMugunthan V N 3589750a3adSRichard Cochran static inline u32 slave_read(struct cpsw_slave *slave, u32 offset) 3599750a3adSRichard Cochran { 3609750a3adSRichard Cochran return __raw_readl(slave->regs + offset); 3619750a3adSRichard Cochran } 3629750a3adSRichard Cochran 3639750a3adSRichard Cochran static inline void slave_write(struct cpsw_slave *slave, u32 val, u32 offset) 3649750a3adSRichard Cochran { 3659750a3adSRichard Cochran __raw_writel(val, slave->regs + offset); 3669750a3adSRichard Cochran } 3679750a3adSRichard Cochran 368649a1688SIvan Khoronzhuk struct cpsw_common { 36956e31bd8SIvan Khoronzhuk struct device *dev; 370606f3993SIvan Khoronzhuk struct cpsw_platform_data data; 371dbc4ec52SIvan Khoronzhuk struct napi_struct napi_rx; 372dbc4ec52SIvan Khoronzhuk struct napi_struct napi_tx; 3735d8d0d4dSIvan Khoronzhuk struct cpsw_ss_regs __iomem *regs; 3745d8d0d4dSIvan Khoronzhuk struct cpsw_wr_regs __iomem *wr_regs; 3755d8d0d4dSIvan Khoronzhuk u8 __iomem *hw_stats; 3765d8d0d4dSIvan Khoronzhuk struct cpsw_host_regs __iomem *host_port_regs; 3772a05a622SIvan Khoronzhuk u32 version; 3782a05a622SIvan Khoronzhuk u32 coal_intvl; 3792a05a622SIvan Khoronzhuk u32 bus_freq_mhz; 3802a05a622SIvan Khoronzhuk int rx_packet_max; 381606f3993SIvan Khoronzhuk struct cpsw_slave *slaves; 3822c836bd9SIvan Khoronzhuk struct cpdma_ctlr *dma; 383e05107e6SIvan Khoronzhuk struct cpdma_chan *txch[CPSW_MAX_QUEUES]; 384e05107e6SIvan Khoronzhuk struct cpdma_chan *rxch[CPSW_MAX_QUEUES]; 3852a05a622SIvan Khoronzhuk struct cpsw_ale *ale; 386e38b5a3dSIvan Khoronzhuk bool quirk_irq; 387e38b5a3dSIvan Khoronzhuk bool rx_irq_disabled; 388e38b5a3dSIvan Khoronzhuk bool tx_irq_disabled; 389e38b5a3dSIvan Khoronzhuk u32 irqs_table[IRQ_NUM]; 3902a05a622SIvan Khoronzhuk struct cpts *cpts; 391e05107e6SIvan Khoronzhuk int rx_ch_num, tx_ch_num; 392649a1688SIvan Khoronzhuk }; 393649a1688SIvan Khoronzhuk 394649a1688SIvan Khoronzhuk struct cpsw_priv { 395df828598SMugunthan V N struct net_device *ndev; 396df828598SMugunthan V N struct device *dev; 397df828598SMugunthan V N u32 msg_enable; 398df828598SMugunthan V N u8 mac_addr[ETH_ALEN]; 3991923d6e4SMugunthan V N bool rx_pause; 4001923d6e4SMugunthan V N bool tx_pause; 401d9ba8f9eSMugunthan V N u32 emac_port; 402649a1688SIvan Khoronzhuk struct cpsw_common *cpsw; 403df828598SMugunthan V N }; 404df828598SMugunthan V N 405d9718546SMugunthan V N struct cpsw_stats { 406d9718546SMugunthan V N char stat_string[ETH_GSTRING_LEN]; 407d9718546SMugunthan V N int type; 408d9718546SMugunthan V N int sizeof_stat; 409d9718546SMugunthan V N int stat_offset; 410d9718546SMugunthan V N }; 411d9718546SMugunthan V N 412d9718546SMugunthan V N enum { 413d9718546SMugunthan V N CPSW_STATS, 414d9718546SMugunthan V N CPDMA_RX_STATS, 415d9718546SMugunthan V N CPDMA_TX_STATS, 416d9718546SMugunthan V N }; 417d9718546SMugunthan V N 418d9718546SMugunthan V N #define CPSW_STAT(m) CPSW_STATS, \ 419d9718546SMugunthan V N sizeof(((struct cpsw_hw_stats *)0)->m), \ 420d9718546SMugunthan V N offsetof(struct cpsw_hw_stats, m) 421d9718546SMugunthan V N #define CPDMA_RX_STAT(m) CPDMA_RX_STATS, \ 422d9718546SMugunthan V N sizeof(((struct cpdma_chan_stats *)0)->m), \ 423d9718546SMugunthan V N offsetof(struct cpdma_chan_stats, m) 424d9718546SMugunthan V N #define CPDMA_TX_STAT(m) CPDMA_TX_STATS, \ 425d9718546SMugunthan V N sizeof(((struct cpdma_chan_stats *)0)->m), \ 426d9718546SMugunthan V N offsetof(struct cpdma_chan_stats, m) 427d9718546SMugunthan V N 428d9718546SMugunthan V N static const struct cpsw_stats cpsw_gstrings_stats[] = { 429d9718546SMugunthan V N { "Good Rx Frames", CPSW_STAT(rxgoodframes) }, 430d9718546SMugunthan V N { "Broadcast Rx Frames", CPSW_STAT(rxbroadcastframes) }, 431d9718546SMugunthan V N { "Multicast Rx Frames", CPSW_STAT(rxmulticastframes) }, 432d9718546SMugunthan V N { "Pause Rx Frames", CPSW_STAT(rxpauseframes) }, 433d9718546SMugunthan V N { "Rx CRC Errors", CPSW_STAT(rxcrcerrors) }, 434d9718546SMugunthan V N { "Rx Align/Code Errors", CPSW_STAT(rxaligncodeerrors) }, 435d9718546SMugunthan V N { "Oversize Rx Frames", CPSW_STAT(rxoversizedframes) }, 436d9718546SMugunthan V N { "Rx Jabbers", CPSW_STAT(rxjabberframes) }, 437d9718546SMugunthan V N { "Undersize (Short) Rx Frames", CPSW_STAT(rxundersizedframes) }, 438d9718546SMugunthan V N { "Rx Fragments", CPSW_STAT(rxfragments) }, 439d9718546SMugunthan V N { "Rx Octets", CPSW_STAT(rxoctets) }, 440d9718546SMugunthan V N { "Good Tx Frames", CPSW_STAT(txgoodframes) }, 441d9718546SMugunthan V N { "Broadcast Tx Frames", CPSW_STAT(txbroadcastframes) }, 442d9718546SMugunthan V N { "Multicast Tx Frames", CPSW_STAT(txmulticastframes) }, 443d9718546SMugunthan V N { "Pause Tx Frames", CPSW_STAT(txpauseframes) }, 444d9718546SMugunthan V N { "Deferred Tx Frames", CPSW_STAT(txdeferredframes) }, 445d9718546SMugunthan V N { "Collisions", CPSW_STAT(txcollisionframes) }, 446d9718546SMugunthan V N { "Single Collision Tx Frames", CPSW_STAT(txsinglecollframes) }, 447d9718546SMugunthan V N { "Multiple Collision Tx Frames", CPSW_STAT(txmultcollframes) }, 448d9718546SMugunthan V N { "Excessive Collisions", CPSW_STAT(txexcessivecollisions) }, 449d9718546SMugunthan V N { "Late Collisions", CPSW_STAT(txlatecollisions) }, 450d9718546SMugunthan V N { "Tx Underrun", CPSW_STAT(txunderrun) }, 451d9718546SMugunthan V N { "Carrier Sense Errors", CPSW_STAT(txcarriersenseerrors) }, 452d9718546SMugunthan V N { "Tx Octets", CPSW_STAT(txoctets) }, 453d9718546SMugunthan V N { "Rx + Tx 64 Octet Frames", CPSW_STAT(octetframes64) }, 454d9718546SMugunthan V N { "Rx + Tx 65-127 Octet Frames", CPSW_STAT(octetframes65t127) }, 455d9718546SMugunthan V N { "Rx + Tx 128-255 Octet Frames", CPSW_STAT(octetframes128t255) }, 456d9718546SMugunthan V N { "Rx + Tx 256-511 Octet Frames", CPSW_STAT(octetframes256t511) }, 457d9718546SMugunthan V N { "Rx + Tx 512-1023 Octet Frames", CPSW_STAT(octetframes512t1023) }, 458d9718546SMugunthan V N { "Rx + Tx 1024-Up Octet Frames", CPSW_STAT(octetframes1024tup) }, 459d9718546SMugunthan V N { "Net Octets", CPSW_STAT(netoctets) }, 460d9718546SMugunthan V N { "Rx Start of Frame Overruns", CPSW_STAT(rxsofoverruns) }, 461d9718546SMugunthan V N { "Rx Middle of Frame Overruns", CPSW_STAT(rxmofoverruns) }, 462d9718546SMugunthan V N { "Rx DMA Overruns", CPSW_STAT(rxdmaoverruns) }, 463d9718546SMugunthan V N }; 464d9718546SMugunthan V N 465e05107e6SIvan Khoronzhuk static const struct cpsw_stats cpsw_gstrings_ch_stats[] = { 466e05107e6SIvan Khoronzhuk { "head_enqueue", CPDMA_RX_STAT(head_enqueue) }, 467e05107e6SIvan Khoronzhuk { "tail_enqueue", CPDMA_RX_STAT(tail_enqueue) }, 468e05107e6SIvan Khoronzhuk { "pad_enqueue", CPDMA_RX_STAT(pad_enqueue) }, 469e05107e6SIvan Khoronzhuk { "misqueued", CPDMA_RX_STAT(misqueued) }, 470e05107e6SIvan Khoronzhuk { "desc_alloc_fail", CPDMA_RX_STAT(desc_alloc_fail) }, 471e05107e6SIvan Khoronzhuk { "pad_alloc_fail", CPDMA_RX_STAT(pad_alloc_fail) }, 472e05107e6SIvan Khoronzhuk { "runt_receive_buf", CPDMA_RX_STAT(runt_receive_buff) }, 473e05107e6SIvan Khoronzhuk { "runt_transmit_buf", CPDMA_RX_STAT(runt_transmit_buff) }, 474e05107e6SIvan Khoronzhuk { "empty_dequeue", CPDMA_RX_STAT(empty_dequeue) }, 475e05107e6SIvan Khoronzhuk { "busy_dequeue", CPDMA_RX_STAT(busy_dequeue) }, 476e05107e6SIvan Khoronzhuk { "good_dequeue", CPDMA_RX_STAT(good_dequeue) }, 477e05107e6SIvan Khoronzhuk { "requeue", CPDMA_RX_STAT(requeue) }, 478e05107e6SIvan Khoronzhuk { "teardown_dequeue", CPDMA_RX_STAT(teardown_dequeue) }, 479e05107e6SIvan Khoronzhuk }; 480e05107e6SIvan Khoronzhuk 481e05107e6SIvan Khoronzhuk #define CPSW_STATS_COMMON_LEN ARRAY_SIZE(cpsw_gstrings_stats) 482e05107e6SIvan Khoronzhuk #define CPSW_STATS_CH_LEN ARRAY_SIZE(cpsw_gstrings_ch_stats) 483d9718546SMugunthan V N 484649a1688SIvan Khoronzhuk #define ndev_to_cpsw(ndev) (((struct cpsw_priv *)netdev_priv(ndev))->cpsw) 485dbc4ec52SIvan Khoronzhuk #define napi_to_cpsw(napi) container_of(napi, struct cpsw_common, napi) 486df828598SMugunthan V N #define for_each_slave(priv, func, arg...) \ 487df828598SMugunthan V N do { \ 4886e6ceaedSSebastian Siewior struct cpsw_slave *slave; \ 489606f3993SIvan Khoronzhuk struct cpsw_common *cpsw = (priv)->cpsw; \ 4906e6ceaedSSebastian Siewior int n; \ 491606f3993SIvan Khoronzhuk if (cpsw->data.dual_emac) \ 492606f3993SIvan Khoronzhuk (func)((cpsw)->slaves + priv->emac_port, ##arg);\ 493d9ba8f9eSMugunthan V N else \ 494606f3993SIvan Khoronzhuk for (n = cpsw->data.slaves, \ 495606f3993SIvan Khoronzhuk slave = cpsw->slaves; \ 4966e6ceaedSSebastian Siewior n; n--) \ 4976e6ceaedSSebastian Siewior (func)(slave++, ##arg); \ 498df828598SMugunthan V N } while (0) 499d9ba8f9eSMugunthan V N 5002a05a622SIvan Khoronzhuk #define cpsw_dual_emac_src_port_detect(cpsw, status, ndev, skb) \ 501d9ba8f9eSMugunthan V N do { \ 502606f3993SIvan Khoronzhuk if (!cpsw->data.dual_emac) \ 503d9ba8f9eSMugunthan V N break; \ 504d9ba8f9eSMugunthan V N if (CPDMA_RX_SOURCE_PORT(status) == 1) { \ 505606f3993SIvan Khoronzhuk ndev = cpsw->slaves[0].ndev; \ 506d9ba8f9eSMugunthan V N skb->dev = ndev; \ 507d9ba8f9eSMugunthan V N } else if (CPDMA_RX_SOURCE_PORT(status) == 2) { \ 508606f3993SIvan Khoronzhuk ndev = cpsw->slaves[1].ndev; \ 509d9ba8f9eSMugunthan V N skb->dev = ndev; \ 510d9ba8f9eSMugunthan V N } \ 511d9ba8f9eSMugunthan V N } while (0) 512606f3993SIvan Khoronzhuk #define cpsw_add_mcast(cpsw, priv, addr) \ 513d9ba8f9eSMugunthan V N do { \ 514606f3993SIvan Khoronzhuk if (cpsw->data.dual_emac) { \ 515606f3993SIvan Khoronzhuk struct cpsw_slave *slave = cpsw->slaves + \ 516d9ba8f9eSMugunthan V N priv->emac_port; \ 5176f1f5836SIvan Khoronzhuk int slave_port = cpsw_get_slave_port( \ 518d9ba8f9eSMugunthan V N slave->slave_num); \ 5192a05a622SIvan Khoronzhuk cpsw_ale_add_mcast(cpsw->ale, addr, \ 52071a2cbb7SGrygorii Strashko 1 << slave_port | ALE_PORT_HOST, \ 521d9ba8f9eSMugunthan V N ALE_VLAN, slave->port_vlan, 0); \ 522d9ba8f9eSMugunthan V N } else { \ 5232a05a622SIvan Khoronzhuk cpsw_ale_add_mcast(cpsw->ale, addr, \ 52461f1cef9SGrygorii Strashko ALE_ALL_PORTS, \ 525d9ba8f9eSMugunthan V N 0, 0, 0); \ 526d9ba8f9eSMugunthan V N } \ 527d9ba8f9eSMugunthan V N } while (0) 528d9ba8f9eSMugunthan V N 5296f1f5836SIvan Khoronzhuk static inline int cpsw_get_slave_port(u32 slave_num) 530d9ba8f9eSMugunthan V N { 531d9ba8f9eSMugunthan V N return slave_num + 1; 532d9ba8f9eSMugunthan V N } 533df828598SMugunthan V N 5340cd8f9ccSMugunthan V N static void cpsw_set_promiscious(struct net_device *ndev, bool enable) 5350cd8f9ccSMugunthan V N { 5362a05a622SIvan Khoronzhuk struct cpsw_common *cpsw = ndev_to_cpsw(ndev); 5372a05a622SIvan Khoronzhuk struct cpsw_ale *ale = cpsw->ale; 5380cd8f9ccSMugunthan V N int i; 5390cd8f9ccSMugunthan V N 540606f3993SIvan Khoronzhuk if (cpsw->data.dual_emac) { 5410cd8f9ccSMugunthan V N bool flag = false; 5420cd8f9ccSMugunthan V N 5430cd8f9ccSMugunthan V N /* Enabling promiscuous mode for one interface will be 5440cd8f9ccSMugunthan V N * common for both the interface as the interface shares 5450cd8f9ccSMugunthan V N * the same hardware resource. 5460cd8f9ccSMugunthan V N */ 547606f3993SIvan Khoronzhuk for (i = 0; i < cpsw->data.slaves; i++) 548606f3993SIvan Khoronzhuk if (cpsw->slaves[i].ndev->flags & IFF_PROMISC) 5490cd8f9ccSMugunthan V N flag = true; 5500cd8f9ccSMugunthan V N 5510cd8f9ccSMugunthan V N if (!enable && flag) { 5520cd8f9ccSMugunthan V N enable = true; 5530cd8f9ccSMugunthan V N dev_err(&ndev->dev, "promiscuity not disabled as the other interface is still in promiscuity mode\n"); 5540cd8f9ccSMugunthan V N } 5550cd8f9ccSMugunthan V N 5560cd8f9ccSMugunthan V N if (enable) { 5570cd8f9ccSMugunthan V N /* Enable Bypass */ 5580cd8f9ccSMugunthan V N cpsw_ale_control_set(ale, 0, ALE_BYPASS, 1); 5590cd8f9ccSMugunthan V N 5600cd8f9ccSMugunthan V N dev_dbg(&ndev->dev, "promiscuity enabled\n"); 5610cd8f9ccSMugunthan V N } else { 5620cd8f9ccSMugunthan V N /* Disable Bypass */ 5630cd8f9ccSMugunthan V N cpsw_ale_control_set(ale, 0, ALE_BYPASS, 0); 5640cd8f9ccSMugunthan V N dev_dbg(&ndev->dev, "promiscuity disabled\n"); 5650cd8f9ccSMugunthan V N } 5660cd8f9ccSMugunthan V N } else { 5670cd8f9ccSMugunthan V N if (enable) { 5680cd8f9ccSMugunthan V N unsigned long timeout = jiffies + HZ; 5690cd8f9ccSMugunthan V N 5706f979eb3SLennart Sorensen /* Disable Learn for all ports (host is port 0 and slaves are port 1 and up */ 571606f3993SIvan Khoronzhuk for (i = 0; i <= cpsw->data.slaves; i++) { 5720cd8f9ccSMugunthan V N cpsw_ale_control_set(ale, i, 5730cd8f9ccSMugunthan V N ALE_PORT_NOLEARN, 1); 5740cd8f9ccSMugunthan V N cpsw_ale_control_set(ale, i, 5750cd8f9ccSMugunthan V N ALE_PORT_NO_SA_UPDATE, 1); 5760cd8f9ccSMugunthan V N } 5770cd8f9ccSMugunthan V N 5780cd8f9ccSMugunthan V N /* Clear All Untouched entries */ 5790cd8f9ccSMugunthan V N cpsw_ale_control_set(ale, 0, ALE_AGEOUT, 1); 5800cd8f9ccSMugunthan V N do { 5810cd8f9ccSMugunthan V N cpu_relax(); 5820cd8f9ccSMugunthan V N if (cpsw_ale_control_get(ale, 0, ALE_AGEOUT)) 5830cd8f9ccSMugunthan V N break; 5840cd8f9ccSMugunthan V N } while (time_after(timeout, jiffies)); 5850cd8f9ccSMugunthan V N cpsw_ale_control_set(ale, 0, ALE_AGEOUT, 1); 5860cd8f9ccSMugunthan V N 5870cd8f9ccSMugunthan V N /* Clear all mcast from ALE */ 58861f1cef9SGrygorii Strashko cpsw_ale_flush_multicast(ale, ALE_ALL_PORTS, -1); 5890cd8f9ccSMugunthan V N 5900cd8f9ccSMugunthan V N /* Flood All Unicast Packets to Host port */ 5910cd8f9ccSMugunthan V N cpsw_ale_control_set(ale, 0, ALE_P0_UNI_FLOOD, 1); 5920cd8f9ccSMugunthan V N dev_dbg(&ndev->dev, "promiscuity enabled\n"); 5930cd8f9ccSMugunthan V N } else { 5946f979eb3SLennart Sorensen /* Don't Flood All Unicast Packets to Host port */ 5950cd8f9ccSMugunthan V N cpsw_ale_control_set(ale, 0, ALE_P0_UNI_FLOOD, 0); 5960cd8f9ccSMugunthan V N 5976f979eb3SLennart Sorensen /* Enable Learn for all ports (host is port 0 and slaves are port 1 and up */ 598606f3993SIvan Khoronzhuk for (i = 0; i <= cpsw->data.slaves; i++) { 5990cd8f9ccSMugunthan V N cpsw_ale_control_set(ale, i, 6000cd8f9ccSMugunthan V N ALE_PORT_NOLEARN, 0); 6010cd8f9ccSMugunthan V N cpsw_ale_control_set(ale, i, 6020cd8f9ccSMugunthan V N ALE_PORT_NO_SA_UPDATE, 0); 6030cd8f9ccSMugunthan V N } 6040cd8f9ccSMugunthan V N dev_dbg(&ndev->dev, "promiscuity disabled\n"); 6050cd8f9ccSMugunthan V N } 6060cd8f9ccSMugunthan V N } 6070cd8f9ccSMugunthan V N } 6080cd8f9ccSMugunthan V N 6095c50a856SMugunthan V N static void cpsw_ndo_set_rx_mode(struct net_device *ndev) 6105c50a856SMugunthan V N { 6115c50a856SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 612606f3993SIvan Khoronzhuk struct cpsw_common *cpsw = priv->cpsw; 61325906052SMugunthan V N int vid; 61425906052SMugunthan V N 615606f3993SIvan Khoronzhuk if (cpsw->data.dual_emac) 616606f3993SIvan Khoronzhuk vid = cpsw->slaves[priv->emac_port].port_vlan; 61725906052SMugunthan V N else 618606f3993SIvan Khoronzhuk vid = cpsw->data.default_vlan; 6195c50a856SMugunthan V N 6205c50a856SMugunthan V N if (ndev->flags & IFF_PROMISC) { 6215c50a856SMugunthan V N /* Enable promiscuous mode */ 6220cd8f9ccSMugunthan V N cpsw_set_promiscious(ndev, true); 6232a05a622SIvan Khoronzhuk cpsw_ale_set_allmulti(cpsw->ale, IFF_ALLMULTI); 6245c50a856SMugunthan V N return; 6250cd8f9ccSMugunthan V N } else { 6260cd8f9ccSMugunthan V N /* Disable promiscuous mode */ 6270cd8f9ccSMugunthan V N cpsw_set_promiscious(ndev, false); 6285c50a856SMugunthan V N } 6295c50a856SMugunthan V N 6301e5c4bc4SLennart Sorensen /* Restore allmulti on vlans if necessary */ 6312a05a622SIvan Khoronzhuk cpsw_ale_set_allmulti(cpsw->ale, priv->ndev->flags & IFF_ALLMULTI); 6321e5c4bc4SLennart Sorensen 6335c50a856SMugunthan V N /* Clear all mcast from ALE */ 6342a05a622SIvan Khoronzhuk cpsw_ale_flush_multicast(cpsw->ale, ALE_ALL_PORTS, vid); 6355c50a856SMugunthan V N 6365c50a856SMugunthan V N if (!netdev_mc_empty(ndev)) { 6375c50a856SMugunthan V N struct netdev_hw_addr *ha; 6385c50a856SMugunthan V N 6395c50a856SMugunthan V N /* program multicast address list into ALE register */ 6405c50a856SMugunthan V N netdev_for_each_mc_addr(ha, ndev) { 641606f3993SIvan Khoronzhuk cpsw_add_mcast(cpsw, priv, (u8 *)ha->addr); 6425c50a856SMugunthan V N } 6435c50a856SMugunthan V N } 6445c50a856SMugunthan V N } 6455c50a856SMugunthan V N 6462c836bd9SIvan Khoronzhuk static void cpsw_intr_enable(struct cpsw_common *cpsw) 647df828598SMugunthan V N { 6485d8d0d4dSIvan Khoronzhuk __raw_writel(0xFF, &cpsw->wr_regs->tx_en); 6495d8d0d4dSIvan Khoronzhuk __raw_writel(0xFF, &cpsw->wr_regs->rx_en); 650df828598SMugunthan V N 6512c836bd9SIvan Khoronzhuk cpdma_ctlr_int_ctrl(cpsw->dma, true); 652df828598SMugunthan V N return; 653df828598SMugunthan V N } 654df828598SMugunthan V N 6552c836bd9SIvan Khoronzhuk static void cpsw_intr_disable(struct cpsw_common *cpsw) 656df828598SMugunthan V N { 6575d8d0d4dSIvan Khoronzhuk __raw_writel(0, &cpsw->wr_regs->tx_en); 6585d8d0d4dSIvan Khoronzhuk __raw_writel(0, &cpsw->wr_regs->rx_en); 659df828598SMugunthan V N 6602c836bd9SIvan Khoronzhuk cpdma_ctlr_int_ctrl(cpsw->dma, false); 661df828598SMugunthan V N return; 662df828598SMugunthan V N } 663df828598SMugunthan V N 6641a3b5056SOlof Johansson static void cpsw_tx_handler(void *token, int len, int status) 665df828598SMugunthan V N { 666e05107e6SIvan Khoronzhuk struct netdev_queue *txq; 667df828598SMugunthan V N struct sk_buff *skb = token; 668df828598SMugunthan V N struct net_device *ndev = skb->dev; 6692a05a622SIvan Khoronzhuk struct cpsw_common *cpsw = ndev_to_cpsw(ndev); 670df828598SMugunthan V N 671fae50823SMugunthan V N /* Check whether the queue is stopped due to stalled tx dma, if the 672fae50823SMugunthan V N * queue is stopped then start the queue as we have free desc for tx 673fae50823SMugunthan V N */ 674e05107e6SIvan Khoronzhuk txq = netdev_get_tx_queue(ndev, skb_get_queue_mapping(skb)); 675e05107e6SIvan Khoronzhuk if (unlikely(netif_tx_queue_stopped(txq))) 676e05107e6SIvan Khoronzhuk netif_tx_wake_queue(txq); 677e05107e6SIvan Khoronzhuk 6782a05a622SIvan Khoronzhuk cpts_tx_timestamp(cpsw->cpts, skb); 6798dc43ddcSTobias Klauser ndev->stats.tx_packets++; 6808dc43ddcSTobias Klauser ndev->stats.tx_bytes += len; 681df828598SMugunthan V N dev_kfree_skb_any(skb); 682df828598SMugunthan V N } 683df828598SMugunthan V N 6841a3b5056SOlof Johansson static void cpsw_rx_handler(void *token, int len, int status) 685df828598SMugunthan V N { 686e05107e6SIvan Khoronzhuk struct cpdma_chan *ch; 687df828598SMugunthan V N struct sk_buff *skb = token; 688b4727e69SSebastian Siewior struct sk_buff *new_skb; 689df828598SMugunthan V N struct net_device *ndev = skb->dev; 690df828598SMugunthan V N int ret = 0; 6912a05a622SIvan Khoronzhuk struct cpsw_common *cpsw = ndev_to_cpsw(ndev); 692df828598SMugunthan V N 6932a05a622SIvan Khoronzhuk cpsw_dual_emac_src_port_detect(cpsw, status, ndev, skb); 694d9ba8f9eSMugunthan V N 69516e5c57dSMugunthan V N if (unlikely(status < 0) || unlikely(!netif_running(ndev))) { 696a0e2c822SMugunthan V N bool ndev_status = false; 697606f3993SIvan Khoronzhuk struct cpsw_slave *slave = cpsw->slaves; 698a0e2c822SMugunthan V N int n; 699a0e2c822SMugunthan V N 700606f3993SIvan Khoronzhuk if (cpsw->data.dual_emac) { 701a0e2c822SMugunthan V N /* In dual emac mode check for all interfaces */ 702606f3993SIvan Khoronzhuk for (n = cpsw->data.slaves; n; n--, slave++) 703a0e2c822SMugunthan V N if (netif_running(slave->ndev)) 704a0e2c822SMugunthan V N ndev_status = true; 705a0e2c822SMugunthan V N } 706a0e2c822SMugunthan V N 707a0e2c822SMugunthan V N if (ndev_status && (status >= 0)) { 708a0e2c822SMugunthan V N /* The packet received is for the interface which 709a0e2c822SMugunthan V N * is already down and the other interface is up 710dbedd44eSJoe Perches * and running, instead of freeing which results 711a0e2c822SMugunthan V N * in reducing of the number of rx descriptor in 712a0e2c822SMugunthan V N * DMA engine, requeue skb back to cpdma. 713a0e2c822SMugunthan V N */ 714a0e2c822SMugunthan V N new_skb = skb; 715a0e2c822SMugunthan V N goto requeue; 716a0e2c822SMugunthan V N } 717a0e2c822SMugunthan V N 718b4727e69SSebastian Siewior /* the interface is going down, skbs are purged */ 719df828598SMugunthan V N dev_kfree_skb_any(skb); 720df828598SMugunthan V N return; 721df828598SMugunthan V N } 722b4727e69SSebastian Siewior 7232a05a622SIvan Khoronzhuk new_skb = netdev_alloc_skb_ip_align(ndev, cpsw->rx_packet_max); 724b4727e69SSebastian Siewior if (new_skb) { 725e05107e6SIvan Khoronzhuk skb_copy_queue_mapping(new_skb, skb); 726df828598SMugunthan V N skb_put(skb, len); 7272a05a622SIvan Khoronzhuk cpts_rx_timestamp(cpsw->cpts, skb); 728df828598SMugunthan V N skb->protocol = eth_type_trans(skb, ndev); 729df828598SMugunthan V N netif_receive_skb(skb); 7308dc43ddcSTobias Klauser ndev->stats.rx_bytes += len; 7318dc43ddcSTobias Klauser ndev->stats.rx_packets++; 732254a49d5SGrygorii Strashko kmemleak_not_leak(new_skb); 733b4727e69SSebastian Siewior } else { 7348dc43ddcSTobias Klauser ndev->stats.rx_dropped++; 735b4727e69SSebastian Siewior new_skb = skb; 736df828598SMugunthan V N } 737df828598SMugunthan V N 738a0e2c822SMugunthan V N requeue: 739ce52c744SIvan Khoronzhuk if (netif_dormant(ndev)) { 740ce52c744SIvan Khoronzhuk dev_kfree_skb_any(new_skb); 741ce52c744SIvan Khoronzhuk return; 742ce52c744SIvan Khoronzhuk } 743ce52c744SIvan Khoronzhuk 744e05107e6SIvan Khoronzhuk ch = cpsw->rxch[skb_get_queue_mapping(new_skb)]; 745e05107e6SIvan Khoronzhuk ret = cpdma_chan_submit(ch, new_skb, new_skb->data, 746b4727e69SSebastian Siewior skb_tailroom(new_skb), 0); 747b4727e69SSebastian Siewior if (WARN_ON(ret < 0)) 748b4727e69SSebastian Siewior dev_kfree_skb_any(new_skb); 749df828598SMugunthan V N } 750df828598SMugunthan V N 751c03abd84SFelipe Balbi static irqreturn_t cpsw_tx_interrupt(int irq, void *dev_id) 752df828598SMugunthan V N { 753dbc4ec52SIvan Khoronzhuk struct cpsw_common *cpsw = dev_id; 7547ce67a38SFelipe Balbi 7555d8d0d4dSIvan Khoronzhuk writel(0, &cpsw->wr_regs->tx_en); 7562c836bd9SIvan Khoronzhuk cpdma_ctlr_eoi(cpsw->dma, CPDMA_EOI_TX); 757c03abd84SFelipe Balbi 758e38b5a3dSIvan Khoronzhuk if (cpsw->quirk_irq) { 759e38b5a3dSIvan Khoronzhuk disable_irq_nosync(cpsw->irqs_table[1]); 760e38b5a3dSIvan Khoronzhuk cpsw->tx_irq_disabled = true; 7617da11600SMugunthan V N } 7627da11600SMugunthan V N 763dbc4ec52SIvan Khoronzhuk napi_schedule(&cpsw->napi_tx); 764c03abd84SFelipe Balbi return IRQ_HANDLED; 765c03abd84SFelipe Balbi } 766c03abd84SFelipe Balbi 767c03abd84SFelipe Balbi static irqreturn_t cpsw_rx_interrupt(int irq, void *dev_id) 768c03abd84SFelipe Balbi { 769dbc4ec52SIvan Khoronzhuk struct cpsw_common *cpsw = dev_id; 770c03abd84SFelipe Balbi 7712c836bd9SIvan Khoronzhuk cpdma_ctlr_eoi(cpsw->dma, CPDMA_EOI_RX); 7725d8d0d4dSIvan Khoronzhuk writel(0, &cpsw->wr_regs->rx_en); 773fd51cf19SSebastian Siewior 774e38b5a3dSIvan Khoronzhuk if (cpsw->quirk_irq) { 775e38b5a3dSIvan Khoronzhuk disable_irq_nosync(cpsw->irqs_table[0]); 776e38b5a3dSIvan Khoronzhuk cpsw->rx_irq_disabled = true; 7777da11600SMugunthan V N } 7787da11600SMugunthan V N 779dbc4ec52SIvan Khoronzhuk napi_schedule(&cpsw->napi_rx); 780df828598SMugunthan V N return IRQ_HANDLED; 781df828598SMugunthan V N } 782df828598SMugunthan V N 78332a7432cSMugunthan V N static int cpsw_tx_poll(struct napi_struct *napi_tx, int budget) 784df828598SMugunthan V N { 785e05107e6SIvan Khoronzhuk u32 ch_map; 786e05107e6SIvan Khoronzhuk int num_tx, ch; 787dbc4ec52SIvan Khoronzhuk struct cpsw_common *cpsw = napi_to_cpsw(napi_tx); 78832a7432cSMugunthan V N 789e05107e6SIvan Khoronzhuk /* process every unprocessed channel */ 790e05107e6SIvan Khoronzhuk ch_map = cpdma_ctrl_txchs_state(cpsw->dma); 791342934a5SIvan Khoronzhuk for (ch = 0, num_tx = 0; ch_map; ch_map >>= 1, ch++) { 792e05107e6SIvan Khoronzhuk if (!(ch_map & 0x01)) 793e05107e6SIvan Khoronzhuk continue; 794e05107e6SIvan Khoronzhuk 795e05107e6SIvan Khoronzhuk num_tx += cpdma_chan_process(cpsw->txch[ch], budget - num_tx); 796342934a5SIvan Khoronzhuk if (num_tx >= budget) 797342934a5SIvan Khoronzhuk break; 798e05107e6SIvan Khoronzhuk } 799e05107e6SIvan Khoronzhuk 80032a7432cSMugunthan V N if (num_tx < budget) { 80132a7432cSMugunthan V N napi_complete(napi_tx); 8025d8d0d4dSIvan Khoronzhuk writel(0xff, &cpsw->wr_regs->tx_en); 803e38b5a3dSIvan Khoronzhuk if (cpsw->quirk_irq && cpsw->tx_irq_disabled) { 804e38b5a3dSIvan Khoronzhuk cpsw->tx_irq_disabled = false; 805e38b5a3dSIvan Khoronzhuk enable_irq(cpsw->irqs_table[1]); 8067da11600SMugunthan V N } 80732a7432cSMugunthan V N } 80832a7432cSMugunthan V N 80932a7432cSMugunthan V N return num_tx; 81032a7432cSMugunthan V N } 81132a7432cSMugunthan V N 81232a7432cSMugunthan V N static int cpsw_rx_poll(struct napi_struct *napi_rx, int budget) 81332a7432cSMugunthan V N { 814e05107e6SIvan Khoronzhuk u32 ch_map; 815e05107e6SIvan Khoronzhuk int num_rx, ch; 816dbc4ec52SIvan Khoronzhuk struct cpsw_common *cpsw = napi_to_cpsw(napi_rx); 817510a1e72SMugunthan V N 818e05107e6SIvan Khoronzhuk /* process every unprocessed channel */ 819e05107e6SIvan Khoronzhuk ch_map = cpdma_ctrl_rxchs_state(cpsw->dma); 820342934a5SIvan Khoronzhuk for (ch = 0, num_rx = 0; ch_map; ch_map >>= 1, ch++) { 821e05107e6SIvan Khoronzhuk if (!(ch_map & 0x01)) 822e05107e6SIvan Khoronzhuk continue; 823e05107e6SIvan Khoronzhuk 824e05107e6SIvan Khoronzhuk num_rx += cpdma_chan_process(cpsw->rxch[ch], budget - num_rx); 825342934a5SIvan Khoronzhuk if (num_rx >= budget) 826342934a5SIvan Khoronzhuk break; 827e05107e6SIvan Khoronzhuk } 828e05107e6SIvan Khoronzhuk 829510a1e72SMugunthan V N if (num_rx < budget) { 83032a7432cSMugunthan V N napi_complete(napi_rx); 8315d8d0d4dSIvan Khoronzhuk writel(0xff, &cpsw->wr_regs->rx_en); 832e38b5a3dSIvan Khoronzhuk if (cpsw->quirk_irq && cpsw->rx_irq_disabled) { 833e38b5a3dSIvan Khoronzhuk cpsw->rx_irq_disabled = false; 834e38b5a3dSIvan Khoronzhuk enable_irq(cpsw->irqs_table[0]); 8357da11600SMugunthan V N } 836510a1e72SMugunthan V N } 837df828598SMugunthan V N 838df828598SMugunthan V N return num_rx; 839df828598SMugunthan V N } 840df828598SMugunthan V N 841df828598SMugunthan V N static inline void soft_reset(const char *module, void __iomem *reg) 842df828598SMugunthan V N { 843df828598SMugunthan V N unsigned long timeout = jiffies + HZ; 844df828598SMugunthan V N 845df828598SMugunthan V N __raw_writel(1, reg); 846df828598SMugunthan V N do { 847df828598SMugunthan V N cpu_relax(); 848df828598SMugunthan V N } while ((__raw_readl(reg) & 1) && time_after(timeout, jiffies)); 849df828598SMugunthan V N 850df828598SMugunthan V N WARN(__raw_readl(reg) & 1, "failed to soft-reset %s\n", module); 851df828598SMugunthan V N } 852df828598SMugunthan V N 853df828598SMugunthan V N #define mac_hi(mac) (((mac)[0] << 0) | ((mac)[1] << 8) | \ 854df828598SMugunthan V N ((mac)[2] << 16) | ((mac)[3] << 24)) 855df828598SMugunthan V N #define mac_lo(mac) (((mac)[4] << 0) | ((mac)[5] << 8)) 856df828598SMugunthan V N 857df828598SMugunthan V N static void cpsw_set_slave_mac(struct cpsw_slave *slave, 858df828598SMugunthan V N struct cpsw_priv *priv) 859df828598SMugunthan V N { 8609750a3adSRichard Cochran slave_write(slave, mac_hi(priv->mac_addr), SA_HI); 8619750a3adSRichard Cochran slave_write(slave, mac_lo(priv->mac_addr), SA_LO); 862df828598SMugunthan V N } 863df828598SMugunthan V N 864df828598SMugunthan V N static void _cpsw_adjust_link(struct cpsw_slave *slave, 865df828598SMugunthan V N struct cpsw_priv *priv, bool *link) 866df828598SMugunthan V N { 867df828598SMugunthan V N struct phy_device *phy = slave->phy; 868df828598SMugunthan V N u32 mac_control = 0; 869df828598SMugunthan V N u32 slave_port; 870606f3993SIvan Khoronzhuk struct cpsw_common *cpsw = priv->cpsw; 871df828598SMugunthan V N 872df828598SMugunthan V N if (!phy) 873df828598SMugunthan V N return; 874df828598SMugunthan V N 8756f1f5836SIvan Khoronzhuk slave_port = cpsw_get_slave_port(slave->slave_num); 876df828598SMugunthan V N 877df828598SMugunthan V N if (phy->link) { 878606f3993SIvan Khoronzhuk mac_control = cpsw->data.mac_control; 879df828598SMugunthan V N 880df828598SMugunthan V N /* enable forwarding */ 8812a05a622SIvan Khoronzhuk cpsw_ale_control_set(cpsw->ale, slave_port, 882df828598SMugunthan V N ALE_PORT_STATE, ALE_PORT_STATE_FORWARD); 883df828598SMugunthan V N 884df828598SMugunthan V N if (phy->speed == 1000) 885df828598SMugunthan V N mac_control |= BIT(7); /* GIGABITEN */ 886df828598SMugunthan V N if (phy->duplex) 887df828598SMugunthan V N mac_control |= BIT(0); /* FULLDUPLEXEN */ 888342b7b74SDaniel Mack 889342b7b74SDaniel Mack /* set speed_in input in case RMII mode is used in 100Mbps */ 890342b7b74SDaniel Mack if (phy->speed == 100) 891342b7b74SDaniel Mack mac_control |= BIT(15); 892a81d8762SMugunthan V N else if (phy->speed == 10) 893a81d8762SMugunthan V N mac_control |= BIT(18); /* In Band mode */ 894342b7b74SDaniel Mack 8951923d6e4SMugunthan V N if (priv->rx_pause) 8961923d6e4SMugunthan V N mac_control |= BIT(3); 8971923d6e4SMugunthan V N 8981923d6e4SMugunthan V N if (priv->tx_pause) 8991923d6e4SMugunthan V N mac_control |= BIT(4); 9001923d6e4SMugunthan V N 901df828598SMugunthan V N *link = true; 902df828598SMugunthan V N } else { 903df828598SMugunthan V N mac_control = 0; 904df828598SMugunthan V N /* disable forwarding */ 9052a05a622SIvan Khoronzhuk cpsw_ale_control_set(cpsw->ale, slave_port, 906df828598SMugunthan V N ALE_PORT_STATE, ALE_PORT_STATE_DISABLE); 907df828598SMugunthan V N } 908df828598SMugunthan V N 909df828598SMugunthan V N if (mac_control != slave->mac_control) { 910df828598SMugunthan V N phy_print_status(phy); 911df828598SMugunthan V N __raw_writel(mac_control, &slave->sliver->mac_control); 912df828598SMugunthan V N } 913df828598SMugunthan V N 914df828598SMugunthan V N slave->mac_control = mac_control; 915df828598SMugunthan V N } 916df828598SMugunthan V N 917df828598SMugunthan V N static void cpsw_adjust_link(struct net_device *ndev) 918df828598SMugunthan V N { 919df828598SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 920df828598SMugunthan V N bool link = false; 921df828598SMugunthan V N 922df828598SMugunthan V N for_each_slave(priv, _cpsw_adjust_link, priv, &link); 923df828598SMugunthan V N 924df828598SMugunthan V N if (link) { 925df828598SMugunthan V N netif_carrier_on(ndev); 926df828598SMugunthan V N if (netif_running(ndev)) 927e05107e6SIvan Khoronzhuk netif_tx_wake_all_queues(ndev); 928df828598SMugunthan V N } else { 929df828598SMugunthan V N netif_carrier_off(ndev); 930e05107e6SIvan Khoronzhuk netif_tx_stop_all_queues(ndev); 931df828598SMugunthan V N } 932df828598SMugunthan V N } 933df828598SMugunthan V N 934ff5b8ef2SMugunthan V N static int cpsw_get_coalesce(struct net_device *ndev, 935ff5b8ef2SMugunthan V N struct ethtool_coalesce *coal) 936ff5b8ef2SMugunthan V N { 9372a05a622SIvan Khoronzhuk struct cpsw_common *cpsw = ndev_to_cpsw(ndev); 938ff5b8ef2SMugunthan V N 9392a05a622SIvan Khoronzhuk coal->rx_coalesce_usecs = cpsw->coal_intvl; 940ff5b8ef2SMugunthan V N return 0; 941ff5b8ef2SMugunthan V N } 942ff5b8ef2SMugunthan V N 943ff5b8ef2SMugunthan V N static int cpsw_set_coalesce(struct net_device *ndev, 944ff5b8ef2SMugunthan V N struct ethtool_coalesce *coal) 945ff5b8ef2SMugunthan V N { 946ff5b8ef2SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 947ff5b8ef2SMugunthan V N u32 int_ctrl; 948ff5b8ef2SMugunthan V N u32 num_interrupts = 0; 949ff5b8ef2SMugunthan V N u32 prescale = 0; 950ff5b8ef2SMugunthan V N u32 addnl_dvdr = 1; 951ff5b8ef2SMugunthan V N u32 coal_intvl = 0; 9525d8d0d4dSIvan Khoronzhuk struct cpsw_common *cpsw = priv->cpsw; 953ff5b8ef2SMugunthan V N 954ff5b8ef2SMugunthan V N coal_intvl = coal->rx_coalesce_usecs; 955ff5b8ef2SMugunthan V N 9565d8d0d4dSIvan Khoronzhuk int_ctrl = readl(&cpsw->wr_regs->int_control); 9572a05a622SIvan Khoronzhuk prescale = cpsw->bus_freq_mhz * 4; 958ff5b8ef2SMugunthan V N 959a84bc2a9SMugunthan V N if (!coal->rx_coalesce_usecs) { 960a84bc2a9SMugunthan V N int_ctrl &= ~(CPSW_INTPRESCALE_MASK | CPSW_INTPACEEN); 961a84bc2a9SMugunthan V N goto update_return; 962a84bc2a9SMugunthan V N } 963a84bc2a9SMugunthan V N 964ff5b8ef2SMugunthan V N if (coal_intvl < CPSW_CMINTMIN_INTVL) 965ff5b8ef2SMugunthan V N coal_intvl = CPSW_CMINTMIN_INTVL; 966ff5b8ef2SMugunthan V N 967ff5b8ef2SMugunthan V N if (coal_intvl > CPSW_CMINTMAX_INTVL) { 968ff5b8ef2SMugunthan V N /* Interrupt pacer works with 4us Pulse, we can 969ff5b8ef2SMugunthan V N * throttle further by dilating the 4us pulse. 970ff5b8ef2SMugunthan V N */ 971ff5b8ef2SMugunthan V N addnl_dvdr = CPSW_INTPRESCALE_MASK / prescale; 972ff5b8ef2SMugunthan V N 973ff5b8ef2SMugunthan V N if (addnl_dvdr > 1) { 974ff5b8ef2SMugunthan V N prescale *= addnl_dvdr; 975ff5b8ef2SMugunthan V N if (coal_intvl > (CPSW_CMINTMAX_INTVL * addnl_dvdr)) 976ff5b8ef2SMugunthan V N coal_intvl = (CPSW_CMINTMAX_INTVL 977ff5b8ef2SMugunthan V N * addnl_dvdr); 978ff5b8ef2SMugunthan V N } else { 979ff5b8ef2SMugunthan V N addnl_dvdr = 1; 980ff5b8ef2SMugunthan V N coal_intvl = CPSW_CMINTMAX_INTVL; 981ff5b8ef2SMugunthan V N } 982ff5b8ef2SMugunthan V N } 983ff5b8ef2SMugunthan V N 984ff5b8ef2SMugunthan V N num_interrupts = (1000 * addnl_dvdr) / coal_intvl; 9855d8d0d4dSIvan Khoronzhuk writel(num_interrupts, &cpsw->wr_regs->rx_imax); 9865d8d0d4dSIvan Khoronzhuk writel(num_interrupts, &cpsw->wr_regs->tx_imax); 987ff5b8ef2SMugunthan V N 988ff5b8ef2SMugunthan V N int_ctrl |= CPSW_INTPACEEN; 989ff5b8ef2SMugunthan V N int_ctrl &= (~CPSW_INTPRESCALE_MASK); 990ff5b8ef2SMugunthan V N int_ctrl |= (prescale & CPSW_INTPRESCALE_MASK); 991a84bc2a9SMugunthan V N 992a84bc2a9SMugunthan V N update_return: 9935d8d0d4dSIvan Khoronzhuk writel(int_ctrl, &cpsw->wr_regs->int_control); 994ff5b8ef2SMugunthan V N 995ff5b8ef2SMugunthan V N cpsw_notice(priv, timer, "Set coalesce to %d usecs.\n", coal_intvl); 9962a05a622SIvan Khoronzhuk cpsw->coal_intvl = coal_intvl; 997ff5b8ef2SMugunthan V N 998ff5b8ef2SMugunthan V N return 0; 999ff5b8ef2SMugunthan V N } 1000ff5b8ef2SMugunthan V N 1001d9718546SMugunthan V N static int cpsw_get_sset_count(struct net_device *ndev, int sset) 1002d9718546SMugunthan V N { 1003e05107e6SIvan Khoronzhuk struct cpsw_common *cpsw = ndev_to_cpsw(ndev); 1004e05107e6SIvan Khoronzhuk 1005d9718546SMugunthan V N switch (sset) { 1006d9718546SMugunthan V N case ETH_SS_STATS: 1007e05107e6SIvan Khoronzhuk return (CPSW_STATS_COMMON_LEN + 1008e05107e6SIvan Khoronzhuk (cpsw->rx_ch_num + cpsw->tx_ch_num) * 1009e05107e6SIvan Khoronzhuk CPSW_STATS_CH_LEN); 1010d9718546SMugunthan V N default: 1011d9718546SMugunthan V N return -EOPNOTSUPP; 1012d9718546SMugunthan V N } 1013d9718546SMugunthan V N } 1014d9718546SMugunthan V N 1015e05107e6SIvan Khoronzhuk static void cpsw_add_ch_strings(u8 **p, int ch_num, int rx_dir) 1016e05107e6SIvan Khoronzhuk { 1017e05107e6SIvan Khoronzhuk int ch_stats_len; 1018e05107e6SIvan Khoronzhuk int line; 1019e05107e6SIvan Khoronzhuk int i; 1020e05107e6SIvan Khoronzhuk 1021e05107e6SIvan Khoronzhuk ch_stats_len = CPSW_STATS_CH_LEN * ch_num; 1022e05107e6SIvan Khoronzhuk for (i = 0; i < ch_stats_len; i++) { 1023e05107e6SIvan Khoronzhuk line = i % CPSW_STATS_CH_LEN; 1024e05107e6SIvan Khoronzhuk snprintf(*p, ETH_GSTRING_LEN, 1025e05107e6SIvan Khoronzhuk "%s DMA chan %d: %s", rx_dir ? "Rx" : "Tx", 1026e05107e6SIvan Khoronzhuk i / CPSW_STATS_CH_LEN, 1027e05107e6SIvan Khoronzhuk cpsw_gstrings_ch_stats[line].stat_string); 1028e05107e6SIvan Khoronzhuk *p += ETH_GSTRING_LEN; 1029e05107e6SIvan Khoronzhuk } 1030e05107e6SIvan Khoronzhuk } 1031e05107e6SIvan Khoronzhuk 1032d9718546SMugunthan V N static void cpsw_get_strings(struct net_device *ndev, u32 stringset, u8 *data) 1033d9718546SMugunthan V N { 1034e05107e6SIvan Khoronzhuk struct cpsw_common *cpsw = ndev_to_cpsw(ndev); 1035d9718546SMugunthan V N u8 *p = data; 1036d9718546SMugunthan V N int i; 1037d9718546SMugunthan V N 1038d9718546SMugunthan V N switch (stringset) { 1039d9718546SMugunthan V N case ETH_SS_STATS: 1040e05107e6SIvan Khoronzhuk for (i = 0; i < CPSW_STATS_COMMON_LEN; i++) { 1041d9718546SMugunthan V N memcpy(p, cpsw_gstrings_stats[i].stat_string, 1042d9718546SMugunthan V N ETH_GSTRING_LEN); 1043d9718546SMugunthan V N p += ETH_GSTRING_LEN; 1044d9718546SMugunthan V N } 1045e05107e6SIvan Khoronzhuk 1046e05107e6SIvan Khoronzhuk cpsw_add_ch_strings(&p, cpsw->rx_ch_num, 1); 1047e05107e6SIvan Khoronzhuk cpsw_add_ch_strings(&p, cpsw->tx_ch_num, 0); 1048d9718546SMugunthan V N break; 1049d9718546SMugunthan V N } 1050d9718546SMugunthan V N } 1051d9718546SMugunthan V N 1052d9718546SMugunthan V N static void cpsw_get_ethtool_stats(struct net_device *ndev, 1053d9718546SMugunthan V N struct ethtool_stats *stats, u64 *data) 1054d9718546SMugunthan V N { 1055d9718546SMugunthan V N u8 *p; 10562c836bd9SIvan Khoronzhuk struct cpsw_common *cpsw = ndev_to_cpsw(ndev); 1057e05107e6SIvan Khoronzhuk struct cpdma_chan_stats ch_stats; 1058e05107e6SIvan Khoronzhuk int i, l, ch; 1059d9718546SMugunthan V N 1060d9718546SMugunthan V N /* Collect Davinci CPDMA stats for Rx and Tx Channel */ 1061e05107e6SIvan Khoronzhuk for (l = 0; l < CPSW_STATS_COMMON_LEN; l++) 1062e05107e6SIvan Khoronzhuk data[l] = readl(cpsw->hw_stats + 1063e05107e6SIvan Khoronzhuk cpsw_gstrings_stats[l].stat_offset); 1064d9718546SMugunthan V N 1065e05107e6SIvan Khoronzhuk for (ch = 0; ch < cpsw->rx_ch_num; ch++) { 1066e05107e6SIvan Khoronzhuk cpdma_chan_get_stats(cpsw->rxch[ch], &ch_stats); 1067e05107e6SIvan Khoronzhuk for (i = 0; i < CPSW_STATS_CH_LEN; i++, l++) { 1068e05107e6SIvan Khoronzhuk p = (u8 *)&ch_stats + 1069e05107e6SIvan Khoronzhuk cpsw_gstrings_ch_stats[i].stat_offset; 1070e05107e6SIvan Khoronzhuk data[l] = *(u32 *)p; 1071e05107e6SIvan Khoronzhuk } 1072e05107e6SIvan Khoronzhuk } 1073d9718546SMugunthan V N 1074e05107e6SIvan Khoronzhuk for (ch = 0; ch < cpsw->tx_ch_num; ch++) { 1075e05107e6SIvan Khoronzhuk cpdma_chan_get_stats(cpsw->txch[ch], &ch_stats); 1076e05107e6SIvan Khoronzhuk for (i = 0; i < CPSW_STATS_CH_LEN; i++, l++) { 1077e05107e6SIvan Khoronzhuk p = (u8 *)&ch_stats + 1078e05107e6SIvan Khoronzhuk cpsw_gstrings_ch_stats[i].stat_offset; 1079e05107e6SIvan Khoronzhuk data[l] = *(u32 *)p; 1080d9718546SMugunthan V N } 1081d9718546SMugunthan V N } 1082d9718546SMugunthan V N } 1083d9718546SMugunthan V N 1084606f3993SIvan Khoronzhuk static int cpsw_common_res_usage_state(struct cpsw_common *cpsw) 1085d9ba8f9eSMugunthan V N { 1086d9ba8f9eSMugunthan V N u32 i; 1087d9ba8f9eSMugunthan V N u32 usage_count = 0; 1088d9ba8f9eSMugunthan V N 1089606f3993SIvan Khoronzhuk if (!cpsw->data.dual_emac) 1090d9ba8f9eSMugunthan V N return 0; 1091d9ba8f9eSMugunthan V N 1092606f3993SIvan Khoronzhuk for (i = 0; i < cpsw->data.slaves; i++) 1093606f3993SIvan Khoronzhuk if (cpsw->slaves[i].open_stat) 1094d9ba8f9eSMugunthan V N usage_count++; 1095d9ba8f9eSMugunthan V N 1096d9ba8f9eSMugunthan V N return usage_count; 1097d9ba8f9eSMugunthan V N } 1098d9ba8f9eSMugunthan V N 109927e9e103SIvan Khoronzhuk static inline int cpsw_tx_packet_submit(struct cpsw_priv *priv, 1100e05107e6SIvan Khoronzhuk struct sk_buff *skb, 1101e05107e6SIvan Khoronzhuk struct cpdma_chan *txch) 1102d9ba8f9eSMugunthan V N { 11032c836bd9SIvan Khoronzhuk struct cpsw_common *cpsw = priv->cpsw; 11042c836bd9SIvan Khoronzhuk 1105e05107e6SIvan Khoronzhuk return cpdma_chan_submit(txch, skb, skb->data, skb->len, 1106606f3993SIvan Khoronzhuk priv->emac_port + cpsw->data.dual_emac); 1107d9ba8f9eSMugunthan V N } 1108d9ba8f9eSMugunthan V N 1109d9ba8f9eSMugunthan V N static inline void cpsw_add_dual_emac_def_ale_entries( 1110d9ba8f9eSMugunthan V N struct cpsw_priv *priv, struct cpsw_slave *slave, 1111d9ba8f9eSMugunthan V N u32 slave_port) 1112d9ba8f9eSMugunthan V N { 11132a05a622SIvan Khoronzhuk struct cpsw_common *cpsw = priv->cpsw; 111471a2cbb7SGrygorii Strashko u32 port_mask = 1 << slave_port | ALE_PORT_HOST; 1115d9ba8f9eSMugunthan V N 11162a05a622SIvan Khoronzhuk if (cpsw->version == CPSW_VERSION_1) 1117d9ba8f9eSMugunthan V N slave_write(slave, slave->port_vlan, CPSW1_PORT_VLAN); 1118d9ba8f9eSMugunthan V N else 1119d9ba8f9eSMugunthan V N slave_write(slave, slave->port_vlan, CPSW2_PORT_VLAN); 11202a05a622SIvan Khoronzhuk cpsw_ale_add_vlan(cpsw->ale, slave->port_vlan, port_mask, 1121d9ba8f9eSMugunthan V N port_mask, port_mask, 0); 11222a05a622SIvan Khoronzhuk cpsw_ale_add_mcast(cpsw->ale, priv->ndev->broadcast, 1123d9ba8f9eSMugunthan V N port_mask, ALE_VLAN, slave->port_vlan, 0); 11242a05a622SIvan Khoronzhuk cpsw_ale_add_ucast(cpsw->ale, priv->mac_addr, 11252a05a622SIvan Khoronzhuk HOST_PORT_NUM, ALE_VLAN | 11262a05a622SIvan Khoronzhuk ALE_SECURE, slave->port_vlan); 1127d9ba8f9eSMugunthan V N } 1128d9ba8f9eSMugunthan V N 11291e7a2e21SDaniel Mack static void soft_reset_slave(struct cpsw_slave *slave) 1130df828598SMugunthan V N { 1131df828598SMugunthan V N char name[32]; 11321e7a2e21SDaniel Mack 11331e7a2e21SDaniel Mack snprintf(name, sizeof(name), "slave-%d", slave->slave_num); 11341e7a2e21SDaniel Mack soft_reset(name, &slave->sliver->soft_reset); 11351e7a2e21SDaniel Mack } 11361e7a2e21SDaniel Mack 11371e7a2e21SDaniel Mack static void cpsw_slave_open(struct cpsw_slave *slave, struct cpsw_priv *priv) 11381e7a2e21SDaniel Mack { 1139df828598SMugunthan V N u32 slave_port; 1140649a1688SIvan Khoronzhuk struct cpsw_common *cpsw = priv->cpsw; 1141df828598SMugunthan V N 11421e7a2e21SDaniel Mack soft_reset_slave(slave); 1143df828598SMugunthan V N 1144df828598SMugunthan V N /* setup priority mapping */ 1145df828598SMugunthan V N __raw_writel(RX_PRIORITY_MAPPING, &slave->sliver->rx_pri_map); 11469750a3adSRichard Cochran 11472a05a622SIvan Khoronzhuk switch (cpsw->version) { 11489750a3adSRichard Cochran case CPSW_VERSION_1: 11499750a3adSRichard Cochran slave_write(slave, TX_PRIORITY_MAPPING, CPSW1_TX_PRI_MAP); 11509750a3adSRichard Cochran break; 11519750a3adSRichard Cochran case CPSW_VERSION_2: 1152c193f365SMugunthan V N case CPSW_VERSION_3: 1153926489beSMugunthan V N case CPSW_VERSION_4: 11549750a3adSRichard Cochran slave_write(slave, TX_PRIORITY_MAPPING, CPSW2_TX_PRI_MAP); 11559750a3adSRichard Cochran break; 11569750a3adSRichard Cochran } 1157df828598SMugunthan V N 1158df828598SMugunthan V N /* setup max packet size, and mac address */ 11592a05a622SIvan Khoronzhuk __raw_writel(cpsw->rx_packet_max, &slave->sliver->rx_maxlen); 1160df828598SMugunthan V N cpsw_set_slave_mac(slave, priv); 1161df828598SMugunthan V N 1162df828598SMugunthan V N slave->mac_control = 0; /* no link yet */ 1163df828598SMugunthan V N 11646f1f5836SIvan Khoronzhuk slave_port = cpsw_get_slave_port(slave->slave_num); 1165df828598SMugunthan V N 1166606f3993SIvan Khoronzhuk if (cpsw->data.dual_emac) 1167d9ba8f9eSMugunthan V N cpsw_add_dual_emac_def_ale_entries(priv, slave, slave_port); 1168d9ba8f9eSMugunthan V N else 11692a05a622SIvan Khoronzhuk cpsw_ale_add_mcast(cpsw->ale, priv->ndev->broadcast, 1170e11b220fSMugunthan V N 1 << slave_port, 0, 0, ALE_MCAST_FWD_2); 1171df828598SMugunthan V N 1172d733f754SDavid Rivshin if (slave->data->phy_node) { 1173552165bcSDavid Rivshin slave->phy = of_phy_connect(priv->ndev, slave->data->phy_node, 11749e42f715SHeiko Schocher &cpsw_adjust_link, 0, slave->data->phy_if); 1175d733f754SDavid Rivshin if (!slave->phy) { 1176d733f754SDavid Rivshin dev_err(priv->dev, "phy \"%s\" not found on slave %d\n", 1177d733f754SDavid Rivshin slave->data->phy_node->full_name, 1178d733f754SDavid Rivshin slave->slave_num); 1179d733f754SDavid Rivshin return; 1180d733f754SDavid Rivshin } 1181d733f754SDavid Rivshin } else { 1182df828598SMugunthan V N slave->phy = phy_connect(priv->ndev, slave->data->phy_id, 1183f9a8f83bSFlorian Fainelli &cpsw_adjust_link, slave->data->phy_if); 1184df828598SMugunthan V N if (IS_ERR(slave->phy)) { 1185d733f754SDavid Rivshin dev_err(priv->dev, 1186d733f754SDavid Rivshin "phy \"%s\" not found on slave %d, err %ld\n", 1187d733f754SDavid Rivshin slave->data->phy_id, slave->slave_num, 1188d733f754SDavid Rivshin PTR_ERR(slave->phy)); 1189df828598SMugunthan V N slave->phy = NULL; 1190d733f754SDavid Rivshin return; 1191d733f754SDavid Rivshin } 1192d733f754SDavid Rivshin } 1193d733f754SDavid Rivshin 11942220943aSAndrew Lunn phy_attached_info(slave->phy); 11952220943aSAndrew Lunn 1196df828598SMugunthan V N phy_start(slave->phy); 1197388367a5SMugunthan V N 1198388367a5SMugunthan V N /* Configure GMII_SEL register */ 119956e31bd8SIvan Khoronzhuk cpsw_phy_sel(cpsw->dev, slave->phy->interface, slave->slave_num); 1200df828598SMugunthan V N } 1201df828598SMugunthan V N 12023b72c2feSMugunthan V N static inline void cpsw_add_default_vlan(struct cpsw_priv *priv) 12033b72c2feSMugunthan V N { 1204606f3993SIvan Khoronzhuk struct cpsw_common *cpsw = priv->cpsw; 1205606f3993SIvan Khoronzhuk const int vlan = cpsw->data.default_vlan; 12063b72c2feSMugunthan V N u32 reg; 12073b72c2feSMugunthan V N int i; 12081e5c4bc4SLennart Sorensen int unreg_mcast_mask; 12093b72c2feSMugunthan V N 12102a05a622SIvan Khoronzhuk reg = (cpsw->version == CPSW_VERSION_1) ? CPSW1_PORT_VLAN : 12113b72c2feSMugunthan V N CPSW2_PORT_VLAN; 12123b72c2feSMugunthan V N 12135d8d0d4dSIvan Khoronzhuk writel(vlan, &cpsw->host_port_regs->port_vlan); 12143b72c2feSMugunthan V N 1215606f3993SIvan Khoronzhuk for (i = 0; i < cpsw->data.slaves; i++) 1216606f3993SIvan Khoronzhuk slave_write(cpsw->slaves + i, vlan, reg); 12173b72c2feSMugunthan V N 12181e5c4bc4SLennart Sorensen if (priv->ndev->flags & IFF_ALLMULTI) 12191e5c4bc4SLennart Sorensen unreg_mcast_mask = ALE_ALL_PORTS; 12201e5c4bc4SLennart Sorensen else 12211e5c4bc4SLennart Sorensen unreg_mcast_mask = ALE_PORT_1 | ALE_PORT_2; 12221e5c4bc4SLennart Sorensen 12232a05a622SIvan Khoronzhuk cpsw_ale_add_vlan(cpsw->ale, vlan, ALE_ALL_PORTS, 122461f1cef9SGrygorii Strashko ALE_ALL_PORTS, ALE_ALL_PORTS, 122561f1cef9SGrygorii Strashko unreg_mcast_mask); 12263b72c2feSMugunthan V N } 12273b72c2feSMugunthan V N 1228df828598SMugunthan V N static void cpsw_init_host_port(struct cpsw_priv *priv) 1229df828598SMugunthan V N { 1230d9ba8f9eSMugunthan V N u32 fifo_mode; 12315d8d0d4dSIvan Khoronzhuk u32 control_reg; 12325d8d0d4dSIvan Khoronzhuk struct cpsw_common *cpsw = priv->cpsw; 12333b72c2feSMugunthan V N 1234df828598SMugunthan V N /* soft reset the controller and initialize ale */ 12355d8d0d4dSIvan Khoronzhuk soft_reset("cpsw", &cpsw->regs->soft_reset); 12362a05a622SIvan Khoronzhuk cpsw_ale_start(cpsw->ale); 1237df828598SMugunthan V N 1238df828598SMugunthan V N /* switch to vlan unaware mode */ 12392a05a622SIvan Khoronzhuk cpsw_ale_control_set(cpsw->ale, HOST_PORT_NUM, ALE_VLAN_AWARE, 12403b72c2feSMugunthan V N CPSW_ALE_VLAN_AWARE); 12415d8d0d4dSIvan Khoronzhuk control_reg = readl(&cpsw->regs->control); 12423b72c2feSMugunthan V N control_reg |= CPSW_VLAN_AWARE; 12435d8d0d4dSIvan Khoronzhuk writel(control_reg, &cpsw->regs->control); 1244606f3993SIvan Khoronzhuk fifo_mode = (cpsw->data.dual_emac) ? CPSW_FIFO_DUAL_MAC_MODE : 1245d9ba8f9eSMugunthan V N CPSW_FIFO_NORMAL_MODE; 12465d8d0d4dSIvan Khoronzhuk writel(fifo_mode, &cpsw->host_port_regs->tx_in_ctl); 1247df828598SMugunthan V N 1248df828598SMugunthan V N /* setup host port priority mapping */ 1249df828598SMugunthan V N __raw_writel(CPDMA_TX_PRIORITY_MAP, 12505d8d0d4dSIvan Khoronzhuk &cpsw->host_port_regs->cpdma_tx_pri_map); 12515d8d0d4dSIvan Khoronzhuk __raw_writel(0, &cpsw->host_port_regs->cpdma_rx_chan_map); 1252df828598SMugunthan V N 12532a05a622SIvan Khoronzhuk cpsw_ale_control_set(cpsw->ale, HOST_PORT_NUM, 1254df828598SMugunthan V N ALE_PORT_STATE, ALE_PORT_STATE_FORWARD); 1255df828598SMugunthan V N 1256606f3993SIvan Khoronzhuk if (!cpsw->data.dual_emac) { 12572a05a622SIvan Khoronzhuk cpsw_ale_add_ucast(cpsw->ale, priv->mac_addr, HOST_PORT_NUM, 1258d9ba8f9eSMugunthan V N 0, 0); 12592a05a622SIvan Khoronzhuk cpsw_ale_add_mcast(cpsw->ale, priv->ndev->broadcast, 126071a2cbb7SGrygorii Strashko ALE_PORT_HOST, 0, 0, ALE_MCAST_FWD_2); 1261df828598SMugunthan V N } 1262d9ba8f9eSMugunthan V N } 1263df828598SMugunthan V N 12643802dce1SIvan Khoronzhuk static int cpsw_fill_rx_channels(struct cpsw_priv *priv) 12653802dce1SIvan Khoronzhuk { 12663802dce1SIvan Khoronzhuk struct cpsw_common *cpsw = priv->cpsw; 12673802dce1SIvan Khoronzhuk struct sk_buff *skb; 12683802dce1SIvan Khoronzhuk int ch_buf_num; 1269e05107e6SIvan Khoronzhuk int ch, i, ret; 12703802dce1SIvan Khoronzhuk 1271e05107e6SIvan Khoronzhuk for (ch = 0; ch < cpsw->rx_ch_num; ch++) { 1272e05107e6SIvan Khoronzhuk ch_buf_num = cpdma_chan_get_rx_buf_num(cpsw->rxch[ch]); 12733802dce1SIvan Khoronzhuk for (i = 0; i < ch_buf_num; i++) { 12743802dce1SIvan Khoronzhuk skb = __netdev_alloc_skb_ip_align(priv->ndev, 12753802dce1SIvan Khoronzhuk cpsw->rx_packet_max, 12763802dce1SIvan Khoronzhuk GFP_KERNEL); 12773802dce1SIvan Khoronzhuk if (!skb) { 12783802dce1SIvan Khoronzhuk cpsw_err(priv, ifup, "cannot allocate skb\n"); 12793802dce1SIvan Khoronzhuk return -ENOMEM; 12803802dce1SIvan Khoronzhuk } 12813802dce1SIvan Khoronzhuk 1282e05107e6SIvan Khoronzhuk skb_set_queue_mapping(skb, ch); 1283e05107e6SIvan Khoronzhuk ret = cpdma_chan_submit(cpsw->rxch[ch], skb, skb->data, 12843802dce1SIvan Khoronzhuk skb_tailroom(skb), 0); 12853802dce1SIvan Khoronzhuk if (ret < 0) { 12863802dce1SIvan Khoronzhuk cpsw_err(priv, ifup, 1287e05107e6SIvan Khoronzhuk "cannot submit skb to channel %d rx, error %d\n", 1288e05107e6SIvan Khoronzhuk ch, ret); 12893802dce1SIvan Khoronzhuk kfree_skb(skb); 12903802dce1SIvan Khoronzhuk return ret; 12913802dce1SIvan Khoronzhuk } 12923802dce1SIvan Khoronzhuk kmemleak_not_leak(skb); 12933802dce1SIvan Khoronzhuk } 12943802dce1SIvan Khoronzhuk 1295e05107e6SIvan Khoronzhuk cpsw_info(priv, ifup, "ch %d rx, submitted %d descriptors\n", 1296e05107e6SIvan Khoronzhuk ch, ch_buf_num); 1297e05107e6SIvan Khoronzhuk } 12983802dce1SIvan Khoronzhuk 1299e05107e6SIvan Khoronzhuk return 0; 13003802dce1SIvan Khoronzhuk } 13013802dce1SIvan Khoronzhuk 13022a05a622SIvan Khoronzhuk static void cpsw_slave_stop(struct cpsw_slave *slave, struct cpsw_common *cpsw) 1303aacebbf8SSebastian Siewior { 13043995d265SSchuyler Patton u32 slave_port; 13053995d265SSchuyler Patton 13066f1f5836SIvan Khoronzhuk slave_port = cpsw_get_slave_port(slave->slave_num); 13073995d265SSchuyler Patton 1308aacebbf8SSebastian Siewior if (!slave->phy) 1309aacebbf8SSebastian Siewior return; 1310aacebbf8SSebastian Siewior phy_stop(slave->phy); 1311aacebbf8SSebastian Siewior phy_disconnect(slave->phy); 1312aacebbf8SSebastian Siewior slave->phy = NULL; 13132a05a622SIvan Khoronzhuk cpsw_ale_control_set(cpsw->ale, slave_port, 13143995d265SSchuyler Patton ALE_PORT_STATE, ALE_PORT_STATE_DISABLE); 13151f95ba00SGrygorii Strashko soft_reset_slave(slave); 1316aacebbf8SSebastian Siewior } 1317aacebbf8SSebastian Siewior 1318df828598SMugunthan V N static int cpsw_ndo_open(struct net_device *ndev) 1319df828598SMugunthan V N { 1320df828598SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 1321649a1688SIvan Khoronzhuk struct cpsw_common *cpsw = priv->cpsw; 13223802dce1SIvan Khoronzhuk int ret; 1323df828598SMugunthan V N u32 reg; 1324df828598SMugunthan V N 132556e31bd8SIvan Khoronzhuk ret = pm_runtime_get_sync(cpsw->dev); 1326108a6537SGrygorii Strashko if (ret < 0) { 132756e31bd8SIvan Khoronzhuk pm_runtime_put_noidle(cpsw->dev); 1328108a6537SGrygorii Strashko return ret; 1329108a6537SGrygorii Strashko } 13303fa88c51SGrygorii Strashko 1331606f3993SIvan Khoronzhuk if (!cpsw_common_res_usage_state(cpsw)) 13322c836bd9SIvan Khoronzhuk cpsw_intr_disable(cpsw); 1333df828598SMugunthan V N netif_carrier_off(ndev); 1334df828598SMugunthan V N 1335e05107e6SIvan Khoronzhuk /* Notify the stack of the actual queue counts. */ 1336e05107e6SIvan Khoronzhuk ret = netif_set_real_num_tx_queues(ndev, cpsw->tx_ch_num); 1337e05107e6SIvan Khoronzhuk if (ret) { 1338e05107e6SIvan Khoronzhuk dev_err(priv->dev, "cannot set real number of tx queues\n"); 1339e05107e6SIvan Khoronzhuk goto err_cleanup; 1340e05107e6SIvan Khoronzhuk } 1341e05107e6SIvan Khoronzhuk 1342e05107e6SIvan Khoronzhuk ret = netif_set_real_num_rx_queues(ndev, cpsw->rx_ch_num); 1343e05107e6SIvan Khoronzhuk if (ret) { 1344e05107e6SIvan Khoronzhuk dev_err(priv->dev, "cannot set real number of rx queues\n"); 1345e05107e6SIvan Khoronzhuk goto err_cleanup; 1346e05107e6SIvan Khoronzhuk } 1347e05107e6SIvan Khoronzhuk 13482a05a622SIvan Khoronzhuk reg = cpsw->version; 1349df828598SMugunthan V N 1350df828598SMugunthan V N dev_info(priv->dev, "initializing cpsw version %d.%d (%d)\n", 1351df828598SMugunthan V N CPSW_MAJOR_VERSION(reg), CPSW_MINOR_VERSION(reg), 1352df828598SMugunthan V N CPSW_RTL_VERSION(reg)); 1353df828598SMugunthan V N 1354df828598SMugunthan V N /* initialize host and slave ports */ 1355606f3993SIvan Khoronzhuk if (!cpsw_common_res_usage_state(cpsw)) 1356df828598SMugunthan V N cpsw_init_host_port(priv); 1357df828598SMugunthan V N for_each_slave(priv, cpsw_slave_open, priv); 1358df828598SMugunthan V N 13593b72c2feSMugunthan V N /* Add default VLAN */ 1360606f3993SIvan Khoronzhuk if (!cpsw->data.dual_emac) 13613b72c2feSMugunthan V N cpsw_add_default_vlan(priv); 1362e6afea0bSMugunthan V N else 13632a05a622SIvan Khoronzhuk cpsw_ale_add_vlan(cpsw->ale, cpsw->data.default_vlan, 136461f1cef9SGrygorii Strashko ALE_ALL_PORTS, ALE_ALL_PORTS, 0, 0); 13653b72c2feSMugunthan V N 1366606f3993SIvan Khoronzhuk if (!cpsw_common_res_usage_state(cpsw)) { 1367d9ba8f9eSMugunthan V N /* disable priority elevation */ 13685d8d0d4dSIvan Khoronzhuk __raw_writel(0, &cpsw->regs->ptype); 1369df828598SMugunthan V N 1370d9ba8f9eSMugunthan V N /* enable statistics collection only on all ports */ 13715d8d0d4dSIvan Khoronzhuk __raw_writel(0x7, &cpsw->regs->stat_port_en); 1372df828598SMugunthan V N 13731923d6e4SMugunthan V N /* Enable internal fifo flow control */ 13745d8d0d4dSIvan Khoronzhuk writel(0x7, &cpsw->regs->flow_control); 13751923d6e4SMugunthan V N 1376dbc4ec52SIvan Khoronzhuk napi_enable(&cpsw->napi_rx); 1377dbc4ec52SIvan Khoronzhuk napi_enable(&cpsw->napi_tx); 1378d354eb85SMugunthan V N 1379e38b5a3dSIvan Khoronzhuk if (cpsw->tx_irq_disabled) { 1380e38b5a3dSIvan Khoronzhuk cpsw->tx_irq_disabled = false; 1381e38b5a3dSIvan Khoronzhuk enable_irq(cpsw->irqs_table[1]); 13827da11600SMugunthan V N } 13837da11600SMugunthan V N 1384e38b5a3dSIvan Khoronzhuk if (cpsw->rx_irq_disabled) { 1385e38b5a3dSIvan Khoronzhuk cpsw->rx_irq_disabled = false; 1386e38b5a3dSIvan Khoronzhuk enable_irq(cpsw->irqs_table[0]); 13877da11600SMugunthan V N } 13887da11600SMugunthan V N 13893802dce1SIvan Khoronzhuk ret = cpsw_fill_rx_channels(priv); 13903802dce1SIvan Khoronzhuk if (ret < 0) 1391aacebbf8SSebastian Siewior goto err_cleanup; 1392f280e89aSMugunthan V N 13932a05a622SIvan Khoronzhuk if (cpts_register(cpsw->dev, cpsw->cpts, 1394606f3993SIvan Khoronzhuk cpsw->data.cpts_clock_mult, 1395606f3993SIvan Khoronzhuk cpsw->data.cpts_clock_shift)) 1396f280e89aSMugunthan V N dev_err(priv->dev, "error registering cpts device\n"); 1397f280e89aSMugunthan V N 1398d9ba8f9eSMugunthan V N } 1399df828598SMugunthan V N 1400ff5b8ef2SMugunthan V N /* Enable Interrupt pacing if configured */ 14012a05a622SIvan Khoronzhuk if (cpsw->coal_intvl != 0) { 1402ff5b8ef2SMugunthan V N struct ethtool_coalesce coal; 1403ff5b8ef2SMugunthan V N 14042a05a622SIvan Khoronzhuk coal.rx_coalesce_usecs = cpsw->coal_intvl; 1405ff5b8ef2SMugunthan V N cpsw_set_coalesce(ndev, &coal); 1406ff5b8ef2SMugunthan V N } 1407ff5b8ef2SMugunthan V N 14082c836bd9SIvan Khoronzhuk cpdma_ctlr_start(cpsw->dma); 14092c836bd9SIvan Khoronzhuk cpsw_intr_enable(cpsw); 1410f63a975eSMugunthan V N 1411606f3993SIvan Khoronzhuk if (cpsw->data.dual_emac) 1412606f3993SIvan Khoronzhuk cpsw->slaves[priv->emac_port].open_stat = true; 1413e05107e6SIvan Khoronzhuk 1414e05107e6SIvan Khoronzhuk netif_tx_start_all_queues(ndev); 1415e05107e6SIvan Khoronzhuk 1416df828598SMugunthan V N return 0; 1417df828598SMugunthan V N 1418aacebbf8SSebastian Siewior err_cleanup: 14192c836bd9SIvan Khoronzhuk cpdma_ctlr_stop(cpsw->dma); 14202a05a622SIvan Khoronzhuk for_each_slave(priv, cpsw_slave_stop, cpsw); 142156e31bd8SIvan Khoronzhuk pm_runtime_put_sync(cpsw->dev); 1422aacebbf8SSebastian Siewior netif_carrier_off(priv->ndev); 1423aacebbf8SSebastian Siewior return ret; 1424df828598SMugunthan V N } 1425df828598SMugunthan V N 1426df828598SMugunthan V N static int cpsw_ndo_stop(struct net_device *ndev) 1427df828598SMugunthan V N { 1428df828598SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 1429649a1688SIvan Khoronzhuk struct cpsw_common *cpsw = priv->cpsw; 1430df828598SMugunthan V N 1431df828598SMugunthan V N cpsw_info(priv, ifdown, "shutting down cpsw device\n"); 1432e05107e6SIvan Khoronzhuk netif_tx_stop_all_queues(priv->ndev); 1433df828598SMugunthan V N netif_carrier_off(priv->ndev); 1434d9ba8f9eSMugunthan V N 1435606f3993SIvan Khoronzhuk if (cpsw_common_res_usage_state(cpsw) <= 1) { 1436dbc4ec52SIvan Khoronzhuk napi_disable(&cpsw->napi_rx); 1437dbc4ec52SIvan Khoronzhuk napi_disable(&cpsw->napi_tx); 14382a05a622SIvan Khoronzhuk cpts_unregister(cpsw->cpts); 14392c836bd9SIvan Khoronzhuk cpsw_intr_disable(cpsw); 14402c836bd9SIvan Khoronzhuk cpdma_ctlr_stop(cpsw->dma); 14412a05a622SIvan Khoronzhuk cpsw_ale_stop(cpsw->ale); 1442d9ba8f9eSMugunthan V N } 14432a05a622SIvan Khoronzhuk for_each_slave(priv, cpsw_slave_stop, cpsw); 144456e31bd8SIvan Khoronzhuk pm_runtime_put_sync(cpsw->dev); 1445606f3993SIvan Khoronzhuk if (cpsw->data.dual_emac) 1446606f3993SIvan Khoronzhuk cpsw->slaves[priv->emac_port].open_stat = false; 1447df828598SMugunthan V N return 0; 1448df828598SMugunthan V N } 1449df828598SMugunthan V N 1450df828598SMugunthan V N static netdev_tx_t cpsw_ndo_start_xmit(struct sk_buff *skb, 1451df828598SMugunthan V N struct net_device *ndev) 1452df828598SMugunthan V N { 1453df828598SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 14542c836bd9SIvan Khoronzhuk struct cpsw_common *cpsw = priv->cpsw; 1455e05107e6SIvan Khoronzhuk struct netdev_queue *txq; 1456e05107e6SIvan Khoronzhuk struct cpdma_chan *txch; 1457e05107e6SIvan Khoronzhuk int ret, q_idx; 1458df828598SMugunthan V N 1459860e9538SFlorian Westphal netif_trans_update(ndev); 1460df828598SMugunthan V N 1461df828598SMugunthan V N if (skb_padto(skb, CPSW_MIN_PACKET_SIZE)) { 1462df828598SMugunthan V N cpsw_err(priv, tx_err, "packet pad failed\n"); 14638dc43ddcSTobias Klauser ndev->stats.tx_dropped++; 1464df828598SMugunthan V N return NETDEV_TX_OK; 1465df828598SMugunthan V N } 1466df828598SMugunthan V N 14679232b16dSMugunthan V N if (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP && 14682a05a622SIvan Khoronzhuk cpsw->cpts->tx_enable) 14692e5b38abSRichard Cochran skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 14702e5b38abSRichard Cochran 14712e5b38abSRichard Cochran skb_tx_timestamp(skb); 14722e5b38abSRichard Cochran 1473e05107e6SIvan Khoronzhuk q_idx = skb_get_queue_mapping(skb); 1474e05107e6SIvan Khoronzhuk if (q_idx >= cpsw->tx_ch_num) 1475e05107e6SIvan Khoronzhuk q_idx = q_idx % cpsw->tx_ch_num; 1476e05107e6SIvan Khoronzhuk 1477e05107e6SIvan Khoronzhuk txch = cpsw->txch[q_idx]; 1478e05107e6SIvan Khoronzhuk ret = cpsw_tx_packet_submit(priv, skb, txch); 1479df828598SMugunthan V N if (unlikely(ret != 0)) { 1480df828598SMugunthan V N cpsw_err(priv, tx_err, "desc submit failed\n"); 1481df828598SMugunthan V N goto fail; 1482df828598SMugunthan V N } 1483df828598SMugunthan V N 1484fae50823SMugunthan V N /* If there is no more tx desc left free then we need to 1485fae50823SMugunthan V N * tell the kernel to stop sending us tx frames. 1486fae50823SMugunthan V N */ 1487e05107e6SIvan Khoronzhuk if (unlikely(!cpdma_check_free_tx_desc(txch))) { 1488e05107e6SIvan Khoronzhuk txq = netdev_get_tx_queue(ndev, q_idx); 1489e05107e6SIvan Khoronzhuk netif_tx_stop_queue(txq); 1490e05107e6SIvan Khoronzhuk } 1491fae50823SMugunthan V N 1492df828598SMugunthan V N return NETDEV_TX_OK; 1493df828598SMugunthan V N fail: 14948dc43ddcSTobias Klauser ndev->stats.tx_dropped++; 1495e05107e6SIvan Khoronzhuk txq = netdev_get_tx_queue(ndev, skb_get_queue_mapping(skb)); 1496e05107e6SIvan Khoronzhuk netif_tx_stop_queue(txq); 1497df828598SMugunthan V N return NETDEV_TX_BUSY; 1498df828598SMugunthan V N } 1499df828598SMugunthan V N 15002e5b38abSRichard Cochran #ifdef CONFIG_TI_CPTS 15012e5b38abSRichard Cochran 15022a05a622SIvan Khoronzhuk static void cpsw_hwtstamp_v1(struct cpsw_common *cpsw) 15032e5b38abSRichard Cochran { 1504606f3993SIvan Khoronzhuk struct cpsw_slave *slave = &cpsw->slaves[cpsw->data.active_slave]; 15052e5b38abSRichard Cochran u32 ts_en, seq_id; 15062e5b38abSRichard Cochran 15072a05a622SIvan Khoronzhuk if (!cpsw->cpts->tx_enable && !cpsw->cpts->rx_enable) { 15082e5b38abSRichard Cochran slave_write(slave, 0, CPSW1_TS_CTL); 15092e5b38abSRichard Cochran return; 15102e5b38abSRichard Cochran } 15112e5b38abSRichard Cochran 15122e5b38abSRichard Cochran seq_id = (30 << CPSW_V1_SEQ_ID_OFS_SHIFT) | ETH_P_1588; 15132e5b38abSRichard Cochran ts_en = EVENT_MSG_BITS << CPSW_V1_MSG_TYPE_OFS; 15142e5b38abSRichard Cochran 15152a05a622SIvan Khoronzhuk if (cpsw->cpts->tx_enable) 15162e5b38abSRichard Cochran ts_en |= CPSW_V1_TS_TX_EN; 15172e5b38abSRichard Cochran 15182a05a622SIvan Khoronzhuk if (cpsw->cpts->rx_enable) 15192e5b38abSRichard Cochran ts_en |= CPSW_V1_TS_RX_EN; 15202e5b38abSRichard Cochran 15212e5b38abSRichard Cochran slave_write(slave, ts_en, CPSW1_TS_CTL); 15222e5b38abSRichard Cochran slave_write(slave, seq_id, CPSW1_TS_SEQ_LTYPE); 15232e5b38abSRichard Cochran } 15242e5b38abSRichard Cochran 15252e5b38abSRichard Cochran static void cpsw_hwtstamp_v2(struct cpsw_priv *priv) 15262e5b38abSRichard Cochran { 1527d9ba8f9eSMugunthan V N struct cpsw_slave *slave; 15285d8d0d4dSIvan Khoronzhuk struct cpsw_common *cpsw = priv->cpsw; 15292e5b38abSRichard Cochran u32 ctrl, mtype; 15302e5b38abSRichard Cochran 1531606f3993SIvan Khoronzhuk if (cpsw->data.dual_emac) 1532606f3993SIvan Khoronzhuk slave = &cpsw->slaves[priv->emac_port]; 1533d9ba8f9eSMugunthan V N else 1534606f3993SIvan Khoronzhuk slave = &cpsw->slaves[cpsw->data.active_slave]; 1535d9ba8f9eSMugunthan V N 15362e5b38abSRichard Cochran ctrl = slave_read(slave, CPSW2_CONTROL); 15372a05a622SIvan Khoronzhuk switch (cpsw->version) { 153809c55372SGeorge Cherian case CPSW_VERSION_2: 153909c55372SGeorge Cherian ctrl &= ~CTRL_V2_ALL_TS_MASK; 15402e5b38abSRichard Cochran 15412a05a622SIvan Khoronzhuk if (cpsw->cpts->tx_enable) 154209c55372SGeorge Cherian ctrl |= CTRL_V2_TX_TS_BITS; 15432e5b38abSRichard Cochran 15442a05a622SIvan Khoronzhuk if (cpsw->cpts->rx_enable) 154509c55372SGeorge Cherian ctrl |= CTRL_V2_RX_TS_BITS; 154609c55372SGeorge Cherian break; 154709c55372SGeorge Cherian case CPSW_VERSION_3: 154809c55372SGeorge Cherian default: 154909c55372SGeorge Cherian ctrl &= ~CTRL_V3_ALL_TS_MASK; 155009c55372SGeorge Cherian 15512a05a622SIvan Khoronzhuk if (cpsw->cpts->tx_enable) 155209c55372SGeorge Cherian ctrl |= CTRL_V3_TX_TS_BITS; 155309c55372SGeorge Cherian 15542a05a622SIvan Khoronzhuk if (cpsw->cpts->rx_enable) 155509c55372SGeorge Cherian ctrl |= CTRL_V3_RX_TS_BITS; 155609c55372SGeorge Cherian break; 155709c55372SGeorge Cherian } 15582e5b38abSRichard Cochran 15592e5b38abSRichard Cochran mtype = (30 << TS_SEQ_ID_OFFSET_SHIFT) | EVENT_MSG_BITS; 15602e5b38abSRichard Cochran 15612e5b38abSRichard Cochran slave_write(slave, mtype, CPSW2_TS_SEQ_MTYPE); 15622e5b38abSRichard Cochran slave_write(slave, ctrl, CPSW2_CONTROL); 15635d8d0d4dSIvan Khoronzhuk __raw_writel(ETH_P_1588, &cpsw->regs->ts_ltype); 15642e5b38abSRichard Cochran } 15652e5b38abSRichard Cochran 1566a5b4145bSBen Hutchings static int cpsw_hwtstamp_set(struct net_device *dev, struct ifreq *ifr) 15672e5b38abSRichard Cochran { 15683177bf6fSMugunthan V N struct cpsw_priv *priv = netdev_priv(dev); 15692e5b38abSRichard Cochran struct hwtstamp_config cfg; 15702a05a622SIvan Khoronzhuk struct cpsw_common *cpsw = priv->cpsw; 15712a05a622SIvan Khoronzhuk struct cpts *cpts = cpsw->cpts; 15722e5b38abSRichard Cochran 15732a05a622SIvan Khoronzhuk if (cpsw->version != CPSW_VERSION_1 && 15742a05a622SIvan Khoronzhuk cpsw->version != CPSW_VERSION_2 && 15752a05a622SIvan Khoronzhuk cpsw->version != CPSW_VERSION_3) 15762ee91e54SBen Hutchings return -EOPNOTSUPP; 15772ee91e54SBen Hutchings 15782e5b38abSRichard Cochran if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg))) 15792e5b38abSRichard Cochran return -EFAULT; 15802e5b38abSRichard Cochran 15812e5b38abSRichard Cochran /* reserved for future extensions */ 15822e5b38abSRichard Cochran if (cfg.flags) 15832e5b38abSRichard Cochran return -EINVAL; 15842e5b38abSRichard Cochran 15852ee91e54SBen Hutchings if (cfg.tx_type != HWTSTAMP_TX_OFF && cfg.tx_type != HWTSTAMP_TX_ON) 15862e5b38abSRichard Cochran return -ERANGE; 15872e5b38abSRichard Cochran 15882e5b38abSRichard Cochran switch (cfg.rx_filter) { 15892e5b38abSRichard Cochran case HWTSTAMP_FILTER_NONE: 15902e5b38abSRichard Cochran cpts->rx_enable = 0; 15912e5b38abSRichard Cochran break; 15922e5b38abSRichard Cochran case HWTSTAMP_FILTER_ALL: 15932e5b38abSRichard Cochran case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: 15942e5b38abSRichard Cochran case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: 15952e5b38abSRichard Cochran case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: 15962e5b38abSRichard Cochran return -ERANGE; 15972e5b38abSRichard Cochran case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: 15982e5b38abSRichard Cochran case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 15992e5b38abSRichard Cochran case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 16002e5b38abSRichard Cochran case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: 16012e5b38abSRichard Cochran case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: 16022e5b38abSRichard Cochran case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: 16032e5b38abSRichard Cochran case HWTSTAMP_FILTER_PTP_V2_EVENT: 16042e5b38abSRichard Cochran case HWTSTAMP_FILTER_PTP_V2_SYNC: 16052e5b38abSRichard Cochran case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 16062e5b38abSRichard Cochran cpts->rx_enable = 1; 16072e5b38abSRichard Cochran cfg.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT; 16082e5b38abSRichard Cochran break; 16092e5b38abSRichard Cochran default: 16102e5b38abSRichard Cochran return -ERANGE; 16112e5b38abSRichard Cochran } 16122e5b38abSRichard Cochran 16132ee91e54SBen Hutchings cpts->tx_enable = cfg.tx_type == HWTSTAMP_TX_ON; 16142ee91e54SBen Hutchings 16152a05a622SIvan Khoronzhuk switch (cpsw->version) { 16162e5b38abSRichard Cochran case CPSW_VERSION_1: 16172a05a622SIvan Khoronzhuk cpsw_hwtstamp_v1(cpsw); 16182e5b38abSRichard Cochran break; 16192e5b38abSRichard Cochran case CPSW_VERSION_2: 1620f7d403cbSGeorge Cherian case CPSW_VERSION_3: 16212e5b38abSRichard Cochran cpsw_hwtstamp_v2(priv); 16222e5b38abSRichard Cochran break; 16232e5b38abSRichard Cochran default: 16242ee91e54SBen Hutchings WARN_ON(1); 16252e5b38abSRichard Cochran } 16262e5b38abSRichard Cochran 16272e5b38abSRichard Cochran return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0; 16282e5b38abSRichard Cochran } 16292e5b38abSRichard Cochran 1630a5b4145bSBen Hutchings static int cpsw_hwtstamp_get(struct net_device *dev, struct ifreq *ifr) 1631a5b4145bSBen Hutchings { 16322a05a622SIvan Khoronzhuk struct cpsw_common *cpsw = ndev_to_cpsw(dev); 16332a05a622SIvan Khoronzhuk struct cpts *cpts = cpsw->cpts; 1634a5b4145bSBen Hutchings struct hwtstamp_config cfg; 1635a5b4145bSBen Hutchings 16362a05a622SIvan Khoronzhuk if (cpsw->version != CPSW_VERSION_1 && 16372a05a622SIvan Khoronzhuk cpsw->version != CPSW_VERSION_2 && 16382a05a622SIvan Khoronzhuk cpsw->version != CPSW_VERSION_3) 1639a5b4145bSBen Hutchings return -EOPNOTSUPP; 1640a5b4145bSBen Hutchings 1641a5b4145bSBen Hutchings cfg.flags = 0; 1642a5b4145bSBen Hutchings cfg.tx_type = cpts->tx_enable ? HWTSTAMP_TX_ON : HWTSTAMP_TX_OFF; 1643a5b4145bSBen Hutchings cfg.rx_filter = (cpts->rx_enable ? 1644a5b4145bSBen Hutchings HWTSTAMP_FILTER_PTP_V2_EVENT : HWTSTAMP_FILTER_NONE); 1645a5b4145bSBen Hutchings 1646a5b4145bSBen Hutchings return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0; 1647a5b4145bSBen Hutchings } 1648a5b4145bSBen Hutchings 16492e5b38abSRichard Cochran #endif /*CONFIG_TI_CPTS*/ 16502e5b38abSRichard Cochran 16512e5b38abSRichard Cochran static int cpsw_ndo_ioctl(struct net_device *dev, struct ifreq *req, int cmd) 16522e5b38abSRichard Cochran { 165311f2c988SMugunthan V N struct cpsw_priv *priv = netdev_priv(dev); 1654606f3993SIvan Khoronzhuk struct cpsw_common *cpsw = priv->cpsw; 1655606f3993SIvan Khoronzhuk int slave_no = cpsw_slave_index(cpsw, priv); 165611f2c988SMugunthan V N 16572e5b38abSRichard Cochran if (!netif_running(dev)) 16582e5b38abSRichard Cochran return -EINVAL; 16592e5b38abSRichard Cochran 166011f2c988SMugunthan V N switch (cmd) { 16612e5b38abSRichard Cochran #ifdef CONFIG_TI_CPTS 166211f2c988SMugunthan V N case SIOCSHWTSTAMP: 1663a5b4145bSBen Hutchings return cpsw_hwtstamp_set(dev, req); 1664a5b4145bSBen Hutchings case SIOCGHWTSTAMP: 1665a5b4145bSBen Hutchings return cpsw_hwtstamp_get(dev, req); 16662e5b38abSRichard Cochran #endif 16672e5b38abSRichard Cochran } 16682e5b38abSRichard Cochran 1669606f3993SIvan Khoronzhuk if (!cpsw->slaves[slave_no].phy) 1670c1b59947SStefan Sørensen return -EOPNOTSUPP; 1671606f3993SIvan Khoronzhuk return phy_mii_ioctl(cpsw->slaves[slave_no].phy, req, cmd); 167211f2c988SMugunthan V N } 167311f2c988SMugunthan V N 1674df828598SMugunthan V N static void cpsw_ndo_tx_timeout(struct net_device *ndev) 1675df828598SMugunthan V N { 1676df828598SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 16772c836bd9SIvan Khoronzhuk struct cpsw_common *cpsw = priv->cpsw; 1678e05107e6SIvan Khoronzhuk int ch; 1679df828598SMugunthan V N 1680df828598SMugunthan V N cpsw_err(priv, tx_err, "transmit timeout, restarting dma\n"); 16818dc43ddcSTobias Klauser ndev->stats.tx_errors++; 16822c836bd9SIvan Khoronzhuk cpsw_intr_disable(cpsw); 1683e05107e6SIvan Khoronzhuk for (ch = 0; ch < cpsw->tx_ch_num; ch++) { 1684e05107e6SIvan Khoronzhuk cpdma_chan_stop(cpsw->txch[ch]); 1685e05107e6SIvan Khoronzhuk cpdma_chan_start(cpsw->txch[ch]); 1686e05107e6SIvan Khoronzhuk } 1687e05107e6SIvan Khoronzhuk 16882c836bd9SIvan Khoronzhuk cpsw_intr_enable(cpsw); 1689df828598SMugunthan V N } 1690df828598SMugunthan V N 1691dcfd8d58SMugunthan V N static int cpsw_ndo_set_mac_address(struct net_device *ndev, void *p) 1692dcfd8d58SMugunthan V N { 1693dcfd8d58SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 1694dcfd8d58SMugunthan V N struct sockaddr *addr = (struct sockaddr *)p; 1695649a1688SIvan Khoronzhuk struct cpsw_common *cpsw = priv->cpsw; 1696dcfd8d58SMugunthan V N int flags = 0; 1697dcfd8d58SMugunthan V N u16 vid = 0; 1698a6c5d14fSGrygorii Strashko int ret; 1699dcfd8d58SMugunthan V N 1700dcfd8d58SMugunthan V N if (!is_valid_ether_addr(addr->sa_data)) 1701dcfd8d58SMugunthan V N return -EADDRNOTAVAIL; 1702dcfd8d58SMugunthan V N 170356e31bd8SIvan Khoronzhuk ret = pm_runtime_get_sync(cpsw->dev); 1704a6c5d14fSGrygorii Strashko if (ret < 0) { 170556e31bd8SIvan Khoronzhuk pm_runtime_put_noidle(cpsw->dev); 1706a6c5d14fSGrygorii Strashko return ret; 1707a6c5d14fSGrygorii Strashko } 1708a6c5d14fSGrygorii Strashko 1709606f3993SIvan Khoronzhuk if (cpsw->data.dual_emac) { 1710606f3993SIvan Khoronzhuk vid = cpsw->slaves[priv->emac_port].port_vlan; 1711dcfd8d58SMugunthan V N flags = ALE_VLAN; 1712dcfd8d58SMugunthan V N } 1713dcfd8d58SMugunthan V N 17142a05a622SIvan Khoronzhuk cpsw_ale_del_ucast(cpsw->ale, priv->mac_addr, HOST_PORT_NUM, 1715dcfd8d58SMugunthan V N flags, vid); 17162a05a622SIvan Khoronzhuk cpsw_ale_add_ucast(cpsw->ale, addr->sa_data, HOST_PORT_NUM, 1717dcfd8d58SMugunthan V N flags, vid); 1718dcfd8d58SMugunthan V N 1719dcfd8d58SMugunthan V N memcpy(priv->mac_addr, addr->sa_data, ETH_ALEN); 1720dcfd8d58SMugunthan V N memcpy(ndev->dev_addr, priv->mac_addr, ETH_ALEN); 1721dcfd8d58SMugunthan V N for_each_slave(priv, cpsw_set_slave_mac, priv); 1722dcfd8d58SMugunthan V N 172356e31bd8SIvan Khoronzhuk pm_runtime_put(cpsw->dev); 1724a6c5d14fSGrygorii Strashko 1725dcfd8d58SMugunthan V N return 0; 1726dcfd8d58SMugunthan V N } 1727dcfd8d58SMugunthan V N 1728df828598SMugunthan V N #ifdef CONFIG_NET_POLL_CONTROLLER 1729df828598SMugunthan V N static void cpsw_ndo_poll_controller(struct net_device *ndev) 1730df828598SMugunthan V N { 1731dbc4ec52SIvan Khoronzhuk struct cpsw_common *cpsw = ndev_to_cpsw(ndev); 1732df828598SMugunthan V N 1733dbc4ec52SIvan Khoronzhuk cpsw_intr_disable(cpsw); 1734dbc4ec52SIvan Khoronzhuk cpsw_rx_interrupt(cpsw->irqs_table[0], cpsw); 1735dbc4ec52SIvan Khoronzhuk cpsw_tx_interrupt(cpsw->irqs_table[1], cpsw); 1736dbc4ec52SIvan Khoronzhuk cpsw_intr_enable(cpsw); 1737df828598SMugunthan V N } 1738df828598SMugunthan V N #endif 1739df828598SMugunthan V N 17403b72c2feSMugunthan V N static inline int cpsw_add_vlan_ale_entry(struct cpsw_priv *priv, 17413b72c2feSMugunthan V N unsigned short vid) 17423b72c2feSMugunthan V N { 17433b72c2feSMugunthan V N int ret; 17449f6bd8faSMugunthan V N int unreg_mcast_mask = 0; 17459f6bd8faSMugunthan V N u32 port_mask; 1746606f3993SIvan Khoronzhuk struct cpsw_common *cpsw = priv->cpsw; 17479f6bd8faSMugunthan V N 1748606f3993SIvan Khoronzhuk if (cpsw->data.dual_emac) { 17499f6bd8faSMugunthan V N port_mask = (1 << (priv->emac_port + 1)) | ALE_PORT_HOST; 17509f6bd8faSMugunthan V N 17519f6bd8faSMugunthan V N if (priv->ndev->flags & IFF_ALLMULTI) 17529f6bd8faSMugunthan V N unreg_mcast_mask = port_mask; 17539f6bd8faSMugunthan V N } else { 17549f6bd8faSMugunthan V N port_mask = ALE_ALL_PORTS; 17551e5c4bc4SLennart Sorensen 17561e5c4bc4SLennart Sorensen if (priv->ndev->flags & IFF_ALLMULTI) 17571e5c4bc4SLennart Sorensen unreg_mcast_mask = ALE_ALL_PORTS; 17581e5c4bc4SLennart Sorensen else 17591e5c4bc4SLennart Sorensen unreg_mcast_mask = ALE_PORT_1 | ALE_PORT_2; 17609f6bd8faSMugunthan V N } 17613b72c2feSMugunthan V N 17622a05a622SIvan Khoronzhuk ret = cpsw_ale_add_vlan(cpsw->ale, vid, port_mask, 0, port_mask, 176361f1cef9SGrygorii Strashko unreg_mcast_mask); 17643b72c2feSMugunthan V N if (ret != 0) 17653b72c2feSMugunthan V N return ret; 17663b72c2feSMugunthan V N 17672a05a622SIvan Khoronzhuk ret = cpsw_ale_add_ucast(cpsw->ale, priv->mac_addr, 176871a2cbb7SGrygorii Strashko HOST_PORT_NUM, ALE_VLAN, vid); 17693b72c2feSMugunthan V N if (ret != 0) 17703b72c2feSMugunthan V N goto clean_vid; 17713b72c2feSMugunthan V N 17722a05a622SIvan Khoronzhuk ret = cpsw_ale_add_mcast(cpsw->ale, priv->ndev->broadcast, 17739f6bd8faSMugunthan V N port_mask, ALE_VLAN, vid, 0); 17743b72c2feSMugunthan V N if (ret != 0) 17753b72c2feSMugunthan V N goto clean_vlan_ucast; 17763b72c2feSMugunthan V N return 0; 17773b72c2feSMugunthan V N 17783b72c2feSMugunthan V N clean_vlan_ucast: 17792a05a622SIvan Khoronzhuk cpsw_ale_del_ucast(cpsw->ale, priv->mac_addr, 178071a2cbb7SGrygorii Strashko HOST_PORT_NUM, ALE_VLAN, vid); 17813b72c2feSMugunthan V N clean_vid: 17822a05a622SIvan Khoronzhuk cpsw_ale_del_vlan(cpsw->ale, vid, 0); 17833b72c2feSMugunthan V N return ret; 17843b72c2feSMugunthan V N } 17853b72c2feSMugunthan V N 17863b72c2feSMugunthan V N static int cpsw_ndo_vlan_rx_add_vid(struct net_device *ndev, 178780d5c368SPatrick McHardy __be16 proto, u16 vid) 17883b72c2feSMugunthan V N { 17893b72c2feSMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 1790649a1688SIvan Khoronzhuk struct cpsw_common *cpsw = priv->cpsw; 1791a6c5d14fSGrygorii Strashko int ret; 17923b72c2feSMugunthan V N 1793606f3993SIvan Khoronzhuk if (vid == cpsw->data.default_vlan) 17943b72c2feSMugunthan V N return 0; 17953b72c2feSMugunthan V N 179656e31bd8SIvan Khoronzhuk ret = pm_runtime_get_sync(cpsw->dev); 1797a6c5d14fSGrygorii Strashko if (ret < 0) { 179856e31bd8SIvan Khoronzhuk pm_runtime_put_noidle(cpsw->dev); 1799a6c5d14fSGrygorii Strashko return ret; 1800a6c5d14fSGrygorii Strashko } 1801a6c5d14fSGrygorii Strashko 1802606f3993SIvan Khoronzhuk if (cpsw->data.dual_emac) { 180302a54164SMugunthan V N /* In dual EMAC, reserved VLAN id should not be used for 180402a54164SMugunthan V N * creating VLAN interfaces as this can break the dual 180502a54164SMugunthan V N * EMAC port separation 180602a54164SMugunthan V N */ 180702a54164SMugunthan V N int i; 180802a54164SMugunthan V N 1809606f3993SIvan Khoronzhuk for (i = 0; i < cpsw->data.slaves; i++) { 1810606f3993SIvan Khoronzhuk if (vid == cpsw->slaves[i].port_vlan) 181102a54164SMugunthan V N return -EINVAL; 181202a54164SMugunthan V N } 181302a54164SMugunthan V N } 181402a54164SMugunthan V N 18153b72c2feSMugunthan V N dev_info(priv->dev, "Adding vlanid %d to vlan filter\n", vid); 1816a6c5d14fSGrygorii Strashko ret = cpsw_add_vlan_ale_entry(priv, vid); 1817a6c5d14fSGrygorii Strashko 181856e31bd8SIvan Khoronzhuk pm_runtime_put(cpsw->dev); 1819a6c5d14fSGrygorii Strashko return ret; 18203b72c2feSMugunthan V N } 18213b72c2feSMugunthan V N 18223b72c2feSMugunthan V N static int cpsw_ndo_vlan_rx_kill_vid(struct net_device *ndev, 182380d5c368SPatrick McHardy __be16 proto, u16 vid) 18243b72c2feSMugunthan V N { 18253b72c2feSMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 1826649a1688SIvan Khoronzhuk struct cpsw_common *cpsw = priv->cpsw; 18273b72c2feSMugunthan V N int ret; 18283b72c2feSMugunthan V N 1829606f3993SIvan Khoronzhuk if (vid == cpsw->data.default_vlan) 18303b72c2feSMugunthan V N return 0; 18313b72c2feSMugunthan V N 183256e31bd8SIvan Khoronzhuk ret = pm_runtime_get_sync(cpsw->dev); 1833a6c5d14fSGrygorii Strashko if (ret < 0) { 183456e31bd8SIvan Khoronzhuk pm_runtime_put_noidle(cpsw->dev); 1835a6c5d14fSGrygorii Strashko return ret; 1836a6c5d14fSGrygorii Strashko } 1837a6c5d14fSGrygorii Strashko 1838606f3993SIvan Khoronzhuk if (cpsw->data.dual_emac) { 183902a54164SMugunthan V N int i; 184002a54164SMugunthan V N 1841606f3993SIvan Khoronzhuk for (i = 0; i < cpsw->data.slaves; i++) { 1842606f3993SIvan Khoronzhuk if (vid == cpsw->slaves[i].port_vlan) 184302a54164SMugunthan V N return -EINVAL; 184402a54164SMugunthan V N } 184502a54164SMugunthan V N } 184602a54164SMugunthan V N 18473b72c2feSMugunthan V N dev_info(priv->dev, "removing vlanid %d from vlan filter\n", vid); 18482a05a622SIvan Khoronzhuk ret = cpsw_ale_del_vlan(cpsw->ale, vid, 0); 18493b72c2feSMugunthan V N if (ret != 0) 18503b72c2feSMugunthan V N return ret; 18513b72c2feSMugunthan V N 18522a05a622SIvan Khoronzhuk ret = cpsw_ale_del_ucast(cpsw->ale, priv->mac_addr, 185361f1cef9SGrygorii Strashko HOST_PORT_NUM, ALE_VLAN, vid); 18543b72c2feSMugunthan V N if (ret != 0) 18553b72c2feSMugunthan V N return ret; 18563b72c2feSMugunthan V N 18572a05a622SIvan Khoronzhuk ret = cpsw_ale_del_mcast(cpsw->ale, priv->ndev->broadcast, 18583b72c2feSMugunthan V N 0, ALE_VLAN, vid); 185956e31bd8SIvan Khoronzhuk pm_runtime_put(cpsw->dev); 1860a6c5d14fSGrygorii Strashko return ret; 18613b72c2feSMugunthan V N } 18623b72c2feSMugunthan V N 186383fcad0cSIvan Khoronzhuk static int cpsw_ndo_set_tx_maxrate(struct net_device *ndev, int queue, u32 rate) 186483fcad0cSIvan Khoronzhuk { 186583fcad0cSIvan Khoronzhuk struct cpsw_priv *priv = netdev_priv(ndev); 186683fcad0cSIvan Khoronzhuk int tx_ch_num = ndev->real_num_tx_queues; 186783fcad0cSIvan Khoronzhuk u32 consumed_rate, min_rate, max_rate; 186883fcad0cSIvan Khoronzhuk struct cpsw_common *cpsw = priv->cpsw; 186983fcad0cSIvan Khoronzhuk struct cpsw_slave *slave; 187083fcad0cSIvan Khoronzhuk int ret, i, weight; 187183fcad0cSIvan Khoronzhuk int rlim_num = 0; 187283fcad0cSIvan Khoronzhuk u32 ch_rate; 187383fcad0cSIvan Khoronzhuk 187483fcad0cSIvan Khoronzhuk ch_rate = netdev_get_tx_queue(ndev, queue)->tx_maxrate; 187583fcad0cSIvan Khoronzhuk if (ch_rate == rate) 187683fcad0cSIvan Khoronzhuk return 0; 187783fcad0cSIvan Khoronzhuk 187883fcad0cSIvan Khoronzhuk if (cpsw->data.dual_emac) 187983fcad0cSIvan Khoronzhuk slave = &cpsw->slaves[priv->emac_port]; 188083fcad0cSIvan Khoronzhuk else 188183fcad0cSIvan Khoronzhuk slave = &cpsw->slaves[cpsw->data.active_slave]; 188283fcad0cSIvan Khoronzhuk max_rate = slave->phy->speed; 188383fcad0cSIvan Khoronzhuk 188483fcad0cSIvan Khoronzhuk consumed_rate = 0; 188583fcad0cSIvan Khoronzhuk for (i = 0; i < tx_ch_num; i++) { 188683fcad0cSIvan Khoronzhuk if (i == queue) 188783fcad0cSIvan Khoronzhuk ch_rate = rate; 188883fcad0cSIvan Khoronzhuk else 188983fcad0cSIvan Khoronzhuk ch_rate = netdev_get_tx_queue(ndev, i)->tx_maxrate; 189083fcad0cSIvan Khoronzhuk 189183fcad0cSIvan Khoronzhuk if (!ch_rate) 189283fcad0cSIvan Khoronzhuk continue; 189383fcad0cSIvan Khoronzhuk 189483fcad0cSIvan Khoronzhuk rlim_num++; 189583fcad0cSIvan Khoronzhuk consumed_rate += ch_rate; 189683fcad0cSIvan Khoronzhuk } 189783fcad0cSIvan Khoronzhuk 189883fcad0cSIvan Khoronzhuk if (consumed_rate > max_rate) 189983fcad0cSIvan Khoronzhuk dev_info(priv->dev, "The common rate shouldn't be more than %dMbps", 190083fcad0cSIvan Khoronzhuk max_rate); 190183fcad0cSIvan Khoronzhuk 190283fcad0cSIvan Khoronzhuk if (consumed_rate > max_rate) { 190383fcad0cSIvan Khoronzhuk if (max_rate == 10 && consumed_rate <= 100) { 190483fcad0cSIvan Khoronzhuk max_rate = 100; 190583fcad0cSIvan Khoronzhuk } else if (max_rate <= 100 && consumed_rate <= 1000) { 190683fcad0cSIvan Khoronzhuk max_rate = 1000; 190783fcad0cSIvan Khoronzhuk } else { 190883fcad0cSIvan Khoronzhuk dev_err(priv->dev, "The common rate cannot be more than %dMbps", 190983fcad0cSIvan Khoronzhuk max_rate); 191083fcad0cSIvan Khoronzhuk return -EINVAL; 191183fcad0cSIvan Khoronzhuk } 191283fcad0cSIvan Khoronzhuk } 191383fcad0cSIvan Khoronzhuk 191483fcad0cSIvan Khoronzhuk if (consumed_rate > max_rate) { 191583fcad0cSIvan Khoronzhuk dev_err(priv->dev, "The common rate cannot be more than %dMbps", 191683fcad0cSIvan Khoronzhuk max_rate); 191783fcad0cSIvan Khoronzhuk return -EINVAL; 191883fcad0cSIvan Khoronzhuk } 191983fcad0cSIvan Khoronzhuk 192083fcad0cSIvan Khoronzhuk rate *= 1000; 192183fcad0cSIvan Khoronzhuk min_rate = cpdma_chan_get_min_rate(cpsw->dma); 192283fcad0cSIvan Khoronzhuk if ((rate < min_rate && rate)) { 192383fcad0cSIvan Khoronzhuk dev_err(priv->dev, "The common rate cannot be less than %dMbps", 192483fcad0cSIvan Khoronzhuk min_rate); 192583fcad0cSIvan Khoronzhuk return -EINVAL; 192683fcad0cSIvan Khoronzhuk } 192783fcad0cSIvan Khoronzhuk 192883fcad0cSIvan Khoronzhuk ret = pm_runtime_get_sync(cpsw->dev); 192983fcad0cSIvan Khoronzhuk if (ret < 0) { 193083fcad0cSIvan Khoronzhuk pm_runtime_put_noidle(cpsw->dev); 193183fcad0cSIvan Khoronzhuk return ret; 193283fcad0cSIvan Khoronzhuk } 193383fcad0cSIvan Khoronzhuk 193483fcad0cSIvan Khoronzhuk if (rlim_num == tx_ch_num) 193583fcad0cSIvan Khoronzhuk max_rate = consumed_rate; 193683fcad0cSIvan Khoronzhuk 193783fcad0cSIvan Khoronzhuk weight = (rate * 100) / (max_rate * 1000); 193883fcad0cSIvan Khoronzhuk cpdma_chan_set_weight(cpsw->txch[queue], weight); 193983fcad0cSIvan Khoronzhuk 194083fcad0cSIvan Khoronzhuk ret = cpdma_chan_set_rate(cpsw->txch[queue], rate); 194183fcad0cSIvan Khoronzhuk pm_runtime_put(cpsw->dev); 194283fcad0cSIvan Khoronzhuk return ret; 194383fcad0cSIvan Khoronzhuk } 194483fcad0cSIvan Khoronzhuk 1945df828598SMugunthan V N static const struct net_device_ops cpsw_netdev_ops = { 1946df828598SMugunthan V N .ndo_open = cpsw_ndo_open, 1947df828598SMugunthan V N .ndo_stop = cpsw_ndo_stop, 1948df828598SMugunthan V N .ndo_start_xmit = cpsw_ndo_start_xmit, 1949dcfd8d58SMugunthan V N .ndo_set_mac_address = cpsw_ndo_set_mac_address, 19502e5b38abSRichard Cochran .ndo_do_ioctl = cpsw_ndo_ioctl, 1951df828598SMugunthan V N .ndo_validate_addr = eth_validate_addr, 1952df828598SMugunthan V N .ndo_tx_timeout = cpsw_ndo_tx_timeout, 19535c50a856SMugunthan V N .ndo_set_rx_mode = cpsw_ndo_set_rx_mode, 195483fcad0cSIvan Khoronzhuk .ndo_set_tx_maxrate = cpsw_ndo_set_tx_maxrate, 1955df828598SMugunthan V N #ifdef CONFIG_NET_POLL_CONTROLLER 1956df828598SMugunthan V N .ndo_poll_controller = cpsw_ndo_poll_controller, 1957df828598SMugunthan V N #endif 19583b72c2feSMugunthan V N .ndo_vlan_rx_add_vid = cpsw_ndo_vlan_rx_add_vid, 19593b72c2feSMugunthan V N .ndo_vlan_rx_kill_vid = cpsw_ndo_vlan_rx_kill_vid, 1960df828598SMugunthan V N }; 1961df828598SMugunthan V N 196252c4f0ecSMugunthan V N static int cpsw_get_regs_len(struct net_device *ndev) 196352c4f0ecSMugunthan V N { 1964606f3993SIvan Khoronzhuk struct cpsw_common *cpsw = ndev_to_cpsw(ndev); 196552c4f0ecSMugunthan V N 1966606f3993SIvan Khoronzhuk return cpsw->data.ale_entries * ALE_ENTRY_WORDS * sizeof(u32); 196752c4f0ecSMugunthan V N } 196852c4f0ecSMugunthan V N 196952c4f0ecSMugunthan V N static void cpsw_get_regs(struct net_device *ndev, 197052c4f0ecSMugunthan V N struct ethtool_regs *regs, void *p) 197152c4f0ecSMugunthan V N { 197252c4f0ecSMugunthan V N u32 *reg = p; 19732a05a622SIvan Khoronzhuk struct cpsw_common *cpsw = ndev_to_cpsw(ndev); 197452c4f0ecSMugunthan V N 197552c4f0ecSMugunthan V N /* update CPSW IP version */ 19762a05a622SIvan Khoronzhuk regs->version = cpsw->version; 197752c4f0ecSMugunthan V N 19782a05a622SIvan Khoronzhuk cpsw_ale_dump(cpsw->ale, reg); 197952c4f0ecSMugunthan V N } 198052c4f0ecSMugunthan V N 1981df828598SMugunthan V N static void cpsw_get_drvinfo(struct net_device *ndev, 1982df828598SMugunthan V N struct ethtool_drvinfo *info) 1983df828598SMugunthan V N { 1984649a1688SIvan Khoronzhuk struct cpsw_common *cpsw = ndev_to_cpsw(ndev); 198556e31bd8SIvan Khoronzhuk struct platform_device *pdev = to_platform_device(cpsw->dev); 19867826d43fSJiri Pirko 198752c4f0ecSMugunthan V N strlcpy(info->driver, "cpsw", sizeof(info->driver)); 19887826d43fSJiri Pirko strlcpy(info->version, "1.0", sizeof(info->version)); 198956e31bd8SIvan Khoronzhuk strlcpy(info->bus_info, pdev->name, sizeof(info->bus_info)); 1990df828598SMugunthan V N } 1991df828598SMugunthan V N 1992df828598SMugunthan V N static u32 cpsw_get_msglevel(struct net_device *ndev) 1993df828598SMugunthan V N { 1994df828598SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 1995df828598SMugunthan V N return priv->msg_enable; 1996df828598SMugunthan V N } 1997df828598SMugunthan V N 1998df828598SMugunthan V N static void cpsw_set_msglevel(struct net_device *ndev, u32 value) 1999df828598SMugunthan V N { 2000df828598SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 2001df828598SMugunthan V N priv->msg_enable = value; 2002df828598SMugunthan V N } 2003df828598SMugunthan V N 20042e5b38abSRichard Cochran static int cpsw_get_ts_info(struct net_device *ndev, 20052e5b38abSRichard Cochran struct ethtool_ts_info *info) 20062e5b38abSRichard Cochran { 20072e5b38abSRichard Cochran #ifdef CONFIG_TI_CPTS 20082a05a622SIvan Khoronzhuk struct cpsw_common *cpsw = ndev_to_cpsw(ndev); 20092e5b38abSRichard Cochran 20102e5b38abSRichard Cochran info->so_timestamping = 20112e5b38abSRichard Cochran SOF_TIMESTAMPING_TX_HARDWARE | 20122e5b38abSRichard Cochran SOF_TIMESTAMPING_TX_SOFTWARE | 20132e5b38abSRichard Cochran SOF_TIMESTAMPING_RX_HARDWARE | 20142e5b38abSRichard Cochran SOF_TIMESTAMPING_RX_SOFTWARE | 20152e5b38abSRichard Cochran SOF_TIMESTAMPING_SOFTWARE | 20162e5b38abSRichard Cochran SOF_TIMESTAMPING_RAW_HARDWARE; 20172a05a622SIvan Khoronzhuk info->phc_index = cpsw->cpts->phc_index; 20182e5b38abSRichard Cochran info->tx_types = 20192e5b38abSRichard Cochran (1 << HWTSTAMP_TX_OFF) | 20202e5b38abSRichard Cochran (1 << HWTSTAMP_TX_ON); 20212e5b38abSRichard Cochran info->rx_filters = 20222e5b38abSRichard Cochran (1 << HWTSTAMP_FILTER_NONE) | 20232e5b38abSRichard Cochran (1 << HWTSTAMP_FILTER_PTP_V2_EVENT); 20242e5b38abSRichard Cochran #else 20252e5b38abSRichard Cochran info->so_timestamping = 20262e5b38abSRichard Cochran SOF_TIMESTAMPING_TX_SOFTWARE | 20272e5b38abSRichard Cochran SOF_TIMESTAMPING_RX_SOFTWARE | 20282e5b38abSRichard Cochran SOF_TIMESTAMPING_SOFTWARE; 20292e5b38abSRichard Cochran info->phc_index = -1; 20302e5b38abSRichard Cochran info->tx_types = 0; 20312e5b38abSRichard Cochran info->rx_filters = 0; 20322e5b38abSRichard Cochran #endif 20332e5b38abSRichard Cochran return 0; 20342e5b38abSRichard Cochran } 20352e5b38abSRichard Cochran 20362479876dSPhilippe Reynes static int cpsw_get_link_ksettings(struct net_device *ndev, 20372479876dSPhilippe Reynes struct ethtool_link_ksettings *ecmd) 2038d3bb9c58SMugunthan V N { 2039d3bb9c58SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 2040606f3993SIvan Khoronzhuk struct cpsw_common *cpsw = priv->cpsw; 2041606f3993SIvan Khoronzhuk int slave_no = cpsw_slave_index(cpsw, priv); 2042d3bb9c58SMugunthan V N 2043606f3993SIvan Khoronzhuk if (cpsw->slaves[slave_no].phy) 20442479876dSPhilippe Reynes return phy_ethtool_ksettings_get(cpsw->slaves[slave_no].phy, 20452479876dSPhilippe Reynes ecmd); 2046d3bb9c58SMugunthan V N else 2047d3bb9c58SMugunthan V N return -EOPNOTSUPP; 2048d3bb9c58SMugunthan V N } 2049d3bb9c58SMugunthan V N 20502479876dSPhilippe Reynes static int cpsw_set_link_ksettings(struct net_device *ndev, 20512479876dSPhilippe Reynes const struct ethtool_link_ksettings *ecmd) 2052d3bb9c58SMugunthan V N { 2053d3bb9c58SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 2054606f3993SIvan Khoronzhuk struct cpsw_common *cpsw = priv->cpsw; 2055606f3993SIvan Khoronzhuk int slave_no = cpsw_slave_index(cpsw, priv); 2056d3bb9c58SMugunthan V N 2057606f3993SIvan Khoronzhuk if (cpsw->slaves[slave_no].phy) 20582479876dSPhilippe Reynes return phy_ethtool_ksettings_set(cpsw->slaves[slave_no].phy, 20592479876dSPhilippe Reynes ecmd); 2060d3bb9c58SMugunthan V N else 2061d3bb9c58SMugunthan V N return -EOPNOTSUPP; 2062d3bb9c58SMugunthan V N } 2063d3bb9c58SMugunthan V N 2064d8a64420SMatus Ujhelyi static void cpsw_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol) 2065d8a64420SMatus Ujhelyi { 2066d8a64420SMatus Ujhelyi struct cpsw_priv *priv = netdev_priv(ndev); 2067606f3993SIvan Khoronzhuk struct cpsw_common *cpsw = priv->cpsw; 2068606f3993SIvan Khoronzhuk int slave_no = cpsw_slave_index(cpsw, priv); 2069d8a64420SMatus Ujhelyi 2070d8a64420SMatus Ujhelyi wol->supported = 0; 2071d8a64420SMatus Ujhelyi wol->wolopts = 0; 2072d8a64420SMatus Ujhelyi 2073606f3993SIvan Khoronzhuk if (cpsw->slaves[slave_no].phy) 2074606f3993SIvan Khoronzhuk phy_ethtool_get_wol(cpsw->slaves[slave_no].phy, wol); 2075d8a64420SMatus Ujhelyi } 2076d8a64420SMatus Ujhelyi 2077d8a64420SMatus Ujhelyi static int cpsw_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol) 2078d8a64420SMatus Ujhelyi { 2079d8a64420SMatus Ujhelyi struct cpsw_priv *priv = netdev_priv(ndev); 2080606f3993SIvan Khoronzhuk struct cpsw_common *cpsw = priv->cpsw; 2081606f3993SIvan Khoronzhuk int slave_no = cpsw_slave_index(cpsw, priv); 2082d8a64420SMatus Ujhelyi 2083606f3993SIvan Khoronzhuk if (cpsw->slaves[slave_no].phy) 2084606f3993SIvan Khoronzhuk return phy_ethtool_set_wol(cpsw->slaves[slave_no].phy, wol); 2085d8a64420SMatus Ujhelyi else 2086d8a64420SMatus Ujhelyi return -EOPNOTSUPP; 2087d8a64420SMatus Ujhelyi } 2088d8a64420SMatus Ujhelyi 20891923d6e4SMugunthan V N static void cpsw_get_pauseparam(struct net_device *ndev, 20901923d6e4SMugunthan V N struct ethtool_pauseparam *pause) 20911923d6e4SMugunthan V N { 20921923d6e4SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 20931923d6e4SMugunthan V N 20941923d6e4SMugunthan V N pause->autoneg = AUTONEG_DISABLE; 20951923d6e4SMugunthan V N pause->rx_pause = priv->rx_pause ? true : false; 20961923d6e4SMugunthan V N pause->tx_pause = priv->tx_pause ? true : false; 20971923d6e4SMugunthan V N } 20981923d6e4SMugunthan V N 20991923d6e4SMugunthan V N static int cpsw_set_pauseparam(struct net_device *ndev, 21001923d6e4SMugunthan V N struct ethtool_pauseparam *pause) 21011923d6e4SMugunthan V N { 21021923d6e4SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 21031923d6e4SMugunthan V N bool link; 21041923d6e4SMugunthan V N 21051923d6e4SMugunthan V N priv->rx_pause = pause->rx_pause ? true : false; 21061923d6e4SMugunthan V N priv->tx_pause = pause->tx_pause ? true : false; 21071923d6e4SMugunthan V N 21081923d6e4SMugunthan V N for_each_slave(priv, _cpsw_adjust_link, priv, &link); 21091923d6e4SMugunthan V N return 0; 21101923d6e4SMugunthan V N } 21111923d6e4SMugunthan V N 21127898b1daSGrygorii Strashko static int cpsw_ethtool_op_begin(struct net_device *ndev) 21137898b1daSGrygorii Strashko { 21147898b1daSGrygorii Strashko struct cpsw_priv *priv = netdev_priv(ndev); 2115649a1688SIvan Khoronzhuk struct cpsw_common *cpsw = priv->cpsw; 21167898b1daSGrygorii Strashko int ret; 21177898b1daSGrygorii Strashko 211856e31bd8SIvan Khoronzhuk ret = pm_runtime_get_sync(cpsw->dev); 21197898b1daSGrygorii Strashko if (ret < 0) { 21207898b1daSGrygorii Strashko cpsw_err(priv, drv, "ethtool begin failed %d\n", ret); 212156e31bd8SIvan Khoronzhuk pm_runtime_put_noidle(cpsw->dev); 21227898b1daSGrygorii Strashko } 21237898b1daSGrygorii Strashko 21247898b1daSGrygorii Strashko return ret; 21257898b1daSGrygorii Strashko } 21267898b1daSGrygorii Strashko 21277898b1daSGrygorii Strashko static void cpsw_ethtool_op_complete(struct net_device *ndev) 21287898b1daSGrygorii Strashko { 21297898b1daSGrygorii Strashko struct cpsw_priv *priv = netdev_priv(ndev); 21307898b1daSGrygorii Strashko int ret; 21317898b1daSGrygorii Strashko 213256e31bd8SIvan Khoronzhuk ret = pm_runtime_put(priv->cpsw->dev); 21337898b1daSGrygorii Strashko if (ret < 0) 21347898b1daSGrygorii Strashko cpsw_err(priv, drv, "ethtool complete failed %d\n", ret); 21357898b1daSGrygorii Strashko } 21367898b1daSGrygorii Strashko 2137ce52c744SIvan Khoronzhuk static void cpsw_get_channels(struct net_device *ndev, 2138ce52c744SIvan Khoronzhuk struct ethtool_channels *ch) 2139ce52c744SIvan Khoronzhuk { 2140ce52c744SIvan Khoronzhuk struct cpsw_common *cpsw = ndev_to_cpsw(ndev); 2141ce52c744SIvan Khoronzhuk 2142ce52c744SIvan Khoronzhuk ch->max_combined = 0; 2143ce52c744SIvan Khoronzhuk ch->max_rx = CPSW_MAX_QUEUES; 2144ce52c744SIvan Khoronzhuk ch->max_tx = CPSW_MAX_QUEUES; 2145ce52c744SIvan Khoronzhuk ch->max_other = 0; 2146ce52c744SIvan Khoronzhuk ch->other_count = 0; 2147ce52c744SIvan Khoronzhuk ch->rx_count = cpsw->rx_ch_num; 2148ce52c744SIvan Khoronzhuk ch->tx_count = cpsw->tx_ch_num; 2149ce52c744SIvan Khoronzhuk ch->combined_count = 0; 2150ce52c744SIvan Khoronzhuk } 2151ce52c744SIvan Khoronzhuk 2152ce52c744SIvan Khoronzhuk static int cpsw_check_ch_settings(struct cpsw_common *cpsw, 2153ce52c744SIvan Khoronzhuk struct ethtool_channels *ch) 2154ce52c744SIvan Khoronzhuk { 2155ce52c744SIvan Khoronzhuk if (ch->combined_count) 2156ce52c744SIvan Khoronzhuk return -EINVAL; 2157ce52c744SIvan Khoronzhuk 2158ce52c744SIvan Khoronzhuk /* verify we have at least one channel in each direction */ 2159ce52c744SIvan Khoronzhuk if (!ch->rx_count || !ch->tx_count) 2160ce52c744SIvan Khoronzhuk return -EINVAL; 2161ce52c744SIvan Khoronzhuk 2162ce52c744SIvan Khoronzhuk if (ch->rx_count > cpsw->data.channels || 2163ce52c744SIvan Khoronzhuk ch->tx_count > cpsw->data.channels) 2164ce52c744SIvan Khoronzhuk return -EINVAL; 2165ce52c744SIvan Khoronzhuk 2166ce52c744SIvan Khoronzhuk return 0; 2167ce52c744SIvan Khoronzhuk } 2168ce52c744SIvan Khoronzhuk 2169ce52c744SIvan Khoronzhuk static int cpsw_update_channels_res(struct cpsw_priv *priv, int ch_num, int rx) 2170ce52c744SIvan Khoronzhuk { 2171ce52c744SIvan Khoronzhuk int (*poll)(struct napi_struct *, int); 2172ce52c744SIvan Khoronzhuk struct cpsw_common *cpsw = priv->cpsw; 2173ce52c744SIvan Khoronzhuk void (*handler)(void *, int, int); 217483fcad0cSIvan Khoronzhuk struct netdev_queue *queue; 2175ce52c744SIvan Khoronzhuk struct cpdma_chan **chan; 2176ce52c744SIvan Khoronzhuk int ret, *ch; 2177ce52c744SIvan Khoronzhuk 2178ce52c744SIvan Khoronzhuk if (rx) { 2179ce52c744SIvan Khoronzhuk ch = &cpsw->rx_ch_num; 2180ce52c744SIvan Khoronzhuk chan = cpsw->rxch; 2181ce52c744SIvan Khoronzhuk handler = cpsw_rx_handler; 2182ce52c744SIvan Khoronzhuk poll = cpsw_rx_poll; 2183ce52c744SIvan Khoronzhuk } else { 2184ce52c744SIvan Khoronzhuk ch = &cpsw->tx_ch_num; 2185ce52c744SIvan Khoronzhuk chan = cpsw->txch; 2186ce52c744SIvan Khoronzhuk handler = cpsw_tx_handler; 2187ce52c744SIvan Khoronzhuk poll = cpsw_tx_poll; 2188ce52c744SIvan Khoronzhuk } 2189ce52c744SIvan Khoronzhuk 2190ce52c744SIvan Khoronzhuk while (*ch < ch_num) { 2191ce52c744SIvan Khoronzhuk chan[*ch] = cpdma_chan_create(cpsw->dma, *ch, handler, rx); 219283fcad0cSIvan Khoronzhuk queue = netdev_get_tx_queue(priv->ndev, *ch); 219383fcad0cSIvan Khoronzhuk queue->tx_maxrate = 0; 2194ce52c744SIvan Khoronzhuk 2195ce52c744SIvan Khoronzhuk if (IS_ERR(chan[*ch])) 2196ce52c744SIvan Khoronzhuk return PTR_ERR(chan[*ch]); 2197ce52c744SIvan Khoronzhuk 2198ce52c744SIvan Khoronzhuk if (!chan[*ch]) 2199ce52c744SIvan Khoronzhuk return -EINVAL; 2200ce52c744SIvan Khoronzhuk 2201ce52c744SIvan Khoronzhuk cpsw_info(priv, ifup, "created new %d %s channel\n", *ch, 2202ce52c744SIvan Khoronzhuk (rx ? "rx" : "tx")); 2203ce52c744SIvan Khoronzhuk (*ch)++; 2204ce52c744SIvan Khoronzhuk } 2205ce52c744SIvan Khoronzhuk 2206ce52c744SIvan Khoronzhuk while (*ch > ch_num) { 2207ce52c744SIvan Khoronzhuk (*ch)--; 2208ce52c744SIvan Khoronzhuk 2209ce52c744SIvan Khoronzhuk ret = cpdma_chan_destroy(chan[*ch]); 2210ce52c744SIvan Khoronzhuk if (ret) 2211ce52c744SIvan Khoronzhuk return ret; 2212ce52c744SIvan Khoronzhuk 2213ce52c744SIvan Khoronzhuk cpsw_info(priv, ifup, "destroyed %d %s channel\n", *ch, 2214ce52c744SIvan Khoronzhuk (rx ? "rx" : "tx")); 2215ce52c744SIvan Khoronzhuk } 2216ce52c744SIvan Khoronzhuk 2217ce52c744SIvan Khoronzhuk return 0; 2218ce52c744SIvan Khoronzhuk } 2219ce52c744SIvan Khoronzhuk 2220ce52c744SIvan Khoronzhuk static int cpsw_update_channels(struct cpsw_priv *priv, 2221ce52c744SIvan Khoronzhuk struct ethtool_channels *ch) 2222ce52c744SIvan Khoronzhuk { 2223ce52c744SIvan Khoronzhuk int ret; 2224ce52c744SIvan Khoronzhuk 2225ce52c744SIvan Khoronzhuk ret = cpsw_update_channels_res(priv, ch->rx_count, 1); 2226ce52c744SIvan Khoronzhuk if (ret) 2227ce52c744SIvan Khoronzhuk return ret; 2228ce52c744SIvan Khoronzhuk 2229ce52c744SIvan Khoronzhuk ret = cpsw_update_channels_res(priv, ch->tx_count, 0); 2230ce52c744SIvan Khoronzhuk if (ret) 2231ce52c744SIvan Khoronzhuk return ret; 2232ce52c744SIvan Khoronzhuk 2233ce52c744SIvan Khoronzhuk return 0; 2234ce52c744SIvan Khoronzhuk } 2235ce52c744SIvan Khoronzhuk 2236ce52c744SIvan Khoronzhuk static int cpsw_set_channels(struct net_device *ndev, 2237ce52c744SIvan Khoronzhuk struct ethtool_channels *chs) 2238ce52c744SIvan Khoronzhuk { 2239ce52c744SIvan Khoronzhuk struct cpsw_priv *priv = netdev_priv(ndev); 2240ce52c744SIvan Khoronzhuk struct cpsw_common *cpsw = priv->cpsw; 2241ce52c744SIvan Khoronzhuk struct cpsw_slave *slave; 2242ce52c744SIvan Khoronzhuk int i, ret; 2243ce52c744SIvan Khoronzhuk 2244ce52c744SIvan Khoronzhuk ret = cpsw_check_ch_settings(cpsw, chs); 2245ce52c744SIvan Khoronzhuk if (ret < 0) 2246ce52c744SIvan Khoronzhuk return ret; 2247ce52c744SIvan Khoronzhuk 2248ce52c744SIvan Khoronzhuk /* Disable NAPI scheduling */ 2249ce52c744SIvan Khoronzhuk cpsw_intr_disable(cpsw); 2250ce52c744SIvan Khoronzhuk 2251ce52c744SIvan Khoronzhuk /* Stop all transmit queues for every network device. 2252ce52c744SIvan Khoronzhuk * Disable re-using rx descriptors with dormant_on. 2253ce52c744SIvan Khoronzhuk */ 2254ce52c744SIvan Khoronzhuk for (i = cpsw->data.slaves, slave = cpsw->slaves; i; i--, slave++) { 2255ce52c744SIvan Khoronzhuk if (!(slave->ndev && netif_running(slave->ndev))) 2256ce52c744SIvan Khoronzhuk continue; 2257ce52c744SIvan Khoronzhuk 2258ce52c744SIvan Khoronzhuk netif_tx_stop_all_queues(slave->ndev); 2259ce52c744SIvan Khoronzhuk netif_dormant_on(slave->ndev); 2260ce52c744SIvan Khoronzhuk } 2261ce52c744SIvan Khoronzhuk 2262ce52c744SIvan Khoronzhuk /* Handle rest of tx packets and stop cpdma channels */ 2263ce52c744SIvan Khoronzhuk cpdma_ctlr_stop(cpsw->dma); 2264ce52c744SIvan Khoronzhuk ret = cpsw_update_channels(priv, chs); 2265ce52c744SIvan Khoronzhuk if (ret) 2266ce52c744SIvan Khoronzhuk goto err; 2267ce52c744SIvan Khoronzhuk 2268ce52c744SIvan Khoronzhuk for (i = cpsw->data.slaves, slave = cpsw->slaves; i; i--, slave++) { 2269ce52c744SIvan Khoronzhuk if (!(slave->ndev && netif_running(slave->ndev))) 2270ce52c744SIvan Khoronzhuk continue; 2271ce52c744SIvan Khoronzhuk 2272ce52c744SIvan Khoronzhuk /* Inform stack about new count of queues */ 2273ce52c744SIvan Khoronzhuk ret = netif_set_real_num_tx_queues(slave->ndev, 2274ce52c744SIvan Khoronzhuk cpsw->tx_ch_num); 2275ce52c744SIvan Khoronzhuk if (ret) { 2276ce52c744SIvan Khoronzhuk dev_err(priv->dev, "cannot set real number of tx queues\n"); 2277ce52c744SIvan Khoronzhuk goto err; 2278ce52c744SIvan Khoronzhuk } 2279ce52c744SIvan Khoronzhuk 2280ce52c744SIvan Khoronzhuk ret = netif_set_real_num_rx_queues(slave->ndev, 2281ce52c744SIvan Khoronzhuk cpsw->rx_ch_num); 2282ce52c744SIvan Khoronzhuk if (ret) { 2283ce52c744SIvan Khoronzhuk dev_err(priv->dev, "cannot set real number of rx queues\n"); 2284ce52c744SIvan Khoronzhuk goto err; 2285ce52c744SIvan Khoronzhuk } 2286ce52c744SIvan Khoronzhuk 2287ce52c744SIvan Khoronzhuk /* Enable rx packets handling */ 2288ce52c744SIvan Khoronzhuk netif_dormant_off(slave->ndev); 2289ce52c744SIvan Khoronzhuk } 2290ce52c744SIvan Khoronzhuk 2291ce52c744SIvan Khoronzhuk if (cpsw_common_res_usage_state(cpsw)) { 2292e19ac157SWei Yongjun ret = cpsw_fill_rx_channels(priv); 2293e19ac157SWei Yongjun if (ret) 2294ce52c744SIvan Khoronzhuk goto err; 2295ce52c744SIvan Khoronzhuk 2296ce52c744SIvan Khoronzhuk /* After this receive is started */ 2297ce52c744SIvan Khoronzhuk cpdma_ctlr_start(cpsw->dma); 2298ce52c744SIvan Khoronzhuk cpsw_intr_enable(cpsw); 2299ce52c744SIvan Khoronzhuk } 2300ce52c744SIvan Khoronzhuk 2301ce52c744SIvan Khoronzhuk /* Resume transmit for every affected interface */ 2302ce52c744SIvan Khoronzhuk for (i = cpsw->data.slaves, slave = cpsw->slaves; i; i--, slave++) { 2303ce52c744SIvan Khoronzhuk if (!(slave->ndev && netif_running(slave->ndev))) 2304ce52c744SIvan Khoronzhuk continue; 2305ce52c744SIvan Khoronzhuk netif_tx_start_all_queues(slave->ndev); 2306ce52c744SIvan Khoronzhuk } 2307ce52c744SIvan Khoronzhuk return 0; 2308ce52c744SIvan Khoronzhuk err: 2309ce52c744SIvan Khoronzhuk dev_err(priv->dev, "cannot update channels number, closing device\n"); 2310ce52c744SIvan Khoronzhuk dev_close(ndev); 2311ce52c744SIvan Khoronzhuk return ret; 2312ce52c744SIvan Khoronzhuk } 2313ce52c744SIvan Khoronzhuk 2314a0909949SYegor Yefremov static int cpsw_get_eee(struct net_device *ndev, struct ethtool_eee *edata) 2315a0909949SYegor Yefremov { 2316a0909949SYegor Yefremov struct cpsw_priv *priv = netdev_priv(ndev); 2317a0909949SYegor Yefremov struct cpsw_common *cpsw = priv->cpsw; 2318a0909949SYegor Yefremov int slave_no = cpsw_slave_index(cpsw, priv); 2319a0909949SYegor Yefremov 2320a0909949SYegor Yefremov if (cpsw->slaves[slave_no].phy) 2321a0909949SYegor Yefremov return phy_ethtool_get_eee(cpsw->slaves[slave_no].phy, edata); 2322a0909949SYegor Yefremov else 2323a0909949SYegor Yefremov return -EOPNOTSUPP; 2324a0909949SYegor Yefremov } 2325a0909949SYegor Yefremov 2326a0909949SYegor Yefremov static int cpsw_set_eee(struct net_device *ndev, struct ethtool_eee *edata) 2327a0909949SYegor Yefremov { 2328a0909949SYegor Yefremov struct cpsw_priv *priv = netdev_priv(ndev); 2329a0909949SYegor Yefremov struct cpsw_common *cpsw = priv->cpsw; 2330a0909949SYegor Yefremov int slave_no = cpsw_slave_index(cpsw, priv); 2331a0909949SYegor Yefremov 2332a0909949SYegor Yefremov if (cpsw->slaves[slave_no].phy) 2333a0909949SYegor Yefremov return phy_ethtool_set_eee(cpsw->slaves[slave_no].phy, edata); 2334a0909949SYegor Yefremov else 2335a0909949SYegor Yefremov return -EOPNOTSUPP; 2336a0909949SYegor Yefremov } 2337a0909949SYegor Yefremov 23386bb10c2bSYegor Yefremov static int cpsw_nway_reset(struct net_device *ndev) 23396bb10c2bSYegor Yefremov { 23406bb10c2bSYegor Yefremov struct cpsw_priv *priv = netdev_priv(ndev); 23416bb10c2bSYegor Yefremov struct cpsw_common *cpsw = priv->cpsw; 23426bb10c2bSYegor Yefremov int slave_no = cpsw_slave_index(cpsw, priv); 23436bb10c2bSYegor Yefremov 23446bb10c2bSYegor Yefremov if (cpsw->slaves[slave_no].phy) 23456bb10c2bSYegor Yefremov return genphy_restart_aneg(cpsw->slaves[slave_no].phy); 23466bb10c2bSYegor Yefremov else 23476bb10c2bSYegor Yefremov return -EOPNOTSUPP; 23486bb10c2bSYegor Yefremov } 23496bb10c2bSYegor Yefremov 2350df828598SMugunthan V N static const struct ethtool_ops cpsw_ethtool_ops = { 2351df828598SMugunthan V N .get_drvinfo = cpsw_get_drvinfo, 2352df828598SMugunthan V N .get_msglevel = cpsw_get_msglevel, 2353df828598SMugunthan V N .set_msglevel = cpsw_set_msglevel, 2354df828598SMugunthan V N .get_link = ethtool_op_get_link, 23552e5b38abSRichard Cochran .get_ts_info = cpsw_get_ts_info, 2356ff5b8ef2SMugunthan V N .get_coalesce = cpsw_get_coalesce, 2357ff5b8ef2SMugunthan V N .set_coalesce = cpsw_set_coalesce, 2358d9718546SMugunthan V N .get_sset_count = cpsw_get_sset_count, 2359d9718546SMugunthan V N .get_strings = cpsw_get_strings, 2360d9718546SMugunthan V N .get_ethtool_stats = cpsw_get_ethtool_stats, 23611923d6e4SMugunthan V N .get_pauseparam = cpsw_get_pauseparam, 23621923d6e4SMugunthan V N .set_pauseparam = cpsw_set_pauseparam, 2363d8a64420SMatus Ujhelyi .get_wol = cpsw_get_wol, 2364d8a64420SMatus Ujhelyi .set_wol = cpsw_set_wol, 236552c4f0ecSMugunthan V N .get_regs_len = cpsw_get_regs_len, 236652c4f0ecSMugunthan V N .get_regs = cpsw_get_regs, 23677898b1daSGrygorii Strashko .begin = cpsw_ethtool_op_begin, 23687898b1daSGrygorii Strashko .complete = cpsw_ethtool_op_complete, 2369ce52c744SIvan Khoronzhuk .get_channels = cpsw_get_channels, 2370ce52c744SIvan Khoronzhuk .set_channels = cpsw_set_channels, 23712479876dSPhilippe Reynes .get_link_ksettings = cpsw_get_link_ksettings, 23722479876dSPhilippe Reynes .set_link_ksettings = cpsw_set_link_ksettings, 2373a0909949SYegor Yefremov .get_eee = cpsw_get_eee, 2374a0909949SYegor Yefremov .set_eee = cpsw_set_eee, 23756bb10c2bSYegor Yefremov .nway_reset = cpsw_nway_reset, 2376df828598SMugunthan V N }; 2377df828598SMugunthan V N 2378606f3993SIvan Khoronzhuk static void cpsw_slave_init(struct cpsw_slave *slave, struct cpsw_common *cpsw, 2379549985eeSRichard Cochran u32 slave_reg_ofs, u32 sliver_reg_ofs) 2380df828598SMugunthan V N { 23815d8d0d4dSIvan Khoronzhuk void __iomem *regs = cpsw->regs; 2382df828598SMugunthan V N int slave_num = slave->slave_num; 2383606f3993SIvan Khoronzhuk struct cpsw_slave_data *data = cpsw->data.slave_data + slave_num; 2384df828598SMugunthan V N 2385df828598SMugunthan V N slave->data = data; 2386549985eeSRichard Cochran slave->regs = regs + slave_reg_ofs; 2387549985eeSRichard Cochran slave->sliver = regs + sliver_reg_ofs; 2388d9ba8f9eSMugunthan V N slave->port_vlan = data->dual_emac_res_vlan; 2389df828598SMugunthan V N } 2390df828598SMugunthan V N 2391552165bcSDavid Rivshin static int cpsw_probe_dt(struct cpsw_platform_data *data, 23922eb32b0aSMugunthan V N struct platform_device *pdev) 23932eb32b0aSMugunthan V N { 23942eb32b0aSMugunthan V N struct device_node *node = pdev->dev.of_node; 23952eb32b0aSMugunthan V N struct device_node *slave_node; 23962eb32b0aSMugunthan V N int i = 0, ret; 23972eb32b0aSMugunthan V N u32 prop; 23982eb32b0aSMugunthan V N 23992eb32b0aSMugunthan V N if (!node) 24002eb32b0aSMugunthan V N return -EINVAL; 24012eb32b0aSMugunthan V N 24022eb32b0aSMugunthan V N if (of_property_read_u32(node, "slaves", &prop)) { 240388c99ff6SGeorge Cherian dev_err(&pdev->dev, "Missing slaves property in the DT.\n"); 24042eb32b0aSMugunthan V N return -EINVAL; 24052eb32b0aSMugunthan V N } 24062eb32b0aSMugunthan V N data->slaves = prop; 24072eb32b0aSMugunthan V N 2408e86ac13bSMugunthan V N if (of_property_read_u32(node, "active_slave", &prop)) { 240988c99ff6SGeorge Cherian dev_err(&pdev->dev, "Missing active_slave property in the DT.\n"); 2410aa1a15e2SDaniel Mack return -EINVAL; 241178ca0b28SRichard Cochran } 2412e86ac13bSMugunthan V N data->active_slave = prop; 241378ca0b28SRichard Cochran 241400ab94eeSRichard Cochran if (of_property_read_u32(node, "cpts_clock_mult", &prop)) { 241588c99ff6SGeorge Cherian dev_err(&pdev->dev, "Missing cpts_clock_mult property in the DT.\n"); 2416aa1a15e2SDaniel Mack return -EINVAL; 241700ab94eeSRichard Cochran } 241800ab94eeSRichard Cochran data->cpts_clock_mult = prop; 241900ab94eeSRichard Cochran 242000ab94eeSRichard Cochran if (of_property_read_u32(node, "cpts_clock_shift", &prop)) { 242188c99ff6SGeorge Cherian dev_err(&pdev->dev, "Missing cpts_clock_shift property in the DT.\n"); 2422aa1a15e2SDaniel Mack return -EINVAL; 242300ab94eeSRichard Cochran } 242400ab94eeSRichard Cochran data->cpts_clock_shift = prop; 242500ab94eeSRichard Cochran 2426aa1a15e2SDaniel Mack data->slave_data = devm_kzalloc(&pdev->dev, data->slaves 2427aa1a15e2SDaniel Mack * sizeof(struct cpsw_slave_data), 2428b2adaca9SJoe Perches GFP_KERNEL); 2429b2adaca9SJoe Perches if (!data->slave_data) 2430aa1a15e2SDaniel Mack return -ENOMEM; 24312eb32b0aSMugunthan V N 24322eb32b0aSMugunthan V N if (of_property_read_u32(node, "cpdma_channels", &prop)) { 243388c99ff6SGeorge Cherian dev_err(&pdev->dev, "Missing cpdma_channels property in the DT.\n"); 2434aa1a15e2SDaniel Mack return -EINVAL; 24352eb32b0aSMugunthan V N } 24362eb32b0aSMugunthan V N data->channels = prop; 24372eb32b0aSMugunthan V N 24382eb32b0aSMugunthan V N if (of_property_read_u32(node, "ale_entries", &prop)) { 243988c99ff6SGeorge Cherian dev_err(&pdev->dev, "Missing ale_entries property in the DT.\n"); 2440aa1a15e2SDaniel Mack return -EINVAL; 24412eb32b0aSMugunthan V N } 24422eb32b0aSMugunthan V N data->ale_entries = prop; 24432eb32b0aSMugunthan V N 24442eb32b0aSMugunthan V N if (of_property_read_u32(node, "bd_ram_size", &prop)) { 244588c99ff6SGeorge Cherian dev_err(&pdev->dev, "Missing bd_ram_size property in the DT.\n"); 2446aa1a15e2SDaniel Mack return -EINVAL; 24472eb32b0aSMugunthan V N } 24482eb32b0aSMugunthan V N data->bd_ram_size = prop; 24492eb32b0aSMugunthan V N 24502eb32b0aSMugunthan V N if (of_property_read_u32(node, "mac_control", &prop)) { 245188c99ff6SGeorge Cherian dev_err(&pdev->dev, "Missing mac_control property in the DT.\n"); 2452aa1a15e2SDaniel Mack return -EINVAL; 24532eb32b0aSMugunthan V N } 24542eb32b0aSMugunthan V N data->mac_control = prop; 24552eb32b0aSMugunthan V N 2456281abd96SMarkus Pargmann if (of_property_read_bool(node, "dual_emac")) 2457281abd96SMarkus Pargmann data->dual_emac = 1; 2458d9ba8f9eSMugunthan V N 24591fb19aa7SVaibhav Hiremath /* 24601fb19aa7SVaibhav Hiremath * Populate all the child nodes here... 24611fb19aa7SVaibhav Hiremath */ 24621fb19aa7SVaibhav Hiremath ret = of_platform_populate(node, NULL, NULL, &pdev->dev); 24631fb19aa7SVaibhav Hiremath /* We do not want to force this, as in some cases may not have child */ 24641fb19aa7SVaibhav Hiremath if (ret) 246588c99ff6SGeorge Cherian dev_warn(&pdev->dev, "Doesn't have any child node\n"); 24661fb19aa7SVaibhav Hiremath 24678658aaf2SBen Hutchings for_each_available_child_of_node(node, slave_node) { 2468549985eeSRichard Cochran struct cpsw_slave_data *slave_data = data->slave_data + i; 2469549985eeSRichard Cochran const void *mac_addr = NULL; 2470549985eeSRichard Cochran int lenp; 2471549985eeSRichard Cochran const __be32 *parp; 2472549985eeSRichard Cochran 2473f468b10eSMarkus Pargmann /* This is no slave child node, continue */ 2474f468b10eSMarkus Pargmann if (strcmp(slave_node->name, "slave")) 2475f468b10eSMarkus Pargmann continue; 2476f468b10eSMarkus Pargmann 2477552165bcSDavid Rivshin slave_data->phy_node = of_parse_phandle(slave_node, 2478552165bcSDavid Rivshin "phy-handle", 0); 2479f1eea5c1SDavid Rivshin parp = of_get_property(slave_node, "phy_id", &lenp); 2480ae092b5bSDavid Rivshin if (slave_data->phy_node) { 2481ae092b5bSDavid Rivshin dev_dbg(&pdev->dev, 2482ae092b5bSDavid Rivshin "slave[%d] using phy-handle=\"%s\"\n", 2483ae092b5bSDavid Rivshin i, slave_data->phy_node->full_name); 2484ae092b5bSDavid Rivshin } else if (of_phy_is_fixed_link(slave_node)) { 2485dfc0a6d3SDavid Rivshin /* In the case of a fixed PHY, the DT node associated 2486dfc0a6d3SDavid Rivshin * to the PHY is the Ethernet MAC DT node. 2487dfc0a6d3SDavid Rivshin */ 24881f71e8c9SMarkus Brunner ret = of_phy_register_fixed_link(slave_node); 248923a09873SJohan Hovold if (ret) { 249023a09873SJohan Hovold if (ret != -EPROBE_DEFER) 249123a09873SJohan Hovold dev_err(&pdev->dev, "failed to register fixed-link phy: %d\n", ret); 24921f71e8c9SMarkus Brunner return ret; 249323a09873SJohan Hovold } 249406cd6d6eSDavid Rivshin slave_data->phy_node = of_node_get(slave_node); 2495f1eea5c1SDavid Rivshin } else if (parp) { 2496f1eea5c1SDavid Rivshin u32 phyid; 2497f1eea5c1SDavid Rivshin struct device_node *mdio_node; 2498f1eea5c1SDavid Rivshin struct platform_device *mdio; 2499f1eea5c1SDavid Rivshin 2500f1eea5c1SDavid Rivshin if (lenp != (sizeof(__be32) * 2)) { 2501f1eea5c1SDavid Rivshin dev_err(&pdev->dev, "Invalid slave[%d] phy_id property\n", i); 250247276fccSMugunthan V N goto no_phy_slave; 2503549985eeSRichard Cochran } 2504549985eeSRichard Cochran mdio_node = of_find_node_by_phandle(be32_to_cpup(parp)); 2505549985eeSRichard Cochran phyid = be32_to_cpup(parp+1); 2506549985eeSRichard Cochran mdio = of_find_device_by_node(mdio_node); 250760e71ab5SJohan Hovold of_node_put(mdio_node); 25086954cc1fSJohan Hovold if (!mdio) { 250956fdb2e0SMarkus Pargmann dev_err(&pdev->dev, "Missing mdio platform device\n"); 25106954cc1fSJohan Hovold return -EINVAL; 25116954cc1fSJohan Hovold } 2512549985eeSRichard Cochran snprintf(slave_data->phy_id, sizeof(slave_data->phy_id), 2513549985eeSRichard Cochran PHY_ID_FMT, mdio->name, phyid); 251486e1d5adSJohan Hovold put_device(&mdio->dev); 2515f1eea5c1SDavid Rivshin } else { 2516ae092b5bSDavid Rivshin dev_err(&pdev->dev, 2517ae092b5bSDavid Rivshin "No slave[%d] phy_id, phy-handle, or fixed-link property\n", 2518ae092b5bSDavid Rivshin i); 2519f1eea5c1SDavid Rivshin goto no_phy_slave; 2520f1eea5c1SDavid Rivshin } 252147276fccSMugunthan V N slave_data->phy_if = of_get_phy_mode(slave_node); 252247276fccSMugunthan V N if (slave_data->phy_if < 0) { 252347276fccSMugunthan V N dev_err(&pdev->dev, "Missing or malformed slave[%d] phy-mode property\n", 252447276fccSMugunthan V N i); 252547276fccSMugunthan V N return slave_data->phy_if; 252647276fccSMugunthan V N } 252747276fccSMugunthan V N 252847276fccSMugunthan V N no_phy_slave: 2529549985eeSRichard Cochran mac_addr = of_get_mac_address(slave_node); 25300ba517b1SMarkus Pargmann if (mac_addr) { 2531549985eeSRichard Cochran memcpy(slave_data->mac_addr, mac_addr, ETH_ALEN); 25320ba517b1SMarkus Pargmann } else { 2533b6745f6eSMugunthan V N ret = ti_cm_get_macid(&pdev->dev, i, 25340ba517b1SMarkus Pargmann slave_data->mac_addr); 25350ba517b1SMarkus Pargmann if (ret) 25360ba517b1SMarkus Pargmann return ret; 25370ba517b1SMarkus Pargmann } 2538d9ba8f9eSMugunthan V N if (data->dual_emac) { 253991c4166cSMugunthan V N if (of_property_read_u32(slave_node, "dual_emac_res_vlan", 2540d9ba8f9eSMugunthan V N &prop)) { 254188c99ff6SGeorge Cherian dev_err(&pdev->dev, "Missing dual_emac_res_vlan in DT.\n"); 2542d9ba8f9eSMugunthan V N slave_data->dual_emac_res_vlan = i+1; 254388c99ff6SGeorge Cherian dev_err(&pdev->dev, "Using %d as Reserved VLAN for %d slave\n", 2544d9ba8f9eSMugunthan V N slave_data->dual_emac_res_vlan, i); 2545d9ba8f9eSMugunthan V N } else { 2546d9ba8f9eSMugunthan V N slave_data->dual_emac_res_vlan = prop; 2547d9ba8f9eSMugunthan V N } 2548d9ba8f9eSMugunthan V N } 2549d9ba8f9eSMugunthan V N 2550549985eeSRichard Cochran i++; 25513a27bfacSMugunthan V N if (i == data->slaves) 25523a27bfacSMugunthan V N break; 2553549985eeSRichard Cochran } 2554549985eeSRichard Cochran 25552eb32b0aSMugunthan V N return 0; 25562eb32b0aSMugunthan V N } 25572eb32b0aSMugunthan V N 2558a4e32b0dSJohan Hovold static void cpsw_remove_dt(struct platform_device *pdev) 2559a4e32b0dSJohan Hovold { 25608cbcc466SJohan Hovold struct net_device *ndev = platform_get_drvdata(pdev); 25618cbcc466SJohan Hovold struct cpsw_common *cpsw = ndev_to_cpsw(ndev); 25628cbcc466SJohan Hovold struct cpsw_platform_data *data = &cpsw->data; 25638cbcc466SJohan Hovold struct device_node *node = pdev->dev.of_node; 25648cbcc466SJohan Hovold struct device_node *slave_node; 25658cbcc466SJohan Hovold int i = 0; 25668cbcc466SJohan Hovold 25678cbcc466SJohan Hovold for_each_available_child_of_node(node, slave_node) { 25688cbcc466SJohan Hovold struct cpsw_slave_data *slave_data = &data->slave_data[i]; 25698cbcc466SJohan Hovold 25708cbcc466SJohan Hovold if (strcmp(slave_node->name, "slave")) 25718cbcc466SJohan Hovold continue; 25728cbcc466SJohan Hovold 25738cbcc466SJohan Hovold if (of_phy_is_fixed_link(slave_node)) { 25748cbcc466SJohan Hovold struct phy_device *phydev; 25758cbcc466SJohan Hovold 25768cbcc466SJohan Hovold phydev = of_phy_find_device(slave_node); 25778cbcc466SJohan Hovold if (phydev) { 25788cbcc466SJohan Hovold fixed_phy_unregister(phydev); 25798cbcc466SJohan Hovold /* Put references taken by 25808cbcc466SJohan Hovold * of_phy_find_device() and 25818cbcc466SJohan Hovold * of_phy_register_fixed_link(). 25828cbcc466SJohan Hovold */ 25838cbcc466SJohan Hovold phy_device_free(phydev); 25848cbcc466SJohan Hovold phy_device_free(phydev); 25858cbcc466SJohan Hovold } 25868cbcc466SJohan Hovold } 25878cbcc466SJohan Hovold 25888cbcc466SJohan Hovold of_node_put(slave_data->phy_node); 25898cbcc466SJohan Hovold 25908cbcc466SJohan Hovold i++; 25918cbcc466SJohan Hovold if (i == data->slaves) 25928cbcc466SJohan Hovold break; 25938cbcc466SJohan Hovold } 25948cbcc466SJohan Hovold 2595a4e32b0dSJohan Hovold of_platform_depopulate(&pdev->dev); 2596a4e32b0dSJohan Hovold } 2597a4e32b0dSJohan Hovold 259856e31bd8SIvan Khoronzhuk static int cpsw_probe_dual_emac(struct cpsw_priv *priv) 2599d9ba8f9eSMugunthan V N { 2600606f3993SIvan Khoronzhuk struct cpsw_common *cpsw = priv->cpsw; 2601606f3993SIvan Khoronzhuk struct cpsw_platform_data *data = &cpsw->data; 2602d9ba8f9eSMugunthan V N struct net_device *ndev; 2603d9ba8f9eSMugunthan V N struct cpsw_priv *priv_sl2; 2604e38b5a3dSIvan Khoronzhuk int ret = 0; 2605d9ba8f9eSMugunthan V N 2606e05107e6SIvan Khoronzhuk ndev = alloc_etherdev_mq(sizeof(struct cpsw_priv), CPSW_MAX_QUEUES); 2607d9ba8f9eSMugunthan V N if (!ndev) { 260856e31bd8SIvan Khoronzhuk dev_err(cpsw->dev, "cpsw: error allocating net_device\n"); 2609d9ba8f9eSMugunthan V N return -ENOMEM; 2610d9ba8f9eSMugunthan V N } 2611d9ba8f9eSMugunthan V N 2612d9ba8f9eSMugunthan V N priv_sl2 = netdev_priv(ndev); 2613606f3993SIvan Khoronzhuk priv_sl2->cpsw = cpsw; 2614d9ba8f9eSMugunthan V N priv_sl2->ndev = ndev; 2615d9ba8f9eSMugunthan V N priv_sl2->dev = &ndev->dev; 2616d9ba8f9eSMugunthan V N priv_sl2->msg_enable = netif_msg_init(debug_level, CPSW_DEBUG); 2617d9ba8f9eSMugunthan V N 2618d9ba8f9eSMugunthan V N if (is_valid_ether_addr(data->slave_data[1].mac_addr)) { 2619d9ba8f9eSMugunthan V N memcpy(priv_sl2->mac_addr, data->slave_data[1].mac_addr, 2620d9ba8f9eSMugunthan V N ETH_ALEN); 262156e31bd8SIvan Khoronzhuk dev_info(cpsw->dev, "cpsw: Detected MACID = %pM\n", 262256e31bd8SIvan Khoronzhuk priv_sl2->mac_addr); 2623d9ba8f9eSMugunthan V N } else { 2624d9ba8f9eSMugunthan V N random_ether_addr(priv_sl2->mac_addr); 262556e31bd8SIvan Khoronzhuk dev_info(cpsw->dev, "cpsw: Random MACID = %pM\n", 262656e31bd8SIvan Khoronzhuk priv_sl2->mac_addr); 2627d9ba8f9eSMugunthan V N } 2628d9ba8f9eSMugunthan V N memcpy(ndev->dev_addr, priv_sl2->mac_addr, ETH_ALEN); 2629d9ba8f9eSMugunthan V N 2630d9ba8f9eSMugunthan V N priv_sl2->emac_port = 1; 2631606f3993SIvan Khoronzhuk cpsw->slaves[1].ndev = ndev; 2632f646968fSPatrick McHardy ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER; 2633d9ba8f9eSMugunthan V N 2634d9ba8f9eSMugunthan V N ndev->netdev_ops = &cpsw_netdev_ops; 26357ad24ea4SWilfried Klaebe ndev->ethtool_ops = &cpsw_ethtool_ops; 2636d9ba8f9eSMugunthan V N 2637d9ba8f9eSMugunthan V N /* register the network device */ 263856e31bd8SIvan Khoronzhuk SET_NETDEV_DEV(ndev, cpsw->dev); 2639d9ba8f9eSMugunthan V N ret = register_netdev(ndev); 2640d9ba8f9eSMugunthan V N if (ret) { 264156e31bd8SIvan Khoronzhuk dev_err(cpsw->dev, "cpsw: error registering net device\n"); 2642d9ba8f9eSMugunthan V N free_netdev(ndev); 2643d9ba8f9eSMugunthan V N ret = -ENODEV; 2644d9ba8f9eSMugunthan V N } 2645d9ba8f9eSMugunthan V N 2646d9ba8f9eSMugunthan V N return ret; 2647d9ba8f9eSMugunthan V N } 2648d9ba8f9eSMugunthan V N 26497da11600SMugunthan V N #define CPSW_QUIRK_IRQ BIT(0) 26507da11600SMugunthan V N 26517da11600SMugunthan V N static struct platform_device_id cpsw_devtype[] = { 26527da11600SMugunthan V N { 26537da11600SMugunthan V N /* keep it for existing comaptibles */ 26547da11600SMugunthan V N .name = "cpsw", 26557da11600SMugunthan V N .driver_data = CPSW_QUIRK_IRQ, 26567da11600SMugunthan V N }, { 26577da11600SMugunthan V N .name = "am335x-cpsw", 26587da11600SMugunthan V N .driver_data = CPSW_QUIRK_IRQ, 26597da11600SMugunthan V N }, { 26607da11600SMugunthan V N .name = "am4372-cpsw", 26617da11600SMugunthan V N .driver_data = 0, 26627da11600SMugunthan V N }, { 26637da11600SMugunthan V N .name = "dra7-cpsw", 26647da11600SMugunthan V N .driver_data = 0, 26657da11600SMugunthan V N }, { 26667da11600SMugunthan V N /* sentinel */ 26677da11600SMugunthan V N } 26687da11600SMugunthan V N }; 26697da11600SMugunthan V N MODULE_DEVICE_TABLE(platform, cpsw_devtype); 26707da11600SMugunthan V N 26717da11600SMugunthan V N enum ti_cpsw_type { 26727da11600SMugunthan V N CPSW = 0, 26737da11600SMugunthan V N AM335X_CPSW, 26747da11600SMugunthan V N AM4372_CPSW, 26757da11600SMugunthan V N DRA7_CPSW, 26767da11600SMugunthan V N }; 26777da11600SMugunthan V N 26787da11600SMugunthan V N static const struct of_device_id cpsw_of_mtable[] = { 26797da11600SMugunthan V N { .compatible = "ti,cpsw", .data = &cpsw_devtype[CPSW], }, 26807da11600SMugunthan V N { .compatible = "ti,am335x-cpsw", .data = &cpsw_devtype[AM335X_CPSW], }, 26817da11600SMugunthan V N { .compatible = "ti,am4372-cpsw", .data = &cpsw_devtype[AM4372_CPSW], }, 26827da11600SMugunthan V N { .compatible = "ti,dra7-cpsw", .data = &cpsw_devtype[DRA7_CPSW], }, 26837da11600SMugunthan V N { /* sentinel */ }, 26847da11600SMugunthan V N }; 26857da11600SMugunthan V N MODULE_DEVICE_TABLE(of, cpsw_of_mtable); 26867da11600SMugunthan V N 2687663e12e6SBill Pemberton static int cpsw_probe(struct platform_device *pdev) 2688df828598SMugunthan V N { 2689ef4183a1SIvan Khoronzhuk struct clk *clk; 2690d1bd9acfSSebastian Siewior struct cpsw_platform_data *data; 2691df828598SMugunthan V N struct net_device *ndev; 2692df828598SMugunthan V N struct cpsw_priv *priv; 2693df828598SMugunthan V N struct cpdma_params dma_params; 2694df828598SMugunthan V N struct cpsw_ale_params ale_params; 2695aa1a15e2SDaniel Mack void __iomem *ss_regs; 2696aa1a15e2SDaniel Mack struct resource *res, *ss_res; 26977da11600SMugunthan V N const struct of_device_id *of_id; 26981d147ccbSMugunthan V N struct gpio_descs *mode; 2699549985eeSRichard Cochran u32 slave_offset, sliver_offset, slave_size; 2700649a1688SIvan Khoronzhuk struct cpsw_common *cpsw; 27015087b915SFelipe Balbi int ret = 0, i; 27025087b915SFelipe Balbi int irq; 2703df828598SMugunthan V N 2704649a1688SIvan Khoronzhuk cpsw = devm_kzalloc(&pdev->dev, sizeof(struct cpsw_common), GFP_KERNEL); 27053420ea88SJohan Hovold if (!cpsw) 27063420ea88SJohan Hovold return -ENOMEM; 27073420ea88SJohan Hovold 270856e31bd8SIvan Khoronzhuk cpsw->dev = &pdev->dev; 2709649a1688SIvan Khoronzhuk 2710e05107e6SIvan Khoronzhuk ndev = alloc_etherdev_mq(sizeof(struct cpsw_priv), CPSW_MAX_QUEUES); 2711df828598SMugunthan V N if (!ndev) { 271288c99ff6SGeorge Cherian dev_err(&pdev->dev, "error allocating net_device\n"); 2713df828598SMugunthan V N return -ENOMEM; 2714df828598SMugunthan V N } 2715df828598SMugunthan V N 2716df828598SMugunthan V N platform_set_drvdata(pdev, ndev); 2717df828598SMugunthan V N priv = netdev_priv(ndev); 2718649a1688SIvan Khoronzhuk priv->cpsw = cpsw; 2719df828598SMugunthan V N priv->ndev = ndev; 2720df828598SMugunthan V N priv->dev = &ndev->dev; 2721df828598SMugunthan V N priv->msg_enable = netif_msg_init(debug_level, CPSW_DEBUG); 27222a05a622SIvan Khoronzhuk cpsw->rx_packet_max = max(rx_packet_max, 128); 27232a05a622SIvan Khoronzhuk cpsw->cpts = devm_kzalloc(&pdev->dev, sizeof(struct cpts), GFP_KERNEL); 27242a05a622SIvan Khoronzhuk if (!cpsw->cpts) { 272588c99ff6SGeorge Cherian dev_err(&pdev->dev, "error allocating cpts\n"); 27264d507dffSMarkus Pargmann ret = -ENOMEM; 27279232b16dSMugunthan V N goto clean_ndev_ret; 27289232b16dSMugunthan V N } 2729df828598SMugunthan V N 27301d147ccbSMugunthan V N mode = devm_gpiod_get_array_optional(&pdev->dev, "mode", GPIOD_OUT_LOW); 27311d147ccbSMugunthan V N if (IS_ERR(mode)) { 27321d147ccbSMugunthan V N ret = PTR_ERR(mode); 27331d147ccbSMugunthan V N dev_err(&pdev->dev, "gpio request failed, ret %d\n", ret); 27341d147ccbSMugunthan V N goto clean_ndev_ret; 27351d147ccbSMugunthan V N } 27361d147ccbSMugunthan V N 27371fb19aa7SVaibhav Hiremath /* 27381fb19aa7SVaibhav Hiremath * This may be required here for child devices. 27391fb19aa7SVaibhav Hiremath */ 27401fb19aa7SVaibhav Hiremath pm_runtime_enable(&pdev->dev); 27411fb19aa7SVaibhav Hiremath 2742739683b4SMugunthan V N /* Select default pin state */ 2743739683b4SMugunthan V N pinctrl_pm_select_default_state(&pdev->dev); 2744739683b4SMugunthan V N 2745a4e32b0dSJohan Hovold /* Need to enable clocks with runtime PM api to access module 2746a4e32b0dSJohan Hovold * registers 2747a4e32b0dSJohan Hovold */ 2748a4e32b0dSJohan Hovold ret = pm_runtime_get_sync(&pdev->dev); 2749a4e32b0dSJohan Hovold if (ret < 0) { 2750a4e32b0dSJohan Hovold pm_runtime_put_noidle(&pdev->dev); 2751aa1a15e2SDaniel Mack goto clean_runtime_disable_ret; 27522eb32b0aSMugunthan V N } 2753a4e32b0dSJohan Hovold 275423a09873SJohan Hovold ret = cpsw_probe_dt(&cpsw->data, pdev); 275523a09873SJohan Hovold if (ret) 2756a4e32b0dSJohan Hovold goto clean_dt_ret; 275723a09873SJohan Hovold 2758606f3993SIvan Khoronzhuk data = &cpsw->data; 2759e05107e6SIvan Khoronzhuk cpsw->rx_ch_num = 1; 2760e05107e6SIvan Khoronzhuk cpsw->tx_ch_num = 1; 27612eb32b0aSMugunthan V N 2762df828598SMugunthan V N if (is_valid_ether_addr(data->slave_data[0].mac_addr)) { 2763df828598SMugunthan V N memcpy(priv->mac_addr, data->slave_data[0].mac_addr, ETH_ALEN); 276488c99ff6SGeorge Cherian dev_info(&pdev->dev, "Detected MACID = %pM\n", priv->mac_addr); 2765df828598SMugunthan V N } else { 27667efd26d0SJoe Perches eth_random_addr(priv->mac_addr); 276788c99ff6SGeorge Cherian dev_info(&pdev->dev, "Random MACID = %pM\n", priv->mac_addr); 2768df828598SMugunthan V N } 2769df828598SMugunthan V N 2770df828598SMugunthan V N memcpy(ndev->dev_addr, priv->mac_addr, ETH_ALEN); 2771df828598SMugunthan V N 2772606f3993SIvan Khoronzhuk cpsw->slaves = devm_kzalloc(&pdev->dev, 2773aa1a15e2SDaniel Mack sizeof(struct cpsw_slave) * data->slaves, 2774df828598SMugunthan V N GFP_KERNEL); 2775606f3993SIvan Khoronzhuk if (!cpsw->slaves) { 2776aa1a15e2SDaniel Mack ret = -ENOMEM; 2777a4e32b0dSJohan Hovold goto clean_dt_ret; 2778df828598SMugunthan V N } 2779df828598SMugunthan V N for (i = 0; i < data->slaves; i++) 2780606f3993SIvan Khoronzhuk cpsw->slaves[i].slave_num = i; 2781df828598SMugunthan V N 2782606f3993SIvan Khoronzhuk cpsw->slaves[0].ndev = ndev; 2783d9ba8f9eSMugunthan V N priv->emac_port = 0; 2784d9ba8f9eSMugunthan V N 2785ef4183a1SIvan Khoronzhuk clk = devm_clk_get(&pdev->dev, "fck"); 2786ef4183a1SIvan Khoronzhuk if (IS_ERR(clk)) { 2787aa1a15e2SDaniel Mack dev_err(priv->dev, "fck is not found\n"); 2788f150bd7fSMugunthan V N ret = -ENODEV; 2789a4e32b0dSJohan Hovold goto clean_dt_ret; 2790df828598SMugunthan V N } 27912a05a622SIvan Khoronzhuk cpsw->bus_freq_mhz = clk_get_rate(clk) / 1000000; 2792df828598SMugunthan V N 2793aa1a15e2SDaniel Mack ss_res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2794aa1a15e2SDaniel Mack ss_regs = devm_ioremap_resource(&pdev->dev, ss_res); 2795aa1a15e2SDaniel Mack if (IS_ERR(ss_regs)) { 2796aa1a15e2SDaniel Mack ret = PTR_ERR(ss_regs); 2797a4e32b0dSJohan Hovold goto clean_dt_ret; 2798df828598SMugunthan V N } 27995d8d0d4dSIvan Khoronzhuk cpsw->regs = ss_regs; 2800df828598SMugunthan V N 28012a05a622SIvan Khoronzhuk cpsw->version = readl(&cpsw->regs->id_ver); 2802f280e89aSMugunthan V N 2803aa1a15e2SDaniel Mack res = platform_get_resource(pdev, IORESOURCE_MEM, 1); 28045d8d0d4dSIvan Khoronzhuk cpsw->wr_regs = devm_ioremap_resource(&pdev->dev, res); 28055d8d0d4dSIvan Khoronzhuk if (IS_ERR(cpsw->wr_regs)) { 28065d8d0d4dSIvan Khoronzhuk ret = PTR_ERR(cpsw->wr_regs); 2807a4e32b0dSJohan Hovold goto clean_dt_ret; 2808df828598SMugunthan V N } 2809df828598SMugunthan V N 2810df828598SMugunthan V N memset(&dma_params, 0, sizeof(dma_params)); 2811549985eeSRichard Cochran memset(&ale_params, 0, sizeof(ale_params)); 2812549985eeSRichard Cochran 28132a05a622SIvan Khoronzhuk switch (cpsw->version) { 2814549985eeSRichard Cochran case CPSW_VERSION_1: 28155d8d0d4dSIvan Khoronzhuk cpsw->host_port_regs = ss_regs + CPSW1_HOST_PORT_OFFSET; 28162a05a622SIvan Khoronzhuk cpsw->cpts->reg = ss_regs + CPSW1_CPTS_OFFSET; 28175d8d0d4dSIvan Khoronzhuk cpsw->hw_stats = ss_regs + CPSW1_HW_STATS; 2818549985eeSRichard Cochran dma_params.dmaregs = ss_regs + CPSW1_CPDMA_OFFSET; 2819549985eeSRichard Cochran dma_params.txhdp = ss_regs + CPSW1_STATERAM_OFFSET; 2820549985eeSRichard Cochran ale_params.ale_regs = ss_regs + CPSW1_ALE_OFFSET; 2821549985eeSRichard Cochran slave_offset = CPSW1_SLAVE_OFFSET; 2822549985eeSRichard Cochran slave_size = CPSW1_SLAVE_SIZE; 2823549985eeSRichard Cochran sliver_offset = CPSW1_SLIVER_OFFSET; 2824549985eeSRichard Cochran dma_params.desc_mem_phys = 0; 2825549985eeSRichard Cochran break; 2826549985eeSRichard Cochran case CPSW_VERSION_2: 2827c193f365SMugunthan V N case CPSW_VERSION_3: 2828926489beSMugunthan V N case CPSW_VERSION_4: 28295d8d0d4dSIvan Khoronzhuk cpsw->host_port_regs = ss_regs + CPSW2_HOST_PORT_OFFSET; 28302a05a622SIvan Khoronzhuk cpsw->cpts->reg = ss_regs + CPSW2_CPTS_OFFSET; 28315d8d0d4dSIvan Khoronzhuk cpsw->hw_stats = ss_regs + CPSW2_HW_STATS; 2832549985eeSRichard Cochran dma_params.dmaregs = ss_regs + CPSW2_CPDMA_OFFSET; 2833549985eeSRichard Cochran dma_params.txhdp = ss_regs + CPSW2_STATERAM_OFFSET; 2834549985eeSRichard Cochran ale_params.ale_regs = ss_regs + CPSW2_ALE_OFFSET; 2835549985eeSRichard Cochran slave_offset = CPSW2_SLAVE_OFFSET; 2836549985eeSRichard Cochran slave_size = CPSW2_SLAVE_SIZE; 2837549985eeSRichard Cochran sliver_offset = CPSW2_SLIVER_OFFSET; 2838549985eeSRichard Cochran dma_params.desc_mem_phys = 2839aa1a15e2SDaniel Mack (u32 __force) ss_res->start + CPSW2_BD_OFFSET; 2840549985eeSRichard Cochran break; 2841549985eeSRichard Cochran default: 28422a05a622SIvan Khoronzhuk dev_err(priv->dev, "unknown version 0x%08x\n", cpsw->version); 2843549985eeSRichard Cochran ret = -ENODEV; 2844a4e32b0dSJohan Hovold goto clean_dt_ret; 2845549985eeSRichard Cochran } 2846606f3993SIvan Khoronzhuk for (i = 0; i < cpsw->data.slaves; i++) { 2847606f3993SIvan Khoronzhuk struct cpsw_slave *slave = &cpsw->slaves[i]; 2848606f3993SIvan Khoronzhuk 2849606f3993SIvan Khoronzhuk cpsw_slave_init(slave, cpsw, slave_offset, sliver_offset); 2850549985eeSRichard Cochran slave_offset += slave_size; 2851549985eeSRichard Cochran sliver_offset += SLIVER_SIZE; 2852549985eeSRichard Cochran } 2853549985eeSRichard Cochran 2854df828598SMugunthan V N dma_params.dev = &pdev->dev; 2855549985eeSRichard Cochran dma_params.rxthresh = dma_params.dmaregs + CPDMA_RXTHRESH; 2856549985eeSRichard Cochran dma_params.rxfree = dma_params.dmaregs + CPDMA_RXFREE; 2857549985eeSRichard Cochran dma_params.rxhdp = dma_params.txhdp + CPDMA_RXHDP; 2858549985eeSRichard Cochran dma_params.txcp = dma_params.txhdp + CPDMA_TXCP; 2859549985eeSRichard Cochran dma_params.rxcp = dma_params.txhdp + CPDMA_RXCP; 2860df828598SMugunthan V N 2861df828598SMugunthan V N dma_params.num_chan = data->channels; 2862df828598SMugunthan V N dma_params.has_soft_reset = true; 2863df828598SMugunthan V N dma_params.min_packet_size = CPSW_MIN_PACKET_SIZE; 2864df828598SMugunthan V N dma_params.desc_mem_size = data->bd_ram_size; 2865df828598SMugunthan V N dma_params.desc_align = 16; 2866df828598SMugunthan V N dma_params.has_ext_regs = true; 2867549985eeSRichard Cochran dma_params.desc_hw_addr = dma_params.desc_mem_phys; 286883fcad0cSIvan Khoronzhuk dma_params.bus_freq_mhz = cpsw->bus_freq_mhz; 2869df828598SMugunthan V N 28702c836bd9SIvan Khoronzhuk cpsw->dma = cpdma_ctlr_create(&dma_params); 28712c836bd9SIvan Khoronzhuk if (!cpsw->dma) { 2872df828598SMugunthan V N dev_err(priv->dev, "error initializing dma\n"); 2873df828598SMugunthan V N ret = -ENOMEM; 2874a4e32b0dSJohan Hovold goto clean_dt_ret; 2875df828598SMugunthan V N } 2876df828598SMugunthan V N 2877925d65e6SIvan Khoronzhuk cpsw->txch[0] = cpdma_chan_create(cpsw->dma, 0, cpsw_tx_handler, 0); 2878925d65e6SIvan Khoronzhuk cpsw->rxch[0] = cpdma_chan_create(cpsw->dma, 0, cpsw_rx_handler, 1); 2879e05107e6SIvan Khoronzhuk if (WARN_ON(!cpsw->rxch[0] || !cpsw->txch[0])) { 2880df828598SMugunthan V N dev_err(priv->dev, "error initializing dma channels\n"); 2881df828598SMugunthan V N ret = -ENOMEM; 2882df828598SMugunthan V N goto clean_dma_ret; 2883df828598SMugunthan V N } 2884df828598SMugunthan V N 2885df828598SMugunthan V N ale_params.dev = &ndev->dev; 2886df828598SMugunthan V N ale_params.ale_ageout = ale_ageout; 2887df828598SMugunthan V N ale_params.ale_entries = data->ale_entries; 2888df828598SMugunthan V N ale_params.ale_ports = data->slaves; 2889df828598SMugunthan V N 28902a05a622SIvan Khoronzhuk cpsw->ale = cpsw_ale_create(&ale_params); 28912a05a622SIvan Khoronzhuk if (!cpsw->ale) { 2892df828598SMugunthan V N dev_err(priv->dev, "error initializing ale engine\n"); 2893df828598SMugunthan V N ret = -ENODEV; 2894df828598SMugunthan V N goto clean_dma_ret; 2895df828598SMugunthan V N } 2896df828598SMugunthan V N 2897c03abd84SFelipe Balbi ndev->irq = platform_get_irq(pdev, 1); 2898df828598SMugunthan V N if (ndev->irq < 0) { 2899df828598SMugunthan V N dev_err(priv->dev, "error getting irq resource\n"); 2900c1e3334fSJulia Lawall ret = ndev->irq; 2901df828598SMugunthan V N goto clean_ale_ret; 2902df828598SMugunthan V N } 2903df828598SMugunthan V N 29047da11600SMugunthan V N of_id = of_match_device(cpsw_of_mtable, &pdev->dev); 29057da11600SMugunthan V N if (of_id) { 29067da11600SMugunthan V N pdev->id_entry = of_id->data; 29077da11600SMugunthan V N if (pdev->id_entry->driver_data) 2908e38b5a3dSIvan Khoronzhuk cpsw->quirk_irq = true; 29097da11600SMugunthan V N } 29107da11600SMugunthan V N 2911c03abd84SFelipe Balbi /* Grab RX and TX IRQs. Note that we also have RX_THRESHOLD and 2912c03abd84SFelipe Balbi * MISC IRQs which are always kept disabled with this driver so 2913c03abd84SFelipe Balbi * we will not request them. 2914c03abd84SFelipe Balbi * 2915c03abd84SFelipe Balbi * If anyone wants to implement support for those, make sure to 2916c03abd84SFelipe Balbi * first request and append them to irqs_table array. 2917c03abd84SFelipe Balbi */ 2918c2b32e58SDaniel Mack 2919c03abd84SFelipe Balbi /* RX IRQ */ 29205087b915SFelipe Balbi irq = platform_get_irq(pdev, 1); 2921c1e3334fSJulia Lawall if (irq < 0) { 2922c1e3334fSJulia Lawall ret = irq; 29235087b915SFelipe Balbi goto clean_ale_ret; 2924c1e3334fSJulia Lawall } 29255087b915SFelipe Balbi 2926e38b5a3dSIvan Khoronzhuk cpsw->irqs_table[0] = irq; 2927c03abd84SFelipe Balbi ret = devm_request_irq(&pdev->dev, irq, cpsw_rx_interrupt, 2928dbc4ec52SIvan Khoronzhuk 0, dev_name(&pdev->dev), cpsw); 29295087b915SFelipe Balbi if (ret < 0) { 29305087b915SFelipe Balbi dev_err(priv->dev, "error attaching irq (%d)\n", ret); 29315087b915SFelipe Balbi goto clean_ale_ret; 2932df828598SMugunthan V N } 2933df828598SMugunthan V N 2934c03abd84SFelipe Balbi /* TX IRQ */ 29355087b915SFelipe Balbi irq = platform_get_irq(pdev, 2); 2936c1e3334fSJulia Lawall if (irq < 0) { 2937c1e3334fSJulia Lawall ret = irq; 29385087b915SFelipe Balbi goto clean_ale_ret; 2939c1e3334fSJulia Lawall } 29405087b915SFelipe Balbi 2941e38b5a3dSIvan Khoronzhuk cpsw->irqs_table[1] = irq; 2942c03abd84SFelipe Balbi ret = devm_request_irq(&pdev->dev, irq, cpsw_tx_interrupt, 2943dbc4ec52SIvan Khoronzhuk 0, dev_name(&pdev->dev), cpsw); 29445087b915SFelipe Balbi if (ret < 0) { 29455087b915SFelipe Balbi dev_err(priv->dev, "error attaching irq (%d)\n", ret); 29465087b915SFelipe Balbi goto clean_ale_ret; 29475087b915SFelipe Balbi } 2948c2b32e58SDaniel Mack 2949f646968fSPatrick McHardy ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER; 2950df828598SMugunthan V N 2951df828598SMugunthan V N ndev->netdev_ops = &cpsw_netdev_ops; 29527ad24ea4SWilfried Klaebe ndev->ethtool_ops = &cpsw_ethtool_ops; 2953dbc4ec52SIvan Khoronzhuk netif_napi_add(ndev, &cpsw->napi_rx, cpsw_rx_poll, CPSW_POLL_WEIGHT); 2954dbc4ec52SIvan Khoronzhuk netif_tx_napi_add(ndev, &cpsw->napi_tx, cpsw_tx_poll, CPSW_POLL_WEIGHT); 2955df828598SMugunthan V N 2956df828598SMugunthan V N /* register the network device */ 2957df828598SMugunthan V N SET_NETDEV_DEV(ndev, &pdev->dev); 2958df828598SMugunthan V N ret = register_netdev(ndev); 2959df828598SMugunthan V N if (ret) { 2960df828598SMugunthan V N dev_err(priv->dev, "error registering net device\n"); 2961df828598SMugunthan V N ret = -ENODEV; 2962aa1a15e2SDaniel Mack goto clean_ale_ret; 2963df828598SMugunthan V N } 2964df828598SMugunthan V N 29651a3b5056SOlof Johansson cpsw_notice(priv, probe, "initialized device (regs %pa, irq %d)\n", 29661a3b5056SOlof Johansson &ss_res->start, ndev->irq); 2967df828598SMugunthan V N 2968606f3993SIvan Khoronzhuk if (cpsw->data.dual_emac) { 296956e31bd8SIvan Khoronzhuk ret = cpsw_probe_dual_emac(priv); 2970d9ba8f9eSMugunthan V N if (ret) { 2971d9ba8f9eSMugunthan V N cpsw_err(priv, probe, "error probe slave 2 emac interface\n"); 2972a7fe9d46SJohan Hovold goto clean_unregister_netdev_ret; 2973d9ba8f9eSMugunthan V N } 2974d9ba8f9eSMugunthan V N } 2975d9ba8f9eSMugunthan V N 2976c46ab7e0SJohan Hovold pm_runtime_put(&pdev->dev); 2977c46ab7e0SJohan Hovold 2978df828598SMugunthan V N return 0; 2979df828598SMugunthan V N 2980a7fe9d46SJohan Hovold clean_unregister_netdev_ret: 2981a7fe9d46SJohan Hovold unregister_netdev(ndev); 2982df828598SMugunthan V N clean_ale_ret: 29832a05a622SIvan Khoronzhuk cpsw_ale_destroy(cpsw->ale); 2984df828598SMugunthan V N clean_dma_ret: 29852c836bd9SIvan Khoronzhuk cpdma_ctlr_destroy(cpsw->dma); 2986a4e32b0dSJohan Hovold clean_dt_ret: 2987a4e32b0dSJohan Hovold cpsw_remove_dt(pdev); 2988c46ab7e0SJohan Hovold pm_runtime_put_sync(&pdev->dev); 2989aa1a15e2SDaniel Mack clean_runtime_disable_ret: 2990f150bd7fSMugunthan V N pm_runtime_disable(&pdev->dev); 2991df828598SMugunthan V N clean_ndev_ret: 2992d1bd9acfSSebastian Siewior free_netdev(priv->ndev); 2993df828598SMugunthan V N return ret; 2994df828598SMugunthan V N } 2995df828598SMugunthan V N 2996663e12e6SBill Pemberton static int cpsw_remove(struct platform_device *pdev) 2997df828598SMugunthan V N { 2998df828598SMugunthan V N struct net_device *ndev = platform_get_drvdata(pdev); 29992a05a622SIvan Khoronzhuk struct cpsw_common *cpsw = ndev_to_cpsw(ndev); 30008a0b6dc9SGrygorii Strashko int ret; 30018a0b6dc9SGrygorii Strashko 30028a0b6dc9SGrygorii Strashko ret = pm_runtime_get_sync(&pdev->dev); 30038a0b6dc9SGrygorii Strashko if (ret < 0) { 30048a0b6dc9SGrygorii Strashko pm_runtime_put_noidle(&pdev->dev); 30058a0b6dc9SGrygorii Strashko return ret; 30068a0b6dc9SGrygorii Strashko } 3007df828598SMugunthan V N 3008606f3993SIvan Khoronzhuk if (cpsw->data.dual_emac) 3009606f3993SIvan Khoronzhuk unregister_netdev(cpsw->slaves[1].ndev); 3010d1bd9acfSSebastian Siewior unregister_netdev(ndev); 3011df828598SMugunthan V N 30122a05a622SIvan Khoronzhuk cpsw_ale_destroy(cpsw->ale); 30132c836bd9SIvan Khoronzhuk cpdma_ctlr_destroy(cpsw->dma); 3014a4e32b0dSJohan Hovold cpsw_remove_dt(pdev); 30158a0b6dc9SGrygorii Strashko pm_runtime_put_sync(&pdev->dev); 30168a0b6dc9SGrygorii Strashko pm_runtime_disable(&pdev->dev); 3017606f3993SIvan Khoronzhuk if (cpsw->data.dual_emac) 3018606f3993SIvan Khoronzhuk free_netdev(cpsw->slaves[1].ndev); 3019df828598SMugunthan V N free_netdev(ndev); 3020df828598SMugunthan V N return 0; 3021df828598SMugunthan V N } 3022df828598SMugunthan V N 30238963a504SGrygorii Strashko #ifdef CONFIG_PM_SLEEP 3024df828598SMugunthan V N static int cpsw_suspend(struct device *dev) 3025df828598SMugunthan V N { 3026df828598SMugunthan V N struct platform_device *pdev = to_platform_device(dev); 3027df828598SMugunthan V N struct net_device *ndev = platform_get_drvdata(pdev); 3028606f3993SIvan Khoronzhuk struct cpsw_common *cpsw = ndev_to_cpsw(ndev); 3029df828598SMugunthan V N 3030606f3993SIvan Khoronzhuk if (cpsw->data.dual_emac) { 3031618073e3SMugunthan V N int i; 3032618073e3SMugunthan V N 3033606f3993SIvan Khoronzhuk for (i = 0; i < cpsw->data.slaves; i++) { 3034606f3993SIvan Khoronzhuk if (netif_running(cpsw->slaves[i].ndev)) 3035606f3993SIvan Khoronzhuk cpsw_ndo_stop(cpsw->slaves[i].ndev); 3036618073e3SMugunthan V N } 3037618073e3SMugunthan V N } else { 3038df828598SMugunthan V N if (netif_running(ndev)) 3039df828598SMugunthan V N cpsw_ndo_stop(ndev); 3040618073e3SMugunthan V N } 30411e7a2e21SDaniel Mack 3042739683b4SMugunthan V N /* Select sleep pin state */ 304356e31bd8SIvan Khoronzhuk pinctrl_pm_select_sleep_state(dev); 3044739683b4SMugunthan V N 3045df828598SMugunthan V N return 0; 3046df828598SMugunthan V N } 3047df828598SMugunthan V N 3048df828598SMugunthan V N static int cpsw_resume(struct device *dev) 3049df828598SMugunthan V N { 3050df828598SMugunthan V N struct platform_device *pdev = to_platform_device(dev); 3051df828598SMugunthan V N struct net_device *ndev = platform_get_drvdata(pdev); 3052606f3993SIvan Khoronzhuk struct cpsw_common *cpsw = netdev_priv(ndev); 3053df828598SMugunthan V N 3054739683b4SMugunthan V N /* Select default pin state */ 305556e31bd8SIvan Khoronzhuk pinctrl_pm_select_default_state(dev); 3056739683b4SMugunthan V N 3057606f3993SIvan Khoronzhuk if (cpsw->data.dual_emac) { 3058618073e3SMugunthan V N int i; 3059618073e3SMugunthan V N 3060606f3993SIvan Khoronzhuk for (i = 0; i < cpsw->data.slaves; i++) { 3061606f3993SIvan Khoronzhuk if (netif_running(cpsw->slaves[i].ndev)) 3062606f3993SIvan Khoronzhuk cpsw_ndo_open(cpsw->slaves[i].ndev); 3063618073e3SMugunthan V N } 3064618073e3SMugunthan V N } else { 3065df828598SMugunthan V N if (netif_running(ndev)) 3066df828598SMugunthan V N cpsw_ndo_open(ndev); 3067618073e3SMugunthan V N } 3068df828598SMugunthan V N return 0; 3069df828598SMugunthan V N } 30708963a504SGrygorii Strashko #endif 3071df828598SMugunthan V N 30728963a504SGrygorii Strashko static SIMPLE_DEV_PM_OPS(cpsw_pm_ops, cpsw_suspend, cpsw_resume); 3073df828598SMugunthan V N 3074df828598SMugunthan V N static struct platform_driver cpsw_driver = { 3075df828598SMugunthan V N .driver = { 3076df828598SMugunthan V N .name = "cpsw", 3077df828598SMugunthan V N .pm = &cpsw_pm_ops, 30781e5c76d4SSachin Kamat .of_match_table = cpsw_of_mtable, 3079df828598SMugunthan V N }, 3080df828598SMugunthan V N .probe = cpsw_probe, 3081663e12e6SBill Pemberton .remove = cpsw_remove, 3082df828598SMugunthan V N }; 3083df828598SMugunthan V N 30846fb3b6b5SGrygorii Strashko module_platform_driver(cpsw_driver); 3085df828598SMugunthan V N 3086df828598SMugunthan V N MODULE_LICENSE("GPL"); 3087df828598SMugunthan V N MODULE_AUTHOR("Cyril Chemparathy <cyril@ti.com>"); 3088df828598SMugunthan V N MODULE_AUTHOR("Mugunthan V N <mugunthanvnm@ti.com>"); 3089df828598SMugunthan V N MODULE_DESCRIPTION("TI CPSW Ethernet driver"); 3090