1df828598SMugunthan V N /* 2df828598SMugunthan V N * Texas Instruments Ethernet Switch Driver 3df828598SMugunthan V N * 4df828598SMugunthan V N * Copyright (C) 2012 Texas Instruments 5df828598SMugunthan V N * 6df828598SMugunthan V N * This program is free software; you can redistribute it and/or 7df828598SMugunthan V N * modify it under the terms of the GNU General Public License as 8df828598SMugunthan V N * published by the Free Software Foundation version 2. 9df828598SMugunthan V N * 10df828598SMugunthan V N * This program is distributed "as is" WITHOUT ANY WARRANTY of any 11df828598SMugunthan V N * kind, whether express or implied; without even the implied warranty 12df828598SMugunthan V N * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13df828598SMugunthan V N * GNU General Public License for more details. 14df828598SMugunthan V N */ 15df828598SMugunthan V N 16df828598SMugunthan V N #include <linux/kernel.h> 17df828598SMugunthan V N #include <linux/io.h> 18df828598SMugunthan V N #include <linux/clk.h> 19df828598SMugunthan V N #include <linux/timer.h> 20df828598SMugunthan V N #include <linux/module.h> 21df828598SMugunthan V N #include <linux/platform_device.h> 22df828598SMugunthan V N #include <linux/irqreturn.h> 23df828598SMugunthan V N #include <linux/interrupt.h> 24df828598SMugunthan V N #include <linux/if_ether.h> 25df828598SMugunthan V N #include <linux/etherdevice.h> 26df828598SMugunthan V N #include <linux/netdevice.h> 272e5b38abSRichard Cochran #include <linux/net_tstamp.h> 28df828598SMugunthan V N #include <linux/phy.h> 29df828598SMugunthan V N #include <linux/workqueue.h> 30df828598SMugunthan V N #include <linux/delay.h> 31f150bd7fSMugunthan V N #include <linux/pm_runtime.h> 321d147ccbSMugunthan V N #include <linux/gpio.h> 332eb32b0aSMugunthan V N #include <linux/of.h> 349e42f715SHeiko Schocher #include <linux/of_mdio.h> 352eb32b0aSMugunthan V N #include <linux/of_net.h> 362eb32b0aSMugunthan V N #include <linux/of_device.h> 373b72c2feSMugunthan V N #include <linux/if_vlan.h> 38df828598SMugunthan V N 39739683b4SMugunthan V N #include <linux/pinctrl/consumer.h> 40df828598SMugunthan V N 41dbe34724SMugunthan V N #include "cpsw.h" 42df828598SMugunthan V N #include "cpsw_ale.h" 432e5b38abSRichard Cochran #include "cpts.h" 44df828598SMugunthan V N #include "davinci_cpdma.h" 45df828598SMugunthan V N 46df828598SMugunthan V N #define CPSW_DEBUG (NETIF_MSG_HW | NETIF_MSG_WOL | \ 47df828598SMugunthan V N NETIF_MSG_DRV | NETIF_MSG_LINK | \ 48df828598SMugunthan V N NETIF_MSG_IFUP | NETIF_MSG_INTR | \ 49df828598SMugunthan V N NETIF_MSG_PROBE | NETIF_MSG_TIMER | \ 50df828598SMugunthan V N NETIF_MSG_IFDOWN | NETIF_MSG_RX_ERR | \ 51df828598SMugunthan V N NETIF_MSG_TX_ERR | NETIF_MSG_TX_DONE | \ 52df828598SMugunthan V N NETIF_MSG_PKTDATA | NETIF_MSG_TX_QUEUED | \ 53df828598SMugunthan V N NETIF_MSG_RX_STATUS) 54df828598SMugunthan V N 55df828598SMugunthan V N #define cpsw_info(priv, type, format, ...) \ 56df828598SMugunthan V N do { \ 57df828598SMugunthan V N if (netif_msg_##type(priv) && net_ratelimit()) \ 58df828598SMugunthan V N dev_info(priv->dev, format, ## __VA_ARGS__); \ 59df828598SMugunthan V N } while (0) 60df828598SMugunthan V N 61df828598SMugunthan V N #define cpsw_err(priv, type, format, ...) \ 62df828598SMugunthan V N do { \ 63df828598SMugunthan V N if (netif_msg_##type(priv) && net_ratelimit()) \ 64df828598SMugunthan V N dev_err(priv->dev, format, ## __VA_ARGS__); \ 65df828598SMugunthan V N } while (0) 66df828598SMugunthan V N 67df828598SMugunthan V N #define cpsw_dbg(priv, type, format, ...) \ 68df828598SMugunthan V N do { \ 69df828598SMugunthan V N if (netif_msg_##type(priv) && net_ratelimit()) \ 70df828598SMugunthan V N dev_dbg(priv->dev, format, ## __VA_ARGS__); \ 71df828598SMugunthan V N } while (0) 72df828598SMugunthan V N 73df828598SMugunthan V N #define cpsw_notice(priv, type, format, ...) \ 74df828598SMugunthan V N do { \ 75df828598SMugunthan V N if (netif_msg_##type(priv) && net_ratelimit()) \ 76df828598SMugunthan V N dev_notice(priv->dev, format, ## __VA_ARGS__); \ 77df828598SMugunthan V N } while (0) 78df828598SMugunthan V N 795c50a856SMugunthan V N #define ALE_ALL_PORTS 0x7 805c50a856SMugunthan V N 81df828598SMugunthan V N #define CPSW_MAJOR_VERSION(reg) (reg >> 8 & 0x7) 82df828598SMugunthan V N #define CPSW_MINOR_VERSION(reg) (reg & 0xff) 83df828598SMugunthan V N #define CPSW_RTL_VERSION(reg) ((reg >> 11) & 0x1f) 84df828598SMugunthan V N 85e90cfac6SRichard Cochran #define CPSW_VERSION_1 0x19010a 86e90cfac6SRichard Cochran #define CPSW_VERSION_2 0x19010c 87c193f365SMugunthan V N #define CPSW_VERSION_3 0x19010f 88926489beSMugunthan V N #define CPSW_VERSION_4 0x190112 89549985eeSRichard Cochran 90549985eeSRichard Cochran #define HOST_PORT_NUM 0 91549985eeSRichard Cochran #define SLIVER_SIZE 0x40 92549985eeSRichard Cochran 93549985eeSRichard Cochran #define CPSW1_HOST_PORT_OFFSET 0x028 94549985eeSRichard Cochran #define CPSW1_SLAVE_OFFSET 0x050 95549985eeSRichard Cochran #define CPSW1_SLAVE_SIZE 0x040 96549985eeSRichard Cochran #define CPSW1_CPDMA_OFFSET 0x100 97549985eeSRichard Cochran #define CPSW1_STATERAM_OFFSET 0x200 98d9718546SMugunthan V N #define CPSW1_HW_STATS 0x400 99549985eeSRichard Cochran #define CPSW1_CPTS_OFFSET 0x500 100549985eeSRichard Cochran #define CPSW1_ALE_OFFSET 0x600 101549985eeSRichard Cochran #define CPSW1_SLIVER_OFFSET 0x700 102549985eeSRichard Cochran 103549985eeSRichard Cochran #define CPSW2_HOST_PORT_OFFSET 0x108 104549985eeSRichard Cochran #define CPSW2_SLAVE_OFFSET 0x200 105549985eeSRichard Cochran #define CPSW2_SLAVE_SIZE 0x100 106549985eeSRichard Cochran #define CPSW2_CPDMA_OFFSET 0x800 107d9718546SMugunthan V N #define CPSW2_HW_STATS 0x900 108549985eeSRichard Cochran #define CPSW2_STATERAM_OFFSET 0xa00 109549985eeSRichard Cochran #define CPSW2_CPTS_OFFSET 0xc00 110549985eeSRichard Cochran #define CPSW2_ALE_OFFSET 0xd00 111549985eeSRichard Cochran #define CPSW2_SLIVER_OFFSET 0xd80 112549985eeSRichard Cochran #define CPSW2_BD_OFFSET 0x2000 113549985eeSRichard Cochran 114df828598SMugunthan V N #define CPDMA_RXTHRESH 0x0c0 115df828598SMugunthan V N #define CPDMA_RXFREE 0x0e0 116df828598SMugunthan V N #define CPDMA_TXHDP 0x00 117df828598SMugunthan V N #define CPDMA_RXHDP 0x20 118df828598SMugunthan V N #define CPDMA_TXCP 0x40 119df828598SMugunthan V N #define CPDMA_RXCP 0x60 120df828598SMugunthan V N 121df828598SMugunthan V N #define CPSW_POLL_WEIGHT 64 122df828598SMugunthan V N #define CPSW_MIN_PACKET_SIZE 60 123df828598SMugunthan V N #define CPSW_MAX_PACKET_SIZE (1500 + 14 + 4 + 4) 124df828598SMugunthan V N 125df828598SMugunthan V N #define RX_PRIORITY_MAPPING 0x76543210 126df828598SMugunthan V N #define TX_PRIORITY_MAPPING 0x33221100 127e05107e6SIvan Khoronzhuk #define CPDMA_TX_PRIORITY_MAP 0x01234567 128df828598SMugunthan V N 1293b72c2feSMugunthan V N #define CPSW_VLAN_AWARE BIT(1) 1303b72c2feSMugunthan V N #define CPSW_ALE_VLAN_AWARE 1 1313b72c2feSMugunthan V N 13235717d8dSJohn Ogness #define CPSW_FIFO_NORMAL_MODE (0 << 16) 13335717d8dSJohn Ogness #define CPSW_FIFO_DUAL_MAC_MODE (1 << 16) 13435717d8dSJohn Ogness #define CPSW_FIFO_RATE_LIMIT_MODE (2 << 16) 135d9ba8f9eSMugunthan V N 136ff5b8ef2SMugunthan V N #define CPSW_INTPACEEN (0x3f << 16) 137ff5b8ef2SMugunthan V N #define CPSW_INTPRESCALE_MASK (0x7FF << 0) 138ff5b8ef2SMugunthan V N #define CPSW_CMINTMAX_CNT 63 139ff5b8ef2SMugunthan V N #define CPSW_CMINTMIN_CNT 2 140ff5b8ef2SMugunthan V N #define CPSW_CMINTMAX_INTVL (1000 / CPSW_CMINTMIN_CNT) 141ff5b8ef2SMugunthan V N #define CPSW_CMINTMIN_INTVL ((1000 / CPSW_CMINTMAX_CNT) + 1) 142ff5b8ef2SMugunthan V N 143606f3993SIvan Khoronzhuk #define cpsw_slave_index(cpsw, priv) \ 144606f3993SIvan Khoronzhuk ((cpsw->data.dual_emac) ? priv->emac_port : \ 145606f3993SIvan Khoronzhuk cpsw->data.active_slave) 146e38b5a3dSIvan Khoronzhuk #define IRQ_NUM 2 147e05107e6SIvan Khoronzhuk #define CPSW_MAX_QUEUES 8 148d3bb9c58SMugunthan V N 149df828598SMugunthan V N static int debug_level; 150df828598SMugunthan V N module_param(debug_level, int, 0); 151df828598SMugunthan V N MODULE_PARM_DESC(debug_level, "cpsw debug level (NETIF_MSG bits)"); 152df828598SMugunthan V N 153df828598SMugunthan V N static int ale_ageout = 10; 154df828598SMugunthan V N module_param(ale_ageout, int, 0); 155df828598SMugunthan V N MODULE_PARM_DESC(ale_ageout, "cpsw ale ageout interval (seconds)"); 156df828598SMugunthan V N 157df828598SMugunthan V N static int rx_packet_max = CPSW_MAX_PACKET_SIZE; 158df828598SMugunthan V N module_param(rx_packet_max, int, 0); 159df828598SMugunthan V N MODULE_PARM_DESC(rx_packet_max, "maximum receive packet size (bytes)"); 160df828598SMugunthan V N 161996a5c27SRichard Cochran struct cpsw_wr_regs { 162df828598SMugunthan V N u32 id_ver; 163df828598SMugunthan V N u32 soft_reset; 164df828598SMugunthan V N u32 control; 165df828598SMugunthan V N u32 int_control; 166df828598SMugunthan V N u32 rx_thresh_en; 167df828598SMugunthan V N u32 rx_en; 168df828598SMugunthan V N u32 tx_en; 169df828598SMugunthan V N u32 misc_en; 170ff5b8ef2SMugunthan V N u32 mem_allign1[8]; 171ff5b8ef2SMugunthan V N u32 rx_thresh_stat; 172ff5b8ef2SMugunthan V N u32 rx_stat; 173ff5b8ef2SMugunthan V N u32 tx_stat; 174ff5b8ef2SMugunthan V N u32 misc_stat; 175ff5b8ef2SMugunthan V N u32 mem_allign2[8]; 176ff5b8ef2SMugunthan V N u32 rx_imax; 177ff5b8ef2SMugunthan V N u32 tx_imax; 178ff5b8ef2SMugunthan V N 179df828598SMugunthan V N }; 180df828598SMugunthan V N 181996a5c27SRichard Cochran struct cpsw_ss_regs { 182df828598SMugunthan V N u32 id_ver; 183df828598SMugunthan V N u32 control; 184df828598SMugunthan V N u32 soft_reset; 185df828598SMugunthan V N u32 stat_port_en; 186df828598SMugunthan V N u32 ptype; 187bd357af2SRichard Cochran u32 soft_idle; 188bd357af2SRichard Cochran u32 thru_rate; 189bd357af2SRichard Cochran u32 gap_thresh; 190bd357af2SRichard Cochran u32 tx_start_wds; 191bd357af2SRichard Cochran u32 flow_control; 192bd357af2SRichard Cochran u32 vlan_ltype; 193bd357af2SRichard Cochran u32 ts_ltype; 194bd357af2SRichard Cochran u32 dlr_ltype; 195df828598SMugunthan V N }; 196df828598SMugunthan V N 1979750a3adSRichard Cochran /* CPSW_PORT_V1 */ 1989750a3adSRichard Cochran #define CPSW1_MAX_BLKS 0x00 /* Maximum FIFO Blocks */ 1999750a3adSRichard Cochran #define CPSW1_BLK_CNT 0x04 /* FIFO Block Usage Count (Read Only) */ 2009750a3adSRichard Cochran #define CPSW1_TX_IN_CTL 0x08 /* Transmit FIFO Control */ 2019750a3adSRichard Cochran #define CPSW1_PORT_VLAN 0x0c /* VLAN Register */ 2029750a3adSRichard Cochran #define CPSW1_TX_PRI_MAP 0x10 /* Tx Header Priority to Switch Pri Mapping */ 2039750a3adSRichard Cochran #define CPSW1_TS_CTL 0x14 /* Time Sync Control */ 2049750a3adSRichard Cochran #define CPSW1_TS_SEQ_LTYPE 0x18 /* Time Sync Sequence ID Offset and Msg Type */ 2059750a3adSRichard Cochran #define CPSW1_TS_VLAN 0x1c /* Time Sync VLAN1 and VLAN2 */ 2069750a3adSRichard Cochran 2079750a3adSRichard Cochran /* CPSW_PORT_V2 */ 2089750a3adSRichard Cochran #define CPSW2_CONTROL 0x00 /* Control Register */ 2099750a3adSRichard Cochran #define CPSW2_MAX_BLKS 0x08 /* Maximum FIFO Blocks */ 2109750a3adSRichard Cochran #define CPSW2_BLK_CNT 0x0c /* FIFO Block Usage Count (Read Only) */ 2119750a3adSRichard Cochran #define CPSW2_TX_IN_CTL 0x10 /* Transmit FIFO Control */ 2129750a3adSRichard Cochran #define CPSW2_PORT_VLAN 0x14 /* VLAN Register */ 2139750a3adSRichard Cochran #define CPSW2_TX_PRI_MAP 0x18 /* Tx Header Priority to Switch Pri Mapping */ 2149750a3adSRichard Cochran #define CPSW2_TS_SEQ_MTYPE 0x1c /* Time Sync Sequence ID Offset and Msg Type */ 2159750a3adSRichard Cochran 2169750a3adSRichard Cochran /* CPSW_PORT_V1 and V2 */ 2179750a3adSRichard Cochran #define SA_LO 0x20 /* CPGMAC_SL Source Address Low */ 2189750a3adSRichard Cochran #define SA_HI 0x24 /* CPGMAC_SL Source Address High */ 2199750a3adSRichard Cochran #define SEND_PERCENT 0x28 /* Transmit Queue Send Percentages */ 2209750a3adSRichard Cochran 2219750a3adSRichard Cochran /* CPSW_PORT_V2 only */ 2229750a3adSRichard Cochran #define RX_DSCP_PRI_MAP0 0x30 /* Rx DSCP Priority to Rx Packet Mapping */ 2239750a3adSRichard Cochran #define RX_DSCP_PRI_MAP1 0x34 /* Rx DSCP Priority to Rx Packet Mapping */ 2249750a3adSRichard Cochran #define RX_DSCP_PRI_MAP2 0x38 /* Rx DSCP Priority to Rx Packet Mapping */ 2259750a3adSRichard Cochran #define RX_DSCP_PRI_MAP3 0x3c /* Rx DSCP Priority to Rx Packet Mapping */ 2269750a3adSRichard Cochran #define RX_DSCP_PRI_MAP4 0x40 /* Rx DSCP Priority to Rx Packet Mapping */ 2279750a3adSRichard Cochran #define RX_DSCP_PRI_MAP5 0x44 /* Rx DSCP Priority to Rx Packet Mapping */ 2289750a3adSRichard Cochran #define RX_DSCP_PRI_MAP6 0x48 /* Rx DSCP Priority to Rx Packet Mapping */ 2299750a3adSRichard Cochran #define RX_DSCP_PRI_MAP7 0x4c /* Rx DSCP Priority to Rx Packet Mapping */ 2309750a3adSRichard Cochran 2319750a3adSRichard Cochran /* Bit definitions for the CPSW2_CONTROL register */ 2329750a3adSRichard Cochran #define PASS_PRI_TAGGED (1<<24) /* Pass Priority Tagged */ 2339750a3adSRichard Cochran #define VLAN_LTYPE2_EN (1<<21) /* VLAN LTYPE 2 enable */ 2349750a3adSRichard Cochran #define VLAN_LTYPE1_EN (1<<20) /* VLAN LTYPE 1 enable */ 2359750a3adSRichard Cochran #define DSCP_PRI_EN (1<<16) /* DSCP Priority Enable */ 2369750a3adSRichard Cochran #define TS_320 (1<<14) /* Time Sync Dest Port 320 enable */ 2379750a3adSRichard Cochran #define TS_319 (1<<13) /* Time Sync Dest Port 319 enable */ 2389750a3adSRichard Cochran #define TS_132 (1<<12) /* Time Sync Dest IP Addr 132 enable */ 2399750a3adSRichard Cochran #define TS_131 (1<<11) /* Time Sync Dest IP Addr 131 enable */ 2409750a3adSRichard Cochran #define TS_130 (1<<10) /* Time Sync Dest IP Addr 130 enable */ 2419750a3adSRichard Cochran #define TS_129 (1<<9) /* Time Sync Dest IP Addr 129 enable */ 24209c55372SGeorge Cherian #define TS_TTL_NONZERO (1<<8) /* Time Sync Time To Live Non-zero enable */ 24309c55372SGeorge Cherian #define TS_ANNEX_F_EN (1<<6) /* Time Sync Annex F enable */ 2449750a3adSRichard Cochran #define TS_ANNEX_D_EN (1<<4) /* Time Sync Annex D enable */ 2459750a3adSRichard Cochran #define TS_LTYPE2_EN (1<<3) /* Time Sync LTYPE 2 enable */ 2469750a3adSRichard Cochran #define TS_LTYPE1_EN (1<<2) /* Time Sync LTYPE 1 enable */ 2479750a3adSRichard Cochran #define TS_TX_EN (1<<1) /* Time Sync Transmit Enable */ 2489750a3adSRichard Cochran #define TS_RX_EN (1<<0) /* Time Sync Receive Enable */ 2499750a3adSRichard Cochran 25009c55372SGeorge Cherian #define CTRL_V2_TS_BITS \ 25109c55372SGeorge Cherian (TS_320 | TS_319 | TS_132 | TS_131 | TS_130 | TS_129 |\ 25209c55372SGeorge Cherian TS_TTL_NONZERO | TS_ANNEX_D_EN | TS_LTYPE1_EN) 2539750a3adSRichard Cochran 25409c55372SGeorge Cherian #define CTRL_V2_ALL_TS_MASK (CTRL_V2_TS_BITS | TS_TX_EN | TS_RX_EN) 25509c55372SGeorge Cherian #define CTRL_V2_TX_TS_BITS (CTRL_V2_TS_BITS | TS_TX_EN) 25609c55372SGeorge Cherian #define CTRL_V2_RX_TS_BITS (CTRL_V2_TS_BITS | TS_RX_EN) 25709c55372SGeorge Cherian 25809c55372SGeorge Cherian 25909c55372SGeorge Cherian #define CTRL_V3_TS_BITS \ 26009c55372SGeorge Cherian (TS_320 | TS_319 | TS_132 | TS_131 | TS_130 | TS_129 |\ 26109c55372SGeorge Cherian TS_TTL_NONZERO | TS_ANNEX_F_EN | TS_ANNEX_D_EN |\ 26209c55372SGeorge Cherian TS_LTYPE1_EN) 26309c55372SGeorge Cherian 26409c55372SGeorge Cherian #define CTRL_V3_ALL_TS_MASK (CTRL_V3_TS_BITS | TS_TX_EN | TS_RX_EN) 26509c55372SGeorge Cherian #define CTRL_V3_TX_TS_BITS (CTRL_V3_TS_BITS | TS_TX_EN) 26609c55372SGeorge Cherian #define CTRL_V3_RX_TS_BITS (CTRL_V3_TS_BITS | TS_RX_EN) 2679750a3adSRichard Cochran 2689750a3adSRichard Cochran /* Bit definitions for the CPSW2_TS_SEQ_MTYPE register */ 2699750a3adSRichard Cochran #define TS_SEQ_ID_OFFSET_SHIFT (16) /* Time Sync Sequence ID Offset */ 2709750a3adSRichard Cochran #define TS_SEQ_ID_OFFSET_MASK (0x3f) 2719750a3adSRichard Cochran #define TS_MSG_TYPE_EN_SHIFT (0) /* Time Sync Message Type Enable */ 2729750a3adSRichard Cochran #define TS_MSG_TYPE_EN_MASK (0xffff) 2739750a3adSRichard Cochran 2749750a3adSRichard Cochran /* The PTP event messages - Sync, Delay_Req, Pdelay_Req, and Pdelay_Resp. */ 2759750a3adSRichard Cochran #define EVENT_MSG_BITS ((1<<0) | (1<<1) | (1<<2) | (1<<3)) 276df828598SMugunthan V N 2772e5b38abSRichard Cochran /* Bit definitions for the CPSW1_TS_CTL register */ 2782e5b38abSRichard Cochran #define CPSW_V1_TS_RX_EN BIT(0) 2792e5b38abSRichard Cochran #define CPSW_V1_TS_TX_EN BIT(4) 2802e5b38abSRichard Cochran #define CPSW_V1_MSG_TYPE_OFS 16 2812e5b38abSRichard Cochran 2822e5b38abSRichard Cochran /* Bit definitions for the CPSW1_TS_SEQ_LTYPE register */ 2832e5b38abSRichard Cochran #define CPSW_V1_SEQ_ID_OFS_SHIFT 16 2842e5b38abSRichard Cochran 285df828598SMugunthan V N struct cpsw_host_regs { 286df828598SMugunthan V N u32 max_blks; 287df828598SMugunthan V N u32 blk_cnt; 288d9ba8f9eSMugunthan V N u32 tx_in_ctl; 289df828598SMugunthan V N u32 port_vlan; 290df828598SMugunthan V N u32 tx_pri_map; 291df828598SMugunthan V N u32 cpdma_tx_pri_map; 292df828598SMugunthan V N u32 cpdma_rx_chan_map; 293df828598SMugunthan V N }; 294df828598SMugunthan V N 295df828598SMugunthan V N struct cpsw_sliver_regs { 296df828598SMugunthan V N u32 id_ver; 297df828598SMugunthan V N u32 mac_control; 298df828598SMugunthan V N u32 mac_status; 299df828598SMugunthan V N u32 soft_reset; 300df828598SMugunthan V N u32 rx_maxlen; 301df828598SMugunthan V N u32 __reserved_0; 302df828598SMugunthan V N u32 rx_pause; 303df828598SMugunthan V N u32 tx_pause; 304df828598SMugunthan V N u32 __reserved_1; 305df828598SMugunthan V N u32 rx_pri_map; 306df828598SMugunthan V N }; 307df828598SMugunthan V N 308d9718546SMugunthan V N struct cpsw_hw_stats { 309d9718546SMugunthan V N u32 rxgoodframes; 310d9718546SMugunthan V N u32 rxbroadcastframes; 311d9718546SMugunthan V N u32 rxmulticastframes; 312d9718546SMugunthan V N u32 rxpauseframes; 313d9718546SMugunthan V N u32 rxcrcerrors; 314d9718546SMugunthan V N u32 rxaligncodeerrors; 315d9718546SMugunthan V N u32 rxoversizedframes; 316d9718546SMugunthan V N u32 rxjabberframes; 317d9718546SMugunthan V N u32 rxundersizedframes; 318d9718546SMugunthan V N u32 rxfragments; 319d9718546SMugunthan V N u32 __pad_0[2]; 320d9718546SMugunthan V N u32 rxoctets; 321d9718546SMugunthan V N u32 txgoodframes; 322d9718546SMugunthan V N u32 txbroadcastframes; 323d9718546SMugunthan V N u32 txmulticastframes; 324d9718546SMugunthan V N u32 txpauseframes; 325d9718546SMugunthan V N u32 txdeferredframes; 326d9718546SMugunthan V N u32 txcollisionframes; 327d9718546SMugunthan V N u32 txsinglecollframes; 328d9718546SMugunthan V N u32 txmultcollframes; 329d9718546SMugunthan V N u32 txexcessivecollisions; 330d9718546SMugunthan V N u32 txlatecollisions; 331d9718546SMugunthan V N u32 txunderrun; 332d9718546SMugunthan V N u32 txcarriersenseerrors; 333d9718546SMugunthan V N u32 txoctets; 334d9718546SMugunthan V N u32 octetframes64; 335d9718546SMugunthan V N u32 octetframes65t127; 336d9718546SMugunthan V N u32 octetframes128t255; 337d9718546SMugunthan V N u32 octetframes256t511; 338d9718546SMugunthan V N u32 octetframes512t1023; 339d9718546SMugunthan V N u32 octetframes1024tup; 340d9718546SMugunthan V N u32 netoctets; 341d9718546SMugunthan V N u32 rxsofoverruns; 342d9718546SMugunthan V N u32 rxmofoverruns; 343d9718546SMugunthan V N u32 rxdmaoverruns; 344d9718546SMugunthan V N }; 345d9718546SMugunthan V N 346df828598SMugunthan V N struct cpsw_slave { 3479750a3adSRichard Cochran void __iomem *regs; 348df828598SMugunthan V N struct cpsw_sliver_regs __iomem *sliver; 349df828598SMugunthan V N int slave_num; 350df828598SMugunthan V N u32 mac_control; 351df828598SMugunthan V N struct cpsw_slave_data *data; 352df828598SMugunthan V N struct phy_device *phy; 353d9ba8f9eSMugunthan V N struct net_device *ndev; 354d9ba8f9eSMugunthan V N u32 port_vlan; 355d9ba8f9eSMugunthan V N u32 open_stat; 356df828598SMugunthan V N }; 357df828598SMugunthan V N 3589750a3adSRichard Cochran static inline u32 slave_read(struct cpsw_slave *slave, u32 offset) 3599750a3adSRichard Cochran { 3609750a3adSRichard Cochran return __raw_readl(slave->regs + offset); 3619750a3adSRichard Cochran } 3629750a3adSRichard Cochran 3639750a3adSRichard Cochran static inline void slave_write(struct cpsw_slave *slave, u32 val, u32 offset) 3649750a3adSRichard Cochran { 3659750a3adSRichard Cochran __raw_writel(val, slave->regs + offset); 3669750a3adSRichard Cochran } 3679750a3adSRichard Cochran 3688feb0a19SIvan Khoronzhuk struct cpsw_vector { 3698feb0a19SIvan Khoronzhuk struct cpdma_chan *ch; 3708feb0a19SIvan Khoronzhuk int budget; 3718feb0a19SIvan Khoronzhuk }; 3728feb0a19SIvan Khoronzhuk 373649a1688SIvan Khoronzhuk struct cpsw_common { 37456e31bd8SIvan Khoronzhuk struct device *dev; 375606f3993SIvan Khoronzhuk struct cpsw_platform_data data; 376dbc4ec52SIvan Khoronzhuk struct napi_struct napi_rx; 377dbc4ec52SIvan Khoronzhuk struct napi_struct napi_tx; 3785d8d0d4dSIvan Khoronzhuk struct cpsw_ss_regs __iomem *regs; 3795d8d0d4dSIvan Khoronzhuk struct cpsw_wr_regs __iomem *wr_regs; 3805d8d0d4dSIvan Khoronzhuk u8 __iomem *hw_stats; 3815d8d0d4dSIvan Khoronzhuk struct cpsw_host_regs __iomem *host_port_regs; 3822a05a622SIvan Khoronzhuk u32 version; 3832a05a622SIvan Khoronzhuk u32 coal_intvl; 3842a05a622SIvan Khoronzhuk u32 bus_freq_mhz; 3852a05a622SIvan Khoronzhuk int rx_packet_max; 386606f3993SIvan Khoronzhuk struct cpsw_slave *slaves; 3872c836bd9SIvan Khoronzhuk struct cpdma_ctlr *dma; 3888feb0a19SIvan Khoronzhuk struct cpsw_vector txv[CPSW_MAX_QUEUES]; 3898feb0a19SIvan Khoronzhuk struct cpsw_vector rxv[CPSW_MAX_QUEUES]; 3902a05a622SIvan Khoronzhuk struct cpsw_ale *ale; 391e38b5a3dSIvan Khoronzhuk bool quirk_irq; 392e38b5a3dSIvan Khoronzhuk bool rx_irq_disabled; 393e38b5a3dSIvan Khoronzhuk bool tx_irq_disabled; 394e38b5a3dSIvan Khoronzhuk u32 irqs_table[IRQ_NUM]; 3952a05a622SIvan Khoronzhuk struct cpts *cpts; 396e05107e6SIvan Khoronzhuk int rx_ch_num, tx_ch_num; 397649a1688SIvan Khoronzhuk }; 398649a1688SIvan Khoronzhuk 399649a1688SIvan Khoronzhuk struct cpsw_priv { 400df828598SMugunthan V N struct net_device *ndev; 401df828598SMugunthan V N struct device *dev; 402df828598SMugunthan V N u32 msg_enable; 403df828598SMugunthan V N u8 mac_addr[ETH_ALEN]; 4041923d6e4SMugunthan V N bool rx_pause; 4051923d6e4SMugunthan V N bool tx_pause; 406d9ba8f9eSMugunthan V N u32 emac_port; 407649a1688SIvan Khoronzhuk struct cpsw_common *cpsw; 408df828598SMugunthan V N }; 409df828598SMugunthan V N 410d9718546SMugunthan V N struct cpsw_stats { 411d9718546SMugunthan V N char stat_string[ETH_GSTRING_LEN]; 412d9718546SMugunthan V N int type; 413d9718546SMugunthan V N int sizeof_stat; 414d9718546SMugunthan V N int stat_offset; 415d9718546SMugunthan V N }; 416d9718546SMugunthan V N 417d9718546SMugunthan V N enum { 418d9718546SMugunthan V N CPSW_STATS, 419d9718546SMugunthan V N CPDMA_RX_STATS, 420d9718546SMugunthan V N CPDMA_TX_STATS, 421d9718546SMugunthan V N }; 422d9718546SMugunthan V N 423d9718546SMugunthan V N #define CPSW_STAT(m) CPSW_STATS, \ 424d9718546SMugunthan V N sizeof(((struct cpsw_hw_stats *)0)->m), \ 425d9718546SMugunthan V N offsetof(struct cpsw_hw_stats, m) 426d9718546SMugunthan V N #define CPDMA_RX_STAT(m) CPDMA_RX_STATS, \ 427d9718546SMugunthan V N sizeof(((struct cpdma_chan_stats *)0)->m), \ 428d9718546SMugunthan V N offsetof(struct cpdma_chan_stats, m) 429d9718546SMugunthan V N #define CPDMA_TX_STAT(m) CPDMA_TX_STATS, \ 430d9718546SMugunthan V N sizeof(((struct cpdma_chan_stats *)0)->m), \ 431d9718546SMugunthan V N offsetof(struct cpdma_chan_stats, m) 432d9718546SMugunthan V N 433d9718546SMugunthan V N static const struct cpsw_stats cpsw_gstrings_stats[] = { 434d9718546SMugunthan V N { "Good Rx Frames", CPSW_STAT(rxgoodframes) }, 435d9718546SMugunthan V N { "Broadcast Rx Frames", CPSW_STAT(rxbroadcastframes) }, 436d9718546SMugunthan V N { "Multicast Rx Frames", CPSW_STAT(rxmulticastframes) }, 437d9718546SMugunthan V N { "Pause Rx Frames", CPSW_STAT(rxpauseframes) }, 438d9718546SMugunthan V N { "Rx CRC Errors", CPSW_STAT(rxcrcerrors) }, 439d9718546SMugunthan V N { "Rx Align/Code Errors", CPSW_STAT(rxaligncodeerrors) }, 440d9718546SMugunthan V N { "Oversize Rx Frames", CPSW_STAT(rxoversizedframes) }, 441d9718546SMugunthan V N { "Rx Jabbers", CPSW_STAT(rxjabberframes) }, 442d9718546SMugunthan V N { "Undersize (Short) Rx Frames", CPSW_STAT(rxundersizedframes) }, 443d9718546SMugunthan V N { "Rx Fragments", CPSW_STAT(rxfragments) }, 444d9718546SMugunthan V N { "Rx Octets", CPSW_STAT(rxoctets) }, 445d9718546SMugunthan V N { "Good Tx Frames", CPSW_STAT(txgoodframes) }, 446d9718546SMugunthan V N { "Broadcast Tx Frames", CPSW_STAT(txbroadcastframes) }, 447d9718546SMugunthan V N { "Multicast Tx Frames", CPSW_STAT(txmulticastframes) }, 448d9718546SMugunthan V N { "Pause Tx Frames", CPSW_STAT(txpauseframes) }, 449d9718546SMugunthan V N { "Deferred Tx Frames", CPSW_STAT(txdeferredframes) }, 450d9718546SMugunthan V N { "Collisions", CPSW_STAT(txcollisionframes) }, 451d9718546SMugunthan V N { "Single Collision Tx Frames", CPSW_STAT(txsinglecollframes) }, 452d9718546SMugunthan V N { "Multiple Collision Tx Frames", CPSW_STAT(txmultcollframes) }, 453d9718546SMugunthan V N { "Excessive Collisions", CPSW_STAT(txexcessivecollisions) }, 454d9718546SMugunthan V N { "Late Collisions", CPSW_STAT(txlatecollisions) }, 455d9718546SMugunthan V N { "Tx Underrun", CPSW_STAT(txunderrun) }, 456d9718546SMugunthan V N { "Carrier Sense Errors", CPSW_STAT(txcarriersenseerrors) }, 457d9718546SMugunthan V N { "Tx Octets", CPSW_STAT(txoctets) }, 458d9718546SMugunthan V N { "Rx + Tx 64 Octet Frames", CPSW_STAT(octetframes64) }, 459d9718546SMugunthan V N { "Rx + Tx 65-127 Octet Frames", CPSW_STAT(octetframes65t127) }, 460d9718546SMugunthan V N { "Rx + Tx 128-255 Octet Frames", CPSW_STAT(octetframes128t255) }, 461d9718546SMugunthan V N { "Rx + Tx 256-511 Octet Frames", CPSW_STAT(octetframes256t511) }, 462d9718546SMugunthan V N { "Rx + Tx 512-1023 Octet Frames", CPSW_STAT(octetframes512t1023) }, 463d9718546SMugunthan V N { "Rx + Tx 1024-Up Octet Frames", CPSW_STAT(octetframes1024tup) }, 464d9718546SMugunthan V N { "Net Octets", CPSW_STAT(netoctets) }, 465d9718546SMugunthan V N { "Rx Start of Frame Overruns", CPSW_STAT(rxsofoverruns) }, 466d9718546SMugunthan V N { "Rx Middle of Frame Overruns", CPSW_STAT(rxmofoverruns) }, 467d9718546SMugunthan V N { "Rx DMA Overruns", CPSW_STAT(rxdmaoverruns) }, 468d9718546SMugunthan V N }; 469d9718546SMugunthan V N 470e05107e6SIvan Khoronzhuk static const struct cpsw_stats cpsw_gstrings_ch_stats[] = { 471e05107e6SIvan Khoronzhuk { "head_enqueue", CPDMA_RX_STAT(head_enqueue) }, 472e05107e6SIvan Khoronzhuk { "tail_enqueue", CPDMA_RX_STAT(tail_enqueue) }, 473e05107e6SIvan Khoronzhuk { "pad_enqueue", CPDMA_RX_STAT(pad_enqueue) }, 474e05107e6SIvan Khoronzhuk { "misqueued", CPDMA_RX_STAT(misqueued) }, 475e05107e6SIvan Khoronzhuk { "desc_alloc_fail", CPDMA_RX_STAT(desc_alloc_fail) }, 476e05107e6SIvan Khoronzhuk { "pad_alloc_fail", CPDMA_RX_STAT(pad_alloc_fail) }, 477e05107e6SIvan Khoronzhuk { "runt_receive_buf", CPDMA_RX_STAT(runt_receive_buff) }, 478e05107e6SIvan Khoronzhuk { "runt_transmit_buf", CPDMA_RX_STAT(runt_transmit_buff) }, 479e05107e6SIvan Khoronzhuk { "empty_dequeue", CPDMA_RX_STAT(empty_dequeue) }, 480e05107e6SIvan Khoronzhuk { "busy_dequeue", CPDMA_RX_STAT(busy_dequeue) }, 481e05107e6SIvan Khoronzhuk { "good_dequeue", CPDMA_RX_STAT(good_dequeue) }, 482e05107e6SIvan Khoronzhuk { "requeue", CPDMA_RX_STAT(requeue) }, 483e05107e6SIvan Khoronzhuk { "teardown_dequeue", CPDMA_RX_STAT(teardown_dequeue) }, 484e05107e6SIvan Khoronzhuk }; 485e05107e6SIvan Khoronzhuk 486e05107e6SIvan Khoronzhuk #define CPSW_STATS_COMMON_LEN ARRAY_SIZE(cpsw_gstrings_stats) 487e05107e6SIvan Khoronzhuk #define CPSW_STATS_CH_LEN ARRAY_SIZE(cpsw_gstrings_ch_stats) 488d9718546SMugunthan V N 489649a1688SIvan Khoronzhuk #define ndev_to_cpsw(ndev) (((struct cpsw_priv *)netdev_priv(ndev))->cpsw) 490dbc4ec52SIvan Khoronzhuk #define napi_to_cpsw(napi) container_of(napi, struct cpsw_common, napi) 491df828598SMugunthan V N #define for_each_slave(priv, func, arg...) \ 492df828598SMugunthan V N do { \ 4936e6ceaedSSebastian Siewior struct cpsw_slave *slave; \ 494606f3993SIvan Khoronzhuk struct cpsw_common *cpsw = (priv)->cpsw; \ 4956e6ceaedSSebastian Siewior int n; \ 496606f3993SIvan Khoronzhuk if (cpsw->data.dual_emac) \ 497606f3993SIvan Khoronzhuk (func)((cpsw)->slaves + priv->emac_port, ##arg);\ 498d9ba8f9eSMugunthan V N else \ 499606f3993SIvan Khoronzhuk for (n = cpsw->data.slaves, \ 500606f3993SIvan Khoronzhuk slave = cpsw->slaves; \ 5016e6ceaedSSebastian Siewior n; n--) \ 5026e6ceaedSSebastian Siewior (func)(slave++, ##arg); \ 503df828598SMugunthan V N } while (0) 504d9ba8f9eSMugunthan V N 5052a05a622SIvan Khoronzhuk #define cpsw_dual_emac_src_port_detect(cpsw, status, ndev, skb) \ 506d9ba8f9eSMugunthan V N do { \ 507606f3993SIvan Khoronzhuk if (!cpsw->data.dual_emac) \ 508d9ba8f9eSMugunthan V N break; \ 509d9ba8f9eSMugunthan V N if (CPDMA_RX_SOURCE_PORT(status) == 1) { \ 510606f3993SIvan Khoronzhuk ndev = cpsw->slaves[0].ndev; \ 511d9ba8f9eSMugunthan V N skb->dev = ndev; \ 512d9ba8f9eSMugunthan V N } else if (CPDMA_RX_SOURCE_PORT(status) == 2) { \ 513606f3993SIvan Khoronzhuk ndev = cpsw->slaves[1].ndev; \ 514d9ba8f9eSMugunthan V N skb->dev = ndev; \ 515d9ba8f9eSMugunthan V N } \ 516d9ba8f9eSMugunthan V N } while (0) 517606f3993SIvan Khoronzhuk #define cpsw_add_mcast(cpsw, priv, addr) \ 518d9ba8f9eSMugunthan V N do { \ 519606f3993SIvan Khoronzhuk if (cpsw->data.dual_emac) { \ 520606f3993SIvan Khoronzhuk struct cpsw_slave *slave = cpsw->slaves + \ 521d9ba8f9eSMugunthan V N priv->emac_port; \ 5226f1f5836SIvan Khoronzhuk int slave_port = cpsw_get_slave_port( \ 523d9ba8f9eSMugunthan V N slave->slave_num); \ 5242a05a622SIvan Khoronzhuk cpsw_ale_add_mcast(cpsw->ale, addr, \ 52571a2cbb7SGrygorii Strashko 1 << slave_port | ALE_PORT_HOST, \ 526d9ba8f9eSMugunthan V N ALE_VLAN, slave->port_vlan, 0); \ 527d9ba8f9eSMugunthan V N } else { \ 5282a05a622SIvan Khoronzhuk cpsw_ale_add_mcast(cpsw->ale, addr, \ 52961f1cef9SGrygorii Strashko ALE_ALL_PORTS, \ 530d9ba8f9eSMugunthan V N 0, 0, 0); \ 531d9ba8f9eSMugunthan V N } \ 532d9ba8f9eSMugunthan V N } while (0) 533d9ba8f9eSMugunthan V N 5346f1f5836SIvan Khoronzhuk static inline int cpsw_get_slave_port(u32 slave_num) 535d9ba8f9eSMugunthan V N { 536d9ba8f9eSMugunthan V N return slave_num + 1; 537d9ba8f9eSMugunthan V N } 538df828598SMugunthan V N 5390cd8f9ccSMugunthan V N static void cpsw_set_promiscious(struct net_device *ndev, bool enable) 5400cd8f9ccSMugunthan V N { 5412a05a622SIvan Khoronzhuk struct cpsw_common *cpsw = ndev_to_cpsw(ndev); 5422a05a622SIvan Khoronzhuk struct cpsw_ale *ale = cpsw->ale; 5430cd8f9ccSMugunthan V N int i; 5440cd8f9ccSMugunthan V N 545606f3993SIvan Khoronzhuk if (cpsw->data.dual_emac) { 5460cd8f9ccSMugunthan V N bool flag = false; 5470cd8f9ccSMugunthan V N 5480cd8f9ccSMugunthan V N /* Enabling promiscuous mode for one interface will be 5490cd8f9ccSMugunthan V N * common for both the interface as the interface shares 5500cd8f9ccSMugunthan V N * the same hardware resource. 5510cd8f9ccSMugunthan V N */ 552606f3993SIvan Khoronzhuk for (i = 0; i < cpsw->data.slaves; i++) 553606f3993SIvan Khoronzhuk if (cpsw->slaves[i].ndev->flags & IFF_PROMISC) 5540cd8f9ccSMugunthan V N flag = true; 5550cd8f9ccSMugunthan V N 5560cd8f9ccSMugunthan V N if (!enable && flag) { 5570cd8f9ccSMugunthan V N enable = true; 5580cd8f9ccSMugunthan V N dev_err(&ndev->dev, "promiscuity not disabled as the other interface is still in promiscuity mode\n"); 5590cd8f9ccSMugunthan V N } 5600cd8f9ccSMugunthan V N 5610cd8f9ccSMugunthan V N if (enable) { 5620cd8f9ccSMugunthan V N /* Enable Bypass */ 5630cd8f9ccSMugunthan V N cpsw_ale_control_set(ale, 0, ALE_BYPASS, 1); 5640cd8f9ccSMugunthan V N 5650cd8f9ccSMugunthan V N dev_dbg(&ndev->dev, "promiscuity enabled\n"); 5660cd8f9ccSMugunthan V N } else { 5670cd8f9ccSMugunthan V N /* Disable Bypass */ 5680cd8f9ccSMugunthan V N cpsw_ale_control_set(ale, 0, ALE_BYPASS, 0); 5690cd8f9ccSMugunthan V N dev_dbg(&ndev->dev, "promiscuity disabled\n"); 5700cd8f9ccSMugunthan V N } 5710cd8f9ccSMugunthan V N } else { 5720cd8f9ccSMugunthan V N if (enable) { 5730cd8f9ccSMugunthan V N unsigned long timeout = jiffies + HZ; 5740cd8f9ccSMugunthan V N 5756f979eb3SLennart Sorensen /* Disable Learn for all ports (host is port 0 and slaves are port 1 and up */ 576606f3993SIvan Khoronzhuk for (i = 0; i <= cpsw->data.slaves; i++) { 5770cd8f9ccSMugunthan V N cpsw_ale_control_set(ale, i, 5780cd8f9ccSMugunthan V N ALE_PORT_NOLEARN, 1); 5790cd8f9ccSMugunthan V N cpsw_ale_control_set(ale, i, 5800cd8f9ccSMugunthan V N ALE_PORT_NO_SA_UPDATE, 1); 5810cd8f9ccSMugunthan V N } 5820cd8f9ccSMugunthan V N 5830cd8f9ccSMugunthan V N /* Clear All Untouched entries */ 5840cd8f9ccSMugunthan V N cpsw_ale_control_set(ale, 0, ALE_AGEOUT, 1); 5850cd8f9ccSMugunthan V N do { 5860cd8f9ccSMugunthan V N cpu_relax(); 5870cd8f9ccSMugunthan V N if (cpsw_ale_control_get(ale, 0, ALE_AGEOUT)) 5880cd8f9ccSMugunthan V N break; 5890cd8f9ccSMugunthan V N } while (time_after(timeout, jiffies)); 5900cd8f9ccSMugunthan V N cpsw_ale_control_set(ale, 0, ALE_AGEOUT, 1); 5910cd8f9ccSMugunthan V N 5920cd8f9ccSMugunthan V N /* Clear all mcast from ALE */ 59361f1cef9SGrygorii Strashko cpsw_ale_flush_multicast(ale, ALE_ALL_PORTS, -1); 5940cd8f9ccSMugunthan V N 5950cd8f9ccSMugunthan V N /* Flood All Unicast Packets to Host port */ 5960cd8f9ccSMugunthan V N cpsw_ale_control_set(ale, 0, ALE_P0_UNI_FLOOD, 1); 5970cd8f9ccSMugunthan V N dev_dbg(&ndev->dev, "promiscuity enabled\n"); 5980cd8f9ccSMugunthan V N } else { 5996f979eb3SLennart Sorensen /* Don't Flood All Unicast Packets to Host port */ 6000cd8f9ccSMugunthan V N cpsw_ale_control_set(ale, 0, ALE_P0_UNI_FLOOD, 0); 6010cd8f9ccSMugunthan V N 6026f979eb3SLennart Sorensen /* Enable Learn for all ports (host is port 0 and slaves are port 1 and up */ 603606f3993SIvan Khoronzhuk for (i = 0; i <= cpsw->data.slaves; i++) { 6040cd8f9ccSMugunthan V N cpsw_ale_control_set(ale, i, 6050cd8f9ccSMugunthan V N ALE_PORT_NOLEARN, 0); 6060cd8f9ccSMugunthan V N cpsw_ale_control_set(ale, i, 6070cd8f9ccSMugunthan V N ALE_PORT_NO_SA_UPDATE, 0); 6080cd8f9ccSMugunthan V N } 6090cd8f9ccSMugunthan V N dev_dbg(&ndev->dev, "promiscuity disabled\n"); 6100cd8f9ccSMugunthan V N } 6110cd8f9ccSMugunthan V N } 6120cd8f9ccSMugunthan V N } 6130cd8f9ccSMugunthan V N 6145c50a856SMugunthan V N static void cpsw_ndo_set_rx_mode(struct net_device *ndev) 6155c50a856SMugunthan V N { 6165c50a856SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 617606f3993SIvan Khoronzhuk struct cpsw_common *cpsw = priv->cpsw; 61825906052SMugunthan V N int vid; 61925906052SMugunthan V N 620606f3993SIvan Khoronzhuk if (cpsw->data.dual_emac) 621606f3993SIvan Khoronzhuk vid = cpsw->slaves[priv->emac_port].port_vlan; 62225906052SMugunthan V N else 623606f3993SIvan Khoronzhuk vid = cpsw->data.default_vlan; 6245c50a856SMugunthan V N 6255c50a856SMugunthan V N if (ndev->flags & IFF_PROMISC) { 6265c50a856SMugunthan V N /* Enable promiscuous mode */ 6270cd8f9ccSMugunthan V N cpsw_set_promiscious(ndev, true); 6282a05a622SIvan Khoronzhuk cpsw_ale_set_allmulti(cpsw->ale, IFF_ALLMULTI); 6295c50a856SMugunthan V N return; 6300cd8f9ccSMugunthan V N } else { 6310cd8f9ccSMugunthan V N /* Disable promiscuous mode */ 6320cd8f9ccSMugunthan V N cpsw_set_promiscious(ndev, false); 6335c50a856SMugunthan V N } 6345c50a856SMugunthan V N 6351e5c4bc4SLennart Sorensen /* Restore allmulti on vlans if necessary */ 6362a05a622SIvan Khoronzhuk cpsw_ale_set_allmulti(cpsw->ale, priv->ndev->flags & IFF_ALLMULTI); 6371e5c4bc4SLennart Sorensen 6385c50a856SMugunthan V N /* Clear all mcast from ALE */ 6392a05a622SIvan Khoronzhuk cpsw_ale_flush_multicast(cpsw->ale, ALE_ALL_PORTS, vid); 6405c50a856SMugunthan V N 6415c50a856SMugunthan V N if (!netdev_mc_empty(ndev)) { 6425c50a856SMugunthan V N struct netdev_hw_addr *ha; 6435c50a856SMugunthan V N 6445c50a856SMugunthan V N /* program multicast address list into ALE register */ 6455c50a856SMugunthan V N netdev_for_each_mc_addr(ha, ndev) { 646606f3993SIvan Khoronzhuk cpsw_add_mcast(cpsw, priv, (u8 *)ha->addr); 6475c50a856SMugunthan V N } 6485c50a856SMugunthan V N } 6495c50a856SMugunthan V N } 6505c50a856SMugunthan V N 6512c836bd9SIvan Khoronzhuk static void cpsw_intr_enable(struct cpsw_common *cpsw) 652df828598SMugunthan V N { 6535d8d0d4dSIvan Khoronzhuk __raw_writel(0xFF, &cpsw->wr_regs->tx_en); 6545d8d0d4dSIvan Khoronzhuk __raw_writel(0xFF, &cpsw->wr_regs->rx_en); 655df828598SMugunthan V N 6562c836bd9SIvan Khoronzhuk cpdma_ctlr_int_ctrl(cpsw->dma, true); 657df828598SMugunthan V N return; 658df828598SMugunthan V N } 659df828598SMugunthan V N 6602c836bd9SIvan Khoronzhuk static void cpsw_intr_disable(struct cpsw_common *cpsw) 661df828598SMugunthan V N { 6625d8d0d4dSIvan Khoronzhuk __raw_writel(0, &cpsw->wr_regs->tx_en); 6635d8d0d4dSIvan Khoronzhuk __raw_writel(0, &cpsw->wr_regs->rx_en); 664df828598SMugunthan V N 6652c836bd9SIvan Khoronzhuk cpdma_ctlr_int_ctrl(cpsw->dma, false); 666df828598SMugunthan V N return; 667df828598SMugunthan V N } 668df828598SMugunthan V N 6691a3b5056SOlof Johansson static void cpsw_tx_handler(void *token, int len, int status) 670df828598SMugunthan V N { 671e05107e6SIvan Khoronzhuk struct netdev_queue *txq; 672df828598SMugunthan V N struct sk_buff *skb = token; 673df828598SMugunthan V N struct net_device *ndev = skb->dev; 6742a05a622SIvan Khoronzhuk struct cpsw_common *cpsw = ndev_to_cpsw(ndev); 675df828598SMugunthan V N 676fae50823SMugunthan V N /* Check whether the queue is stopped due to stalled tx dma, if the 677fae50823SMugunthan V N * queue is stopped then start the queue as we have free desc for tx 678fae50823SMugunthan V N */ 679e05107e6SIvan Khoronzhuk txq = netdev_get_tx_queue(ndev, skb_get_queue_mapping(skb)); 680e05107e6SIvan Khoronzhuk if (unlikely(netif_tx_queue_stopped(txq))) 681e05107e6SIvan Khoronzhuk netif_tx_wake_queue(txq); 682e05107e6SIvan Khoronzhuk 6832a05a622SIvan Khoronzhuk cpts_tx_timestamp(cpsw->cpts, skb); 6848dc43ddcSTobias Klauser ndev->stats.tx_packets++; 6858dc43ddcSTobias Klauser ndev->stats.tx_bytes += len; 686df828598SMugunthan V N dev_kfree_skb_any(skb); 687df828598SMugunthan V N } 688df828598SMugunthan V N 6891a3b5056SOlof Johansson static void cpsw_rx_handler(void *token, int len, int status) 690df828598SMugunthan V N { 691e05107e6SIvan Khoronzhuk struct cpdma_chan *ch; 692df828598SMugunthan V N struct sk_buff *skb = token; 693b4727e69SSebastian Siewior struct sk_buff *new_skb; 694df828598SMugunthan V N struct net_device *ndev = skb->dev; 695df828598SMugunthan V N int ret = 0; 6962a05a622SIvan Khoronzhuk struct cpsw_common *cpsw = ndev_to_cpsw(ndev); 697df828598SMugunthan V N 6982a05a622SIvan Khoronzhuk cpsw_dual_emac_src_port_detect(cpsw, status, ndev, skb); 699d9ba8f9eSMugunthan V N 70016e5c57dSMugunthan V N if (unlikely(status < 0) || unlikely(!netif_running(ndev))) { 701a0e2c822SMugunthan V N bool ndev_status = false; 702606f3993SIvan Khoronzhuk struct cpsw_slave *slave = cpsw->slaves; 703a0e2c822SMugunthan V N int n; 704a0e2c822SMugunthan V N 705606f3993SIvan Khoronzhuk if (cpsw->data.dual_emac) { 706a0e2c822SMugunthan V N /* In dual emac mode check for all interfaces */ 707606f3993SIvan Khoronzhuk for (n = cpsw->data.slaves; n; n--, slave++) 708a0e2c822SMugunthan V N if (netif_running(slave->ndev)) 709a0e2c822SMugunthan V N ndev_status = true; 710a0e2c822SMugunthan V N } 711a0e2c822SMugunthan V N 712a0e2c822SMugunthan V N if (ndev_status && (status >= 0)) { 713a0e2c822SMugunthan V N /* The packet received is for the interface which 714a0e2c822SMugunthan V N * is already down and the other interface is up 715dbedd44eSJoe Perches * and running, instead of freeing which results 716a0e2c822SMugunthan V N * in reducing of the number of rx descriptor in 717a0e2c822SMugunthan V N * DMA engine, requeue skb back to cpdma. 718a0e2c822SMugunthan V N */ 719a0e2c822SMugunthan V N new_skb = skb; 720a0e2c822SMugunthan V N goto requeue; 721a0e2c822SMugunthan V N } 722a0e2c822SMugunthan V N 723b4727e69SSebastian Siewior /* the interface is going down, skbs are purged */ 724df828598SMugunthan V N dev_kfree_skb_any(skb); 725df828598SMugunthan V N return; 726df828598SMugunthan V N } 727b4727e69SSebastian Siewior 7282a05a622SIvan Khoronzhuk new_skb = netdev_alloc_skb_ip_align(ndev, cpsw->rx_packet_max); 729b4727e69SSebastian Siewior if (new_skb) { 730e05107e6SIvan Khoronzhuk skb_copy_queue_mapping(new_skb, skb); 731df828598SMugunthan V N skb_put(skb, len); 7322a05a622SIvan Khoronzhuk cpts_rx_timestamp(cpsw->cpts, skb); 733df828598SMugunthan V N skb->protocol = eth_type_trans(skb, ndev); 734df828598SMugunthan V N netif_receive_skb(skb); 7358dc43ddcSTobias Klauser ndev->stats.rx_bytes += len; 7368dc43ddcSTobias Klauser ndev->stats.rx_packets++; 737254a49d5SGrygorii Strashko kmemleak_not_leak(new_skb); 738b4727e69SSebastian Siewior } else { 7398dc43ddcSTobias Klauser ndev->stats.rx_dropped++; 740b4727e69SSebastian Siewior new_skb = skb; 741df828598SMugunthan V N } 742df828598SMugunthan V N 743a0e2c822SMugunthan V N requeue: 744ce52c744SIvan Khoronzhuk if (netif_dormant(ndev)) { 745ce52c744SIvan Khoronzhuk dev_kfree_skb_any(new_skb); 746ce52c744SIvan Khoronzhuk return; 747ce52c744SIvan Khoronzhuk } 748ce52c744SIvan Khoronzhuk 7498feb0a19SIvan Khoronzhuk ch = cpsw->rxv[skb_get_queue_mapping(new_skb)].ch; 750e05107e6SIvan Khoronzhuk ret = cpdma_chan_submit(ch, new_skb, new_skb->data, 751b4727e69SSebastian Siewior skb_tailroom(new_skb), 0); 752b4727e69SSebastian Siewior if (WARN_ON(ret < 0)) 753b4727e69SSebastian Siewior dev_kfree_skb_any(new_skb); 754df828598SMugunthan V N } 755df828598SMugunthan V N 75632b78d85SIvan Khoronzhuk static void cpsw_split_res(struct net_device *ndev) 75748e0a83eSIvan Khoronzhuk { 75848e0a83eSIvan Khoronzhuk struct cpsw_priv *priv = netdev_priv(ndev); 75932b78d85SIvan Khoronzhuk u32 consumed_rate = 0, bigest_rate = 0; 76048e0a83eSIvan Khoronzhuk struct cpsw_common *cpsw = priv->cpsw; 76148e0a83eSIvan Khoronzhuk struct cpsw_vector *txv = cpsw->txv; 76232b78d85SIvan Khoronzhuk int i, ch_weight, rlim_ch_num = 0; 76348e0a83eSIvan Khoronzhuk int budget, bigest_rate_ch = 0; 76448e0a83eSIvan Khoronzhuk struct cpsw_slave *slave; 76548e0a83eSIvan Khoronzhuk u32 ch_rate, max_rate; 76648e0a83eSIvan Khoronzhuk int ch_budget = 0; 76748e0a83eSIvan Khoronzhuk 76848e0a83eSIvan Khoronzhuk for (i = 0; i < cpsw->tx_ch_num; i++) { 76948e0a83eSIvan Khoronzhuk ch_rate = cpdma_chan_get_rate(txv[i].ch); 77048e0a83eSIvan Khoronzhuk if (!ch_rate) 77148e0a83eSIvan Khoronzhuk continue; 77248e0a83eSIvan Khoronzhuk 77348e0a83eSIvan Khoronzhuk rlim_ch_num++; 77448e0a83eSIvan Khoronzhuk consumed_rate += ch_rate; 77548e0a83eSIvan Khoronzhuk } 77648e0a83eSIvan Khoronzhuk 77748e0a83eSIvan Khoronzhuk if (cpsw->tx_ch_num == rlim_ch_num) { 77848e0a83eSIvan Khoronzhuk max_rate = consumed_rate; 77932b78d85SIvan Khoronzhuk } else if (!rlim_ch_num) { 78032b78d85SIvan Khoronzhuk ch_budget = CPSW_POLL_WEIGHT / cpsw->tx_ch_num; 78132b78d85SIvan Khoronzhuk bigest_rate = 0; 78232b78d85SIvan Khoronzhuk max_rate = consumed_rate; 78348e0a83eSIvan Khoronzhuk } else { 78432b78d85SIvan Khoronzhuk slave = &cpsw->slaves[cpsw_slave_index(cpsw, priv)]; 78532b78d85SIvan Khoronzhuk max_rate = slave->phy->speed * 1000; 78632b78d85SIvan Khoronzhuk 78748e0a83eSIvan Khoronzhuk ch_budget = (consumed_rate * CPSW_POLL_WEIGHT) / max_rate; 78848e0a83eSIvan Khoronzhuk ch_budget = (CPSW_POLL_WEIGHT - ch_budget) / 78948e0a83eSIvan Khoronzhuk (cpsw->tx_ch_num - rlim_ch_num); 79048e0a83eSIvan Khoronzhuk bigest_rate = (max_rate - consumed_rate) / 79148e0a83eSIvan Khoronzhuk (cpsw->tx_ch_num - rlim_ch_num); 79248e0a83eSIvan Khoronzhuk } 79348e0a83eSIvan Khoronzhuk 79432b78d85SIvan Khoronzhuk /* split tx weight/budget */ 79548e0a83eSIvan Khoronzhuk budget = CPSW_POLL_WEIGHT; 79648e0a83eSIvan Khoronzhuk for (i = 0; i < cpsw->tx_ch_num; i++) { 79748e0a83eSIvan Khoronzhuk ch_rate = cpdma_chan_get_rate(txv[i].ch); 79848e0a83eSIvan Khoronzhuk if (ch_rate) { 79948e0a83eSIvan Khoronzhuk txv[i].budget = (ch_rate * CPSW_POLL_WEIGHT) / max_rate; 80048e0a83eSIvan Khoronzhuk if (!txv[i].budget) 80132b78d85SIvan Khoronzhuk txv[i].budget++; 80248e0a83eSIvan Khoronzhuk if (ch_rate > bigest_rate) { 80348e0a83eSIvan Khoronzhuk bigest_rate_ch = i; 80448e0a83eSIvan Khoronzhuk bigest_rate = ch_rate; 80548e0a83eSIvan Khoronzhuk } 80632b78d85SIvan Khoronzhuk 80732b78d85SIvan Khoronzhuk ch_weight = (ch_rate * 100) / max_rate; 80832b78d85SIvan Khoronzhuk if (!ch_weight) 80932b78d85SIvan Khoronzhuk ch_weight++; 81032b78d85SIvan Khoronzhuk cpdma_chan_set_weight(cpsw->txv[i].ch, ch_weight); 81148e0a83eSIvan Khoronzhuk } else { 81248e0a83eSIvan Khoronzhuk txv[i].budget = ch_budget; 81348e0a83eSIvan Khoronzhuk if (!bigest_rate_ch) 81448e0a83eSIvan Khoronzhuk bigest_rate_ch = i; 81532b78d85SIvan Khoronzhuk cpdma_chan_set_weight(cpsw->txv[i].ch, 0); 81648e0a83eSIvan Khoronzhuk } 81748e0a83eSIvan Khoronzhuk 81848e0a83eSIvan Khoronzhuk budget -= txv[i].budget; 81948e0a83eSIvan Khoronzhuk } 82048e0a83eSIvan Khoronzhuk 82148e0a83eSIvan Khoronzhuk if (budget) 82248e0a83eSIvan Khoronzhuk txv[bigest_rate_ch].budget += budget; 82348e0a83eSIvan Khoronzhuk 82448e0a83eSIvan Khoronzhuk /* split rx budget */ 82548e0a83eSIvan Khoronzhuk budget = CPSW_POLL_WEIGHT; 82648e0a83eSIvan Khoronzhuk ch_budget = budget / cpsw->rx_ch_num; 82748e0a83eSIvan Khoronzhuk for (i = 0; i < cpsw->rx_ch_num; i++) { 82848e0a83eSIvan Khoronzhuk cpsw->rxv[i].budget = ch_budget; 82948e0a83eSIvan Khoronzhuk budget -= ch_budget; 83048e0a83eSIvan Khoronzhuk } 83148e0a83eSIvan Khoronzhuk 83248e0a83eSIvan Khoronzhuk if (budget) 83348e0a83eSIvan Khoronzhuk cpsw->rxv[0].budget += budget; 83448e0a83eSIvan Khoronzhuk } 83548e0a83eSIvan Khoronzhuk 836c03abd84SFelipe Balbi static irqreturn_t cpsw_tx_interrupt(int irq, void *dev_id) 837df828598SMugunthan V N { 838dbc4ec52SIvan Khoronzhuk struct cpsw_common *cpsw = dev_id; 8397ce67a38SFelipe Balbi 8405d8d0d4dSIvan Khoronzhuk writel(0, &cpsw->wr_regs->tx_en); 8412c836bd9SIvan Khoronzhuk cpdma_ctlr_eoi(cpsw->dma, CPDMA_EOI_TX); 842c03abd84SFelipe Balbi 843e38b5a3dSIvan Khoronzhuk if (cpsw->quirk_irq) { 844e38b5a3dSIvan Khoronzhuk disable_irq_nosync(cpsw->irqs_table[1]); 845e38b5a3dSIvan Khoronzhuk cpsw->tx_irq_disabled = true; 8467da11600SMugunthan V N } 8477da11600SMugunthan V N 848dbc4ec52SIvan Khoronzhuk napi_schedule(&cpsw->napi_tx); 849c03abd84SFelipe Balbi return IRQ_HANDLED; 850c03abd84SFelipe Balbi } 851c03abd84SFelipe Balbi 852c03abd84SFelipe Balbi static irqreturn_t cpsw_rx_interrupt(int irq, void *dev_id) 853c03abd84SFelipe Balbi { 854dbc4ec52SIvan Khoronzhuk struct cpsw_common *cpsw = dev_id; 855c03abd84SFelipe Balbi 8562c836bd9SIvan Khoronzhuk cpdma_ctlr_eoi(cpsw->dma, CPDMA_EOI_RX); 8575d8d0d4dSIvan Khoronzhuk writel(0, &cpsw->wr_regs->rx_en); 858fd51cf19SSebastian Siewior 859e38b5a3dSIvan Khoronzhuk if (cpsw->quirk_irq) { 860e38b5a3dSIvan Khoronzhuk disable_irq_nosync(cpsw->irqs_table[0]); 861e38b5a3dSIvan Khoronzhuk cpsw->rx_irq_disabled = true; 8627da11600SMugunthan V N } 8637da11600SMugunthan V N 864dbc4ec52SIvan Khoronzhuk napi_schedule(&cpsw->napi_rx); 865df828598SMugunthan V N return IRQ_HANDLED; 866df828598SMugunthan V N } 867df828598SMugunthan V N 86832a7432cSMugunthan V N static int cpsw_tx_poll(struct napi_struct *napi_tx, int budget) 869df828598SMugunthan V N { 870e05107e6SIvan Khoronzhuk u32 ch_map; 8718feb0a19SIvan Khoronzhuk int num_tx, cur_budget, ch; 872dbc4ec52SIvan Khoronzhuk struct cpsw_common *cpsw = napi_to_cpsw(napi_tx); 8738feb0a19SIvan Khoronzhuk struct cpsw_vector *txv; 87432a7432cSMugunthan V N 875e05107e6SIvan Khoronzhuk /* process every unprocessed channel */ 876e05107e6SIvan Khoronzhuk ch_map = cpdma_ctrl_txchs_state(cpsw->dma); 877342934a5SIvan Khoronzhuk for (ch = 0, num_tx = 0; ch_map; ch_map >>= 1, ch++) { 878e05107e6SIvan Khoronzhuk if (!(ch_map & 0x01)) 879e05107e6SIvan Khoronzhuk continue; 880e05107e6SIvan Khoronzhuk 8818feb0a19SIvan Khoronzhuk txv = &cpsw->txv[ch]; 8828feb0a19SIvan Khoronzhuk if (unlikely(txv->budget > budget - num_tx)) 8838feb0a19SIvan Khoronzhuk cur_budget = budget - num_tx; 8848feb0a19SIvan Khoronzhuk else 8858feb0a19SIvan Khoronzhuk cur_budget = txv->budget; 8868feb0a19SIvan Khoronzhuk 8878feb0a19SIvan Khoronzhuk num_tx += cpdma_chan_process(txv->ch, cur_budget); 888342934a5SIvan Khoronzhuk if (num_tx >= budget) 889342934a5SIvan Khoronzhuk break; 890e05107e6SIvan Khoronzhuk } 891e05107e6SIvan Khoronzhuk 89232a7432cSMugunthan V N if (num_tx < budget) { 89332a7432cSMugunthan V N napi_complete(napi_tx); 8945d8d0d4dSIvan Khoronzhuk writel(0xff, &cpsw->wr_regs->tx_en); 895e38b5a3dSIvan Khoronzhuk if (cpsw->quirk_irq && cpsw->tx_irq_disabled) { 896e38b5a3dSIvan Khoronzhuk cpsw->tx_irq_disabled = false; 897e38b5a3dSIvan Khoronzhuk enable_irq(cpsw->irqs_table[1]); 8987da11600SMugunthan V N } 89932a7432cSMugunthan V N } 90032a7432cSMugunthan V N 90132a7432cSMugunthan V N return num_tx; 90232a7432cSMugunthan V N } 90332a7432cSMugunthan V N 90432a7432cSMugunthan V N static int cpsw_rx_poll(struct napi_struct *napi_rx, int budget) 90532a7432cSMugunthan V N { 906e05107e6SIvan Khoronzhuk u32 ch_map; 9078feb0a19SIvan Khoronzhuk int num_rx, cur_budget, ch; 908dbc4ec52SIvan Khoronzhuk struct cpsw_common *cpsw = napi_to_cpsw(napi_rx); 9098feb0a19SIvan Khoronzhuk struct cpsw_vector *rxv; 910510a1e72SMugunthan V N 911e05107e6SIvan Khoronzhuk /* process every unprocessed channel */ 912e05107e6SIvan Khoronzhuk ch_map = cpdma_ctrl_rxchs_state(cpsw->dma); 913342934a5SIvan Khoronzhuk for (ch = 0, num_rx = 0; ch_map; ch_map >>= 1, ch++) { 914e05107e6SIvan Khoronzhuk if (!(ch_map & 0x01)) 915e05107e6SIvan Khoronzhuk continue; 916e05107e6SIvan Khoronzhuk 9178feb0a19SIvan Khoronzhuk rxv = &cpsw->rxv[ch]; 9188feb0a19SIvan Khoronzhuk if (unlikely(rxv->budget > budget - num_rx)) 9198feb0a19SIvan Khoronzhuk cur_budget = budget - num_rx; 9208feb0a19SIvan Khoronzhuk else 9218feb0a19SIvan Khoronzhuk cur_budget = rxv->budget; 9228feb0a19SIvan Khoronzhuk 9238feb0a19SIvan Khoronzhuk num_rx += cpdma_chan_process(rxv->ch, cur_budget); 924342934a5SIvan Khoronzhuk if (num_rx >= budget) 925342934a5SIvan Khoronzhuk break; 926e05107e6SIvan Khoronzhuk } 927e05107e6SIvan Khoronzhuk 928510a1e72SMugunthan V N if (num_rx < budget) { 92932a7432cSMugunthan V N napi_complete(napi_rx); 9305d8d0d4dSIvan Khoronzhuk writel(0xff, &cpsw->wr_regs->rx_en); 931e38b5a3dSIvan Khoronzhuk if (cpsw->quirk_irq && cpsw->rx_irq_disabled) { 932e38b5a3dSIvan Khoronzhuk cpsw->rx_irq_disabled = false; 933e38b5a3dSIvan Khoronzhuk enable_irq(cpsw->irqs_table[0]); 9347da11600SMugunthan V N } 935510a1e72SMugunthan V N } 936df828598SMugunthan V N 937df828598SMugunthan V N return num_rx; 938df828598SMugunthan V N } 939df828598SMugunthan V N 940df828598SMugunthan V N static inline void soft_reset(const char *module, void __iomem *reg) 941df828598SMugunthan V N { 942df828598SMugunthan V N unsigned long timeout = jiffies + HZ; 943df828598SMugunthan V N 944df828598SMugunthan V N __raw_writel(1, reg); 945df828598SMugunthan V N do { 946df828598SMugunthan V N cpu_relax(); 947df828598SMugunthan V N } while ((__raw_readl(reg) & 1) && time_after(timeout, jiffies)); 948df828598SMugunthan V N 949df828598SMugunthan V N WARN(__raw_readl(reg) & 1, "failed to soft-reset %s\n", module); 950df828598SMugunthan V N } 951df828598SMugunthan V N 952df828598SMugunthan V N #define mac_hi(mac) (((mac)[0] << 0) | ((mac)[1] << 8) | \ 953df828598SMugunthan V N ((mac)[2] << 16) | ((mac)[3] << 24)) 954df828598SMugunthan V N #define mac_lo(mac) (((mac)[4] << 0) | ((mac)[5] << 8)) 955df828598SMugunthan V N 956df828598SMugunthan V N static void cpsw_set_slave_mac(struct cpsw_slave *slave, 957df828598SMugunthan V N struct cpsw_priv *priv) 958df828598SMugunthan V N { 9599750a3adSRichard Cochran slave_write(slave, mac_hi(priv->mac_addr), SA_HI); 9609750a3adSRichard Cochran slave_write(slave, mac_lo(priv->mac_addr), SA_LO); 961df828598SMugunthan V N } 962df828598SMugunthan V N 963df828598SMugunthan V N static void _cpsw_adjust_link(struct cpsw_slave *slave, 964df828598SMugunthan V N struct cpsw_priv *priv, bool *link) 965df828598SMugunthan V N { 966df828598SMugunthan V N struct phy_device *phy = slave->phy; 967df828598SMugunthan V N u32 mac_control = 0; 968df828598SMugunthan V N u32 slave_port; 969606f3993SIvan Khoronzhuk struct cpsw_common *cpsw = priv->cpsw; 970df828598SMugunthan V N 971df828598SMugunthan V N if (!phy) 972df828598SMugunthan V N return; 973df828598SMugunthan V N 9746f1f5836SIvan Khoronzhuk slave_port = cpsw_get_slave_port(slave->slave_num); 975df828598SMugunthan V N 976df828598SMugunthan V N if (phy->link) { 977606f3993SIvan Khoronzhuk mac_control = cpsw->data.mac_control; 978df828598SMugunthan V N 979df828598SMugunthan V N /* enable forwarding */ 9802a05a622SIvan Khoronzhuk cpsw_ale_control_set(cpsw->ale, slave_port, 981df828598SMugunthan V N ALE_PORT_STATE, ALE_PORT_STATE_FORWARD); 982df828598SMugunthan V N 983df828598SMugunthan V N if (phy->speed == 1000) 984df828598SMugunthan V N mac_control |= BIT(7); /* GIGABITEN */ 985df828598SMugunthan V N if (phy->duplex) 986df828598SMugunthan V N mac_control |= BIT(0); /* FULLDUPLEXEN */ 987342b7b74SDaniel Mack 988342b7b74SDaniel Mack /* set speed_in input in case RMII mode is used in 100Mbps */ 989342b7b74SDaniel Mack if (phy->speed == 100) 990342b7b74SDaniel Mack mac_control |= BIT(15); 991a81d8762SMugunthan V N else if (phy->speed == 10) 992a81d8762SMugunthan V N mac_control |= BIT(18); /* In Band mode */ 993342b7b74SDaniel Mack 9941923d6e4SMugunthan V N if (priv->rx_pause) 9951923d6e4SMugunthan V N mac_control |= BIT(3); 9961923d6e4SMugunthan V N 9971923d6e4SMugunthan V N if (priv->tx_pause) 9981923d6e4SMugunthan V N mac_control |= BIT(4); 9991923d6e4SMugunthan V N 1000df828598SMugunthan V N *link = true; 1001df828598SMugunthan V N } else { 1002df828598SMugunthan V N mac_control = 0; 1003df828598SMugunthan V N /* disable forwarding */ 10042a05a622SIvan Khoronzhuk cpsw_ale_control_set(cpsw->ale, slave_port, 1005df828598SMugunthan V N ALE_PORT_STATE, ALE_PORT_STATE_DISABLE); 1006df828598SMugunthan V N } 1007df828598SMugunthan V N 1008df828598SMugunthan V N if (mac_control != slave->mac_control) { 1009df828598SMugunthan V N phy_print_status(phy); 1010df828598SMugunthan V N __raw_writel(mac_control, &slave->sliver->mac_control); 1011df828598SMugunthan V N } 1012df828598SMugunthan V N 1013df828598SMugunthan V N slave->mac_control = mac_control; 1014df828598SMugunthan V N } 1015df828598SMugunthan V N 1016df828598SMugunthan V N static void cpsw_adjust_link(struct net_device *ndev) 1017df828598SMugunthan V N { 1018df828598SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 1019df828598SMugunthan V N bool link = false; 1020df828598SMugunthan V N 1021df828598SMugunthan V N for_each_slave(priv, _cpsw_adjust_link, priv, &link); 1022df828598SMugunthan V N 1023df828598SMugunthan V N if (link) { 102432b78d85SIvan Khoronzhuk cpsw_split_res(priv->ndev); 1025df828598SMugunthan V N netif_carrier_on(ndev); 1026df828598SMugunthan V N if (netif_running(ndev)) 1027e05107e6SIvan Khoronzhuk netif_tx_wake_all_queues(ndev); 1028df828598SMugunthan V N } else { 1029df828598SMugunthan V N netif_carrier_off(ndev); 1030e05107e6SIvan Khoronzhuk netif_tx_stop_all_queues(ndev); 1031df828598SMugunthan V N } 1032df828598SMugunthan V N } 1033df828598SMugunthan V N 1034ff5b8ef2SMugunthan V N static int cpsw_get_coalesce(struct net_device *ndev, 1035ff5b8ef2SMugunthan V N struct ethtool_coalesce *coal) 1036ff5b8ef2SMugunthan V N { 10372a05a622SIvan Khoronzhuk struct cpsw_common *cpsw = ndev_to_cpsw(ndev); 1038ff5b8ef2SMugunthan V N 10392a05a622SIvan Khoronzhuk coal->rx_coalesce_usecs = cpsw->coal_intvl; 1040ff5b8ef2SMugunthan V N return 0; 1041ff5b8ef2SMugunthan V N } 1042ff5b8ef2SMugunthan V N 1043ff5b8ef2SMugunthan V N static int cpsw_set_coalesce(struct net_device *ndev, 1044ff5b8ef2SMugunthan V N struct ethtool_coalesce *coal) 1045ff5b8ef2SMugunthan V N { 1046ff5b8ef2SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 1047ff5b8ef2SMugunthan V N u32 int_ctrl; 1048ff5b8ef2SMugunthan V N u32 num_interrupts = 0; 1049ff5b8ef2SMugunthan V N u32 prescale = 0; 1050ff5b8ef2SMugunthan V N u32 addnl_dvdr = 1; 1051ff5b8ef2SMugunthan V N u32 coal_intvl = 0; 10525d8d0d4dSIvan Khoronzhuk struct cpsw_common *cpsw = priv->cpsw; 1053ff5b8ef2SMugunthan V N 1054ff5b8ef2SMugunthan V N coal_intvl = coal->rx_coalesce_usecs; 1055ff5b8ef2SMugunthan V N 10565d8d0d4dSIvan Khoronzhuk int_ctrl = readl(&cpsw->wr_regs->int_control); 10572a05a622SIvan Khoronzhuk prescale = cpsw->bus_freq_mhz * 4; 1058ff5b8ef2SMugunthan V N 1059a84bc2a9SMugunthan V N if (!coal->rx_coalesce_usecs) { 1060a84bc2a9SMugunthan V N int_ctrl &= ~(CPSW_INTPRESCALE_MASK | CPSW_INTPACEEN); 1061a84bc2a9SMugunthan V N goto update_return; 1062a84bc2a9SMugunthan V N } 1063a84bc2a9SMugunthan V N 1064ff5b8ef2SMugunthan V N if (coal_intvl < CPSW_CMINTMIN_INTVL) 1065ff5b8ef2SMugunthan V N coal_intvl = CPSW_CMINTMIN_INTVL; 1066ff5b8ef2SMugunthan V N 1067ff5b8ef2SMugunthan V N if (coal_intvl > CPSW_CMINTMAX_INTVL) { 1068ff5b8ef2SMugunthan V N /* Interrupt pacer works with 4us Pulse, we can 1069ff5b8ef2SMugunthan V N * throttle further by dilating the 4us pulse. 1070ff5b8ef2SMugunthan V N */ 1071ff5b8ef2SMugunthan V N addnl_dvdr = CPSW_INTPRESCALE_MASK / prescale; 1072ff5b8ef2SMugunthan V N 1073ff5b8ef2SMugunthan V N if (addnl_dvdr > 1) { 1074ff5b8ef2SMugunthan V N prescale *= addnl_dvdr; 1075ff5b8ef2SMugunthan V N if (coal_intvl > (CPSW_CMINTMAX_INTVL * addnl_dvdr)) 1076ff5b8ef2SMugunthan V N coal_intvl = (CPSW_CMINTMAX_INTVL 1077ff5b8ef2SMugunthan V N * addnl_dvdr); 1078ff5b8ef2SMugunthan V N } else { 1079ff5b8ef2SMugunthan V N addnl_dvdr = 1; 1080ff5b8ef2SMugunthan V N coal_intvl = CPSW_CMINTMAX_INTVL; 1081ff5b8ef2SMugunthan V N } 1082ff5b8ef2SMugunthan V N } 1083ff5b8ef2SMugunthan V N 1084ff5b8ef2SMugunthan V N num_interrupts = (1000 * addnl_dvdr) / coal_intvl; 10855d8d0d4dSIvan Khoronzhuk writel(num_interrupts, &cpsw->wr_regs->rx_imax); 10865d8d0d4dSIvan Khoronzhuk writel(num_interrupts, &cpsw->wr_regs->tx_imax); 1087ff5b8ef2SMugunthan V N 1088ff5b8ef2SMugunthan V N int_ctrl |= CPSW_INTPACEEN; 1089ff5b8ef2SMugunthan V N int_ctrl &= (~CPSW_INTPRESCALE_MASK); 1090ff5b8ef2SMugunthan V N int_ctrl |= (prescale & CPSW_INTPRESCALE_MASK); 1091a84bc2a9SMugunthan V N 1092a84bc2a9SMugunthan V N update_return: 10935d8d0d4dSIvan Khoronzhuk writel(int_ctrl, &cpsw->wr_regs->int_control); 1094ff5b8ef2SMugunthan V N 1095ff5b8ef2SMugunthan V N cpsw_notice(priv, timer, "Set coalesce to %d usecs.\n", coal_intvl); 10962a05a622SIvan Khoronzhuk cpsw->coal_intvl = coal_intvl; 1097ff5b8ef2SMugunthan V N 1098ff5b8ef2SMugunthan V N return 0; 1099ff5b8ef2SMugunthan V N } 1100ff5b8ef2SMugunthan V N 1101d9718546SMugunthan V N static int cpsw_get_sset_count(struct net_device *ndev, int sset) 1102d9718546SMugunthan V N { 1103e05107e6SIvan Khoronzhuk struct cpsw_common *cpsw = ndev_to_cpsw(ndev); 1104e05107e6SIvan Khoronzhuk 1105d9718546SMugunthan V N switch (sset) { 1106d9718546SMugunthan V N case ETH_SS_STATS: 1107e05107e6SIvan Khoronzhuk return (CPSW_STATS_COMMON_LEN + 1108e05107e6SIvan Khoronzhuk (cpsw->rx_ch_num + cpsw->tx_ch_num) * 1109e05107e6SIvan Khoronzhuk CPSW_STATS_CH_LEN); 1110d9718546SMugunthan V N default: 1111d9718546SMugunthan V N return -EOPNOTSUPP; 1112d9718546SMugunthan V N } 1113d9718546SMugunthan V N } 1114d9718546SMugunthan V N 1115e05107e6SIvan Khoronzhuk static void cpsw_add_ch_strings(u8 **p, int ch_num, int rx_dir) 1116e05107e6SIvan Khoronzhuk { 1117e05107e6SIvan Khoronzhuk int ch_stats_len; 1118e05107e6SIvan Khoronzhuk int line; 1119e05107e6SIvan Khoronzhuk int i; 1120e05107e6SIvan Khoronzhuk 1121e05107e6SIvan Khoronzhuk ch_stats_len = CPSW_STATS_CH_LEN * ch_num; 1122e05107e6SIvan Khoronzhuk for (i = 0; i < ch_stats_len; i++) { 1123e05107e6SIvan Khoronzhuk line = i % CPSW_STATS_CH_LEN; 1124e05107e6SIvan Khoronzhuk snprintf(*p, ETH_GSTRING_LEN, 1125e05107e6SIvan Khoronzhuk "%s DMA chan %d: %s", rx_dir ? "Rx" : "Tx", 1126e05107e6SIvan Khoronzhuk i / CPSW_STATS_CH_LEN, 1127e05107e6SIvan Khoronzhuk cpsw_gstrings_ch_stats[line].stat_string); 1128e05107e6SIvan Khoronzhuk *p += ETH_GSTRING_LEN; 1129e05107e6SIvan Khoronzhuk } 1130e05107e6SIvan Khoronzhuk } 1131e05107e6SIvan Khoronzhuk 1132d9718546SMugunthan V N static void cpsw_get_strings(struct net_device *ndev, u32 stringset, u8 *data) 1133d9718546SMugunthan V N { 1134e05107e6SIvan Khoronzhuk struct cpsw_common *cpsw = ndev_to_cpsw(ndev); 1135d9718546SMugunthan V N u8 *p = data; 1136d9718546SMugunthan V N int i; 1137d9718546SMugunthan V N 1138d9718546SMugunthan V N switch (stringset) { 1139d9718546SMugunthan V N case ETH_SS_STATS: 1140e05107e6SIvan Khoronzhuk for (i = 0; i < CPSW_STATS_COMMON_LEN; i++) { 1141d9718546SMugunthan V N memcpy(p, cpsw_gstrings_stats[i].stat_string, 1142d9718546SMugunthan V N ETH_GSTRING_LEN); 1143d9718546SMugunthan V N p += ETH_GSTRING_LEN; 1144d9718546SMugunthan V N } 1145e05107e6SIvan Khoronzhuk 1146e05107e6SIvan Khoronzhuk cpsw_add_ch_strings(&p, cpsw->rx_ch_num, 1); 1147e05107e6SIvan Khoronzhuk cpsw_add_ch_strings(&p, cpsw->tx_ch_num, 0); 1148d9718546SMugunthan V N break; 1149d9718546SMugunthan V N } 1150d9718546SMugunthan V N } 1151d9718546SMugunthan V N 1152d9718546SMugunthan V N static void cpsw_get_ethtool_stats(struct net_device *ndev, 1153d9718546SMugunthan V N struct ethtool_stats *stats, u64 *data) 1154d9718546SMugunthan V N { 1155d9718546SMugunthan V N u8 *p; 11562c836bd9SIvan Khoronzhuk struct cpsw_common *cpsw = ndev_to_cpsw(ndev); 1157e05107e6SIvan Khoronzhuk struct cpdma_chan_stats ch_stats; 1158e05107e6SIvan Khoronzhuk int i, l, ch; 1159d9718546SMugunthan V N 1160d9718546SMugunthan V N /* Collect Davinci CPDMA stats for Rx and Tx Channel */ 1161e05107e6SIvan Khoronzhuk for (l = 0; l < CPSW_STATS_COMMON_LEN; l++) 1162e05107e6SIvan Khoronzhuk data[l] = readl(cpsw->hw_stats + 1163e05107e6SIvan Khoronzhuk cpsw_gstrings_stats[l].stat_offset); 1164d9718546SMugunthan V N 1165e05107e6SIvan Khoronzhuk for (ch = 0; ch < cpsw->rx_ch_num; ch++) { 11668feb0a19SIvan Khoronzhuk cpdma_chan_get_stats(cpsw->rxv[ch].ch, &ch_stats); 1167e05107e6SIvan Khoronzhuk for (i = 0; i < CPSW_STATS_CH_LEN; i++, l++) { 1168e05107e6SIvan Khoronzhuk p = (u8 *)&ch_stats + 1169e05107e6SIvan Khoronzhuk cpsw_gstrings_ch_stats[i].stat_offset; 1170e05107e6SIvan Khoronzhuk data[l] = *(u32 *)p; 1171e05107e6SIvan Khoronzhuk } 1172e05107e6SIvan Khoronzhuk } 1173d9718546SMugunthan V N 1174e05107e6SIvan Khoronzhuk for (ch = 0; ch < cpsw->tx_ch_num; ch++) { 11758feb0a19SIvan Khoronzhuk cpdma_chan_get_stats(cpsw->txv[ch].ch, &ch_stats); 1176e05107e6SIvan Khoronzhuk for (i = 0; i < CPSW_STATS_CH_LEN; i++, l++) { 1177e05107e6SIvan Khoronzhuk p = (u8 *)&ch_stats + 1178e05107e6SIvan Khoronzhuk cpsw_gstrings_ch_stats[i].stat_offset; 1179e05107e6SIvan Khoronzhuk data[l] = *(u32 *)p; 1180d9718546SMugunthan V N } 1181d9718546SMugunthan V N } 1182d9718546SMugunthan V N } 1183d9718546SMugunthan V N 1184606f3993SIvan Khoronzhuk static int cpsw_common_res_usage_state(struct cpsw_common *cpsw) 1185d9ba8f9eSMugunthan V N { 1186d9ba8f9eSMugunthan V N u32 i; 1187d9ba8f9eSMugunthan V N u32 usage_count = 0; 1188d9ba8f9eSMugunthan V N 1189606f3993SIvan Khoronzhuk if (!cpsw->data.dual_emac) 1190d9ba8f9eSMugunthan V N return 0; 1191d9ba8f9eSMugunthan V N 1192606f3993SIvan Khoronzhuk for (i = 0; i < cpsw->data.slaves; i++) 1193606f3993SIvan Khoronzhuk if (cpsw->slaves[i].open_stat) 1194d9ba8f9eSMugunthan V N usage_count++; 1195d9ba8f9eSMugunthan V N 1196d9ba8f9eSMugunthan V N return usage_count; 1197d9ba8f9eSMugunthan V N } 1198d9ba8f9eSMugunthan V N 119927e9e103SIvan Khoronzhuk static inline int cpsw_tx_packet_submit(struct cpsw_priv *priv, 1200e05107e6SIvan Khoronzhuk struct sk_buff *skb, 1201e05107e6SIvan Khoronzhuk struct cpdma_chan *txch) 1202d9ba8f9eSMugunthan V N { 12032c836bd9SIvan Khoronzhuk struct cpsw_common *cpsw = priv->cpsw; 12042c836bd9SIvan Khoronzhuk 1205e05107e6SIvan Khoronzhuk return cpdma_chan_submit(txch, skb, skb->data, skb->len, 1206606f3993SIvan Khoronzhuk priv->emac_port + cpsw->data.dual_emac); 1207d9ba8f9eSMugunthan V N } 1208d9ba8f9eSMugunthan V N 1209d9ba8f9eSMugunthan V N static inline void cpsw_add_dual_emac_def_ale_entries( 1210d9ba8f9eSMugunthan V N struct cpsw_priv *priv, struct cpsw_slave *slave, 1211d9ba8f9eSMugunthan V N u32 slave_port) 1212d9ba8f9eSMugunthan V N { 12132a05a622SIvan Khoronzhuk struct cpsw_common *cpsw = priv->cpsw; 121471a2cbb7SGrygorii Strashko u32 port_mask = 1 << slave_port | ALE_PORT_HOST; 1215d9ba8f9eSMugunthan V N 12162a05a622SIvan Khoronzhuk if (cpsw->version == CPSW_VERSION_1) 1217d9ba8f9eSMugunthan V N slave_write(slave, slave->port_vlan, CPSW1_PORT_VLAN); 1218d9ba8f9eSMugunthan V N else 1219d9ba8f9eSMugunthan V N slave_write(slave, slave->port_vlan, CPSW2_PORT_VLAN); 12202a05a622SIvan Khoronzhuk cpsw_ale_add_vlan(cpsw->ale, slave->port_vlan, port_mask, 1221d9ba8f9eSMugunthan V N port_mask, port_mask, 0); 12222a05a622SIvan Khoronzhuk cpsw_ale_add_mcast(cpsw->ale, priv->ndev->broadcast, 1223d9ba8f9eSMugunthan V N port_mask, ALE_VLAN, slave->port_vlan, 0); 12242a05a622SIvan Khoronzhuk cpsw_ale_add_ucast(cpsw->ale, priv->mac_addr, 12252a05a622SIvan Khoronzhuk HOST_PORT_NUM, ALE_VLAN | 12262a05a622SIvan Khoronzhuk ALE_SECURE, slave->port_vlan); 1227d9ba8f9eSMugunthan V N } 1228d9ba8f9eSMugunthan V N 12291e7a2e21SDaniel Mack static void soft_reset_slave(struct cpsw_slave *slave) 1230df828598SMugunthan V N { 1231df828598SMugunthan V N char name[32]; 12321e7a2e21SDaniel Mack 12331e7a2e21SDaniel Mack snprintf(name, sizeof(name), "slave-%d", slave->slave_num); 12341e7a2e21SDaniel Mack soft_reset(name, &slave->sliver->soft_reset); 12351e7a2e21SDaniel Mack } 12361e7a2e21SDaniel Mack 12371e7a2e21SDaniel Mack static void cpsw_slave_open(struct cpsw_slave *slave, struct cpsw_priv *priv) 12381e7a2e21SDaniel Mack { 1239df828598SMugunthan V N u32 slave_port; 1240649a1688SIvan Khoronzhuk struct cpsw_common *cpsw = priv->cpsw; 1241df828598SMugunthan V N 12421e7a2e21SDaniel Mack soft_reset_slave(slave); 1243df828598SMugunthan V N 1244df828598SMugunthan V N /* setup priority mapping */ 1245df828598SMugunthan V N __raw_writel(RX_PRIORITY_MAPPING, &slave->sliver->rx_pri_map); 12469750a3adSRichard Cochran 12472a05a622SIvan Khoronzhuk switch (cpsw->version) { 12489750a3adSRichard Cochran case CPSW_VERSION_1: 12499750a3adSRichard Cochran slave_write(slave, TX_PRIORITY_MAPPING, CPSW1_TX_PRI_MAP); 12509750a3adSRichard Cochran break; 12519750a3adSRichard Cochran case CPSW_VERSION_2: 1252c193f365SMugunthan V N case CPSW_VERSION_3: 1253926489beSMugunthan V N case CPSW_VERSION_4: 12549750a3adSRichard Cochran slave_write(slave, TX_PRIORITY_MAPPING, CPSW2_TX_PRI_MAP); 12559750a3adSRichard Cochran break; 12569750a3adSRichard Cochran } 1257df828598SMugunthan V N 1258df828598SMugunthan V N /* setup max packet size, and mac address */ 12592a05a622SIvan Khoronzhuk __raw_writel(cpsw->rx_packet_max, &slave->sliver->rx_maxlen); 1260df828598SMugunthan V N cpsw_set_slave_mac(slave, priv); 1261df828598SMugunthan V N 1262df828598SMugunthan V N slave->mac_control = 0; /* no link yet */ 1263df828598SMugunthan V N 12646f1f5836SIvan Khoronzhuk slave_port = cpsw_get_slave_port(slave->slave_num); 1265df828598SMugunthan V N 1266606f3993SIvan Khoronzhuk if (cpsw->data.dual_emac) 1267d9ba8f9eSMugunthan V N cpsw_add_dual_emac_def_ale_entries(priv, slave, slave_port); 1268d9ba8f9eSMugunthan V N else 12692a05a622SIvan Khoronzhuk cpsw_ale_add_mcast(cpsw->ale, priv->ndev->broadcast, 1270e11b220fSMugunthan V N 1 << slave_port, 0, 0, ALE_MCAST_FWD_2); 1271df828598SMugunthan V N 1272d733f754SDavid Rivshin if (slave->data->phy_node) { 1273552165bcSDavid Rivshin slave->phy = of_phy_connect(priv->ndev, slave->data->phy_node, 12749e42f715SHeiko Schocher &cpsw_adjust_link, 0, slave->data->phy_if); 1275d733f754SDavid Rivshin if (!slave->phy) { 1276d733f754SDavid Rivshin dev_err(priv->dev, "phy \"%s\" not found on slave %d\n", 1277d733f754SDavid Rivshin slave->data->phy_node->full_name, 1278d733f754SDavid Rivshin slave->slave_num); 1279d733f754SDavid Rivshin return; 1280d733f754SDavid Rivshin } 1281d733f754SDavid Rivshin } else { 1282df828598SMugunthan V N slave->phy = phy_connect(priv->ndev, slave->data->phy_id, 1283f9a8f83bSFlorian Fainelli &cpsw_adjust_link, slave->data->phy_if); 1284df828598SMugunthan V N if (IS_ERR(slave->phy)) { 1285d733f754SDavid Rivshin dev_err(priv->dev, 1286d733f754SDavid Rivshin "phy \"%s\" not found on slave %d, err %ld\n", 1287d733f754SDavid Rivshin slave->data->phy_id, slave->slave_num, 1288d733f754SDavid Rivshin PTR_ERR(slave->phy)); 1289df828598SMugunthan V N slave->phy = NULL; 1290d733f754SDavid Rivshin return; 1291d733f754SDavid Rivshin } 1292d733f754SDavid Rivshin } 1293d733f754SDavid Rivshin 12942220943aSAndrew Lunn phy_attached_info(slave->phy); 12952220943aSAndrew Lunn 1296df828598SMugunthan V N phy_start(slave->phy); 1297388367a5SMugunthan V N 1298388367a5SMugunthan V N /* Configure GMII_SEL register */ 129956e31bd8SIvan Khoronzhuk cpsw_phy_sel(cpsw->dev, slave->phy->interface, slave->slave_num); 1300df828598SMugunthan V N } 1301df828598SMugunthan V N 13023b72c2feSMugunthan V N static inline void cpsw_add_default_vlan(struct cpsw_priv *priv) 13033b72c2feSMugunthan V N { 1304606f3993SIvan Khoronzhuk struct cpsw_common *cpsw = priv->cpsw; 1305606f3993SIvan Khoronzhuk const int vlan = cpsw->data.default_vlan; 13063b72c2feSMugunthan V N u32 reg; 13073b72c2feSMugunthan V N int i; 13081e5c4bc4SLennart Sorensen int unreg_mcast_mask; 13093b72c2feSMugunthan V N 13102a05a622SIvan Khoronzhuk reg = (cpsw->version == CPSW_VERSION_1) ? CPSW1_PORT_VLAN : 13113b72c2feSMugunthan V N CPSW2_PORT_VLAN; 13123b72c2feSMugunthan V N 13135d8d0d4dSIvan Khoronzhuk writel(vlan, &cpsw->host_port_regs->port_vlan); 13143b72c2feSMugunthan V N 1315606f3993SIvan Khoronzhuk for (i = 0; i < cpsw->data.slaves; i++) 1316606f3993SIvan Khoronzhuk slave_write(cpsw->slaves + i, vlan, reg); 13173b72c2feSMugunthan V N 13181e5c4bc4SLennart Sorensen if (priv->ndev->flags & IFF_ALLMULTI) 13191e5c4bc4SLennart Sorensen unreg_mcast_mask = ALE_ALL_PORTS; 13201e5c4bc4SLennart Sorensen else 13211e5c4bc4SLennart Sorensen unreg_mcast_mask = ALE_PORT_1 | ALE_PORT_2; 13221e5c4bc4SLennart Sorensen 13232a05a622SIvan Khoronzhuk cpsw_ale_add_vlan(cpsw->ale, vlan, ALE_ALL_PORTS, 132461f1cef9SGrygorii Strashko ALE_ALL_PORTS, ALE_ALL_PORTS, 132561f1cef9SGrygorii Strashko unreg_mcast_mask); 13263b72c2feSMugunthan V N } 13273b72c2feSMugunthan V N 1328df828598SMugunthan V N static void cpsw_init_host_port(struct cpsw_priv *priv) 1329df828598SMugunthan V N { 1330d9ba8f9eSMugunthan V N u32 fifo_mode; 13315d8d0d4dSIvan Khoronzhuk u32 control_reg; 13325d8d0d4dSIvan Khoronzhuk struct cpsw_common *cpsw = priv->cpsw; 13333b72c2feSMugunthan V N 1334df828598SMugunthan V N /* soft reset the controller and initialize ale */ 13355d8d0d4dSIvan Khoronzhuk soft_reset("cpsw", &cpsw->regs->soft_reset); 13362a05a622SIvan Khoronzhuk cpsw_ale_start(cpsw->ale); 1337df828598SMugunthan V N 1338df828598SMugunthan V N /* switch to vlan unaware mode */ 13392a05a622SIvan Khoronzhuk cpsw_ale_control_set(cpsw->ale, HOST_PORT_NUM, ALE_VLAN_AWARE, 13403b72c2feSMugunthan V N CPSW_ALE_VLAN_AWARE); 13415d8d0d4dSIvan Khoronzhuk control_reg = readl(&cpsw->regs->control); 13423b72c2feSMugunthan V N control_reg |= CPSW_VLAN_AWARE; 13435d8d0d4dSIvan Khoronzhuk writel(control_reg, &cpsw->regs->control); 1344606f3993SIvan Khoronzhuk fifo_mode = (cpsw->data.dual_emac) ? CPSW_FIFO_DUAL_MAC_MODE : 1345d9ba8f9eSMugunthan V N CPSW_FIFO_NORMAL_MODE; 13465d8d0d4dSIvan Khoronzhuk writel(fifo_mode, &cpsw->host_port_regs->tx_in_ctl); 1347df828598SMugunthan V N 1348df828598SMugunthan V N /* setup host port priority mapping */ 1349df828598SMugunthan V N __raw_writel(CPDMA_TX_PRIORITY_MAP, 13505d8d0d4dSIvan Khoronzhuk &cpsw->host_port_regs->cpdma_tx_pri_map); 13515d8d0d4dSIvan Khoronzhuk __raw_writel(0, &cpsw->host_port_regs->cpdma_rx_chan_map); 1352df828598SMugunthan V N 13532a05a622SIvan Khoronzhuk cpsw_ale_control_set(cpsw->ale, HOST_PORT_NUM, 1354df828598SMugunthan V N ALE_PORT_STATE, ALE_PORT_STATE_FORWARD); 1355df828598SMugunthan V N 1356606f3993SIvan Khoronzhuk if (!cpsw->data.dual_emac) { 13572a05a622SIvan Khoronzhuk cpsw_ale_add_ucast(cpsw->ale, priv->mac_addr, HOST_PORT_NUM, 1358d9ba8f9eSMugunthan V N 0, 0); 13592a05a622SIvan Khoronzhuk cpsw_ale_add_mcast(cpsw->ale, priv->ndev->broadcast, 136071a2cbb7SGrygorii Strashko ALE_PORT_HOST, 0, 0, ALE_MCAST_FWD_2); 1361df828598SMugunthan V N } 1362d9ba8f9eSMugunthan V N } 1363df828598SMugunthan V N 13643802dce1SIvan Khoronzhuk static int cpsw_fill_rx_channels(struct cpsw_priv *priv) 13653802dce1SIvan Khoronzhuk { 13663802dce1SIvan Khoronzhuk struct cpsw_common *cpsw = priv->cpsw; 13673802dce1SIvan Khoronzhuk struct sk_buff *skb; 13683802dce1SIvan Khoronzhuk int ch_buf_num; 1369e05107e6SIvan Khoronzhuk int ch, i, ret; 13703802dce1SIvan Khoronzhuk 1371e05107e6SIvan Khoronzhuk for (ch = 0; ch < cpsw->rx_ch_num; ch++) { 13728feb0a19SIvan Khoronzhuk ch_buf_num = cpdma_chan_get_rx_buf_num(cpsw->rxv[ch].ch); 13733802dce1SIvan Khoronzhuk for (i = 0; i < ch_buf_num; i++) { 13743802dce1SIvan Khoronzhuk skb = __netdev_alloc_skb_ip_align(priv->ndev, 13753802dce1SIvan Khoronzhuk cpsw->rx_packet_max, 13763802dce1SIvan Khoronzhuk GFP_KERNEL); 13773802dce1SIvan Khoronzhuk if (!skb) { 13783802dce1SIvan Khoronzhuk cpsw_err(priv, ifup, "cannot allocate skb\n"); 13793802dce1SIvan Khoronzhuk return -ENOMEM; 13803802dce1SIvan Khoronzhuk } 13813802dce1SIvan Khoronzhuk 1382e05107e6SIvan Khoronzhuk skb_set_queue_mapping(skb, ch); 13838feb0a19SIvan Khoronzhuk ret = cpdma_chan_submit(cpsw->rxv[ch].ch, skb, 13848feb0a19SIvan Khoronzhuk skb->data, skb_tailroom(skb), 13858feb0a19SIvan Khoronzhuk 0); 13863802dce1SIvan Khoronzhuk if (ret < 0) { 13873802dce1SIvan Khoronzhuk cpsw_err(priv, ifup, 1388e05107e6SIvan Khoronzhuk "cannot submit skb to channel %d rx, error %d\n", 1389e05107e6SIvan Khoronzhuk ch, ret); 13903802dce1SIvan Khoronzhuk kfree_skb(skb); 13913802dce1SIvan Khoronzhuk return ret; 13923802dce1SIvan Khoronzhuk } 13933802dce1SIvan Khoronzhuk kmemleak_not_leak(skb); 13943802dce1SIvan Khoronzhuk } 13953802dce1SIvan Khoronzhuk 1396e05107e6SIvan Khoronzhuk cpsw_info(priv, ifup, "ch %d rx, submitted %d descriptors\n", 1397e05107e6SIvan Khoronzhuk ch, ch_buf_num); 1398e05107e6SIvan Khoronzhuk } 13993802dce1SIvan Khoronzhuk 1400e05107e6SIvan Khoronzhuk return 0; 14013802dce1SIvan Khoronzhuk } 14023802dce1SIvan Khoronzhuk 14032a05a622SIvan Khoronzhuk static void cpsw_slave_stop(struct cpsw_slave *slave, struct cpsw_common *cpsw) 1404aacebbf8SSebastian Siewior { 14053995d265SSchuyler Patton u32 slave_port; 14063995d265SSchuyler Patton 14076f1f5836SIvan Khoronzhuk slave_port = cpsw_get_slave_port(slave->slave_num); 14083995d265SSchuyler Patton 1409aacebbf8SSebastian Siewior if (!slave->phy) 1410aacebbf8SSebastian Siewior return; 1411aacebbf8SSebastian Siewior phy_stop(slave->phy); 1412aacebbf8SSebastian Siewior phy_disconnect(slave->phy); 1413aacebbf8SSebastian Siewior slave->phy = NULL; 14142a05a622SIvan Khoronzhuk cpsw_ale_control_set(cpsw->ale, slave_port, 14153995d265SSchuyler Patton ALE_PORT_STATE, ALE_PORT_STATE_DISABLE); 14161f95ba00SGrygorii Strashko soft_reset_slave(slave); 1417aacebbf8SSebastian Siewior } 1418aacebbf8SSebastian Siewior 1419df828598SMugunthan V N static int cpsw_ndo_open(struct net_device *ndev) 1420df828598SMugunthan V N { 1421df828598SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 1422649a1688SIvan Khoronzhuk struct cpsw_common *cpsw = priv->cpsw; 14233802dce1SIvan Khoronzhuk int ret; 1424df828598SMugunthan V N u32 reg; 1425df828598SMugunthan V N 142656e31bd8SIvan Khoronzhuk ret = pm_runtime_get_sync(cpsw->dev); 1427108a6537SGrygorii Strashko if (ret < 0) { 142856e31bd8SIvan Khoronzhuk pm_runtime_put_noidle(cpsw->dev); 1429108a6537SGrygorii Strashko return ret; 1430108a6537SGrygorii Strashko } 14313fa88c51SGrygorii Strashko 1432606f3993SIvan Khoronzhuk if (!cpsw_common_res_usage_state(cpsw)) 14332c836bd9SIvan Khoronzhuk cpsw_intr_disable(cpsw); 1434df828598SMugunthan V N netif_carrier_off(ndev); 1435df828598SMugunthan V N 1436e05107e6SIvan Khoronzhuk /* Notify the stack of the actual queue counts. */ 1437e05107e6SIvan Khoronzhuk ret = netif_set_real_num_tx_queues(ndev, cpsw->tx_ch_num); 1438e05107e6SIvan Khoronzhuk if (ret) { 1439e05107e6SIvan Khoronzhuk dev_err(priv->dev, "cannot set real number of tx queues\n"); 1440e05107e6SIvan Khoronzhuk goto err_cleanup; 1441e05107e6SIvan Khoronzhuk } 1442e05107e6SIvan Khoronzhuk 1443e05107e6SIvan Khoronzhuk ret = netif_set_real_num_rx_queues(ndev, cpsw->rx_ch_num); 1444e05107e6SIvan Khoronzhuk if (ret) { 1445e05107e6SIvan Khoronzhuk dev_err(priv->dev, "cannot set real number of rx queues\n"); 1446e05107e6SIvan Khoronzhuk goto err_cleanup; 1447e05107e6SIvan Khoronzhuk } 1448e05107e6SIvan Khoronzhuk 14492a05a622SIvan Khoronzhuk reg = cpsw->version; 1450df828598SMugunthan V N 1451df828598SMugunthan V N dev_info(priv->dev, "initializing cpsw version %d.%d (%d)\n", 1452df828598SMugunthan V N CPSW_MAJOR_VERSION(reg), CPSW_MINOR_VERSION(reg), 1453df828598SMugunthan V N CPSW_RTL_VERSION(reg)); 1454df828598SMugunthan V N 1455df828598SMugunthan V N /* initialize host and slave ports */ 1456606f3993SIvan Khoronzhuk if (!cpsw_common_res_usage_state(cpsw)) 1457df828598SMugunthan V N cpsw_init_host_port(priv); 1458df828598SMugunthan V N for_each_slave(priv, cpsw_slave_open, priv); 1459df828598SMugunthan V N 14603b72c2feSMugunthan V N /* Add default VLAN */ 1461606f3993SIvan Khoronzhuk if (!cpsw->data.dual_emac) 14623b72c2feSMugunthan V N cpsw_add_default_vlan(priv); 1463e6afea0bSMugunthan V N else 14642a05a622SIvan Khoronzhuk cpsw_ale_add_vlan(cpsw->ale, cpsw->data.default_vlan, 146561f1cef9SGrygorii Strashko ALE_ALL_PORTS, ALE_ALL_PORTS, 0, 0); 14663b72c2feSMugunthan V N 1467606f3993SIvan Khoronzhuk if (!cpsw_common_res_usage_state(cpsw)) { 1468d9ba8f9eSMugunthan V N /* disable priority elevation */ 14695d8d0d4dSIvan Khoronzhuk __raw_writel(0, &cpsw->regs->ptype); 1470df828598SMugunthan V N 1471d9ba8f9eSMugunthan V N /* enable statistics collection only on all ports */ 14725d8d0d4dSIvan Khoronzhuk __raw_writel(0x7, &cpsw->regs->stat_port_en); 1473df828598SMugunthan V N 14741923d6e4SMugunthan V N /* Enable internal fifo flow control */ 14755d8d0d4dSIvan Khoronzhuk writel(0x7, &cpsw->regs->flow_control); 14761923d6e4SMugunthan V N 1477dbc4ec52SIvan Khoronzhuk napi_enable(&cpsw->napi_rx); 1478dbc4ec52SIvan Khoronzhuk napi_enable(&cpsw->napi_tx); 1479d354eb85SMugunthan V N 1480e38b5a3dSIvan Khoronzhuk if (cpsw->tx_irq_disabled) { 1481e38b5a3dSIvan Khoronzhuk cpsw->tx_irq_disabled = false; 1482e38b5a3dSIvan Khoronzhuk enable_irq(cpsw->irqs_table[1]); 14837da11600SMugunthan V N } 14847da11600SMugunthan V N 1485e38b5a3dSIvan Khoronzhuk if (cpsw->rx_irq_disabled) { 1486e38b5a3dSIvan Khoronzhuk cpsw->rx_irq_disabled = false; 1487e38b5a3dSIvan Khoronzhuk enable_irq(cpsw->irqs_table[0]); 14887da11600SMugunthan V N } 14897da11600SMugunthan V N 14903802dce1SIvan Khoronzhuk ret = cpsw_fill_rx_channels(priv); 14913802dce1SIvan Khoronzhuk if (ret < 0) 1492aacebbf8SSebastian Siewior goto err_cleanup; 1493f280e89aSMugunthan V N 14948a2c9a5aSGrygorii Strashko if (cpts_register(cpsw->cpts)) 1495f280e89aSMugunthan V N dev_err(priv->dev, "error registering cpts device\n"); 1496f280e89aSMugunthan V N 1497d9ba8f9eSMugunthan V N } 1498df828598SMugunthan V N 1499ff5b8ef2SMugunthan V N /* Enable Interrupt pacing if configured */ 15002a05a622SIvan Khoronzhuk if (cpsw->coal_intvl != 0) { 1501ff5b8ef2SMugunthan V N struct ethtool_coalesce coal; 1502ff5b8ef2SMugunthan V N 15032a05a622SIvan Khoronzhuk coal.rx_coalesce_usecs = cpsw->coal_intvl; 1504ff5b8ef2SMugunthan V N cpsw_set_coalesce(ndev, &coal); 1505ff5b8ef2SMugunthan V N } 1506ff5b8ef2SMugunthan V N 15072c836bd9SIvan Khoronzhuk cpdma_ctlr_start(cpsw->dma); 15082c836bd9SIvan Khoronzhuk cpsw_intr_enable(cpsw); 1509f63a975eSMugunthan V N 1510606f3993SIvan Khoronzhuk if (cpsw->data.dual_emac) 1511606f3993SIvan Khoronzhuk cpsw->slaves[priv->emac_port].open_stat = true; 1512e05107e6SIvan Khoronzhuk 1513df828598SMugunthan V N return 0; 1514df828598SMugunthan V N 1515aacebbf8SSebastian Siewior err_cleanup: 15162c836bd9SIvan Khoronzhuk cpdma_ctlr_stop(cpsw->dma); 15172a05a622SIvan Khoronzhuk for_each_slave(priv, cpsw_slave_stop, cpsw); 151856e31bd8SIvan Khoronzhuk pm_runtime_put_sync(cpsw->dev); 1519aacebbf8SSebastian Siewior netif_carrier_off(priv->ndev); 1520aacebbf8SSebastian Siewior return ret; 1521df828598SMugunthan V N } 1522df828598SMugunthan V N 1523df828598SMugunthan V N static int cpsw_ndo_stop(struct net_device *ndev) 1524df828598SMugunthan V N { 1525df828598SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 1526649a1688SIvan Khoronzhuk struct cpsw_common *cpsw = priv->cpsw; 1527df828598SMugunthan V N 1528df828598SMugunthan V N cpsw_info(priv, ifdown, "shutting down cpsw device\n"); 1529e05107e6SIvan Khoronzhuk netif_tx_stop_all_queues(priv->ndev); 1530df828598SMugunthan V N netif_carrier_off(priv->ndev); 1531d9ba8f9eSMugunthan V N 1532606f3993SIvan Khoronzhuk if (cpsw_common_res_usage_state(cpsw) <= 1) { 1533dbc4ec52SIvan Khoronzhuk napi_disable(&cpsw->napi_rx); 1534dbc4ec52SIvan Khoronzhuk napi_disable(&cpsw->napi_tx); 15352a05a622SIvan Khoronzhuk cpts_unregister(cpsw->cpts); 15362c836bd9SIvan Khoronzhuk cpsw_intr_disable(cpsw); 15372c836bd9SIvan Khoronzhuk cpdma_ctlr_stop(cpsw->dma); 15382a05a622SIvan Khoronzhuk cpsw_ale_stop(cpsw->ale); 1539d9ba8f9eSMugunthan V N } 15402a05a622SIvan Khoronzhuk for_each_slave(priv, cpsw_slave_stop, cpsw); 154156e31bd8SIvan Khoronzhuk pm_runtime_put_sync(cpsw->dev); 1542606f3993SIvan Khoronzhuk if (cpsw->data.dual_emac) 1543606f3993SIvan Khoronzhuk cpsw->slaves[priv->emac_port].open_stat = false; 1544df828598SMugunthan V N return 0; 1545df828598SMugunthan V N } 1546df828598SMugunthan V N 1547df828598SMugunthan V N static netdev_tx_t cpsw_ndo_start_xmit(struct sk_buff *skb, 1548df828598SMugunthan V N struct net_device *ndev) 1549df828598SMugunthan V N { 1550df828598SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 15512c836bd9SIvan Khoronzhuk struct cpsw_common *cpsw = priv->cpsw; 1552e05107e6SIvan Khoronzhuk struct netdev_queue *txq; 1553e05107e6SIvan Khoronzhuk struct cpdma_chan *txch; 1554e05107e6SIvan Khoronzhuk int ret, q_idx; 1555df828598SMugunthan V N 1556860e9538SFlorian Westphal netif_trans_update(ndev); 1557df828598SMugunthan V N 1558df828598SMugunthan V N if (skb_padto(skb, CPSW_MIN_PACKET_SIZE)) { 1559df828598SMugunthan V N cpsw_err(priv, tx_err, "packet pad failed\n"); 15608dc43ddcSTobias Klauser ndev->stats.tx_dropped++; 1561df828598SMugunthan V N return NETDEV_TX_OK; 1562df828598SMugunthan V N } 1563df828598SMugunthan V N 15649232b16dSMugunthan V N if (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP && 1565b63ba58eSGrygorii Strashko cpts_is_tx_enabled(cpsw->cpts)) 15662e5b38abSRichard Cochran skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 15672e5b38abSRichard Cochran 15682e5b38abSRichard Cochran skb_tx_timestamp(skb); 15692e5b38abSRichard Cochran 1570e05107e6SIvan Khoronzhuk q_idx = skb_get_queue_mapping(skb); 1571e05107e6SIvan Khoronzhuk if (q_idx >= cpsw->tx_ch_num) 1572e05107e6SIvan Khoronzhuk q_idx = q_idx % cpsw->tx_ch_num; 1573e05107e6SIvan Khoronzhuk 15748feb0a19SIvan Khoronzhuk txch = cpsw->txv[q_idx].ch; 1575e05107e6SIvan Khoronzhuk ret = cpsw_tx_packet_submit(priv, skb, txch); 1576df828598SMugunthan V N if (unlikely(ret != 0)) { 1577df828598SMugunthan V N cpsw_err(priv, tx_err, "desc submit failed\n"); 1578df828598SMugunthan V N goto fail; 1579df828598SMugunthan V N } 1580df828598SMugunthan V N 1581fae50823SMugunthan V N /* If there is no more tx desc left free then we need to 1582fae50823SMugunthan V N * tell the kernel to stop sending us tx frames. 1583fae50823SMugunthan V N */ 1584e05107e6SIvan Khoronzhuk if (unlikely(!cpdma_check_free_tx_desc(txch))) { 1585e05107e6SIvan Khoronzhuk txq = netdev_get_tx_queue(ndev, q_idx); 1586e05107e6SIvan Khoronzhuk netif_tx_stop_queue(txq); 1587e05107e6SIvan Khoronzhuk } 1588fae50823SMugunthan V N 1589df828598SMugunthan V N return NETDEV_TX_OK; 1590df828598SMugunthan V N fail: 15918dc43ddcSTobias Klauser ndev->stats.tx_dropped++; 1592e05107e6SIvan Khoronzhuk txq = netdev_get_tx_queue(ndev, skb_get_queue_mapping(skb)); 1593e05107e6SIvan Khoronzhuk netif_tx_stop_queue(txq); 1594df828598SMugunthan V N return NETDEV_TX_BUSY; 1595df828598SMugunthan V N } 1596df828598SMugunthan V N 1597c8395d4eSGrygorii Strashko #if IS_ENABLED(CONFIG_TI_CPTS) 15982e5b38abSRichard Cochran 15992a05a622SIvan Khoronzhuk static void cpsw_hwtstamp_v1(struct cpsw_common *cpsw) 16002e5b38abSRichard Cochran { 1601606f3993SIvan Khoronzhuk struct cpsw_slave *slave = &cpsw->slaves[cpsw->data.active_slave]; 16022e5b38abSRichard Cochran u32 ts_en, seq_id; 16032e5b38abSRichard Cochran 1604b63ba58eSGrygorii Strashko if (!cpts_is_tx_enabled(cpsw->cpts) && 1605b63ba58eSGrygorii Strashko !cpts_is_rx_enabled(cpsw->cpts)) { 16062e5b38abSRichard Cochran slave_write(slave, 0, CPSW1_TS_CTL); 16072e5b38abSRichard Cochran return; 16082e5b38abSRichard Cochran } 16092e5b38abSRichard Cochran 16102e5b38abSRichard Cochran seq_id = (30 << CPSW_V1_SEQ_ID_OFS_SHIFT) | ETH_P_1588; 16112e5b38abSRichard Cochran ts_en = EVENT_MSG_BITS << CPSW_V1_MSG_TYPE_OFS; 16122e5b38abSRichard Cochran 1613b63ba58eSGrygorii Strashko if (cpts_is_tx_enabled(cpsw->cpts)) 16142e5b38abSRichard Cochran ts_en |= CPSW_V1_TS_TX_EN; 16152e5b38abSRichard Cochran 1616b63ba58eSGrygorii Strashko if (cpts_is_rx_enabled(cpsw->cpts)) 16172e5b38abSRichard Cochran ts_en |= CPSW_V1_TS_RX_EN; 16182e5b38abSRichard Cochran 16192e5b38abSRichard Cochran slave_write(slave, ts_en, CPSW1_TS_CTL); 16202e5b38abSRichard Cochran slave_write(slave, seq_id, CPSW1_TS_SEQ_LTYPE); 16212e5b38abSRichard Cochran } 16222e5b38abSRichard Cochran 16232e5b38abSRichard Cochran static void cpsw_hwtstamp_v2(struct cpsw_priv *priv) 16242e5b38abSRichard Cochran { 1625d9ba8f9eSMugunthan V N struct cpsw_slave *slave; 16265d8d0d4dSIvan Khoronzhuk struct cpsw_common *cpsw = priv->cpsw; 16272e5b38abSRichard Cochran u32 ctrl, mtype; 16282e5b38abSRichard Cochran 1629cb7d78d0SIvan Khoronzhuk slave = &cpsw->slaves[cpsw_slave_index(cpsw, priv)]; 1630d9ba8f9eSMugunthan V N 16312e5b38abSRichard Cochran ctrl = slave_read(slave, CPSW2_CONTROL); 16322a05a622SIvan Khoronzhuk switch (cpsw->version) { 163309c55372SGeorge Cherian case CPSW_VERSION_2: 163409c55372SGeorge Cherian ctrl &= ~CTRL_V2_ALL_TS_MASK; 16352e5b38abSRichard Cochran 1636b63ba58eSGrygorii Strashko if (cpts_is_tx_enabled(cpsw->cpts)) 163709c55372SGeorge Cherian ctrl |= CTRL_V2_TX_TS_BITS; 16382e5b38abSRichard Cochran 1639b63ba58eSGrygorii Strashko if (cpts_is_rx_enabled(cpsw->cpts)) 164009c55372SGeorge Cherian ctrl |= CTRL_V2_RX_TS_BITS; 164109c55372SGeorge Cherian break; 164209c55372SGeorge Cherian case CPSW_VERSION_3: 164309c55372SGeorge Cherian default: 164409c55372SGeorge Cherian ctrl &= ~CTRL_V3_ALL_TS_MASK; 164509c55372SGeorge Cherian 1646b63ba58eSGrygorii Strashko if (cpts_is_tx_enabled(cpsw->cpts)) 164709c55372SGeorge Cherian ctrl |= CTRL_V3_TX_TS_BITS; 164809c55372SGeorge Cherian 1649b63ba58eSGrygorii Strashko if (cpts_is_rx_enabled(cpsw->cpts)) 165009c55372SGeorge Cherian ctrl |= CTRL_V3_RX_TS_BITS; 165109c55372SGeorge Cherian break; 165209c55372SGeorge Cherian } 16532e5b38abSRichard Cochran 16542e5b38abSRichard Cochran mtype = (30 << TS_SEQ_ID_OFFSET_SHIFT) | EVENT_MSG_BITS; 16552e5b38abSRichard Cochran 16562e5b38abSRichard Cochran slave_write(slave, mtype, CPSW2_TS_SEQ_MTYPE); 16572e5b38abSRichard Cochran slave_write(slave, ctrl, CPSW2_CONTROL); 16585d8d0d4dSIvan Khoronzhuk __raw_writel(ETH_P_1588, &cpsw->regs->ts_ltype); 16592e5b38abSRichard Cochran } 16602e5b38abSRichard Cochran 1661a5b4145bSBen Hutchings static int cpsw_hwtstamp_set(struct net_device *dev, struct ifreq *ifr) 16622e5b38abSRichard Cochran { 16633177bf6fSMugunthan V N struct cpsw_priv *priv = netdev_priv(dev); 16642e5b38abSRichard Cochran struct hwtstamp_config cfg; 16652a05a622SIvan Khoronzhuk struct cpsw_common *cpsw = priv->cpsw; 16662a05a622SIvan Khoronzhuk struct cpts *cpts = cpsw->cpts; 16672e5b38abSRichard Cochran 16682a05a622SIvan Khoronzhuk if (cpsw->version != CPSW_VERSION_1 && 16692a05a622SIvan Khoronzhuk cpsw->version != CPSW_VERSION_2 && 16702a05a622SIvan Khoronzhuk cpsw->version != CPSW_VERSION_3) 16712ee91e54SBen Hutchings return -EOPNOTSUPP; 16722ee91e54SBen Hutchings 16732e5b38abSRichard Cochran if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg))) 16742e5b38abSRichard Cochran return -EFAULT; 16752e5b38abSRichard Cochran 16762e5b38abSRichard Cochran /* reserved for future extensions */ 16772e5b38abSRichard Cochran if (cfg.flags) 16782e5b38abSRichard Cochran return -EINVAL; 16792e5b38abSRichard Cochran 16802ee91e54SBen Hutchings if (cfg.tx_type != HWTSTAMP_TX_OFF && cfg.tx_type != HWTSTAMP_TX_ON) 16812e5b38abSRichard Cochran return -ERANGE; 16822e5b38abSRichard Cochran 16832e5b38abSRichard Cochran switch (cfg.rx_filter) { 16842e5b38abSRichard Cochran case HWTSTAMP_FILTER_NONE: 1685b63ba58eSGrygorii Strashko cpts_rx_enable(cpts, 0); 16862e5b38abSRichard Cochran break; 16872e5b38abSRichard Cochran case HWTSTAMP_FILTER_ALL: 16882e5b38abSRichard Cochran case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: 16892e5b38abSRichard Cochran case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: 16902e5b38abSRichard Cochran case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: 16912e5b38abSRichard Cochran return -ERANGE; 16922e5b38abSRichard Cochran case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: 16932e5b38abSRichard Cochran case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 16942e5b38abSRichard Cochran case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 16952e5b38abSRichard Cochran case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: 16962e5b38abSRichard Cochran case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: 16972e5b38abSRichard Cochran case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: 16982e5b38abSRichard Cochran case HWTSTAMP_FILTER_PTP_V2_EVENT: 16992e5b38abSRichard Cochran case HWTSTAMP_FILTER_PTP_V2_SYNC: 17002e5b38abSRichard Cochran case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 1701b63ba58eSGrygorii Strashko cpts_rx_enable(cpts, 1); 17022e5b38abSRichard Cochran cfg.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT; 17032e5b38abSRichard Cochran break; 17042e5b38abSRichard Cochran default: 17052e5b38abSRichard Cochran return -ERANGE; 17062e5b38abSRichard Cochran } 17072e5b38abSRichard Cochran 1708b63ba58eSGrygorii Strashko cpts_tx_enable(cpts, cfg.tx_type == HWTSTAMP_TX_ON); 17092ee91e54SBen Hutchings 17102a05a622SIvan Khoronzhuk switch (cpsw->version) { 17112e5b38abSRichard Cochran case CPSW_VERSION_1: 17122a05a622SIvan Khoronzhuk cpsw_hwtstamp_v1(cpsw); 17132e5b38abSRichard Cochran break; 17142e5b38abSRichard Cochran case CPSW_VERSION_2: 1715f7d403cbSGeorge Cherian case CPSW_VERSION_3: 17162e5b38abSRichard Cochran cpsw_hwtstamp_v2(priv); 17172e5b38abSRichard Cochran break; 17182e5b38abSRichard Cochran default: 17192ee91e54SBen Hutchings WARN_ON(1); 17202e5b38abSRichard Cochran } 17212e5b38abSRichard Cochran 17222e5b38abSRichard Cochran return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0; 17232e5b38abSRichard Cochran } 17242e5b38abSRichard Cochran 1725a5b4145bSBen Hutchings static int cpsw_hwtstamp_get(struct net_device *dev, struct ifreq *ifr) 1726a5b4145bSBen Hutchings { 17272a05a622SIvan Khoronzhuk struct cpsw_common *cpsw = ndev_to_cpsw(dev); 17282a05a622SIvan Khoronzhuk struct cpts *cpts = cpsw->cpts; 1729a5b4145bSBen Hutchings struct hwtstamp_config cfg; 1730a5b4145bSBen Hutchings 17312a05a622SIvan Khoronzhuk if (cpsw->version != CPSW_VERSION_1 && 17322a05a622SIvan Khoronzhuk cpsw->version != CPSW_VERSION_2 && 17332a05a622SIvan Khoronzhuk cpsw->version != CPSW_VERSION_3) 1734a5b4145bSBen Hutchings return -EOPNOTSUPP; 1735a5b4145bSBen Hutchings 1736a5b4145bSBen Hutchings cfg.flags = 0; 1737b63ba58eSGrygorii Strashko cfg.tx_type = cpts_is_tx_enabled(cpts) ? 1738b63ba58eSGrygorii Strashko HWTSTAMP_TX_ON : HWTSTAMP_TX_OFF; 1739b63ba58eSGrygorii Strashko cfg.rx_filter = (cpts_is_rx_enabled(cpts) ? 1740a5b4145bSBen Hutchings HWTSTAMP_FILTER_PTP_V2_EVENT : HWTSTAMP_FILTER_NONE); 1741a5b4145bSBen Hutchings 1742a5b4145bSBen Hutchings return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0; 1743a5b4145bSBen Hutchings } 1744c8395d4eSGrygorii Strashko #else 1745c8395d4eSGrygorii Strashko static int cpsw_hwtstamp_get(struct net_device *dev, struct ifreq *ifr) 1746c8395d4eSGrygorii Strashko { 1747c8395d4eSGrygorii Strashko return -EOPNOTSUPP; 1748c8395d4eSGrygorii Strashko } 1749a5b4145bSBen Hutchings 1750c8395d4eSGrygorii Strashko static int cpsw_hwtstamp_set(struct net_device *dev, struct ifreq *ifr) 1751c8395d4eSGrygorii Strashko { 1752c8395d4eSGrygorii Strashko return -EOPNOTSUPP; 1753c8395d4eSGrygorii Strashko } 17542e5b38abSRichard Cochran #endif /*CONFIG_TI_CPTS*/ 17552e5b38abSRichard Cochran 17562e5b38abSRichard Cochran static int cpsw_ndo_ioctl(struct net_device *dev, struct ifreq *req, int cmd) 17572e5b38abSRichard Cochran { 175811f2c988SMugunthan V N struct cpsw_priv *priv = netdev_priv(dev); 1759606f3993SIvan Khoronzhuk struct cpsw_common *cpsw = priv->cpsw; 1760606f3993SIvan Khoronzhuk int slave_no = cpsw_slave_index(cpsw, priv); 176111f2c988SMugunthan V N 17622e5b38abSRichard Cochran if (!netif_running(dev)) 17632e5b38abSRichard Cochran return -EINVAL; 17642e5b38abSRichard Cochran 176511f2c988SMugunthan V N switch (cmd) { 176611f2c988SMugunthan V N case SIOCSHWTSTAMP: 1767a5b4145bSBen Hutchings return cpsw_hwtstamp_set(dev, req); 1768a5b4145bSBen Hutchings case SIOCGHWTSTAMP: 1769a5b4145bSBen Hutchings return cpsw_hwtstamp_get(dev, req); 17702e5b38abSRichard Cochran } 17712e5b38abSRichard Cochran 1772606f3993SIvan Khoronzhuk if (!cpsw->slaves[slave_no].phy) 1773c1b59947SStefan Sørensen return -EOPNOTSUPP; 1774606f3993SIvan Khoronzhuk return phy_mii_ioctl(cpsw->slaves[slave_no].phy, req, cmd); 177511f2c988SMugunthan V N } 177611f2c988SMugunthan V N 1777df828598SMugunthan V N static void cpsw_ndo_tx_timeout(struct net_device *ndev) 1778df828598SMugunthan V N { 1779df828598SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 17802c836bd9SIvan Khoronzhuk struct cpsw_common *cpsw = priv->cpsw; 1781e05107e6SIvan Khoronzhuk int ch; 1782df828598SMugunthan V N 1783df828598SMugunthan V N cpsw_err(priv, tx_err, "transmit timeout, restarting dma\n"); 17848dc43ddcSTobias Klauser ndev->stats.tx_errors++; 17852c836bd9SIvan Khoronzhuk cpsw_intr_disable(cpsw); 1786e05107e6SIvan Khoronzhuk for (ch = 0; ch < cpsw->tx_ch_num; ch++) { 17878feb0a19SIvan Khoronzhuk cpdma_chan_stop(cpsw->txv[ch].ch); 17888feb0a19SIvan Khoronzhuk cpdma_chan_start(cpsw->txv[ch].ch); 1789e05107e6SIvan Khoronzhuk } 1790e05107e6SIvan Khoronzhuk 17912c836bd9SIvan Khoronzhuk cpsw_intr_enable(cpsw); 1792df828598SMugunthan V N } 1793df828598SMugunthan V N 1794dcfd8d58SMugunthan V N static int cpsw_ndo_set_mac_address(struct net_device *ndev, void *p) 1795dcfd8d58SMugunthan V N { 1796dcfd8d58SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 1797dcfd8d58SMugunthan V N struct sockaddr *addr = (struct sockaddr *)p; 1798649a1688SIvan Khoronzhuk struct cpsw_common *cpsw = priv->cpsw; 1799dcfd8d58SMugunthan V N int flags = 0; 1800dcfd8d58SMugunthan V N u16 vid = 0; 1801a6c5d14fSGrygorii Strashko int ret; 1802dcfd8d58SMugunthan V N 1803dcfd8d58SMugunthan V N if (!is_valid_ether_addr(addr->sa_data)) 1804dcfd8d58SMugunthan V N return -EADDRNOTAVAIL; 1805dcfd8d58SMugunthan V N 180656e31bd8SIvan Khoronzhuk ret = pm_runtime_get_sync(cpsw->dev); 1807a6c5d14fSGrygorii Strashko if (ret < 0) { 180856e31bd8SIvan Khoronzhuk pm_runtime_put_noidle(cpsw->dev); 1809a6c5d14fSGrygorii Strashko return ret; 1810a6c5d14fSGrygorii Strashko } 1811a6c5d14fSGrygorii Strashko 1812606f3993SIvan Khoronzhuk if (cpsw->data.dual_emac) { 1813606f3993SIvan Khoronzhuk vid = cpsw->slaves[priv->emac_port].port_vlan; 1814dcfd8d58SMugunthan V N flags = ALE_VLAN; 1815dcfd8d58SMugunthan V N } 1816dcfd8d58SMugunthan V N 18172a05a622SIvan Khoronzhuk cpsw_ale_del_ucast(cpsw->ale, priv->mac_addr, HOST_PORT_NUM, 1818dcfd8d58SMugunthan V N flags, vid); 18192a05a622SIvan Khoronzhuk cpsw_ale_add_ucast(cpsw->ale, addr->sa_data, HOST_PORT_NUM, 1820dcfd8d58SMugunthan V N flags, vid); 1821dcfd8d58SMugunthan V N 1822dcfd8d58SMugunthan V N memcpy(priv->mac_addr, addr->sa_data, ETH_ALEN); 1823dcfd8d58SMugunthan V N memcpy(ndev->dev_addr, priv->mac_addr, ETH_ALEN); 1824dcfd8d58SMugunthan V N for_each_slave(priv, cpsw_set_slave_mac, priv); 1825dcfd8d58SMugunthan V N 182656e31bd8SIvan Khoronzhuk pm_runtime_put(cpsw->dev); 1827a6c5d14fSGrygorii Strashko 1828dcfd8d58SMugunthan V N return 0; 1829dcfd8d58SMugunthan V N } 1830dcfd8d58SMugunthan V N 1831df828598SMugunthan V N #ifdef CONFIG_NET_POLL_CONTROLLER 1832df828598SMugunthan V N static void cpsw_ndo_poll_controller(struct net_device *ndev) 1833df828598SMugunthan V N { 1834dbc4ec52SIvan Khoronzhuk struct cpsw_common *cpsw = ndev_to_cpsw(ndev); 1835df828598SMugunthan V N 1836dbc4ec52SIvan Khoronzhuk cpsw_intr_disable(cpsw); 1837dbc4ec52SIvan Khoronzhuk cpsw_rx_interrupt(cpsw->irqs_table[0], cpsw); 1838dbc4ec52SIvan Khoronzhuk cpsw_tx_interrupt(cpsw->irqs_table[1], cpsw); 1839dbc4ec52SIvan Khoronzhuk cpsw_intr_enable(cpsw); 1840df828598SMugunthan V N } 1841df828598SMugunthan V N #endif 1842df828598SMugunthan V N 18433b72c2feSMugunthan V N static inline int cpsw_add_vlan_ale_entry(struct cpsw_priv *priv, 18443b72c2feSMugunthan V N unsigned short vid) 18453b72c2feSMugunthan V N { 18463b72c2feSMugunthan V N int ret; 18479f6bd8faSMugunthan V N int unreg_mcast_mask = 0; 18489f6bd8faSMugunthan V N u32 port_mask; 1849606f3993SIvan Khoronzhuk struct cpsw_common *cpsw = priv->cpsw; 18509f6bd8faSMugunthan V N 1851606f3993SIvan Khoronzhuk if (cpsw->data.dual_emac) { 18529f6bd8faSMugunthan V N port_mask = (1 << (priv->emac_port + 1)) | ALE_PORT_HOST; 18539f6bd8faSMugunthan V N 18549f6bd8faSMugunthan V N if (priv->ndev->flags & IFF_ALLMULTI) 18559f6bd8faSMugunthan V N unreg_mcast_mask = port_mask; 18569f6bd8faSMugunthan V N } else { 18579f6bd8faSMugunthan V N port_mask = ALE_ALL_PORTS; 18581e5c4bc4SLennart Sorensen 18591e5c4bc4SLennart Sorensen if (priv->ndev->flags & IFF_ALLMULTI) 18601e5c4bc4SLennart Sorensen unreg_mcast_mask = ALE_ALL_PORTS; 18611e5c4bc4SLennart Sorensen else 18621e5c4bc4SLennart Sorensen unreg_mcast_mask = ALE_PORT_1 | ALE_PORT_2; 18639f6bd8faSMugunthan V N } 18643b72c2feSMugunthan V N 18652a05a622SIvan Khoronzhuk ret = cpsw_ale_add_vlan(cpsw->ale, vid, port_mask, 0, port_mask, 186661f1cef9SGrygorii Strashko unreg_mcast_mask); 18673b72c2feSMugunthan V N if (ret != 0) 18683b72c2feSMugunthan V N return ret; 18693b72c2feSMugunthan V N 18702a05a622SIvan Khoronzhuk ret = cpsw_ale_add_ucast(cpsw->ale, priv->mac_addr, 187171a2cbb7SGrygorii Strashko HOST_PORT_NUM, ALE_VLAN, vid); 18723b72c2feSMugunthan V N if (ret != 0) 18733b72c2feSMugunthan V N goto clean_vid; 18743b72c2feSMugunthan V N 18752a05a622SIvan Khoronzhuk ret = cpsw_ale_add_mcast(cpsw->ale, priv->ndev->broadcast, 18769f6bd8faSMugunthan V N port_mask, ALE_VLAN, vid, 0); 18773b72c2feSMugunthan V N if (ret != 0) 18783b72c2feSMugunthan V N goto clean_vlan_ucast; 18793b72c2feSMugunthan V N return 0; 18803b72c2feSMugunthan V N 18813b72c2feSMugunthan V N clean_vlan_ucast: 18822a05a622SIvan Khoronzhuk cpsw_ale_del_ucast(cpsw->ale, priv->mac_addr, 188371a2cbb7SGrygorii Strashko HOST_PORT_NUM, ALE_VLAN, vid); 18843b72c2feSMugunthan V N clean_vid: 18852a05a622SIvan Khoronzhuk cpsw_ale_del_vlan(cpsw->ale, vid, 0); 18863b72c2feSMugunthan V N return ret; 18873b72c2feSMugunthan V N } 18883b72c2feSMugunthan V N 18893b72c2feSMugunthan V N static int cpsw_ndo_vlan_rx_add_vid(struct net_device *ndev, 189080d5c368SPatrick McHardy __be16 proto, u16 vid) 18913b72c2feSMugunthan V N { 18923b72c2feSMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 1893649a1688SIvan Khoronzhuk struct cpsw_common *cpsw = priv->cpsw; 1894a6c5d14fSGrygorii Strashko int ret; 18953b72c2feSMugunthan V N 1896606f3993SIvan Khoronzhuk if (vid == cpsw->data.default_vlan) 18973b72c2feSMugunthan V N return 0; 18983b72c2feSMugunthan V N 189956e31bd8SIvan Khoronzhuk ret = pm_runtime_get_sync(cpsw->dev); 1900a6c5d14fSGrygorii Strashko if (ret < 0) { 190156e31bd8SIvan Khoronzhuk pm_runtime_put_noidle(cpsw->dev); 1902a6c5d14fSGrygorii Strashko return ret; 1903a6c5d14fSGrygorii Strashko } 1904a6c5d14fSGrygorii Strashko 1905606f3993SIvan Khoronzhuk if (cpsw->data.dual_emac) { 190602a54164SMugunthan V N /* In dual EMAC, reserved VLAN id should not be used for 190702a54164SMugunthan V N * creating VLAN interfaces as this can break the dual 190802a54164SMugunthan V N * EMAC port separation 190902a54164SMugunthan V N */ 191002a54164SMugunthan V N int i; 191102a54164SMugunthan V N 1912606f3993SIvan Khoronzhuk for (i = 0; i < cpsw->data.slaves; i++) { 1913606f3993SIvan Khoronzhuk if (vid == cpsw->slaves[i].port_vlan) 191402a54164SMugunthan V N return -EINVAL; 191502a54164SMugunthan V N } 191602a54164SMugunthan V N } 191702a54164SMugunthan V N 19183b72c2feSMugunthan V N dev_info(priv->dev, "Adding vlanid %d to vlan filter\n", vid); 1919a6c5d14fSGrygorii Strashko ret = cpsw_add_vlan_ale_entry(priv, vid); 1920a6c5d14fSGrygorii Strashko 192156e31bd8SIvan Khoronzhuk pm_runtime_put(cpsw->dev); 1922a6c5d14fSGrygorii Strashko return ret; 19233b72c2feSMugunthan V N } 19243b72c2feSMugunthan V N 19253b72c2feSMugunthan V N static int cpsw_ndo_vlan_rx_kill_vid(struct net_device *ndev, 192680d5c368SPatrick McHardy __be16 proto, u16 vid) 19273b72c2feSMugunthan V N { 19283b72c2feSMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 1929649a1688SIvan Khoronzhuk struct cpsw_common *cpsw = priv->cpsw; 19303b72c2feSMugunthan V N int ret; 19313b72c2feSMugunthan V N 1932606f3993SIvan Khoronzhuk if (vid == cpsw->data.default_vlan) 19333b72c2feSMugunthan V N return 0; 19343b72c2feSMugunthan V N 193556e31bd8SIvan Khoronzhuk ret = pm_runtime_get_sync(cpsw->dev); 1936a6c5d14fSGrygorii Strashko if (ret < 0) { 193756e31bd8SIvan Khoronzhuk pm_runtime_put_noidle(cpsw->dev); 1938a6c5d14fSGrygorii Strashko return ret; 1939a6c5d14fSGrygorii Strashko } 1940a6c5d14fSGrygorii Strashko 1941606f3993SIvan Khoronzhuk if (cpsw->data.dual_emac) { 194202a54164SMugunthan V N int i; 194302a54164SMugunthan V N 1944606f3993SIvan Khoronzhuk for (i = 0; i < cpsw->data.slaves; i++) { 1945606f3993SIvan Khoronzhuk if (vid == cpsw->slaves[i].port_vlan) 194602a54164SMugunthan V N return -EINVAL; 194702a54164SMugunthan V N } 194802a54164SMugunthan V N } 194902a54164SMugunthan V N 19503b72c2feSMugunthan V N dev_info(priv->dev, "removing vlanid %d from vlan filter\n", vid); 19512a05a622SIvan Khoronzhuk ret = cpsw_ale_del_vlan(cpsw->ale, vid, 0); 19523b72c2feSMugunthan V N if (ret != 0) 19533b72c2feSMugunthan V N return ret; 19543b72c2feSMugunthan V N 19552a05a622SIvan Khoronzhuk ret = cpsw_ale_del_ucast(cpsw->ale, priv->mac_addr, 195661f1cef9SGrygorii Strashko HOST_PORT_NUM, ALE_VLAN, vid); 19573b72c2feSMugunthan V N if (ret != 0) 19583b72c2feSMugunthan V N return ret; 19593b72c2feSMugunthan V N 19602a05a622SIvan Khoronzhuk ret = cpsw_ale_del_mcast(cpsw->ale, priv->ndev->broadcast, 19613b72c2feSMugunthan V N 0, ALE_VLAN, vid); 196256e31bd8SIvan Khoronzhuk pm_runtime_put(cpsw->dev); 1963a6c5d14fSGrygorii Strashko return ret; 19643b72c2feSMugunthan V N } 19653b72c2feSMugunthan V N 196683fcad0cSIvan Khoronzhuk static int cpsw_ndo_set_tx_maxrate(struct net_device *ndev, int queue, u32 rate) 196783fcad0cSIvan Khoronzhuk { 196883fcad0cSIvan Khoronzhuk struct cpsw_priv *priv = netdev_priv(ndev); 196983fcad0cSIvan Khoronzhuk struct cpsw_common *cpsw = priv->cpsw; 197032b78d85SIvan Khoronzhuk u32 min_rate; 197183fcad0cSIvan Khoronzhuk u32 ch_rate; 197232b78d85SIvan Khoronzhuk int ret; 197383fcad0cSIvan Khoronzhuk 197483fcad0cSIvan Khoronzhuk ch_rate = netdev_get_tx_queue(ndev, queue)->tx_maxrate; 197583fcad0cSIvan Khoronzhuk if (ch_rate == rate) 197683fcad0cSIvan Khoronzhuk return 0; 197783fcad0cSIvan Khoronzhuk 197832b78d85SIvan Khoronzhuk ch_rate = rate * 1000; 197983fcad0cSIvan Khoronzhuk min_rate = cpdma_chan_get_min_rate(cpsw->dma); 198032b78d85SIvan Khoronzhuk if ((ch_rate < min_rate && ch_rate)) { 198132b78d85SIvan Khoronzhuk dev_err(priv->dev, "The channel rate cannot be less than %dMbps", 198283fcad0cSIvan Khoronzhuk min_rate); 198383fcad0cSIvan Khoronzhuk return -EINVAL; 198483fcad0cSIvan Khoronzhuk } 198583fcad0cSIvan Khoronzhuk 198632b78d85SIvan Khoronzhuk if (rate > 2000) { 198732b78d85SIvan Khoronzhuk dev_err(priv->dev, "The channel rate cannot be more than 2Gbps"); 198832b78d85SIvan Khoronzhuk return -EINVAL; 198932b78d85SIvan Khoronzhuk } 199032b78d85SIvan Khoronzhuk 199183fcad0cSIvan Khoronzhuk ret = pm_runtime_get_sync(cpsw->dev); 199283fcad0cSIvan Khoronzhuk if (ret < 0) { 199383fcad0cSIvan Khoronzhuk pm_runtime_put_noidle(cpsw->dev); 199483fcad0cSIvan Khoronzhuk return ret; 199583fcad0cSIvan Khoronzhuk } 199683fcad0cSIvan Khoronzhuk 199732b78d85SIvan Khoronzhuk ret = cpdma_chan_set_rate(cpsw->txv[queue].ch, ch_rate); 199883fcad0cSIvan Khoronzhuk pm_runtime_put(cpsw->dev); 199932b78d85SIvan Khoronzhuk 200032b78d85SIvan Khoronzhuk if (ret) 200132b78d85SIvan Khoronzhuk return ret; 200232b78d85SIvan Khoronzhuk 200332b78d85SIvan Khoronzhuk cpsw_split_res(ndev); 200483fcad0cSIvan Khoronzhuk return ret; 200583fcad0cSIvan Khoronzhuk } 200683fcad0cSIvan Khoronzhuk 2007df828598SMugunthan V N static const struct net_device_ops cpsw_netdev_ops = { 2008df828598SMugunthan V N .ndo_open = cpsw_ndo_open, 2009df828598SMugunthan V N .ndo_stop = cpsw_ndo_stop, 2010df828598SMugunthan V N .ndo_start_xmit = cpsw_ndo_start_xmit, 2011dcfd8d58SMugunthan V N .ndo_set_mac_address = cpsw_ndo_set_mac_address, 20122e5b38abSRichard Cochran .ndo_do_ioctl = cpsw_ndo_ioctl, 2013df828598SMugunthan V N .ndo_validate_addr = eth_validate_addr, 2014df828598SMugunthan V N .ndo_tx_timeout = cpsw_ndo_tx_timeout, 20155c50a856SMugunthan V N .ndo_set_rx_mode = cpsw_ndo_set_rx_mode, 201683fcad0cSIvan Khoronzhuk .ndo_set_tx_maxrate = cpsw_ndo_set_tx_maxrate, 2017df828598SMugunthan V N #ifdef CONFIG_NET_POLL_CONTROLLER 2018df828598SMugunthan V N .ndo_poll_controller = cpsw_ndo_poll_controller, 2019df828598SMugunthan V N #endif 20203b72c2feSMugunthan V N .ndo_vlan_rx_add_vid = cpsw_ndo_vlan_rx_add_vid, 20213b72c2feSMugunthan V N .ndo_vlan_rx_kill_vid = cpsw_ndo_vlan_rx_kill_vid, 2022df828598SMugunthan V N }; 2023df828598SMugunthan V N 202452c4f0ecSMugunthan V N static int cpsw_get_regs_len(struct net_device *ndev) 202552c4f0ecSMugunthan V N { 2026606f3993SIvan Khoronzhuk struct cpsw_common *cpsw = ndev_to_cpsw(ndev); 202752c4f0ecSMugunthan V N 2028606f3993SIvan Khoronzhuk return cpsw->data.ale_entries * ALE_ENTRY_WORDS * sizeof(u32); 202952c4f0ecSMugunthan V N } 203052c4f0ecSMugunthan V N 203152c4f0ecSMugunthan V N static void cpsw_get_regs(struct net_device *ndev, 203252c4f0ecSMugunthan V N struct ethtool_regs *regs, void *p) 203352c4f0ecSMugunthan V N { 203452c4f0ecSMugunthan V N u32 *reg = p; 20352a05a622SIvan Khoronzhuk struct cpsw_common *cpsw = ndev_to_cpsw(ndev); 203652c4f0ecSMugunthan V N 203752c4f0ecSMugunthan V N /* update CPSW IP version */ 20382a05a622SIvan Khoronzhuk regs->version = cpsw->version; 203952c4f0ecSMugunthan V N 20402a05a622SIvan Khoronzhuk cpsw_ale_dump(cpsw->ale, reg); 204152c4f0ecSMugunthan V N } 204252c4f0ecSMugunthan V N 2043df828598SMugunthan V N static void cpsw_get_drvinfo(struct net_device *ndev, 2044df828598SMugunthan V N struct ethtool_drvinfo *info) 2045df828598SMugunthan V N { 2046649a1688SIvan Khoronzhuk struct cpsw_common *cpsw = ndev_to_cpsw(ndev); 204756e31bd8SIvan Khoronzhuk struct platform_device *pdev = to_platform_device(cpsw->dev); 20487826d43fSJiri Pirko 204952c4f0ecSMugunthan V N strlcpy(info->driver, "cpsw", sizeof(info->driver)); 20507826d43fSJiri Pirko strlcpy(info->version, "1.0", sizeof(info->version)); 205156e31bd8SIvan Khoronzhuk strlcpy(info->bus_info, pdev->name, sizeof(info->bus_info)); 2052df828598SMugunthan V N } 2053df828598SMugunthan V N 2054df828598SMugunthan V N static u32 cpsw_get_msglevel(struct net_device *ndev) 2055df828598SMugunthan V N { 2056df828598SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 2057df828598SMugunthan V N return priv->msg_enable; 2058df828598SMugunthan V N } 2059df828598SMugunthan V N 2060df828598SMugunthan V N static void cpsw_set_msglevel(struct net_device *ndev, u32 value) 2061df828598SMugunthan V N { 2062df828598SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 2063df828598SMugunthan V N priv->msg_enable = value; 2064df828598SMugunthan V N } 2065df828598SMugunthan V N 2066c8395d4eSGrygorii Strashko #if IS_ENABLED(CONFIG_TI_CPTS) 20672e5b38abSRichard Cochran static int cpsw_get_ts_info(struct net_device *ndev, 20682e5b38abSRichard Cochran struct ethtool_ts_info *info) 20692e5b38abSRichard Cochran { 20702a05a622SIvan Khoronzhuk struct cpsw_common *cpsw = ndev_to_cpsw(ndev); 20712e5b38abSRichard Cochran 20722e5b38abSRichard Cochran info->so_timestamping = 20732e5b38abSRichard Cochran SOF_TIMESTAMPING_TX_HARDWARE | 20742e5b38abSRichard Cochran SOF_TIMESTAMPING_TX_SOFTWARE | 20752e5b38abSRichard Cochran SOF_TIMESTAMPING_RX_HARDWARE | 20762e5b38abSRichard Cochran SOF_TIMESTAMPING_RX_SOFTWARE | 20772e5b38abSRichard Cochran SOF_TIMESTAMPING_SOFTWARE | 20782e5b38abSRichard Cochran SOF_TIMESTAMPING_RAW_HARDWARE; 20792a05a622SIvan Khoronzhuk info->phc_index = cpsw->cpts->phc_index; 20802e5b38abSRichard Cochran info->tx_types = 20812e5b38abSRichard Cochran (1 << HWTSTAMP_TX_OFF) | 20822e5b38abSRichard Cochran (1 << HWTSTAMP_TX_ON); 20832e5b38abSRichard Cochran info->rx_filters = 20842e5b38abSRichard Cochran (1 << HWTSTAMP_FILTER_NONE) | 20852e5b38abSRichard Cochran (1 << HWTSTAMP_FILTER_PTP_V2_EVENT); 2086c8395d4eSGrygorii Strashko return 0; 2087c8395d4eSGrygorii Strashko } 20882e5b38abSRichard Cochran #else 2089c8395d4eSGrygorii Strashko static int cpsw_get_ts_info(struct net_device *ndev, 2090c8395d4eSGrygorii Strashko struct ethtool_ts_info *info) 2091c8395d4eSGrygorii Strashko { 20922e5b38abSRichard Cochran info->so_timestamping = 20932e5b38abSRichard Cochran SOF_TIMESTAMPING_TX_SOFTWARE | 20942e5b38abSRichard Cochran SOF_TIMESTAMPING_RX_SOFTWARE | 20952e5b38abSRichard Cochran SOF_TIMESTAMPING_SOFTWARE; 20962e5b38abSRichard Cochran info->phc_index = -1; 20972e5b38abSRichard Cochran info->tx_types = 0; 20982e5b38abSRichard Cochran info->rx_filters = 0; 20992e5b38abSRichard Cochran return 0; 21002e5b38abSRichard Cochran } 2101c8395d4eSGrygorii Strashko #endif 21022e5b38abSRichard Cochran 21032479876dSPhilippe Reynes static int cpsw_get_link_ksettings(struct net_device *ndev, 21042479876dSPhilippe Reynes struct ethtool_link_ksettings *ecmd) 2105d3bb9c58SMugunthan V N { 2106d3bb9c58SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 2107606f3993SIvan Khoronzhuk struct cpsw_common *cpsw = priv->cpsw; 2108606f3993SIvan Khoronzhuk int slave_no = cpsw_slave_index(cpsw, priv); 2109d3bb9c58SMugunthan V N 2110606f3993SIvan Khoronzhuk if (cpsw->slaves[slave_no].phy) 21112479876dSPhilippe Reynes return phy_ethtool_ksettings_get(cpsw->slaves[slave_no].phy, 21122479876dSPhilippe Reynes ecmd); 2113d3bb9c58SMugunthan V N else 2114d3bb9c58SMugunthan V N return -EOPNOTSUPP; 2115d3bb9c58SMugunthan V N } 2116d3bb9c58SMugunthan V N 21172479876dSPhilippe Reynes static int cpsw_set_link_ksettings(struct net_device *ndev, 21182479876dSPhilippe Reynes const struct ethtool_link_ksettings *ecmd) 2119d3bb9c58SMugunthan V N { 2120d3bb9c58SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 2121606f3993SIvan Khoronzhuk struct cpsw_common *cpsw = priv->cpsw; 2122606f3993SIvan Khoronzhuk int slave_no = cpsw_slave_index(cpsw, priv); 2123d3bb9c58SMugunthan V N 2124606f3993SIvan Khoronzhuk if (cpsw->slaves[slave_no].phy) 21252479876dSPhilippe Reynes return phy_ethtool_ksettings_set(cpsw->slaves[slave_no].phy, 21262479876dSPhilippe Reynes ecmd); 2127d3bb9c58SMugunthan V N else 2128d3bb9c58SMugunthan V N return -EOPNOTSUPP; 2129d3bb9c58SMugunthan V N } 2130d3bb9c58SMugunthan V N 2131d8a64420SMatus Ujhelyi static void cpsw_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol) 2132d8a64420SMatus Ujhelyi { 2133d8a64420SMatus Ujhelyi struct cpsw_priv *priv = netdev_priv(ndev); 2134606f3993SIvan Khoronzhuk struct cpsw_common *cpsw = priv->cpsw; 2135606f3993SIvan Khoronzhuk int slave_no = cpsw_slave_index(cpsw, priv); 2136d8a64420SMatus Ujhelyi 2137d8a64420SMatus Ujhelyi wol->supported = 0; 2138d8a64420SMatus Ujhelyi wol->wolopts = 0; 2139d8a64420SMatus Ujhelyi 2140606f3993SIvan Khoronzhuk if (cpsw->slaves[slave_no].phy) 2141606f3993SIvan Khoronzhuk phy_ethtool_get_wol(cpsw->slaves[slave_no].phy, wol); 2142d8a64420SMatus Ujhelyi } 2143d8a64420SMatus Ujhelyi 2144d8a64420SMatus Ujhelyi static int cpsw_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol) 2145d8a64420SMatus Ujhelyi { 2146d8a64420SMatus Ujhelyi struct cpsw_priv *priv = netdev_priv(ndev); 2147606f3993SIvan Khoronzhuk struct cpsw_common *cpsw = priv->cpsw; 2148606f3993SIvan Khoronzhuk int slave_no = cpsw_slave_index(cpsw, priv); 2149d8a64420SMatus Ujhelyi 2150606f3993SIvan Khoronzhuk if (cpsw->slaves[slave_no].phy) 2151606f3993SIvan Khoronzhuk return phy_ethtool_set_wol(cpsw->slaves[slave_no].phy, wol); 2152d8a64420SMatus Ujhelyi else 2153d8a64420SMatus Ujhelyi return -EOPNOTSUPP; 2154d8a64420SMatus Ujhelyi } 2155d8a64420SMatus Ujhelyi 21561923d6e4SMugunthan V N static void cpsw_get_pauseparam(struct net_device *ndev, 21571923d6e4SMugunthan V N struct ethtool_pauseparam *pause) 21581923d6e4SMugunthan V N { 21591923d6e4SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 21601923d6e4SMugunthan V N 21611923d6e4SMugunthan V N pause->autoneg = AUTONEG_DISABLE; 21621923d6e4SMugunthan V N pause->rx_pause = priv->rx_pause ? true : false; 21631923d6e4SMugunthan V N pause->tx_pause = priv->tx_pause ? true : false; 21641923d6e4SMugunthan V N } 21651923d6e4SMugunthan V N 21661923d6e4SMugunthan V N static int cpsw_set_pauseparam(struct net_device *ndev, 21671923d6e4SMugunthan V N struct ethtool_pauseparam *pause) 21681923d6e4SMugunthan V N { 21691923d6e4SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 21701923d6e4SMugunthan V N bool link; 21711923d6e4SMugunthan V N 21721923d6e4SMugunthan V N priv->rx_pause = pause->rx_pause ? true : false; 21731923d6e4SMugunthan V N priv->tx_pause = pause->tx_pause ? true : false; 21741923d6e4SMugunthan V N 21751923d6e4SMugunthan V N for_each_slave(priv, _cpsw_adjust_link, priv, &link); 21761923d6e4SMugunthan V N return 0; 21771923d6e4SMugunthan V N } 21781923d6e4SMugunthan V N 21797898b1daSGrygorii Strashko static int cpsw_ethtool_op_begin(struct net_device *ndev) 21807898b1daSGrygorii Strashko { 21817898b1daSGrygorii Strashko struct cpsw_priv *priv = netdev_priv(ndev); 2182649a1688SIvan Khoronzhuk struct cpsw_common *cpsw = priv->cpsw; 21837898b1daSGrygorii Strashko int ret; 21847898b1daSGrygorii Strashko 218556e31bd8SIvan Khoronzhuk ret = pm_runtime_get_sync(cpsw->dev); 21867898b1daSGrygorii Strashko if (ret < 0) { 21877898b1daSGrygorii Strashko cpsw_err(priv, drv, "ethtool begin failed %d\n", ret); 218856e31bd8SIvan Khoronzhuk pm_runtime_put_noidle(cpsw->dev); 21897898b1daSGrygorii Strashko } 21907898b1daSGrygorii Strashko 21917898b1daSGrygorii Strashko return ret; 21927898b1daSGrygorii Strashko } 21937898b1daSGrygorii Strashko 21947898b1daSGrygorii Strashko static void cpsw_ethtool_op_complete(struct net_device *ndev) 21957898b1daSGrygorii Strashko { 21967898b1daSGrygorii Strashko struct cpsw_priv *priv = netdev_priv(ndev); 21977898b1daSGrygorii Strashko int ret; 21987898b1daSGrygorii Strashko 219956e31bd8SIvan Khoronzhuk ret = pm_runtime_put(priv->cpsw->dev); 22007898b1daSGrygorii Strashko if (ret < 0) 22017898b1daSGrygorii Strashko cpsw_err(priv, drv, "ethtool complete failed %d\n", ret); 22027898b1daSGrygorii Strashko } 22037898b1daSGrygorii Strashko 2204ce52c744SIvan Khoronzhuk static void cpsw_get_channels(struct net_device *ndev, 2205ce52c744SIvan Khoronzhuk struct ethtool_channels *ch) 2206ce52c744SIvan Khoronzhuk { 2207ce52c744SIvan Khoronzhuk struct cpsw_common *cpsw = ndev_to_cpsw(ndev); 2208ce52c744SIvan Khoronzhuk 2209ce52c744SIvan Khoronzhuk ch->max_combined = 0; 2210ce52c744SIvan Khoronzhuk ch->max_rx = CPSW_MAX_QUEUES; 2211ce52c744SIvan Khoronzhuk ch->max_tx = CPSW_MAX_QUEUES; 2212ce52c744SIvan Khoronzhuk ch->max_other = 0; 2213ce52c744SIvan Khoronzhuk ch->other_count = 0; 2214ce52c744SIvan Khoronzhuk ch->rx_count = cpsw->rx_ch_num; 2215ce52c744SIvan Khoronzhuk ch->tx_count = cpsw->tx_ch_num; 2216ce52c744SIvan Khoronzhuk ch->combined_count = 0; 2217ce52c744SIvan Khoronzhuk } 2218ce52c744SIvan Khoronzhuk 2219ce52c744SIvan Khoronzhuk static int cpsw_check_ch_settings(struct cpsw_common *cpsw, 2220ce52c744SIvan Khoronzhuk struct ethtool_channels *ch) 2221ce52c744SIvan Khoronzhuk { 2222ce52c744SIvan Khoronzhuk if (ch->combined_count) 2223ce52c744SIvan Khoronzhuk return -EINVAL; 2224ce52c744SIvan Khoronzhuk 2225ce52c744SIvan Khoronzhuk /* verify we have at least one channel in each direction */ 2226ce52c744SIvan Khoronzhuk if (!ch->rx_count || !ch->tx_count) 2227ce52c744SIvan Khoronzhuk return -EINVAL; 2228ce52c744SIvan Khoronzhuk 2229ce52c744SIvan Khoronzhuk if (ch->rx_count > cpsw->data.channels || 2230ce52c744SIvan Khoronzhuk ch->tx_count > cpsw->data.channels) 2231ce52c744SIvan Khoronzhuk return -EINVAL; 2232ce52c744SIvan Khoronzhuk 2233ce52c744SIvan Khoronzhuk return 0; 2234ce52c744SIvan Khoronzhuk } 2235ce52c744SIvan Khoronzhuk 2236ce52c744SIvan Khoronzhuk static int cpsw_update_channels_res(struct cpsw_priv *priv, int ch_num, int rx) 2237ce52c744SIvan Khoronzhuk { 2238ce52c744SIvan Khoronzhuk int (*poll)(struct napi_struct *, int); 2239ce52c744SIvan Khoronzhuk struct cpsw_common *cpsw = priv->cpsw; 2240ce52c744SIvan Khoronzhuk void (*handler)(void *, int, int); 224183fcad0cSIvan Khoronzhuk struct netdev_queue *queue; 22428feb0a19SIvan Khoronzhuk struct cpsw_vector *vec; 2243ce52c744SIvan Khoronzhuk int ret, *ch; 2244ce52c744SIvan Khoronzhuk 2245ce52c744SIvan Khoronzhuk if (rx) { 2246ce52c744SIvan Khoronzhuk ch = &cpsw->rx_ch_num; 22478feb0a19SIvan Khoronzhuk vec = cpsw->rxv; 2248ce52c744SIvan Khoronzhuk handler = cpsw_rx_handler; 2249ce52c744SIvan Khoronzhuk poll = cpsw_rx_poll; 2250ce52c744SIvan Khoronzhuk } else { 2251ce52c744SIvan Khoronzhuk ch = &cpsw->tx_ch_num; 22528feb0a19SIvan Khoronzhuk vec = cpsw->txv; 2253ce52c744SIvan Khoronzhuk handler = cpsw_tx_handler; 2254ce52c744SIvan Khoronzhuk poll = cpsw_tx_poll; 2255ce52c744SIvan Khoronzhuk } 2256ce52c744SIvan Khoronzhuk 2257ce52c744SIvan Khoronzhuk while (*ch < ch_num) { 22588feb0a19SIvan Khoronzhuk vec[*ch].ch = cpdma_chan_create(cpsw->dma, *ch, handler, rx); 225983fcad0cSIvan Khoronzhuk queue = netdev_get_tx_queue(priv->ndev, *ch); 226083fcad0cSIvan Khoronzhuk queue->tx_maxrate = 0; 2261ce52c744SIvan Khoronzhuk 22628feb0a19SIvan Khoronzhuk if (IS_ERR(vec[*ch].ch)) 22638feb0a19SIvan Khoronzhuk return PTR_ERR(vec[*ch].ch); 2264ce52c744SIvan Khoronzhuk 22658feb0a19SIvan Khoronzhuk if (!vec[*ch].ch) 2266ce52c744SIvan Khoronzhuk return -EINVAL; 2267ce52c744SIvan Khoronzhuk 2268ce52c744SIvan Khoronzhuk cpsw_info(priv, ifup, "created new %d %s channel\n", *ch, 2269ce52c744SIvan Khoronzhuk (rx ? "rx" : "tx")); 2270ce52c744SIvan Khoronzhuk (*ch)++; 2271ce52c744SIvan Khoronzhuk } 2272ce52c744SIvan Khoronzhuk 2273ce52c744SIvan Khoronzhuk while (*ch > ch_num) { 2274ce52c744SIvan Khoronzhuk (*ch)--; 2275ce52c744SIvan Khoronzhuk 22768feb0a19SIvan Khoronzhuk ret = cpdma_chan_destroy(vec[*ch].ch); 2277ce52c744SIvan Khoronzhuk if (ret) 2278ce52c744SIvan Khoronzhuk return ret; 2279ce52c744SIvan Khoronzhuk 2280ce52c744SIvan Khoronzhuk cpsw_info(priv, ifup, "destroyed %d %s channel\n", *ch, 2281ce52c744SIvan Khoronzhuk (rx ? "rx" : "tx")); 2282ce52c744SIvan Khoronzhuk } 2283ce52c744SIvan Khoronzhuk 2284ce52c744SIvan Khoronzhuk return 0; 2285ce52c744SIvan Khoronzhuk } 2286ce52c744SIvan Khoronzhuk 2287ce52c744SIvan Khoronzhuk static int cpsw_update_channels(struct cpsw_priv *priv, 2288ce52c744SIvan Khoronzhuk struct ethtool_channels *ch) 2289ce52c744SIvan Khoronzhuk { 2290ce52c744SIvan Khoronzhuk int ret; 2291ce52c744SIvan Khoronzhuk 2292ce52c744SIvan Khoronzhuk ret = cpsw_update_channels_res(priv, ch->rx_count, 1); 2293ce52c744SIvan Khoronzhuk if (ret) 2294ce52c744SIvan Khoronzhuk return ret; 2295ce52c744SIvan Khoronzhuk 2296ce52c744SIvan Khoronzhuk ret = cpsw_update_channels_res(priv, ch->tx_count, 0); 2297ce52c744SIvan Khoronzhuk if (ret) 2298ce52c744SIvan Khoronzhuk return ret; 2299ce52c744SIvan Khoronzhuk 2300ce52c744SIvan Khoronzhuk return 0; 2301ce52c744SIvan Khoronzhuk } 2302ce52c744SIvan Khoronzhuk 2303ce52c744SIvan Khoronzhuk static int cpsw_set_channels(struct net_device *ndev, 2304ce52c744SIvan Khoronzhuk struct ethtool_channels *chs) 2305ce52c744SIvan Khoronzhuk { 2306ce52c744SIvan Khoronzhuk struct cpsw_priv *priv = netdev_priv(ndev); 2307ce52c744SIvan Khoronzhuk struct cpsw_common *cpsw = priv->cpsw; 2308ce52c744SIvan Khoronzhuk struct cpsw_slave *slave; 2309ce52c744SIvan Khoronzhuk int i, ret; 2310ce52c744SIvan Khoronzhuk 2311ce52c744SIvan Khoronzhuk ret = cpsw_check_ch_settings(cpsw, chs); 2312ce52c744SIvan Khoronzhuk if (ret < 0) 2313ce52c744SIvan Khoronzhuk return ret; 2314ce52c744SIvan Khoronzhuk 2315ce52c744SIvan Khoronzhuk /* Disable NAPI scheduling */ 2316ce52c744SIvan Khoronzhuk cpsw_intr_disable(cpsw); 2317ce52c744SIvan Khoronzhuk 2318ce52c744SIvan Khoronzhuk /* Stop all transmit queues for every network device. 2319ce52c744SIvan Khoronzhuk * Disable re-using rx descriptors with dormant_on. 2320ce52c744SIvan Khoronzhuk */ 2321ce52c744SIvan Khoronzhuk for (i = cpsw->data.slaves, slave = cpsw->slaves; i; i--, slave++) { 2322ce52c744SIvan Khoronzhuk if (!(slave->ndev && netif_running(slave->ndev))) 2323ce52c744SIvan Khoronzhuk continue; 2324ce52c744SIvan Khoronzhuk 2325ce52c744SIvan Khoronzhuk netif_tx_stop_all_queues(slave->ndev); 2326ce52c744SIvan Khoronzhuk netif_dormant_on(slave->ndev); 2327ce52c744SIvan Khoronzhuk } 2328ce52c744SIvan Khoronzhuk 2329ce52c744SIvan Khoronzhuk /* Handle rest of tx packets and stop cpdma channels */ 2330ce52c744SIvan Khoronzhuk cpdma_ctlr_stop(cpsw->dma); 2331ce52c744SIvan Khoronzhuk ret = cpsw_update_channels(priv, chs); 2332ce52c744SIvan Khoronzhuk if (ret) 2333ce52c744SIvan Khoronzhuk goto err; 2334ce52c744SIvan Khoronzhuk 2335ce52c744SIvan Khoronzhuk for (i = cpsw->data.slaves, slave = cpsw->slaves; i; i--, slave++) { 2336ce52c744SIvan Khoronzhuk if (!(slave->ndev && netif_running(slave->ndev))) 2337ce52c744SIvan Khoronzhuk continue; 2338ce52c744SIvan Khoronzhuk 2339ce52c744SIvan Khoronzhuk /* Inform stack about new count of queues */ 2340ce52c744SIvan Khoronzhuk ret = netif_set_real_num_tx_queues(slave->ndev, 2341ce52c744SIvan Khoronzhuk cpsw->tx_ch_num); 2342ce52c744SIvan Khoronzhuk if (ret) { 2343ce52c744SIvan Khoronzhuk dev_err(priv->dev, "cannot set real number of tx queues\n"); 2344ce52c744SIvan Khoronzhuk goto err; 2345ce52c744SIvan Khoronzhuk } 2346ce52c744SIvan Khoronzhuk 2347ce52c744SIvan Khoronzhuk ret = netif_set_real_num_rx_queues(slave->ndev, 2348ce52c744SIvan Khoronzhuk cpsw->rx_ch_num); 2349ce52c744SIvan Khoronzhuk if (ret) { 2350ce52c744SIvan Khoronzhuk dev_err(priv->dev, "cannot set real number of rx queues\n"); 2351ce52c744SIvan Khoronzhuk goto err; 2352ce52c744SIvan Khoronzhuk } 2353ce52c744SIvan Khoronzhuk 2354ce52c744SIvan Khoronzhuk /* Enable rx packets handling */ 2355ce52c744SIvan Khoronzhuk netif_dormant_off(slave->ndev); 2356ce52c744SIvan Khoronzhuk } 2357ce52c744SIvan Khoronzhuk 2358ce52c744SIvan Khoronzhuk if (cpsw_common_res_usage_state(cpsw)) { 2359e19ac157SWei Yongjun ret = cpsw_fill_rx_channels(priv); 2360e19ac157SWei Yongjun if (ret) 2361ce52c744SIvan Khoronzhuk goto err; 2362ce52c744SIvan Khoronzhuk 236332b78d85SIvan Khoronzhuk cpsw_split_res(ndev); 23648feb0a19SIvan Khoronzhuk 2365ce52c744SIvan Khoronzhuk /* After this receive is started */ 2366ce52c744SIvan Khoronzhuk cpdma_ctlr_start(cpsw->dma); 2367ce52c744SIvan Khoronzhuk cpsw_intr_enable(cpsw); 2368ce52c744SIvan Khoronzhuk } 2369ce52c744SIvan Khoronzhuk 2370ce52c744SIvan Khoronzhuk /* Resume transmit for every affected interface */ 2371ce52c744SIvan Khoronzhuk for (i = cpsw->data.slaves, slave = cpsw->slaves; i; i--, slave++) { 2372ce52c744SIvan Khoronzhuk if (!(slave->ndev && netif_running(slave->ndev))) 2373ce52c744SIvan Khoronzhuk continue; 2374ce52c744SIvan Khoronzhuk netif_tx_start_all_queues(slave->ndev); 2375ce52c744SIvan Khoronzhuk } 2376ce52c744SIvan Khoronzhuk return 0; 2377ce52c744SIvan Khoronzhuk err: 2378ce52c744SIvan Khoronzhuk dev_err(priv->dev, "cannot update channels number, closing device\n"); 2379ce52c744SIvan Khoronzhuk dev_close(ndev); 2380ce52c744SIvan Khoronzhuk return ret; 2381ce52c744SIvan Khoronzhuk } 2382ce52c744SIvan Khoronzhuk 2383a0909949SYegor Yefremov static int cpsw_get_eee(struct net_device *ndev, struct ethtool_eee *edata) 2384a0909949SYegor Yefremov { 2385a0909949SYegor Yefremov struct cpsw_priv *priv = netdev_priv(ndev); 2386a0909949SYegor Yefremov struct cpsw_common *cpsw = priv->cpsw; 2387a0909949SYegor Yefremov int slave_no = cpsw_slave_index(cpsw, priv); 2388a0909949SYegor Yefremov 2389a0909949SYegor Yefremov if (cpsw->slaves[slave_no].phy) 2390a0909949SYegor Yefremov return phy_ethtool_get_eee(cpsw->slaves[slave_no].phy, edata); 2391a0909949SYegor Yefremov else 2392a0909949SYegor Yefremov return -EOPNOTSUPP; 2393a0909949SYegor Yefremov } 2394a0909949SYegor Yefremov 2395a0909949SYegor Yefremov static int cpsw_set_eee(struct net_device *ndev, struct ethtool_eee *edata) 2396a0909949SYegor Yefremov { 2397a0909949SYegor Yefremov struct cpsw_priv *priv = netdev_priv(ndev); 2398a0909949SYegor Yefremov struct cpsw_common *cpsw = priv->cpsw; 2399a0909949SYegor Yefremov int slave_no = cpsw_slave_index(cpsw, priv); 2400a0909949SYegor Yefremov 2401a0909949SYegor Yefremov if (cpsw->slaves[slave_no].phy) 2402a0909949SYegor Yefremov return phy_ethtool_set_eee(cpsw->slaves[slave_no].phy, edata); 2403a0909949SYegor Yefremov else 2404a0909949SYegor Yefremov return -EOPNOTSUPP; 2405a0909949SYegor Yefremov } 2406a0909949SYegor Yefremov 24076bb10c2bSYegor Yefremov static int cpsw_nway_reset(struct net_device *ndev) 24086bb10c2bSYegor Yefremov { 24096bb10c2bSYegor Yefremov struct cpsw_priv *priv = netdev_priv(ndev); 24106bb10c2bSYegor Yefremov struct cpsw_common *cpsw = priv->cpsw; 24116bb10c2bSYegor Yefremov int slave_no = cpsw_slave_index(cpsw, priv); 24126bb10c2bSYegor Yefremov 24136bb10c2bSYegor Yefremov if (cpsw->slaves[slave_no].phy) 24146bb10c2bSYegor Yefremov return genphy_restart_aneg(cpsw->slaves[slave_no].phy); 24156bb10c2bSYegor Yefremov else 24166bb10c2bSYegor Yefremov return -EOPNOTSUPP; 24176bb10c2bSYegor Yefremov } 24186bb10c2bSYegor Yefremov 2419df828598SMugunthan V N static const struct ethtool_ops cpsw_ethtool_ops = { 2420df828598SMugunthan V N .get_drvinfo = cpsw_get_drvinfo, 2421df828598SMugunthan V N .get_msglevel = cpsw_get_msglevel, 2422df828598SMugunthan V N .set_msglevel = cpsw_set_msglevel, 2423df828598SMugunthan V N .get_link = ethtool_op_get_link, 24242e5b38abSRichard Cochran .get_ts_info = cpsw_get_ts_info, 2425ff5b8ef2SMugunthan V N .get_coalesce = cpsw_get_coalesce, 2426ff5b8ef2SMugunthan V N .set_coalesce = cpsw_set_coalesce, 2427d9718546SMugunthan V N .get_sset_count = cpsw_get_sset_count, 2428d9718546SMugunthan V N .get_strings = cpsw_get_strings, 2429d9718546SMugunthan V N .get_ethtool_stats = cpsw_get_ethtool_stats, 24301923d6e4SMugunthan V N .get_pauseparam = cpsw_get_pauseparam, 24311923d6e4SMugunthan V N .set_pauseparam = cpsw_set_pauseparam, 2432d8a64420SMatus Ujhelyi .get_wol = cpsw_get_wol, 2433d8a64420SMatus Ujhelyi .set_wol = cpsw_set_wol, 243452c4f0ecSMugunthan V N .get_regs_len = cpsw_get_regs_len, 243552c4f0ecSMugunthan V N .get_regs = cpsw_get_regs, 24367898b1daSGrygorii Strashko .begin = cpsw_ethtool_op_begin, 24377898b1daSGrygorii Strashko .complete = cpsw_ethtool_op_complete, 2438ce52c744SIvan Khoronzhuk .get_channels = cpsw_get_channels, 2439ce52c744SIvan Khoronzhuk .set_channels = cpsw_set_channels, 24402479876dSPhilippe Reynes .get_link_ksettings = cpsw_get_link_ksettings, 24412479876dSPhilippe Reynes .set_link_ksettings = cpsw_set_link_ksettings, 2442a0909949SYegor Yefremov .get_eee = cpsw_get_eee, 2443a0909949SYegor Yefremov .set_eee = cpsw_set_eee, 24446bb10c2bSYegor Yefremov .nway_reset = cpsw_nway_reset, 2445df828598SMugunthan V N }; 2446df828598SMugunthan V N 2447606f3993SIvan Khoronzhuk static void cpsw_slave_init(struct cpsw_slave *slave, struct cpsw_common *cpsw, 2448549985eeSRichard Cochran u32 slave_reg_ofs, u32 sliver_reg_ofs) 2449df828598SMugunthan V N { 24505d8d0d4dSIvan Khoronzhuk void __iomem *regs = cpsw->regs; 2451df828598SMugunthan V N int slave_num = slave->slave_num; 2452606f3993SIvan Khoronzhuk struct cpsw_slave_data *data = cpsw->data.slave_data + slave_num; 2453df828598SMugunthan V N 2454df828598SMugunthan V N slave->data = data; 2455549985eeSRichard Cochran slave->regs = regs + slave_reg_ofs; 2456549985eeSRichard Cochran slave->sliver = regs + sliver_reg_ofs; 2457d9ba8f9eSMugunthan V N slave->port_vlan = data->dual_emac_res_vlan; 2458df828598SMugunthan V N } 2459df828598SMugunthan V N 2460552165bcSDavid Rivshin static int cpsw_probe_dt(struct cpsw_platform_data *data, 24612eb32b0aSMugunthan V N struct platform_device *pdev) 24622eb32b0aSMugunthan V N { 24632eb32b0aSMugunthan V N struct device_node *node = pdev->dev.of_node; 24642eb32b0aSMugunthan V N struct device_node *slave_node; 24652eb32b0aSMugunthan V N int i = 0, ret; 24662eb32b0aSMugunthan V N u32 prop; 24672eb32b0aSMugunthan V N 24682eb32b0aSMugunthan V N if (!node) 24692eb32b0aSMugunthan V N return -EINVAL; 24702eb32b0aSMugunthan V N 24712eb32b0aSMugunthan V N if (of_property_read_u32(node, "slaves", &prop)) { 247288c99ff6SGeorge Cherian dev_err(&pdev->dev, "Missing slaves property in the DT.\n"); 24732eb32b0aSMugunthan V N return -EINVAL; 24742eb32b0aSMugunthan V N } 24752eb32b0aSMugunthan V N data->slaves = prop; 24762eb32b0aSMugunthan V N 2477e86ac13bSMugunthan V N if (of_property_read_u32(node, "active_slave", &prop)) { 247888c99ff6SGeorge Cherian dev_err(&pdev->dev, "Missing active_slave property in the DT.\n"); 2479aa1a15e2SDaniel Mack return -EINVAL; 248078ca0b28SRichard Cochran } 2481e86ac13bSMugunthan V N data->active_slave = prop; 248278ca0b28SRichard Cochran 2483aa1a15e2SDaniel Mack data->slave_data = devm_kzalloc(&pdev->dev, data->slaves 2484aa1a15e2SDaniel Mack * sizeof(struct cpsw_slave_data), 2485b2adaca9SJoe Perches GFP_KERNEL); 2486b2adaca9SJoe Perches if (!data->slave_data) 2487aa1a15e2SDaniel Mack return -ENOMEM; 24882eb32b0aSMugunthan V N 24892eb32b0aSMugunthan V N if (of_property_read_u32(node, "cpdma_channels", &prop)) { 249088c99ff6SGeorge Cherian dev_err(&pdev->dev, "Missing cpdma_channels property in the DT.\n"); 2491aa1a15e2SDaniel Mack return -EINVAL; 24922eb32b0aSMugunthan V N } 24932eb32b0aSMugunthan V N data->channels = prop; 24942eb32b0aSMugunthan V N 24952eb32b0aSMugunthan V N if (of_property_read_u32(node, "ale_entries", &prop)) { 249688c99ff6SGeorge Cherian dev_err(&pdev->dev, "Missing ale_entries property in the DT.\n"); 2497aa1a15e2SDaniel Mack return -EINVAL; 24982eb32b0aSMugunthan V N } 24992eb32b0aSMugunthan V N data->ale_entries = prop; 25002eb32b0aSMugunthan V N 25012eb32b0aSMugunthan V N if (of_property_read_u32(node, "bd_ram_size", &prop)) { 250288c99ff6SGeorge Cherian dev_err(&pdev->dev, "Missing bd_ram_size property in the DT.\n"); 2503aa1a15e2SDaniel Mack return -EINVAL; 25042eb32b0aSMugunthan V N } 25052eb32b0aSMugunthan V N data->bd_ram_size = prop; 25062eb32b0aSMugunthan V N 25072eb32b0aSMugunthan V N if (of_property_read_u32(node, "mac_control", &prop)) { 250888c99ff6SGeorge Cherian dev_err(&pdev->dev, "Missing mac_control property in the DT.\n"); 2509aa1a15e2SDaniel Mack return -EINVAL; 25102eb32b0aSMugunthan V N } 25112eb32b0aSMugunthan V N data->mac_control = prop; 25122eb32b0aSMugunthan V N 2513281abd96SMarkus Pargmann if (of_property_read_bool(node, "dual_emac")) 2514281abd96SMarkus Pargmann data->dual_emac = 1; 2515d9ba8f9eSMugunthan V N 25161fb19aa7SVaibhav Hiremath /* 25171fb19aa7SVaibhav Hiremath * Populate all the child nodes here... 25181fb19aa7SVaibhav Hiremath */ 25191fb19aa7SVaibhav Hiremath ret = of_platform_populate(node, NULL, NULL, &pdev->dev); 25201fb19aa7SVaibhav Hiremath /* We do not want to force this, as in some cases may not have child */ 25211fb19aa7SVaibhav Hiremath if (ret) 252288c99ff6SGeorge Cherian dev_warn(&pdev->dev, "Doesn't have any child node\n"); 25231fb19aa7SVaibhav Hiremath 25248658aaf2SBen Hutchings for_each_available_child_of_node(node, slave_node) { 2525549985eeSRichard Cochran struct cpsw_slave_data *slave_data = data->slave_data + i; 2526549985eeSRichard Cochran const void *mac_addr = NULL; 2527549985eeSRichard Cochran int lenp; 2528549985eeSRichard Cochran const __be32 *parp; 2529549985eeSRichard Cochran 2530f468b10eSMarkus Pargmann /* This is no slave child node, continue */ 2531f468b10eSMarkus Pargmann if (strcmp(slave_node->name, "slave")) 2532f468b10eSMarkus Pargmann continue; 2533f468b10eSMarkus Pargmann 2534552165bcSDavid Rivshin slave_data->phy_node = of_parse_phandle(slave_node, 2535552165bcSDavid Rivshin "phy-handle", 0); 2536f1eea5c1SDavid Rivshin parp = of_get_property(slave_node, "phy_id", &lenp); 2537ae092b5bSDavid Rivshin if (slave_data->phy_node) { 2538ae092b5bSDavid Rivshin dev_dbg(&pdev->dev, 2539ae092b5bSDavid Rivshin "slave[%d] using phy-handle=\"%s\"\n", 2540ae092b5bSDavid Rivshin i, slave_data->phy_node->full_name); 2541ae092b5bSDavid Rivshin } else if (of_phy_is_fixed_link(slave_node)) { 2542dfc0a6d3SDavid Rivshin /* In the case of a fixed PHY, the DT node associated 2543dfc0a6d3SDavid Rivshin * to the PHY is the Ethernet MAC DT node. 2544dfc0a6d3SDavid Rivshin */ 25451f71e8c9SMarkus Brunner ret = of_phy_register_fixed_link(slave_node); 254623a09873SJohan Hovold if (ret) { 254723a09873SJohan Hovold if (ret != -EPROBE_DEFER) 254823a09873SJohan Hovold dev_err(&pdev->dev, "failed to register fixed-link phy: %d\n", ret); 25491f71e8c9SMarkus Brunner return ret; 255023a09873SJohan Hovold } 255106cd6d6eSDavid Rivshin slave_data->phy_node = of_node_get(slave_node); 2552f1eea5c1SDavid Rivshin } else if (parp) { 2553f1eea5c1SDavid Rivshin u32 phyid; 2554f1eea5c1SDavid Rivshin struct device_node *mdio_node; 2555f1eea5c1SDavid Rivshin struct platform_device *mdio; 2556f1eea5c1SDavid Rivshin 2557f1eea5c1SDavid Rivshin if (lenp != (sizeof(__be32) * 2)) { 2558f1eea5c1SDavid Rivshin dev_err(&pdev->dev, "Invalid slave[%d] phy_id property\n", i); 255947276fccSMugunthan V N goto no_phy_slave; 2560549985eeSRichard Cochran } 2561549985eeSRichard Cochran mdio_node = of_find_node_by_phandle(be32_to_cpup(parp)); 2562549985eeSRichard Cochran phyid = be32_to_cpup(parp+1); 2563549985eeSRichard Cochran mdio = of_find_device_by_node(mdio_node); 256460e71ab5SJohan Hovold of_node_put(mdio_node); 25656954cc1fSJohan Hovold if (!mdio) { 256656fdb2e0SMarkus Pargmann dev_err(&pdev->dev, "Missing mdio platform device\n"); 25676954cc1fSJohan Hovold return -EINVAL; 25686954cc1fSJohan Hovold } 2569549985eeSRichard Cochran snprintf(slave_data->phy_id, sizeof(slave_data->phy_id), 2570549985eeSRichard Cochran PHY_ID_FMT, mdio->name, phyid); 257186e1d5adSJohan Hovold put_device(&mdio->dev); 2572f1eea5c1SDavid Rivshin } else { 2573ae092b5bSDavid Rivshin dev_err(&pdev->dev, 2574ae092b5bSDavid Rivshin "No slave[%d] phy_id, phy-handle, or fixed-link property\n", 2575ae092b5bSDavid Rivshin i); 2576f1eea5c1SDavid Rivshin goto no_phy_slave; 2577f1eea5c1SDavid Rivshin } 257847276fccSMugunthan V N slave_data->phy_if = of_get_phy_mode(slave_node); 257947276fccSMugunthan V N if (slave_data->phy_if < 0) { 258047276fccSMugunthan V N dev_err(&pdev->dev, "Missing or malformed slave[%d] phy-mode property\n", 258147276fccSMugunthan V N i); 258247276fccSMugunthan V N return slave_data->phy_if; 258347276fccSMugunthan V N } 258447276fccSMugunthan V N 258547276fccSMugunthan V N no_phy_slave: 2586549985eeSRichard Cochran mac_addr = of_get_mac_address(slave_node); 25870ba517b1SMarkus Pargmann if (mac_addr) { 2588549985eeSRichard Cochran memcpy(slave_data->mac_addr, mac_addr, ETH_ALEN); 25890ba517b1SMarkus Pargmann } else { 2590b6745f6eSMugunthan V N ret = ti_cm_get_macid(&pdev->dev, i, 25910ba517b1SMarkus Pargmann slave_data->mac_addr); 25920ba517b1SMarkus Pargmann if (ret) 25930ba517b1SMarkus Pargmann return ret; 25940ba517b1SMarkus Pargmann } 2595d9ba8f9eSMugunthan V N if (data->dual_emac) { 259691c4166cSMugunthan V N if (of_property_read_u32(slave_node, "dual_emac_res_vlan", 2597d9ba8f9eSMugunthan V N &prop)) { 259888c99ff6SGeorge Cherian dev_err(&pdev->dev, "Missing dual_emac_res_vlan in DT.\n"); 2599d9ba8f9eSMugunthan V N slave_data->dual_emac_res_vlan = i+1; 260088c99ff6SGeorge Cherian dev_err(&pdev->dev, "Using %d as Reserved VLAN for %d slave\n", 2601d9ba8f9eSMugunthan V N slave_data->dual_emac_res_vlan, i); 2602d9ba8f9eSMugunthan V N } else { 2603d9ba8f9eSMugunthan V N slave_data->dual_emac_res_vlan = prop; 2604d9ba8f9eSMugunthan V N } 2605d9ba8f9eSMugunthan V N } 2606d9ba8f9eSMugunthan V N 2607549985eeSRichard Cochran i++; 26083a27bfacSMugunthan V N if (i == data->slaves) 26093a27bfacSMugunthan V N break; 2610549985eeSRichard Cochran } 2611549985eeSRichard Cochran 26122eb32b0aSMugunthan V N return 0; 26132eb32b0aSMugunthan V N } 26142eb32b0aSMugunthan V N 2615a4e32b0dSJohan Hovold static void cpsw_remove_dt(struct platform_device *pdev) 2616a4e32b0dSJohan Hovold { 26178cbcc466SJohan Hovold struct net_device *ndev = platform_get_drvdata(pdev); 26188cbcc466SJohan Hovold struct cpsw_common *cpsw = ndev_to_cpsw(ndev); 26198cbcc466SJohan Hovold struct cpsw_platform_data *data = &cpsw->data; 26208cbcc466SJohan Hovold struct device_node *node = pdev->dev.of_node; 26218cbcc466SJohan Hovold struct device_node *slave_node; 26228cbcc466SJohan Hovold int i = 0; 26238cbcc466SJohan Hovold 26248cbcc466SJohan Hovold for_each_available_child_of_node(node, slave_node) { 26258cbcc466SJohan Hovold struct cpsw_slave_data *slave_data = &data->slave_data[i]; 26268cbcc466SJohan Hovold 26278cbcc466SJohan Hovold if (strcmp(slave_node->name, "slave")) 26288cbcc466SJohan Hovold continue; 26298cbcc466SJohan Hovold 26303f65047cSJohan Hovold if (of_phy_is_fixed_link(slave_node)) 26313f65047cSJohan Hovold of_phy_deregister_fixed_link(slave_node); 26328cbcc466SJohan Hovold 26338cbcc466SJohan Hovold of_node_put(slave_data->phy_node); 26348cbcc466SJohan Hovold 26358cbcc466SJohan Hovold i++; 26368cbcc466SJohan Hovold if (i == data->slaves) 26378cbcc466SJohan Hovold break; 26388cbcc466SJohan Hovold } 26398cbcc466SJohan Hovold 2640a4e32b0dSJohan Hovold of_platform_depopulate(&pdev->dev); 2641a4e32b0dSJohan Hovold } 2642a4e32b0dSJohan Hovold 264356e31bd8SIvan Khoronzhuk static int cpsw_probe_dual_emac(struct cpsw_priv *priv) 2644d9ba8f9eSMugunthan V N { 2645606f3993SIvan Khoronzhuk struct cpsw_common *cpsw = priv->cpsw; 2646606f3993SIvan Khoronzhuk struct cpsw_platform_data *data = &cpsw->data; 2647d9ba8f9eSMugunthan V N struct net_device *ndev; 2648d9ba8f9eSMugunthan V N struct cpsw_priv *priv_sl2; 2649e38b5a3dSIvan Khoronzhuk int ret = 0; 2650d9ba8f9eSMugunthan V N 2651e05107e6SIvan Khoronzhuk ndev = alloc_etherdev_mq(sizeof(struct cpsw_priv), CPSW_MAX_QUEUES); 2652d9ba8f9eSMugunthan V N if (!ndev) { 265356e31bd8SIvan Khoronzhuk dev_err(cpsw->dev, "cpsw: error allocating net_device\n"); 2654d9ba8f9eSMugunthan V N return -ENOMEM; 2655d9ba8f9eSMugunthan V N } 2656d9ba8f9eSMugunthan V N 2657d9ba8f9eSMugunthan V N priv_sl2 = netdev_priv(ndev); 2658606f3993SIvan Khoronzhuk priv_sl2->cpsw = cpsw; 2659d9ba8f9eSMugunthan V N priv_sl2->ndev = ndev; 2660d9ba8f9eSMugunthan V N priv_sl2->dev = &ndev->dev; 2661d9ba8f9eSMugunthan V N priv_sl2->msg_enable = netif_msg_init(debug_level, CPSW_DEBUG); 2662d9ba8f9eSMugunthan V N 2663d9ba8f9eSMugunthan V N if (is_valid_ether_addr(data->slave_data[1].mac_addr)) { 2664d9ba8f9eSMugunthan V N memcpy(priv_sl2->mac_addr, data->slave_data[1].mac_addr, 2665d9ba8f9eSMugunthan V N ETH_ALEN); 266656e31bd8SIvan Khoronzhuk dev_info(cpsw->dev, "cpsw: Detected MACID = %pM\n", 266756e31bd8SIvan Khoronzhuk priv_sl2->mac_addr); 2668d9ba8f9eSMugunthan V N } else { 2669d9ba8f9eSMugunthan V N random_ether_addr(priv_sl2->mac_addr); 267056e31bd8SIvan Khoronzhuk dev_info(cpsw->dev, "cpsw: Random MACID = %pM\n", 267156e31bd8SIvan Khoronzhuk priv_sl2->mac_addr); 2672d9ba8f9eSMugunthan V N } 2673d9ba8f9eSMugunthan V N memcpy(ndev->dev_addr, priv_sl2->mac_addr, ETH_ALEN); 2674d9ba8f9eSMugunthan V N 2675d9ba8f9eSMugunthan V N priv_sl2->emac_port = 1; 2676606f3993SIvan Khoronzhuk cpsw->slaves[1].ndev = ndev; 2677f646968fSPatrick McHardy ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER; 2678d9ba8f9eSMugunthan V N 2679d9ba8f9eSMugunthan V N ndev->netdev_ops = &cpsw_netdev_ops; 26807ad24ea4SWilfried Klaebe ndev->ethtool_ops = &cpsw_ethtool_ops; 2681d9ba8f9eSMugunthan V N 2682d9ba8f9eSMugunthan V N /* register the network device */ 268356e31bd8SIvan Khoronzhuk SET_NETDEV_DEV(ndev, cpsw->dev); 2684d9ba8f9eSMugunthan V N ret = register_netdev(ndev); 2685d9ba8f9eSMugunthan V N if (ret) { 268656e31bd8SIvan Khoronzhuk dev_err(cpsw->dev, "cpsw: error registering net device\n"); 2687d9ba8f9eSMugunthan V N free_netdev(ndev); 2688d9ba8f9eSMugunthan V N ret = -ENODEV; 2689d9ba8f9eSMugunthan V N } 2690d9ba8f9eSMugunthan V N 2691d9ba8f9eSMugunthan V N return ret; 2692d9ba8f9eSMugunthan V N } 2693d9ba8f9eSMugunthan V N 26947da11600SMugunthan V N #define CPSW_QUIRK_IRQ BIT(0) 26957da11600SMugunthan V N 26967da11600SMugunthan V N static struct platform_device_id cpsw_devtype[] = { 26977da11600SMugunthan V N { 26987da11600SMugunthan V N /* keep it for existing comaptibles */ 26997da11600SMugunthan V N .name = "cpsw", 27007da11600SMugunthan V N .driver_data = CPSW_QUIRK_IRQ, 27017da11600SMugunthan V N }, { 27027da11600SMugunthan V N .name = "am335x-cpsw", 27037da11600SMugunthan V N .driver_data = CPSW_QUIRK_IRQ, 27047da11600SMugunthan V N }, { 27057da11600SMugunthan V N .name = "am4372-cpsw", 27067da11600SMugunthan V N .driver_data = 0, 27077da11600SMugunthan V N }, { 27087da11600SMugunthan V N .name = "dra7-cpsw", 27097da11600SMugunthan V N .driver_data = 0, 27107da11600SMugunthan V N }, { 27117da11600SMugunthan V N /* sentinel */ 27127da11600SMugunthan V N } 27137da11600SMugunthan V N }; 27147da11600SMugunthan V N MODULE_DEVICE_TABLE(platform, cpsw_devtype); 27157da11600SMugunthan V N 27167da11600SMugunthan V N enum ti_cpsw_type { 27177da11600SMugunthan V N CPSW = 0, 27187da11600SMugunthan V N AM335X_CPSW, 27197da11600SMugunthan V N AM4372_CPSW, 27207da11600SMugunthan V N DRA7_CPSW, 27217da11600SMugunthan V N }; 27227da11600SMugunthan V N 27237da11600SMugunthan V N static const struct of_device_id cpsw_of_mtable[] = { 27247da11600SMugunthan V N { .compatible = "ti,cpsw", .data = &cpsw_devtype[CPSW], }, 27257da11600SMugunthan V N { .compatible = "ti,am335x-cpsw", .data = &cpsw_devtype[AM335X_CPSW], }, 27267da11600SMugunthan V N { .compatible = "ti,am4372-cpsw", .data = &cpsw_devtype[AM4372_CPSW], }, 27277da11600SMugunthan V N { .compatible = "ti,dra7-cpsw", .data = &cpsw_devtype[DRA7_CPSW], }, 27287da11600SMugunthan V N { /* sentinel */ }, 27297da11600SMugunthan V N }; 27307da11600SMugunthan V N MODULE_DEVICE_TABLE(of, cpsw_of_mtable); 27317da11600SMugunthan V N 2732663e12e6SBill Pemberton static int cpsw_probe(struct platform_device *pdev) 2733df828598SMugunthan V N { 2734ef4183a1SIvan Khoronzhuk struct clk *clk; 2735d1bd9acfSSebastian Siewior struct cpsw_platform_data *data; 2736df828598SMugunthan V N struct net_device *ndev; 2737df828598SMugunthan V N struct cpsw_priv *priv; 2738df828598SMugunthan V N struct cpdma_params dma_params; 2739df828598SMugunthan V N struct cpsw_ale_params ale_params; 2740aa1a15e2SDaniel Mack void __iomem *ss_regs; 27418a2c9a5aSGrygorii Strashko void __iomem *cpts_regs; 2742aa1a15e2SDaniel Mack struct resource *res, *ss_res; 27437da11600SMugunthan V N const struct of_device_id *of_id; 27441d147ccbSMugunthan V N struct gpio_descs *mode; 2745549985eeSRichard Cochran u32 slave_offset, sliver_offset, slave_size; 2746649a1688SIvan Khoronzhuk struct cpsw_common *cpsw; 27475087b915SFelipe Balbi int ret = 0, i; 27485087b915SFelipe Balbi int irq; 2749df828598SMugunthan V N 2750649a1688SIvan Khoronzhuk cpsw = devm_kzalloc(&pdev->dev, sizeof(struct cpsw_common), GFP_KERNEL); 27513420ea88SJohan Hovold if (!cpsw) 27523420ea88SJohan Hovold return -ENOMEM; 27533420ea88SJohan Hovold 275456e31bd8SIvan Khoronzhuk cpsw->dev = &pdev->dev; 2755649a1688SIvan Khoronzhuk 2756e05107e6SIvan Khoronzhuk ndev = alloc_etherdev_mq(sizeof(struct cpsw_priv), CPSW_MAX_QUEUES); 2757df828598SMugunthan V N if (!ndev) { 275888c99ff6SGeorge Cherian dev_err(&pdev->dev, "error allocating net_device\n"); 2759df828598SMugunthan V N return -ENOMEM; 2760df828598SMugunthan V N } 2761df828598SMugunthan V N 2762df828598SMugunthan V N platform_set_drvdata(pdev, ndev); 2763df828598SMugunthan V N priv = netdev_priv(ndev); 2764649a1688SIvan Khoronzhuk priv->cpsw = cpsw; 2765df828598SMugunthan V N priv->ndev = ndev; 2766df828598SMugunthan V N priv->dev = &ndev->dev; 2767df828598SMugunthan V N priv->msg_enable = netif_msg_init(debug_level, CPSW_DEBUG); 27682a05a622SIvan Khoronzhuk cpsw->rx_packet_max = max(rx_packet_max, 128); 2769df828598SMugunthan V N 27701d147ccbSMugunthan V N mode = devm_gpiod_get_array_optional(&pdev->dev, "mode", GPIOD_OUT_LOW); 27711d147ccbSMugunthan V N if (IS_ERR(mode)) { 27721d147ccbSMugunthan V N ret = PTR_ERR(mode); 27731d147ccbSMugunthan V N dev_err(&pdev->dev, "gpio request failed, ret %d\n", ret); 27741d147ccbSMugunthan V N goto clean_ndev_ret; 27751d147ccbSMugunthan V N } 27761d147ccbSMugunthan V N 27771fb19aa7SVaibhav Hiremath /* 27781fb19aa7SVaibhav Hiremath * This may be required here for child devices. 27791fb19aa7SVaibhav Hiremath */ 27801fb19aa7SVaibhav Hiremath pm_runtime_enable(&pdev->dev); 27811fb19aa7SVaibhav Hiremath 2782739683b4SMugunthan V N /* Select default pin state */ 2783739683b4SMugunthan V N pinctrl_pm_select_default_state(&pdev->dev); 2784739683b4SMugunthan V N 2785a4e32b0dSJohan Hovold /* Need to enable clocks with runtime PM api to access module 2786a4e32b0dSJohan Hovold * registers 2787a4e32b0dSJohan Hovold */ 2788a4e32b0dSJohan Hovold ret = pm_runtime_get_sync(&pdev->dev); 2789a4e32b0dSJohan Hovold if (ret < 0) { 2790a4e32b0dSJohan Hovold pm_runtime_put_noidle(&pdev->dev); 2791aa1a15e2SDaniel Mack goto clean_runtime_disable_ret; 27922eb32b0aSMugunthan V N } 2793a4e32b0dSJohan Hovold 279423a09873SJohan Hovold ret = cpsw_probe_dt(&cpsw->data, pdev); 279523a09873SJohan Hovold if (ret) 2796a4e32b0dSJohan Hovold goto clean_dt_ret; 279723a09873SJohan Hovold 2798606f3993SIvan Khoronzhuk data = &cpsw->data; 2799e05107e6SIvan Khoronzhuk cpsw->rx_ch_num = 1; 2800e05107e6SIvan Khoronzhuk cpsw->tx_ch_num = 1; 28012eb32b0aSMugunthan V N 2802df828598SMugunthan V N if (is_valid_ether_addr(data->slave_data[0].mac_addr)) { 2803df828598SMugunthan V N memcpy(priv->mac_addr, data->slave_data[0].mac_addr, ETH_ALEN); 280488c99ff6SGeorge Cherian dev_info(&pdev->dev, "Detected MACID = %pM\n", priv->mac_addr); 2805df828598SMugunthan V N } else { 28067efd26d0SJoe Perches eth_random_addr(priv->mac_addr); 280788c99ff6SGeorge Cherian dev_info(&pdev->dev, "Random MACID = %pM\n", priv->mac_addr); 2808df828598SMugunthan V N } 2809df828598SMugunthan V N 2810df828598SMugunthan V N memcpy(ndev->dev_addr, priv->mac_addr, ETH_ALEN); 2811df828598SMugunthan V N 2812606f3993SIvan Khoronzhuk cpsw->slaves = devm_kzalloc(&pdev->dev, 2813aa1a15e2SDaniel Mack sizeof(struct cpsw_slave) * data->slaves, 2814df828598SMugunthan V N GFP_KERNEL); 2815606f3993SIvan Khoronzhuk if (!cpsw->slaves) { 2816aa1a15e2SDaniel Mack ret = -ENOMEM; 2817a4e32b0dSJohan Hovold goto clean_dt_ret; 2818df828598SMugunthan V N } 2819df828598SMugunthan V N for (i = 0; i < data->slaves; i++) 2820606f3993SIvan Khoronzhuk cpsw->slaves[i].slave_num = i; 2821df828598SMugunthan V N 2822606f3993SIvan Khoronzhuk cpsw->slaves[0].ndev = ndev; 2823d9ba8f9eSMugunthan V N priv->emac_port = 0; 2824d9ba8f9eSMugunthan V N 2825ef4183a1SIvan Khoronzhuk clk = devm_clk_get(&pdev->dev, "fck"); 2826ef4183a1SIvan Khoronzhuk if (IS_ERR(clk)) { 2827aa1a15e2SDaniel Mack dev_err(priv->dev, "fck is not found\n"); 2828f150bd7fSMugunthan V N ret = -ENODEV; 2829a4e32b0dSJohan Hovold goto clean_dt_ret; 2830df828598SMugunthan V N } 28312a05a622SIvan Khoronzhuk cpsw->bus_freq_mhz = clk_get_rate(clk) / 1000000; 2832df828598SMugunthan V N 2833aa1a15e2SDaniel Mack ss_res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2834aa1a15e2SDaniel Mack ss_regs = devm_ioremap_resource(&pdev->dev, ss_res); 2835aa1a15e2SDaniel Mack if (IS_ERR(ss_regs)) { 2836aa1a15e2SDaniel Mack ret = PTR_ERR(ss_regs); 2837a4e32b0dSJohan Hovold goto clean_dt_ret; 2838df828598SMugunthan V N } 28395d8d0d4dSIvan Khoronzhuk cpsw->regs = ss_regs; 2840df828598SMugunthan V N 28412a05a622SIvan Khoronzhuk cpsw->version = readl(&cpsw->regs->id_ver); 2842f280e89aSMugunthan V N 2843aa1a15e2SDaniel Mack res = platform_get_resource(pdev, IORESOURCE_MEM, 1); 28445d8d0d4dSIvan Khoronzhuk cpsw->wr_regs = devm_ioremap_resource(&pdev->dev, res); 28455d8d0d4dSIvan Khoronzhuk if (IS_ERR(cpsw->wr_regs)) { 28465d8d0d4dSIvan Khoronzhuk ret = PTR_ERR(cpsw->wr_regs); 2847a4e32b0dSJohan Hovold goto clean_dt_ret; 2848df828598SMugunthan V N } 2849df828598SMugunthan V N 2850df828598SMugunthan V N memset(&dma_params, 0, sizeof(dma_params)); 2851549985eeSRichard Cochran memset(&ale_params, 0, sizeof(ale_params)); 2852549985eeSRichard Cochran 28532a05a622SIvan Khoronzhuk switch (cpsw->version) { 2854549985eeSRichard Cochran case CPSW_VERSION_1: 28555d8d0d4dSIvan Khoronzhuk cpsw->host_port_regs = ss_regs + CPSW1_HOST_PORT_OFFSET; 28568a2c9a5aSGrygorii Strashko cpts_regs = ss_regs + CPSW1_CPTS_OFFSET; 28575d8d0d4dSIvan Khoronzhuk cpsw->hw_stats = ss_regs + CPSW1_HW_STATS; 2858549985eeSRichard Cochran dma_params.dmaregs = ss_regs + CPSW1_CPDMA_OFFSET; 2859549985eeSRichard Cochran dma_params.txhdp = ss_regs + CPSW1_STATERAM_OFFSET; 2860549985eeSRichard Cochran ale_params.ale_regs = ss_regs + CPSW1_ALE_OFFSET; 2861549985eeSRichard Cochran slave_offset = CPSW1_SLAVE_OFFSET; 2862549985eeSRichard Cochran slave_size = CPSW1_SLAVE_SIZE; 2863549985eeSRichard Cochran sliver_offset = CPSW1_SLIVER_OFFSET; 2864549985eeSRichard Cochran dma_params.desc_mem_phys = 0; 2865549985eeSRichard Cochran break; 2866549985eeSRichard Cochran case CPSW_VERSION_2: 2867c193f365SMugunthan V N case CPSW_VERSION_3: 2868926489beSMugunthan V N case CPSW_VERSION_4: 28695d8d0d4dSIvan Khoronzhuk cpsw->host_port_regs = ss_regs + CPSW2_HOST_PORT_OFFSET; 28708a2c9a5aSGrygorii Strashko cpts_regs = ss_regs + CPSW2_CPTS_OFFSET; 28715d8d0d4dSIvan Khoronzhuk cpsw->hw_stats = ss_regs + CPSW2_HW_STATS; 2872549985eeSRichard Cochran dma_params.dmaregs = ss_regs + CPSW2_CPDMA_OFFSET; 2873549985eeSRichard Cochran dma_params.txhdp = ss_regs + CPSW2_STATERAM_OFFSET; 2874549985eeSRichard Cochran ale_params.ale_regs = ss_regs + CPSW2_ALE_OFFSET; 2875549985eeSRichard Cochran slave_offset = CPSW2_SLAVE_OFFSET; 2876549985eeSRichard Cochran slave_size = CPSW2_SLAVE_SIZE; 2877549985eeSRichard Cochran sliver_offset = CPSW2_SLIVER_OFFSET; 2878549985eeSRichard Cochran dma_params.desc_mem_phys = 2879aa1a15e2SDaniel Mack (u32 __force) ss_res->start + CPSW2_BD_OFFSET; 2880549985eeSRichard Cochran break; 2881549985eeSRichard Cochran default: 28822a05a622SIvan Khoronzhuk dev_err(priv->dev, "unknown version 0x%08x\n", cpsw->version); 2883549985eeSRichard Cochran ret = -ENODEV; 2884a4e32b0dSJohan Hovold goto clean_dt_ret; 2885549985eeSRichard Cochran } 2886606f3993SIvan Khoronzhuk for (i = 0; i < cpsw->data.slaves; i++) { 2887606f3993SIvan Khoronzhuk struct cpsw_slave *slave = &cpsw->slaves[i]; 2888606f3993SIvan Khoronzhuk 2889606f3993SIvan Khoronzhuk cpsw_slave_init(slave, cpsw, slave_offset, sliver_offset); 2890549985eeSRichard Cochran slave_offset += slave_size; 2891549985eeSRichard Cochran sliver_offset += SLIVER_SIZE; 2892549985eeSRichard Cochran } 2893549985eeSRichard Cochran 2894df828598SMugunthan V N dma_params.dev = &pdev->dev; 2895549985eeSRichard Cochran dma_params.rxthresh = dma_params.dmaregs + CPDMA_RXTHRESH; 2896549985eeSRichard Cochran dma_params.rxfree = dma_params.dmaregs + CPDMA_RXFREE; 2897549985eeSRichard Cochran dma_params.rxhdp = dma_params.txhdp + CPDMA_RXHDP; 2898549985eeSRichard Cochran dma_params.txcp = dma_params.txhdp + CPDMA_TXCP; 2899549985eeSRichard Cochran dma_params.rxcp = dma_params.txhdp + CPDMA_RXCP; 2900df828598SMugunthan V N 2901df828598SMugunthan V N dma_params.num_chan = data->channels; 2902df828598SMugunthan V N dma_params.has_soft_reset = true; 2903df828598SMugunthan V N dma_params.min_packet_size = CPSW_MIN_PACKET_SIZE; 2904df828598SMugunthan V N dma_params.desc_mem_size = data->bd_ram_size; 2905df828598SMugunthan V N dma_params.desc_align = 16; 2906df828598SMugunthan V N dma_params.has_ext_regs = true; 2907549985eeSRichard Cochran dma_params.desc_hw_addr = dma_params.desc_mem_phys; 290883fcad0cSIvan Khoronzhuk dma_params.bus_freq_mhz = cpsw->bus_freq_mhz; 2909df828598SMugunthan V N 29102c836bd9SIvan Khoronzhuk cpsw->dma = cpdma_ctlr_create(&dma_params); 29112c836bd9SIvan Khoronzhuk if (!cpsw->dma) { 2912df828598SMugunthan V N dev_err(priv->dev, "error initializing dma\n"); 2913df828598SMugunthan V N ret = -ENOMEM; 2914a4e32b0dSJohan Hovold goto clean_dt_ret; 2915df828598SMugunthan V N } 2916df828598SMugunthan V N 29178feb0a19SIvan Khoronzhuk cpsw->txv[0].ch = cpdma_chan_create(cpsw->dma, 0, cpsw_tx_handler, 0); 29188feb0a19SIvan Khoronzhuk cpsw->rxv[0].ch = cpdma_chan_create(cpsw->dma, 0, cpsw_rx_handler, 1); 29198feb0a19SIvan Khoronzhuk if (WARN_ON(!cpsw->rxv[0].ch || !cpsw->txv[0].ch)) { 2920df828598SMugunthan V N dev_err(priv->dev, "error initializing dma channels\n"); 2921df828598SMugunthan V N ret = -ENOMEM; 2922df828598SMugunthan V N goto clean_dma_ret; 2923df828598SMugunthan V N } 2924df828598SMugunthan V N 2925df828598SMugunthan V N ale_params.dev = &ndev->dev; 2926df828598SMugunthan V N ale_params.ale_ageout = ale_ageout; 2927df828598SMugunthan V N ale_params.ale_entries = data->ale_entries; 2928df828598SMugunthan V N ale_params.ale_ports = data->slaves; 2929df828598SMugunthan V N 29302a05a622SIvan Khoronzhuk cpsw->ale = cpsw_ale_create(&ale_params); 29312a05a622SIvan Khoronzhuk if (!cpsw->ale) { 2932df828598SMugunthan V N dev_err(priv->dev, "error initializing ale engine\n"); 2933df828598SMugunthan V N ret = -ENODEV; 2934df828598SMugunthan V N goto clean_dma_ret; 2935df828598SMugunthan V N } 2936df828598SMugunthan V N 29374a88fb95SGrygorii Strashko cpsw->cpts = cpts_create(cpsw->dev, cpts_regs, cpsw->dev->of_node); 29388a2c9a5aSGrygorii Strashko if (IS_ERR(cpsw->cpts)) { 29398a2c9a5aSGrygorii Strashko ret = PTR_ERR(cpsw->cpts); 29408a2c9a5aSGrygorii Strashko goto clean_ale_ret; 29418a2c9a5aSGrygorii Strashko } 29428a2c9a5aSGrygorii Strashko 2943c03abd84SFelipe Balbi ndev->irq = platform_get_irq(pdev, 1); 2944df828598SMugunthan V N if (ndev->irq < 0) { 2945df828598SMugunthan V N dev_err(priv->dev, "error getting irq resource\n"); 2946c1e3334fSJulia Lawall ret = ndev->irq; 2947df828598SMugunthan V N goto clean_ale_ret; 2948df828598SMugunthan V N } 2949df828598SMugunthan V N 29507da11600SMugunthan V N of_id = of_match_device(cpsw_of_mtable, &pdev->dev); 29517da11600SMugunthan V N if (of_id) { 29527da11600SMugunthan V N pdev->id_entry = of_id->data; 29537da11600SMugunthan V N if (pdev->id_entry->driver_data) 2954e38b5a3dSIvan Khoronzhuk cpsw->quirk_irq = true; 29557da11600SMugunthan V N } 29567da11600SMugunthan V N 2957c03abd84SFelipe Balbi /* Grab RX and TX IRQs. Note that we also have RX_THRESHOLD and 2958c03abd84SFelipe Balbi * MISC IRQs which are always kept disabled with this driver so 2959c03abd84SFelipe Balbi * we will not request them. 2960c03abd84SFelipe Balbi * 2961c03abd84SFelipe Balbi * If anyone wants to implement support for those, make sure to 2962c03abd84SFelipe Balbi * first request and append them to irqs_table array. 2963c03abd84SFelipe Balbi */ 2964c2b32e58SDaniel Mack 2965c03abd84SFelipe Balbi /* RX IRQ */ 29665087b915SFelipe Balbi irq = platform_get_irq(pdev, 1); 2967c1e3334fSJulia Lawall if (irq < 0) { 2968c1e3334fSJulia Lawall ret = irq; 29695087b915SFelipe Balbi goto clean_ale_ret; 2970c1e3334fSJulia Lawall } 29715087b915SFelipe Balbi 2972e38b5a3dSIvan Khoronzhuk cpsw->irqs_table[0] = irq; 2973c03abd84SFelipe Balbi ret = devm_request_irq(&pdev->dev, irq, cpsw_rx_interrupt, 2974dbc4ec52SIvan Khoronzhuk 0, dev_name(&pdev->dev), cpsw); 29755087b915SFelipe Balbi if (ret < 0) { 29765087b915SFelipe Balbi dev_err(priv->dev, "error attaching irq (%d)\n", ret); 29775087b915SFelipe Balbi goto clean_ale_ret; 2978df828598SMugunthan V N } 2979df828598SMugunthan V N 2980c03abd84SFelipe Balbi /* TX IRQ */ 29815087b915SFelipe Balbi irq = platform_get_irq(pdev, 2); 2982c1e3334fSJulia Lawall if (irq < 0) { 2983c1e3334fSJulia Lawall ret = irq; 29845087b915SFelipe Balbi goto clean_ale_ret; 2985c1e3334fSJulia Lawall } 29865087b915SFelipe Balbi 2987e38b5a3dSIvan Khoronzhuk cpsw->irqs_table[1] = irq; 2988c03abd84SFelipe Balbi ret = devm_request_irq(&pdev->dev, irq, cpsw_tx_interrupt, 2989dbc4ec52SIvan Khoronzhuk 0, dev_name(&pdev->dev), cpsw); 29905087b915SFelipe Balbi if (ret < 0) { 29915087b915SFelipe Balbi dev_err(priv->dev, "error attaching irq (%d)\n", ret); 29925087b915SFelipe Balbi goto clean_ale_ret; 29935087b915SFelipe Balbi } 2994c2b32e58SDaniel Mack 2995f646968fSPatrick McHardy ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER; 2996df828598SMugunthan V N 2997df828598SMugunthan V N ndev->netdev_ops = &cpsw_netdev_ops; 29987ad24ea4SWilfried Klaebe ndev->ethtool_ops = &cpsw_ethtool_ops; 2999dbc4ec52SIvan Khoronzhuk netif_napi_add(ndev, &cpsw->napi_rx, cpsw_rx_poll, CPSW_POLL_WEIGHT); 3000dbc4ec52SIvan Khoronzhuk netif_tx_napi_add(ndev, &cpsw->napi_tx, cpsw_tx_poll, CPSW_POLL_WEIGHT); 3001df828598SMugunthan V N 3002df828598SMugunthan V N /* register the network device */ 3003df828598SMugunthan V N SET_NETDEV_DEV(ndev, &pdev->dev); 3004df828598SMugunthan V N ret = register_netdev(ndev); 3005df828598SMugunthan V N if (ret) { 3006df828598SMugunthan V N dev_err(priv->dev, "error registering net device\n"); 3007df828598SMugunthan V N ret = -ENODEV; 3008aa1a15e2SDaniel Mack goto clean_ale_ret; 3009df828598SMugunthan V N } 3010df828598SMugunthan V N 30111a3b5056SOlof Johansson cpsw_notice(priv, probe, "initialized device (regs %pa, irq %d)\n", 30121a3b5056SOlof Johansson &ss_res->start, ndev->irq); 3013df828598SMugunthan V N 3014606f3993SIvan Khoronzhuk if (cpsw->data.dual_emac) { 301556e31bd8SIvan Khoronzhuk ret = cpsw_probe_dual_emac(priv); 3016d9ba8f9eSMugunthan V N if (ret) { 3017d9ba8f9eSMugunthan V N cpsw_err(priv, probe, "error probe slave 2 emac interface\n"); 3018a7fe9d46SJohan Hovold goto clean_unregister_netdev_ret; 3019d9ba8f9eSMugunthan V N } 3020d9ba8f9eSMugunthan V N } 3021d9ba8f9eSMugunthan V N 3022c46ab7e0SJohan Hovold pm_runtime_put(&pdev->dev); 3023c46ab7e0SJohan Hovold 3024df828598SMugunthan V N return 0; 3025df828598SMugunthan V N 3026a7fe9d46SJohan Hovold clean_unregister_netdev_ret: 3027a7fe9d46SJohan Hovold unregister_netdev(ndev); 3028df828598SMugunthan V N clean_ale_ret: 30292a05a622SIvan Khoronzhuk cpsw_ale_destroy(cpsw->ale); 3030df828598SMugunthan V N clean_dma_ret: 30312c836bd9SIvan Khoronzhuk cpdma_ctlr_destroy(cpsw->dma); 3032a4e32b0dSJohan Hovold clean_dt_ret: 3033a4e32b0dSJohan Hovold cpsw_remove_dt(pdev); 3034c46ab7e0SJohan Hovold pm_runtime_put_sync(&pdev->dev); 3035aa1a15e2SDaniel Mack clean_runtime_disable_ret: 3036f150bd7fSMugunthan V N pm_runtime_disable(&pdev->dev); 3037df828598SMugunthan V N clean_ndev_ret: 3038d1bd9acfSSebastian Siewior free_netdev(priv->ndev); 3039df828598SMugunthan V N return ret; 3040df828598SMugunthan V N } 3041df828598SMugunthan V N 3042663e12e6SBill Pemberton static int cpsw_remove(struct platform_device *pdev) 3043df828598SMugunthan V N { 3044df828598SMugunthan V N struct net_device *ndev = platform_get_drvdata(pdev); 30452a05a622SIvan Khoronzhuk struct cpsw_common *cpsw = ndev_to_cpsw(ndev); 30468a0b6dc9SGrygorii Strashko int ret; 30478a0b6dc9SGrygorii Strashko 30488a0b6dc9SGrygorii Strashko ret = pm_runtime_get_sync(&pdev->dev); 30498a0b6dc9SGrygorii Strashko if (ret < 0) { 30508a0b6dc9SGrygorii Strashko pm_runtime_put_noidle(&pdev->dev); 30518a0b6dc9SGrygorii Strashko return ret; 30528a0b6dc9SGrygorii Strashko } 3053df828598SMugunthan V N 3054606f3993SIvan Khoronzhuk if (cpsw->data.dual_emac) 3055606f3993SIvan Khoronzhuk unregister_netdev(cpsw->slaves[1].ndev); 3056d1bd9acfSSebastian Siewior unregister_netdev(ndev); 3057df828598SMugunthan V N 30588a2c9a5aSGrygorii Strashko cpts_release(cpsw->cpts); 30592a05a622SIvan Khoronzhuk cpsw_ale_destroy(cpsw->ale); 30602c836bd9SIvan Khoronzhuk cpdma_ctlr_destroy(cpsw->dma); 3061a4e32b0dSJohan Hovold cpsw_remove_dt(pdev); 30628a0b6dc9SGrygorii Strashko pm_runtime_put_sync(&pdev->dev); 30638a0b6dc9SGrygorii Strashko pm_runtime_disable(&pdev->dev); 3064606f3993SIvan Khoronzhuk if (cpsw->data.dual_emac) 3065606f3993SIvan Khoronzhuk free_netdev(cpsw->slaves[1].ndev); 3066df828598SMugunthan V N free_netdev(ndev); 3067df828598SMugunthan V N return 0; 3068df828598SMugunthan V N } 3069df828598SMugunthan V N 30708963a504SGrygorii Strashko #ifdef CONFIG_PM_SLEEP 3071df828598SMugunthan V N static int cpsw_suspend(struct device *dev) 3072df828598SMugunthan V N { 3073df828598SMugunthan V N struct platform_device *pdev = to_platform_device(dev); 3074df828598SMugunthan V N struct net_device *ndev = platform_get_drvdata(pdev); 3075606f3993SIvan Khoronzhuk struct cpsw_common *cpsw = ndev_to_cpsw(ndev); 3076df828598SMugunthan V N 3077606f3993SIvan Khoronzhuk if (cpsw->data.dual_emac) { 3078618073e3SMugunthan V N int i; 3079618073e3SMugunthan V N 3080606f3993SIvan Khoronzhuk for (i = 0; i < cpsw->data.slaves; i++) { 3081606f3993SIvan Khoronzhuk if (netif_running(cpsw->slaves[i].ndev)) 3082606f3993SIvan Khoronzhuk cpsw_ndo_stop(cpsw->slaves[i].ndev); 3083618073e3SMugunthan V N } 3084618073e3SMugunthan V N } else { 3085df828598SMugunthan V N if (netif_running(ndev)) 3086df828598SMugunthan V N cpsw_ndo_stop(ndev); 3087618073e3SMugunthan V N } 30881e7a2e21SDaniel Mack 3089739683b4SMugunthan V N /* Select sleep pin state */ 309056e31bd8SIvan Khoronzhuk pinctrl_pm_select_sleep_state(dev); 3091739683b4SMugunthan V N 3092df828598SMugunthan V N return 0; 3093df828598SMugunthan V N } 3094df828598SMugunthan V N 3095df828598SMugunthan V N static int cpsw_resume(struct device *dev) 3096df828598SMugunthan V N { 3097df828598SMugunthan V N struct platform_device *pdev = to_platform_device(dev); 3098df828598SMugunthan V N struct net_device *ndev = platform_get_drvdata(pdev); 3099606f3993SIvan Khoronzhuk struct cpsw_common *cpsw = netdev_priv(ndev); 3100df828598SMugunthan V N 3101739683b4SMugunthan V N /* Select default pin state */ 310256e31bd8SIvan Khoronzhuk pinctrl_pm_select_default_state(dev); 3103739683b4SMugunthan V N 31044ccfd638SGrygorii Strashko /* shut up ASSERT_RTNL() warning in netif_set_real_num_tx/rx_queues */ 31054ccfd638SGrygorii Strashko rtnl_lock(); 3106606f3993SIvan Khoronzhuk if (cpsw->data.dual_emac) { 3107618073e3SMugunthan V N int i; 3108618073e3SMugunthan V N 3109606f3993SIvan Khoronzhuk for (i = 0; i < cpsw->data.slaves; i++) { 3110606f3993SIvan Khoronzhuk if (netif_running(cpsw->slaves[i].ndev)) 3111606f3993SIvan Khoronzhuk cpsw_ndo_open(cpsw->slaves[i].ndev); 3112618073e3SMugunthan V N } 3113618073e3SMugunthan V N } else { 3114df828598SMugunthan V N if (netif_running(ndev)) 3115df828598SMugunthan V N cpsw_ndo_open(ndev); 3116618073e3SMugunthan V N } 31174ccfd638SGrygorii Strashko rtnl_unlock(); 31184ccfd638SGrygorii Strashko 3119df828598SMugunthan V N return 0; 3120df828598SMugunthan V N } 31218963a504SGrygorii Strashko #endif 3122df828598SMugunthan V N 31238963a504SGrygorii Strashko static SIMPLE_DEV_PM_OPS(cpsw_pm_ops, cpsw_suspend, cpsw_resume); 3124df828598SMugunthan V N 3125df828598SMugunthan V N static struct platform_driver cpsw_driver = { 3126df828598SMugunthan V N .driver = { 3127df828598SMugunthan V N .name = "cpsw", 3128df828598SMugunthan V N .pm = &cpsw_pm_ops, 31291e5c76d4SSachin Kamat .of_match_table = cpsw_of_mtable, 3130df828598SMugunthan V N }, 3131df828598SMugunthan V N .probe = cpsw_probe, 3132663e12e6SBill Pemberton .remove = cpsw_remove, 3133df828598SMugunthan V N }; 3134df828598SMugunthan V N 31356fb3b6b5SGrygorii Strashko module_platform_driver(cpsw_driver); 3136df828598SMugunthan V N 3137df828598SMugunthan V N MODULE_LICENSE("GPL"); 3138df828598SMugunthan V N MODULE_AUTHOR("Cyril Chemparathy <cyril@ti.com>"); 3139df828598SMugunthan V N MODULE_AUTHOR("Mugunthan V N <mugunthanvnm@ti.com>"); 3140df828598SMugunthan V N MODULE_DESCRIPTION("TI CPSW Ethernet driver"); 3141