1df828598SMugunthan V N /* 2df828598SMugunthan V N * Texas Instruments Ethernet Switch Driver 3df828598SMugunthan V N * 4df828598SMugunthan V N * Copyright (C) 2012 Texas Instruments 5df828598SMugunthan V N * 6df828598SMugunthan V N * This program is free software; you can redistribute it and/or 7df828598SMugunthan V N * modify it under the terms of the GNU General Public License as 8df828598SMugunthan V N * published by the Free Software Foundation version 2. 9df828598SMugunthan V N * 10df828598SMugunthan V N * This program is distributed "as is" WITHOUT ANY WARRANTY of any 11df828598SMugunthan V N * kind, whether express or implied; without even the implied warranty 12df828598SMugunthan V N * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13df828598SMugunthan V N * GNU General Public License for more details. 14df828598SMugunthan V N */ 15df828598SMugunthan V N 16df828598SMugunthan V N #include <linux/kernel.h> 17df828598SMugunthan V N #include <linux/io.h> 18df828598SMugunthan V N #include <linux/clk.h> 19df828598SMugunthan V N #include <linux/timer.h> 20df828598SMugunthan V N #include <linux/module.h> 21df828598SMugunthan V N #include <linux/platform_device.h> 22df828598SMugunthan V N #include <linux/irqreturn.h> 23df828598SMugunthan V N #include <linux/interrupt.h> 24df828598SMugunthan V N #include <linux/if_ether.h> 25df828598SMugunthan V N #include <linux/etherdevice.h> 26df828598SMugunthan V N #include <linux/netdevice.h> 272e5b38abSRichard Cochran #include <linux/net_tstamp.h> 28df828598SMugunthan V N #include <linux/phy.h> 29df828598SMugunthan V N #include <linux/workqueue.h> 30df828598SMugunthan V N #include <linux/delay.h> 31f150bd7fSMugunthan V N #include <linux/pm_runtime.h> 322eb32b0aSMugunthan V N #include <linux/of.h> 332eb32b0aSMugunthan V N #include <linux/of_net.h> 342eb32b0aSMugunthan V N #include <linux/of_device.h> 35df828598SMugunthan V N 36df828598SMugunthan V N #include <linux/platform_data/cpsw.h> 37df828598SMugunthan V N 38df828598SMugunthan V N #include "cpsw_ale.h" 392e5b38abSRichard Cochran #include "cpts.h" 40df828598SMugunthan V N #include "davinci_cpdma.h" 41df828598SMugunthan V N 42df828598SMugunthan V N #define CPSW_DEBUG (NETIF_MSG_HW | NETIF_MSG_WOL | \ 43df828598SMugunthan V N NETIF_MSG_DRV | NETIF_MSG_LINK | \ 44df828598SMugunthan V N NETIF_MSG_IFUP | NETIF_MSG_INTR | \ 45df828598SMugunthan V N NETIF_MSG_PROBE | NETIF_MSG_TIMER | \ 46df828598SMugunthan V N NETIF_MSG_IFDOWN | NETIF_MSG_RX_ERR | \ 47df828598SMugunthan V N NETIF_MSG_TX_ERR | NETIF_MSG_TX_DONE | \ 48df828598SMugunthan V N NETIF_MSG_PKTDATA | NETIF_MSG_TX_QUEUED | \ 49df828598SMugunthan V N NETIF_MSG_RX_STATUS) 50df828598SMugunthan V N 51df828598SMugunthan V N #define cpsw_info(priv, type, format, ...) \ 52df828598SMugunthan V N do { \ 53df828598SMugunthan V N if (netif_msg_##type(priv) && net_ratelimit()) \ 54df828598SMugunthan V N dev_info(priv->dev, format, ## __VA_ARGS__); \ 55df828598SMugunthan V N } while (0) 56df828598SMugunthan V N 57df828598SMugunthan V N #define cpsw_err(priv, type, format, ...) \ 58df828598SMugunthan V N do { \ 59df828598SMugunthan V N if (netif_msg_##type(priv) && net_ratelimit()) \ 60df828598SMugunthan V N dev_err(priv->dev, format, ## __VA_ARGS__); \ 61df828598SMugunthan V N } while (0) 62df828598SMugunthan V N 63df828598SMugunthan V N #define cpsw_dbg(priv, type, format, ...) \ 64df828598SMugunthan V N do { \ 65df828598SMugunthan V N if (netif_msg_##type(priv) && net_ratelimit()) \ 66df828598SMugunthan V N dev_dbg(priv->dev, format, ## __VA_ARGS__); \ 67df828598SMugunthan V N } while (0) 68df828598SMugunthan V N 69df828598SMugunthan V N #define cpsw_notice(priv, type, format, ...) \ 70df828598SMugunthan V N do { \ 71df828598SMugunthan V N if (netif_msg_##type(priv) && net_ratelimit()) \ 72df828598SMugunthan V N dev_notice(priv->dev, format, ## __VA_ARGS__); \ 73df828598SMugunthan V N } while (0) 74df828598SMugunthan V N 755c50a856SMugunthan V N #define ALE_ALL_PORTS 0x7 765c50a856SMugunthan V N 77df828598SMugunthan V N #define CPSW_MAJOR_VERSION(reg) (reg >> 8 & 0x7) 78df828598SMugunthan V N #define CPSW_MINOR_VERSION(reg) (reg & 0xff) 79df828598SMugunthan V N #define CPSW_RTL_VERSION(reg) ((reg >> 11) & 0x1f) 80df828598SMugunthan V N 81e90cfac6SRichard Cochran #define CPSW_VERSION_1 0x19010a 82e90cfac6SRichard Cochran #define CPSW_VERSION_2 0x19010c 83549985eeSRichard Cochran 84549985eeSRichard Cochran #define HOST_PORT_NUM 0 85549985eeSRichard Cochran #define SLIVER_SIZE 0x40 86549985eeSRichard Cochran 87549985eeSRichard Cochran #define CPSW1_HOST_PORT_OFFSET 0x028 88549985eeSRichard Cochran #define CPSW1_SLAVE_OFFSET 0x050 89549985eeSRichard Cochran #define CPSW1_SLAVE_SIZE 0x040 90549985eeSRichard Cochran #define CPSW1_CPDMA_OFFSET 0x100 91549985eeSRichard Cochran #define CPSW1_STATERAM_OFFSET 0x200 92549985eeSRichard Cochran #define CPSW1_CPTS_OFFSET 0x500 93549985eeSRichard Cochran #define CPSW1_ALE_OFFSET 0x600 94549985eeSRichard Cochran #define CPSW1_SLIVER_OFFSET 0x700 95549985eeSRichard Cochran 96549985eeSRichard Cochran #define CPSW2_HOST_PORT_OFFSET 0x108 97549985eeSRichard Cochran #define CPSW2_SLAVE_OFFSET 0x200 98549985eeSRichard Cochran #define CPSW2_SLAVE_SIZE 0x100 99549985eeSRichard Cochran #define CPSW2_CPDMA_OFFSET 0x800 100549985eeSRichard Cochran #define CPSW2_STATERAM_OFFSET 0xa00 101549985eeSRichard Cochran #define CPSW2_CPTS_OFFSET 0xc00 102549985eeSRichard Cochran #define CPSW2_ALE_OFFSET 0xd00 103549985eeSRichard Cochran #define CPSW2_SLIVER_OFFSET 0xd80 104549985eeSRichard Cochran #define CPSW2_BD_OFFSET 0x2000 105549985eeSRichard Cochran 106df828598SMugunthan V N #define CPDMA_RXTHRESH 0x0c0 107df828598SMugunthan V N #define CPDMA_RXFREE 0x0e0 108df828598SMugunthan V N #define CPDMA_TXHDP 0x00 109df828598SMugunthan V N #define CPDMA_RXHDP 0x20 110df828598SMugunthan V N #define CPDMA_TXCP 0x40 111df828598SMugunthan V N #define CPDMA_RXCP 0x60 112df828598SMugunthan V N 113df828598SMugunthan V N #define CPSW_POLL_WEIGHT 64 114df828598SMugunthan V N #define CPSW_MIN_PACKET_SIZE 60 115df828598SMugunthan V N #define CPSW_MAX_PACKET_SIZE (1500 + 14 + 4 + 4) 116df828598SMugunthan V N 117df828598SMugunthan V N #define RX_PRIORITY_MAPPING 0x76543210 118df828598SMugunthan V N #define TX_PRIORITY_MAPPING 0x33221100 119df828598SMugunthan V N #define CPDMA_TX_PRIORITY_MAP 0x76543210 120df828598SMugunthan V N 121df828598SMugunthan V N #define cpsw_enable_irq(priv) \ 122df828598SMugunthan V N do { \ 123df828598SMugunthan V N u32 i; \ 124df828598SMugunthan V N for (i = 0; i < priv->num_irqs; i++) \ 125df828598SMugunthan V N enable_irq(priv->irqs_table[i]); \ 126df828598SMugunthan V N } while (0); 127df828598SMugunthan V N #define cpsw_disable_irq(priv) \ 128df828598SMugunthan V N do { \ 129df828598SMugunthan V N u32 i; \ 130df828598SMugunthan V N for (i = 0; i < priv->num_irqs; i++) \ 131df828598SMugunthan V N disable_irq_nosync(priv->irqs_table[i]); \ 132df828598SMugunthan V N } while (0); 133df828598SMugunthan V N 134df828598SMugunthan V N static int debug_level; 135df828598SMugunthan V N module_param(debug_level, int, 0); 136df828598SMugunthan V N MODULE_PARM_DESC(debug_level, "cpsw debug level (NETIF_MSG bits)"); 137df828598SMugunthan V N 138df828598SMugunthan V N static int ale_ageout = 10; 139df828598SMugunthan V N module_param(ale_ageout, int, 0); 140df828598SMugunthan V N MODULE_PARM_DESC(ale_ageout, "cpsw ale ageout interval (seconds)"); 141df828598SMugunthan V N 142df828598SMugunthan V N static int rx_packet_max = CPSW_MAX_PACKET_SIZE; 143df828598SMugunthan V N module_param(rx_packet_max, int, 0); 144df828598SMugunthan V N MODULE_PARM_DESC(rx_packet_max, "maximum receive packet size (bytes)"); 145df828598SMugunthan V N 146996a5c27SRichard Cochran struct cpsw_wr_regs { 147df828598SMugunthan V N u32 id_ver; 148df828598SMugunthan V N u32 soft_reset; 149df828598SMugunthan V N u32 control; 150df828598SMugunthan V N u32 int_control; 151df828598SMugunthan V N u32 rx_thresh_en; 152df828598SMugunthan V N u32 rx_en; 153df828598SMugunthan V N u32 tx_en; 154df828598SMugunthan V N u32 misc_en; 155df828598SMugunthan V N }; 156df828598SMugunthan V N 157996a5c27SRichard Cochran struct cpsw_ss_regs { 158df828598SMugunthan V N u32 id_ver; 159df828598SMugunthan V N u32 control; 160df828598SMugunthan V N u32 soft_reset; 161df828598SMugunthan V N u32 stat_port_en; 162df828598SMugunthan V N u32 ptype; 163bd357af2SRichard Cochran u32 soft_idle; 164bd357af2SRichard Cochran u32 thru_rate; 165bd357af2SRichard Cochran u32 gap_thresh; 166bd357af2SRichard Cochran u32 tx_start_wds; 167bd357af2SRichard Cochran u32 flow_control; 168bd357af2SRichard Cochran u32 vlan_ltype; 169bd357af2SRichard Cochran u32 ts_ltype; 170bd357af2SRichard Cochran u32 dlr_ltype; 171df828598SMugunthan V N }; 172df828598SMugunthan V N 1739750a3adSRichard Cochran /* CPSW_PORT_V1 */ 1749750a3adSRichard Cochran #define CPSW1_MAX_BLKS 0x00 /* Maximum FIFO Blocks */ 1759750a3adSRichard Cochran #define CPSW1_BLK_CNT 0x04 /* FIFO Block Usage Count (Read Only) */ 1769750a3adSRichard Cochran #define CPSW1_TX_IN_CTL 0x08 /* Transmit FIFO Control */ 1779750a3adSRichard Cochran #define CPSW1_PORT_VLAN 0x0c /* VLAN Register */ 1789750a3adSRichard Cochran #define CPSW1_TX_PRI_MAP 0x10 /* Tx Header Priority to Switch Pri Mapping */ 1799750a3adSRichard Cochran #define CPSW1_TS_CTL 0x14 /* Time Sync Control */ 1809750a3adSRichard Cochran #define CPSW1_TS_SEQ_LTYPE 0x18 /* Time Sync Sequence ID Offset and Msg Type */ 1819750a3adSRichard Cochran #define CPSW1_TS_VLAN 0x1c /* Time Sync VLAN1 and VLAN2 */ 1829750a3adSRichard Cochran 1839750a3adSRichard Cochran /* CPSW_PORT_V2 */ 1849750a3adSRichard Cochran #define CPSW2_CONTROL 0x00 /* Control Register */ 1859750a3adSRichard Cochran #define CPSW2_MAX_BLKS 0x08 /* Maximum FIFO Blocks */ 1869750a3adSRichard Cochran #define CPSW2_BLK_CNT 0x0c /* FIFO Block Usage Count (Read Only) */ 1879750a3adSRichard Cochran #define CPSW2_TX_IN_CTL 0x10 /* Transmit FIFO Control */ 1889750a3adSRichard Cochran #define CPSW2_PORT_VLAN 0x14 /* VLAN Register */ 1899750a3adSRichard Cochran #define CPSW2_TX_PRI_MAP 0x18 /* Tx Header Priority to Switch Pri Mapping */ 1909750a3adSRichard Cochran #define CPSW2_TS_SEQ_MTYPE 0x1c /* Time Sync Sequence ID Offset and Msg Type */ 1919750a3adSRichard Cochran 1929750a3adSRichard Cochran /* CPSW_PORT_V1 and V2 */ 1939750a3adSRichard Cochran #define SA_LO 0x20 /* CPGMAC_SL Source Address Low */ 1949750a3adSRichard Cochran #define SA_HI 0x24 /* CPGMAC_SL Source Address High */ 1959750a3adSRichard Cochran #define SEND_PERCENT 0x28 /* Transmit Queue Send Percentages */ 1969750a3adSRichard Cochran 1979750a3adSRichard Cochran /* CPSW_PORT_V2 only */ 1989750a3adSRichard Cochran #define RX_DSCP_PRI_MAP0 0x30 /* Rx DSCP Priority to Rx Packet Mapping */ 1999750a3adSRichard Cochran #define RX_DSCP_PRI_MAP1 0x34 /* Rx DSCP Priority to Rx Packet Mapping */ 2009750a3adSRichard Cochran #define RX_DSCP_PRI_MAP2 0x38 /* Rx DSCP Priority to Rx Packet Mapping */ 2019750a3adSRichard Cochran #define RX_DSCP_PRI_MAP3 0x3c /* Rx DSCP Priority to Rx Packet Mapping */ 2029750a3adSRichard Cochran #define RX_DSCP_PRI_MAP4 0x40 /* Rx DSCP Priority to Rx Packet Mapping */ 2039750a3adSRichard Cochran #define RX_DSCP_PRI_MAP5 0x44 /* Rx DSCP Priority to Rx Packet Mapping */ 2049750a3adSRichard Cochran #define RX_DSCP_PRI_MAP6 0x48 /* Rx DSCP Priority to Rx Packet Mapping */ 2059750a3adSRichard Cochran #define RX_DSCP_PRI_MAP7 0x4c /* Rx DSCP Priority to Rx Packet Mapping */ 2069750a3adSRichard Cochran 2079750a3adSRichard Cochran /* Bit definitions for the CPSW2_CONTROL register */ 2089750a3adSRichard Cochran #define PASS_PRI_TAGGED (1<<24) /* Pass Priority Tagged */ 2099750a3adSRichard Cochran #define VLAN_LTYPE2_EN (1<<21) /* VLAN LTYPE 2 enable */ 2109750a3adSRichard Cochran #define VLAN_LTYPE1_EN (1<<20) /* VLAN LTYPE 1 enable */ 2119750a3adSRichard Cochran #define DSCP_PRI_EN (1<<16) /* DSCP Priority Enable */ 2129750a3adSRichard Cochran #define TS_320 (1<<14) /* Time Sync Dest Port 320 enable */ 2139750a3adSRichard Cochran #define TS_319 (1<<13) /* Time Sync Dest Port 319 enable */ 2149750a3adSRichard Cochran #define TS_132 (1<<12) /* Time Sync Dest IP Addr 132 enable */ 2159750a3adSRichard Cochran #define TS_131 (1<<11) /* Time Sync Dest IP Addr 131 enable */ 2169750a3adSRichard Cochran #define TS_130 (1<<10) /* Time Sync Dest IP Addr 130 enable */ 2179750a3adSRichard Cochran #define TS_129 (1<<9) /* Time Sync Dest IP Addr 129 enable */ 2189750a3adSRichard Cochran #define TS_BIT8 (1<<8) /* ts_ttl_nonzero? */ 2199750a3adSRichard Cochran #define TS_ANNEX_D_EN (1<<4) /* Time Sync Annex D enable */ 2209750a3adSRichard Cochran #define TS_LTYPE2_EN (1<<3) /* Time Sync LTYPE 2 enable */ 2219750a3adSRichard Cochran #define TS_LTYPE1_EN (1<<2) /* Time Sync LTYPE 1 enable */ 2229750a3adSRichard Cochran #define TS_TX_EN (1<<1) /* Time Sync Transmit Enable */ 2239750a3adSRichard Cochran #define TS_RX_EN (1<<0) /* Time Sync Receive Enable */ 2249750a3adSRichard Cochran 2259750a3adSRichard Cochran #define CTRL_TS_BITS \ 2269750a3adSRichard Cochran (TS_320 | TS_319 | TS_132 | TS_131 | TS_130 | TS_129 | TS_BIT8 | \ 2279750a3adSRichard Cochran TS_ANNEX_D_EN | TS_LTYPE1_EN) 2289750a3adSRichard Cochran 2299750a3adSRichard Cochran #define CTRL_ALL_TS_MASK (CTRL_TS_BITS | TS_TX_EN | TS_RX_EN) 2309750a3adSRichard Cochran #define CTRL_TX_TS_BITS (CTRL_TS_BITS | TS_TX_EN) 2319750a3adSRichard Cochran #define CTRL_RX_TS_BITS (CTRL_TS_BITS | TS_RX_EN) 2329750a3adSRichard Cochran 2339750a3adSRichard Cochran /* Bit definitions for the CPSW2_TS_SEQ_MTYPE register */ 2349750a3adSRichard Cochran #define TS_SEQ_ID_OFFSET_SHIFT (16) /* Time Sync Sequence ID Offset */ 2359750a3adSRichard Cochran #define TS_SEQ_ID_OFFSET_MASK (0x3f) 2369750a3adSRichard Cochran #define TS_MSG_TYPE_EN_SHIFT (0) /* Time Sync Message Type Enable */ 2379750a3adSRichard Cochran #define TS_MSG_TYPE_EN_MASK (0xffff) 2389750a3adSRichard Cochran 2399750a3adSRichard Cochran /* The PTP event messages - Sync, Delay_Req, Pdelay_Req, and Pdelay_Resp. */ 2409750a3adSRichard Cochran #define EVENT_MSG_BITS ((1<<0) | (1<<1) | (1<<2) | (1<<3)) 241df828598SMugunthan V N 2422e5b38abSRichard Cochran /* Bit definitions for the CPSW1_TS_CTL register */ 2432e5b38abSRichard Cochran #define CPSW_V1_TS_RX_EN BIT(0) 2442e5b38abSRichard Cochran #define CPSW_V1_TS_TX_EN BIT(4) 2452e5b38abSRichard Cochran #define CPSW_V1_MSG_TYPE_OFS 16 2462e5b38abSRichard Cochran 2472e5b38abSRichard Cochran /* Bit definitions for the CPSW1_TS_SEQ_LTYPE register */ 2482e5b38abSRichard Cochran #define CPSW_V1_SEQ_ID_OFS_SHIFT 16 2492e5b38abSRichard Cochran 250df828598SMugunthan V N struct cpsw_host_regs { 251df828598SMugunthan V N u32 max_blks; 252df828598SMugunthan V N u32 blk_cnt; 253df828598SMugunthan V N u32 flow_thresh; 254df828598SMugunthan V N u32 port_vlan; 255df828598SMugunthan V N u32 tx_pri_map; 256df828598SMugunthan V N u32 cpdma_tx_pri_map; 257df828598SMugunthan V N u32 cpdma_rx_chan_map; 258df828598SMugunthan V N }; 259df828598SMugunthan V N 260df828598SMugunthan V N struct cpsw_sliver_regs { 261df828598SMugunthan V N u32 id_ver; 262df828598SMugunthan V N u32 mac_control; 263df828598SMugunthan V N u32 mac_status; 264df828598SMugunthan V N u32 soft_reset; 265df828598SMugunthan V N u32 rx_maxlen; 266df828598SMugunthan V N u32 __reserved_0; 267df828598SMugunthan V N u32 rx_pause; 268df828598SMugunthan V N u32 tx_pause; 269df828598SMugunthan V N u32 __reserved_1; 270df828598SMugunthan V N u32 rx_pri_map; 271df828598SMugunthan V N }; 272df828598SMugunthan V N 273df828598SMugunthan V N struct cpsw_slave { 2749750a3adSRichard Cochran void __iomem *regs; 275df828598SMugunthan V N struct cpsw_sliver_regs __iomem *sliver; 276df828598SMugunthan V N int slave_num; 277df828598SMugunthan V N u32 mac_control; 278df828598SMugunthan V N struct cpsw_slave_data *data; 279df828598SMugunthan V N struct phy_device *phy; 280df828598SMugunthan V N }; 281df828598SMugunthan V N 2829750a3adSRichard Cochran static inline u32 slave_read(struct cpsw_slave *slave, u32 offset) 2839750a3adSRichard Cochran { 2849750a3adSRichard Cochran return __raw_readl(slave->regs + offset); 2859750a3adSRichard Cochran } 2869750a3adSRichard Cochran 2879750a3adSRichard Cochran static inline void slave_write(struct cpsw_slave *slave, u32 val, u32 offset) 2889750a3adSRichard Cochran { 2899750a3adSRichard Cochran __raw_writel(val, slave->regs + offset); 2909750a3adSRichard Cochran } 2919750a3adSRichard Cochran 292df828598SMugunthan V N struct cpsw_priv { 293df828598SMugunthan V N spinlock_t lock; 294df828598SMugunthan V N struct platform_device *pdev; 295df828598SMugunthan V N struct net_device *ndev; 296df828598SMugunthan V N struct resource *cpsw_res; 297a65dd5b2SRichard Cochran struct resource *cpsw_wr_res; 298df828598SMugunthan V N struct napi_struct napi; 299df828598SMugunthan V N struct device *dev; 300df828598SMugunthan V N struct cpsw_platform_data data; 301996a5c27SRichard Cochran struct cpsw_ss_regs __iomem *regs; 302996a5c27SRichard Cochran struct cpsw_wr_regs __iomem *wr_regs; 303df828598SMugunthan V N struct cpsw_host_regs __iomem *host_port_regs; 304df828598SMugunthan V N u32 msg_enable; 305e90cfac6SRichard Cochran u32 version; 306df828598SMugunthan V N struct net_device_stats stats; 307df828598SMugunthan V N int rx_packet_max; 308df828598SMugunthan V N int host_port; 309df828598SMugunthan V N struct clk *clk; 310df828598SMugunthan V N u8 mac_addr[ETH_ALEN]; 311df828598SMugunthan V N struct cpsw_slave *slaves; 312df828598SMugunthan V N struct cpdma_ctlr *dma; 313df828598SMugunthan V N struct cpdma_chan *txch, *rxch; 314df828598SMugunthan V N struct cpsw_ale *ale; 315df828598SMugunthan V N /* snapshot of IRQ numbers */ 316df828598SMugunthan V N u32 irqs_table[4]; 317df828598SMugunthan V N u32 num_irqs; 3182e5b38abSRichard Cochran struct cpts cpts; 319df828598SMugunthan V N }; 320df828598SMugunthan V N 321df828598SMugunthan V N #define napi_to_priv(napi) container_of(napi, struct cpsw_priv, napi) 322df828598SMugunthan V N #define for_each_slave(priv, func, arg...) \ 323df828598SMugunthan V N do { \ 324df828598SMugunthan V N int idx; \ 325df828598SMugunthan V N for (idx = 0; idx < (priv)->data.slaves; idx++) \ 326df828598SMugunthan V N (func)((priv)->slaves + idx, ##arg); \ 327df828598SMugunthan V N } while (0) 328df828598SMugunthan V N 3295c50a856SMugunthan V N static void cpsw_ndo_set_rx_mode(struct net_device *ndev) 3305c50a856SMugunthan V N { 3315c50a856SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 3325c50a856SMugunthan V N 3335c50a856SMugunthan V N if (ndev->flags & IFF_PROMISC) { 3345c50a856SMugunthan V N /* Enable promiscuous mode */ 3355c50a856SMugunthan V N dev_err(priv->dev, "Ignoring Promiscuous mode\n"); 3365c50a856SMugunthan V N return; 3375c50a856SMugunthan V N } 3385c50a856SMugunthan V N 3395c50a856SMugunthan V N /* Clear all mcast from ALE */ 3405c50a856SMugunthan V N cpsw_ale_flush_multicast(priv->ale, ALE_ALL_PORTS << priv->host_port); 3415c50a856SMugunthan V N 3425c50a856SMugunthan V N if (!netdev_mc_empty(ndev)) { 3435c50a856SMugunthan V N struct netdev_hw_addr *ha; 3445c50a856SMugunthan V N 3455c50a856SMugunthan V N /* program multicast address list into ALE register */ 3465c50a856SMugunthan V N netdev_for_each_mc_addr(ha, ndev) { 3475c50a856SMugunthan V N cpsw_ale_add_mcast(priv->ale, (u8 *)ha->addr, 3485c50a856SMugunthan V N ALE_ALL_PORTS << priv->host_port, 0, 0); 3495c50a856SMugunthan V N } 3505c50a856SMugunthan V N } 3515c50a856SMugunthan V N } 3525c50a856SMugunthan V N 353df828598SMugunthan V N static void cpsw_intr_enable(struct cpsw_priv *priv) 354df828598SMugunthan V N { 355996a5c27SRichard Cochran __raw_writel(0xFF, &priv->wr_regs->tx_en); 356996a5c27SRichard Cochran __raw_writel(0xFF, &priv->wr_regs->rx_en); 357df828598SMugunthan V N 358df828598SMugunthan V N cpdma_ctlr_int_ctrl(priv->dma, true); 359df828598SMugunthan V N return; 360df828598SMugunthan V N } 361df828598SMugunthan V N 362df828598SMugunthan V N static void cpsw_intr_disable(struct cpsw_priv *priv) 363df828598SMugunthan V N { 364996a5c27SRichard Cochran __raw_writel(0, &priv->wr_regs->tx_en); 365996a5c27SRichard Cochran __raw_writel(0, &priv->wr_regs->rx_en); 366df828598SMugunthan V N 367df828598SMugunthan V N cpdma_ctlr_int_ctrl(priv->dma, false); 368df828598SMugunthan V N return; 369df828598SMugunthan V N } 370df828598SMugunthan V N 371df828598SMugunthan V N void cpsw_tx_handler(void *token, int len, int status) 372df828598SMugunthan V N { 373df828598SMugunthan V N struct sk_buff *skb = token; 374df828598SMugunthan V N struct net_device *ndev = skb->dev; 375df828598SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 376df828598SMugunthan V N 377df828598SMugunthan V N if (unlikely(netif_queue_stopped(ndev))) 378df828598SMugunthan V N netif_start_queue(ndev); 3792e5b38abSRichard Cochran cpts_tx_timestamp(&priv->cpts, skb); 380df828598SMugunthan V N priv->stats.tx_packets++; 381df828598SMugunthan V N priv->stats.tx_bytes += len; 382df828598SMugunthan V N dev_kfree_skb_any(skb); 383df828598SMugunthan V N } 384df828598SMugunthan V N 385df828598SMugunthan V N void cpsw_rx_handler(void *token, int len, int status) 386df828598SMugunthan V N { 387df828598SMugunthan V N struct sk_buff *skb = token; 388df828598SMugunthan V N struct net_device *ndev = skb->dev; 389df828598SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 390df828598SMugunthan V N int ret = 0; 391df828598SMugunthan V N 392df828598SMugunthan V N /* free and bail if we are shutting down */ 393df828598SMugunthan V N if (unlikely(!netif_running(ndev)) || 394df828598SMugunthan V N unlikely(!netif_carrier_ok(ndev))) { 395df828598SMugunthan V N dev_kfree_skb_any(skb); 396df828598SMugunthan V N return; 397df828598SMugunthan V N } 398df828598SMugunthan V N if (likely(status >= 0)) { 399df828598SMugunthan V N skb_put(skb, len); 4002e5b38abSRichard Cochran cpts_rx_timestamp(&priv->cpts, skb); 401df828598SMugunthan V N skb->protocol = eth_type_trans(skb, ndev); 402df828598SMugunthan V N netif_receive_skb(skb); 403df828598SMugunthan V N priv->stats.rx_bytes += len; 404df828598SMugunthan V N priv->stats.rx_packets++; 405df828598SMugunthan V N skb = NULL; 406df828598SMugunthan V N } 407df828598SMugunthan V N 408df828598SMugunthan V N if (unlikely(!netif_running(ndev))) { 409df828598SMugunthan V N if (skb) 410df828598SMugunthan V N dev_kfree_skb_any(skb); 411df828598SMugunthan V N return; 412df828598SMugunthan V N } 413df828598SMugunthan V N 414df828598SMugunthan V N if (likely(!skb)) { 415df828598SMugunthan V N skb = netdev_alloc_skb_ip_align(ndev, priv->rx_packet_max); 416df828598SMugunthan V N if (WARN_ON(!skb)) 417df828598SMugunthan V N return; 418df828598SMugunthan V N 419df828598SMugunthan V N ret = cpdma_chan_submit(priv->rxch, skb, skb->data, 420df828598SMugunthan V N skb_tailroom(skb), GFP_KERNEL); 421df828598SMugunthan V N } 422df828598SMugunthan V N WARN_ON(ret < 0); 423df828598SMugunthan V N } 424df828598SMugunthan V N 425df828598SMugunthan V N static irqreturn_t cpsw_interrupt(int irq, void *dev_id) 426df828598SMugunthan V N { 427df828598SMugunthan V N struct cpsw_priv *priv = dev_id; 428df828598SMugunthan V N 429df828598SMugunthan V N if (likely(netif_running(priv->ndev))) { 430df828598SMugunthan V N cpsw_intr_disable(priv); 431df828598SMugunthan V N cpsw_disable_irq(priv); 432df828598SMugunthan V N napi_schedule(&priv->napi); 433df828598SMugunthan V N } 434df828598SMugunthan V N return IRQ_HANDLED; 435df828598SMugunthan V N } 436df828598SMugunthan V N 437df828598SMugunthan V N static inline int cpsw_get_slave_port(struct cpsw_priv *priv, u32 slave_num) 438df828598SMugunthan V N { 439df828598SMugunthan V N if (priv->host_port == 0) 440df828598SMugunthan V N return slave_num + 1; 441df828598SMugunthan V N else 442df828598SMugunthan V N return slave_num; 443df828598SMugunthan V N } 444df828598SMugunthan V N 445df828598SMugunthan V N static int cpsw_poll(struct napi_struct *napi, int budget) 446df828598SMugunthan V N { 447df828598SMugunthan V N struct cpsw_priv *priv = napi_to_priv(napi); 448df828598SMugunthan V N int num_tx, num_rx; 449df828598SMugunthan V N 450df828598SMugunthan V N num_tx = cpdma_chan_process(priv->txch, 128); 451df828598SMugunthan V N num_rx = cpdma_chan_process(priv->rxch, budget); 452df828598SMugunthan V N 453df828598SMugunthan V N if (num_rx || num_tx) 454df828598SMugunthan V N cpsw_dbg(priv, intr, "poll %d rx, %d tx pkts\n", 455df828598SMugunthan V N num_rx, num_tx); 456df828598SMugunthan V N 457df828598SMugunthan V N if (num_rx < budget) { 458df828598SMugunthan V N napi_complete(napi); 459df828598SMugunthan V N cpsw_intr_enable(priv); 460df828598SMugunthan V N cpdma_ctlr_eoi(priv->dma); 461df828598SMugunthan V N cpsw_enable_irq(priv); 462df828598SMugunthan V N } 463df828598SMugunthan V N 464df828598SMugunthan V N return num_rx; 465df828598SMugunthan V N } 466df828598SMugunthan V N 467df828598SMugunthan V N static inline void soft_reset(const char *module, void __iomem *reg) 468df828598SMugunthan V N { 469df828598SMugunthan V N unsigned long timeout = jiffies + HZ; 470df828598SMugunthan V N 471df828598SMugunthan V N __raw_writel(1, reg); 472df828598SMugunthan V N do { 473df828598SMugunthan V N cpu_relax(); 474df828598SMugunthan V N } while ((__raw_readl(reg) & 1) && time_after(timeout, jiffies)); 475df828598SMugunthan V N 476df828598SMugunthan V N WARN(__raw_readl(reg) & 1, "failed to soft-reset %s\n", module); 477df828598SMugunthan V N } 478df828598SMugunthan V N 479df828598SMugunthan V N #define mac_hi(mac) (((mac)[0] << 0) | ((mac)[1] << 8) | \ 480df828598SMugunthan V N ((mac)[2] << 16) | ((mac)[3] << 24)) 481df828598SMugunthan V N #define mac_lo(mac) (((mac)[4] << 0) | ((mac)[5] << 8)) 482df828598SMugunthan V N 483df828598SMugunthan V N static void cpsw_set_slave_mac(struct cpsw_slave *slave, 484df828598SMugunthan V N struct cpsw_priv *priv) 485df828598SMugunthan V N { 4869750a3adSRichard Cochran slave_write(slave, mac_hi(priv->mac_addr), SA_HI); 4879750a3adSRichard Cochran slave_write(slave, mac_lo(priv->mac_addr), SA_LO); 488df828598SMugunthan V N } 489df828598SMugunthan V N 490df828598SMugunthan V N static void _cpsw_adjust_link(struct cpsw_slave *slave, 491df828598SMugunthan V N struct cpsw_priv *priv, bool *link) 492df828598SMugunthan V N { 493df828598SMugunthan V N struct phy_device *phy = slave->phy; 494df828598SMugunthan V N u32 mac_control = 0; 495df828598SMugunthan V N u32 slave_port; 496df828598SMugunthan V N 497df828598SMugunthan V N if (!phy) 498df828598SMugunthan V N return; 499df828598SMugunthan V N 500df828598SMugunthan V N slave_port = cpsw_get_slave_port(priv, slave->slave_num); 501df828598SMugunthan V N 502df828598SMugunthan V N if (phy->link) { 503df828598SMugunthan V N mac_control = priv->data.mac_control; 504df828598SMugunthan V N 505df828598SMugunthan V N /* enable forwarding */ 506df828598SMugunthan V N cpsw_ale_control_set(priv->ale, slave_port, 507df828598SMugunthan V N ALE_PORT_STATE, ALE_PORT_STATE_FORWARD); 508df828598SMugunthan V N 509df828598SMugunthan V N if (phy->speed == 1000) 510df828598SMugunthan V N mac_control |= BIT(7); /* GIGABITEN */ 511df828598SMugunthan V N if (phy->duplex) 512df828598SMugunthan V N mac_control |= BIT(0); /* FULLDUPLEXEN */ 513342b7b74SDaniel Mack 514342b7b74SDaniel Mack /* set speed_in input in case RMII mode is used in 100Mbps */ 515342b7b74SDaniel Mack if (phy->speed == 100) 516342b7b74SDaniel Mack mac_control |= BIT(15); 517342b7b74SDaniel Mack 518df828598SMugunthan V N *link = true; 519df828598SMugunthan V N } else { 520df828598SMugunthan V N mac_control = 0; 521df828598SMugunthan V N /* disable forwarding */ 522df828598SMugunthan V N cpsw_ale_control_set(priv->ale, slave_port, 523df828598SMugunthan V N ALE_PORT_STATE, ALE_PORT_STATE_DISABLE); 524df828598SMugunthan V N } 525df828598SMugunthan V N 526df828598SMugunthan V N if (mac_control != slave->mac_control) { 527df828598SMugunthan V N phy_print_status(phy); 528df828598SMugunthan V N __raw_writel(mac_control, &slave->sliver->mac_control); 529df828598SMugunthan V N } 530df828598SMugunthan V N 531df828598SMugunthan V N slave->mac_control = mac_control; 532df828598SMugunthan V N } 533df828598SMugunthan V N 534df828598SMugunthan V N static void cpsw_adjust_link(struct net_device *ndev) 535df828598SMugunthan V N { 536df828598SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 537df828598SMugunthan V N bool link = false; 538df828598SMugunthan V N 539df828598SMugunthan V N for_each_slave(priv, _cpsw_adjust_link, priv, &link); 540df828598SMugunthan V N 541df828598SMugunthan V N if (link) { 542df828598SMugunthan V N netif_carrier_on(ndev); 543df828598SMugunthan V N if (netif_running(ndev)) 544df828598SMugunthan V N netif_wake_queue(ndev); 545df828598SMugunthan V N } else { 546df828598SMugunthan V N netif_carrier_off(ndev); 547df828598SMugunthan V N netif_stop_queue(ndev); 548df828598SMugunthan V N } 549df828598SMugunthan V N } 550df828598SMugunthan V N 551df828598SMugunthan V N static inline int __show_stat(char *buf, int maxlen, const char *name, u32 val) 552df828598SMugunthan V N { 553df828598SMugunthan V N static char *leader = "........................................"; 554df828598SMugunthan V N 555df828598SMugunthan V N if (!val) 556df828598SMugunthan V N return 0; 557df828598SMugunthan V N else 558df828598SMugunthan V N return snprintf(buf, maxlen, "%s %s %10d\n", name, 559df828598SMugunthan V N leader + strlen(name), val); 560df828598SMugunthan V N } 561df828598SMugunthan V N 562df828598SMugunthan V N static void cpsw_slave_open(struct cpsw_slave *slave, struct cpsw_priv *priv) 563df828598SMugunthan V N { 564df828598SMugunthan V N char name[32]; 565df828598SMugunthan V N u32 slave_port; 566df828598SMugunthan V N 567df828598SMugunthan V N sprintf(name, "slave-%d", slave->slave_num); 568df828598SMugunthan V N 569df828598SMugunthan V N soft_reset(name, &slave->sliver->soft_reset); 570df828598SMugunthan V N 571df828598SMugunthan V N /* setup priority mapping */ 572df828598SMugunthan V N __raw_writel(RX_PRIORITY_MAPPING, &slave->sliver->rx_pri_map); 5739750a3adSRichard Cochran 5749750a3adSRichard Cochran switch (priv->version) { 5759750a3adSRichard Cochran case CPSW_VERSION_1: 5769750a3adSRichard Cochran slave_write(slave, TX_PRIORITY_MAPPING, CPSW1_TX_PRI_MAP); 5779750a3adSRichard Cochran break; 5789750a3adSRichard Cochran case CPSW_VERSION_2: 5799750a3adSRichard Cochran slave_write(slave, TX_PRIORITY_MAPPING, CPSW2_TX_PRI_MAP); 5809750a3adSRichard Cochran break; 5819750a3adSRichard Cochran } 582df828598SMugunthan V N 583df828598SMugunthan V N /* setup max packet size, and mac address */ 584df828598SMugunthan V N __raw_writel(priv->rx_packet_max, &slave->sliver->rx_maxlen); 585df828598SMugunthan V N cpsw_set_slave_mac(slave, priv); 586df828598SMugunthan V N 587df828598SMugunthan V N slave->mac_control = 0; /* no link yet */ 588df828598SMugunthan V N 589df828598SMugunthan V N slave_port = cpsw_get_slave_port(priv, slave->slave_num); 590df828598SMugunthan V N 591df828598SMugunthan V N cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast, 592df828598SMugunthan V N 1 << slave_port, 0, ALE_MCAST_FWD_2); 593df828598SMugunthan V N 594df828598SMugunthan V N slave->phy = phy_connect(priv->ndev, slave->data->phy_id, 595df828598SMugunthan V N &cpsw_adjust_link, 0, slave->data->phy_if); 596df828598SMugunthan V N if (IS_ERR(slave->phy)) { 597df828598SMugunthan V N dev_err(priv->dev, "phy %s not found on slave %d\n", 598df828598SMugunthan V N slave->data->phy_id, slave->slave_num); 599df828598SMugunthan V N slave->phy = NULL; 600df828598SMugunthan V N } else { 601df828598SMugunthan V N dev_info(priv->dev, "phy found : id is : 0x%x\n", 602df828598SMugunthan V N slave->phy->phy_id); 603df828598SMugunthan V N phy_start(slave->phy); 604df828598SMugunthan V N } 605df828598SMugunthan V N } 606df828598SMugunthan V N 607df828598SMugunthan V N static void cpsw_init_host_port(struct cpsw_priv *priv) 608df828598SMugunthan V N { 609df828598SMugunthan V N /* soft reset the controller and initialize ale */ 610df828598SMugunthan V N soft_reset("cpsw", &priv->regs->soft_reset); 611df828598SMugunthan V N cpsw_ale_start(priv->ale); 612df828598SMugunthan V N 613df828598SMugunthan V N /* switch to vlan unaware mode */ 614df828598SMugunthan V N cpsw_ale_control_set(priv->ale, 0, ALE_VLAN_AWARE, 0); 615df828598SMugunthan V N 616df828598SMugunthan V N /* setup host port priority mapping */ 617df828598SMugunthan V N __raw_writel(CPDMA_TX_PRIORITY_MAP, 618df828598SMugunthan V N &priv->host_port_regs->cpdma_tx_pri_map); 619df828598SMugunthan V N __raw_writel(0, &priv->host_port_regs->cpdma_rx_chan_map); 620df828598SMugunthan V N 621df828598SMugunthan V N cpsw_ale_control_set(priv->ale, priv->host_port, 622df828598SMugunthan V N ALE_PORT_STATE, ALE_PORT_STATE_FORWARD); 623df828598SMugunthan V N 624df828598SMugunthan V N cpsw_ale_add_ucast(priv->ale, priv->mac_addr, priv->host_port, 0); 625df828598SMugunthan V N cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast, 626df828598SMugunthan V N 1 << priv->host_port, 0, ALE_MCAST_FWD_2); 627df828598SMugunthan V N } 628df828598SMugunthan V N 629df828598SMugunthan V N static int cpsw_ndo_open(struct net_device *ndev) 630df828598SMugunthan V N { 631df828598SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 632df828598SMugunthan V N int i, ret; 633df828598SMugunthan V N u32 reg; 634df828598SMugunthan V N 635df828598SMugunthan V N cpsw_intr_disable(priv); 636df828598SMugunthan V N netif_carrier_off(ndev); 637df828598SMugunthan V N 638f150bd7fSMugunthan V N pm_runtime_get_sync(&priv->pdev->dev); 639df828598SMugunthan V N 640549985eeSRichard Cochran reg = priv->version; 641df828598SMugunthan V N 642df828598SMugunthan V N dev_info(priv->dev, "initializing cpsw version %d.%d (%d)\n", 643df828598SMugunthan V N CPSW_MAJOR_VERSION(reg), CPSW_MINOR_VERSION(reg), 644df828598SMugunthan V N CPSW_RTL_VERSION(reg)); 645df828598SMugunthan V N 646df828598SMugunthan V N /* initialize host and slave ports */ 647df828598SMugunthan V N cpsw_init_host_port(priv); 648df828598SMugunthan V N for_each_slave(priv, cpsw_slave_open, priv); 649df828598SMugunthan V N 650df828598SMugunthan V N /* setup tx dma to fixed prio and zero offset */ 651df828598SMugunthan V N cpdma_control_set(priv->dma, CPDMA_TX_PRIO_FIXED, 1); 652df828598SMugunthan V N cpdma_control_set(priv->dma, CPDMA_RX_BUFFER_OFFSET, 0); 653df828598SMugunthan V N 654df828598SMugunthan V N /* disable priority elevation and enable statistics on all ports */ 655df828598SMugunthan V N __raw_writel(0, &priv->regs->ptype); 656df828598SMugunthan V N 657df828598SMugunthan V N /* enable statistics collection only on the host port */ 658df828598SMugunthan V N __raw_writel(0x7, &priv->regs->stat_port_en); 659df828598SMugunthan V N 660df828598SMugunthan V N if (WARN_ON(!priv->data.rx_descs)) 661df828598SMugunthan V N priv->data.rx_descs = 128; 662df828598SMugunthan V N 663df828598SMugunthan V N for (i = 0; i < priv->data.rx_descs; i++) { 664df828598SMugunthan V N struct sk_buff *skb; 665df828598SMugunthan V N 666df828598SMugunthan V N ret = -ENOMEM; 667df828598SMugunthan V N skb = netdev_alloc_skb_ip_align(priv->ndev, 668df828598SMugunthan V N priv->rx_packet_max); 669df828598SMugunthan V N if (!skb) 670df828598SMugunthan V N break; 671df828598SMugunthan V N ret = cpdma_chan_submit(priv->rxch, skb, skb->data, 672df828598SMugunthan V N skb_tailroom(skb), GFP_KERNEL); 673df828598SMugunthan V N if (WARN_ON(ret < 0)) 674df828598SMugunthan V N break; 675df828598SMugunthan V N } 676df828598SMugunthan V N /* continue even if we didn't manage to submit all receive descs */ 677df828598SMugunthan V N cpsw_info(priv, ifup, "submitted %d rx descriptors\n", i); 678df828598SMugunthan V N 679df828598SMugunthan V N cpdma_ctlr_start(priv->dma); 680df828598SMugunthan V N cpsw_intr_enable(priv); 681df828598SMugunthan V N napi_enable(&priv->napi); 682df828598SMugunthan V N cpdma_ctlr_eoi(priv->dma); 683df828598SMugunthan V N 684df828598SMugunthan V N return 0; 685df828598SMugunthan V N } 686df828598SMugunthan V N 687df828598SMugunthan V N static void cpsw_slave_stop(struct cpsw_slave *slave, struct cpsw_priv *priv) 688df828598SMugunthan V N { 689df828598SMugunthan V N if (!slave->phy) 690df828598SMugunthan V N return; 691df828598SMugunthan V N phy_stop(slave->phy); 692df828598SMugunthan V N phy_disconnect(slave->phy); 693df828598SMugunthan V N slave->phy = NULL; 694df828598SMugunthan V N } 695df828598SMugunthan V N 696df828598SMugunthan V N static int cpsw_ndo_stop(struct net_device *ndev) 697df828598SMugunthan V N { 698df828598SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 699df828598SMugunthan V N 700df828598SMugunthan V N cpsw_info(priv, ifdown, "shutting down cpsw device\n"); 701df828598SMugunthan V N netif_stop_queue(priv->ndev); 702df828598SMugunthan V N napi_disable(&priv->napi); 703df828598SMugunthan V N netif_carrier_off(priv->ndev); 70471380f9bSMugunthan V N cpsw_intr_disable(priv); 70571380f9bSMugunthan V N cpdma_ctlr_int_ctrl(priv->dma, false); 70671380f9bSMugunthan V N cpdma_ctlr_stop(priv->dma); 707df828598SMugunthan V N cpsw_ale_stop(priv->ale); 708df828598SMugunthan V N for_each_slave(priv, cpsw_slave_stop, priv); 709f150bd7fSMugunthan V N pm_runtime_put_sync(&priv->pdev->dev); 710df828598SMugunthan V N return 0; 711df828598SMugunthan V N } 712df828598SMugunthan V N 713df828598SMugunthan V N static netdev_tx_t cpsw_ndo_start_xmit(struct sk_buff *skb, 714df828598SMugunthan V N struct net_device *ndev) 715df828598SMugunthan V N { 716df828598SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 717df828598SMugunthan V N int ret; 718df828598SMugunthan V N 719df828598SMugunthan V N ndev->trans_start = jiffies; 720df828598SMugunthan V N 721df828598SMugunthan V N if (skb_padto(skb, CPSW_MIN_PACKET_SIZE)) { 722df828598SMugunthan V N cpsw_err(priv, tx_err, "packet pad failed\n"); 723df828598SMugunthan V N priv->stats.tx_dropped++; 724df828598SMugunthan V N return NETDEV_TX_OK; 725df828598SMugunthan V N } 726df828598SMugunthan V N 7272e5b38abSRichard Cochran if (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP && priv->cpts.tx_enable) 7282e5b38abSRichard Cochran skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 7292e5b38abSRichard Cochran 7302e5b38abSRichard Cochran skb_tx_timestamp(skb); 7312e5b38abSRichard Cochran 732df828598SMugunthan V N ret = cpdma_chan_submit(priv->txch, skb, skb->data, 733df828598SMugunthan V N skb->len, GFP_KERNEL); 734df828598SMugunthan V N if (unlikely(ret != 0)) { 735df828598SMugunthan V N cpsw_err(priv, tx_err, "desc submit failed\n"); 736df828598SMugunthan V N goto fail; 737df828598SMugunthan V N } 738df828598SMugunthan V N 739df828598SMugunthan V N return NETDEV_TX_OK; 740df828598SMugunthan V N fail: 741df828598SMugunthan V N priv->stats.tx_dropped++; 742df828598SMugunthan V N netif_stop_queue(ndev); 743df828598SMugunthan V N return NETDEV_TX_BUSY; 744df828598SMugunthan V N } 745df828598SMugunthan V N 746df828598SMugunthan V N static void cpsw_ndo_change_rx_flags(struct net_device *ndev, int flags) 747df828598SMugunthan V N { 748df828598SMugunthan V N /* 749df828598SMugunthan V N * The switch cannot operate in promiscuous mode without substantial 750df828598SMugunthan V N * headache. For promiscuous mode to work, we would need to put the 751df828598SMugunthan V N * ALE in bypass mode and route all traffic to the host port. 752df828598SMugunthan V N * Subsequently, the host will need to operate as a "bridge", learn, 753df828598SMugunthan V N * and flood as needed. For now, we simply complain here and 754df828598SMugunthan V N * do nothing about it :-) 755df828598SMugunthan V N */ 756df828598SMugunthan V N if ((flags & IFF_PROMISC) && (ndev->flags & IFF_PROMISC)) 757df828598SMugunthan V N dev_err(&ndev->dev, "promiscuity ignored!\n"); 758df828598SMugunthan V N 759df828598SMugunthan V N /* 760df828598SMugunthan V N * The switch cannot filter multicast traffic unless it is configured 761df828598SMugunthan V N * in "VLAN Aware" mode. Unfortunately, VLAN awareness requires a 762df828598SMugunthan V N * whole bunch of additional logic that this driver does not implement 763df828598SMugunthan V N * at present. 764df828598SMugunthan V N */ 765df828598SMugunthan V N if ((flags & IFF_ALLMULTI) && !(ndev->flags & IFF_ALLMULTI)) 766df828598SMugunthan V N dev_err(&ndev->dev, "multicast traffic cannot be filtered!\n"); 767df828598SMugunthan V N } 768df828598SMugunthan V N 7692e5b38abSRichard Cochran #ifdef CONFIG_TI_CPTS 7702e5b38abSRichard Cochran 7712e5b38abSRichard Cochran static void cpsw_hwtstamp_v1(struct cpsw_priv *priv) 7722e5b38abSRichard Cochran { 7732e5b38abSRichard Cochran struct cpsw_slave *slave = &priv->slaves[priv->data.cpts_active_slave]; 7742e5b38abSRichard Cochran u32 ts_en, seq_id; 7752e5b38abSRichard Cochran 7762e5b38abSRichard Cochran if (!priv->cpts.tx_enable && !priv->cpts.rx_enable) { 7772e5b38abSRichard Cochran slave_write(slave, 0, CPSW1_TS_CTL); 7782e5b38abSRichard Cochran return; 7792e5b38abSRichard Cochran } 7802e5b38abSRichard Cochran 7812e5b38abSRichard Cochran seq_id = (30 << CPSW_V1_SEQ_ID_OFS_SHIFT) | ETH_P_1588; 7822e5b38abSRichard Cochran ts_en = EVENT_MSG_BITS << CPSW_V1_MSG_TYPE_OFS; 7832e5b38abSRichard Cochran 7842e5b38abSRichard Cochran if (priv->cpts.tx_enable) 7852e5b38abSRichard Cochran ts_en |= CPSW_V1_TS_TX_EN; 7862e5b38abSRichard Cochran 7872e5b38abSRichard Cochran if (priv->cpts.rx_enable) 7882e5b38abSRichard Cochran ts_en |= CPSW_V1_TS_RX_EN; 7892e5b38abSRichard Cochran 7902e5b38abSRichard Cochran slave_write(slave, ts_en, CPSW1_TS_CTL); 7912e5b38abSRichard Cochran slave_write(slave, seq_id, CPSW1_TS_SEQ_LTYPE); 7922e5b38abSRichard Cochran } 7932e5b38abSRichard Cochran 7942e5b38abSRichard Cochran static void cpsw_hwtstamp_v2(struct cpsw_priv *priv) 7952e5b38abSRichard Cochran { 7962e5b38abSRichard Cochran struct cpsw_slave *slave = &priv->slaves[priv->data.cpts_active_slave]; 7972e5b38abSRichard Cochran u32 ctrl, mtype; 7982e5b38abSRichard Cochran 7992e5b38abSRichard Cochran ctrl = slave_read(slave, CPSW2_CONTROL); 8002e5b38abSRichard Cochran ctrl &= ~CTRL_ALL_TS_MASK; 8012e5b38abSRichard Cochran 8022e5b38abSRichard Cochran if (priv->cpts.tx_enable) 8032e5b38abSRichard Cochran ctrl |= CTRL_TX_TS_BITS; 8042e5b38abSRichard Cochran 8052e5b38abSRichard Cochran if (priv->cpts.rx_enable) 8062e5b38abSRichard Cochran ctrl |= CTRL_RX_TS_BITS; 8072e5b38abSRichard Cochran 8082e5b38abSRichard Cochran mtype = (30 << TS_SEQ_ID_OFFSET_SHIFT) | EVENT_MSG_BITS; 8092e5b38abSRichard Cochran 8102e5b38abSRichard Cochran slave_write(slave, mtype, CPSW2_TS_SEQ_MTYPE); 8112e5b38abSRichard Cochran slave_write(slave, ctrl, CPSW2_CONTROL); 8122e5b38abSRichard Cochran __raw_writel(ETH_P_1588, &priv->regs->ts_ltype); 8132e5b38abSRichard Cochran } 8142e5b38abSRichard Cochran 8153177bf6fSMugunthan V N static int cpsw_hwtstamp_ioctl(struct net_device *dev, struct ifreq *ifr) 8162e5b38abSRichard Cochran { 8173177bf6fSMugunthan V N struct cpsw_priv *priv = netdev_priv(dev); 8182e5b38abSRichard Cochran struct cpts *cpts = &priv->cpts; 8192e5b38abSRichard Cochran struct hwtstamp_config cfg; 8202e5b38abSRichard Cochran 8212e5b38abSRichard Cochran if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg))) 8222e5b38abSRichard Cochran return -EFAULT; 8232e5b38abSRichard Cochran 8242e5b38abSRichard Cochran /* reserved for future extensions */ 8252e5b38abSRichard Cochran if (cfg.flags) 8262e5b38abSRichard Cochran return -EINVAL; 8272e5b38abSRichard Cochran 8282e5b38abSRichard Cochran switch (cfg.tx_type) { 8292e5b38abSRichard Cochran case HWTSTAMP_TX_OFF: 8302e5b38abSRichard Cochran cpts->tx_enable = 0; 8312e5b38abSRichard Cochran break; 8322e5b38abSRichard Cochran case HWTSTAMP_TX_ON: 8332e5b38abSRichard Cochran cpts->tx_enable = 1; 8342e5b38abSRichard Cochran break; 8352e5b38abSRichard Cochran default: 8362e5b38abSRichard Cochran return -ERANGE; 8372e5b38abSRichard Cochran } 8382e5b38abSRichard Cochran 8392e5b38abSRichard Cochran switch (cfg.rx_filter) { 8402e5b38abSRichard Cochran case HWTSTAMP_FILTER_NONE: 8412e5b38abSRichard Cochran cpts->rx_enable = 0; 8422e5b38abSRichard Cochran break; 8432e5b38abSRichard Cochran case HWTSTAMP_FILTER_ALL: 8442e5b38abSRichard Cochran case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: 8452e5b38abSRichard Cochran case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: 8462e5b38abSRichard Cochran case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: 8472e5b38abSRichard Cochran return -ERANGE; 8482e5b38abSRichard Cochran case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: 8492e5b38abSRichard Cochran case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 8502e5b38abSRichard Cochran case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 8512e5b38abSRichard Cochran case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: 8522e5b38abSRichard Cochran case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: 8532e5b38abSRichard Cochran case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: 8542e5b38abSRichard Cochran case HWTSTAMP_FILTER_PTP_V2_EVENT: 8552e5b38abSRichard Cochran case HWTSTAMP_FILTER_PTP_V2_SYNC: 8562e5b38abSRichard Cochran case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 8572e5b38abSRichard Cochran cpts->rx_enable = 1; 8582e5b38abSRichard Cochran cfg.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT; 8592e5b38abSRichard Cochran break; 8602e5b38abSRichard Cochran default: 8612e5b38abSRichard Cochran return -ERANGE; 8622e5b38abSRichard Cochran } 8632e5b38abSRichard Cochran 8642e5b38abSRichard Cochran switch (priv->version) { 8652e5b38abSRichard Cochran case CPSW_VERSION_1: 8662e5b38abSRichard Cochran cpsw_hwtstamp_v1(priv); 8672e5b38abSRichard Cochran break; 8682e5b38abSRichard Cochran case CPSW_VERSION_2: 8692e5b38abSRichard Cochran cpsw_hwtstamp_v2(priv); 8702e5b38abSRichard Cochran break; 8712e5b38abSRichard Cochran default: 8722e5b38abSRichard Cochran return -ENOTSUPP; 8732e5b38abSRichard Cochran } 8742e5b38abSRichard Cochran 8752e5b38abSRichard Cochran return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0; 8762e5b38abSRichard Cochran } 8772e5b38abSRichard Cochran 8782e5b38abSRichard Cochran #endif /*CONFIG_TI_CPTS*/ 8792e5b38abSRichard Cochran 8802e5b38abSRichard Cochran static int cpsw_ndo_ioctl(struct net_device *dev, struct ifreq *req, int cmd) 8812e5b38abSRichard Cochran { 8822e5b38abSRichard Cochran if (!netif_running(dev)) 8832e5b38abSRichard Cochran return -EINVAL; 8842e5b38abSRichard Cochran 8852e5b38abSRichard Cochran #ifdef CONFIG_TI_CPTS 8862e5b38abSRichard Cochran if (cmd == SIOCSHWTSTAMP) 8873177bf6fSMugunthan V N return cpsw_hwtstamp_ioctl(dev, req); 8882e5b38abSRichard Cochran #endif 8892e5b38abSRichard Cochran return -ENOTSUPP; 8902e5b38abSRichard Cochran } 8912e5b38abSRichard Cochran 892df828598SMugunthan V N static void cpsw_ndo_tx_timeout(struct net_device *ndev) 893df828598SMugunthan V N { 894df828598SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 895df828598SMugunthan V N 896df828598SMugunthan V N cpsw_err(priv, tx_err, "transmit timeout, restarting dma\n"); 897df828598SMugunthan V N priv->stats.tx_errors++; 898df828598SMugunthan V N cpsw_intr_disable(priv); 899df828598SMugunthan V N cpdma_ctlr_int_ctrl(priv->dma, false); 900df828598SMugunthan V N cpdma_chan_stop(priv->txch); 901df828598SMugunthan V N cpdma_chan_start(priv->txch); 902df828598SMugunthan V N cpdma_ctlr_int_ctrl(priv->dma, true); 903df828598SMugunthan V N cpsw_intr_enable(priv); 904df828598SMugunthan V N cpdma_ctlr_eoi(priv->dma); 905df828598SMugunthan V N } 906df828598SMugunthan V N 907df828598SMugunthan V N static struct net_device_stats *cpsw_ndo_get_stats(struct net_device *ndev) 908df828598SMugunthan V N { 909df828598SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 910df828598SMugunthan V N return &priv->stats; 911df828598SMugunthan V N } 912df828598SMugunthan V N 913df828598SMugunthan V N #ifdef CONFIG_NET_POLL_CONTROLLER 914df828598SMugunthan V N static void cpsw_ndo_poll_controller(struct net_device *ndev) 915df828598SMugunthan V N { 916df828598SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 917df828598SMugunthan V N 918df828598SMugunthan V N cpsw_intr_disable(priv); 919df828598SMugunthan V N cpdma_ctlr_int_ctrl(priv->dma, false); 920df828598SMugunthan V N cpsw_interrupt(ndev->irq, priv); 921df828598SMugunthan V N cpdma_ctlr_int_ctrl(priv->dma, true); 922df828598SMugunthan V N cpsw_intr_enable(priv); 923df828598SMugunthan V N cpdma_ctlr_eoi(priv->dma); 924df828598SMugunthan V N } 925df828598SMugunthan V N #endif 926df828598SMugunthan V N 927df828598SMugunthan V N static const struct net_device_ops cpsw_netdev_ops = { 928df828598SMugunthan V N .ndo_open = cpsw_ndo_open, 929df828598SMugunthan V N .ndo_stop = cpsw_ndo_stop, 930df828598SMugunthan V N .ndo_start_xmit = cpsw_ndo_start_xmit, 931df828598SMugunthan V N .ndo_change_rx_flags = cpsw_ndo_change_rx_flags, 9322e5b38abSRichard Cochran .ndo_do_ioctl = cpsw_ndo_ioctl, 933df828598SMugunthan V N .ndo_validate_addr = eth_validate_addr, 9345c473ed2SDavid S. Miller .ndo_change_mtu = eth_change_mtu, 935df828598SMugunthan V N .ndo_tx_timeout = cpsw_ndo_tx_timeout, 936df828598SMugunthan V N .ndo_get_stats = cpsw_ndo_get_stats, 9375c50a856SMugunthan V N .ndo_set_rx_mode = cpsw_ndo_set_rx_mode, 938df828598SMugunthan V N #ifdef CONFIG_NET_POLL_CONTROLLER 939df828598SMugunthan V N .ndo_poll_controller = cpsw_ndo_poll_controller, 940df828598SMugunthan V N #endif 941df828598SMugunthan V N }; 942df828598SMugunthan V N 943df828598SMugunthan V N static void cpsw_get_drvinfo(struct net_device *ndev, 944df828598SMugunthan V N struct ethtool_drvinfo *info) 945df828598SMugunthan V N { 946df828598SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 947df828598SMugunthan V N strcpy(info->driver, "TI CPSW Driver v1.0"); 948df828598SMugunthan V N strcpy(info->version, "1.0"); 949df828598SMugunthan V N strcpy(info->bus_info, priv->pdev->name); 950df828598SMugunthan V N } 951df828598SMugunthan V N 952df828598SMugunthan V N static u32 cpsw_get_msglevel(struct net_device *ndev) 953df828598SMugunthan V N { 954df828598SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 955df828598SMugunthan V N return priv->msg_enable; 956df828598SMugunthan V N } 957df828598SMugunthan V N 958df828598SMugunthan V N static void cpsw_set_msglevel(struct net_device *ndev, u32 value) 959df828598SMugunthan V N { 960df828598SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 961df828598SMugunthan V N priv->msg_enable = value; 962df828598SMugunthan V N } 963df828598SMugunthan V N 9642e5b38abSRichard Cochran static int cpsw_get_ts_info(struct net_device *ndev, 9652e5b38abSRichard Cochran struct ethtool_ts_info *info) 9662e5b38abSRichard Cochran { 9672e5b38abSRichard Cochran #ifdef CONFIG_TI_CPTS 9682e5b38abSRichard Cochran struct cpsw_priv *priv = netdev_priv(ndev); 9692e5b38abSRichard Cochran 9702e5b38abSRichard Cochran info->so_timestamping = 9712e5b38abSRichard Cochran SOF_TIMESTAMPING_TX_HARDWARE | 9722e5b38abSRichard Cochran SOF_TIMESTAMPING_TX_SOFTWARE | 9732e5b38abSRichard Cochran SOF_TIMESTAMPING_RX_HARDWARE | 9742e5b38abSRichard Cochran SOF_TIMESTAMPING_RX_SOFTWARE | 9752e5b38abSRichard Cochran SOF_TIMESTAMPING_SOFTWARE | 9762e5b38abSRichard Cochran SOF_TIMESTAMPING_RAW_HARDWARE; 9772e5b38abSRichard Cochran info->phc_index = priv->cpts.phc_index; 9782e5b38abSRichard Cochran info->tx_types = 9792e5b38abSRichard Cochran (1 << HWTSTAMP_TX_OFF) | 9802e5b38abSRichard Cochran (1 << HWTSTAMP_TX_ON); 9812e5b38abSRichard Cochran info->rx_filters = 9822e5b38abSRichard Cochran (1 << HWTSTAMP_FILTER_NONE) | 9832e5b38abSRichard Cochran (1 << HWTSTAMP_FILTER_PTP_V2_EVENT); 9842e5b38abSRichard Cochran #else 9852e5b38abSRichard Cochran info->so_timestamping = 9862e5b38abSRichard Cochran SOF_TIMESTAMPING_TX_SOFTWARE | 9872e5b38abSRichard Cochran SOF_TIMESTAMPING_RX_SOFTWARE | 9882e5b38abSRichard Cochran SOF_TIMESTAMPING_SOFTWARE; 9892e5b38abSRichard Cochran info->phc_index = -1; 9902e5b38abSRichard Cochran info->tx_types = 0; 9912e5b38abSRichard Cochran info->rx_filters = 0; 9922e5b38abSRichard Cochran #endif 9932e5b38abSRichard Cochran return 0; 9942e5b38abSRichard Cochran } 9952e5b38abSRichard Cochran 996df828598SMugunthan V N static const struct ethtool_ops cpsw_ethtool_ops = { 997df828598SMugunthan V N .get_drvinfo = cpsw_get_drvinfo, 998df828598SMugunthan V N .get_msglevel = cpsw_get_msglevel, 999df828598SMugunthan V N .set_msglevel = cpsw_set_msglevel, 1000df828598SMugunthan V N .get_link = ethtool_op_get_link, 10012e5b38abSRichard Cochran .get_ts_info = cpsw_get_ts_info, 1002df828598SMugunthan V N }; 1003df828598SMugunthan V N 1004549985eeSRichard Cochran static void cpsw_slave_init(struct cpsw_slave *slave, struct cpsw_priv *priv, 1005549985eeSRichard Cochran u32 slave_reg_ofs, u32 sliver_reg_ofs) 1006df828598SMugunthan V N { 1007df828598SMugunthan V N void __iomem *regs = priv->regs; 1008df828598SMugunthan V N int slave_num = slave->slave_num; 1009df828598SMugunthan V N struct cpsw_slave_data *data = priv->data.slave_data + slave_num; 1010df828598SMugunthan V N 1011df828598SMugunthan V N slave->data = data; 1012549985eeSRichard Cochran slave->regs = regs + slave_reg_ofs; 1013549985eeSRichard Cochran slave->sliver = regs + sliver_reg_ofs; 1014df828598SMugunthan V N } 1015df828598SMugunthan V N 10162eb32b0aSMugunthan V N static int cpsw_probe_dt(struct cpsw_platform_data *data, 10172eb32b0aSMugunthan V N struct platform_device *pdev) 10182eb32b0aSMugunthan V N { 10192eb32b0aSMugunthan V N struct device_node *node = pdev->dev.of_node; 10202eb32b0aSMugunthan V N struct device_node *slave_node; 10212eb32b0aSMugunthan V N int i = 0, ret; 10222eb32b0aSMugunthan V N u32 prop; 10232eb32b0aSMugunthan V N 10242eb32b0aSMugunthan V N if (!node) 10252eb32b0aSMugunthan V N return -EINVAL; 10262eb32b0aSMugunthan V N 10272eb32b0aSMugunthan V N if (of_property_read_u32(node, "slaves", &prop)) { 10282eb32b0aSMugunthan V N pr_err("Missing slaves property in the DT.\n"); 10292eb32b0aSMugunthan V N return -EINVAL; 10302eb32b0aSMugunthan V N } 10312eb32b0aSMugunthan V N data->slaves = prop; 10322eb32b0aSMugunthan V N 103378ca0b28SRichard Cochran if (of_property_read_u32(node, "cpts_active_slave", &prop)) { 103478ca0b28SRichard Cochran pr_err("Missing cpts_active_slave property in the DT.\n"); 103578ca0b28SRichard Cochran ret = -EINVAL; 103678ca0b28SRichard Cochran goto error_ret; 103778ca0b28SRichard Cochran } 103878ca0b28SRichard Cochran data->cpts_active_slave = prop; 103978ca0b28SRichard Cochran 104000ab94eeSRichard Cochran if (of_property_read_u32(node, "cpts_clock_mult", &prop)) { 104100ab94eeSRichard Cochran pr_err("Missing cpts_clock_mult property in the DT.\n"); 104200ab94eeSRichard Cochran ret = -EINVAL; 104300ab94eeSRichard Cochran goto error_ret; 104400ab94eeSRichard Cochran } 104500ab94eeSRichard Cochran data->cpts_clock_mult = prop; 104600ab94eeSRichard Cochran 104700ab94eeSRichard Cochran if (of_property_read_u32(node, "cpts_clock_shift", &prop)) { 104800ab94eeSRichard Cochran pr_err("Missing cpts_clock_shift property in the DT.\n"); 104900ab94eeSRichard Cochran ret = -EINVAL; 105000ab94eeSRichard Cochran goto error_ret; 105100ab94eeSRichard Cochran } 105200ab94eeSRichard Cochran data->cpts_clock_shift = prop; 105300ab94eeSRichard Cochran 10542eb32b0aSMugunthan V N data->slave_data = kzalloc(sizeof(struct cpsw_slave_data) * 10552eb32b0aSMugunthan V N data->slaves, GFP_KERNEL); 10562eb32b0aSMugunthan V N if (!data->slave_data) { 10572eb32b0aSMugunthan V N pr_err("Could not allocate slave memory.\n"); 10582eb32b0aSMugunthan V N return -EINVAL; 10592eb32b0aSMugunthan V N } 10602eb32b0aSMugunthan V N 10612eb32b0aSMugunthan V N if (of_property_read_u32(node, "cpdma_channels", &prop)) { 10622eb32b0aSMugunthan V N pr_err("Missing cpdma_channels property in the DT.\n"); 10632eb32b0aSMugunthan V N ret = -EINVAL; 10642eb32b0aSMugunthan V N goto error_ret; 10652eb32b0aSMugunthan V N } 10662eb32b0aSMugunthan V N data->channels = prop; 10672eb32b0aSMugunthan V N 10682eb32b0aSMugunthan V N if (of_property_read_u32(node, "ale_entries", &prop)) { 10692eb32b0aSMugunthan V N pr_err("Missing ale_entries property in the DT.\n"); 10702eb32b0aSMugunthan V N ret = -EINVAL; 10712eb32b0aSMugunthan V N goto error_ret; 10722eb32b0aSMugunthan V N } 10732eb32b0aSMugunthan V N data->ale_entries = prop; 10742eb32b0aSMugunthan V N 10752eb32b0aSMugunthan V N if (of_property_read_u32(node, "bd_ram_size", &prop)) { 10762eb32b0aSMugunthan V N pr_err("Missing bd_ram_size property in the DT.\n"); 10772eb32b0aSMugunthan V N ret = -EINVAL; 10782eb32b0aSMugunthan V N goto error_ret; 10792eb32b0aSMugunthan V N } 10802eb32b0aSMugunthan V N data->bd_ram_size = prop; 10812eb32b0aSMugunthan V N 10822eb32b0aSMugunthan V N if (of_property_read_u32(node, "rx_descs", &prop)) { 10832eb32b0aSMugunthan V N pr_err("Missing rx_descs property in the DT.\n"); 10842eb32b0aSMugunthan V N ret = -EINVAL; 10852eb32b0aSMugunthan V N goto error_ret; 10862eb32b0aSMugunthan V N } 10872eb32b0aSMugunthan V N data->rx_descs = prop; 10882eb32b0aSMugunthan V N 10892eb32b0aSMugunthan V N if (of_property_read_u32(node, "mac_control", &prop)) { 10902eb32b0aSMugunthan V N pr_err("Missing mac_control property in the DT.\n"); 10912eb32b0aSMugunthan V N ret = -EINVAL; 10922eb32b0aSMugunthan V N goto error_ret; 10932eb32b0aSMugunthan V N } 10942eb32b0aSMugunthan V N data->mac_control = prop; 10952eb32b0aSMugunthan V N 10961fb19aa7SVaibhav Hiremath /* 10971fb19aa7SVaibhav Hiremath * Populate all the child nodes here... 10981fb19aa7SVaibhav Hiremath */ 10991fb19aa7SVaibhav Hiremath ret = of_platform_populate(node, NULL, NULL, &pdev->dev); 11001fb19aa7SVaibhav Hiremath /* We do not want to force this, as in some cases may not have child */ 11011fb19aa7SVaibhav Hiremath if (ret) 11021fb19aa7SVaibhav Hiremath pr_warn("Doesn't have any child node\n"); 11031fb19aa7SVaibhav Hiremath 1104549985eeSRichard Cochran for_each_node_by_name(slave_node, "slave") { 1105549985eeSRichard Cochran struct cpsw_slave_data *slave_data = data->slave_data + i; 1106549985eeSRichard Cochran const void *mac_addr = NULL; 1107549985eeSRichard Cochran u32 phyid; 1108549985eeSRichard Cochran int lenp; 1109549985eeSRichard Cochran const __be32 *parp; 1110549985eeSRichard Cochran struct device_node *mdio_node; 1111549985eeSRichard Cochran struct platform_device *mdio; 1112549985eeSRichard Cochran 1113549985eeSRichard Cochran parp = of_get_property(slave_node, "phy_id", &lenp); 1114549985eeSRichard Cochran if ((parp == NULL) && (lenp != (sizeof(void *) * 2))) { 1115549985eeSRichard Cochran pr_err("Missing slave[%d] phy_id property\n", i); 1116549985eeSRichard Cochran ret = -EINVAL; 1117549985eeSRichard Cochran goto error_ret; 1118549985eeSRichard Cochran } 1119549985eeSRichard Cochran mdio_node = of_find_node_by_phandle(be32_to_cpup(parp)); 1120549985eeSRichard Cochran phyid = be32_to_cpup(parp+1); 1121549985eeSRichard Cochran mdio = of_find_device_by_node(mdio_node); 1122549985eeSRichard Cochran snprintf(slave_data->phy_id, sizeof(slave_data->phy_id), 1123549985eeSRichard Cochran PHY_ID_FMT, mdio->name, phyid); 1124549985eeSRichard Cochran 1125549985eeSRichard Cochran mac_addr = of_get_mac_address(slave_node); 1126549985eeSRichard Cochran if (mac_addr) 1127549985eeSRichard Cochran memcpy(slave_data->mac_addr, mac_addr, ETH_ALEN); 1128549985eeSRichard Cochran 1129549985eeSRichard Cochran i++; 1130549985eeSRichard Cochran } 1131549985eeSRichard Cochran 11322eb32b0aSMugunthan V N return 0; 11332eb32b0aSMugunthan V N 11342eb32b0aSMugunthan V N error_ret: 11352eb32b0aSMugunthan V N kfree(data->slave_data); 11362eb32b0aSMugunthan V N return ret; 11372eb32b0aSMugunthan V N } 11382eb32b0aSMugunthan V N 1139df828598SMugunthan V N static int __devinit cpsw_probe(struct platform_device *pdev) 1140df828598SMugunthan V N { 1141df828598SMugunthan V N struct cpsw_platform_data *data = pdev->dev.platform_data; 1142df828598SMugunthan V N struct net_device *ndev; 1143df828598SMugunthan V N struct cpsw_priv *priv; 1144df828598SMugunthan V N struct cpdma_params dma_params; 1145df828598SMugunthan V N struct cpsw_ale_params ale_params; 1146549985eeSRichard Cochran void __iomem *ss_regs, *wr_regs; 1147df828598SMugunthan V N struct resource *res; 1148549985eeSRichard Cochran u32 slave_offset, sliver_offset, slave_size; 1149df828598SMugunthan V N int ret = 0, i, k = 0; 1150df828598SMugunthan V N 1151df828598SMugunthan V N ndev = alloc_etherdev(sizeof(struct cpsw_priv)); 1152df828598SMugunthan V N if (!ndev) { 1153df828598SMugunthan V N pr_err("error allocating net_device\n"); 1154df828598SMugunthan V N return -ENOMEM; 1155df828598SMugunthan V N } 1156df828598SMugunthan V N 1157df828598SMugunthan V N platform_set_drvdata(pdev, ndev); 1158df828598SMugunthan V N priv = netdev_priv(ndev); 1159df828598SMugunthan V N spin_lock_init(&priv->lock); 1160df828598SMugunthan V N priv->pdev = pdev; 1161df828598SMugunthan V N priv->ndev = ndev; 1162df828598SMugunthan V N priv->dev = &ndev->dev; 1163df828598SMugunthan V N priv->msg_enable = netif_msg_init(debug_level, CPSW_DEBUG); 1164df828598SMugunthan V N priv->rx_packet_max = max(rx_packet_max, 128); 1165df828598SMugunthan V N 11661fb19aa7SVaibhav Hiremath /* 11671fb19aa7SVaibhav Hiremath * This may be required here for child devices. 11681fb19aa7SVaibhav Hiremath */ 11691fb19aa7SVaibhav Hiremath pm_runtime_enable(&pdev->dev); 11701fb19aa7SVaibhav Hiremath 11712eb32b0aSMugunthan V N if (cpsw_probe_dt(&priv->data, pdev)) { 11722eb32b0aSMugunthan V N pr_err("cpsw: platform data missing\n"); 11732eb32b0aSMugunthan V N ret = -ENODEV; 11742eb32b0aSMugunthan V N goto clean_ndev_ret; 11752eb32b0aSMugunthan V N } 11762eb32b0aSMugunthan V N data = &priv->data; 11772eb32b0aSMugunthan V N 1178df828598SMugunthan V N if (is_valid_ether_addr(data->slave_data[0].mac_addr)) { 1179df828598SMugunthan V N memcpy(priv->mac_addr, data->slave_data[0].mac_addr, ETH_ALEN); 1180df828598SMugunthan V N pr_info("Detected MACID = %pM", priv->mac_addr); 1181df828598SMugunthan V N } else { 11827efd26d0SJoe Perches eth_random_addr(priv->mac_addr); 1183df828598SMugunthan V N pr_info("Random MACID = %pM", priv->mac_addr); 1184df828598SMugunthan V N } 1185df828598SMugunthan V N 1186df828598SMugunthan V N memcpy(ndev->dev_addr, priv->mac_addr, ETH_ALEN); 1187df828598SMugunthan V N 1188df828598SMugunthan V N priv->slaves = kzalloc(sizeof(struct cpsw_slave) * data->slaves, 1189df828598SMugunthan V N GFP_KERNEL); 1190df828598SMugunthan V N if (!priv->slaves) { 1191df828598SMugunthan V N ret = -EBUSY; 1192df828598SMugunthan V N goto clean_ndev_ret; 1193df828598SMugunthan V N } 1194df828598SMugunthan V N for (i = 0; i < data->slaves; i++) 1195df828598SMugunthan V N priv->slaves[i].slave_num = i; 1196df828598SMugunthan V N 1197f150bd7fSMugunthan V N priv->clk = clk_get(&pdev->dev, "fck"); 1198df828598SMugunthan V N if (IS_ERR(priv->clk)) { 1199f150bd7fSMugunthan V N dev_err(&pdev->dev, "fck is not found\n"); 1200f150bd7fSMugunthan V N ret = -ENODEV; 1201f150bd7fSMugunthan V N goto clean_slave_ret; 1202df828598SMugunthan V N } 1203df828598SMugunthan V N 1204df828598SMugunthan V N priv->cpsw_res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1205df828598SMugunthan V N if (!priv->cpsw_res) { 1206df828598SMugunthan V N dev_err(priv->dev, "error getting i/o resource\n"); 1207df828598SMugunthan V N ret = -ENOENT; 1208df828598SMugunthan V N goto clean_clk_ret; 1209df828598SMugunthan V N } 1210df828598SMugunthan V N if (!request_mem_region(priv->cpsw_res->start, 1211df828598SMugunthan V N resource_size(priv->cpsw_res), ndev->name)) { 1212df828598SMugunthan V N dev_err(priv->dev, "failed request i/o region\n"); 1213df828598SMugunthan V N ret = -ENXIO; 1214df828598SMugunthan V N goto clean_clk_ret; 1215df828598SMugunthan V N } 1216549985eeSRichard Cochran ss_regs = ioremap(priv->cpsw_res->start, resource_size(priv->cpsw_res)); 1217549985eeSRichard Cochran if (!ss_regs) { 1218df828598SMugunthan V N dev_err(priv->dev, "unable to map i/o region\n"); 1219df828598SMugunthan V N goto clean_cpsw_iores_ret; 1220df828598SMugunthan V N } 1221549985eeSRichard Cochran priv->regs = ss_regs; 1222549985eeSRichard Cochran priv->version = __raw_readl(&priv->regs->id_ver); 1223549985eeSRichard Cochran priv->host_port = HOST_PORT_NUM; 1224df828598SMugunthan V N 1225a65dd5b2SRichard Cochran priv->cpsw_wr_res = platform_get_resource(pdev, IORESOURCE_MEM, 1); 1226a65dd5b2SRichard Cochran if (!priv->cpsw_wr_res) { 1227df828598SMugunthan V N dev_err(priv->dev, "error getting i/o resource\n"); 1228df828598SMugunthan V N ret = -ENOENT; 12295250c969SRichard Cochran goto clean_iomap_ret; 1230df828598SMugunthan V N } 1231a65dd5b2SRichard Cochran if (!request_mem_region(priv->cpsw_wr_res->start, 1232a65dd5b2SRichard Cochran resource_size(priv->cpsw_wr_res), ndev->name)) { 1233df828598SMugunthan V N dev_err(priv->dev, "failed request i/o region\n"); 1234df828598SMugunthan V N ret = -ENXIO; 12355250c969SRichard Cochran goto clean_iomap_ret; 1236df828598SMugunthan V N } 1237549985eeSRichard Cochran wr_regs = ioremap(priv->cpsw_wr_res->start, 1238a65dd5b2SRichard Cochran resource_size(priv->cpsw_wr_res)); 1239549985eeSRichard Cochran if (!wr_regs) { 1240df828598SMugunthan V N dev_err(priv->dev, "unable to map i/o region\n"); 1241a65dd5b2SRichard Cochran goto clean_cpsw_wr_iores_ret; 1242df828598SMugunthan V N } 1243549985eeSRichard Cochran priv->wr_regs = wr_regs; 1244df828598SMugunthan V N 1245df828598SMugunthan V N memset(&dma_params, 0, sizeof(dma_params)); 1246549985eeSRichard Cochran memset(&ale_params, 0, sizeof(ale_params)); 1247549985eeSRichard Cochran 1248549985eeSRichard Cochran switch (priv->version) { 1249549985eeSRichard Cochran case CPSW_VERSION_1: 1250549985eeSRichard Cochran priv->host_port_regs = ss_regs + CPSW1_HOST_PORT_OFFSET; 1251549985eeSRichard Cochran priv->cpts.reg = ss_regs + CPSW1_CPTS_OFFSET; 1252549985eeSRichard Cochran dma_params.dmaregs = ss_regs + CPSW1_CPDMA_OFFSET; 1253549985eeSRichard Cochran dma_params.txhdp = ss_regs + CPSW1_STATERAM_OFFSET; 1254549985eeSRichard Cochran ale_params.ale_regs = ss_regs + CPSW1_ALE_OFFSET; 1255549985eeSRichard Cochran slave_offset = CPSW1_SLAVE_OFFSET; 1256549985eeSRichard Cochran slave_size = CPSW1_SLAVE_SIZE; 1257549985eeSRichard Cochran sliver_offset = CPSW1_SLIVER_OFFSET; 1258549985eeSRichard Cochran dma_params.desc_mem_phys = 0; 1259549985eeSRichard Cochran break; 1260549985eeSRichard Cochran case CPSW_VERSION_2: 1261549985eeSRichard Cochran priv->host_port_regs = ss_regs + CPSW2_HOST_PORT_OFFSET; 1262549985eeSRichard Cochran priv->cpts.reg = ss_regs + CPSW2_CPTS_OFFSET; 1263549985eeSRichard Cochran dma_params.dmaregs = ss_regs + CPSW2_CPDMA_OFFSET; 1264549985eeSRichard Cochran dma_params.txhdp = ss_regs + CPSW2_STATERAM_OFFSET; 1265549985eeSRichard Cochran ale_params.ale_regs = ss_regs + CPSW2_ALE_OFFSET; 1266549985eeSRichard Cochran slave_offset = CPSW2_SLAVE_OFFSET; 1267549985eeSRichard Cochran slave_size = CPSW2_SLAVE_SIZE; 1268549985eeSRichard Cochran sliver_offset = CPSW2_SLIVER_OFFSET; 1269549985eeSRichard Cochran dma_params.desc_mem_phys = 1270549985eeSRichard Cochran (u32 __force) priv->cpsw_res->start + CPSW2_BD_OFFSET; 1271549985eeSRichard Cochran break; 1272549985eeSRichard Cochran default: 1273549985eeSRichard Cochran dev_err(priv->dev, "unknown version 0x%08x\n", priv->version); 1274549985eeSRichard Cochran ret = -ENODEV; 1275549985eeSRichard Cochran goto clean_cpsw_wr_iores_ret; 1276549985eeSRichard Cochran } 1277549985eeSRichard Cochran for (i = 0; i < priv->data.slaves; i++) { 1278549985eeSRichard Cochran struct cpsw_slave *slave = &priv->slaves[i]; 1279549985eeSRichard Cochran cpsw_slave_init(slave, priv, slave_offset, sliver_offset); 1280549985eeSRichard Cochran slave_offset += slave_size; 1281549985eeSRichard Cochran sliver_offset += SLIVER_SIZE; 1282549985eeSRichard Cochran } 1283549985eeSRichard Cochran 1284df828598SMugunthan V N dma_params.dev = &pdev->dev; 1285549985eeSRichard Cochran dma_params.rxthresh = dma_params.dmaregs + CPDMA_RXTHRESH; 1286549985eeSRichard Cochran dma_params.rxfree = dma_params.dmaregs + CPDMA_RXFREE; 1287549985eeSRichard Cochran dma_params.rxhdp = dma_params.txhdp + CPDMA_RXHDP; 1288549985eeSRichard Cochran dma_params.txcp = dma_params.txhdp + CPDMA_TXCP; 1289549985eeSRichard Cochran dma_params.rxcp = dma_params.txhdp + CPDMA_RXCP; 1290df828598SMugunthan V N 1291df828598SMugunthan V N dma_params.num_chan = data->channels; 1292df828598SMugunthan V N dma_params.has_soft_reset = true; 1293df828598SMugunthan V N dma_params.min_packet_size = CPSW_MIN_PACKET_SIZE; 1294df828598SMugunthan V N dma_params.desc_mem_size = data->bd_ram_size; 1295df828598SMugunthan V N dma_params.desc_align = 16; 1296df828598SMugunthan V N dma_params.has_ext_regs = true; 1297549985eeSRichard Cochran dma_params.desc_hw_addr = dma_params.desc_mem_phys; 1298df828598SMugunthan V N 1299df828598SMugunthan V N priv->dma = cpdma_ctlr_create(&dma_params); 1300df828598SMugunthan V N if (!priv->dma) { 1301df828598SMugunthan V N dev_err(priv->dev, "error initializing dma\n"); 1302df828598SMugunthan V N ret = -ENOMEM; 13035250c969SRichard Cochran goto clean_wr_iomap_ret; 1304df828598SMugunthan V N } 1305df828598SMugunthan V N 1306df828598SMugunthan V N priv->txch = cpdma_chan_create(priv->dma, tx_chan_num(0), 1307df828598SMugunthan V N cpsw_tx_handler); 1308df828598SMugunthan V N priv->rxch = cpdma_chan_create(priv->dma, rx_chan_num(0), 1309df828598SMugunthan V N cpsw_rx_handler); 1310df828598SMugunthan V N 1311df828598SMugunthan V N if (WARN_ON(!priv->txch || !priv->rxch)) { 1312df828598SMugunthan V N dev_err(priv->dev, "error initializing dma channels\n"); 1313df828598SMugunthan V N ret = -ENOMEM; 1314df828598SMugunthan V N goto clean_dma_ret; 1315df828598SMugunthan V N } 1316df828598SMugunthan V N 1317df828598SMugunthan V N ale_params.dev = &ndev->dev; 1318df828598SMugunthan V N ale_params.ale_ageout = ale_ageout; 1319df828598SMugunthan V N ale_params.ale_entries = data->ale_entries; 1320df828598SMugunthan V N ale_params.ale_ports = data->slaves; 1321df828598SMugunthan V N 1322df828598SMugunthan V N priv->ale = cpsw_ale_create(&ale_params); 1323df828598SMugunthan V N if (!priv->ale) { 1324df828598SMugunthan V N dev_err(priv->dev, "error initializing ale engine\n"); 1325df828598SMugunthan V N ret = -ENODEV; 1326df828598SMugunthan V N goto clean_dma_ret; 1327df828598SMugunthan V N } 1328df828598SMugunthan V N 1329df828598SMugunthan V N ndev->irq = platform_get_irq(pdev, 0); 1330df828598SMugunthan V N if (ndev->irq < 0) { 1331df828598SMugunthan V N dev_err(priv->dev, "error getting irq resource\n"); 1332df828598SMugunthan V N ret = -ENOENT; 1333df828598SMugunthan V N goto clean_ale_ret; 1334df828598SMugunthan V N } 1335df828598SMugunthan V N 1336df828598SMugunthan V N while ((res = platform_get_resource(priv->pdev, IORESOURCE_IRQ, k))) { 1337df828598SMugunthan V N for (i = res->start; i <= res->end; i++) { 1338df828598SMugunthan V N if (request_irq(i, cpsw_interrupt, IRQF_DISABLED, 1339df828598SMugunthan V N dev_name(&pdev->dev), priv)) { 1340df828598SMugunthan V N dev_err(priv->dev, "error attaching irq\n"); 1341df828598SMugunthan V N goto clean_ale_ret; 1342df828598SMugunthan V N } 1343df828598SMugunthan V N priv->irqs_table[k] = i; 1344df828598SMugunthan V N priv->num_irqs = k; 1345df828598SMugunthan V N } 1346df828598SMugunthan V N k++; 1347df828598SMugunthan V N } 1348df828598SMugunthan V N 1349df828598SMugunthan V N ndev->flags |= IFF_ALLMULTI; /* see cpsw_ndo_change_rx_flags() */ 1350df828598SMugunthan V N 1351df828598SMugunthan V N ndev->netdev_ops = &cpsw_netdev_ops; 1352df828598SMugunthan V N SET_ETHTOOL_OPS(ndev, &cpsw_ethtool_ops); 1353df828598SMugunthan V N netif_napi_add(ndev, &priv->napi, cpsw_poll, CPSW_POLL_WEIGHT); 1354df828598SMugunthan V N 1355df828598SMugunthan V N /* register the network device */ 1356df828598SMugunthan V N SET_NETDEV_DEV(ndev, &pdev->dev); 1357df828598SMugunthan V N ret = register_netdev(ndev); 1358df828598SMugunthan V N if (ret) { 1359df828598SMugunthan V N dev_err(priv->dev, "error registering net device\n"); 1360df828598SMugunthan V N ret = -ENODEV; 1361df828598SMugunthan V N goto clean_irq_ret; 1362df828598SMugunthan V N } 1363df828598SMugunthan V N 13642e5b38abSRichard Cochran if (cpts_register(&pdev->dev, &priv->cpts, 13652e5b38abSRichard Cochran data->cpts_clock_mult, data->cpts_clock_shift)) 13662e5b38abSRichard Cochran dev_err(priv->dev, "error registering cpts device\n"); 13672e5b38abSRichard Cochran 1368df828598SMugunthan V N cpsw_notice(priv, probe, "initialized device (regs %x, irq %d)\n", 1369df828598SMugunthan V N priv->cpsw_res->start, ndev->irq); 1370df828598SMugunthan V N 1371df828598SMugunthan V N return 0; 1372df828598SMugunthan V N 1373df828598SMugunthan V N clean_irq_ret: 1374df828598SMugunthan V N free_irq(ndev->irq, priv); 1375df828598SMugunthan V N clean_ale_ret: 1376df828598SMugunthan V N cpsw_ale_destroy(priv->ale); 1377df828598SMugunthan V N clean_dma_ret: 1378df828598SMugunthan V N cpdma_chan_destroy(priv->txch); 1379df828598SMugunthan V N cpdma_chan_destroy(priv->rxch); 1380df828598SMugunthan V N cpdma_ctlr_destroy(priv->dma); 13815250c969SRichard Cochran clean_wr_iomap_ret: 13825250c969SRichard Cochran iounmap(priv->wr_regs); 1383a65dd5b2SRichard Cochran clean_cpsw_wr_iores_ret: 1384a65dd5b2SRichard Cochran release_mem_region(priv->cpsw_wr_res->start, 1385a65dd5b2SRichard Cochran resource_size(priv->cpsw_wr_res)); 13865250c969SRichard Cochran clean_iomap_ret: 13875250c969SRichard Cochran iounmap(priv->regs); 1388df828598SMugunthan V N clean_cpsw_iores_ret: 1389df828598SMugunthan V N release_mem_region(priv->cpsw_res->start, 1390df828598SMugunthan V N resource_size(priv->cpsw_res)); 1391df828598SMugunthan V N clean_clk_ret: 1392df828598SMugunthan V N clk_put(priv->clk); 1393f150bd7fSMugunthan V N clean_slave_ret: 1394f150bd7fSMugunthan V N pm_runtime_disable(&pdev->dev); 1395df828598SMugunthan V N kfree(priv->slaves); 1396df828598SMugunthan V N clean_ndev_ret: 1397df828598SMugunthan V N free_netdev(ndev); 1398df828598SMugunthan V N return ret; 1399df828598SMugunthan V N } 1400df828598SMugunthan V N 1401df828598SMugunthan V N static int __devexit cpsw_remove(struct platform_device *pdev) 1402df828598SMugunthan V N { 1403df828598SMugunthan V N struct net_device *ndev = platform_get_drvdata(pdev); 1404df828598SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 1405df828598SMugunthan V N 1406df828598SMugunthan V N pr_info("removing device"); 1407df828598SMugunthan V N platform_set_drvdata(pdev, NULL); 1408df828598SMugunthan V N 14092e5b38abSRichard Cochran cpts_unregister(&priv->cpts); 1410df828598SMugunthan V N free_irq(ndev->irq, priv); 1411df828598SMugunthan V N cpsw_ale_destroy(priv->ale); 1412df828598SMugunthan V N cpdma_chan_destroy(priv->txch); 1413df828598SMugunthan V N cpdma_chan_destroy(priv->rxch); 1414df828598SMugunthan V N cpdma_ctlr_destroy(priv->dma); 1415df828598SMugunthan V N iounmap(priv->regs); 1416df828598SMugunthan V N release_mem_region(priv->cpsw_res->start, 1417df828598SMugunthan V N resource_size(priv->cpsw_res)); 14185250c969SRichard Cochran iounmap(priv->wr_regs); 1419a65dd5b2SRichard Cochran release_mem_region(priv->cpsw_wr_res->start, 1420a65dd5b2SRichard Cochran resource_size(priv->cpsw_wr_res)); 1421f150bd7fSMugunthan V N pm_runtime_disable(&pdev->dev); 1422df828598SMugunthan V N clk_put(priv->clk); 1423df828598SMugunthan V N kfree(priv->slaves); 1424df828598SMugunthan V N free_netdev(ndev); 1425df828598SMugunthan V N 1426df828598SMugunthan V N return 0; 1427df828598SMugunthan V N } 1428df828598SMugunthan V N 1429df828598SMugunthan V N static int cpsw_suspend(struct device *dev) 1430df828598SMugunthan V N { 1431df828598SMugunthan V N struct platform_device *pdev = to_platform_device(dev); 1432df828598SMugunthan V N struct net_device *ndev = platform_get_drvdata(pdev); 1433df828598SMugunthan V N 1434df828598SMugunthan V N if (netif_running(ndev)) 1435df828598SMugunthan V N cpsw_ndo_stop(ndev); 1436f150bd7fSMugunthan V N pm_runtime_put_sync(&pdev->dev); 1437f150bd7fSMugunthan V N 1438df828598SMugunthan V N return 0; 1439df828598SMugunthan V N } 1440df828598SMugunthan V N 1441df828598SMugunthan V N static int cpsw_resume(struct device *dev) 1442df828598SMugunthan V N { 1443df828598SMugunthan V N struct platform_device *pdev = to_platform_device(dev); 1444df828598SMugunthan V N struct net_device *ndev = platform_get_drvdata(pdev); 1445df828598SMugunthan V N 1446f150bd7fSMugunthan V N pm_runtime_get_sync(&pdev->dev); 1447df828598SMugunthan V N if (netif_running(ndev)) 1448df828598SMugunthan V N cpsw_ndo_open(ndev); 1449df828598SMugunthan V N return 0; 1450df828598SMugunthan V N } 1451df828598SMugunthan V N 1452df828598SMugunthan V N static const struct dev_pm_ops cpsw_pm_ops = { 1453df828598SMugunthan V N .suspend = cpsw_suspend, 1454df828598SMugunthan V N .resume = cpsw_resume, 1455df828598SMugunthan V N }; 1456df828598SMugunthan V N 14572eb32b0aSMugunthan V N static const struct of_device_id cpsw_of_mtable[] = { 14582eb32b0aSMugunthan V N { .compatible = "ti,cpsw", }, 14592eb32b0aSMugunthan V N { /* sentinel */ }, 14602eb32b0aSMugunthan V N }; 14612eb32b0aSMugunthan V N 1462df828598SMugunthan V N static struct platform_driver cpsw_driver = { 1463df828598SMugunthan V N .driver = { 1464df828598SMugunthan V N .name = "cpsw", 1465df828598SMugunthan V N .owner = THIS_MODULE, 1466df828598SMugunthan V N .pm = &cpsw_pm_ops, 14672eb32b0aSMugunthan V N .of_match_table = of_match_ptr(cpsw_of_mtable), 1468df828598SMugunthan V N }, 1469df828598SMugunthan V N .probe = cpsw_probe, 1470df828598SMugunthan V N .remove = __devexit_p(cpsw_remove), 1471df828598SMugunthan V N }; 1472df828598SMugunthan V N 1473df828598SMugunthan V N static int __init cpsw_init(void) 1474df828598SMugunthan V N { 1475df828598SMugunthan V N return platform_driver_register(&cpsw_driver); 1476df828598SMugunthan V N } 1477df828598SMugunthan V N late_initcall(cpsw_init); 1478df828598SMugunthan V N 1479df828598SMugunthan V N static void __exit cpsw_exit(void) 1480df828598SMugunthan V N { 1481df828598SMugunthan V N platform_driver_unregister(&cpsw_driver); 1482df828598SMugunthan V N } 1483df828598SMugunthan V N module_exit(cpsw_exit); 1484df828598SMugunthan V N 1485df828598SMugunthan V N MODULE_LICENSE("GPL"); 1486df828598SMugunthan V N MODULE_AUTHOR("Cyril Chemparathy <cyril@ti.com>"); 1487df828598SMugunthan V N MODULE_AUTHOR("Mugunthan V N <mugunthanvnm@ti.com>"); 1488df828598SMugunthan V N MODULE_DESCRIPTION("TI CPSW Ethernet driver"); 1489