1df828598SMugunthan V N /* 2df828598SMugunthan V N * Texas Instruments Ethernet Switch Driver 3df828598SMugunthan V N * 4df828598SMugunthan V N * Copyright (C) 2012 Texas Instruments 5df828598SMugunthan V N * 6df828598SMugunthan V N * This program is free software; you can redistribute it and/or 7df828598SMugunthan V N * modify it under the terms of the GNU General Public License as 8df828598SMugunthan V N * published by the Free Software Foundation version 2. 9df828598SMugunthan V N * 10df828598SMugunthan V N * This program is distributed "as is" WITHOUT ANY WARRANTY of any 11df828598SMugunthan V N * kind, whether express or implied; without even the implied warranty 12df828598SMugunthan V N * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13df828598SMugunthan V N * GNU General Public License for more details. 14df828598SMugunthan V N */ 15df828598SMugunthan V N 16df828598SMugunthan V N #include <linux/kernel.h> 17df828598SMugunthan V N #include <linux/io.h> 18df828598SMugunthan V N #include <linux/clk.h> 19df828598SMugunthan V N #include <linux/timer.h> 20df828598SMugunthan V N #include <linux/module.h> 21df828598SMugunthan V N #include <linux/platform_device.h> 22df828598SMugunthan V N #include <linux/irqreturn.h> 23df828598SMugunthan V N #include <linux/interrupt.h> 24df828598SMugunthan V N #include <linux/if_ether.h> 25df828598SMugunthan V N #include <linux/etherdevice.h> 26df828598SMugunthan V N #include <linux/netdevice.h> 272e5b38abSRichard Cochran #include <linux/net_tstamp.h> 28df828598SMugunthan V N #include <linux/phy.h> 29df828598SMugunthan V N #include <linux/workqueue.h> 30df828598SMugunthan V N #include <linux/delay.h> 31f150bd7fSMugunthan V N #include <linux/pm_runtime.h> 321d147ccbSMugunthan V N #include <linux/gpio.h> 332eb32b0aSMugunthan V N #include <linux/of.h> 349e42f715SHeiko Schocher #include <linux/of_mdio.h> 352eb32b0aSMugunthan V N #include <linux/of_net.h> 362eb32b0aSMugunthan V N #include <linux/of_device.h> 373b72c2feSMugunthan V N #include <linux/if_vlan.h> 38df828598SMugunthan V N 39739683b4SMugunthan V N #include <linux/pinctrl/consumer.h> 40df828598SMugunthan V N 41dbe34724SMugunthan V N #include "cpsw.h" 42df828598SMugunthan V N #include "cpsw_ale.h" 432e5b38abSRichard Cochran #include "cpts.h" 44df828598SMugunthan V N #include "davinci_cpdma.h" 45df828598SMugunthan V N 46df828598SMugunthan V N #define CPSW_DEBUG (NETIF_MSG_HW | NETIF_MSG_WOL | \ 47df828598SMugunthan V N NETIF_MSG_DRV | NETIF_MSG_LINK | \ 48df828598SMugunthan V N NETIF_MSG_IFUP | NETIF_MSG_INTR | \ 49df828598SMugunthan V N NETIF_MSG_PROBE | NETIF_MSG_TIMER | \ 50df828598SMugunthan V N NETIF_MSG_IFDOWN | NETIF_MSG_RX_ERR | \ 51df828598SMugunthan V N NETIF_MSG_TX_ERR | NETIF_MSG_TX_DONE | \ 52df828598SMugunthan V N NETIF_MSG_PKTDATA | NETIF_MSG_TX_QUEUED | \ 53df828598SMugunthan V N NETIF_MSG_RX_STATUS) 54df828598SMugunthan V N 55df828598SMugunthan V N #define cpsw_info(priv, type, format, ...) \ 56df828598SMugunthan V N do { \ 57df828598SMugunthan V N if (netif_msg_##type(priv) && net_ratelimit()) \ 58df828598SMugunthan V N dev_info(priv->dev, format, ## __VA_ARGS__); \ 59df828598SMugunthan V N } while (0) 60df828598SMugunthan V N 61df828598SMugunthan V N #define cpsw_err(priv, type, format, ...) \ 62df828598SMugunthan V N do { \ 63df828598SMugunthan V N if (netif_msg_##type(priv) && net_ratelimit()) \ 64df828598SMugunthan V N dev_err(priv->dev, format, ## __VA_ARGS__); \ 65df828598SMugunthan V N } while (0) 66df828598SMugunthan V N 67df828598SMugunthan V N #define cpsw_dbg(priv, type, format, ...) \ 68df828598SMugunthan V N do { \ 69df828598SMugunthan V N if (netif_msg_##type(priv) && net_ratelimit()) \ 70df828598SMugunthan V N dev_dbg(priv->dev, format, ## __VA_ARGS__); \ 71df828598SMugunthan V N } while (0) 72df828598SMugunthan V N 73df828598SMugunthan V N #define cpsw_notice(priv, type, format, ...) \ 74df828598SMugunthan V N do { \ 75df828598SMugunthan V N if (netif_msg_##type(priv) && net_ratelimit()) \ 76df828598SMugunthan V N dev_notice(priv->dev, format, ## __VA_ARGS__); \ 77df828598SMugunthan V N } while (0) 78df828598SMugunthan V N 795c50a856SMugunthan V N #define ALE_ALL_PORTS 0x7 805c50a856SMugunthan V N 81df828598SMugunthan V N #define CPSW_MAJOR_VERSION(reg) (reg >> 8 & 0x7) 82df828598SMugunthan V N #define CPSW_MINOR_VERSION(reg) (reg & 0xff) 83df828598SMugunthan V N #define CPSW_RTL_VERSION(reg) ((reg >> 11) & 0x1f) 84df828598SMugunthan V N 85e90cfac6SRichard Cochran #define CPSW_VERSION_1 0x19010a 86e90cfac6SRichard Cochran #define CPSW_VERSION_2 0x19010c 87c193f365SMugunthan V N #define CPSW_VERSION_3 0x19010f 88926489beSMugunthan V N #define CPSW_VERSION_4 0x190112 89549985eeSRichard Cochran 90549985eeSRichard Cochran #define HOST_PORT_NUM 0 91549985eeSRichard Cochran #define SLIVER_SIZE 0x40 92549985eeSRichard Cochran 93549985eeSRichard Cochran #define CPSW1_HOST_PORT_OFFSET 0x028 94549985eeSRichard Cochran #define CPSW1_SLAVE_OFFSET 0x050 95549985eeSRichard Cochran #define CPSW1_SLAVE_SIZE 0x040 96549985eeSRichard Cochran #define CPSW1_CPDMA_OFFSET 0x100 97549985eeSRichard Cochran #define CPSW1_STATERAM_OFFSET 0x200 98d9718546SMugunthan V N #define CPSW1_HW_STATS 0x400 99549985eeSRichard Cochran #define CPSW1_CPTS_OFFSET 0x500 100549985eeSRichard Cochran #define CPSW1_ALE_OFFSET 0x600 101549985eeSRichard Cochran #define CPSW1_SLIVER_OFFSET 0x700 102549985eeSRichard Cochran 103549985eeSRichard Cochran #define CPSW2_HOST_PORT_OFFSET 0x108 104549985eeSRichard Cochran #define CPSW2_SLAVE_OFFSET 0x200 105549985eeSRichard Cochran #define CPSW2_SLAVE_SIZE 0x100 106549985eeSRichard Cochran #define CPSW2_CPDMA_OFFSET 0x800 107d9718546SMugunthan V N #define CPSW2_HW_STATS 0x900 108549985eeSRichard Cochran #define CPSW2_STATERAM_OFFSET 0xa00 109549985eeSRichard Cochran #define CPSW2_CPTS_OFFSET 0xc00 110549985eeSRichard Cochran #define CPSW2_ALE_OFFSET 0xd00 111549985eeSRichard Cochran #define CPSW2_SLIVER_OFFSET 0xd80 112549985eeSRichard Cochran #define CPSW2_BD_OFFSET 0x2000 113549985eeSRichard Cochran 114df828598SMugunthan V N #define CPDMA_RXTHRESH 0x0c0 115df828598SMugunthan V N #define CPDMA_RXFREE 0x0e0 116df828598SMugunthan V N #define CPDMA_TXHDP 0x00 117df828598SMugunthan V N #define CPDMA_RXHDP 0x20 118df828598SMugunthan V N #define CPDMA_TXCP 0x40 119df828598SMugunthan V N #define CPDMA_RXCP 0x60 120df828598SMugunthan V N 121df828598SMugunthan V N #define CPSW_POLL_WEIGHT 64 122df828598SMugunthan V N #define CPSW_MIN_PACKET_SIZE 60 123df828598SMugunthan V N #define CPSW_MAX_PACKET_SIZE (1500 + 14 + 4 + 4) 124df828598SMugunthan V N 125df828598SMugunthan V N #define RX_PRIORITY_MAPPING 0x76543210 126df828598SMugunthan V N #define TX_PRIORITY_MAPPING 0x33221100 127df828598SMugunthan V N #define CPDMA_TX_PRIORITY_MAP 0x76543210 128df828598SMugunthan V N 1293b72c2feSMugunthan V N #define CPSW_VLAN_AWARE BIT(1) 1303b72c2feSMugunthan V N #define CPSW_ALE_VLAN_AWARE 1 1313b72c2feSMugunthan V N 13235717d8dSJohn Ogness #define CPSW_FIFO_NORMAL_MODE (0 << 16) 13335717d8dSJohn Ogness #define CPSW_FIFO_DUAL_MAC_MODE (1 << 16) 13435717d8dSJohn Ogness #define CPSW_FIFO_RATE_LIMIT_MODE (2 << 16) 135d9ba8f9eSMugunthan V N 136ff5b8ef2SMugunthan V N #define CPSW_INTPACEEN (0x3f << 16) 137ff5b8ef2SMugunthan V N #define CPSW_INTPRESCALE_MASK (0x7FF << 0) 138ff5b8ef2SMugunthan V N #define CPSW_CMINTMAX_CNT 63 139ff5b8ef2SMugunthan V N #define CPSW_CMINTMIN_CNT 2 140ff5b8ef2SMugunthan V N #define CPSW_CMINTMAX_INTVL (1000 / CPSW_CMINTMIN_CNT) 141ff5b8ef2SMugunthan V N #define CPSW_CMINTMIN_INTVL ((1000 / CPSW_CMINTMAX_CNT) + 1) 142ff5b8ef2SMugunthan V N 143d3bb9c58SMugunthan V N #define cpsw_slave_index(priv) \ 144d3bb9c58SMugunthan V N ((priv->data.dual_emac) ? priv->emac_port : \ 145d3bb9c58SMugunthan V N priv->data.active_slave) 146d3bb9c58SMugunthan V N 147df828598SMugunthan V N static int debug_level; 148df828598SMugunthan V N module_param(debug_level, int, 0); 149df828598SMugunthan V N MODULE_PARM_DESC(debug_level, "cpsw debug level (NETIF_MSG bits)"); 150df828598SMugunthan V N 151df828598SMugunthan V N static int ale_ageout = 10; 152df828598SMugunthan V N module_param(ale_ageout, int, 0); 153df828598SMugunthan V N MODULE_PARM_DESC(ale_ageout, "cpsw ale ageout interval (seconds)"); 154df828598SMugunthan V N 155df828598SMugunthan V N static int rx_packet_max = CPSW_MAX_PACKET_SIZE; 156df828598SMugunthan V N module_param(rx_packet_max, int, 0); 157df828598SMugunthan V N MODULE_PARM_DESC(rx_packet_max, "maximum receive packet size (bytes)"); 158df828598SMugunthan V N 159996a5c27SRichard Cochran struct cpsw_wr_regs { 160df828598SMugunthan V N u32 id_ver; 161df828598SMugunthan V N u32 soft_reset; 162df828598SMugunthan V N u32 control; 163df828598SMugunthan V N u32 int_control; 164df828598SMugunthan V N u32 rx_thresh_en; 165df828598SMugunthan V N u32 rx_en; 166df828598SMugunthan V N u32 tx_en; 167df828598SMugunthan V N u32 misc_en; 168ff5b8ef2SMugunthan V N u32 mem_allign1[8]; 169ff5b8ef2SMugunthan V N u32 rx_thresh_stat; 170ff5b8ef2SMugunthan V N u32 rx_stat; 171ff5b8ef2SMugunthan V N u32 tx_stat; 172ff5b8ef2SMugunthan V N u32 misc_stat; 173ff5b8ef2SMugunthan V N u32 mem_allign2[8]; 174ff5b8ef2SMugunthan V N u32 rx_imax; 175ff5b8ef2SMugunthan V N u32 tx_imax; 176ff5b8ef2SMugunthan V N 177df828598SMugunthan V N }; 178df828598SMugunthan V N 179996a5c27SRichard Cochran struct cpsw_ss_regs { 180df828598SMugunthan V N u32 id_ver; 181df828598SMugunthan V N u32 control; 182df828598SMugunthan V N u32 soft_reset; 183df828598SMugunthan V N u32 stat_port_en; 184df828598SMugunthan V N u32 ptype; 185bd357af2SRichard Cochran u32 soft_idle; 186bd357af2SRichard Cochran u32 thru_rate; 187bd357af2SRichard Cochran u32 gap_thresh; 188bd357af2SRichard Cochran u32 tx_start_wds; 189bd357af2SRichard Cochran u32 flow_control; 190bd357af2SRichard Cochran u32 vlan_ltype; 191bd357af2SRichard Cochran u32 ts_ltype; 192bd357af2SRichard Cochran u32 dlr_ltype; 193df828598SMugunthan V N }; 194df828598SMugunthan V N 1959750a3adSRichard Cochran /* CPSW_PORT_V1 */ 1969750a3adSRichard Cochran #define CPSW1_MAX_BLKS 0x00 /* Maximum FIFO Blocks */ 1979750a3adSRichard Cochran #define CPSW1_BLK_CNT 0x04 /* FIFO Block Usage Count (Read Only) */ 1989750a3adSRichard Cochran #define CPSW1_TX_IN_CTL 0x08 /* Transmit FIFO Control */ 1999750a3adSRichard Cochran #define CPSW1_PORT_VLAN 0x0c /* VLAN Register */ 2009750a3adSRichard Cochran #define CPSW1_TX_PRI_MAP 0x10 /* Tx Header Priority to Switch Pri Mapping */ 2019750a3adSRichard Cochran #define CPSW1_TS_CTL 0x14 /* Time Sync Control */ 2029750a3adSRichard Cochran #define CPSW1_TS_SEQ_LTYPE 0x18 /* Time Sync Sequence ID Offset and Msg Type */ 2039750a3adSRichard Cochran #define CPSW1_TS_VLAN 0x1c /* Time Sync VLAN1 and VLAN2 */ 2049750a3adSRichard Cochran 2059750a3adSRichard Cochran /* CPSW_PORT_V2 */ 2069750a3adSRichard Cochran #define CPSW2_CONTROL 0x00 /* Control Register */ 2079750a3adSRichard Cochran #define CPSW2_MAX_BLKS 0x08 /* Maximum FIFO Blocks */ 2089750a3adSRichard Cochran #define CPSW2_BLK_CNT 0x0c /* FIFO Block Usage Count (Read Only) */ 2099750a3adSRichard Cochran #define CPSW2_TX_IN_CTL 0x10 /* Transmit FIFO Control */ 2109750a3adSRichard Cochran #define CPSW2_PORT_VLAN 0x14 /* VLAN Register */ 2119750a3adSRichard Cochran #define CPSW2_TX_PRI_MAP 0x18 /* Tx Header Priority to Switch Pri Mapping */ 2129750a3adSRichard Cochran #define CPSW2_TS_SEQ_MTYPE 0x1c /* Time Sync Sequence ID Offset and Msg Type */ 2139750a3adSRichard Cochran 2149750a3adSRichard Cochran /* CPSW_PORT_V1 and V2 */ 2159750a3adSRichard Cochran #define SA_LO 0x20 /* CPGMAC_SL Source Address Low */ 2169750a3adSRichard Cochran #define SA_HI 0x24 /* CPGMAC_SL Source Address High */ 2179750a3adSRichard Cochran #define SEND_PERCENT 0x28 /* Transmit Queue Send Percentages */ 2189750a3adSRichard Cochran 2199750a3adSRichard Cochran /* CPSW_PORT_V2 only */ 2209750a3adSRichard Cochran #define RX_DSCP_PRI_MAP0 0x30 /* Rx DSCP Priority to Rx Packet Mapping */ 2219750a3adSRichard Cochran #define RX_DSCP_PRI_MAP1 0x34 /* Rx DSCP Priority to Rx Packet Mapping */ 2229750a3adSRichard Cochran #define RX_DSCP_PRI_MAP2 0x38 /* Rx DSCP Priority to Rx Packet Mapping */ 2239750a3adSRichard Cochran #define RX_DSCP_PRI_MAP3 0x3c /* Rx DSCP Priority to Rx Packet Mapping */ 2249750a3adSRichard Cochran #define RX_DSCP_PRI_MAP4 0x40 /* Rx DSCP Priority to Rx Packet Mapping */ 2259750a3adSRichard Cochran #define RX_DSCP_PRI_MAP5 0x44 /* Rx DSCP Priority to Rx Packet Mapping */ 2269750a3adSRichard Cochran #define RX_DSCP_PRI_MAP6 0x48 /* Rx DSCP Priority to Rx Packet Mapping */ 2279750a3adSRichard Cochran #define RX_DSCP_PRI_MAP7 0x4c /* Rx DSCP Priority to Rx Packet Mapping */ 2289750a3adSRichard Cochran 2299750a3adSRichard Cochran /* Bit definitions for the CPSW2_CONTROL register */ 2309750a3adSRichard Cochran #define PASS_PRI_TAGGED (1<<24) /* Pass Priority Tagged */ 2319750a3adSRichard Cochran #define VLAN_LTYPE2_EN (1<<21) /* VLAN LTYPE 2 enable */ 2329750a3adSRichard Cochran #define VLAN_LTYPE1_EN (1<<20) /* VLAN LTYPE 1 enable */ 2339750a3adSRichard Cochran #define DSCP_PRI_EN (1<<16) /* DSCP Priority Enable */ 2349750a3adSRichard Cochran #define TS_320 (1<<14) /* Time Sync Dest Port 320 enable */ 2359750a3adSRichard Cochran #define TS_319 (1<<13) /* Time Sync Dest Port 319 enable */ 2369750a3adSRichard Cochran #define TS_132 (1<<12) /* Time Sync Dest IP Addr 132 enable */ 2379750a3adSRichard Cochran #define TS_131 (1<<11) /* Time Sync Dest IP Addr 131 enable */ 2389750a3adSRichard Cochran #define TS_130 (1<<10) /* Time Sync Dest IP Addr 130 enable */ 2399750a3adSRichard Cochran #define TS_129 (1<<9) /* Time Sync Dest IP Addr 129 enable */ 24009c55372SGeorge Cherian #define TS_TTL_NONZERO (1<<8) /* Time Sync Time To Live Non-zero enable */ 24109c55372SGeorge Cherian #define TS_ANNEX_F_EN (1<<6) /* Time Sync Annex F enable */ 2429750a3adSRichard Cochran #define TS_ANNEX_D_EN (1<<4) /* Time Sync Annex D enable */ 2439750a3adSRichard Cochran #define TS_LTYPE2_EN (1<<3) /* Time Sync LTYPE 2 enable */ 2449750a3adSRichard Cochran #define TS_LTYPE1_EN (1<<2) /* Time Sync LTYPE 1 enable */ 2459750a3adSRichard Cochran #define TS_TX_EN (1<<1) /* Time Sync Transmit Enable */ 2469750a3adSRichard Cochran #define TS_RX_EN (1<<0) /* Time Sync Receive Enable */ 2479750a3adSRichard Cochran 24809c55372SGeorge Cherian #define CTRL_V2_TS_BITS \ 24909c55372SGeorge Cherian (TS_320 | TS_319 | TS_132 | TS_131 | TS_130 | TS_129 |\ 25009c55372SGeorge Cherian TS_TTL_NONZERO | TS_ANNEX_D_EN | TS_LTYPE1_EN) 2519750a3adSRichard Cochran 25209c55372SGeorge Cherian #define CTRL_V2_ALL_TS_MASK (CTRL_V2_TS_BITS | TS_TX_EN | TS_RX_EN) 25309c55372SGeorge Cherian #define CTRL_V2_TX_TS_BITS (CTRL_V2_TS_BITS | TS_TX_EN) 25409c55372SGeorge Cherian #define CTRL_V2_RX_TS_BITS (CTRL_V2_TS_BITS | TS_RX_EN) 25509c55372SGeorge Cherian 25609c55372SGeorge Cherian 25709c55372SGeorge Cherian #define CTRL_V3_TS_BITS \ 25809c55372SGeorge Cherian (TS_320 | TS_319 | TS_132 | TS_131 | TS_130 | TS_129 |\ 25909c55372SGeorge Cherian TS_TTL_NONZERO | TS_ANNEX_F_EN | TS_ANNEX_D_EN |\ 26009c55372SGeorge Cherian TS_LTYPE1_EN) 26109c55372SGeorge Cherian 26209c55372SGeorge Cherian #define CTRL_V3_ALL_TS_MASK (CTRL_V3_TS_BITS | TS_TX_EN | TS_RX_EN) 26309c55372SGeorge Cherian #define CTRL_V3_TX_TS_BITS (CTRL_V3_TS_BITS | TS_TX_EN) 26409c55372SGeorge Cherian #define CTRL_V3_RX_TS_BITS (CTRL_V3_TS_BITS | TS_RX_EN) 2659750a3adSRichard Cochran 2669750a3adSRichard Cochran /* Bit definitions for the CPSW2_TS_SEQ_MTYPE register */ 2679750a3adSRichard Cochran #define TS_SEQ_ID_OFFSET_SHIFT (16) /* Time Sync Sequence ID Offset */ 2689750a3adSRichard Cochran #define TS_SEQ_ID_OFFSET_MASK (0x3f) 2699750a3adSRichard Cochran #define TS_MSG_TYPE_EN_SHIFT (0) /* Time Sync Message Type Enable */ 2709750a3adSRichard Cochran #define TS_MSG_TYPE_EN_MASK (0xffff) 2719750a3adSRichard Cochran 2729750a3adSRichard Cochran /* The PTP event messages - Sync, Delay_Req, Pdelay_Req, and Pdelay_Resp. */ 2739750a3adSRichard Cochran #define EVENT_MSG_BITS ((1<<0) | (1<<1) | (1<<2) | (1<<3)) 274df828598SMugunthan V N 2752e5b38abSRichard Cochran /* Bit definitions for the CPSW1_TS_CTL register */ 2762e5b38abSRichard Cochran #define CPSW_V1_TS_RX_EN BIT(0) 2772e5b38abSRichard Cochran #define CPSW_V1_TS_TX_EN BIT(4) 2782e5b38abSRichard Cochran #define CPSW_V1_MSG_TYPE_OFS 16 2792e5b38abSRichard Cochran 2802e5b38abSRichard Cochran /* Bit definitions for the CPSW1_TS_SEQ_LTYPE register */ 2812e5b38abSRichard Cochran #define CPSW_V1_SEQ_ID_OFS_SHIFT 16 2822e5b38abSRichard Cochran 283df828598SMugunthan V N struct cpsw_host_regs { 284df828598SMugunthan V N u32 max_blks; 285df828598SMugunthan V N u32 blk_cnt; 286d9ba8f9eSMugunthan V N u32 tx_in_ctl; 287df828598SMugunthan V N u32 port_vlan; 288df828598SMugunthan V N u32 tx_pri_map; 289df828598SMugunthan V N u32 cpdma_tx_pri_map; 290df828598SMugunthan V N u32 cpdma_rx_chan_map; 291df828598SMugunthan V N }; 292df828598SMugunthan V N 293df828598SMugunthan V N struct cpsw_sliver_regs { 294df828598SMugunthan V N u32 id_ver; 295df828598SMugunthan V N u32 mac_control; 296df828598SMugunthan V N u32 mac_status; 297df828598SMugunthan V N u32 soft_reset; 298df828598SMugunthan V N u32 rx_maxlen; 299df828598SMugunthan V N u32 __reserved_0; 300df828598SMugunthan V N u32 rx_pause; 301df828598SMugunthan V N u32 tx_pause; 302df828598SMugunthan V N u32 __reserved_1; 303df828598SMugunthan V N u32 rx_pri_map; 304df828598SMugunthan V N }; 305df828598SMugunthan V N 306d9718546SMugunthan V N struct cpsw_hw_stats { 307d9718546SMugunthan V N u32 rxgoodframes; 308d9718546SMugunthan V N u32 rxbroadcastframes; 309d9718546SMugunthan V N u32 rxmulticastframes; 310d9718546SMugunthan V N u32 rxpauseframes; 311d9718546SMugunthan V N u32 rxcrcerrors; 312d9718546SMugunthan V N u32 rxaligncodeerrors; 313d9718546SMugunthan V N u32 rxoversizedframes; 314d9718546SMugunthan V N u32 rxjabberframes; 315d9718546SMugunthan V N u32 rxundersizedframes; 316d9718546SMugunthan V N u32 rxfragments; 317d9718546SMugunthan V N u32 __pad_0[2]; 318d9718546SMugunthan V N u32 rxoctets; 319d9718546SMugunthan V N u32 txgoodframes; 320d9718546SMugunthan V N u32 txbroadcastframes; 321d9718546SMugunthan V N u32 txmulticastframes; 322d9718546SMugunthan V N u32 txpauseframes; 323d9718546SMugunthan V N u32 txdeferredframes; 324d9718546SMugunthan V N u32 txcollisionframes; 325d9718546SMugunthan V N u32 txsinglecollframes; 326d9718546SMugunthan V N u32 txmultcollframes; 327d9718546SMugunthan V N u32 txexcessivecollisions; 328d9718546SMugunthan V N u32 txlatecollisions; 329d9718546SMugunthan V N u32 txunderrun; 330d9718546SMugunthan V N u32 txcarriersenseerrors; 331d9718546SMugunthan V N u32 txoctets; 332d9718546SMugunthan V N u32 octetframes64; 333d9718546SMugunthan V N u32 octetframes65t127; 334d9718546SMugunthan V N u32 octetframes128t255; 335d9718546SMugunthan V N u32 octetframes256t511; 336d9718546SMugunthan V N u32 octetframes512t1023; 337d9718546SMugunthan V N u32 octetframes1024tup; 338d9718546SMugunthan V N u32 netoctets; 339d9718546SMugunthan V N u32 rxsofoverruns; 340d9718546SMugunthan V N u32 rxmofoverruns; 341d9718546SMugunthan V N u32 rxdmaoverruns; 342d9718546SMugunthan V N }; 343d9718546SMugunthan V N 344df828598SMugunthan V N struct cpsw_slave { 3459750a3adSRichard Cochran void __iomem *regs; 346df828598SMugunthan V N struct cpsw_sliver_regs __iomem *sliver; 347df828598SMugunthan V N int slave_num; 348df828598SMugunthan V N u32 mac_control; 349df828598SMugunthan V N struct cpsw_slave_data *data; 350df828598SMugunthan V N struct phy_device *phy; 351d9ba8f9eSMugunthan V N struct net_device *ndev; 352d9ba8f9eSMugunthan V N u32 port_vlan; 353d9ba8f9eSMugunthan V N u32 open_stat; 354df828598SMugunthan V N }; 355df828598SMugunthan V N 3569750a3adSRichard Cochran static inline u32 slave_read(struct cpsw_slave *slave, u32 offset) 3579750a3adSRichard Cochran { 3589750a3adSRichard Cochran return __raw_readl(slave->regs + offset); 3599750a3adSRichard Cochran } 3609750a3adSRichard Cochran 3619750a3adSRichard Cochran static inline void slave_write(struct cpsw_slave *slave, u32 val, u32 offset) 3629750a3adSRichard Cochran { 3639750a3adSRichard Cochran __raw_writel(val, slave->regs + offset); 3649750a3adSRichard Cochran } 3659750a3adSRichard Cochran 366df828598SMugunthan V N struct cpsw_priv { 367df828598SMugunthan V N struct platform_device *pdev; 368df828598SMugunthan V N struct net_device *ndev; 36932a7432cSMugunthan V N struct napi_struct napi_rx; 37032a7432cSMugunthan V N struct napi_struct napi_tx; 371df828598SMugunthan V N struct device *dev; 372df828598SMugunthan V N struct cpsw_platform_data data; 373996a5c27SRichard Cochran struct cpsw_ss_regs __iomem *regs; 374996a5c27SRichard Cochran struct cpsw_wr_regs __iomem *wr_regs; 375d9718546SMugunthan V N u8 __iomem *hw_stats; 376df828598SMugunthan V N struct cpsw_host_regs __iomem *host_port_regs; 377df828598SMugunthan V N u32 msg_enable; 378e90cfac6SRichard Cochran u32 version; 379ff5b8ef2SMugunthan V N u32 coal_intvl; 380ff5b8ef2SMugunthan V N u32 bus_freq_mhz; 381df828598SMugunthan V N int rx_packet_max; 382df828598SMugunthan V N struct clk *clk; 383df828598SMugunthan V N u8 mac_addr[ETH_ALEN]; 384df828598SMugunthan V N struct cpsw_slave *slaves; 385df828598SMugunthan V N struct cpdma_ctlr *dma; 386df828598SMugunthan V N struct cpdma_chan *txch, *rxch; 387df828598SMugunthan V N struct cpsw_ale *ale; 3881923d6e4SMugunthan V N bool rx_pause; 3891923d6e4SMugunthan V N bool tx_pause; 3907da11600SMugunthan V N bool quirk_irq; 3917da11600SMugunthan V N bool rx_irq_disabled; 3927da11600SMugunthan V N bool tx_irq_disabled; 393df828598SMugunthan V N /* snapshot of IRQ numbers */ 394df828598SMugunthan V N u32 irqs_table[4]; 395df828598SMugunthan V N u32 num_irqs; 3969232b16dSMugunthan V N struct cpts *cpts; 397d9ba8f9eSMugunthan V N u32 emac_port; 398df828598SMugunthan V N }; 399df828598SMugunthan V N 400d9718546SMugunthan V N struct cpsw_stats { 401d9718546SMugunthan V N char stat_string[ETH_GSTRING_LEN]; 402d9718546SMugunthan V N int type; 403d9718546SMugunthan V N int sizeof_stat; 404d9718546SMugunthan V N int stat_offset; 405d9718546SMugunthan V N }; 406d9718546SMugunthan V N 407d9718546SMugunthan V N enum { 408d9718546SMugunthan V N CPSW_STATS, 409d9718546SMugunthan V N CPDMA_RX_STATS, 410d9718546SMugunthan V N CPDMA_TX_STATS, 411d9718546SMugunthan V N }; 412d9718546SMugunthan V N 413d9718546SMugunthan V N #define CPSW_STAT(m) CPSW_STATS, \ 414d9718546SMugunthan V N sizeof(((struct cpsw_hw_stats *)0)->m), \ 415d9718546SMugunthan V N offsetof(struct cpsw_hw_stats, m) 416d9718546SMugunthan V N #define CPDMA_RX_STAT(m) CPDMA_RX_STATS, \ 417d9718546SMugunthan V N sizeof(((struct cpdma_chan_stats *)0)->m), \ 418d9718546SMugunthan V N offsetof(struct cpdma_chan_stats, m) 419d9718546SMugunthan V N #define CPDMA_TX_STAT(m) CPDMA_TX_STATS, \ 420d9718546SMugunthan V N sizeof(((struct cpdma_chan_stats *)0)->m), \ 421d9718546SMugunthan V N offsetof(struct cpdma_chan_stats, m) 422d9718546SMugunthan V N 423d9718546SMugunthan V N static const struct cpsw_stats cpsw_gstrings_stats[] = { 424d9718546SMugunthan V N { "Good Rx Frames", CPSW_STAT(rxgoodframes) }, 425d9718546SMugunthan V N { "Broadcast Rx Frames", CPSW_STAT(rxbroadcastframes) }, 426d9718546SMugunthan V N { "Multicast Rx Frames", CPSW_STAT(rxmulticastframes) }, 427d9718546SMugunthan V N { "Pause Rx Frames", CPSW_STAT(rxpauseframes) }, 428d9718546SMugunthan V N { "Rx CRC Errors", CPSW_STAT(rxcrcerrors) }, 429d9718546SMugunthan V N { "Rx Align/Code Errors", CPSW_STAT(rxaligncodeerrors) }, 430d9718546SMugunthan V N { "Oversize Rx Frames", CPSW_STAT(rxoversizedframes) }, 431d9718546SMugunthan V N { "Rx Jabbers", CPSW_STAT(rxjabberframes) }, 432d9718546SMugunthan V N { "Undersize (Short) Rx Frames", CPSW_STAT(rxundersizedframes) }, 433d9718546SMugunthan V N { "Rx Fragments", CPSW_STAT(rxfragments) }, 434d9718546SMugunthan V N { "Rx Octets", CPSW_STAT(rxoctets) }, 435d9718546SMugunthan V N { "Good Tx Frames", CPSW_STAT(txgoodframes) }, 436d9718546SMugunthan V N { "Broadcast Tx Frames", CPSW_STAT(txbroadcastframes) }, 437d9718546SMugunthan V N { "Multicast Tx Frames", CPSW_STAT(txmulticastframes) }, 438d9718546SMugunthan V N { "Pause Tx Frames", CPSW_STAT(txpauseframes) }, 439d9718546SMugunthan V N { "Deferred Tx Frames", CPSW_STAT(txdeferredframes) }, 440d9718546SMugunthan V N { "Collisions", CPSW_STAT(txcollisionframes) }, 441d9718546SMugunthan V N { "Single Collision Tx Frames", CPSW_STAT(txsinglecollframes) }, 442d9718546SMugunthan V N { "Multiple Collision Tx Frames", CPSW_STAT(txmultcollframes) }, 443d9718546SMugunthan V N { "Excessive Collisions", CPSW_STAT(txexcessivecollisions) }, 444d9718546SMugunthan V N { "Late Collisions", CPSW_STAT(txlatecollisions) }, 445d9718546SMugunthan V N { "Tx Underrun", CPSW_STAT(txunderrun) }, 446d9718546SMugunthan V N { "Carrier Sense Errors", CPSW_STAT(txcarriersenseerrors) }, 447d9718546SMugunthan V N { "Tx Octets", CPSW_STAT(txoctets) }, 448d9718546SMugunthan V N { "Rx + Tx 64 Octet Frames", CPSW_STAT(octetframes64) }, 449d9718546SMugunthan V N { "Rx + Tx 65-127 Octet Frames", CPSW_STAT(octetframes65t127) }, 450d9718546SMugunthan V N { "Rx + Tx 128-255 Octet Frames", CPSW_STAT(octetframes128t255) }, 451d9718546SMugunthan V N { "Rx + Tx 256-511 Octet Frames", CPSW_STAT(octetframes256t511) }, 452d9718546SMugunthan V N { "Rx + Tx 512-1023 Octet Frames", CPSW_STAT(octetframes512t1023) }, 453d9718546SMugunthan V N { "Rx + Tx 1024-Up Octet Frames", CPSW_STAT(octetframes1024tup) }, 454d9718546SMugunthan V N { "Net Octets", CPSW_STAT(netoctets) }, 455d9718546SMugunthan V N { "Rx Start of Frame Overruns", CPSW_STAT(rxsofoverruns) }, 456d9718546SMugunthan V N { "Rx Middle of Frame Overruns", CPSW_STAT(rxmofoverruns) }, 457d9718546SMugunthan V N { "Rx DMA Overruns", CPSW_STAT(rxdmaoverruns) }, 458d9718546SMugunthan V N { "Rx DMA chan: head_enqueue", CPDMA_RX_STAT(head_enqueue) }, 459d9718546SMugunthan V N { "Rx DMA chan: tail_enqueue", CPDMA_RX_STAT(tail_enqueue) }, 460d9718546SMugunthan V N { "Rx DMA chan: pad_enqueue", CPDMA_RX_STAT(pad_enqueue) }, 461d9718546SMugunthan V N { "Rx DMA chan: misqueued", CPDMA_RX_STAT(misqueued) }, 462d9718546SMugunthan V N { "Rx DMA chan: desc_alloc_fail", CPDMA_RX_STAT(desc_alloc_fail) }, 463d9718546SMugunthan V N { "Rx DMA chan: pad_alloc_fail", CPDMA_RX_STAT(pad_alloc_fail) }, 464d9718546SMugunthan V N { "Rx DMA chan: runt_receive_buf", CPDMA_RX_STAT(runt_receive_buff) }, 465d9718546SMugunthan V N { "Rx DMA chan: runt_transmit_buf", CPDMA_RX_STAT(runt_transmit_buff) }, 466d9718546SMugunthan V N { "Rx DMA chan: empty_dequeue", CPDMA_RX_STAT(empty_dequeue) }, 467d9718546SMugunthan V N { "Rx DMA chan: busy_dequeue", CPDMA_RX_STAT(busy_dequeue) }, 468d9718546SMugunthan V N { "Rx DMA chan: good_dequeue", CPDMA_RX_STAT(good_dequeue) }, 469d9718546SMugunthan V N { "Rx DMA chan: requeue", CPDMA_RX_STAT(requeue) }, 470d9718546SMugunthan V N { "Rx DMA chan: teardown_dequeue", CPDMA_RX_STAT(teardown_dequeue) }, 471d9718546SMugunthan V N { "Tx DMA chan: head_enqueue", CPDMA_TX_STAT(head_enqueue) }, 472d9718546SMugunthan V N { "Tx DMA chan: tail_enqueue", CPDMA_TX_STAT(tail_enqueue) }, 473d9718546SMugunthan V N { "Tx DMA chan: pad_enqueue", CPDMA_TX_STAT(pad_enqueue) }, 474d9718546SMugunthan V N { "Tx DMA chan: misqueued", CPDMA_TX_STAT(misqueued) }, 475d9718546SMugunthan V N { "Tx DMA chan: desc_alloc_fail", CPDMA_TX_STAT(desc_alloc_fail) }, 476d9718546SMugunthan V N { "Tx DMA chan: pad_alloc_fail", CPDMA_TX_STAT(pad_alloc_fail) }, 477d9718546SMugunthan V N { "Tx DMA chan: runt_receive_buf", CPDMA_TX_STAT(runt_receive_buff) }, 478d9718546SMugunthan V N { "Tx DMA chan: runt_transmit_buf", CPDMA_TX_STAT(runt_transmit_buff) }, 479d9718546SMugunthan V N { "Tx DMA chan: empty_dequeue", CPDMA_TX_STAT(empty_dequeue) }, 480d9718546SMugunthan V N { "Tx DMA chan: busy_dequeue", CPDMA_TX_STAT(busy_dequeue) }, 481d9718546SMugunthan V N { "Tx DMA chan: good_dequeue", CPDMA_TX_STAT(good_dequeue) }, 482d9718546SMugunthan V N { "Tx DMA chan: requeue", CPDMA_TX_STAT(requeue) }, 483d9718546SMugunthan V N { "Tx DMA chan: teardown_dequeue", CPDMA_TX_STAT(teardown_dequeue) }, 484d9718546SMugunthan V N }; 485d9718546SMugunthan V N 486d9718546SMugunthan V N #define CPSW_STATS_LEN ARRAY_SIZE(cpsw_gstrings_stats) 487d9718546SMugunthan V N 488df828598SMugunthan V N #define napi_to_priv(napi) container_of(napi, struct cpsw_priv, napi) 489df828598SMugunthan V N #define for_each_slave(priv, func, arg...) \ 490df828598SMugunthan V N do { \ 4916e6ceaedSSebastian Siewior struct cpsw_slave *slave; \ 4926e6ceaedSSebastian Siewior int n; \ 493d9ba8f9eSMugunthan V N if (priv->data.dual_emac) \ 494d9ba8f9eSMugunthan V N (func)((priv)->slaves + priv->emac_port, ##arg);\ 495d9ba8f9eSMugunthan V N else \ 4966e6ceaedSSebastian Siewior for (n = (priv)->data.slaves, \ 4976e6ceaedSSebastian Siewior slave = (priv)->slaves; \ 4986e6ceaedSSebastian Siewior n; n--) \ 4996e6ceaedSSebastian Siewior (func)(slave++, ##arg); \ 500df828598SMugunthan V N } while (0) 501d9ba8f9eSMugunthan V N #define cpsw_get_slave_ndev(priv, __slave_no__) \ 5021973db0dSMugunthan V N ((__slave_no__ < priv->data.slaves) ? \ 5031973db0dSMugunthan V N priv->slaves[__slave_no__].ndev : NULL) 504d9ba8f9eSMugunthan V N #define cpsw_get_slave_priv(priv, __slave_no__) \ 5051973db0dSMugunthan V N (((__slave_no__ < priv->data.slaves) && \ 5061973db0dSMugunthan V N (priv->slaves[__slave_no__].ndev)) ? \ 507d9ba8f9eSMugunthan V N netdev_priv(priv->slaves[__slave_no__].ndev) : NULL) \ 508d9ba8f9eSMugunthan V N 509d9ba8f9eSMugunthan V N #define cpsw_dual_emac_src_port_detect(status, priv, ndev, skb) \ 510d9ba8f9eSMugunthan V N do { \ 511d9ba8f9eSMugunthan V N if (!priv->data.dual_emac) \ 512d9ba8f9eSMugunthan V N break; \ 513d9ba8f9eSMugunthan V N if (CPDMA_RX_SOURCE_PORT(status) == 1) { \ 514d9ba8f9eSMugunthan V N ndev = cpsw_get_slave_ndev(priv, 0); \ 515d9ba8f9eSMugunthan V N priv = netdev_priv(ndev); \ 516d9ba8f9eSMugunthan V N skb->dev = ndev; \ 517d9ba8f9eSMugunthan V N } else if (CPDMA_RX_SOURCE_PORT(status) == 2) { \ 518d9ba8f9eSMugunthan V N ndev = cpsw_get_slave_ndev(priv, 1); \ 519d9ba8f9eSMugunthan V N priv = netdev_priv(ndev); \ 520d9ba8f9eSMugunthan V N skb->dev = ndev; \ 521d9ba8f9eSMugunthan V N } \ 522d9ba8f9eSMugunthan V N } while (0) 523d9ba8f9eSMugunthan V N #define cpsw_add_mcast(priv, addr) \ 524d9ba8f9eSMugunthan V N do { \ 525d9ba8f9eSMugunthan V N if (priv->data.dual_emac) { \ 526d9ba8f9eSMugunthan V N struct cpsw_slave *slave = priv->slaves + \ 527d9ba8f9eSMugunthan V N priv->emac_port; \ 528d9ba8f9eSMugunthan V N int slave_port = cpsw_get_slave_port(priv, \ 529d9ba8f9eSMugunthan V N slave->slave_num); \ 530d9ba8f9eSMugunthan V N cpsw_ale_add_mcast(priv->ale, addr, \ 53171a2cbb7SGrygorii Strashko 1 << slave_port | ALE_PORT_HOST, \ 532d9ba8f9eSMugunthan V N ALE_VLAN, slave->port_vlan, 0); \ 533d9ba8f9eSMugunthan V N } else { \ 534d9ba8f9eSMugunthan V N cpsw_ale_add_mcast(priv->ale, addr, \ 53561f1cef9SGrygorii Strashko ALE_ALL_PORTS, \ 536d9ba8f9eSMugunthan V N 0, 0, 0); \ 537d9ba8f9eSMugunthan V N } \ 538d9ba8f9eSMugunthan V N } while (0) 539d9ba8f9eSMugunthan V N 540d9ba8f9eSMugunthan V N static inline int cpsw_get_slave_port(struct cpsw_priv *priv, u32 slave_num) 541d9ba8f9eSMugunthan V N { 542d9ba8f9eSMugunthan V N return slave_num + 1; 543d9ba8f9eSMugunthan V N } 544df828598SMugunthan V N 5450cd8f9ccSMugunthan V N static void cpsw_set_promiscious(struct net_device *ndev, bool enable) 5460cd8f9ccSMugunthan V N { 5470cd8f9ccSMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 5480cd8f9ccSMugunthan V N struct cpsw_ale *ale = priv->ale; 5490cd8f9ccSMugunthan V N int i; 5500cd8f9ccSMugunthan V N 5510cd8f9ccSMugunthan V N if (priv->data.dual_emac) { 5520cd8f9ccSMugunthan V N bool flag = false; 5530cd8f9ccSMugunthan V N 5540cd8f9ccSMugunthan V N /* Enabling promiscuous mode for one interface will be 5550cd8f9ccSMugunthan V N * common for both the interface as the interface shares 5560cd8f9ccSMugunthan V N * the same hardware resource. 5570cd8f9ccSMugunthan V N */ 5580d961b3bSHeiko Schocher for (i = 0; i < priv->data.slaves; i++) 5590cd8f9ccSMugunthan V N if (priv->slaves[i].ndev->flags & IFF_PROMISC) 5600cd8f9ccSMugunthan V N flag = true; 5610cd8f9ccSMugunthan V N 5620cd8f9ccSMugunthan V N if (!enable && flag) { 5630cd8f9ccSMugunthan V N enable = true; 5640cd8f9ccSMugunthan V N dev_err(&ndev->dev, "promiscuity not disabled as the other interface is still in promiscuity mode\n"); 5650cd8f9ccSMugunthan V N } 5660cd8f9ccSMugunthan V N 5670cd8f9ccSMugunthan V N if (enable) { 5680cd8f9ccSMugunthan V N /* Enable Bypass */ 5690cd8f9ccSMugunthan V N cpsw_ale_control_set(ale, 0, ALE_BYPASS, 1); 5700cd8f9ccSMugunthan V N 5710cd8f9ccSMugunthan V N dev_dbg(&ndev->dev, "promiscuity enabled\n"); 5720cd8f9ccSMugunthan V N } else { 5730cd8f9ccSMugunthan V N /* Disable Bypass */ 5740cd8f9ccSMugunthan V N cpsw_ale_control_set(ale, 0, ALE_BYPASS, 0); 5750cd8f9ccSMugunthan V N dev_dbg(&ndev->dev, "promiscuity disabled\n"); 5760cd8f9ccSMugunthan V N } 5770cd8f9ccSMugunthan V N } else { 5780cd8f9ccSMugunthan V N if (enable) { 5790cd8f9ccSMugunthan V N unsigned long timeout = jiffies + HZ; 5800cd8f9ccSMugunthan V N 5816f979eb3SLennart Sorensen /* Disable Learn for all ports (host is port 0 and slaves are port 1 and up */ 5826f979eb3SLennart Sorensen for (i = 0; i <= priv->data.slaves; i++) { 5830cd8f9ccSMugunthan V N cpsw_ale_control_set(ale, i, 5840cd8f9ccSMugunthan V N ALE_PORT_NOLEARN, 1); 5850cd8f9ccSMugunthan V N cpsw_ale_control_set(ale, i, 5860cd8f9ccSMugunthan V N ALE_PORT_NO_SA_UPDATE, 1); 5870cd8f9ccSMugunthan V N } 5880cd8f9ccSMugunthan V N 5890cd8f9ccSMugunthan V N /* Clear All Untouched entries */ 5900cd8f9ccSMugunthan V N cpsw_ale_control_set(ale, 0, ALE_AGEOUT, 1); 5910cd8f9ccSMugunthan V N do { 5920cd8f9ccSMugunthan V N cpu_relax(); 5930cd8f9ccSMugunthan V N if (cpsw_ale_control_get(ale, 0, ALE_AGEOUT)) 5940cd8f9ccSMugunthan V N break; 5950cd8f9ccSMugunthan V N } while (time_after(timeout, jiffies)); 5960cd8f9ccSMugunthan V N cpsw_ale_control_set(ale, 0, ALE_AGEOUT, 1); 5970cd8f9ccSMugunthan V N 5980cd8f9ccSMugunthan V N /* Clear all mcast from ALE */ 59961f1cef9SGrygorii Strashko cpsw_ale_flush_multicast(ale, ALE_ALL_PORTS, -1); 6000cd8f9ccSMugunthan V N 6010cd8f9ccSMugunthan V N /* Flood All Unicast Packets to Host port */ 6020cd8f9ccSMugunthan V N cpsw_ale_control_set(ale, 0, ALE_P0_UNI_FLOOD, 1); 6030cd8f9ccSMugunthan V N dev_dbg(&ndev->dev, "promiscuity enabled\n"); 6040cd8f9ccSMugunthan V N } else { 6056f979eb3SLennart Sorensen /* Don't Flood All Unicast Packets to Host port */ 6060cd8f9ccSMugunthan V N cpsw_ale_control_set(ale, 0, ALE_P0_UNI_FLOOD, 0); 6070cd8f9ccSMugunthan V N 6086f979eb3SLennart Sorensen /* Enable Learn for all ports (host is port 0 and slaves are port 1 and up */ 6096f979eb3SLennart Sorensen for (i = 0; i <= priv->data.slaves; i++) { 6100cd8f9ccSMugunthan V N cpsw_ale_control_set(ale, i, 6110cd8f9ccSMugunthan V N ALE_PORT_NOLEARN, 0); 6120cd8f9ccSMugunthan V N cpsw_ale_control_set(ale, i, 6130cd8f9ccSMugunthan V N ALE_PORT_NO_SA_UPDATE, 0); 6140cd8f9ccSMugunthan V N } 6150cd8f9ccSMugunthan V N dev_dbg(&ndev->dev, "promiscuity disabled\n"); 6160cd8f9ccSMugunthan V N } 6170cd8f9ccSMugunthan V N } 6180cd8f9ccSMugunthan V N } 6190cd8f9ccSMugunthan V N 6205c50a856SMugunthan V N static void cpsw_ndo_set_rx_mode(struct net_device *ndev) 6215c50a856SMugunthan V N { 6225c50a856SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 62325906052SMugunthan V N int vid; 62425906052SMugunthan V N 62525906052SMugunthan V N if (priv->data.dual_emac) 62625906052SMugunthan V N vid = priv->slaves[priv->emac_port].port_vlan; 62725906052SMugunthan V N else 62825906052SMugunthan V N vid = priv->data.default_vlan; 6295c50a856SMugunthan V N 6305c50a856SMugunthan V N if (ndev->flags & IFF_PROMISC) { 6315c50a856SMugunthan V N /* Enable promiscuous mode */ 6320cd8f9ccSMugunthan V N cpsw_set_promiscious(ndev, true); 6331e5c4bc4SLennart Sorensen cpsw_ale_set_allmulti(priv->ale, IFF_ALLMULTI); 6345c50a856SMugunthan V N return; 6350cd8f9ccSMugunthan V N } else { 6360cd8f9ccSMugunthan V N /* Disable promiscuous mode */ 6370cd8f9ccSMugunthan V N cpsw_set_promiscious(ndev, false); 6385c50a856SMugunthan V N } 6395c50a856SMugunthan V N 6401e5c4bc4SLennart Sorensen /* Restore allmulti on vlans if necessary */ 6411e5c4bc4SLennart Sorensen cpsw_ale_set_allmulti(priv->ale, priv->ndev->flags & IFF_ALLMULTI); 6421e5c4bc4SLennart Sorensen 6435c50a856SMugunthan V N /* Clear all mcast from ALE */ 64461f1cef9SGrygorii Strashko cpsw_ale_flush_multicast(priv->ale, ALE_ALL_PORTS, vid); 6455c50a856SMugunthan V N 6465c50a856SMugunthan V N if (!netdev_mc_empty(ndev)) { 6475c50a856SMugunthan V N struct netdev_hw_addr *ha; 6485c50a856SMugunthan V N 6495c50a856SMugunthan V N /* program multicast address list into ALE register */ 6505c50a856SMugunthan V N netdev_for_each_mc_addr(ha, ndev) { 651d9ba8f9eSMugunthan V N cpsw_add_mcast(priv, (u8 *)ha->addr); 6525c50a856SMugunthan V N } 6535c50a856SMugunthan V N } 6545c50a856SMugunthan V N } 6555c50a856SMugunthan V N 656df828598SMugunthan V N static void cpsw_intr_enable(struct cpsw_priv *priv) 657df828598SMugunthan V N { 658996a5c27SRichard Cochran __raw_writel(0xFF, &priv->wr_regs->tx_en); 659996a5c27SRichard Cochran __raw_writel(0xFF, &priv->wr_regs->rx_en); 660df828598SMugunthan V N 661df828598SMugunthan V N cpdma_ctlr_int_ctrl(priv->dma, true); 662df828598SMugunthan V N return; 663df828598SMugunthan V N } 664df828598SMugunthan V N 665df828598SMugunthan V N static void cpsw_intr_disable(struct cpsw_priv *priv) 666df828598SMugunthan V N { 667996a5c27SRichard Cochran __raw_writel(0, &priv->wr_regs->tx_en); 668996a5c27SRichard Cochran __raw_writel(0, &priv->wr_regs->rx_en); 669df828598SMugunthan V N 670df828598SMugunthan V N cpdma_ctlr_int_ctrl(priv->dma, false); 671df828598SMugunthan V N return; 672df828598SMugunthan V N } 673df828598SMugunthan V N 6741a3b5056SOlof Johansson static void cpsw_tx_handler(void *token, int len, int status) 675df828598SMugunthan V N { 676df828598SMugunthan V N struct sk_buff *skb = token; 677df828598SMugunthan V N struct net_device *ndev = skb->dev; 678df828598SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 679df828598SMugunthan V N 680fae50823SMugunthan V N /* Check whether the queue is stopped due to stalled tx dma, if the 681fae50823SMugunthan V N * queue is stopped then start the queue as we have free desc for tx 682fae50823SMugunthan V N */ 683df828598SMugunthan V N if (unlikely(netif_queue_stopped(ndev))) 684b56d6b3fSMugunthan V N netif_wake_queue(ndev); 6859232b16dSMugunthan V N cpts_tx_timestamp(priv->cpts, skb); 6868dc43ddcSTobias Klauser ndev->stats.tx_packets++; 6878dc43ddcSTobias Klauser ndev->stats.tx_bytes += len; 688df828598SMugunthan V N dev_kfree_skb_any(skb); 689df828598SMugunthan V N } 690df828598SMugunthan V N 6911a3b5056SOlof Johansson static void cpsw_rx_handler(void *token, int len, int status) 692df828598SMugunthan V N { 693df828598SMugunthan V N struct sk_buff *skb = token; 694b4727e69SSebastian Siewior struct sk_buff *new_skb; 695df828598SMugunthan V N struct net_device *ndev = skb->dev; 696df828598SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 697df828598SMugunthan V N int ret = 0; 698df828598SMugunthan V N 699d9ba8f9eSMugunthan V N cpsw_dual_emac_src_port_detect(status, priv, ndev, skb); 700d9ba8f9eSMugunthan V N 70116e5c57dSMugunthan V N if (unlikely(status < 0) || unlikely(!netif_running(ndev))) { 702a0e2c822SMugunthan V N bool ndev_status = false; 703a0e2c822SMugunthan V N struct cpsw_slave *slave = priv->slaves; 704a0e2c822SMugunthan V N int n; 705a0e2c822SMugunthan V N 706a0e2c822SMugunthan V N if (priv->data.dual_emac) { 707a0e2c822SMugunthan V N /* In dual emac mode check for all interfaces */ 708a0e2c822SMugunthan V N for (n = priv->data.slaves; n; n--, slave++) 709a0e2c822SMugunthan V N if (netif_running(slave->ndev)) 710a0e2c822SMugunthan V N ndev_status = true; 711a0e2c822SMugunthan V N } 712a0e2c822SMugunthan V N 713a0e2c822SMugunthan V N if (ndev_status && (status >= 0)) { 714a0e2c822SMugunthan V N /* The packet received is for the interface which 715a0e2c822SMugunthan V N * is already down and the other interface is up 716dbedd44eSJoe Perches * and running, instead of freeing which results 717a0e2c822SMugunthan V N * in reducing of the number of rx descriptor in 718a0e2c822SMugunthan V N * DMA engine, requeue skb back to cpdma. 719a0e2c822SMugunthan V N */ 720a0e2c822SMugunthan V N new_skb = skb; 721a0e2c822SMugunthan V N goto requeue; 722a0e2c822SMugunthan V N } 723a0e2c822SMugunthan V N 724b4727e69SSebastian Siewior /* the interface is going down, skbs are purged */ 725df828598SMugunthan V N dev_kfree_skb_any(skb); 726df828598SMugunthan V N return; 727df828598SMugunthan V N } 728b4727e69SSebastian Siewior 729b4727e69SSebastian Siewior new_skb = netdev_alloc_skb_ip_align(ndev, priv->rx_packet_max); 730b4727e69SSebastian Siewior if (new_skb) { 731df828598SMugunthan V N skb_put(skb, len); 7329232b16dSMugunthan V N cpts_rx_timestamp(priv->cpts, skb); 733df828598SMugunthan V N skb->protocol = eth_type_trans(skb, ndev); 734df828598SMugunthan V N netif_receive_skb(skb); 7358dc43ddcSTobias Klauser ndev->stats.rx_bytes += len; 7368dc43ddcSTobias Klauser ndev->stats.rx_packets++; 737254a49d5SGrygorii Strashko kmemleak_not_leak(new_skb); 738b4727e69SSebastian Siewior } else { 7398dc43ddcSTobias Klauser ndev->stats.rx_dropped++; 740b4727e69SSebastian Siewior new_skb = skb; 741df828598SMugunthan V N } 742df828598SMugunthan V N 743a0e2c822SMugunthan V N requeue: 744b4727e69SSebastian Siewior ret = cpdma_chan_submit(priv->rxch, new_skb, new_skb->data, 745b4727e69SSebastian Siewior skb_tailroom(new_skb), 0); 746b4727e69SSebastian Siewior if (WARN_ON(ret < 0)) 747b4727e69SSebastian Siewior dev_kfree_skb_any(new_skb); 748df828598SMugunthan V N } 749df828598SMugunthan V N 750c03abd84SFelipe Balbi static irqreturn_t cpsw_tx_interrupt(int irq, void *dev_id) 751df828598SMugunthan V N { 752df828598SMugunthan V N struct cpsw_priv *priv = dev_id; 7537ce67a38SFelipe Balbi 75432a7432cSMugunthan V N writel(0, &priv->wr_regs->tx_en); 755c03abd84SFelipe Balbi cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_TX); 756c03abd84SFelipe Balbi 7577da11600SMugunthan V N if (priv->quirk_irq) { 7587da11600SMugunthan V N disable_irq_nosync(priv->irqs_table[1]); 7597da11600SMugunthan V N priv->tx_irq_disabled = true; 7607da11600SMugunthan V N } 7617da11600SMugunthan V N 76232a7432cSMugunthan V N napi_schedule(&priv->napi_tx); 763c03abd84SFelipe Balbi return IRQ_HANDLED; 764c03abd84SFelipe Balbi } 765c03abd84SFelipe Balbi 766c03abd84SFelipe Balbi static irqreturn_t cpsw_rx_interrupt(int irq, void *dev_id) 767c03abd84SFelipe Balbi { 768c03abd84SFelipe Balbi struct cpsw_priv *priv = dev_id; 769c03abd84SFelipe Balbi 770c03abd84SFelipe Balbi cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_RX); 771870915feSMugunthan V N writel(0, &priv->wr_regs->rx_en); 772fd51cf19SSebastian Siewior 7737da11600SMugunthan V N if (priv->quirk_irq) { 7747da11600SMugunthan V N disable_irq_nosync(priv->irqs_table[0]); 7757da11600SMugunthan V N priv->rx_irq_disabled = true; 7767da11600SMugunthan V N } 7777da11600SMugunthan V N 77832a7432cSMugunthan V N napi_schedule(&priv->napi_rx); 779df828598SMugunthan V N return IRQ_HANDLED; 780df828598SMugunthan V N } 781df828598SMugunthan V N 78232a7432cSMugunthan V N static int cpsw_tx_poll(struct napi_struct *napi_tx, int budget) 783df828598SMugunthan V N { 78432a7432cSMugunthan V N struct cpsw_priv *priv = napi_to_priv(napi_tx); 78532a7432cSMugunthan V N int num_tx; 78632a7432cSMugunthan V N 78732a7432cSMugunthan V N num_tx = cpdma_chan_process(priv->txch, budget); 78832a7432cSMugunthan V N if (num_tx < budget) { 78932a7432cSMugunthan V N napi_complete(napi_tx); 79032a7432cSMugunthan V N writel(0xff, &priv->wr_regs->tx_en); 7917da11600SMugunthan V N if (priv->quirk_irq && priv->tx_irq_disabled) { 7927da11600SMugunthan V N priv->tx_irq_disabled = false; 7937da11600SMugunthan V N enable_irq(priv->irqs_table[1]); 7947da11600SMugunthan V N } 79532a7432cSMugunthan V N } 79632a7432cSMugunthan V N 79732a7432cSMugunthan V N if (num_tx) 79832a7432cSMugunthan V N cpsw_dbg(priv, intr, "poll %d tx pkts\n", num_tx); 79932a7432cSMugunthan V N 80032a7432cSMugunthan V N return num_tx; 80132a7432cSMugunthan V N } 80232a7432cSMugunthan V N 80332a7432cSMugunthan V N static int cpsw_rx_poll(struct napi_struct *napi_rx, int budget) 80432a7432cSMugunthan V N { 80532a7432cSMugunthan V N struct cpsw_priv *priv = napi_to_priv(napi_rx); 8061e353cddSMugunthan V N int num_rx; 807510a1e72SMugunthan V N 808df828598SMugunthan V N num_rx = cpdma_chan_process(priv->rxch, budget); 809510a1e72SMugunthan V N if (num_rx < budget) { 81032a7432cSMugunthan V N napi_complete(napi_rx); 811870915feSMugunthan V N writel(0xff, &priv->wr_regs->rx_en); 8127da11600SMugunthan V N if (priv->quirk_irq && priv->rx_irq_disabled) { 8137da11600SMugunthan V N priv->rx_irq_disabled = false; 8147da11600SMugunthan V N enable_irq(priv->irqs_table[0]); 8157da11600SMugunthan V N } 816510a1e72SMugunthan V N } 817df828598SMugunthan V N 8181e353cddSMugunthan V N if (num_rx) 8191e353cddSMugunthan V N cpsw_dbg(priv, intr, "poll %d rx pkts\n", num_rx); 820df828598SMugunthan V N 821df828598SMugunthan V N return num_rx; 822df828598SMugunthan V N } 823df828598SMugunthan V N 824df828598SMugunthan V N static inline void soft_reset(const char *module, void __iomem *reg) 825df828598SMugunthan V N { 826df828598SMugunthan V N unsigned long timeout = jiffies + HZ; 827df828598SMugunthan V N 828df828598SMugunthan V N __raw_writel(1, reg); 829df828598SMugunthan V N do { 830df828598SMugunthan V N cpu_relax(); 831df828598SMugunthan V N } while ((__raw_readl(reg) & 1) && time_after(timeout, jiffies)); 832df828598SMugunthan V N 833df828598SMugunthan V N WARN(__raw_readl(reg) & 1, "failed to soft-reset %s\n", module); 834df828598SMugunthan V N } 835df828598SMugunthan V N 836df828598SMugunthan V N #define mac_hi(mac) (((mac)[0] << 0) | ((mac)[1] << 8) | \ 837df828598SMugunthan V N ((mac)[2] << 16) | ((mac)[3] << 24)) 838df828598SMugunthan V N #define mac_lo(mac) (((mac)[4] << 0) | ((mac)[5] << 8)) 839df828598SMugunthan V N 840df828598SMugunthan V N static void cpsw_set_slave_mac(struct cpsw_slave *slave, 841df828598SMugunthan V N struct cpsw_priv *priv) 842df828598SMugunthan V N { 8439750a3adSRichard Cochran slave_write(slave, mac_hi(priv->mac_addr), SA_HI); 8449750a3adSRichard Cochran slave_write(slave, mac_lo(priv->mac_addr), SA_LO); 845df828598SMugunthan V N } 846df828598SMugunthan V N 847df828598SMugunthan V N static void _cpsw_adjust_link(struct cpsw_slave *slave, 848df828598SMugunthan V N struct cpsw_priv *priv, bool *link) 849df828598SMugunthan V N { 850df828598SMugunthan V N struct phy_device *phy = slave->phy; 851df828598SMugunthan V N u32 mac_control = 0; 852df828598SMugunthan V N u32 slave_port; 853df828598SMugunthan V N 854df828598SMugunthan V N if (!phy) 855df828598SMugunthan V N return; 856df828598SMugunthan V N 857df828598SMugunthan V N slave_port = cpsw_get_slave_port(priv, slave->slave_num); 858df828598SMugunthan V N 859df828598SMugunthan V N if (phy->link) { 860df828598SMugunthan V N mac_control = priv->data.mac_control; 861df828598SMugunthan V N 862df828598SMugunthan V N /* enable forwarding */ 863df828598SMugunthan V N cpsw_ale_control_set(priv->ale, slave_port, 864df828598SMugunthan V N ALE_PORT_STATE, ALE_PORT_STATE_FORWARD); 865df828598SMugunthan V N 866df828598SMugunthan V N if (phy->speed == 1000) 867df828598SMugunthan V N mac_control |= BIT(7); /* GIGABITEN */ 868df828598SMugunthan V N if (phy->duplex) 869df828598SMugunthan V N mac_control |= BIT(0); /* FULLDUPLEXEN */ 870342b7b74SDaniel Mack 871342b7b74SDaniel Mack /* set speed_in input in case RMII mode is used in 100Mbps */ 872342b7b74SDaniel Mack if (phy->speed == 100) 873342b7b74SDaniel Mack mac_control |= BIT(15); 874a81d8762SMugunthan V N else if (phy->speed == 10) 875a81d8762SMugunthan V N mac_control |= BIT(18); /* In Band mode */ 876342b7b74SDaniel Mack 8771923d6e4SMugunthan V N if (priv->rx_pause) 8781923d6e4SMugunthan V N mac_control |= BIT(3); 8791923d6e4SMugunthan V N 8801923d6e4SMugunthan V N if (priv->tx_pause) 8811923d6e4SMugunthan V N mac_control |= BIT(4); 8821923d6e4SMugunthan V N 883df828598SMugunthan V N *link = true; 884df828598SMugunthan V N } else { 885df828598SMugunthan V N mac_control = 0; 886df828598SMugunthan V N /* disable forwarding */ 887df828598SMugunthan V N cpsw_ale_control_set(priv->ale, slave_port, 888df828598SMugunthan V N ALE_PORT_STATE, ALE_PORT_STATE_DISABLE); 889df828598SMugunthan V N } 890df828598SMugunthan V N 891df828598SMugunthan V N if (mac_control != slave->mac_control) { 892df828598SMugunthan V N phy_print_status(phy); 893df828598SMugunthan V N __raw_writel(mac_control, &slave->sliver->mac_control); 894df828598SMugunthan V N } 895df828598SMugunthan V N 896df828598SMugunthan V N slave->mac_control = mac_control; 897df828598SMugunthan V N } 898df828598SMugunthan V N 899df828598SMugunthan V N static void cpsw_adjust_link(struct net_device *ndev) 900df828598SMugunthan V N { 901df828598SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 902df828598SMugunthan V N bool link = false; 903df828598SMugunthan V N 904df828598SMugunthan V N for_each_slave(priv, _cpsw_adjust_link, priv, &link); 905df828598SMugunthan V N 906df828598SMugunthan V N if (link) { 907df828598SMugunthan V N netif_carrier_on(ndev); 908df828598SMugunthan V N if (netif_running(ndev)) 909df828598SMugunthan V N netif_wake_queue(ndev); 910df828598SMugunthan V N } else { 911df828598SMugunthan V N netif_carrier_off(ndev); 912df828598SMugunthan V N netif_stop_queue(ndev); 913df828598SMugunthan V N } 914df828598SMugunthan V N } 915df828598SMugunthan V N 916ff5b8ef2SMugunthan V N static int cpsw_get_coalesce(struct net_device *ndev, 917ff5b8ef2SMugunthan V N struct ethtool_coalesce *coal) 918ff5b8ef2SMugunthan V N { 919ff5b8ef2SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 920ff5b8ef2SMugunthan V N 921ff5b8ef2SMugunthan V N coal->rx_coalesce_usecs = priv->coal_intvl; 922ff5b8ef2SMugunthan V N return 0; 923ff5b8ef2SMugunthan V N } 924ff5b8ef2SMugunthan V N 925ff5b8ef2SMugunthan V N static int cpsw_set_coalesce(struct net_device *ndev, 926ff5b8ef2SMugunthan V N struct ethtool_coalesce *coal) 927ff5b8ef2SMugunthan V N { 928ff5b8ef2SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 929ff5b8ef2SMugunthan V N u32 int_ctrl; 930ff5b8ef2SMugunthan V N u32 num_interrupts = 0; 931ff5b8ef2SMugunthan V N u32 prescale = 0; 932ff5b8ef2SMugunthan V N u32 addnl_dvdr = 1; 933ff5b8ef2SMugunthan V N u32 coal_intvl = 0; 934ff5b8ef2SMugunthan V N 935ff5b8ef2SMugunthan V N coal_intvl = coal->rx_coalesce_usecs; 936ff5b8ef2SMugunthan V N 937ff5b8ef2SMugunthan V N int_ctrl = readl(&priv->wr_regs->int_control); 938ff5b8ef2SMugunthan V N prescale = priv->bus_freq_mhz * 4; 939ff5b8ef2SMugunthan V N 940a84bc2a9SMugunthan V N if (!coal->rx_coalesce_usecs) { 941a84bc2a9SMugunthan V N int_ctrl &= ~(CPSW_INTPRESCALE_MASK | CPSW_INTPACEEN); 942a84bc2a9SMugunthan V N goto update_return; 943a84bc2a9SMugunthan V N } 944a84bc2a9SMugunthan V N 945ff5b8ef2SMugunthan V N if (coal_intvl < CPSW_CMINTMIN_INTVL) 946ff5b8ef2SMugunthan V N coal_intvl = CPSW_CMINTMIN_INTVL; 947ff5b8ef2SMugunthan V N 948ff5b8ef2SMugunthan V N if (coal_intvl > CPSW_CMINTMAX_INTVL) { 949ff5b8ef2SMugunthan V N /* Interrupt pacer works with 4us Pulse, we can 950ff5b8ef2SMugunthan V N * throttle further by dilating the 4us pulse. 951ff5b8ef2SMugunthan V N */ 952ff5b8ef2SMugunthan V N addnl_dvdr = CPSW_INTPRESCALE_MASK / prescale; 953ff5b8ef2SMugunthan V N 954ff5b8ef2SMugunthan V N if (addnl_dvdr > 1) { 955ff5b8ef2SMugunthan V N prescale *= addnl_dvdr; 956ff5b8ef2SMugunthan V N if (coal_intvl > (CPSW_CMINTMAX_INTVL * addnl_dvdr)) 957ff5b8ef2SMugunthan V N coal_intvl = (CPSW_CMINTMAX_INTVL 958ff5b8ef2SMugunthan V N * addnl_dvdr); 959ff5b8ef2SMugunthan V N } else { 960ff5b8ef2SMugunthan V N addnl_dvdr = 1; 961ff5b8ef2SMugunthan V N coal_intvl = CPSW_CMINTMAX_INTVL; 962ff5b8ef2SMugunthan V N } 963ff5b8ef2SMugunthan V N } 964ff5b8ef2SMugunthan V N 965ff5b8ef2SMugunthan V N num_interrupts = (1000 * addnl_dvdr) / coal_intvl; 966ff5b8ef2SMugunthan V N writel(num_interrupts, &priv->wr_regs->rx_imax); 967ff5b8ef2SMugunthan V N writel(num_interrupts, &priv->wr_regs->tx_imax); 968ff5b8ef2SMugunthan V N 969ff5b8ef2SMugunthan V N int_ctrl |= CPSW_INTPACEEN; 970ff5b8ef2SMugunthan V N int_ctrl &= (~CPSW_INTPRESCALE_MASK); 971ff5b8ef2SMugunthan V N int_ctrl |= (prescale & CPSW_INTPRESCALE_MASK); 972a84bc2a9SMugunthan V N 973a84bc2a9SMugunthan V N update_return: 974ff5b8ef2SMugunthan V N writel(int_ctrl, &priv->wr_regs->int_control); 975ff5b8ef2SMugunthan V N 976ff5b8ef2SMugunthan V N cpsw_notice(priv, timer, "Set coalesce to %d usecs.\n", coal_intvl); 977ff5b8ef2SMugunthan V N if (priv->data.dual_emac) { 978ff5b8ef2SMugunthan V N int i; 979ff5b8ef2SMugunthan V N 980ff5b8ef2SMugunthan V N for (i = 0; i < priv->data.slaves; i++) { 981ff5b8ef2SMugunthan V N priv = netdev_priv(priv->slaves[i].ndev); 982ff5b8ef2SMugunthan V N priv->coal_intvl = coal_intvl; 983ff5b8ef2SMugunthan V N } 984ff5b8ef2SMugunthan V N } else { 985ff5b8ef2SMugunthan V N priv->coal_intvl = coal_intvl; 986ff5b8ef2SMugunthan V N } 987ff5b8ef2SMugunthan V N 988ff5b8ef2SMugunthan V N return 0; 989ff5b8ef2SMugunthan V N } 990ff5b8ef2SMugunthan V N 991d9718546SMugunthan V N static int cpsw_get_sset_count(struct net_device *ndev, int sset) 992d9718546SMugunthan V N { 993d9718546SMugunthan V N switch (sset) { 994d9718546SMugunthan V N case ETH_SS_STATS: 995d9718546SMugunthan V N return CPSW_STATS_LEN; 996d9718546SMugunthan V N default: 997d9718546SMugunthan V N return -EOPNOTSUPP; 998d9718546SMugunthan V N } 999d9718546SMugunthan V N } 1000d9718546SMugunthan V N 1001d9718546SMugunthan V N static void cpsw_get_strings(struct net_device *ndev, u32 stringset, u8 *data) 1002d9718546SMugunthan V N { 1003d9718546SMugunthan V N u8 *p = data; 1004d9718546SMugunthan V N int i; 1005d9718546SMugunthan V N 1006d9718546SMugunthan V N switch (stringset) { 1007d9718546SMugunthan V N case ETH_SS_STATS: 1008d9718546SMugunthan V N for (i = 0; i < CPSW_STATS_LEN; i++) { 1009d9718546SMugunthan V N memcpy(p, cpsw_gstrings_stats[i].stat_string, 1010d9718546SMugunthan V N ETH_GSTRING_LEN); 1011d9718546SMugunthan V N p += ETH_GSTRING_LEN; 1012d9718546SMugunthan V N } 1013d9718546SMugunthan V N break; 1014d9718546SMugunthan V N } 1015d9718546SMugunthan V N } 1016d9718546SMugunthan V N 1017d9718546SMugunthan V N static void cpsw_get_ethtool_stats(struct net_device *ndev, 1018d9718546SMugunthan V N struct ethtool_stats *stats, u64 *data) 1019d9718546SMugunthan V N { 1020d9718546SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 1021d9718546SMugunthan V N struct cpdma_chan_stats rx_stats; 1022d9718546SMugunthan V N struct cpdma_chan_stats tx_stats; 1023d9718546SMugunthan V N u32 val; 1024d9718546SMugunthan V N u8 *p; 1025d9718546SMugunthan V N int i; 1026d9718546SMugunthan V N 1027d9718546SMugunthan V N /* Collect Davinci CPDMA stats for Rx and Tx Channel */ 1028d9718546SMugunthan V N cpdma_chan_get_stats(priv->rxch, &rx_stats); 1029d9718546SMugunthan V N cpdma_chan_get_stats(priv->txch, &tx_stats); 1030d9718546SMugunthan V N 1031d9718546SMugunthan V N for (i = 0; i < CPSW_STATS_LEN; i++) { 1032d9718546SMugunthan V N switch (cpsw_gstrings_stats[i].type) { 1033d9718546SMugunthan V N case CPSW_STATS: 1034d9718546SMugunthan V N val = readl(priv->hw_stats + 1035d9718546SMugunthan V N cpsw_gstrings_stats[i].stat_offset); 1036d9718546SMugunthan V N data[i] = val; 1037d9718546SMugunthan V N break; 1038d9718546SMugunthan V N 1039d9718546SMugunthan V N case CPDMA_RX_STATS: 1040d9718546SMugunthan V N p = (u8 *)&rx_stats + 1041d9718546SMugunthan V N cpsw_gstrings_stats[i].stat_offset; 1042d9718546SMugunthan V N data[i] = *(u32 *)p; 1043d9718546SMugunthan V N break; 1044d9718546SMugunthan V N 1045d9718546SMugunthan V N case CPDMA_TX_STATS: 1046d9718546SMugunthan V N p = (u8 *)&tx_stats + 1047d9718546SMugunthan V N cpsw_gstrings_stats[i].stat_offset; 1048d9718546SMugunthan V N data[i] = *(u32 *)p; 1049d9718546SMugunthan V N break; 1050d9718546SMugunthan V N } 1051d9718546SMugunthan V N } 1052d9718546SMugunthan V N } 1053d9718546SMugunthan V N 1054d9ba8f9eSMugunthan V N static int cpsw_common_res_usage_state(struct cpsw_priv *priv) 1055d9ba8f9eSMugunthan V N { 1056d9ba8f9eSMugunthan V N u32 i; 1057d9ba8f9eSMugunthan V N u32 usage_count = 0; 1058d9ba8f9eSMugunthan V N 1059d9ba8f9eSMugunthan V N if (!priv->data.dual_emac) 1060d9ba8f9eSMugunthan V N return 0; 1061d9ba8f9eSMugunthan V N 1062d9ba8f9eSMugunthan V N for (i = 0; i < priv->data.slaves; i++) 1063d9ba8f9eSMugunthan V N if (priv->slaves[i].open_stat) 1064d9ba8f9eSMugunthan V N usage_count++; 1065d9ba8f9eSMugunthan V N 1066d9ba8f9eSMugunthan V N return usage_count; 1067d9ba8f9eSMugunthan V N } 1068d9ba8f9eSMugunthan V N 1069d9ba8f9eSMugunthan V N static inline int cpsw_tx_packet_submit(struct net_device *ndev, 1070d9ba8f9eSMugunthan V N struct cpsw_priv *priv, struct sk_buff *skb) 1071d9ba8f9eSMugunthan V N { 1072d9ba8f9eSMugunthan V N if (!priv->data.dual_emac) 1073d9ba8f9eSMugunthan V N return cpdma_chan_submit(priv->txch, skb, skb->data, 1074aef614e1SSebastian Siewior skb->len, 0); 1075d9ba8f9eSMugunthan V N 1076d9ba8f9eSMugunthan V N if (ndev == cpsw_get_slave_ndev(priv, 0)) 1077d9ba8f9eSMugunthan V N return cpdma_chan_submit(priv->txch, skb, skb->data, 1078aef614e1SSebastian Siewior skb->len, 1); 1079d9ba8f9eSMugunthan V N else 1080d9ba8f9eSMugunthan V N return cpdma_chan_submit(priv->txch, skb, skb->data, 1081aef614e1SSebastian Siewior skb->len, 2); 1082d9ba8f9eSMugunthan V N } 1083d9ba8f9eSMugunthan V N 1084d9ba8f9eSMugunthan V N static inline void cpsw_add_dual_emac_def_ale_entries( 1085d9ba8f9eSMugunthan V N struct cpsw_priv *priv, struct cpsw_slave *slave, 1086d9ba8f9eSMugunthan V N u32 slave_port) 1087d9ba8f9eSMugunthan V N { 108871a2cbb7SGrygorii Strashko u32 port_mask = 1 << slave_port | ALE_PORT_HOST; 1089d9ba8f9eSMugunthan V N 1090d9ba8f9eSMugunthan V N if (priv->version == CPSW_VERSION_1) 1091d9ba8f9eSMugunthan V N slave_write(slave, slave->port_vlan, CPSW1_PORT_VLAN); 1092d9ba8f9eSMugunthan V N else 1093d9ba8f9eSMugunthan V N slave_write(slave, slave->port_vlan, CPSW2_PORT_VLAN); 1094d9ba8f9eSMugunthan V N cpsw_ale_add_vlan(priv->ale, slave->port_vlan, port_mask, 1095d9ba8f9eSMugunthan V N port_mask, port_mask, 0); 1096d9ba8f9eSMugunthan V N cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast, 1097d9ba8f9eSMugunthan V N port_mask, ALE_VLAN, slave->port_vlan, 0); 1098d9ba8f9eSMugunthan V N cpsw_ale_add_ucast(priv->ale, priv->mac_addr, 109971a2cbb7SGrygorii Strashko HOST_PORT_NUM, ALE_VLAN | ALE_SECURE, slave->port_vlan); 1100d9ba8f9eSMugunthan V N } 1101d9ba8f9eSMugunthan V N 11021e7a2e21SDaniel Mack static void soft_reset_slave(struct cpsw_slave *slave) 1103df828598SMugunthan V N { 1104df828598SMugunthan V N char name[32]; 11051e7a2e21SDaniel Mack 11061e7a2e21SDaniel Mack snprintf(name, sizeof(name), "slave-%d", slave->slave_num); 11071e7a2e21SDaniel Mack soft_reset(name, &slave->sliver->soft_reset); 11081e7a2e21SDaniel Mack } 11091e7a2e21SDaniel Mack 11101e7a2e21SDaniel Mack static void cpsw_slave_open(struct cpsw_slave *slave, struct cpsw_priv *priv) 11111e7a2e21SDaniel Mack { 1112df828598SMugunthan V N u32 slave_port; 1113df828598SMugunthan V N 11141e7a2e21SDaniel Mack soft_reset_slave(slave); 1115df828598SMugunthan V N 1116df828598SMugunthan V N /* setup priority mapping */ 1117df828598SMugunthan V N __raw_writel(RX_PRIORITY_MAPPING, &slave->sliver->rx_pri_map); 11189750a3adSRichard Cochran 11199750a3adSRichard Cochran switch (priv->version) { 11209750a3adSRichard Cochran case CPSW_VERSION_1: 11219750a3adSRichard Cochran slave_write(slave, TX_PRIORITY_MAPPING, CPSW1_TX_PRI_MAP); 11229750a3adSRichard Cochran break; 11239750a3adSRichard Cochran case CPSW_VERSION_2: 1124c193f365SMugunthan V N case CPSW_VERSION_3: 1125926489beSMugunthan V N case CPSW_VERSION_4: 11269750a3adSRichard Cochran slave_write(slave, TX_PRIORITY_MAPPING, CPSW2_TX_PRI_MAP); 11279750a3adSRichard Cochran break; 11289750a3adSRichard Cochran } 1129df828598SMugunthan V N 1130df828598SMugunthan V N /* setup max packet size, and mac address */ 1131df828598SMugunthan V N __raw_writel(priv->rx_packet_max, &slave->sliver->rx_maxlen); 1132df828598SMugunthan V N cpsw_set_slave_mac(slave, priv); 1133df828598SMugunthan V N 1134df828598SMugunthan V N slave->mac_control = 0; /* no link yet */ 1135df828598SMugunthan V N 1136df828598SMugunthan V N slave_port = cpsw_get_slave_port(priv, slave->slave_num); 1137df828598SMugunthan V N 1138d9ba8f9eSMugunthan V N if (priv->data.dual_emac) 1139d9ba8f9eSMugunthan V N cpsw_add_dual_emac_def_ale_entries(priv, slave, slave_port); 1140d9ba8f9eSMugunthan V N else 1141df828598SMugunthan V N cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast, 1142e11b220fSMugunthan V N 1 << slave_port, 0, 0, ALE_MCAST_FWD_2); 1143df828598SMugunthan V N 1144d733f754SDavid Rivshin if (slave->data->phy_node) { 1145552165bcSDavid Rivshin slave->phy = of_phy_connect(priv->ndev, slave->data->phy_node, 11469e42f715SHeiko Schocher &cpsw_adjust_link, 0, slave->data->phy_if); 1147d733f754SDavid Rivshin if (!slave->phy) { 1148d733f754SDavid Rivshin dev_err(priv->dev, "phy \"%s\" not found on slave %d\n", 1149d733f754SDavid Rivshin slave->data->phy_node->full_name, 1150d733f754SDavid Rivshin slave->slave_num); 1151d733f754SDavid Rivshin return; 1152d733f754SDavid Rivshin } 1153d733f754SDavid Rivshin } else { 1154df828598SMugunthan V N slave->phy = phy_connect(priv->ndev, slave->data->phy_id, 1155f9a8f83bSFlorian Fainelli &cpsw_adjust_link, slave->data->phy_if); 1156df828598SMugunthan V N if (IS_ERR(slave->phy)) { 1157d733f754SDavid Rivshin dev_err(priv->dev, 1158d733f754SDavid Rivshin "phy \"%s\" not found on slave %d, err %ld\n", 1159d733f754SDavid Rivshin slave->data->phy_id, slave->slave_num, 1160d733f754SDavid Rivshin PTR_ERR(slave->phy)); 1161df828598SMugunthan V N slave->phy = NULL; 1162d733f754SDavid Rivshin return; 1163d733f754SDavid Rivshin } 1164d733f754SDavid Rivshin } 1165d733f754SDavid Rivshin 11662220943aSAndrew Lunn phy_attached_info(slave->phy); 11672220943aSAndrew Lunn 1168df828598SMugunthan V N phy_start(slave->phy); 1169388367a5SMugunthan V N 1170388367a5SMugunthan V N /* Configure GMII_SEL register */ 1171d733f754SDavid Rivshin cpsw_phy_sel(&priv->pdev->dev, slave->phy->interface, slave->slave_num); 1172df828598SMugunthan V N } 1173df828598SMugunthan V N 11743b72c2feSMugunthan V N static inline void cpsw_add_default_vlan(struct cpsw_priv *priv) 11753b72c2feSMugunthan V N { 11763b72c2feSMugunthan V N const int vlan = priv->data.default_vlan; 11773b72c2feSMugunthan V N u32 reg; 11783b72c2feSMugunthan V N int i; 11791e5c4bc4SLennart Sorensen int unreg_mcast_mask; 11803b72c2feSMugunthan V N 11813b72c2feSMugunthan V N reg = (priv->version == CPSW_VERSION_1) ? CPSW1_PORT_VLAN : 11823b72c2feSMugunthan V N CPSW2_PORT_VLAN; 11833b72c2feSMugunthan V N 11843b72c2feSMugunthan V N writel(vlan, &priv->host_port_regs->port_vlan); 11853b72c2feSMugunthan V N 11860237c110SDaniel Mack for (i = 0; i < priv->data.slaves; i++) 11873b72c2feSMugunthan V N slave_write(priv->slaves + i, vlan, reg); 11883b72c2feSMugunthan V N 11891e5c4bc4SLennart Sorensen if (priv->ndev->flags & IFF_ALLMULTI) 11901e5c4bc4SLennart Sorensen unreg_mcast_mask = ALE_ALL_PORTS; 11911e5c4bc4SLennart Sorensen else 11921e5c4bc4SLennart Sorensen unreg_mcast_mask = ALE_PORT_1 | ALE_PORT_2; 11931e5c4bc4SLennart Sorensen 119461f1cef9SGrygorii Strashko cpsw_ale_add_vlan(priv->ale, vlan, ALE_ALL_PORTS, 119561f1cef9SGrygorii Strashko ALE_ALL_PORTS, ALE_ALL_PORTS, 119661f1cef9SGrygorii Strashko unreg_mcast_mask); 11973b72c2feSMugunthan V N } 11983b72c2feSMugunthan V N 1199df828598SMugunthan V N static void cpsw_init_host_port(struct cpsw_priv *priv) 1200df828598SMugunthan V N { 12013b72c2feSMugunthan V N u32 control_reg; 1202d9ba8f9eSMugunthan V N u32 fifo_mode; 12033b72c2feSMugunthan V N 1204df828598SMugunthan V N /* soft reset the controller and initialize ale */ 1205df828598SMugunthan V N soft_reset("cpsw", &priv->regs->soft_reset); 1206df828598SMugunthan V N cpsw_ale_start(priv->ale); 1207df828598SMugunthan V N 1208df828598SMugunthan V N /* switch to vlan unaware mode */ 120971a2cbb7SGrygorii Strashko cpsw_ale_control_set(priv->ale, HOST_PORT_NUM, ALE_VLAN_AWARE, 12103b72c2feSMugunthan V N CPSW_ALE_VLAN_AWARE); 12113b72c2feSMugunthan V N control_reg = readl(&priv->regs->control); 12123b72c2feSMugunthan V N control_reg |= CPSW_VLAN_AWARE; 12133b72c2feSMugunthan V N writel(control_reg, &priv->regs->control); 1214d9ba8f9eSMugunthan V N fifo_mode = (priv->data.dual_emac) ? CPSW_FIFO_DUAL_MAC_MODE : 1215d9ba8f9eSMugunthan V N CPSW_FIFO_NORMAL_MODE; 1216d9ba8f9eSMugunthan V N writel(fifo_mode, &priv->host_port_regs->tx_in_ctl); 1217df828598SMugunthan V N 1218df828598SMugunthan V N /* setup host port priority mapping */ 1219df828598SMugunthan V N __raw_writel(CPDMA_TX_PRIORITY_MAP, 1220df828598SMugunthan V N &priv->host_port_regs->cpdma_tx_pri_map); 1221df828598SMugunthan V N __raw_writel(0, &priv->host_port_regs->cpdma_rx_chan_map); 1222df828598SMugunthan V N 122371a2cbb7SGrygorii Strashko cpsw_ale_control_set(priv->ale, HOST_PORT_NUM, 1224df828598SMugunthan V N ALE_PORT_STATE, ALE_PORT_STATE_FORWARD); 1225df828598SMugunthan V N 1226d9ba8f9eSMugunthan V N if (!priv->data.dual_emac) { 122771a2cbb7SGrygorii Strashko cpsw_ale_add_ucast(priv->ale, priv->mac_addr, HOST_PORT_NUM, 1228d9ba8f9eSMugunthan V N 0, 0); 1229df828598SMugunthan V N cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast, 123071a2cbb7SGrygorii Strashko ALE_PORT_HOST, 0, 0, ALE_MCAST_FWD_2); 1231df828598SMugunthan V N } 1232d9ba8f9eSMugunthan V N } 1233df828598SMugunthan V N 1234aacebbf8SSebastian Siewior static void cpsw_slave_stop(struct cpsw_slave *slave, struct cpsw_priv *priv) 1235aacebbf8SSebastian Siewior { 12363995d265SSchuyler Patton u32 slave_port; 12373995d265SSchuyler Patton 12383995d265SSchuyler Patton slave_port = cpsw_get_slave_port(priv, slave->slave_num); 12393995d265SSchuyler Patton 1240aacebbf8SSebastian Siewior if (!slave->phy) 1241aacebbf8SSebastian Siewior return; 1242aacebbf8SSebastian Siewior phy_stop(slave->phy); 1243aacebbf8SSebastian Siewior phy_disconnect(slave->phy); 1244aacebbf8SSebastian Siewior slave->phy = NULL; 12453995d265SSchuyler Patton cpsw_ale_control_set(priv->ale, slave_port, 12463995d265SSchuyler Patton ALE_PORT_STATE, ALE_PORT_STATE_DISABLE); 12471f95ba00SGrygorii Strashko soft_reset_slave(slave); 1248aacebbf8SSebastian Siewior } 1249aacebbf8SSebastian Siewior 1250df828598SMugunthan V N static int cpsw_ndo_open(struct net_device *ndev) 1251df828598SMugunthan V N { 1252df828598SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 1253df828598SMugunthan V N int i, ret; 1254df828598SMugunthan V N u32 reg; 1255df828598SMugunthan V N 1256108a6537SGrygorii Strashko ret = pm_runtime_get_sync(&priv->pdev->dev); 1257108a6537SGrygorii Strashko if (ret < 0) { 1258108a6537SGrygorii Strashko pm_runtime_put_noidle(&priv->pdev->dev); 1259108a6537SGrygorii Strashko return ret; 1260108a6537SGrygorii Strashko } 12613fa88c51SGrygorii Strashko 1262d9ba8f9eSMugunthan V N if (!cpsw_common_res_usage_state(priv)) 1263df828598SMugunthan V N cpsw_intr_disable(priv); 1264df828598SMugunthan V N netif_carrier_off(ndev); 1265df828598SMugunthan V N 1266549985eeSRichard Cochran reg = priv->version; 1267df828598SMugunthan V N 1268df828598SMugunthan V N dev_info(priv->dev, "initializing cpsw version %d.%d (%d)\n", 1269df828598SMugunthan V N CPSW_MAJOR_VERSION(reg), CPSW_MINOR_VERSION(reg), 1270df828598SMugunthan V N CPSW_RTL_VERSION(reg)); 1271df828598SMugunthan V N 1272df828598SMugunthan V N /* initialize host and slave ports */ 1273d9ba8f9eSMugunthan V N if (!cpsw_common_res_usage_state(priv)) 1274df828598SMugunthan V N cpsw_init_host_port(priv); 1275df828598SMugunthan V N for_each_slave(priv, cpsw_slave_open, priv); 1276df828598SMugunthan V N 12773b72c2feSMugunthan V N /* Add default VLAN */ 1278e6afea0bSMugunthan V N if (!priv->data.dual_emac) 12793b72c2feSMugunthan V N cpsw_add_default_vlan(priv); 1280e6afea0bSMugunthan V N else 1281e6afea0bSMugunthan V N cpsw_ale_add_vlan(priv->ale, priv->data.default_vlan, 128261f1cef9SGrygorii Strashko ALE_ALL_PORTS, ALE_ALL_PORTS, 0, 0); 12833b72c2feSMugunthan V N 1284d9ba8f9eSMugunthan V N if (!cpsw_common_res_usage_state(priv)) { 1285d354eb85SMugunthan V N struct cpsw_priv *priv_sl0 = cpsw_get_slave_priv(priv, 0); 12861793331eSIvan Khoronzhuk int buf_num; 1287d354eb85SMugunthan V N 1288df828598SMugunthan V N /* setup tx dma to fixed prio and zero offset */ 1289df828598SMugunthan V N cpdma_control_set(priv->dma, CPDMA_TX_PRIO_FIXED, 1); 1290df828598SMugunthan V N cpdma_control_set(priv->dma, CPDMA_RX_BUFFER_OFFSET, 0); 1291df828598SMugunthan V N 1292d9ba8f9eSMugunthan V N /* disable priority elevation */ 1293df828598SMugunthan V N __raw_writel(0, &priv->regs->ptype); 1294df828598SMugunthan V N 1295d9ba8f9eSMugunthan V N /* enable statistics collection only on all ports */ 1296df828598SMugunthan V N __raw_writel(0x7, &priv->regs->stat_port_en); 1297df828598SMugunthan V N 12981923d6e4SMugunthan V N /* Enable internal fifo flow control */ 12991923d6e4SMugunthan V N writel(0x7, &priv->regs->flow_control); 13001923d6e4SMugunthan V N 130132a7432cSMugunthan V N napi_enable(&priv_sl0->napi_rx); 130232a7432cSMugunthan V N napi_enable(&priv_sl0->napi_tx); 1303d354eb85SMugunthan V N 13047da11600SMugunthan V N if (priv_sl0->tx_irq_disabled) { 13057da11600SMugunthan V N priv_sl0->tx_irq_disabled = false; 13067da11600SMugunthan V N enable_irq(priv->irqs_table[1]); 13077da11600SMugunthan V N } 13087da11600SMugunthan V N 13097da11600SMugunthan V N if (priv_sl0->rx_irq_disabled) { 13107da11600SMugunthan V N priv_sl0->rx_irq_disabled = false; 13117da11600SMugunthan V N enable_irq(priv->irqs_table[0]); 13127da11600SMugunthan V N } 13137da11600SMugunthan V N 13141793331eSIvan Khoronzhuk buf_num = cpdma_chan_get_rx_buf_num(priv->dma); 13151793331eSIvan Khoronzhuk for (i = 0; i < buf_num; i++) { 1316df828598SMugunthan V N struct sk_buff *skb; 1317df828598SMugunthan V N 1318df828598SMugunthan V N ret = -ENOMEM; 1319aacebbf8SSebastian Siewior skb = __netdev_alloc_skb_ip_align(priv->ndev, 1320aacebbf8SSebastian Siewior priv->rx_packet_max, GFP_KERNEL); 1321df828598SMugunthan V N if (!skb) 1322aacebbf8SSebastian Siewior goto err_cleanup; 1323df828598SMugunthan V N ret = cpdma_chan_submit(priv->rxch, skb, skb->data, 1324aef614e1SSebastian Siewior skb_tailroom(skb), 0); 1325aacebbf8SSebastian Siewior if (ret < 0) { 1326aacebbf8SSebastian Siewior kfree_skb(skb); 1327aacebbf8SSebastian Siewior goto err_cleanup; 1328aacebbf8SSebastian Siewior } 1329254a49d5SGrygorii Strashko kmemleak_not_leak(skb); 1330df828598SMugunthan V N } 1331d9ba8f9eSMugunthan V N /* continue even if we didn't manage to submit all 1332d9ba8f9eSMugunthan V N * receive descs 1333d9ba8f9eSMugunthan V N */ 1334df828598SMugunthan V N cpsw_info(priv, ifup, "submitted %d rx descriptors\n", i); 1335f280e89aSMugunthan V N 1336f280e89aSMugunthan V N if (cpts_register(&priv->pdev->dev, priv->cpts, 1337f280e89aSMugunthan V N priv->data.cpts_clock_mult, 1338f280e89aSMugunthan V N priv->data.cpts_clock_shift)) 1339f280e89aSMugunthan V N dev_err(priv->dev, "error registering cpts device\n"); 1340f280e89aSMugunthan V N 1341d9ba8f9eSMugunthan V N } 1342df828598SMugunthan V N 1343ff5b8ef2SMugunthan V N /* Enable Interrupt pacing if configured */ 1344ff5b8ef2SMugunthan V N if (priv->coal_intvl != 0) { 1345ff5b8ef2SMugunthan V N struct ethtool_coalesce coal; 1346ff5b8ef2SMugunthan V N 13478478b6cdSIvan Khoronzhuk coal.rx_coalesce_usecs = priv->coal_intvl; 1348ff5b8ef2SMugunthan V N cpsw_set_coalesce(ndev, &coal); 1349ff5b8ef2SMugunthan V N } 1350ff5b8ef2SMugunthan V N 1351f63a975eSMugunthan V N cpdma_ctlr_start(priv->dma); 1352f63a975eSMugunthan V N cpsw_intr_enable(priv); 1353f63a975eSMugunthan V N 1354d9ba8f9eSMugunthan V N if (priv->data.dual_emac) 1355d9ba8f9eSMugunthan V N priv->slaves[priv->emac_port].open_stat = true; 1356df828598SMugunthan V N return 0; 1357df828598SMugunthan V N 1358aacebbf8SSebastian Siewior err_cleanup: 1359aacebbf8SSebastian Siewior cpdma_ctlr_stop(priv->dma); 1360aacebbf8SSebastian Siewior for_each_slave(priv, cpsw_slave_stop, priv); 1361aacebbf8SSebastian Siewior pm_runtime_put_sync(&priv->pdev->dev); 1362aacebbf8SSebastian Siewior netif_carrier_off(priv->ndev); 1363aacebbf8SSebastian Siewior return ret; 1364df828598SMugunthan V N } 1365df828598SMugunthan V N 1366df828598SMugunthan V N static int cpsw_ndo_stop(struct net_device *ndev) 1367df828598SMugunthan V N { 1368df828598SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 1369df828598SMugunthan V N 1370df828598SMugunthan V N cpsw_info(priv, ifdown, "shutting down cpsw device\n"); 1371df828598SMugunthan V N netif_stop_queue(priv->ndev); 1372df828598SMugunthan V N netif_carrier_off(priv->ndev); 1373d9ba8f9eSMugunthan V N 1374d9ba8f9eSMugunthan V N if (cpsw_common_res_usage_state(priv) <= 1) { 1375d354eb85SMugunthan V N struct cpsw_priv *priv_sl0 = cpsw_get_slave_priv(priv, 0); 1376d354eb85SMugunthan V N 137732a7432cSMugunthan V N napi_disable(&priv_sl0->napi_rx); 137832a7432cSMugunthan V N napi_disable(&priv_sl0->napi_tx); 1379f280e89aSMugunthan V N cpts_unregister(priv->cpts); 138071380f9bSMugunthan V N cpsw_intr_disable(priv); 138171380f9bSMugunthan V N cpdma_ctlr_stop(priv->dma); 1382df828598SMugunthan V N cpsw_ale_stop(priv->ale); 1383d9ba8f9eSMugunthan V N } 1384df828598SMugunthan V N for_each_slave(priv, cpsw_slave_stop, priv); 1385f150bd7fSMugunthan V N pm_runtime_put_sync(&priv->pdev->dev); 1386d9ba8f9eSMugunthan V N if (priv->data.dual_emac) 1387d9ba8f9eSMugunthan V N priv->slaves[priv->emac_port].open_stat = false; 1388df828598SMugunthan V N return 0; 1389df828598SMugunthan V N } 1390df828598SMugunthan V N 1391df828598SMugunthan V N static netdev_tx_t cpsw_ndo_start_xmit(struct sk_buff *skb, 1392df828598SMugunthan V N struct net_device *ndev) 1393df828598SMugunthan V N { 1394df828598SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 1395df828598SMugunthan V N int ret; 1396df828598SMugunthan V N 1397860e9538SFlorian Westphal netif_trans_update(ndev); 1398df828598SMugunthan V N 1399df828598SMugunthan V N if (skb_padto(skb, CPSW_MIN_PACKET_SIZE)) { 1400df828598SMugunthan V N cpsw_err(priv, tx_err, "packet pad failed\n"); 14018dc43ddcSTobias Klauser ndev->stats.tx_dropped++; 1402df828598SMugunthan V N return NETDEV_TX_OK; 1403df828598SMugunthan V N } 1404df828598SMugunthan V N 14059232b16dSMugunthan V N if (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP && 14069232b16dSMugunthan V N priv->cpts->tx_enable) 14072e5b38abSRichard Cochran skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 14082e5b38abSRichard Cochran 14092e5b38abSRichard Cochran skb_tx_timestamp(skb); 14102e5b38abSRichard Cochran 1411d9ba8f9eSMugunthan V N ret = cpsw_tx_packet_submit(ndev, priv, skb); 1412df828598SMugunthan V N if (unlikely(ret != 0)) { 1413df828598SMugunthan V N cpsw_err(priv, tx_err, "desc submit failed\n"); 1414df828598SMugunthan V N goto fail; 1415df828598SMugunthan V N } 1416df828598SMugunthan V N 1417fae50823SMugunthan V N /* If there is no more tx desc left free then we need to 1418fae50823SMugunthan V N * tell the kernel to stop sending us tx frames. 1419fae50823SMugunthan V N */ 1420d35162f8SDaniel Mack if (unlikely(!cpdma_check_free_tx_desc(priv->txch))) 1421fae50823SMugunthan V N netif_stop_queue(ndev); 1422fae50823SMugunthan V N 1423df828598SMugunthan V N return NETDEV_TX_OK; 1424df828598SMugunthan V N fail: 14258dc43ddcSTobias Klauser ndev->stats.tx_dropped++; 1426df828598SMugunthan V N netif_stop_queue(ndev); 1427df828598SMugunthan V N return NETDEV_TX_BUSY; 1428df828598SMugunthan V N } 1429df828598SMugunthan V N 14302e5b38abSRichard Cochran #ifdef CONFIG_TI_CPTS 14312e5b38abSRichard Cochran 14322e5b38abSRichard Cochran static void cpsw_hwtstamp_v1(struct cpsw_priv *priv) 14332e5b38abSRichard Cochran { 1434e86ac13bSMugunthan V N struct cpsw_slave *slave = &priv->slaves[priv->data.active_slave]; 14352e5b38abSRichard Cochran u32 ts_en, seq_id; 14362e5b38abSRichard Cochran 14379232b16dSMugunthan V N if (!priv->cpts->tx_enable && !priv->cpts->rx_enable) { 14382e5b38abSRichard Cochran slave_write(slave, 0, CPSW1_TS_CTL); 14392e5b38abSRichard Cochran return; 14402e5b38abSRichard Cochran } 14412e5b38abSRichard Cochran 14422e5b38abSRichard Cochran seq_id = (30 << CPSW_V1_SEQ_ID_OFS_SHIFT) | ETH_P_1588; 14432e5b38abSRichard Cochran ts_en = EVENT_MSG_BITS << CPSW_V1_MSG_TYPE_OFS; 14442e5b38abSRichard Cochran 14459232b16dSMugunthan V N if (priv->cpts->tx_enable) 14462e5b38abSRichard Cochran ts_en |= CPSW_V1_TS_TX_EN; 14472e5b38abSRichard Cochran 14489232b16dSMugunthan V N if (priv->cpts->rx_enable) 14492e5b38abSRichard Cochran ts_en |= CPSW_V1_TS_RX_EN; 14502e5b38abSRichard Cochran 14512e5b38abSRichard Cochran slave_write(slave, ts_en, CPSW1_TS_CTL); 14522e5b38abSRichard Cochran slave_write(slave, seq_id, CPSW1_TS_SEQ_LTYPE); 14532e5b38abSRichard Cochran } 14542e5b38abSRichard Cochran 14552e5b38abSRichard Cochran static void cpsw_hwtstamp_v2(struct cpsw_priv *priv) 14562e5b38abSRichard Cochran { 1457d9ba8f9eSMugunthan V N struct cpsw_slave *slave; 14582e5b38abSRichard Cochran u32 ctrl, mtype; 14592e5b38abSRichard Cochran 1460d9ba8f9eSMugunthan V N if (priv->data.dual_emac) 1461d9ba8f9eSMugunthan V N slave = &priv->slaves[priv->emac_port]; 1462d9ba8f9eSMugunthan V N else 1463e86ac13bSMugunthan V N slave = &priv->slaves[priv->data.active_slave]; 1464d9ba8f9eSMugunthan V N 14652e5b38abSRichard Cochran ctrl = slave_read(slave, CPSW2_CONTROL); 146609c55372SGeorge Cherian switch (priv->version) { 146709c55372SGeorge Cherian case CPSW_VERSION_2: 146809c55372SGeorge Cherian ctrl &= ~CTRL_V2_ALL_TS_MASK; 14692e5b38abSRichard Cochran 14709232b16dSMugunthan V N if (priv->cpts->tx_enable) 147109c55372SGeorge Cherian ctrl |= CTRL_V2_TX_TS_BITS; 14722e5b38abSRichard Cochran 14739232b16dSMugunthan V N if (priv->cpts->rx_enable) 147409c55372SGeorge Cherian ctrl |= CTRL_V2_RX_TS_BITS; 147509c55372SGeorge Cherian break; 147609c55372SGeorge Cherian case CPSW_VERSION_3: 147709c55372SGeorge Cherian default: 147809c55372SGeorge Cherian ctrl &= ~CTRL_V3_ALL_TS_MASK; 147909c55372SGeorge Cherian 148009c55372SGeorge Cherian if (priv->cpts->tx_enable) 148109c55372SGeorge Cherian ctrl |= CTRL_V3_TX_TS_BITS; 148209c55372SGeorge Cherian 148309c55372SGeorge Cherian if (priv->cpts->rx_enable) 148409c55372SGeorge Cherian ctrl |= CTRL_V3_RX_TS_BITS; 148509c55372SGeorge Cherian break; 148609c55372SGeorge Cherian } 14872e5b38abSRichard Cochran 14882e5b38abSRichard Cochran mtype = (30 << TS_SEQ_ID_OFFSET_SHIFT) | EVENT_MSG_BITS; 14892e5b38abSRichard Cochran 14902e5b38abSRichard Cochran slave_write(slave, mtype, CPSW2_TS_SEQ_MTYPE); 14912e5b38abSRichard Cochran slave_write(slave, ctrl, CPSW2_CONTROL); 14922e5b38abSRichard Cochran __raw_writel(ETH_P_1588, &priv->regs->ts_ltype); 14932e5b38abSRichard Cochran } 14942e5b38abSRichard Cochran 1495a5b4145bSBen Hutchings static int cpsw_hwtstamp_set(struct net_device *dev, struct ifreq *ifr) 14962e5b38abSRichard Cochran { 14973177bf6fSMugunthan V N struct cpsw_priv *priv = netdev_priv(dev); 14989232b16dSMugunthan V N struct cpts *cpts = priv->cpts; 14992e5b38abSRichard Cochran struct hwtstamp_config cfg; 15002e5b38abSRichard Cochran 15012ee91e54SBen Hutchings if (priv->version != CPSW_VERSION_1 && 1502f7d403cbSGeorge Cherian priv->version != CPSW_VERSION_2 && 1503f7d403cbSGeorge Cherian priv->version != CPSW_VERSION_3) 15042ee91e54SBen Hutchings return -EOPNOTSUPP; 15052ee91e54SBen Hutchings 15062e5b38abSRichard Cochran if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg))) 15072e5b38abSRichard Cochran return -EFAULT; 15082e5b38abSRichard Cochran 15092e5b38abSRichard Cochran /* reserved for future extensions */ 15102e5b38abSRichard Cochran if (cfg.flags) 15112e5b38abSRichard Cochran return -EINVAL; 15122e5b38abSRichard Cochran 15132ee91e54SBen Hutchings if (cfg.tx_type != HWTSTAMP_TX_OFF && cfg.tx_type != HWTSTAMP_TX_ON) 15142e5b38abSRichard Cochran return -ERANGE; 15152e5b38abSRichard Cochran 15162e5b38abSRichard Cochran switch (cfg.rx_filter) { 15172e5b38abSRichard Cochran case HWTSTAMP_FILTER_NONE: 15182e5b38abSRichard Cochran cpts->rx_enable = 0; 15192e5b38abSRichard Cochran break; 15202e5b38abSRichard Cochran case HWTSTAMP_FILTER_ALL: 15212e5b38abSRichard Cochran case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: 15222e5b38abSRichard Cochran case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: 15232e5b38abSRichard Cochran case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: 15242e5b38abSRichard Cochran return -ERANGE; 15252e5b38abSRichard Cochran case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: 15262e5b38abSRichard Cochran case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 15272e5b38abSRichard Cochran case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 15282e5b38abSRichard Cochran case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: 15292e5b38abSRichard Cochran case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: 15302e5b38abSRichard Cochran case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: 15312e5b38abSRichard Cochran case HWTSTAMP_FILTER_PTP_V2_EVENT: 15322e5b38abSRichard Cochran case HWTSTAMP_FILTER_PTP_V2_SYNC: 15332e5b38abSRichard Cochran case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 15342e5b38abSRichard Cochran cpts->rx_enable = 1; 15352e5b38abSRichard Cochran cfg.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT; 15362e5b38abSRichard Cochran break; 15372e5b38abSRichard Cochran default: 15382e5b38abSRichard Cochran return -ERANGE; 15392e5b38abSRichard Cochran } 15402e5b38abSRichard Cochran 15412ee91e54SBen Hutchings cpts->tx_enable = cfg.tx_type == HWTSTAMP_TX_ON; 15422ee91e54SBen Hutchings 15432e5b38abSRichard Cochran switch (priv->version) { 15442e5b38abSRichard Cochran case CPSW_VERSION_1: 15452e5b38abSRichard Cochran cpsw_hwtstamp_v1(priv); 15462e5b38abSRichard Cochran break; 15472e5b38abSRichard Cochran case CPSW_VERSION_2: 1548f7d403cbSGeorge Cherian case CPSW_VERSION_3: 15492e5b38abSRichard Cochran cpsw_hwtstamp_v2(priv); 15502e5b38abSRichard Cochran break; 15512e5b38abSRichard Cochran default: 15522ee91e54SBen Hutchings WARN_ON(1); 15532e5b38abSRichard Cochran } 15542e5b38abSRichard Cochran 15552e5b38abSRichard Cochran return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0; 15562e5b38abSRichard Cochran } 15572e5b38abSRichard Cochran 1558a5b4145bSBen Hutchings static int cpsw_hwtstamp_get(struct net_device *dev, struct ifreq *ifr) 1559a5b4145bSBen Hutchings { 1560a5b4145bSBen Hutchings struct cpsw_priv *priv = netdev_priv(dev); 1561a5b4145bSBen Hutchings struct cpts *cpts = priv->cpts; 1562a5b4145bSBen Hutchings struct hwtstamp_config cfg; 1563a5b4145bSBen Hutchings 1564a5b4145bSBen Hutchings if (priv->version != CPSW_VERSION_1 && 1565f7d403cbSGeorge Cherian priv->version != CPSW_VERSION_2 && 1566f7d403cbSGeorge Cherian priv->version != CPSW_VERSION_3) 1567a5b4145bSBen Hutchings return -EOPNOTSUPP; 1568a5b4145bSBen Hutchings 1569a5b4145bSBen Hutchings cfg.flags = 0; 1570a5b4145bSBen Hutchings cfg.tx_type = cpts->tx_enable ? HWTSTAMP_TX_ON : HWTSTAMP_TX_OFF; 1571a5b4145bSBen Hutchings cfg.rx_filter = (cpts->rx_enable ? 1572a5b4145bSBen Hutchings HWTSTAMP_FILTER_PTP_V2_EVENT : HWTSTAMP_FILTER_NONE); 1573a5b4145bSBen Hutchings 1574a5b4145bSBen Hutchings return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0; 1575a5b4145bSBen Hutchings } 1576a5b4145bSBen Hutchings 15772e5b38abSRichard Cochran #endif /*CONFIG_TI_CPTS*/ 15782e5b38abSRichard Cochran 15792e5b38abSRichard Cochran static int cpsw_ndo_ioctl(struct net_device *dev, struct ifreq *req, int cmd) 15802e5b38abSRichard Cochran { 158111f2c988SMugunthan V N struct cpsw_priv *priv = netdev_priv(dev); 158211f2c988SMugunthan V N int slave_no = cpsw_slave_index(priv); 158311f2c988SMugunthan V N 15842e5b38abSRichard Cochran if (!netif_running(dev)) 15852e5b38abSRichard Cochran return -EINVAL; 15862e5b38abSRichard Cochran 158711f2c988SMugunthan V N switch (cmd) { 15882e5b38abSRichard Cochran #ifdef CONFIG_TI_CPTS 158911f2c988SMugunthan V N case SIOCSHWTSTAMP: 1590a5b4145bSBen Hutchings return cpsw_hwtstamp_set(dev, req); 1591a5b4145bSBen Hutchings case SIOCGHWTSTAMP: 1592a5b4145bSBen Hutchings return cpsw_hwtstamp_get(dev, req); 15932e5b38abSRichard Cochran #endif 15942e5b38abSRichard Cochran } 15952e5b38abSRichard Cochran 1596c1b59947SStefan Sørensen if (!priv->slaves[slave_no].phy) 1597c1b59947SStefan Sørensen return -EOPNOTSUPP; 1598c1b59947SStefan Sørensen return phy_mii_ioctl(priv->slaves[slave_no].phy, req, cmd); 159911f2c988SMugunthan V N } 160011f2c988SMugunthan V N 1601df828598SMugunthan V N static void cpsw_ndo_tx_timeout(struct net_device *ndev) 1602df828598SMugunthan V N { 1603df828598SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 1604df828598SMugunthan V N 1605df828598SMugunthan V N cpsw_err(priv, tx_err, "transmit timeout, restarting dma\n"); 16068dc43ddcSTobias Klauser ndev->stats.tx_errors++; 1607df828598SMugunthan V N cpsw_intr_disable(priv); 1608df828598SMugunthan V N cpdma_chan_stop(priv->txch); 1609df828598SMugunthan V N cpdma_chan_start(priv->txch); 1610df828598SMugunthan V N cpsw_intr_enable(priv); 1611df828598SMugunthan V N } 1612df828598SMugunthan V N 1613dcfd8d58SMugunthan V N static int cpsw_ndo_set_mac_address(struct net_device *ndev, void *p) 1614dcfd8d58SMugunthan V N { 1615dcfd8d58SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 1616dcfd8d58SMugunthan V N struct sockaddr *addr = (struct sockaddr *)p; 1617dcfd8d58SMugunthan V N int flags = 0; 1618dcfd8d58SMugunthan V N u16 vid = 0; 1619a6c5d14fSGrygorii Strashko int ret; 1620dcfd8d58SMugunthan V N 1621dcfd8d58SMugunthan V N if (!is_valid_ether_addr(addr->sa_data)) 1622dcfd8d58SMugunthan V N return -EADDRNOTAVAIL; 1623dcfd8d58SMugunthan V N 1624a6c5d14fSGrygorii Strashko ret = pm_runtime_get_sync(&priv->pdev->dev); 1625a6c5d14fSGrygorii Strashko if (ret < 0) { 1626a6c5d14fSGrygorii Strashko pm_runtime_put_noidle(&priv->pdev->dev); 1627a6c5d14fSGrygorii Strashko return ret; 1628a6c5d14fSGrygorii Strashko } 1629a6c5d14fSGrygorii Strashko 1630dcfd8d58SMugunthan V N if (priv->data.dual_emac) { 1631dcfd8d58SMugunthan V N vid = priv->slaves[priv->emac_port].port_vlan; 1632dcfd8d58SMugunthan V N flags = ALE_VLAN; 1633dcfd8d58SMugunthan V N } 1634dcfd8d58SMugunthan V N 163571a2cbb7SGrygorii Strashko cpsw_ale_del_ucast(priv->ale, priv->mac_addr, HOST_PORT_NUM, 1636dcfd8d58SMugunthan V N flags, vid); 163771a2cbb7SGrygorii Strashko cpsw_ale_add_ucast(priv->ale, addr->sa_data, HOST_PORT_NUM, 1638dcfd8d58SMugunthan V N flags, vid); 1639dcfd8d58SMugunthan V N 1640dcfd8d58SMugunthan V N memcpy(priv->mac_addr, addr->sa_data, ETH_ALEN); 1641dcfd8d58SMugunthan V N memcpy(ndev->dev_addr, priv->mac_addr, ETH_ALEN); 1642dcfd8d58SMugunthan V N for_each_slave(priv, cpsw_set_slave_mac, priv); 1643dcfd8d58SMugunthan V N 1644a6c5d14fSGrygorii Strashko pm_runtime_put(&priv->pdev->dev); 1645a6c5d14fSGrygorii Strashko 1646dcfd8d58SMugunthan V N return 0; 1647dcfd8d58SMugunthan V N } 1648dcfd8d58SMugunthan V N 1649df828598SMugunthan V N #ifdef CONFIG_NET_POLL_CONTROLLER 1650df828598SMugunthan V N static void cpsw_ndo_poll_controller(struct net_device *ndev) 1651df828598SMugunthan V N { 1652df828598SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 1653df828598SMugunthan V N 1654df828598SMugunthan V N cpsw_intr_disable(priv); 165592cb13fbSFelipe Balbi cpsw_rx_interrupt(priv->irqs_table[0], priv); 165692cb13fbSFelipe Balbi cpsw_tx_interrupt(priv->irqs_table[1], priv); 1657df828598SMugunthan V N cpsw_intr_enable(priv); 1658df828598SMugunthan V N } 1659df828598SMugunthan V N #endif 1660df828598SMugunthan V N 16613b72c2feSMugunthan V N static inline int cpsw_add_vlan_ale_entry(struct cpsw_priv *priv, 16623b72c2feSMugunthan V N unsigned short vid) 16633b72c2feSMugunthan V N { 16643b72c2feSMugunthan V N int ret; 16659f6bd8faSMugunthan V N int unreg_mcast_mask = 0; 16669f6bd8faSMugunthan V N u32 port_mask; 16679f6bd8faSMugunthan V N 16689f6bd8faSMugunthan V N if (priv->data.dual_emac) { 16699f6bd8faSMugunthan V N port_mask = (1 << (priv->emac_port + 1)) | ALE_PORT_HOST; 16709f6bd8faSMugunthan V N 16719f6bd8faSMugunthan V N if (priv->ndev->flags & IFF_ALLMULTI) 16729f6bd8faSMugunthan V N unreg_mcast_mask = port_mask; 16739f6bd8faSMugunthan V N } else { 16749f6bd8faSMugunthan V N port_mask = ALE_ALL_PORTS; 16751e5c4bc4SLennart Sorensen 16761e5c4bc4SLennart Sorensen if (priv->ndev->flags & IFF_ALLMULTI) 16771e5c4bc4SLennart Sorensen unreg_mcast_mask = ALE_ALL_PORTS; 16781e5c4bc4SLennart Sorensen else 16791e5c4bc4SLennart Sorensen unreg_mcast_mask = ALE_PORT_1 | ALE_PORT_2; 16809f6bd8faSMugunthan V N } 16813b72c2feSMugunthan V N 16829f6bd8faSMugunthan V N ret = cpsw_ale_add_vlan(priv->ale, vid, port_mask, 0, port_mask, 168361f1cef9SGrygorii Strashko unreg_mcast_mask); 16843b72c2feSMugunthan V N if (ret != 0) 16853b72c2feSMugunthan V N return ret; 16863b72c2feSMugunthan V N 16873b72c2feSMugunthan V N ret = cpsw_ale_add_ucast(priv->ale, priv->mac_addr, 168871a2cbb7SGrygorii Strashko HOST_PORT_NUM, ALE_VLAN, vid); 16893b72c2feSMugunthan V N if (ret != 0) 16903b72c2feSMugunthan V N goto clean_vid; 16913b72c2feSMugunthan V N 16923b72c2feSMugunthan V N ret = cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast, 16939f6bd8faSMugunthan V N port_mask, ALE_VLAN, vid, 0); 16943b72c2feSMugunthan V N if (ret != 0) 16953b72c2feSMugunthan V N goto clean_vlan_ucast; 16963b72c2feSMugunthan V N return 0; 16973b72c2feSMugunthan V N 16983b72c2feSMugunthan V N clean_vlan_ucast: 16993b72c2feSMugunthan V N cpsw_ale_del_ucast(priv->ale, priv->mac_addr, 170071a2cbb7SGrygorii Strashko HOST_PORT_NUM, ALE_VLAN, vid); 17013b72c2feSMugunthan V N clean_vid: 17023b72c2feSMugunthan V N cpsw_ale_del_vlan(priv->ale, vid, 0); 17033b72c2feSMugunthan V N return ret; 17043b72c2feSMugunthan V N } 17053b72c2feSMugunthan V N 17063b72c2feSMugunthan V N static int cpsw_ndo_vlan_rx_add_vid(struct net_device *ndev, 170780d5c368SPatrick McHardy __be16 proto, u16 vid) 17083b72c2feSMugunthan V N { 17093b72c2feSMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 1710a6c5d14fSGrygorii Strashko int ret; 17113b72c2feSMugunthan V N 17123b72c2feSMugunthan V N if (vid == priv->data.default_vlan) 17133b72c2feSMugunthan V N return 0; 17143b72c2feSMugunthan V N 1715a6c5d14fSGrygorii Strashko ret = pm_runtime_get_sync(&priv->pdev->dev); 1716a6c5d14fSGrygorii Strashko if (ret < 0) { 1717a6c5d14fSGrygorii Strashko pm_runtime_put_noidle(&priv->pdev->dev); 1718a6c5d14fSGrygorii Strashko return ret; 1719a6c5d14fSGrygorii Strashko } 1720a6c5d14fSGrygorii Strashko 172102a54164SMugunthan V N if (priv->data.dual_emac) { 172202a54164SMugunthan V N /* In dual EMAC, reserved VLAN id should not be used for 172302a54164SMugunthan V N * creating VLAN interfaces as this can break the dual 172402a54164SMugunthan V N * EMAC port separation 172502a54164SMugunthan V N */ 172602a54164SMugunthan V N int i; 172702a54164SMugunthan V N 172802a54164SMugunthan V N for (i = 0; i < priv->data.slaves; i++) { 172902a54164SMugunthan V N if (vid == priv->slaves[i].port_vlan) 173002a54164SMugunthan V N return -EINVAL; 173102a54164SMugunthan V N } 173202a54164SMugunthan V N } 173302a54164SMugunthan V N 17343b72c2feSMugunthan V N dev_info(priv->dev, "Adding vlanid %d to vlan filter\n", vid); 1735a6c5d14fSGrygorii Strashko ret = cpsw_add_vlan_ale_entry(priv, vid); 1736a6c5d14fSGrygorii Strashko 1737a6c5d14fSGrygorii Strashko pm_runtime_put(&priv->pdev->dev); 1738a6c5d14fSGrygorii Strashko return ret; 17393b72c2feSMugunthan V N } 17403b72c2feSMugunthan V N 17413b72c2feSMugunthan V N static int cpsw_ndo_vlan_rx_kill_vid(struct net_device *ndev, 174280d5c368SPatrick McHardy __be16 proto, u16 vid) 17433b72c2feSMugunthan V N { 17443b72c2feSMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 17453b72c2feSMugunthan V N int ret; 17463b72c2feSMugunthan V N 17473b72c2feSMugunthan V N if (vid == priv->data.default_vlan) 17483b72c2feSMugunthan V N return 0; 17493b72c2feSMugunthan V N 1750a6c5d14fSGrygorii Strashko ret = pm_runtime_get_sync(&priv->pdev->dev); 1751a6c5d14fSGrygorii Strashko if (ret < 0) { 1752a6c5d14fSGrygorii Strashko pm_runtime_put_noidle(&priv->pdev->dev); 1753a6c5d14fSGrygorii Strashko return ret; 1754a6c5d14fSGrygorii Strashko } 1755a6c5d14fSGrygorii Strashko 175602a54164SMugunthan V N if (priv->data.dual_emac) { 175702a54164SMugunthan V N int i; 175802a54164SMugunthan V N 175902a54164SMugunthan V N for (i = 0; i < priv->data.slaves; i++) { 176002a54164SMugunthan V N if (vid == priv->slaves[i].port_vlan) 176102a54164SMugunthan V N return -EINVAL; 176202a54164SMugunthan V N } 176302a54164SMugunthan V N } 176402a54164SMugunthan V N 17653b72c2feSMugunthan V N dev_info(priv->dev, "removing vlanid %d from vlan filter\n", vid); 17663b72c2feSMugunthan V N ret = cpsw_ale_del_vlan(priv->ale, vid, 0); 17673b72c2feSMugunthan V N if (ret != 0) 17683b72c2feSMugunthan V N return ret; 17693b72c2feSMugunthan V N 17703b72c2feSMugunthan V N ret = cpsw_ale_del_ucast(priv->ale, priv->mac_addr, 177161f1cef9SGrygorii Strashko HOST_PORT_NUM, ALE_VLAN, vid); 17723b72c2feSMugunthan V N if (ret != 0) 17733b72c2feSMugunthan V N return ret; 17743b72c2feSMugunthan V N 1775a6c5d14fSGrygorii Strashko ret = cpsw_ale_del_mcast(priv->ale, priv->ndev->broadcast, 17763b72c2feSMugunthan V N 0, ALE_VLAN, vid); 1777a6c5d14fSGrygorii Strashko pm_runtime_put(&priv->pdev->dev); 1778a6c5d14fSGrygorii Strashko return ret; 17793b72c2feSMugunthan V N } 17803b72c2feSMugunthan V N 1781df828598SMugunthan V N static const struct net_device_ops cpsw_netdev_ops = { 1782df828598SMugunthan V N .ndo_open = cpsw_ndo_open, 1783df828598SMugunthan V N .ndo_stop = cpsw_ndo_stop, 1784df828598SMugunthan V N .ndo_start_xmit = cpsw_ndo_start_xmit, 1785dcfd8d58SMugunthan V N .ndo_set_mac_address = cpsw_ndo_set_mac_address, 17862e5b38abSRichard Cochran .ndo_do_ioctl = cpsw_ndo_ioctl, 1787df828598SMugunthan V N .ndo_validate_addr = eth_validate_addr, 17885c473ed2SDavid S. Miller .ndo_change_mtu = eth_change_mtu, 1789df828598SMugunthan V N .ndo_tx_timeout = cpsw_ndo_tx_timeout, 17905c50a856SMugunthan V N .ndo_set_rx_mode = cpsw_ndo_set_rx_mode, 1791df828598SMugunthan V N #ifdef CONFIG_NET_POLL_CONTROLLER 1792df828598SMugunthan V N .ndo_poll_controller = cpsw_ndo_poll_controller, 1793df828598SMugunthan V N #endif 17943b72c2feSMugunthan V N .ndo_vlan_rx_add_vid = cpsw_ndo_vlan_rx_add_vid, 17953b72c2feSMugunthan V N .ndo_vlan_rx_kill_vid = cpsw_ndo_vlan_rx_kill_vid, 1796df828598SMugunthan V N }; 1797df828598SMugunthan V N 179852c4f0ecSMugunthan V N static int cpsw_get_regs_len(struct net_device *ndev) 179952c4f0ecSMugunthan V N { 180052c4f0ecSMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 180152c4f0ecSMugunthan V N 180252c4f0ecSMugunthan V N return priv->data.ale_entries * ALE_ENTRY_WORDS * sizeof(u32); 180352c4f0ecSMugunthan V N } 180452c4f0ecSMugunthan V N 180552c4f0ecSMugunthan V N static void cpsw_get_regs(struct net_device *ndev, 180652c4f0ecSMugunthan V N struct ethtool_regs *regs, void *p) 180752c4f0ecSMugunthan V N { 180852c4f0ecSMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 180952c4f0ecSMugunthan V N u32 *reg = p; 181052c4f0ecSMugunthan V N 181152c4f0ecSMugunthan V N /* update CPSW IP version */ 181252c4f0ecSMugunthan V N regs->version = priv->version; 181352c4f0ecSMugunthan V N 181452c4f0ecSMugunthan V N cpsw_ale_dump(priv->ale, reg); 181552c4f0ecSMugunthan V N } 181652c4f0ecSMugunthan V N 1817df828598SMugunthan V N static void cpsw_get_drvinfo(struct net_device *ndev, 1818df828598SMugunthan V N struct ethtool_drvinfo *info) 1819df828598SMugunthan V N { 1820df828598SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 18217826d43fSJiri Pirko 182252c4f0ecSMugunthan V N strlcpy(info->driver, "cpsw", sizeof(info->driver)); 18237826d43fSJiri Pirko strlcpy(info->version, "1.0", sizeof(info->version)); 18247826d43fSJiri Pirko strlcpy(info->bus_info, priv->pdev->name, sizeof(info->bus_info)); 1825df828598SMugunthan V N } 1826df828598SMugunthan V N 1827df828598SMugunthan V N static u32 cpsw_get_msglevel(struct net_device *ndev) 1828df828598SMugunthan V N { 1829df828598SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 1830df828598SMugunthan V N return priv->msg_enable; 1831df828598SMugunthan V N } 1832df828598SMugunthan V N 1833df828598SMugunthan V N static void cpsw_set_msglevel(struct net_device *ndev, u32 value) 1834df828598SMugunthan V N { 1835df828598SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 1836df828598SMugunthan V N priv->msg_enable = value; 1837df828598SMugunthan V N } 1838df828598SMugunthan V N 18392e5b38abSRichard Cochran static int cpsw_get_ts_info(struct net_device *ndev, 18402e5b38abSRichard Cochran struct ethtool_ts_info *info) 18412e5b38abSRichard Cochran { 18422e5b38abSRichard Cochran #ifdef CONFIG_TI_CPTS 18432e5b38abSRichard Cochran struct cpsw_priv *priv = netdev_priv(ndev); 18442e5b38abSRichard Cochran 18452e5b38abSRichard Cochran info->so_timestamping = 18462e5b38abSRichard Cochran SOF_TIMESTAMPING_TX_HARDWARE | 18472e5b38abSRichard Cochran SOF_TIMESTAMPING_TX_SOFTWARE | 18482e5b38abSRichard Cochran SOF_TIMESTAMPING_RX_HARDWARE | 18492e5b38abSRichard Cochran SOF_TIMESTAMPING_RX_SOFTWARE | 18502e5b38abSRichard Cochran SOF_TIMESTAMPING_SOFTWARE | 18512e5b38abSRichard Cochran SOF_TIMESTAMPING_RAW_HARDWARE; 18529232b16dSMugunthan V N info->phc_index = priv->cpts->phc_index; 18532e5b38abSRichard Cochran info->tx_types = 18542e5b38abSRichard Cochran (1 << HWTSTAMP_TX_OFF) | 18552e5b38abSRichard Cochran (1 << HWTSTAMP_TX_ON); 18562e5b38abSRichard Cochran info->rx_filters = 18572e5b38abSRichard Cochran (1 << HWTSTAMP_FILTER_NONE) | 18582e5b38abSRichard Cochran (1 << HWTSTAMP_FILTER_PTP_V2_EVENT); 18592e5b38abSRichard Cochran #else 18602e5b38abSRichard Cochran info->so_timestamping = 18612e5b38abSRichard Cochran SOF_TIMESTAMPING_TX_SOFTWARE | 18622e5b38abSRichard Cochran SOF_TIMESTAMPING_RX_SOFTWARE | 18632e5b38abSRichard Cochran SOF_TIMESTAMPING_SOFTWARE; 18642e5b38abSRichard Cochran info->phc_index = -1; 18652e5b38abSRichard Cochran info->tx_types = 0; 18662e5b38abSRichard Cochran info->rx_filters = 0; 18672e5b38abSRichard Cochran #endif 18682e5b38abSRichard Cochran return 0; 18692e5b38abSRichard Cochran } 18702e5b38abSRichard Cochran 1871d3bb9c58SMugunthan V N static int cpsw_get_settings(struct net_device *ndev, 1872d3bb9c58SMugunthan V N struct ethtool_cmd *ecmd) 1873d3bb9c58SMugunthan V N { 1874d3bb9c58SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 1875d3bb9c58SMugunthan V N int slave_no = cpsw_slave_index(priv); 1876d3bb9c58SMugunthan V N 1877d3bb9c58SMugunthan V N if (priv->slaves[slave_no].phy) 1878d3bb9c58SMugunthan V N return phy_ethtool_gset(priv->slaves[slave_no].phy, ecmd); 1879d3bb9c58SMugunthan V N else 1880d3bb9c58SMugunthan V N return -EOPNOTSUPP; 1881d3bb9c58SMugunthan V N } 1882d3bb9c58SMugunthan V N 1883d3bb9c58SMugunthan V N static int cpsw_set_settings(struct net_device *ndev, struct ethtool_cmd *ecmd) 1884d3bb9c58SMugunthan V N { 1885d3bb9c58SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 1886d3bb9c58SMugunthan V N int slave_no = cpsw_slave_index(priv); 1887d3bb9c58SMugunthan V N 1888d3bb9c58SMugunthan V N if (priv->slaves[slave_no].phy) 1889d3bb9c58SMugunthan V N return phy_ethtool_sset(priv->slaves[slave_no].phy, ecmd); 1890d3bb9c58SMugunthan V N else 1891d3bb9c58SMugunthan V N return -EOPNOTSUPP; 1892d3bb9c58SMugunthan V N } 1893d3bb9c58SMugunthan V N 1894d8a64420SMatus Ujhelyi static void cpsw_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol) 1895d8a64420SMatus Ujhelyi { 1896d8a64420SMatus Ujhelyi struct cpsw_priv *priv = netdev_priv(ndev); 1897d8a64420SMatus Ujhelyi int slave_no = cpsw_slave_index(priv); 1898d8a64420SMatus Ujhelyi 1899d8a64420SMatus Ujhelyi wol->supported = 0; 1900d8a64420SMatus Ujhelyi wol->wolopts = 0; 1901d8a64420SMatus Ujhelyi 1902d8a64420SMatus Ujhelyi if (priv->slaves[slave_no].phy) 1903d8a64420SMatus Ujhelyi phy_ethtool_get_wol(priv->slaves[slave_no].phy, wol); 1904d8a64420SMatus Ujhelyi } 1905d8a64420SMatus Ujhelyi 1906d8a64420SMatus Ujhelyi static int cpsw_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol) 1907d8a64420SMatus Ujhelyi { 1908d8a64420SMatus Ujhelyi struct cpsw_priv *priv = netdev_priv(ndev); 1909d8a64420SMatus Ujhelyi int slave_no = cpsw_slave_index(priv); 1910d8a64420SMatus Ujhelyi 1911d8a64420SMatus Ujhelyi if (priv->slaves[slave_no].phy) 1912d8a64420SMatus Ujhelyi return phy_ethtool_set_wol(priv->slaves[slave_no].phy, wol); 1913d8a64420SMatus Ujhelyi else 1914d8a64420SMatus Ujhelyi return -EOPNOTSUPP; 1915d8a64420SMatus Ujhelyi } 1916d8a64420SMatus Ujhelyi 19171923d6e4SMugunthan V N static void cpsw_get_pauseparam(struct net_device *ndev, 19181923d6e4SMugunthan V N struct ethtool_pauseparam *pause) 19191923d6e4SMugunthan V N { 19201923d6e4SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 19211923d6e4SMugunthan V N 19221923d6e4SMugunthan V N pause->autoneg = AUTONEG_DISABLE; 19231923d6e4SMugunthan V N pause->rx_pause = priv->rx_pause ? true : false; 19241923d6e4SMugunthan V N pause->tx_pause = priv->tx_pause ? true : false; 19251923d6e4SMugunthan V N } 19261923d6e4SMugunthan V N 19271923d6e4SMugunthan V N static int cpsw_set_pauseparam(struct net_device *ndev, 19281923d6e4SMugunthan V N struct ethtool_pauseparam *pause) 19291923d6e4SMugunthan V N { 19301923d6e4SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 19311923d6e4SMugunthan V N bool link; 19321923d6e4SMugunthan V N 19331923d6e4SMugunthan V N priv->rx_pause = pause->rx_pause ? true : false; 19341923d6e4SMugunthan V N priv->tx_pause = pause->tx_pause ? true : false; 19351923d6e4SMugunthan V N 19361923d6e4SMugunthan V N for_each_slave(priv, _cpsw_adjust_link, priv, &link); 19371923d6e4SMugunthan V N return 0; 19381923d6e4SMugunthan V N } 19391923d6e4SMugunthan V N 19407898b1daSGrygorii Strashko static int cpsw_ethtool_op_begin(struct net_device *ndev) 19417898b1daSGrygorii Strashko { 19427898b1daSGrygorii Strashko struct cpsw_priv *priv = netdev_priv(ndev); 19437898b1daSGrygorii Strashko int ret; 19447898b1daSGrygorii Strashko 19457898b1daSGrygorii Strashko ret = pm_runtime_get_sync(&priv->pdev->dev); 19467898b1daSGrygorii Strashko if (ret < 0) { 19477898b1daSGrygorii Strashko cpsw_err(priv, drv, "ethtool begin failed %d\n", ret); 19487898b1daSGrygorii Strashko pm_runtime_put_noidle(&priv->pdev->dev); 19497898b1daSGrygorii Strashko } 19507898b1daSGrygorii Strashko 19517898b1daSGrygorii Strashko return ret; 19527898b1daSGrygorii Strashko } 19537898b1daSGrygorii Strashko 19547898b1daSGrygorii Strashko static void cpsw_ethtool_op_complete(struct net_device *ndev) 19557898b1daSGrygorii Strashko { 19567898b1daSGrygorii Strashko struct cpsw_priv *priv = netdev_priv(ndev); 19577898b1daSGrygorii Strashko int ret; 19587898b1daSGrygorii Strashko 19597898b1daSGrygorii Strashko ret = pm_runtime_put(&priv->pdev->dev); 19607898b1daSGrygorii Strashko if (ret < 0) 19617898b1daSGrygorii Strashko cpsw_err(priv, drv, "ethtool complete failed %d\n", ret); 19627898b1daSGrygorii Strashko } 19637898b1daSGrygorii Strashko 1964df828598SMugunthan V N static const struct ethtool_ops cpsw_ethtool_ops = { 1965df828598SMugunthan V N .get_drvinfo = cpsw_get_drvinfo, 1966df828598SMugunthan V N .get_msglevel = cpsw_get_msglevel, 1967df828598SMugunthan V N .set_msglevel = cpsw_set_msglevel, 1968df828598SMugunthan V N .get_link = ethtool_op_get_link, 19692e5b38abSRichard Cochran .get_ts_info = cpsw_get_ts_info, 1970d3bb9c58SMugunthan V N .get_settings = cpsw_get_settings, 1971d3bb9c58SMugunthan V N .set_settings = cpsw_set_settings, 1972ff5b8ef2SMugunthan V N .get_coalesce = cpsw_get_coalesce, 1973ff5b8ef2SMugunthan V N .set_coalesce = cpsw_set_coalesce, 1974d9718546SMugunthan V N .get_sset_count = cpsw_get_sset_count, 1975d9718546SMugunthan V N .get_strings = cpsw_get_strings, 1976d9718546SMugunthan V N .get_ethtool_stats = cpsw_get_ethtool_stats, 19771923d6e4SMugunthan V N .get_pauseparam = cpsw_get_pauseparam, 19781923d6e4SMugunthan V N .set_pauseparam = cpsw_set_pauseparam, 1979d8a64420SMatus Ujhelyi .get_wol = cpsw_get_wol, 1980d8a64420SMatus Ujhelyi .set_wol = cpsw_set_wol, 198152c4f0ecSMugunthan V N .get_regs_len = cpsw_get_regs_len, 198252c4f0ecSMugunthan V N .get_regs = cpsw_get_regs, 19837898b1daSGrygorii Strashko .begin = cpsw_ethtool_op_begin, 19847898b1daSGrygorii Strashko .complete = cpsw_ethtool_op_complete, 1985df828598SMugunthan V N }; 1986df828598SMugunthan V N 1987549985eeSRichard Cochran static void cpsw_slave_init(struct cpsw_slave *slave, struct cpsw_priv *priv, 1988549985eeSRichard Cochran u32 slave_reg_ofs, u32 sliver_reg_ofs) 1989df828598SMugunthan V N { 1990df828598SMugunthan V N void __iomem *regs = priv->regs; 1991df828598SMugunthan V N int slave_num = slave->slave_num; 1992df828598SMugunthan V N struct cpsw_slave_data *data = priv->data.slave_data + slave_num; 1993df828598SMugunthan V N 1994df828598SMugunthan V N slave->data = data; 1995549985eeSRichard Cochran slave->regs = regs + slave_reg_ofs; 1996549985eeSRichard Cochran slave->sliver = regs + sliver_reg_ofs; 1997d9ba8f9eSMugunthan V N slave->port_vlan = data->dual_emac_res_vlan; 1998df828598SMugunthan V N } 1999df828598SMugunthan V N 2000552165bcSDavid Rivshin static int cpsw_probe_dt(struct cpsw_platform_data *data, 20012eb32b0aSMugunthan V N struct platform_device *pdev) 20022eb32b0aSMugunthan V N { 20032eb32b0aSMugunthan V N struct device_node *node = pdev->dev.of_node; 20042eb32b0aSMugunthan V N struct device_node *slave_node; 20052eb32b0aSMugunthan V N int i = 0, ret; 20062eb32b0aSMugunthan V N u32 prop; 20072eb32b0aSMugunthan V N 20082eb32b0aSMugunthan V N if (!node) 20092eb32b0aSMugunthan V N return -EINVAL; 20102eb32b0aSMugunthan V N 20112eb32b0aSMugunthan V N if (of_property_read_u32(node, "slaves", &prop)) { 201288c99ff6SGeorge Cherian dev_err(&pdev->dev, "Missing slaves property in the DT.\n"); 20132eb32b0aSMugunthan V N return -EINVAL; 20142eb32b0aSMugunthan V N } 20152eb32b0aSMugunthan V N data->slaves = prop; 20162eb32b0aSMugunthan V N 2017e86ac13bSMugunthan V N if (of_property_read_u32(node, "active_slave", &prop)) { 201888c99ff6SGeorge Cherian dev_err(&pdev->dev, "Missing active_slave property in the DT.\n"); 2019aa1a15e2SDaniel Mack return -EINVAL; 202078ca0b28SRichard Cochran } 2021e86ac13bSMugunthan V N data->active_slave = prop; 202278ca0b28SRichard Cochran 202300ab94eeSRichard Cochran if (of_property_read_u32(node, "cpts_clock_mult", &prop)) { 202488c99ff6SGeorge Cherian dev_err(&pdev->dev, "Missing cpts_clock_mult property in the DT.\n"); 2025aa1a15e2SDaniel Mack return -EINVAL; 202600ab94eeSRichard Cochran } 202700ab94eeSRichard Cochran data->cpts_clock_mult = prop; 202800ab94eeSRichard Cochran 202900ab94eeSRichard Cochran if (of_property_read_u32(node, "cpts_clock_shift", &prop)) { 203088c99ff6SGeorge Cherian dev_err(&pdev->dev, "Missing cpts_clock_shift property in the DT.\n"); 2031aa1a15e2SDaniel Mack return -EINVAL; 203200ab94eeSRichard Cochran } 203300ab94eeSRichard Cochran data->cpts_clock_shift = prop; 203400ab94eeSRichard Cochran 2035aa1a15e2SDaniel Mack data->slave_data = devm_kzalloc(&pdev->dev, data->slaves 2036aa1a15e2SDaniel Mack * sizeof(struct cpsw_slave_data), 2037b2adaca9SJoe Perches GFP_KERNEL); 2038b2adaca9SJoe Perches if (!data->slave_data) 2039aa1a15e2SDaniel Mack return -ENOMEM; 20402eb32b0aSMugunthan V N 20412eb32b0aSMugunthan V N if (of_property_read_u32(node, "cpdma_channels", &prop)) { 204288c99ff6SGeorge Cherian dev_err(&pdev->dev, "Missing cpdma_channels property in the DT.\n"); 2043aa1a15e2SDaniel Mack return -EINVAL; 20442eb32b0aSMugunthan V N } 20452eb32b0aSMugunthan V N data->channels = prop; 20462eb32b0aSMugunthan V N 20472eb32b0aSMugunthan V N if (of_property_read_u32(node, "ale_entries", &prop)) { 204888c99ff6SGeorge Cherian dev_err(&pdev->dev, "Missing ale_entries property in the DT.\n"); 2049aa1a15e2SDaniel Mack return -EINVAL; 20502eb32b0aSMugunthan V N } 20512eb32b0aSMugunthan V N data->ale_entries = prop; 20522eb32b0aSMugunthan V N 20532eb32b0aSMugunthan V N if (of_property_read_u32(node, "bd_ram_size", &prop)) { 205488c99ff6SGeorge Cherian dev_err(&pdev->dev, "Missing bd_ram_size property in the DT.\n"); 2055aa1a15e2SDaniel Mack return -EINVAL; 20562eb32b0aSMugunthan V N } 20572eb32b0aSMugunthan V N data->bd_ram_size = prop; 20582eb32b0aSMugunthan V N 20592eb32b0aSMugunthan V N if (of_property_read_u32(node, "mac_control", &prop)) { 206088c99ff6SGeorge Cherian dev_err(&pdev->dev, "Missing mac_control property in the DT.\n"); 2061aa1a15e2SDaniel Mack return -EINVAL; 20622eb32b0aSMugunthan V N } 20632eb32b0aSMugunthan V N data->mac_control = prop; 20642eb32b0aSMugunthan V N 2065281abd96SMarkus Pargmann if (of_property_read_bool(node, "dual_emac")) 2066281abd96SMarkus Pargmann data->dual_emac = 1; 2067d9ba8f9eSMugunthan V N 20681fb19aa7SVaibhav Hiremath /* 20691fb19aa7SVaibhav Hiremath * Populate all the child nodes here... 20701fb19aa7SVaibhav Hiremath */ 20711fb19aa7SVaibhav Hiremath ret = of_platform_populate(node, NULL, NULL, &pdev->dev); 20721fb19aa7SVaibhav Hiremath /* We do not want to force this, as in some cases may not have child */ 20731fb19aa7SVaibhav Hiremath if (ret) 207488c99ff6SGeorge Cherian dev_warn(&pdev->dev, "Doesn't have any child node\n"); 20751fb19aa7SVaibhav Hiremath 20768658aaf2SBen Hutchings for_each_available_child_of_node(node, slave_node) { 2077549985eeSRichard Cochran struct cpsw_slave_data *slave_data = data->slave_data + i; 2078549985eeSRichard Cochran const void *mac_addr = NULL; 2079549985eeSRichard Cochran int lenp; 2080549985eeSRichard Cochran const __be32 *parp; 2081549985eeSRichard Cochran 2082f468b10eSMarkus Pargmann /* This is no slave child node, continue */ 2083f468b10eSMarkus Pargmann if (strcmp(slave_node->name, "slave")) 2084f468b10eSMarkus Pargmann continue; 2085f468b10eSMarkus Pargmann 2086552165bcSDavid Rivshin slave_data->phy_node = of_parse_phandle(slave_node, 2087552165bcSDavid Rivshin "phy-handle", 0); 2088f1eea5c1SDavid Rivshin parp = of_get_property(slave_node, "phy_id", &lenp); 2089ae092b5bSDavid Rivshin if (slave_data->phy_node) { 2090ae092b5bSDavid Rivshin dev_dbg(&pdev->dev, 2091ae092b5bSDavid Rivshin "slave[%d] using phy-handle=\"%s\"\n", 2092ae092b5bSDavid Rivshin i, slave_data->phy_node->full_name); 2093ae092b5bSDavid Rivshin } else if (of_phy_is_fixed_link(slave_node)) { 2094dfc0a6d3SDavid Rivshin /* In the case of a fixed PHY, the DT node associated 2095dfc0a6d3SDavid Rivshin * to the PHY is the Ethernet MAC DT node. 2096dfc0a6d3SDavid Rivshin */ 20971f71e8c9SMarkus Brunner ret = of_phy_register_fixed_link(slave_node); 20981f71e8c9SMarkus Brunner if (ret) 20991f71e8c9SMarkus Brunner return ret; 210006cd6d6eSDavid Rivshin slave_data->phy_node = of_node_get(slave_node); 2101f1eea5c1SDavid Rivshin } else if (parp) { 2102f1eea5c1SDavid Rivshin u32 phyid; 2103f1eea5c1SDavid Rivshin struct device_node *mdio_node; 2104f1eea5c1SDavid Rivshin struct platform_device *mdio; 2105f1eea5c1SDavid Rivshin 2106f1eea5c1SDavid Rivshin if (lenp != (sizeof(__be32) * 2)) { 2107f1eea5c1SDavid Rivshin dev_err(&pdev->dev, "Invalid slave[%d] phy_id property\n", i); 210847276fccSMugunthan V N goto no_phy_slave; 2109549985eeSRichard Cochran } 2110549985eeSRichard Cochran mdio_node = of_find_node_by_phandle(be32_to_cpup(parp)); 2111549985eeSRichard Cochran phyid = be32_to_cpup(parp+1); 2112549985eeSRichard Cochran mdio = of_find_device_by_node(mdio_node); 211360e71ab5SJohan Hovold of_node_put(mdio_node); 21146954cc1fSJohan Hovold if (!mdio) { 211556fdb2e0SMarkus Pargmann dev_err(&pdev->dev, "Missing mdio platform device\n"); 21166954cc1fSJohan Hovold return -EINVAL; 21176954cc1fSJohan Hovold } 2118549985eeSRichard Cochran snprintf(slave_data->phy_id, sizeof(slave_data->phy_id), 2119549985eeSRichard Cochran PHY_ID_FMT, mdio->name, phyid); 2120f1eea5c1SDavid Rivshin } else { 2121ae092b5bSDavid Rivshin dev_err(&pdev->dev, 2122ae092b5bSDavid Rivshin "No slave[%d] phy_id, phy-handle, or fixed-link property\n", 2123ae092b5bSDavid Rivshin i); 2124f1eea5c1SDavid Rivshin goto no_phy_slave; 2125f1eea5c1SDavid Rivshin } 212647276fccSMugunthan V N slave_data->phy_if = of_get_phy_mode(slave_node); 212747276fccSMugunthan V N if (slave_data->phy_if < 0) { 212847276fccSMugunthan V N dev_err(&pdev->dev, "Missing or malformed slave[%d] phy-mode property\n", 212947276fccSMugunthan V N i); 213047276fccSMugunthan V N return slave_data->phy_if; 213147276fccSMugunthan V N } 213247276fccSMugunthan V N 213347276fccSMugunthan V N no_phy_slave: 2134549985eeSRichard Cochran mac_addr = of_get_mac_address(slave_node); 21350ba517b1SMarkus Pargmann if (mac_addr) { 2136549985eeSRichard Cochran memcpy(slave_data->mac_addr, mac_addr, ETH_ALEN); 21370ba517b1SMarkus Pargmann } else { 2138b6745f6eSMugunthan V N ret = ti_cm_get_macid(&pdev->dev, i, 21390ba517b1SMarkus Pargmann slave_data->mac_addr); 21400ba517b1SMarkus Pargmann if (ret) 21410ba517b1SMarkus Pargmann return ret; 21420ba517b1SMarkus Pargmann } 2143d9ba8f9eSMugunthan V N if (data->dual_emac) { 214491c4166cSMugunthan V N if (of_property_read_u32(slave_node, "dual_emac_res_vlan", 2145d9ba8f9eSMugunthan V N &prop)) { 214688c99ff6SGeorge Cherian dev_err(&pdev->dev, "Missing dual_emac_res_vlan in DT.\n"); 2147d9ba8f9eSMugunthan V N slave_data->dual_emac_res_vlan = i+1; 214888c99ff6SGeorge Cherian dev_err(&pdev->dev, "Using %d as Reserved VLAN for %d slave\n", 2149d9ba8f9eSMugunthan V N slave_data->dual_emac_res_vlan, i); 2150d9ba8f9eSMugunthan V N } else { 2151d9ba8f9eSMugunthan V N slave_data->dual_emac_res_vlan = prop; 2152d9ba8f9eSMugunthan V N } 2153d9ba8f9eSMugunthan V N } 2154d9ba8f9eSMugunthan V N 2155549985eeSRichard Cochran i++; 21563a27bfacSMugunthan V N if (i == data->slaves) 21573a27bfacSMugunthan V N break; 2158549985eeSRichard Cochran } 2159549985eeSRichard Cochran 21602eb32b0aSMugunthan V N return 0; 21612eb32b0aSMugunthan V N } 21622eb32b0aSMugunthan V N 2163d9ba8f9eSMugunthan V N static int cpsw_probe_dual_emac(struct platform_device *pdev, 2164d9ba8f9eSMugunthan V N struct cpsw_priv *priv) 2165d9ba8f9eSMugunthan V N { 2166d9ba8f9eSMugunthan V N struct cpsw_platform_data *data = &priv->data; 2167d9ba8f9eSMugunthan V N struct net_device *ndev; 2168d9ba8f9eSMugunthan V N struct cpsw_priv *priv_sl2; 2169d9ba8f9eSMugunthan V N int ret = 0, i; 2170d9ba8f9eSMugunthan V N 2171d9ba8f9eSMugunthan V N ndev = alloc_etherdev(sizeof(struct cpsw_priv)); 2172d9ba8f9eSMugunthan V N if (!ndev) { 217388c99ff6SGeorge Cherian dev_err(&pdev->dev, "cpsw: error allocating net_device\n"); 2174d9ba8f9eSMugunthan V N return -ENOMEM; 2175d9ba8f9eSMugunthan V N } 2176d9ba8f9eSMugunthan V N 2177d9ba8f9eSMugunthan V N priv_sl2 = netdev_priv(ndev); 2178d9ba8f9eSMugunthan V N priv_sl2->data = *data; 2179d9ba8f9eSMugunthan V N priv_sl2->pdev = pdev; 2180d9ba8f9eSMugunthan V N priv_sl2->ndev = ndev; 2181d9ba8f9eSMugunthan V N priv_sl2->dev = &ndev->dev; 2182d9ba8f9eSMugunthan V N priv_sl2->msg_enable = netif_msg_init(debug_level, CPSW_DEBUG); 2183d9ba8f9eSMugunthan V N priv_sl2->rx_packet_max = max(rx_packet_max, 128); 2184d9ba8f9eSMugunthan V N 2185d9ba8f9eSMugunthan V N if (is_valid_ether_addr(data->slave_data[1].mac_addr)) { 2186d9ba8f9eSMugunthan V N memcpy(priv_sl2->mac_addr, data->slave_data[1].mac_addr, 2187d9ba8f9eSMugunthan V N ETH_ALEN); 218888c99ff6SGeorge Cherian dev_info(&pdev->dev, "cpsw: Detected MACID = %pM\n", priv_sl2->mac_addr); 2189d9ba8f9eSMugunthan V N } else { 2190d9ba8f9eSMugunthan V N random_ether_addr(priv_sl2->mac_addr); 219188c99ff6SGeorge Cherian dev_info(&pdev->dev, "cpsw: Random MACID = %pM\n", priv_sl2->mac_addr); 2192d9ba8f9eSMugunthan V N } 2193d9ba8f9eSMugunthan V N memcpy(ndev->dev_addr, priv_sl2->mac_addr, ETH_ALEN); 2194d9ba8f9eSMugunthan V N 2195d9ba8f9eSMugunthan V N priv_sl2->slaves = priv->slaves; 2196d9ba8f9eSMugunthan V N priv_sl2->clk = priv->clk; 2197d9ba8f9eSMugunthan V N 2198ff5b8ef2SMugunthan V N priv_sl2->coal_intvl = 0; 2199ff5b8ef2SMugunthan V N priv_sl2->bus_freq_mhz = priv->bus_freq_mhz; 2200ff5b8ef2SMugunthan V N 2201d9ba8f9eSMugunthan V N priv_sl2->regs = priv->regs; 2202d9ba8f9eSMugunthan V N priv_sl2->host_port_regs = priv->host_port_regs; 2203d9ba8f9eSMugunthan V N priv_sl2->wr_regs = priv->wr_regs; 2204d9718546SMugunthan V N priv_sl2->hw_stats = priv->hw_stats; 2205d9ba8f9eSMugunthan V N priv_sl2->dma = priv->dma; 2206d9ba8f9eSMugunthan V N priv_sl2->txch = priv->txch; 2207d9ba8f9eSMugunthan V N priv_sl2->rxch = priv->rxch; 2208d9ba8f9eSMugunthan V N priv_sl2->ale = priv->ale; 2209d9ba8f9eSMugunthan V N priv_sl2->emac_port = 1; 2210d9ba8f9eSMugunthan V N priv->slaves[1].ndev = ndev; 2211d9ba8f9eSMugunthan V N priv_sl2->cpts = priv->cpts; 2212d9ba8f9eSMugunthan V N priv_sl2->version = priv->version; 2213d9ba8f9eSMugunthan V N 2214d9ba8f9eSMugunthan V N for (i = 0; i < priv->num_irqs; i++) { 2215d9ba8f9eSMugunthan V N priv_sl2->irqs_table[i] = priv->irqs_table[i]; 2216d9ba8f9eSMugunthan V N priv_sl2->num_irqs = priv->num_irqs; 2217d9ba8f9eSMugunthan V N } 2218f646968fSPatrick McHardy ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER; 2219d9ba8f9eSMugunthan V N 2220d9ba8f9eSMugunthan V N ndev->netdev_ops = &cpsw_netdev_ops; 22217ad24ea4SWilfried Klaebe ndev->ethtool_ops = &cpsw_ethtool_ops; 2222d9ba8f9eSMugunthan V N 2223d9ba8f9eSMugunthan V N /* register the network device */ 2224d9ba8f9eSMugunthan V N SET_NETDEV_DEV(ndev, &pdev->dev); 2225d9ba8f9eSMugunthan V N ret = register_netdev(ndev); 2226d9ba8f9eSMugunthan V N if (ret) { 222788c99ff6SGeorge Cherian dev_err(&pdev->dev, "cpsw: error registering net device\n"); 2228d9ba8f9eSMugunthan V N free_netdev(ndev); 2229d9ba8f9eSMugunthan V N ret = -ENODEV; 2230d9ba8f9eSMugunthan V N } 2231d9ba8f9eSMugunthan V N 2232d9ba8f9eSMugunthan V N return ret; 2233d9ba8f9eSMugunthan V N } 2234d9ba8f9eSMugunthan V N 22357da11600SMugunthan V N #define CPSW_QUIRK_IRQ BIT(0) 22367da11600SMugunthan V N 22377da11600SMugunthan V N static struct platform_device_id cpsw_devtype[] = { 22387da11600SMugunthan V N { 22397da11600SMugunthan V N /* keep it for existing comaptibles */ 22407da11600SMugunthan V N .name = "cpsw", 22417da11600SMugunthan V N .driver_data = CPSW_QUIRK_IRQ, 22427da11600SMugunthan V N }, { 22437da11600SMugunthan V N .name = "am335x-cpsw", 22447da11600SMugunthan V N .driver_data = CPSW_QUIRK_IRQ, 22457da11600SMugunthan V N }, { 22467da11600SMugunthan V N .name = "am4372-cpsw", 22477da11600SMugunthan V N .driver_data = 0, 22487da11600SMugunthan V N }, { 22497da11600SMugunthan V N .name = "dra7-cpsw", 22507da11600SMugunthan V N .driver_data = 0, 22517da11600SMugunthan V N }, { 22527da11600SMugunthan V N /* sentinel */ 22537da11600SMugunthan V N } 22547da11600SMugunthan V N }; 22557da11600SMugunthan V N MODULE_DEVICE_TABLE(platform, cpsw_devtype); 22567da11600SMugunthan V N 22577da11600SMugunthan V N enum ti_cpsw_type { 22587da11600SMugunthan V N CPSW = 0, 22597da11600SMugunthan V N AM335X_CPSW, 22607da11600SMugunthan V N AM4372_CPSW, 22617da11600SMugunthan V N DRA7_CPSW, 22627da11600SMugunthan V N }; 22637da11600SMugunthan V N 22647da11600SMugunthan V N static const struct of_device_id cpsw_of_mtable[] = { 22657da11600SMugunthan V N { .compatible = "ti,cpsw", .data = &cpsw_devtype[CPSW], }, 22667da11600SMugunthan V N { .compatible = "ti,am335x-cpsw", .data = &cpsw_devtype[AM335X_CPSW], }, 22677da11600SMugunthan V N { .compatible = "ti,am4372-cpsw", .data = &cpsw_devtype[AM4372_CPSW], }, 22687da11600SMugunthan V N { .compatible = "ti,dra7-cpsw", .data = &cpsw_devtype[DRA7_CPSW], }, 22697da11600SMugunthan V N { /* sentinel */ }, 22707da11600SMugunthan V N }; 22717da11600SMugunthan V N MODULE_DEVICE_TABLE(of, cpsw_of_mtable); 22727da11600SMugunthan V N 2273663e12e6SBill Pemberton static int cpsw_probe(struct platform_device *pdev) 2274df828598SMugunthan V N { 2275d1bd9acfSSebastian Siewior struct cpsw_platform_data *data; 2276df828598SMugunthan V N struct net_device *ndev; 2277df828598SMugunthan V N struct cpsw_priv *priv; 2278df828598SMugunthan V N struct cpdma_params dma_params; 2279df828598SMugunthan V N struct cpsw_ale_params ale_params; 2280aa1a15e2SDaniel Mack void __iomem *ss_regs; 2281aa1a15e2SDaniel Mack struct resource *res, *ss_res; 22827da11600SMugunthan V N const struct of_device_id *of_id; 22831d147ccbSMugunthan V N struct gpio_descs *mode; 2284549985eeSRichard Cochran u32 slave_offset, sliver_offset, slave_size; 22855087b915SFelipe Balbi int ret = 0, i; 22865087b915SFelipe Balbi int irq; 2287df828598SMugunthan V N 2288df828598SMugunthan V N ndev = alloc_etherdev(sizeof(struct cpsw_priv)); 2289df828598SMugunthan V N if (!ndev) { 229088c99ff6SGeorge Cherian dev_err(&pdev->dev, "error allocating net_device\n"); 2291df828598SMugunthan V N return -ENOMEM; 2292df828598SMugunthan V N } 2293df828598SMugunthan V N 2294df828598SMugunthan V N platform_set_drvdata(pdev, ndev); 2295df828598SMugunthan V N priv = netdev_priv(ndev); 2296df828598SMugunthan V N priv->pdev = pdev; 2297df828598SMugunthan V N priv->ndev = ndev; 2298df828598SMugunthan V N priv->dev = &ndev->dev; 2299df828598SMugunthan V N priv->msg_enable = netif_msg_init(debug_level, CPSW_DEBUG); 2300df828598SMugunthan V N priv->rx_packet_max = max(rx_packet_max, 128); 23019232b16dSMugunthan V N priv->cpts = devm_kzalloc(&pdev->dev, sizeof(struct cpts), GFP_KERNEL); 2302ab8e99d2SSebastian Siewior if (!priv->cpts) { 230388c99ff6SGeorge Cherian dev_err(&pdev->dev, "error allocating cpts\n"); 23044d507dffSMarkus Pargmann ret = -ENOMEM; 23059232b16dSMugunthan V N goto clean_ndev_ret; 23069232b16dSMugunthan V N } 2307df828598SMugunthan V N 23081d147ccbSMugunthan V N mode = devm_gpiod_get_array_optional(&pdev->dev, "mode", GPIOD_OUT_LOW); 23091d147ccbSMugunthan V N if (IS_ERR(mode)) { 23101d147ccbSMugunthan V N ret = PTR_ERR(mode); 23111d147ccbSMugunthan V N dev_err(&pdev->dev, "gpio request failed, ret %d\n", ret); 23121d147ccbSMugunthan V N goto clean_ndev_ret; 23131d147ccbSMugunthan V N } 23141d147ccbSMugunthan V N 23151fb19aa7SVaibhav Hiremath /* 23161fb19aa7SVaibhav Hiremath * This may be required here for child devices. 23171fb19aa7SVaibhav Hiremath */ 23181fb19aa7SVaibhav Hiremath pm_runtime_enable(&pdev->dev); 23191fb19aa7SVaibhav Hiremath 2320739683b4SMugunthan V N /* Select default pin state */ 2321739683b4SMugunthan V N pinctrl_pm_select_default_state(&pdev->dev); 2322739683b4SMugunthan V N 2323552165bcSDavid Rivshin if (cpsw_probe_dt(&priv->data, pdev)) { 232488c99ff6SGeorge Cherian dev_err(&pdev->dev, "cpsw: platform data missing\n"); 23252eb32b0aSMugunthan V N ret = -ENODEV; 2326aa1a15e2SDaniel Mack goto clean_runtime_disable_ret; 23272eb32b0aSMugunthan V N } 23282eb32b0aSMugunthan V N data = &priv->data; 23292eb32b0aSMugunthan V N 2330df828598SMugunthan V N if (is_valid_ether_addr(data->slave_data[0].mac_addr)) { 2331df828598SMugunthan V N memcpy(priv->mac_addr, data->slave_data[0].mac_addr, ETH_ALEN); 233288c99ff6SGeorge Cherian dev_info(&pdev->dev, "Detected MACID = %pM\n", priv->mac_addr); 2333df828598SMugunthan V N } else { 23347efd26d0SJoe Perches eth_random_addr(priv->mac_addr); 233588c99ff6SGeorge Cherian dev_info(&pdev->dev, "Random MACID = %pM\n", priv->mac_addr); 2336df828598SMugunthan V N } 2337df828598SMugunthan V N 2338df828598SMugunthan V N memcpy(ndev->dev_addr, priv->mac_addr, ETH_ALEN); 2339df828598SMugunthan V N 2340aa1a15e2SDaniel Mack priv->slaves = devm_kzalloc(&pdev->dev, 2341aa1a15e2SDaniel Mack sizeof(struct cpsw_slave) * data->slaves, 2342df828598SMugunthan V N GFP_KERNEL); 2343df828598SMugunthan V N if (!priv->slaves) { 2344aa1a15e2SDaniel Mack ret = -ENOMEM; 2345aa1a15e2SDaniel Mack goto clean_runtime_disable_ret; 2346df828598SMugunthan V N } 2347df828598SMugunthan V N for (i = 0; i < data->slaves; i++) 2348df828598SMugunthan V N priv->slaves[i].slave_num = i; 2349df828598SMugunthan V N 2350d9ba8f9eSMugunthan V N priv->slaves[0].ndev = ndev; 2351d9ba8f9eSMugunthan V N priv->emac_port = 0; 2352d9ba8f9eSMugunthan V N 2353aa1a15e2SDaniel Mack priv->clk = devm_clk_get(&pdev->dev, "fck"); 2354df828598SMugunthan V N if (IS_ERR(priv->clk)) { 2355aa1a15e2SDaniel Mack dev_err(priv->dev, "fck is not found\n"); 2356f150bd7fSMugunthan V N ret = -ENODEV; 2357aa1a15e2SDaniel Mack goto clean_runtime_disable_ret; 2358df828598SMugunthan V N } 2359ff5b8ef2SMugunthan V N priv->coal_intvl = 0; 2360ff5b8ef2SMugunthan V N priv->bus_freq_mhz = clk_get_rate(priv->clk) / 1000000; 2361df828598SMugunthan V N 2362aa1a15e2SDaniel Mack ss_res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2363aa1a15e2SDaniel Mack ss_regs = devm_ioremap_resource(&pdev->dev, ss_res); 2364aa1a15e2SDaniel Mack if (IS_ERR(ss_regs)) { 2365aa1a15e2SDaniel Mack ret = PTR_ERR(ss_regs); 2366aa1a15e2SDaniel Mack goto clean_runtime_disable_ret; 2367df828598SMugunthan V N } 2368549985eeSRichard Cochran priv->regs = ss_regs; 2369df828598SMugunthan V N 2370f280e89aSMugunthan V N /* Need to enable clocks with runtime PM api to access module 2371f280e89aSMugunthan V N * registers 2372f280e89aSMugunthan V N */ 2373108a6537SGrygorii Strashko ret = pm_runtime_get_sync(&pdev->dev); 2374108a6537SGrygorii Strashko if (ret < 0) { 2375108a6537SGrygorii Strashko pm_runtime_put_noidle(&pdev->dev); 2376108a6537SGrygorii Strashko goto clean_runtime_disable_ret; 2377108a6537SGrygorii Strashko } 2378f280e89aSMugunthan V N priv->version = readl(&priv->regs->id_ver); 2379f280e89aSMugunthan V N pm_runtime_put_sync(&pdev->dev); 2380f280e89aSMugunthan V N 2381aa1a15e2SDaniel Mack res = platform_get_resource(pdev, IORESOURCE_MEM, 1); 2382aa1a15e2SDaniel Mack priv->wr_regs = devm_ioremap_resource(&pdev->dev, res); 2383aa1a15e2SDaniel Mack if (IS_ERR(priv->wr_regs)) { 2384aa1a15e2SDaniel Mack ret = PTR_ERR(priv->wr_regs); 2385aa1a15e2SDaniel Mack goto clean_runtime_disable_ret; 2386df828598SMugunthan V N } 2387df828598SMugunthan V N 2388df828598SMugunthan V N memset(&dma_params, 0, sizeof(dma_params)); 2389549985eeSRichard Cochran memset(&ale_params, 0, sizeof(ale_params)); 2390549985eeSRichard Cochran 2391549985eeSRichard Cochran switch (priv->version) { 2392549985eeSRichard Cochran case CPSW_VERSION_1: 2393549985eeSRichard Cochran priv->host_port_regs = ss_regs + CPSW1_HOST_PORT_OFFSET; 23949232b16dSMugunthan V N priv->cpts->reg = ss_regs + CPSW1_CPTS_OFFSET; 2395d9718546SMugunthan V N priv->hw_stats = ss_regs + CPSW1_HW_STATS; 2396549985eeSRichard Cochran dma_params.dmaregs = ss_regs + CPSW1_CPDMA_OFFSET; 2397549985eeSRichard Cochran dma_params.txhdp = ss_regs + CPSW1_STATERAM_OFFSET; 2398549985eeSRichard Cochran ale_params.ale_regs = ss_regs + CPSW1_ALE_OFFSET; 2399549985eeSRichard Cochran slave_offset = CPSW1_SLAVE_OFFSET; 2400549985eeSRichard Cochran slave_size = CPSW1_SLAVE_SIZE; 2401549985eeSRichard Cochran sliver_offset = CPSW1_SLIVER_OFFSET; 2402549985eeSRichard Cochran dma_params.desc_mem_phys = 0; 2403549985eeSRichard Cochran break; 2404549985eeSRichard Cochran case CPSW_VERSION_2: 2405c193f365SMugunthan V N case CPSW_VERSION_3: 2406926489beSMugunthan V N case CPSW_VERSION_4: 2407549985eeSRichard Cochran priv->host_port_regs = ss_regs + CPSW2_HOST_PORT_OFFSET; 24089232b16dSMugunthan V N priv->cpts->reg = ss_regs + CPSW2_CPTS_OFFSET; 2409d9718546SMugunthan V N priv->hw_stats = ss_regs + CPSW2_HW_STATS; 2410549985eeSRichard Cochran dma_params.dmaregs = ss_regs + CPSW2_CPDMA_OFFSET; 2411549985eeSRichard Cochran dma_params.txhdp = ss_regs + CPSW2_STATERAM_OFFSET; 2412549985eeSRichard Cochran ale_params.ale_regs = ss_regs + CPSW2_ALE_OFFSET; 2413549985eeSRichard Cochran slave_offset = CPSW2_SLAVE_OFFSET; 2414549985eeSRichard Cochran slave_size = CPSW2_SLAVE_SIZE; 2415549985eeSRichard Cochran sliver_offset = CPSW2_SLIVER_OFFSET; 2416549985eeSRichard Cochran dma_params.desc_mem_phys = 2417aa1a15e2SDaniel Mack (u32 __force) ss_res->start + CPSW2_BD_OFFSET; 2418549985eeSRichard Cochran break; 2419549985eeSRichard Cochran default: 2420549985eeSRichard Cochran dev_err(priv->dev, "unknown version 0x%08x\n", priv->version); 2421549985eeSRichard Cochran ret = -ENODEV; 2422aa1a15e2SDaniel Mack goto clean_runtime_disable_ret; 2423549985eeSRichard Cochran } 2424549985eeSRichard Cochran for (i = 0; i < priv->data.slaves; i++) { 2425549985eeSRichard Cochran struct cpsw_slave *slave = &priv->slaves[i]; 2426549985eeSRichard Cochran cpsw_slave_init(slave, priv, slave_offset, sliver_offset); 2427549985eeSRichard Cochran slave_offset += slave_size; 2428549985eeSRichard Cochran sliver_offset += SLIVER_SIZE; 2429549985eeSRichard Cochran } 2430549985eeSRichard Cochran 2431df828598SMugunthan V N dma_params.dev = &pdev->dev; 2432549985eeSRichard Cochran dma_params.rxthresh = dma_params.dmaregs + CPDMA_RXTHRESH; 2433549985eeSRichard Cochran dma_params.rxfree = dma_params.dmaregs + CPDMA_RXFREE; 2434549985eeSRichard Cochran dma_params.rxhdp = dma_params.txhdp + CPDMA_RXHDP; 2435549985eeSRichard Cochran dma_params.txcp = dma_params.txhdp + CPDMA_TXCP; 2436549985eeSRichard Cochran dma_params.rxcp = dma_params.txhdp + CPDMA_RXCP; 2437df828598SMugunthan V N 2438df828598SMugunthan V N dma_params.num_chan = data->channels; 2439df828598SMugunthan V N dma_params.has_soft_reset = true; 2440df828598SMugunthan V N dma_params.min_packet_size = CPSW_MIN_PACKET_SIZE; 2441df828598SMugunthan V N dma_params.desc_mem_size = data->bd_ram_size; 2442df828598SMugunthan V N dma_params.desc_align = 16; 2443df828598SMugunthan V N dma_params.has_ext_regs = true; 2444549985eeSRichard Cochran dma_params.desc_hw_addr = dma_params.desc_mem_phys; 2445df828598SMugunthan V N 2446df828598SMugunthan V N priv->dma = cpdma_ctlr_create(&dma_params); 2447df828598SMugunthan V N if (!priv->dma) { 2448df828598SMugunthan V N dev_err(priv->dev, "error initializing dma\n"); 2449df828598SMugunthan V N ret = -ENOMEM; 2450aa1a15e2SDaniel Mack goto clean_runtime_disable_ret; 2451df828598SMugunthan V N } 2452df828598SMugunthan V N 2453df828598SMugunthan V N priv->txch = cpdma_chan_create(priv->dma, tx_chan_num(0), 2454df828598SMugunthan V N cpsw_tx_handler); 2455df828598SMugunthan V N priv->rxch = cpdma_chan_create(priv->dma, rx_chan_num(0), 2456df828598SMugunthan V N cpsw_rx_handler); 2457df828598SMugunthan V N 2458df828598SMugunthan V N if (WARN_ON(!priv->txch || !priv->rxch)) { 2459df828598SMugunthan V N dev_err(priv->dev, "error initializing dma channels\n"); 2460df828598SMugunthan V N ret = -ENOMEM; 2461df828598SMugunthan V N goto clean_dma_ret; 2462df828598SMugunthan V N } 2463df828598SMugunthan V N 2464df828598SMugunthan V N ale_params.dev = &ndev->dev; 2465df828598SMugunthan V N ale_params.ale_ageout = ale_ageout; 2466df828598SMugunthan V N ale_params.ale_entries = data->ale_entries; 2467df828598SMugunthan V N ale_params.ale_ports = data->slaves; 2468df828598SMugunthan V N 2469df828598SMugunthan V N priv->ale = cpsw_ale_create(&ale_params); 2470df828598SMugunthan V N if (!priv->ale) { 2471df828598SMugunthan V N dev_err(priv->dev, "error initializing ale engine\n"); 2472df828598SMugunthan V N ret = -ENODEV; 2473df828598SMugunthan V N goto clean_dma_ret; 2474df828598SMugunthan V N } 2475df828598SMugunthan V N 2476c03abd84SFelipe Balbi ndev->irq = platform_get_irq(pdev, 1); 2477df828598SMugunthan V N if (ndev->irq < 0) { 2478df828598SMugunthan V N dev_err(priv->dev, "error getting irq resource\n"); 2479c1e3334fSJulia Lawall ret = ndev->irq; 2480df828598SMugunthan V N goto clean_ale_ret; 2481df828598SMugunthan V N } 2482df828598SMugunthan V N 24837da11600SMugunthan V N of_id = of_match_device(cpsw_of_mtable, &pdev->dev); 24847da11600SMugunthan V N if (of_id) { 24857da11600SMugunthan V N pdev->id_entry = of_id->data; 24867da11600SMugunthan V N if (pdev->id_entry->driver_data) 24877da11600SMugunthan V N priv->quirk_irq = true; 24887da11600SMugunthan V N } 24897da11600SMugunthan V N 2490c03abd84SFelipe Balbi /* Grab RX and TX IRQs. Note that we also have RX_THRESHOLD and 2491c03abd84SFelipe Balbi * MISC IRQs which are always kept disabled with this driver so 2492c03abd84SFelipe Balbi * we will not request them. 2493c03abd84SFelipe Balbi * 2494c03abd84SFelipe Balbi * If anyone wants to implement support for those, make sure to 2495c03abd84SFelipe Balbi * first request and append them to irqs_table array. 2496c03abd84SFelipe Balbi */ 2497c2b32e58SDaniel Mack 2498c03abd84SFelipe Balbi /* RX IRQ */ 24995087b915SFelipe Balbi irq = platform_get_irq(pdev, 1); 2500c1e3334fSJulia Lawall if (irq < 0) { 2501c1e3334fSJulia Lawall ret = irq; 25025087b915SFelipe Balbi goto clean_ale_ret; 2503c1e3334fSJulia Lawall } 25045087b915SFelipe Balbi 2505c03abd84SFelipe Balbi priv->irqs_table[0] = irq; 2506c03abd84SFelipe Balbi ret = devm_request_irq(&pdev->dev, irq, cpsw_rx_interrupt, 25075087b915SFelipe Balbi 0, dev_name(&pdev->dev), priv); 25085087b915SFelipe Balbi if (ret < 0) { 25095087b915SFelipe Balbi dev_err(priv->dev, "error attaching irq (%d)\n", ret); 25105087b915SFelipe Balbi goto clean_ale_ret; 2511df828598SMugunthan V N } 2512df828598SMugunthan V N 2513c03abd84SFelipe Balbi /* TX IRQ */ 25145087b915SFelipe Balbi irq = platform_get_irq(pdev, 2); 2515c1e3334fSJulia Lawall if (irq < 0) { 2516c1e3334fSJulia Lawall ret = irq; 25175087b915SFelipe Balbi goto clean_ale_ret; 2518c1e3334fSJulia Lawall } 25195087b915SFelipe Balbi 2520c03abd84SFelipe Balbi priv->irqs_table[1] = irq; 2521c03abd84SFelipe Balbi ret = devm_request_irq(&pdev->dev, irq, cpsw_tx_interrupt, 25225087b915SFelipe Balbi 0, dev_name(&pdev->dev), priv); 25235087b915SFelipe Balbi if (ret < 0) { 25245087b915SFelipe Balbi dev_err(priv->dev, "error attaching irq (%d)\n", ret); 25255087b915SFelipe Balbi goto clean_ale_ret; 25265087b915SFelipe Balbi } 2527c03abd84SFelipe Balbi priv->num_irqs = 2; 2528c2b32e58SDaniel Mack 2529f646968fSPatrick McHardy ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER; 2530df828598SMugunthan V N 2531df828598SMugunthan V N ndev->netdev_ops = &cpsw_netdev_ops; 25327ad24ea4SWilfried Klaebe ndev->ethtool_ops = &cpsw_ethtool_ops; 253332a7432cSMugunthan V N netif_napi_add(ndev, &priv->napi_rx, cpsw_rx_poll, CPSW_POLL_WEIGHT); 2534d64b5e85SEric Dumazet netif_tx_napi_add(ndev, &priv->napi_tx, cpsw_tx_poll, CPSW_POLL_WEIGHT); 2535df828598SMugunthan V N 2536df828598SMugunthan V N /* register the network device */ 2537df828598SMugunthan V N SET_NETDEV_DEV(ndev, &pdev->dev); 2538df828598SMugunthan V N ret = register_netdev(ndev); 2539df828598SMugunthan V N if (ret) { 2540df828598SMugunthan V N dev_err(priv->dev, "error registering net device\n"); 2541df828598SMugunthan V N ret = -ENODEV; 2542aa1a15e2SDaniel Mack goto clean_ale_ret; 2543df828598SMugunthan V N } 2544df828598SMugunthan V N 25451a3b5056SOlof Johansson cpsw_notice(priv, probe, "initialized device (regs %pa, irq %d)\n", 25461a3b5056SOlof Johansson &ss_res->start, ndev->irq); 2547df828598SMugunthan V N 2548d9ba8f9eSMugunthan V N if (priv->data.dual_emac) { 2549d9ba8f9eSMugunthan V N ret = cpsw_probe_dual_emac(pdev, priv); 2550d9ba8f9eSMugunthan V N if (ret) { 2551d9ba8f9eSMugunthan V N cpsw_err(priv, probe, "error probe slave 2 emac interface\n"); 2552aa1a15e2SDaniel Mack goto clean_ale_ret; 2553d9ba8f9eSMugunthan V N } 2554d9ba8f9eSMugunthan V N } 2555d9ba8f9eSMugunthan V N 2556df828598SMugunthan V N return 0; 2557df828598SMugunthan V N 2558df828598SMugunthan V N clean_ale_ret: 2559df828598SMugunthan V N cpsw_ale_destroy(priv->ale); 2560df828598SMugunthan V N clean_dma_ret: 2561df828598SMugunthan V N cpdma_ctlr_destroy(priv->dma); 2562aa1a15e2SDaniel Mack clean_runtime_disable_ret: 2563f150bd7fSMugunthan V N pm_runtime_disable(&pdev->dev); 2564df828598SMugunthan V N clean_ndev_ret: 2565d1bd9acfSSebastian Siewior free_netdev(priv->ndev); 2566df828598SMugunthan V N return ret; 2567df828598SMugunthan V N } 2568df828598SMugunthan V N 2569663e12e6SBill Pemberton static int cpsw_remove(struct platform_device *pdev) 2570df828598SMugunthan V N { 2571df828598SMugunthan V N struct net_device *ndev = platform_get_drvdata(pdev); 2572df828598SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 25738a0b6dc9SGrygorii Strashko int ret; 25748a0b6dc9SGrygorii Strashko 25758a0b6dc9SGrygorii Strashko ret = pm_runtime_get_sync(&pdev->dev); 25768a0b6dc9SGrygorii Strashko if (ret < 0) { 25778a0b6dc9SGrygorii Strashko pm_runtime_put_noidle(&pdev->dev); 25788a0b6dc9SGrygorii Strashko return ret; 25798a0b6dc9SGrygorii Strashko } 2580df828598SMugunthan V N 2581d1bd9acfSSebastian Siewior if (priv->data.dual_emac) 2582d1bd9acfSSebastian Siewior unregister_netdev(cpsw_get_slave_ndev(priv, 1)); 2583d1bd9acfSSebastian Siewior unregister_netdev(ndev); 2584df828598SMugunthan V N 2585df828598SMugunthan V N cpsw_ale_destroy(priv->ale); 2586df828598SMugunthan V N cpdma_ctlr_destroy(priv->dma); 25873bf2cb3aSGrygorii Strashko of_platform_depopulate(&pdev->dev); 25888a0b6dc9SGrygorii Strashko pm_runtime_put_sync(&pdev->dev); 25898a0b6dc9SGrygorii Strashko pm_runtime_disable(&pdev->dev); 2590d1bd9acfSSebastian Siewior if (priv->data.dual_emac) 2591d1bd9acfSSebastian Siewior free_netdev(cpsw_get_slave_ndev(priv, 1)); 2592df828598SMugunthan V N free_netdev(ndev); 2593df828598SMugunthan V N return 0; 2594df828598SMugunthan V N } 2595df828598SMugunthan V N 25968963a504SGrygorii Strashko #ifdef CONFIG_PM_SLEEP 2597df828598SMugunthan V N static int cpsw_suspend(struct device *dev) 2598df828598SMugunthan V N { 2599df828598SMugunthan V N struct platform_device *pdev = to_platform_device(dev); 2600df828598SMugunthan V N struct net_device *ndev = platform_get_drvdata(pdev); 2601b90fc27aSMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 2602df828598SMugunthan V N 2603618073e3SMugunthan V N if (priv->data.dual_emac) { 2604618073e3SMugunthan V N int i; 2605618073e3SMugunthan V N 2606618073e3SMugunthan V N for (i = 0; i < priv->data.slaves; i++) { 2607618073e3SMugunthan V N if (netif_running(priv->slaves[i].ndev)) 2608618073e3SMugunthan V N cpsw_ndo_stop(priv->slaves[i].ndev); 2609618073e3SMugunthan V N } 2610618073e3SMugunthan V N } else { 2611df828598SMugunthan V N if (netif_running(ndev)) 2612df828598SMugunthan V N cpsw_ndo_stop(ndev); 2613618073e3SMugunthan V N } 26141e7a2e21SDaniel Mack 2615739683b4SMugunthan V N /* Select sleep pin state */ 2616739683b4SMugunthan V N pinctrl_pm_select_sleep_state(&pdev->dev); 2617739683b4SMugunthan V N 2618df828598SMugunthan V N return 0; 2619df828598SMugunthan V N } 2620df828598SMugunthan V N 2621df828598SMugunthan V N static int cpsw_resume(struct device *dev) 2622df828598SMugunthan V N { 2623df828598SMugunthan V N struct platform_device *pdev = to_platform_device(dev); 2624df828598SMugunthan V N struct net_device *ndev = platform_get_drvdata(pdev); 2625618073e3SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 2626df828598SMugunthan V N 2627739683b4SMugunthan V N /* Select default pin state */ 2628739683b4SMugunthan V N pinctrl_pm_select_default_state(&pdev->dev); 2629739683b4SMugunthan V N 2630618073e3SMugunthan V N if (priv->data.dual_emac) { 2631618073e3SMugunthan V N int i; 2632618073e3SMugunthan V N 2633618073e3SMugunthan V N for (i = 0; i < priv->data.slaves; i++) { 2634618073e3SMugunthan V N if (netif_running(priv->slaves[i].ndev)) 2635618073e3SMugunthan V N cpsw_ndo_open(priv->slaves[i].ndev); 2636618073e3SMugunthan V N } 2637618073e3SMugunthan V N } else { 2638df828598SMugunthan V N if (netif_running(ndev)) 2639df828598SMugunthan V N cpsw_ndo_open(ndev); 2640618073e3SMugunthan V N } 2641df828598SMugunthan V N return 0; 2642df828598SMugunthan V N } 26438963a504SGrygorii Strashko #endif 2644df828598SMugunthan V N 26458963a504SGrygorii Strashko static SIMPLE_DEV_PM_OPS(cpsw_pm_ops, cpsw_suspend, cpsw_resume); 2646df828598SMugunthan V N 2647df828598SMugunthan V N static struct platform_driver cpsw_driver = { 2648df828598SMugunthan V N .driver = { 2649df828598SMugunthan V N .name = "cpsw", 2650df828598SMugunthan V N .pm = &cpsw_pm_ops, 26511e5c76d4SSachin Kamat .of_match_table = cpsw_of_mtable, 2652df828598SMugunthan V N }, 2653df828598SMugunthan V N .probe = cpsw_probe, 2654663e12e6SBill Pemberton .remove = cpsw_remove, 2655df828598SMugunthan V N }; 2656df828598SMugunthan V N 26576fb3b6b5SGrygorii Strashko module_platform_driver(cpsw_driver); 2658df828598SMugunthan V N 2659df828598SMugunthan V N MODULE_LICENSE("GPL"); 2660df828598SMugunthan V N MODULE_AUTHOR("Cyril Chemparathy <cyril@ti.com>"); 2661df828598SMugunthan V N MODULE_AUTHOR("Mugunthan V N <mugunthanvnm@ti.com>"); 2662df828598SMugunthan V N MODULE_DESCRIPTION("TI CPSW Ethernet driver"); 2663