1df828598SMugunthan V N /* 2df828598SMugunthan V N * Texas Instruments Ethernet Switch Driver 3df828598SMugunthan V N * 4df828598SMugunthan V N * Copyright (C) 2012 Texas Instruments 5df828598SMugunthan V N * 6df828598SMugunthan V N * This program is free software; you can redistribute it and/or 7df828598SMugunthan V N * modify it under the terms of the GNU General Public License as 8df828598SMugunthan V N * published by the Free Software Foundation version 2. 9df828598SMugunthan V N * 10df828598SMugunthan V N * This program is distributed "as is" WITHOUT ANY WARRANTY of any 11df828598SMugunthan V N * kind, whether express or implied; without even the implied warranty 12df828598SMugunthan V N * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13df828598SMugunthan V N * GNU General Public License for more details. 14df828598SMugunthan V N */ 15df828598SMugunthan V N 16df828598SMugunthan V N #include <linux/kernel.h> 17df828598SMugunthan V N #include <linux/io.h> 18df828598SMugunthan V N #include <linux/clk.h> 19df828598SMugunthan V N #include <linux/timer.h> 20df828598SMugunthan V N #include <linux/module.h> 21df828598SMugunthan V N #include <linux/platform_device.h> 22df828598SMugunthan V N #include <linux/irqreturn.h> 23df828598SMugunthan V N #include <linux/interrupt.h> 24df828598SMugunthan V N #include <linux/if_ether.h> 25df828598SMugunthan V N #include <linux/etherdevice.h> 26df828598SMugunthan V N #include <linux/netdevice.h> 272e5b38abSRichard Cochran #include <linux/net_tstamp.h> 28df828598SMugunthan V N #include <linux/phy.h> 29df828598SMugunthan V N #include <linux/workqueue.h> 30df828598SMugunthan V N #include <linux/delay.h> 31f150bd7fSMugunthan V N #include <linux/pm_runtime.h> 321d147ccbSMugunthan V N #include <linux/gpio.h> 332eb32b0aSMugunthan V N #include <linux/of.h> 349e42f715SHeiko Schocher #include <linux/of_mdio.h> 352eb32b0aSMugunthan V N #include <linux/of_net.h> 362eb32b0aSMugunthan V N #include <linux/of_device.h> 373b72c2feSMugunthan V N #include <linux/if_vlan.h> 38df828598SMugunthan V N 39739683b4SMugunthan V N #include <linux/pinctrl/consumer.h> 40df828598SMugunthan V N 41dbe34724SMugunthan V N #include "cpsw.h" 42df828598SMugunthan V N #include "cpsw_ale.h" 432e5b38abSRichard Cochran #include "cpts.h" 44df828598SMugunthan V N #include "davinci_cpdma.h" 45df828598SMugunthan V N 46df828598SMugunthan V N #define CPSW_DEBUG (NETIF_MSG_HW | NETIF_MSG_WOL | \ 47df828598SMugunthan V N NETIF_MSG_DRV | NETIF_MSG_LINK | \ 48df828598SMugunthan V N NETIF_MSG_IFUP | NETIF_MSG_INTR | \ 49df828598SMugunthan V N NETIF_MSG_PROBE | NETIF_MSG_TIMER | \ 50df828598SMugunthan V N NETIF_MSG_IFDOWN | NETIF_MSG_RX_ERR | \ 51df828598SMugunthan V N NETIF_MSG_TX_ERR | NETIF_MSG_TX_DONE | \ 52df828598SMugunthan V N NETIF_MSG_PKTDATA | NETIF_MSG_TX_QUEUED | \ 53df828598SMugunthan V N NETIF_MSG_RX_STATUS) 54df828598SMugunthan V N 55df828598SMugunthan V N #define cpsw_info(priv, type, format, ...) \ 56df828598SMugunthan V N do { \ 57df828598SMugunthan V N if (netif_msg_##type(priv) && net_ratelimit()) \ 58df828598SMugunthan V N dev_info(priv->dev, format, ## __VA_ARGS__); \ 59df828598SMugunthan V N } while (0) 60df828598SMugunthan V N 61df828598SMugunthan V N #define cpsw_err(priv, type, format, ...) \ 62df828598SMugunthan V N do { \ 63df828598SMugunthan V N if (netif_msg_##type(priv) && net_ratelimit()) \ 64df828598SMugunthan V N dev_err(priv->dev, format, ## __VA_ARGS__); \ 65df828598SMugunthan V N } while (0) 66df828598SMugunthan V N 67df828598SMugunthan V N #define cpsw_dbg(priv, type, format, ...) \ 68df828598SMugunthan V N do { \ 69df828598SMugunthan V N if (netif_msg_##type(priv) && net_ratelimit()) \ 70df828598SMugunthan V N dev_dbg(priv->dev, format, ## __VA_ARGS__); \ 71df828598SMugunthan V N } while (0) 72df828598SMugunthan V N 73df828598SMugunthan V N #define cpsw_notice(priv, type, format, ...) \ 74df828598SMugunthan V N do { \ 75df828598SMugunthan V N if (netif_msg_##type(priv) && net_ratelimit()) \ 76df828598SMugunthan V N dev_notice(priv->dev, format, ## __VA_ARGS__); \ 77df828598SMugunthan V N } while (0) 78df828598SMugunthan V N 795c50a856SMugunthan V N #define ALE_ALL_PORTS 0x7 805c50a856SMugunthan V N 81df828598SMugunthan V N #define CPSW_MAJOR_VERSION(reg) (reg >> 8 & 0x7) 82df828598SMugunthan V N #define CPSW_MINOR_VERSION(reg) (reg & 0xff) 83df828598SMugunthan V N #define CPSW_RTL_VERSION(reg) ((reg >> 11) & 0x1f) 84df828598SMugunthan V N 85e90cfac6SRichard Cochran #define CPSW_VERSION_1 0x19010a 86e90cfac6SRichard Cochran #define CPSW_VERSION_2 0x19010c 87c193f365SMugunthan V N #define CPSW_VERSION_3 0x19010f 88926489beSMugunthan V N #define CPSW_VERSION_4 0x190112 89549985eeSRichard Cochran 90549985eeSRichard Cochran #define HOST_PORT_NUM 0 91549985eeSRichard Cochran #define SLIVER_SIZE 0x40 92549985eeSRichard Cochran 93549985eeSRichard Cochran #define CPSW1_HOST_PORT_OFFSET 0x028 94549985eeSRichard Cochran #define CPSW1_SLAVE_OFFSET 0x050 95549985eeSRichard Cochran #define CPSW1_SLAVE_SIZE 0x040 96549985eeSRichard Cochran #define CPSW1_CPDMA_OFFSET 0x100 97549985eeSRichard Cochran #define CPSW1_STATERAM_OFFSET 0x200 98d9718546SMugunthan V N #define CPSW1_HW_STATS 0x400 99549985eeSRichard Cochran #define CPSW1_CPTS_OFFSET 0x500 100549985eeSRichard Cochran #define CPSW1_ALE_OFFSET 0x600 101549985eeSRichard Cochran #define CPSW1_SLIVER_OFFSET 0x700 102549985eeSRichard Cochran 103549985eeSRichard Cochran #define CPSW2_HOST_PORT_OFFSET 0x108 104549985eeSRichard Cochran #define CPSW2_SLAVE_OFFSET 0x200 105549985eeSRichard Cochran #define CPSW2_SLAVE_SIZE 0x100 106549985eeSRichard Cochran #define CPSW2_CPDMA_OFFSET 0x800 107d9718546SMugunthan V N #define CPSW2_HW_STATS 0x900 108549985eeSRichard Cochran #define CPSW2_STATERAM_OFFSET 0xa00 109549985eeSRichard Cochran #define CPSW2_CPTS_OFFSET 0xc00 110549985eeSRichard Cochran #define CPSW2_ALE_OFFSET 0xd00 111549985eeSRichard Cochran #define CPSW2_SLIVER_OFFSET 0xd80 112549985eeSRichard Cochran #define CPSW2_BD_OFFSET 0x2000 113549985eeSRichard Cochran 114df828598SMugunthan V N #define CPDMA_RXTHRESH 0x0c0 115df828598SMugunthan V N #define CPDMA_RXFREE 0x0e0 116df828598SMugunthan V N #define CPDMA_TXHDP 0x00 117df828598SMugunthan V N #define CPDMA_RXHDP 0x20 118df828598SMugunthan V N #define CPDMA_TXCP 0x40 119df828598SMugunthan V N #define CPDMA_RXCP 0x60 120df828598SMugunthan V N 121df828598SMugunthan V N #define CPSW_POLL_WEIGHT 64 122df828598SMugunthan V N #define CPSW_MIN_PACKET_SIZE 60 123df828598SMugunthan V N #define CPSW_MAX_PACKET_SIZE (1500 + 14 + 4 + 4) 124df828598SMugunthan V N 125df828598SMugunthan V N #define RX_PRIORITY_MAPPING 0x76543210 126df828598SMugunthan V N #define TX_PRIORITY_MAPPING 0x33221100 127e05107e6SIvan Khoronzhuk #define CPDMA_TX_PRIORITY_MAP 0x01234567 128df828598SMugunthan V N 1293b72c2feSMugunthan V N #define CPSW_VLAN_AWARE BIT(1) 1303b72c2feSMugunthan V N #define CPSW_ALE_VLAN_AWARE 1 1313b72c2feSMugunthan V N 13235717d8dSJohn Ogness #define CPSW_FIFO_NORMAL_MODE (0 << 16) 13335717d8dSJohn Ogness #define CPSW_FIFO_DUAL_MAC_MODE (1 << 16) 13435717d8dSJohn Ogness #define CPSW_FIFO_RATE_LIMIT_MODE (2 << 16) 135d9ba8f9eSMugunthan V N 136ff5b8ef2SMugunthan V N #define CPSW_INTPACEEN (0x3f << 16) 137ff5b8ef2SMugunthan V N #define CPSW_INTPRESCALE_MASK (0x7FF << 0) 138ff5b8ef2SMugunthan V N #define CPSW_CMINTMAX_CNT 63 139ff5b8ef2SMugunthan V N #define CPSW_CMINTMIN_CNT 2 140ff5b8ef2SMugunthan V N #define CPSW_CMINTMAX_INTVL (1000 / CPSW_CMINTMIN_CNT) 141ff5b8ef2SMugunthan V N #define CPSW_CMINTMIN_INTVL ((1000 / CPSW_CMINTMAX_CNT) + 1) 142ff5b8ef2SMugunthan V N 143606f3993SIvan Khoronzhuk #define cpsw_slave_index(cpsw, priv) \ 144606f3993SIvan Khoronzhuk ((cpsw->data.dual_emac) ? priv->emac_port : \ 145606f3993SIvan Khoronzhuk cpsw->data.active_slave) 146e38b5a3dSIvan Khoronzhuk #define IRQ_NUM 2 147e05107e6SIvan Khoronzhuk #define CPSW_MAX_QUEUES 8 148d3bb9c58SMugunthan V N 149df828598SMugunthan V N static int debug_level; 150df828598SMugunthan V N module_param(debug_level, int, 0); 151df828598SMugunthan V N MODULE_PARM_DESC(debug_level, "cpsw debug level (NETIF_MSG bits)"); 152df828598SMugunthan V N 153df828598SMugunthan V N static int ale_ageout = 10; 154df828598SMugunthan V N module_param(ale_ageout, int, 0); 155df828598SMugunthan V N MODULE_PARM_DESC(ale_ageout, "cpsw ale ageout interval (seconds)"); 156df828598SMugunthan V N 157df828598SMugunthan V N static int rx_packet_max = CPSW_MAX_PACKET_SIZE; 158df828598SMugunthan V N module_param(rx_packet_max, int, 0); 159df828598SMugunthan V N MODULE_PARM_DESC(rx_packet_max, "maximum receive packet size (bytes)"); 160df828598SMugunthan V N 161996a5c27SRichard Cochran struct cpsw_wr_regs { 162df828598SMugunthan V N u32 id_ver; 163df828598SMugunthan V N u32 soft_reset; 164df828598SMugunthan V N u32 control; 165df828598SMugunthan V N u32 int_control; 166df828598SMugunthan V N u32 rx_thresh_en; 167df828598SMugunthan V N u32 rx_en; 168df828598SMugunthan V N u32 tx_en; 169df828598SMugunthan V N u32 misc_en; 170ff5b8ef2SMugunthan V N u32 mem_allign1[8]; 171ff5b8ef2SMugunthan V N u32 rx_thresh_stat; 172ff5b8ef2SMugunthan V N u32 rx_stat; 173ff5b8ef2SMugunthan V N u32 tx_stat; 174ff5b8ef2SMugunthan V N u32 misc_stat; 175ff5b8ef2SMugunthan V N u32 mem_allign2[8]; 176ff5b8ef2SMugunthan V N u32 rx_imax; 177ff5b8ef2SMugunthan V N u32 tx_imax; 178ff5b8ef2SMugunthan V N 179df828598SMugunthan V N }; 180df828598SMugunthan V N 181996a5c27SRichard Cochran struct cpsw_ss_regs { 182df828598SMugunthan V N u32 id_ver; 183df828598SMugunthan V N u32 control; 184df828598SMugunthan V N u32 soft_reset; 185df828598SMugunthan V N u32 stat_port_en; 186df828598SMugunthan V N u32 ptype; 187bd357af2SRichard Cochran u32 soft_idle; 188bd357af2SRichard Cochran u32 thru_rate; 189bd357af2SRichard Cochran u32 gap_thresh; 190bd357af2SRichard Cochran u32 tx_start_wds; 191bd357af2SRichard Cochran u32 flow_control; 192bd357af2SRichard Cochran u32 vlan_ltype; 193bd357af2SRichard Cochran u32 ts_ltype; 194bd357af2SRichard Cochran u32 dlr_ltype; 195df828598SMugunthan V N }; 196df828598SMugunthan V N 1979750a3adSRichard Cochran /* CPSW_PORT_V1 */ 1989750a3adSRichard Cochran #define CPSW1_MAX_BLKS 0x00 /* Maximum FIFO Blocks */ 1999750a3adSRichard Cochran #define CPSW1_BLK_CNT 0x04 /* FIFO Block Usage Count (Read Only) */ 2009750a3adSRichard Cochran #define CPSW1_TX_IN_CTL 0x08 /* Transmit FIFO Control */ 2019750a3adSRichard Cochran #define CPSW1_PORT_VLAN 0x0c /* VLAN Register */ 2029750a3adSRichard Cochran #define CPSW1_TX_PRI_MAP 0x10 /* Tx Header Priority to Switch Pri Mapping */ 2039750a3adSRichard Cochran #define CPSW1_TS_CTL 0x14 /* Time Sync Control */ 2049750a3adSRichard Cochran #define CPSW1_TS_SEQ_LTYPE 0x18 /* Time Sync Sequence ID Offset and Msg Type */ 2059750a3adSRichard Cochran #define CPSW1_TS_VLAN 0x1c /* Time Sync VLAN1 and VLAN2 */ 2069750a3adSRichard Cochran 2079750a3adSRichard Cochran /* CPSW_PORT_V2 */ 2089750a3adSRichard Cochran #define CPSW2_CONTROL 0x00 /* Control Register */ 2099750a3adSRichard Cochran #define CPSW2_MAX_BLKS 0x08 /* Maximum FIFO Blocks */ 2109750a3adSRichard Cochran #define CPSW2_BLK_CNT 0x0c /* FIFO Block Usage Count (Read Only) */ 2119750a3adSRichard Cochran #define CPSW2_TX_IN_CTL 0x10 /* Transmit FIFO Control */ 2129750a3adSRichard Cochran #define CPSW2_PORT_VLAN 0x14 /* VLAN Register */ 2139750a3adSRichard Cochran #define CPSW2_TX_PRI_MAP 0x18 /* Tx Header Priority to Switch Pri Mapping */ 2149750a3adSRichard Cochran #define CPSW2_TS_SEQ_MTYPE 0x1c /* Time Sync Sequence ID Offset and Msg Type */ 2159750a3adSRichard Cochran 2169750a3adSRichard Cochran /* CPSW_PORT_V1 and V2 */ 2179750a3adSRichard Cochran #define SA_LO 0x20 /* CPGMAC_SL Source Address Low */ 2189750a3adSRichard Cochran #define SA_HI 0x24 /* CPGMAC_SL Source Address High */ 2199750a3adSRichard Cochran #define SEND_PERCENT 0x28 /* Transmit Queue Send Percentages */ 2209750a3adSRichard Cochran 2219750a3adSRichard Cochran /* CPSW_PORT_V2 only */ 2229750a3adSRichard Cochran #define RX_DSCP_PRI_MAP0 0x30 /* Rx DSCP Priority to Rx Packet Mapping */ 2239750a3adSRichard Cochran #define RX_DSCP_PRI_MAP1 0x34 /* Rx DSCP Priority to Rx Packet Mapping */ 2249750a3adSRichard Cochran #define RX_DSCP_PRI_MAP2 0x38 /* Rx DSCP Priority to Rx Packet Mapping */ 2259750a3adSRichard Cochran #define RX_DSCP_PRI_MAP3 0x3c /* Rx DSCP Priority to Rx Packet Mapping */ 2269750a3adSRichard Cochran #define RX_DSCP_PRI_MAP4 0x40 /* Rx DSCP Priority to Rx Packet Mapping */ 2279750a3adSRichard Cochran #define RX_DSCP_PRI_MAP5 0x44 /* Rx DSCP Priority to Rx Packet Mapping */ 2289750a3adSRichard Cochran #define RX_DSCP_PRI_MAP6 0x48 /* Rx DSCP Priority to Rx Packet Mapping */ 2299750a3adSRichard Cochran #define RX_DSCP_PRI_MAP7 0x4c /* Rx DSCP Priority to Rx Packet Mapping */ 2309750a3adSRichard Cochran 2319750a3adSRichard Cochran /* Bit definitions for the CPSW2_CONTROL register */ 2329750a3adSRichard Cochran #define PASS_PRI_TAGGED (1<<24) /* Pass Priority Tagged */ 2339750a3adSRichard Cochran #define VLAN_LTYPE2_EN (1<<21) /* VLAN LTYPE 2 enable */ 2349750a3adSRichard Cochran #define VLAN_LTYPE1_EN (1<<20) /* VLAN LTYPE 1 enable */ 2359750a3adSRichard Cochran #define DSCP_PRI_EN (1<<16) /* DSCP Priority Enable */ 2369750a3adSRichard Cochran #define TS_320 (1<<14) /* Time Sync Dest Port 320 enable */ 2379750a3adSRichard Cochran #define TS_319 (1<<13) /* Time Sync Dest Port 319 enable */ 2389750a3adSRichard Cochran #define TS_132 (1<<12) /* Time Sync Dest IP Addr 132 enable */ 2399750a3adSRichard Cochran #define TS_131 (1<<11) /* Time Sync Dest IP Addr 131 enable */ 2409750a3adSRichard Cochran #define TS_130 (1<<10) /* Time Sync Dest IP Addr 130 enable */ 2419750a3adSRichard Cochran #define TS_129 (1<<9) /* Time Sync Dest IP Addr 129 enable */ 24209c55372SGeorge Cherian #define TS_TTL_NONZERO (1<<8) /* Time Sync Time To Live Non-zero enable */ 24309c55372SGeorge Cherian #define TS_ANNEX_F_EN (1<<6) /* Time Sync Annex F enable */ 2449750a3adSRichard Cochran #define TS_ANNEX_D_EN (1<<4) /* Time Sync Annex D enable */ 2459750a3adSRichard Cochran #define TS_LTYPE2_EN (1<<3) /* Time Sync LTYPE 2 enable */ 2469750a3adSRichard Cochran #define TS_LTYPE1_EN (1<<2) /* Time Sync LTYPE 1 enable */ 2479750a3adSRichard Cochran #define TS_TX_EN (1<<1) /* Time Sync Transmit Enable */ 2489750a3adSRichard Cochran #define TS_RX_EN (1<<0) /* Time Sync Receive Enable */ 2499750a3adSRichard Cochran 25009c55372SGeorge Cherian #define CTRL_V2_TS_BITS \ 25109c55372SGeorge Cherian (TS_320 | TS_319 | TS_132 | TS_131 | TS_130 | TS_129 |\ 25209c55372SGeorge Cherian TS_TTL_NONZERO | TS_ANNEX_D_EN | TS_LTYPE1_EN) 2539750a3adSRichard Cochran 25409c55372SGeorge Cherian #define CTRL_V2_ALL_TS_MASK (CTRL_V2_TS_BITS | TS_TX_EN | TS_RX_EN) 25509c55372SGeorge Cherian #define CTRL_V2_TX_TS_BITS (CTRL_V2_TS_BITS | TS_TX_EN) 25609c55372SGeorge Cherian #define CTRL_V2_RX_TS_BITS (CTRL_V2_TS_BITS | TS_RX_EN) 25709c55372SGeorge Cherian 25809c55372SGeorge Cherian 25909c55372SGeorge Cherian #define CTRL_V3_TS_BITS \ 26009c55372SGeorge Cherian (TS_320 | TS_319 | TS_132 | TS_131 | TS_130 | TS_129 |\ 26109c55372SGeorge Cherian TS_TTL_NONZERO | TS_ANNEX_F_EN | TS_ANNEX_D_EN |\ 26209c55372SGeorge Cherian TS_LTYPE1_EN) 26309c55372SGeorge Cherian 26409c55372SGeorge Cherian #define CTRL_V3_ALL_TS_MASK (CTRL_V3_TS_BITS | TS_TX_EN | TS_RX_EN) 26509c55372SGeorge Cherian #define CTRL_V3_TX_TS_BITS (CTRL_V3_TS_BITS | TS_TX_EN) 26609c55372SGeorge Cherian #define CTRL_V3_RX_TS_BITS (CTRL_V3_TS_BITS | TS_RX_EN) 2679750a3adSRichard Cochran 2689750a3adSRichard Cochran /* Bit definitions for the CPSW2_TS_SEQ_MTYPE register */ 2699750a3adSRichard Cochran #define TS_SEQ_ID_OFFSET_SHIFT (16) /* Time Sync Sequence ID Offset */ 2709750a3adSRichard Cochran #define TS_SEQ_ID_OFFSET_MASK (0x3f) 2719750a3adSRichard Cochran #define TS_MSG_TYPE_EN_SHIFT (0) /* Time Sync Message Type Enable */ 2729750a3adSRichard Cochran #define TS_MSG_TYPE_EN_MASK (0xffff) 2739750a3adSRichard Cochran 2749750a3adSRichard Cochran /* The PTP event messages - Sync, Delay_Req, Pdelay_Req, and Pdelay_Resp. */ 2759750a3adSRichard Cochran #define EVENT_MSG_BITS ((1<<0) | (1<<1) | (1<<2) | (1<<3)) 276df828598SMugunthan V N 2772e5b38abSRichard Cochran /* Bit definitions for the CPSW1_TS_CTL register */ 2782e5b38abSRichard Cochran #define CPSW_V1_TS_RX_EN BIT(0) 2792e5b38abSRichard Cochran #define CPSW_V1_TS_TX_EN BIT(4) 2802e5b38abSRichard Cochran #define CPSW_V1_MSG_TYPE_OFS 16 2812e5b38abSRichard Cochran 2822e5b38abSRichard Cochran /* Bit definitions for the CPSW1_TS_SEQ_LTYPE register */ 2832e5b38abSRichard Cochran #define CPSW_V1_SEQ_ID_OFS_SHIFT 16 2842e5b38abSRichard Cochran 285df828598SMugunthan V N struct cpsw_host_regs { 286df828598SMugunthan V N u32 max_blks; 287df828598SMugunthan V N u32 blk_cnt; 288d9ba8f9eSMugunthan V N u32 tx_in_ctl; 289df828598SMugunthan V N u32 port_vlan; 290df828598SMugunthan V N u32 tx_pri_map; 291df828598SMugunthan V N u32 cpdma_tx_pri_map; 292df828598SMugunthan V N u32 cpdma_rx_chan_map; 293df828598SMugunthan V N }; 294df828598SMugunthan V N 295df828598SMugunthan V N struct cpsw_sliver_regs { 296df828598SMugunthan V N u32 id_ver; 297df828598SMugunthan V N u32 mac_control; 298df828598SMugunthan V N u32 mac_status; 299df828598SMugunthan V N u32 soft_reset; 300df828598SMugunthan V N u32 rx_maxlen; 301df828598SMugunthan V N u32 __reserved_0; 302df828598SMugunthan V N u32 rx_pause; 303df828598SMugunthan V N u32 tx_pause; 304df828598SMugunthan V N u32 __reserved_1; 305df828598SMugunthan V N u32 rx_pri_map; 306df828598SMugunthan V N }; 307df828598SMugunthan V N 308d9718546SMugunthan V N struct cpsw_hw_stats { 309d9718546SMugunthan V N u32 rxgoodframes; 310d9718546SMugunthan V N u32 rxbroadcastframes; 311d9718546SMugunthan V N u32 rxmulticastframes; 312d9718546SMugunthan V N u32 rxpauseframes; 313d9718546SMugunthan V N u32 rxcrcerrors; 314d9718546SMugunthan V N u32 rxaligncodeerrors; 315d9718546SMugunthan V N u32 rxoversizedframes; 316d9718546SMugunthan V N u32 rxjabberframes; 317d9718546SMugunthan V N u32 rxundersizedframes; 318d9718546SMugunthan V N u32 rxfragments; 319d9718546SMugunthan V N u32 __pad_0[2]; 320d9718546SMugunthan V N u32 rxoctets; 321d9718546SMugunthan V N u32 txgoodframes; 322d9718546SMugunthan V N u32 txbroadcastframes; 323d9718546SMugunthan V N u32 txmulticastframes; 324d9718546SMugunthan V N u32 txpauseframes; 325d9718546SMugunthan V N u32 txdeferredframes; 326d9718546SMugunthan V N u32 txcollisionframes; 327d9718546SMugunthan V N u32 txsinglecollframes; 328d9718546SMugunthan V N u32 txmultcollframes; 329d9718546SMugunthan V N u32 txexcessivecollisions; 330d9718546SMugunthan V N u32 txlatecollisions; 331d9718546SMugunthan V N u32 txunderrun; 332d9718546SMugunthan V N u32 txcarriersenseerrors; 333d9718546SMugunthan V N u32 txoctets; 334d9718546SMugunthan V N u32 octetframes64; 335d9718546SMugunthan V N u32 octetframes65t127; 336d9718546SMugunthan V N u32 octetframes128t255; 337d9718546SMugunthan V N u32 octetframes256t511; 338d9718546SMugunthan V N u32 octetframes512t1023; 339d9718546SMugunthan V N u32 octetframes1024tup; 340d9718546SMugunthan V N u32 netoctets; 341d9718546SMugunthan V N u32 rxsofoverruns; 342d9718546SMugunthan V N u32 rxmofoverruns; 343d9718546SMugunthan V N u32 rxdmaoverruns; 344d9718546SMugunthan V N }; 345d9718546SMugunthan V N 346df828598SMugunthan V N struct cpsw_slave { 3479750a3adSRichard Cochran void __iomem *regs; 348df828598SMugunthan V N struct cpsw_sliver_regs __iomem *sliver; 349df828598SMugunthan V N int slave_num; 350df828598SMugunthan V N u32 mac_control; 351df828598SMugunthan V N struct cpsw_slave_data *data; 352df828598SMugunthan V N struct phy_device *phy; 353d9ba8f9eSMugunthan V N struct net_device *ndev; 354d9ba8f9eSMugunthan V N u32 port_vlan; 355d9ba8f9eSMugunthan V N u32 open_stat; 356df828598SMugunthan V N }; 357df828598SMugunthan V N 3589750a3adSRichard Cochran static inline u32 slave_read(struct cpsw_slave *slave, u32 offset) 3599750a3adSRichard Cochran { 3609750a3adSRichard Cochran return __raw_readl(slave->regs + offset); 3619750a3adSRichard Cochran } 3629750a3adSRichard Cochran 3639750a3adSRichard Cochran static inline void slave_write(struct cpsw_slave *slave, u32 val, u32 offset) 3649750a3adSRichard Cochran { 3659750a3adSRichard Cochran __raw_writel(val, slave->regs + offset); 3669750a3adSRichard Cochran } 3679750a3adSRichard Cochran 368649a1688SIvan Khoronzhuk struct cpsw_common { 36956e31bd8SIvan Khoronzhuk struct device *dev; 370606f3993SIvan Khoronzhuk struct cpsw_platform_data data; 371dbc4ec52SIvan Khoronzhuk struct napi_struct napi_rx; 372dbc4ec52SIvan Khoronzhuk struct napi_struct napi_tx; 3735d8d0d4dSIvan Khoronzhuk struct cpsw_ss_regs __iomem *regs; 3745d8d0d4dSIvan Khoronzhuk struct cpsw_wr_regs __iomem *wr_regs; 3755d8d0d4dSIvan Khoronzhuk u8 __iomem *hw_stats; 3765d8d0d4dSIvan Khoronzhuk struct cpsw_host_regs __iomem *host_port_regs; 3772a05a622SIvan Khoronzhuk u32 version; 3782a05a622SIvan Khoronzhuk u32 coal_intvl; 3792a05a622SIvan Khoronzhuk u32 bus_freq_mhz; 3802a05a622SIvan Khoronzhuk int rx_packet_max; 381606f3993SIvan Khoronzhuk struct cpsw_slave *slaves; 3822c836bd9SIvan Khoronzhuk struct cpdma_ctlr *dma; 383e05107e6SIvan Khoronzhuk struct cpdma_chan *txch[CPSW_MAX_QUEUES]; 384e05107e6SIvan Khoronzhuk struct cpdma_chan *rxch[CPSW_MAX_QUEUES]; 3852a05a622SIvan Khoronzhuk struct cpsw_ale *ale; 386e38b5a3dSIvan Khoronzhuk bool quirk_irq; 387e38b5a3dSIvan Khoronzhuk bool rx_irq_disabled; 388e38b5a3dSIvan Khoronzhuk bool tx_irq_disabled; 389e38b5a3dSIvan Khoronzhuk u32 irqs_table[IRQ_NUM]; 3902a05a622SIvan Khoronzhuk struct cpts *cpts; 391e05107e6SIvan Khoronzhuk int rx_ch_num, tx_ch_num; 392649a1688SIvan Khoronzhuk }; 393649a1688SIvan Khoronzhuk 394649a1688SIvan Khoronzhuk struct cpsw_priv { 395df828598SMugunthan V N struct net_device *ndev; 396df828598SMugunthan V N struct device *dev; 397df828598SMugunthan V N u32 msg_enable; 398df828598SMugunthan V N u8 mac_addr[ETH_ALEN]; 3991923d6e4SMugunthan V N bool rx_pause; 4001923d6e4SMugunthan V N bool tx_pause; 401d9ba8f9eSMugunthan V N u32 emac_port; 402649a1688SIvan Khoronzhuk struct cpsw_common *cpsw; 403df828598SMugunthan V N }; 404df828598SMugunthan V N 405d9718546SMugunthan V N struct cpsw_stats { 406d9718546SMugunthan V N char stat_string[ETH_GSTRING_LEN]; 407d9718546SMugunthan V N int type; 408d9718546SMugunthan V N int sizeof_stat; 409d9718546SMugunthan V N int stat_offset; 410d9718546SMugunthan V N }; 411d9718546SMugunthan V N 412d9718546SMugunthan V N enum { 413d9718546SMugunthan V N CPSW_STATS, 414d9718546SMugunthan V N CPDMA_RX_STATS, 415d9718546SMugunthan V N CPDMA_TX_STATS, 416d9718546SMugunthan V N }; 417d9718546SMugunthan V N 418d9718546SMugunthan V N #define CPSW_STAT(m) CPSW_STATS, \ 419d9718546SMugunthan V N sizeof(((struct cpsw_hw_stats *)0)->m), \ 420d9718546SMugunthan V N offsetof(struct cpsw_hw_stats, m) 421d9718546SMugunthan V N #define CPDMA_RX_STAT(m) CPDMA_RX_STATS, \ 422d9718546SMugunthan V N sizeof(((struct cpdma_chan_stats *)0)->m), \ 423d9718546SMugunthan V N offsetof(struct cpdma_chan_stats, m) 424d9718546SMugunthan V N #define CPDMA_TX_STAT(m) CPDMA_TX_STATS, \ 425d9718546SMugunthan V N sizeof(((struct cpdma_chan_stats *)0)->m), \ 426d9718546SMugunthan V N offsetof(struct cpdma_chan_stats, m) 427d9718546SMugunthan V N 428d9718546SMugunthan V N static const struct cpsw_stats cpsw_gstrings_stats[] = { 429d9718546SMugunthan V N { "Good Rx Frames", CPSW_STAT(rxgoodframes) }, 430d9718546SMugunthan V N { "Broadcast Rx Frames", CPSW_STAT(rxbroadcastframes) }, 431d9718546SMugunthan V N { "Multicast Rx Frames", CPSW_STAT(rxmulticastframes) }, 432d9718546SMugunthan V N { "Pause Rx Frames", CPSW_STAT(rxpauseframes) }, 433d9718546SMugunthan V N { "Rx CRC Errors", CPSW_STAT(rxcrcerrors) }, 434d9718546SMugunthan V N { "Rx Align/Code Errors", CPSW_STAT(rxaligncodeerrors) }, 435d9718546SMugunthan V N { "Oversize Rx Frames", CPSW_STAT(rxoversizedframes) }, 436d9718546SMugunthan V N { "Rx Jabbers", CPSW_STAT(rxjabberframes) }, 437d9718546SMugunthan V N { "Undersize (Short) Rx Frames", CPSW_STAT(rxundersizedframes) }, 438d9718546SMugunthan V N { "Rx Fragments", CPSW_STAT(rxfragments) }, 439d9718546SMugunthan V N { "Rx Octets", CPSW_STAT(rxoctets) }, 440d9718546SMugunthan V N { "Good Tx Frames", CPSW_STAT(txgoodframes) }, 441d9718546SMugunthan V N { "Broadcast Tx Frames", CPSW_STAT(txbroadcastframes) }, 442d9718546SMugunthan V N { "Multicast Tx Frames", CPSW_STAT(txmulticastframes) }, 443d9718546SMugunthan V N { "Pause Tx Frames", CPSW_STAT(txpauseframes) }, 444d9718546SMugunthan V N { "Deferred Tx Frames", CPSW_STAT(txdeferredframes) }, 445d9718546SMugunthan V N { "Collisions", CPSW_STAT(txcollisionframes) }, 446d9718546SMugunthan V N { "Single Collision Tx Frames", CPSW_STAT(txsinglecollframes) }, 447d9718546SMugunthan V N { "Multiple Collision Tx Frames", CPSW_STAT(txmultcollframes) }, 448d9718546SMugunthan V N { "Excessive Collisions", CPSW_STAT(txexcessivecollisions) }, 449d9718546SMugunthan V N { "Late Collisions", CPSW_STAT(txlatecollisions) }, 450d9718546SMugunthan V N { "Tx Underrun", CPSW_STAT(txunderrun) }, 451d9718546SMugunthan V N { "Carrier Sense Errors", CPSW_STAT(txcarriersenseerrors) }, 452d9718546SMugunthan V N { "Tx Octets", CPSW_STAT(txoctets) }, 453d9718546SMugunthan V N { "Rx + Tx 64 Octet Frames", CPSW_STAT(octetframes64) }, 454d9718546SMugunthan V N { "Rx + Tx 65-127 Octet Frames", CPSW_STAT(octetframes65t127) }, 455d9718546SMugunthan V N { "Rx + Tx 128-255 Octet Frames", CPSW_STAT(octetframes128t255) }, 456d9718546SMugunthan V N { "Rx + Tx 256-511 Octet Frames", CPSW_STAT(octetframes256t511) }, 457d9718546SMugunthan V N { "Rx + Tx 512-1023 Octet Frames", CPSW_STAT(octetframes512t1023) }, 458d9718546SMugunthan V N { "Rx + Tx 1024-Up Octet Frames", CPSW_STAT(octetframes1024tup) }, 459d9718546SMugunthan V N { "Net Octets", CPSW_STAT(netoctets) }, 460d9718546SMugunthan V N { "Rx Start of Frame Overruns", CPSW_STAT(rxsofoverruns) }, 461d9718546SMugunthan V N { "Rx Middle of Frame Overruns", CPSW_STAT(rxmofoverruns) }, 462d9718546SMugunthan V N { "Rx DMA Overruns", CPSW_STAT(rxdmaoverruns) }, 463d9718546SMugunthan V N }; 464d9718546SMugunthan V N 465e05107e6SIvan Khoronzhuk static const struct cpsw_stats cpsw_gstrings_ch_stats[] = { 466e05107e6SIvan Khoronzhuk { "head_enqueue", CPDMA_RX_STAT(head_enqueue) }, 467e05107e6SIvan Khoronzhuk { "tail_enqueue", CPDMA_RX_STAT(tail_enqueue) }, 468e05107e6SIvan Khoronzhuk { "pad_enqueue", CPDMA_RX_STAT(pad_enqueue) }, 469e05107e6SIvan Khoronzhuk { "misqueued", CPDMA_RX_STAT(misqueued) }, 470e05107e6SIvan Khoronzhuk { "desc_alloc_fail", CPDMA_RX_STAT(desc_alloc_fail) }, 471e05107e6SIvan Khoronzhuk { "pad_alloc_fail", CPDMA_RX_STAT(pad_alloc_fail) }, 472e05107e6SIvan Khoronzhuk { "runt_receive_buf", CPDMA_RX_STAT(runt_receive_buff) }, 473e05107e6SIvan Khoronzhuk { "runt_transmit_buf", CPDMA_RX_STAT(runt_transmit_buff) }, 474e05107e6SIvan Khoronzhuk { "empty_dequeue", CPDMA_RX_STAT(empty_dequeue) }, 475e05107e6SIvan Khoronzhuk { "busy_dequeue", CPDMA_RX_STAT(busy_dequeue) }, 476e05107e6SIvan Khoronzhuk { "good_dequeue", CPDMA_RX_STAT(good_dequeue) }, 477e05107e6SIvan Khoronzhuk { "requeue", CPDMA_RX_STAT(requeue) }, 478e05107e6SIvan Khoronzhuk { "teardown_dequeue", CPDMA_RX_STAT(teardown_dequeue) }, 479e05107e6SIvan Khoronzhuk }; 480e05107e6SIvan Khoronzhuk 481e05107e6SIvan Khoronzhuk #define CPSW_STATS_COMMON_LEN ARRAY_SIZE(cpsw_gstrings_stats) 482e05107e6SIvan Khoronzhuk #define CPSW_STATS_CH_LEN ARRAY_SIZE(cpsw_gstrings_ch_stats) 483d9718546SMugunthan V N 484649a1688SIvan Khoronzhuk #define ndev_to_cpsw(ndev) (((struct cpsw_priv *)netdev_priv(ndev))->cpsw) 485dbc4ec52SIvan Khoronzhuk #define napi_to_cpsw(napi) container_of(napi, struct cpsw_common, napi) 486df828598SMugunthan V N #define for_each_slave(priv, func, arg...) \ 487df828598SMugunthan V N do { \ 4886e6ceaedSSebastian Siewior struct cpsw_slave *slave; \ 489606f3993SIvan Khoronzhuk struct cpsw_common *cpsw = (priv)->cpsw; \ 4906e6ceaedSSebastian Siewior int n; \ 491606f3993SIvan Khoronzhuk if (cpsw->data.dual_emac) \ 492606f3993SIvan Khoronzhuk (func)((cpsw)->slaves + priv->emac_port, ##arg);\ 493d9ba8f9eSMugunthan V N else \ 494606f3993SIvan Khoronzhuk for (n = cpsw->data.slaves, \ 495606f3993SIvan Khoronzhuk slave = cpsw->slaves; \ 4966e6ceaedSSebastian Siewior n; n--) \ 4976e6ceaedSSebastian Siewior (func)(slave++, ##arg); \ 498df828598SMugunthan V N } while (0) 499d9ba8f9eSMugunthan V N 5002a05a622SIvan Khoronzhuk #define cpsw_dual_emac_src_port_detect(cpsw, status, ndev, skb) \ 501d9ba8f9eSMugunthan V N do { \ 502606f3993SIvan Khoronzhuk if (!cpsw->data.dual_emac) \ 503d9ba8f9eSMugunthan V N break; \ 504d9ba8f9eSMugunthan V N if (CPDMA_RX_SOURCE_PORT(status) == 1) { \ 505606f3993SIvan Khoronzhuk ndev = cpsw->slaves[0].ndev; \ 506d9ba8f9eSMugunthan V N skb->dev = ndev; \ 507d9ba8f9eSMugunthan V N } else if (CPDMA_RX_SOURCE_PORT(status) == 2) { \ 508606f3993SIvan Khoronzhuk ndev = cpsw->slaves[1].ndev; \ 509d9ba8f9eSMugunthan V N skb->dev = ndev; \ 510d9ba8f9eSMugunthan V N } \ 511d9ba8f9eSMugunthan V N } while (0) 512606f3993SIvan Khoronzhuk #define cpsw_add_mcast(cpsw, priv, addr) \ 513d9ba8f9eSMugunthan V N do { \ 514606f3993SIvan Khoronzhuk if (cpsw->data.dual_emac) { \ 515606f3993SIvan Khoronzhuk struct cpsw_slave *slave = cpsw->slaves + \ 516d9ba8f9eSMugunthan V N priv->emac_port; \ 5176f1f5836SIvan Khoronzhuk int slave_port = cpsw_get_slave_port( \ 518d9ba8f9eSMugunthan V N slave->slave_num); \ 5192a05a622SIvan Khoronzhuk cpsw_ale_add_mcast(cpsw->ale, addr, \ 52071a2cbb7SGrygorii Strashko 1 << slave_port | ALE_PORT_HOST, \ 521d9ba8f9eSMugunthan V N ALE_VLAN, slave->port_vlan, 0); \ 522d9ba8f9eSMugunthan V N } else { \ 5232a05a622SIvan Khoronzhuk cpsw_ale_add_mcast(cpsw->ale, addr, \ 52461f1cef9SGrygorii Strashko ALE_ALL_PORTS, \ 525d9ba8f9eSMugunthan V N 0, 0, 0); \ 526d9ba8f9eSMugunthan V N } \ 527d9ba8f9eSMugunthan V N } while (0) 528d9ba8f9eSMugunthan V N 5296f1f5836SIvan Khoronzhuk static inline int cpsw_get_slave_port(u32 slave_num) 530d9ba8f9eSMugunthan V N { 531d9ba8f9eSMugunthan V N return slave_num + 1; 532d9ba8f9eSMugunthan V N } 533df828598SMugunthan V N 5340cd8f9ccSMugunthan V N static void cpsw_set_promiscious(struct net_device *ndev, bool enable) 5350cd8f9ccSMugunthan V N { 5362a05a622SIvan Khoronzhuk struct cpsw_common *cpsw = ndev_to_cpsw(ndev); 5372a05a622SIvan Khoronzhuk struct cpsw_ale *ale = cpsw->ale; 5380cd8f9ccSMugunthan V N int i; 5390cd8f9ccSMugunthan V N 540606f3993SIvan Khoronzhuk if (cpsw->data.dual_emac) { 5410cd8f9ccSMugunthan V N bool flag = false; 5420cd8f9ccSMugunthan V N 5430cd8f9ccSMugunthan V N /* Enabling promiscuous mode for one interface will be 5440cd8f9ccSMugunthan V N * common for both the interface as the interface shares 5450cd8f9ccSMugunthan V N * the same hardware resource. 5460cd8f9ccSMugunthan V N */ 547606f3993SIvan Khoronzhuk for (i = 0; i < cpsw->data.slaves; i++) 548606f3993SIvan Khoronzhuk if (cpsw->slaves[i].ndev->flags & IFF_PROMISC) 5490cd8f9ccSMugunthan V N flag = true; 5500cd8f9ccSMugunthan V N 5510cd8f9ccSMugunthan V N if (!enable && flag) { 5520cd8f9ccSMugunthan V N enable = true; 5530cd8f9ccSMugunthan V N dev_err(&ndev->dev, "promiscuity not disabled as the other interface is still in promiscuity mode\n"); 5540cd8f9ccSMugunthan V N } 5550cd8f9ccSMugunthan V N 5560cd8f9ccSMugunthan V N if (enable) { 5570cd8f9ccSMugunthan V N /* Enable Bypass */ 5580cd8f9ccSMugunthan V N cpsw_ale_control_set(ale, 0, ALE_BYPASS, 1); 5590cd8f9ccSMugunthan V N 5600cd8f9ccSMugunthan V N dev_dbg(&ndev->dev, "promiscuity enabled\n"); 5610cd8f9ccSMugunthan V N } else { 5620cd8f9ccSMugunthan V N /* Disable Bypass */ 5630cd8f9ccSMugunthan V N cpsw_ale_control_set(ale, 0, ALE_BYPASS, 0); 5640cd8f9ccSMugunthan V N dev_dbg(&ndev->dev, "promiscuity disabled\n"); 5650cd8f9ccSMugunthan V N } 5660cd8f9ccSMugunthan V N } else { 5670cd8f9ccSMugunthan V N if (enable) { 5680cd8f9ccSMugunthan V N unsigned long timeout = jiffies + HZ; 5690cd8f9ccSMugunthan V N 5706f979eb3SLennart Sorensen /* Disable Learn for all ports (host is port 0 and slaves are port 1 and up */ 571606f3993SIvan Khoronzhuk for (i = 0; i <= cpsw->data.slaves; i++) { 5720cd8f9ccSMugunthan V N cpsw_ale_control_set(ale, i, 5730cd8f9ccSMugunthan V N ALE_PORT_NOLEARN, 1); 5740cd8f9ccSMugunthan V N cpsw_ale_control_set(ale, i, 5750cd8f9ccSMugunthan V N ALE_PORT_NO_SA_UPDATE, 1); 5760cd8f9ccSMugunthan V N } 5770cd8f9ccSMugunthan V N 5780cd8f9ccSMugunthan V N /* Clear All Untouched entries */ 5790cd8f9ccSMugunthan V N cpsw_ale_control_set(ale, 0, ALE_AGEOUT, 1); 5800cd8f9ccSMugunthan V N do { 5810cd8f9ccSMugunthan V N cpu_relax(); 5820cd8f9ccSMugunthan V N if (cpsw_ale_control_get(ale, 0, ALE_AGEOUT)) 5830cd8f9ccSMugunthan V N break; 5840cd8f9ccSMugunthan V N } while (time_after(timeout, jiffies)); 5850cd8f9ccSMugunthan V N cpsw_ale_control_set(ale, 0, ALE_AGEOUT, 1); 5860cd8f9ccSMugunthan V N 5870cd8f9ccSMugunthan V N /* Clear all mcast from ALE */ 58861f1cef9SGrygorii Strashko cpsw_ale_flush_multicast(ale, ALE_ALL_PORTS, -1); 5890cd8f9ccSMugunthan V N 5900cd8f9ccSMugunthan V N /* Flood All Unicast Packets to Host port */ 5910cd8f9ccSMugunthan V N cpsw_ale_control_set(ale, 0, ALE_P0_UNI_FLOOD, 1); 5920cd8f9ccSMugunthan V N dev_dbg(&ndev->dev, "promiscuity enabled\n"); 5930cd8f9ccSMugunthan V N } else { 5946f979eb3SLennart Sorensen /* Don't Flood All Unicast Packets to Host port */ 5950cd8f9ccSMugunthan V N cpsw_ale_control_set(ale, 0, ALE_P0_UNI_FLOOD, 0); 5960cd8f9ccSMugunthan V N 5976f979eb3SLennart Sorensen /* Enable Learn for all ports (host is port 0 and slaves are port 1 and up */ 598606f3993SIvan Khoronzhuk for (i = 0; i <= cpsw->data.slaves; i++) { 5990cd8f9ccSMugunthan V N cpsw_ale_control_set(ale, i, 6000cd8f9ccSMugunthan V N ALE_PORT_NOLEARN, 0); 6010cd8f9ccSMugunthan V N cpsw_ale_control_set(ale, i, 6020cd8f9ccSMugunthan V N ALE_PORT_NO_SA_UPDATE, 0); 6030cd8f9ccSMugunthan V N } 6040cd8f9ccSMugunthan V N dev_dbg(&ndev->dev, "promiscuity disabled\n"); 6050cd8f9ccSMugunthan V N } 6060cd8f9ccSMugunthan V N } 6070cd8f9ccSMugunthan V N } 6080cd8f9ccSMugunthan V N 6095c50a856SMugunthan V N static void cpsw_ndo_set_rx_mode(struct net_device *ndev) 6105c50a856SMugunthan V N { 6115c50a856SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 612606f3993SIvan Khoronzhuk struct cpsw_common *cpsw = priv->cpsw; 61325906052SMugunthan V N int vid; 61425906052SMugunthan V N 615606f3993SIvan Khoronzhuk if (cpsw->data.dual_emac) 616606f3993SIvan Khoronzhuk vid = cpsw->slaves[priv->emac_port].port_vlan; 61725906052SMugunthan V N else 618606f3993SIvan Khoronzhuk vid = cpsw->data.default_vlan; 6195c50a856SMugunthan V N 6205c50a856SMugunthan V N if (ndev->flags & IFF_PROMISC) { 6215c50a856SMugunthan V N /* Enable promiscuous mode */ 6220cd8f9ccSMugunthan V N cpsw_set_promiscious(ndev, true); 6232a05a622SIvan Khoronzhuk cpsw_ale_set_allmulti(cpsw->ale, IFF_ALLMULTI); 6245c50a856SMugunthan V N return; 6250cd8f9ccSMugunthan V N } else { 6260cd8f9ccSMugunthan V N /* Disable promiscuous mode */ 6270cd8f9ccSMugunthan V N cpsw_set_promiscious(ndev, false); 6285c50a856SMugunthan V N } 6295c50a856SMugunthan V N 6301e5c4bc4SLennart Sorensen /* Restore allmulti on vlans if necessary */ 6312a05a622SIvan Khoronzhuk cpsw_ale_set_allmulti(cpsw->ale, priv->ndev->flags & IFF_ALLMULTI); 6321e5c4bc4SLennart Sorensen 6335c50a856SMugunthan V N /* Clear all mcast from ALE */ 6342a05a622SIvan Khoronzhuk cpsw_ale_flush_multicast(cpsw->ale, ALE_ALL_PORTS, vid); 6355c50a856SMugunthan V N 6365c50a856SMugunthan V N if (!netdev_mc_empty(ndev)) { 6375c50a856SMugunthan V N struct netdev_hw_addr *ha; 6385c50a856SMugunthan V N 6395c50a856SMugunthan V N /* program multicast address list into ALE register */ 6405c50a856SMugunthan V N netdev_for_each_mc_addr(ha, ndev) { 641606f3993SIvan Khoronzhuk cpsw_add_mcast(cpsw, priv, (u8 *)ha->addr); 6425c50a856SMugunthan V N } 6435c50a856SMugunthan V N } 6445c50a856SMugunthan V N } 6455c50a856SMugunthan V N 6462c836bd9SIvan Khoronzhuk static void cpsw_intr_enable(struct cpsw_common *cpsw) 647df828598SMugunthan V N { 6485d8d0d4dSIvan Khoronzhuk __raw_writel(0xFF, &cpsw->wr_regs->tx_en); 6495d8d0d4dSIvan Khoronzhuk __raw_writel(0xFF, &cpsw->wr_regs->rx_en); 650df828598SMugunthan V N 6512c836bd9SIvan Khoronzhuk cpdma_ctlr_int_ctrl(cpsw->dma, true); 652df828598SMugunthan V N return; 653df828598SMugunthan V N } 654df828598SMugunthan V N 6552c836bd9SIvan Khoronzhuk static void cpsw_intr_disable(struct cpsw_common *cpsw) 656df828598SMugunthan V N { 6575d8d0d4dSIvan Khoronzhuk __raw_writel(0, &cpsw->wr_regs->tx_en); 6585d8d0d4dSIvan Khoronzhuk __raw_writel(0, &cpsw->wr_regs->rx_en); 659df828598SMugunthan V N 6602c836bd9SIvan Khoronzhuk cpdma_ctlr_int_ctrl(cpsw->dma, false); 661df828598SMugunthan V N return; 662df828598SMugunthan V N } 663df828598SMugunthan V N 6641a3b5056SOlof Johansson static void cpsw_tx_handler(void *token, int len, int status) 665df828598SMugunthan V N { 666e05107e6SIvan Khoronzhuk struct netdev_queue *txq; 667df828598SMugunthan V N struct sk_buff *skb = token; 668df828598SMugunthan V N struct net_device *ndev = skb->dev; 6692a05a622SIvan Khoronzhuk struct cpsw_common *cpsw = ndev_to_cpsw(ndev); 670df828598SMugunthan V N 671fae50823SMugunthan V N /* Check whether the queue is stopped due to stalled tx dma, if the 672fae50823SMugunthan V N * queue is stopped then start the queue as we have free desc for tx 673fae50823SMugunthan V N */ 674e05107e6SIvan Khoronzhuk txq = netdev_get_tx_queue(ndev, skb_get_queue_mapping(skb)); 675e05107e6SIvan Khoronzhuk if (unlikely(netif_tx_queue_stopped(txq))) 676e05107e6SIvan Khoronzhuk netif_tx_wake_queue(txq); 677e05107e6SIvan Khoronzhuk 6782a05a622SIvan Khoronzhuk cpts_tx_timestamp(cpsw->cpts, skb); 6798dc43ddcSTobias Klauser ndev->stats.tx_packets++; 6808dc43ddcSTobias Klauser ndev->stats.tx_bytes += len; 681df828598SMugunthan V N dev_kfree_skb_any(skb); 682df828598SMugunthan V N } 683df828598SMugunthan V N 6841a3b5056SOlof Johansson static void cpsw_rx_handler(void *token, int len, int status) 685df828598SMugunthan V N { 686e05107e6SIvan Khoronzhuk struct cpdma_chan *ch; 687df828598SMugunthan V N struct sk_buff *skb = token; 688b4727e69SSebastian Siewior struct sk_buff *new_skb; 689df828598SMugunthan V N struct net_device *ndev = skb->dev; 690df828598SMugunthan V N int ret = 0; 6912a05a622SIvan Khoronzhuk struct cpsw_common *cpsw = ndev_to_cpsw(ndev); 692df828598SMugunthan V N 6932a05a622SIvan Khoronzhuk cpsw_dual_emac_src_port_detect(cpsw, status, ndev, skb); 694d9ba8f9eSMugunthan V N 69516e5c57dSMugunthan V N if (unlikely(status < 0) || unlikely(!netif_running(ndev))) { 696a0e2c822SMugunthan V N bool ndev_status = false; 697606f3993SIvan Khoronzhuk struct cpsw_slave *slave = cpsw->slaves; 698a0e2c822SMugunthan V N int n; 699a0e2c822SMugunthan V N 700606f3993SIvan Khoronzhuk if (cpsw->data.dual_emac) { 701a0e2c822SMugunthan V N /* In dual emac mode check for all interfaces */ 702606f3993SIvan Khoronzhuk for (n = cpsw->data.slaves; n; n--, slave++) 703a0e2c822SMugunthan V N if (netif_running(slave->ndev)) 704a0e2c822SMugunthan V N ndev_status = true; 705a0e2c822SMugunthan V N } 706a0e2c822SMugunthan V N 707a0e2c822SMugunthan V N if (ndev_status && (status >= 0)) { 708a0e2c822SMugunthan V N /* The packet received is for the interface which 709a0e2c822SMugunthan V N * is already down and the other interface is up 710dbedd44eSJoe Perches * and running, instead of freeing which results 711a0e2c822SMugunthan V N * in reducing of the number of rx descriptor in 712a0e2c822SMugunthan V N * DMA engine, requeue skb back to cpdma. 713a0e2c822SMugunthan V N */ 714a0e2c822SMugunthan V N new_skb = skb; 715a0e2c822SMugunthan V N goto requeue; 716a0e2c822SMugunthan V N } 717a0e2c822SMugunthan V N 718b4727e69SSebastian Siewior /* the interface is going down, skbs are purged */ 719df828598SMugunthan V N dev_kfree_skb_any(skb); 720df828598SMugunthan V N return; 721df828598SMugunthan V N } 722b4727e69SSebastian Siewior 7232a05a622SIvan Khoronzhuk new_skb = netdev_alloc_skb_ip_align(ndev, cpsw->rx_packet_max); 724b4727e69SSebastian Siewior if (new_skb) { 725e05107e6SIvan Khoronzhuk skb_copy_queue_mapping(new_skb, skb); 726df828598SMugunthan V N skb_put(skb, len); 7272a05a622SIvan Khoronzhuk cpts_rx_timestamp(cpsw->cpts, skb); 728df828598SMugunthan V N skb->protocol = eth_type_trans(skb, ndev); 729df828598SMugunthan V N netif_receive_skb(skb); 7308dc43ddcSTobias Klauser ndev->stats.rx_bytes += len; 7318dc43ddcSTobias Klauser ndev->stats.rx_packets++; 732254a49d5SGrygorii Strashko kmemleak_not_leak(new_skb); 733b4727e69SSebastian Siewior } else { 7348dc43ddcSTobias Klauser ndev->stats.rx_dropped++; 735b4727e69SSebastian Siewior new_skb = skb; 736df828598SMugunthan V N } 737df828598SMugunthan V N 738a0e2c822SMugunthan V N requeue: 739ce52c744SIvan Khoronzhuk if (netif_dormant(ndev)) { 740ce52c744SIvan Khoronzhuk dev_kfree_skb_any(new_skb); 741ce52c744SIvan Khoronzhuk return; 742ce52c744SIvan Khoronzhuk } 743ce52c744SIvan Khoronzhuk 744e05107e6SIvan Khoronzhuk ch = cpsw->rxch[skb_get_queue_mapping(new_skb)]; 745e05107e6SIvan Khoronzhuk ret = cpdma_chan_submit(ch, new_skb, new_skb->data, 746b4727e69SSebastian Siewior skb_tailroom(new_skb), 0); 747b4727e69SSebastian Siewior if (WARN_ON(ret < 0)) 748b4727e69SSebastian Siewior dev_kfree_skb_any(new_skb); 749df828598SMugunthan V N } 750df828598SMugunthan V N 751c03abd84SFelipe Balbi static irqreturn_t cpsw_tx_interrupt(int irq, void *dev_id) 752df828598SMugunthan V N { 753dbc4ec52SIvan Khoronzhuk struct cpsw_common *cpsw = dev_id; 7547ce67a38SFelipe Balbi 7555d8d0d4dSIvan Khoronzhuk writel(0, &cpsw->wr_regs->tx_en); 7562c836bd9SIvan Khoronzhuk cpdma_ctlr_eoi(cpsw->dma, CPDMA_EOI_TX); 757c03abd84SFelipe Balbi 758e38b5a3dSIvan Khoronzhuk if (cpsw->quirk_irq) { 759e38b5a3dSIvan Khoronzhuk disable_irq_nosync(cpsw->irqs_table[1]); 760e38b5a3dSIvan Khoronzhuk cpsw->tx_irq_disabled = true; 7617da11600SMugunthan V N } 7627da11600SMugunthan V N 763dbc4ec52SIvan Khoronzhuk napi_schedule(&cpsw->napi_tx); 764c03abd84SFelipe Balbi return IRQ_HANDLED; 765c03abd84SFelipe Balbi } 766c03abd84SFelipe Balbi 767c03abd84SFelipe Balbi static irqreturn_t cpsw_rx_interrupt(int irq, void *dev_id) 768c03abd84SFelipe Balbi { 769dbc4ec52SIvan Khoronzhuk struct cpsw_common *cpsw = dev_id; 770c03abd84SFelipe Balbi 7712c836bd9SIvan Khoronzhuk cpdma_ctlr_eoi(cpsw->dma, CPDMA_EOI_RX); 7725d8d0d4dSIvan Khoronzhuk writel(0, &cpsw->wr_regs->rx_en); 773fd51cf19SSebastian Siewior 774e38b5a3dSIvan Khoronzhuk if (cpsw->quirk_irq) { 775e38b5a3dSIvan Khoronzhuk disable_irq_nosync(cpsw->irqs_table[0]); 776e38b5a3dSIvan Khoronzhuk cpsw->rx_irq_disabled = true; 7777da11600SMugunthan V N } 7787da11600SMugunthan V N 779dbc4ec52SIvan Khoronzhuk napi_schedule(&cpsw->napi_rx); 780df828598SMugunthan V N return IRQ_HANDLED; 781df828598SMugunthan V N } 782df828598SMugunthan V N 78332a7432cSMugunthan V N static int cpsw_tx_poll(struct napi_struct *napi_tx, int budget) 784df828598SMugunthan V N { 785e05107e6SIvan Khoronzhuk u32 ch_map; 786e05107e6SIvan Khoronzhuk int num_tx, ch; 787dbc4ec52SIvan Khoronzhuk struct cpsw_common *cpsw = napi_to_cpsw(napi_tx); 78832a7432cSMugunthan V N 789e05107e6SIvan Khoronzhuk /* process every unprocessed channel */ 790e05107e6SIvan Khoronzhuk ch_map = cpdma_ctrl_txchs_state(cpsw->dma); 791e05107e6SIvan Khoronzhuk for (ch = 0, num_tx = 0; num_tx < budget; ch_map >>= 1, ch++) { 792e05107e6SIvan Khoronzhuk if (!ch_map) { 793e05107e6SIvan Khoronzhuk ch_map = cpdma_ctrl_txchs_state(cpsw->dma); 794e05107e6SIvan Khoronzhuk if (!ch_map) 795e05107e6SIvan Khoronzhuk break; 796e05107e6SIvan Khoronzhuk 797e05107e6SIvan Khoronzhuk ch = 0; 798e05107e6SIvan Khoronzhuk } 799e05107e6SIvan Khoronzhuk 800e05107e6SIvan Khoronzhuk if (!(ch_map & 0x01)) 801e05107e6SIvan Khoronzhuk continue; 802e05107e6SIvan Khoronzhuk 803e05107e6SIvan Khoronzhuk num_tx += cpdma_chan_process(cpsw->txch[ch], budget - num_tx); 804e05107e6SIvan Khoronzhuk } 805e05107e6SIvan Khoronzhuk 80632a7432cSMugunthan V N if (num_tx < budget) { 80732a7432cSMugunthan V N napi_complete(napi_tx); 8085d8d0d4dSIvan Khoronzhuk writel(0xff, &cpsw->wr_regs->tx_en); 809e38b5a3dSIvan Khoronzhuk if (cpsw->quirk_irq && cpsw->tx_irq_disabled) { 810e38b5a3dSIvan Khoronzhuk cpsw->tx_irq_disabled = false; 811e38b5a3dSIvan Khoronzhuk enable_irq(cpsw->irqs_table[1]); 8127da11600SMugunthan V N } 81332a7432cSMugunthan V N } 81432a7432cSMugunthan V N 81532a7432cSMugunthan V N return num_tx; 81632a7432cSMugunthan V N } 81732a7432cSMugunthan V N 81832a7432cSMugunthan V N static int cpsw_rx_poll(struct napi_struct *napi_rx, int budget) 81932a7432cSMugunthan V N { 820e05107e6SIvan Khoronzhuk u32 ch_map; 821e05107e6SIvan Khoronzhuk int num_rx, ch; 822dbc4ec52SIvan Khoronzhuk struct cpsw_common *cpsw = napi_to_cpsw(napi_rx); 823510a1e72SMugunthan V N 824e05107e6SIvan Khoronzhuk /* process every unprocessed channel */ 825e05107e6SIvan Khoronzhuk ch_map = cpdma_ctrl_rxchs_state(cpsw->dma); 826e05107e6SIvan Khoronzhuk for (ch = 0, num_rx = 0; num_rx < budget; ch_map >>= 1, ch++) { 827e05107e6SIvan Khoronzhuk if (!ch_map) { 828e05107e6SIvan Khoronzhuk ch_map = cpdma_ctrl_rxchs_state(cpsw->dma); 829e05107e6SIvan Khoronzhuk if (!ch_map) 830e05107e6SIvan Khoronzhuk break; 831e05107e6SIvan Khoronzhuk 832e05107e6SIvan Khoronzhuk ch = 0; 833e05107e6SIvan Khoronzhuk } 834e05107e6SIvan Khoronzhuk 835e05107e6SIvan Khoronzhuk if (!(ch_map & 0x01)) 836e05107e6SIvan Khoronzhuk continue; 837e05107e6SIvan Khoronzhuk 838e05107e6SIvan Khoronzhuk num_rx += cpdma_chan_process(cpsw->rxch[ch], budget - num_rx); 839e05107e6SIvan Khoronzhuk } 840e05107e6SIvan Khoronzhuk 841510a1e72SMugunthan V N if (num_rx < budget) { 84232a7432cSMugunthan V N napi_complete(napi_rx); 8435d8d0d4dSIvan Khoronzhuk writel(0xff, &cpsw->wr_regs->rx_en); 844e38b5a3dSIvan Khoronzhuk if (cpsw->quirk_irq && cpsw->rx_irq_disabled) { 845e38b5a3dSIvan Khoronzhuk cpsw->rx_irq_disabled = false; 846e38b5a3dSIvan Khoronzhuk enable_irq(cpsw->irqs_table[0]); 8477da11600SMugunthan V N } 848510a1e72SMugunthan V N } 849df828598SMugunthan V N 850df828598SMugunthan V N return num_rx; 851df828598SMugunthan V N } 852df828598SMugunthan V N 853df828598SMugunthan V N static inline void soft_reset(const char *module, void __iomem *reg) 854df828598SMugunthan V N { 855df828598SMugunthan V N unsigned long timeout = jiffies + HZ; 856df828598SMugunthan V N 857df828598SMugunthan V N __raw_writel(1, reg); 858df828598SMugunthan V N do { 859df828598SMugunthan V N cpu_relax(); 860df828598SMugunthan V N } while ((__raw_readl(reg) & 1) && time_after(timeout, jiffies)); 861df828598SMugunthan V N 862df828598SMugunthan V N WARN(__raw_readl(reg) & 1, "failed to soft-reset %s\n", module); 863df828598SMugunthan V N } 864df828598SMugunthan V N 865df828598SMugunthan V N #define mac_hi(mac) (((mac)[0] << 0) | ((mac)[1] << 8) | \ 866df828598SMugunthan V N ((mac)[2] << 16) | ((mac)[3] << 24)) 867df828598SMugunthan V N #define mac_lo(mac) (((mac)[4] << 0) | ((mac)[5] << 8)) 868df828598SMugunthan V N 869df828598SMugunthan V N static void cpsw_set_slave_mac(struct cpsw_slave *slave, 870df828598SMugunthan V N struct cpsw_priv *priv) 871df828598SMugunthan V N { 8729750a3adSRichard Cochran slave_write(slave, mac_hi(priv->mac_addr), SA_HI); 8739750a3adSRichard Cochran slave_write(slave, mac_lo(priv->mac_addr), SA_LO); 874df828598SMugunthan V N } 875df828598SMugunthan V N 876df828598SMugunthan V N static void _cpsw_adjust_link(struct cpsw_slave *slave, 877df828598SMugunthan V N struct cpsw_priv *priv, bool *link) 878df828598SMugunthan V N { 879df828598SMugunthan V N struct phy_device *phy = slave->phy; 880df828598SMugunthan V N u32 mac_control = 0; 881df828598SMugunthan V N u32 slave_port; 882606f3993SIvan Khoronzhuk struct cpsw_common *cpsw = priv->cpsw; 883df828598SMugunthan V N 884df828598SMugunthan V N if (!phy) 885df828598SMugunthan V N return; 886df828598SMugunthan V N 8876f1f5836SIvan Khoronzhuk slave_port = cpsw_get_slave_port(slave->slave_num); 888df828598SMugunthan V N 889df828598SMugunthan V N if (phy->link) { 890606f3993SIvan Khoronzhuk mac_control = cpsw->data.mac_control; 891df828598SMugunthan V N 892df828598SMugunthan V N /* enable forwarding */ 8932a05a622SIvan Khoronzhuk cpsw_ale_control_set(cpsw->ale, slave_port, 894df828598SMugunthan V N ALE_PORT_STATE, ALE_PORT_STATE_FORWARD); 895df828598SMugunthan V N 896df828598SMugunthan V N if (phy->speed == 1000) 897df828598SMugunthan V N mac_control |= BIT(7); /* GIGABITEN */ 898df828598SMugunthan V N if (phy->duplex) 899df828598SMugunthan V N mac_control |= BIT(0); /* FULLDUPLEXEN */ 900342b7b74SDaniel Mack 901342b7b74SDaniel Mack /* set speed_in input in case RMII mode is used in 100Mbps */ 902342b7b74SDaniel Mack if (phy->speed == 100) 903342b7b74SDaniel Mack mac_control |= BIT(15); 904a81d8762SMugunthan V N else if (phy->speed == 10) 905a81d8762SMugunthan V N mac_control |= BIT(18); /* In Band mode */ 906342b7b74SDaniel Mack 9071923d6e4SMugunthan V N if (priv->rx_pause) 9081923d6e4SMugunthan V N mac_control |= BIT(3); 9091923d6e4SMugunthan V N 9101923d6e4SMugunthan V N if (priv->tx_pause) 9111923d6e4SMugunthan V N mac_control |= BIT(4); 9121923d6e4SMugunthan V N 913df828598SMugunthan V N *link = true; 914df828598SMugunthan V N } else { 915df828598SMugunthan V N mac_control = 0; 916df828598SMugunthan V N /* disable forwarding */ 9172a05a622SIvan Khoronzhuk cpsw_ale_control_set(cpsw->ale, slave_port, 918df828598SMugunthan V N ALE_PORT_STATE, ALE_PORT_STATE_DISABLE); 919df828598SMugunthan V N } 920df828598SMugunthan V N 921df828598SMugunthan V N if (mac_control != slave->mac_control) { 922df828598SMugunthan V N phy_print_status(phy); 923df828598SMugunthan V N __raw_writel(mac_control, &slave->sliver->mac_control); 924df828598SMugunthan V N } 925df828598SMugunthan V N 926df828598SMugunthan V N slave->mac_control = mac_control; 927df828598SMugunthan V N } 928df828598SMugunthan V N 929df828598SMugunthan V N static void cpsw_adjust_link(struct net_device *ndev) 930df828598SMugunthan V N { 931df828598SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 932df828598SMugunthan V N bool link = false; 933df828598SMugunthan V N 934df828598SMugunthan V N for_each_slave(priv, _cpsw_adjust_link, priv, &link); 935df828598SMugunthan V N 936df828598SMugunthan V N if (link) { 937df828598SMugunthan V N netif_carrier_on(ndev); 938df828598SMugunthan V N if (netif_running(ndev)) 939e05107e6SIvan Khoronzhuk netif_tx_wake_all_queues(ndev); 940df828598SMugunthan V N } else { 941df828598SMugunthan V N netif_carrier_off(ndev); 942e05107e6SIvan Khoronzhuk netif_tx_stop_all_queues(ndev); 943df828598SMugunthan V N } 944df828598SMugunthan V N } 945df828598SMugunthan V N 946ff5b8ef2SMugunthan V N static int cpsw_get_coalesce(struct net_device *ndev, 947ff5b8ef2SMugunthan V N struct ethtool_coalesce *coal) 948ff5b8ef2SMugunthan V N { 9492a05a622SIvan Khoronzhuk struct cpsw_common *cpsw = ndev_to_cpsw(ndev); 950ff5b8ef2SMugunthan V N 9512a05a622SIvan Khoronzhuk coal->rx_coalesce_usecs = cpsw->coal_intvl; 952ff5b8ef2SMugunthan V N return 0; 953ff5b8ef2SMugunthan V N } 954ff5b8ef2SMugunthan V N 955ff5b8ef2SMugunthan V N static int cpsw_set_coalesce(struct net_device *ndev, 956ff5b8ef2SMugunthan V N struct ethtool_coalesce *coal) 957ff5b8ef2SMugunthan V N { 958ff5b8ef2SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 959ff5b8ef2SMugunthan V N u32 int_ctrl; 960ff5b8ef2SMugunthan V N u32 num_interrupts = 0; 961ff5b8ef2SMugunthan V N u32 prescale = 0; 962ff5b8ef2SMugunthan V N u32 addnl_dvdr = 1; 963ff5b8ef2SMugunthan V N u32 coal_intvl = 0; 9645d8d0d4dSIvan Khoronzhuk struct cpsw_common *cpsw = priv->cpsw; 965ff5b8ef2SMugunthan V N 966ff5b8ef2SMugunthan V N coal_intvl = coal->rx_coalesce_usecs; 967ff5b8ef2SMugunthan V N 9685d8d0d4dSIvan Khoronzhuk int_ctrl = readl(&cpsw->wr_regs->int_control); 9692a05a622SIvan Khoronzhuk prescale = cpsw->bus_freq_mhz * 4; 970ff5b8ef2SMugunthan V N 971a84bc2a9SMugunthan V N if (!coal->rx_coalesce_usecs) { 972a84bc2a9SMugunthan V N int_ctrl &= ~(CPSW_INTPRESCALE_MASK | CPSW_INTPACEEN); 973a84bc2a9SMugunthan V N goto update_return; 974a84bc2a9SMugunthan V N } 975a84bc2a9SMugunthan V N 976ff5b8ef2SMugunthan V N if (coal_intvl < CPSW_CMINTMIN_INTVL) 977ff5b8ef2SMugunthan V N coal_intvl = CPSW_CMINTMIN_INTVL; 978ff5b8ef2SMugunthan V N 979ff5b8ef2SMugunthan V N if (coal_intvl > CPSW_CMINTMAX_INTVL) { 980ff5b8ef2SMugunthan V N /* Interrupt pacer works with 4us Pulse, we can 981ff5b8ef2SMugunthan V N * throttle further by dilating the 4us pulse. 982ff5b8ef2SMugunthan V N */ 983ff5b8ef2SMugunthan V N addnl_dvdr = CPSW_INTPRESCALE_MASK / prescale; 984ff5b8ef2SMugunthan V N 985ff5b8ef2SMugunthan V N if (addnl_dvdr > 1) { 986ff5b8ef2SMugunthan V N prescale *= addnl_dvdr; 987ff5b8ef2SMugunthan V N if (coal_intvl > (CPSW_CMINTMAX_INTVL * addnl_dvdr)) 988ff5b8ef2SMugunthan V N coal_intvl = (CPSW_CMINTMAX_INTVL 989ff5b8ef2SMugunthan V N * addnl_dvdr); 990ff5b8ef2SMugunthan V N } else { 991ff5b8ef2SMugunthan V N addnl_dvdr = 1; 992ff5b8ef2SMugunthan V N coal_intvl = CPSW_CMINTMAX_INTVL; 993ff5b8ef2SMugunthan V N } 994ff5b8ef2SMugunthan V N } 995ff5b8ef2SMugunthan V N 996ff5b8ef2SMugunthan V N num_interrupts = (1000 * addnl_dvdr) / coal_intvl; 9975d8d0d4dSIvan Khoronzhuk writel(num_interrupts, &cpsw->wr_regs->rx_imax); 9985d8d0d4dSIvan Khoronzhuk writel(num_interrupts, &cpsw->wr_regs->tx_imax); 999ff5b8ef2SMugunthan V N 1000ff5b8ef2SMugunthan V N int_ctrl |= CPSW_INTPACEEN; 1001ff5b8ef2SMugunthan V N int_ctrl &= (~CPSW_INTPRESCALE_MASK); 1002ff5b8ef2SMugunthan V N int_ctrl |= (prescale & CPSW_INTPRESCALE_MASK); 1003a84bc2a9SMugunthan V N 1004a84bc2a9SMugunthan V N update_return: 10055d8d0d4dSIvan Khoronzhuk writel(int_ctrl, &cpsw->wr_regs->int_control); 1006ff5b8ef2SMugunthan V N 1007ff5b8ef2SMugunthan V N cpsw_notice(priv, timer, "Set coalesce to %d usecs.\n", coal_intvl); 10082a05a622SIvan Khoronzhuk cpsw->coal_intvl = coal_intvl; 1009ff5b8ef2SMugunthan V N 1010ff5b8ef2SMugunthan V N return 0; 1011ff5b8ef2SMugunthan V N } 1012ff5b8ef2SMugunthan V N 1013d9718546SMugunthan V N static int cpsw_get_sset_count(struct net_device *ndev, int sset) 1014d9718546SMugunthan V N { 1015e05107e6SIvan Khoronzhuk struct cpsw_common *cpsw = ndev_to_cpsw(ndev); 1016e05107e6SIvan Khoronzhuk 1017d9718546SMugunthan V N switch (sset) { 1018d9718546SMugunthan V N case ETH_SS_STATS: 1019e05107e6SIvan Khoronzhuk return (CPSW_STATS_COMMON_LEN + 1020e05107e6SIvan Khoronzhuk (cpsw->rx_ch_num + cpsw->tx_ch_num) * 1021e05107e6SIvan Khoronzhuk CPSW_STATS_CH_LEN); 1022d9718546SMugunthan V N default: 1023d9718546SMugunthan V N return -EOPNOTSUPP; 1024d9718546SMugunthan V N } 1025d9718546SMugunthan V N } 1026d9718546SMugunthan V N 1027e05107e6SIvan Khoronzhuk static void cpsw_add_ch_strings(u8 **p, int ch_num, int rx_dir) 1028e05107e6SIvan Khoronzhuk { 1029e05107e6SIvan Khoronzhuk int ch_stats_len; 1030e05107e6SIvan Khoronzhuk int line; 1031e05107e6SIvan Khoronzhuk int i; 1032e05107e6SIvan Khoronzhuk 1033e05107e6SIvan Khoronzhuk ch_stats_len = CPSW_STATS_CH_LEN * ch_num; 1034e05107e6SIvan Khoronzhuk for (i = 0; i < ch_stats_len; i++) { 1035e05107e6SIvan Khoronzhuk line = i % CPSW_STATS_CH_LEN; 1036e05107e6SIvan Khoronzhuk snprintf(*p, ETH_GSTRING_LEN, 1037e05107e6SIvan Khoronzhuk "%s DMA chan %d: %s", rx_dir ? "Rx" : "Tx", 1038e05107e6SIvan Khoronzhuk i / CPSW_STATS_CH_LEN, 1039e05107e6SIvan Khoronzhuk cpsw_gstrings_ch_stats[line].stat_string); 1040e05107e6SIvan Khoronzhuk *p += ETH_GSTRING_LEN; 1041e05107e6SIvan Khoronzhuk } 1042e05107e6SIvan Khoronzhuk } 1043e05107e6SIvan Khoronzhuk 1044d9718546SMugunthan V N static void cpsw_get_strings(struct net_device *ndev, u32 stringset, u8 *data) 1045d9718546SMugunthan V N { 1046e05107e6SIvan Khoronzhuk struct cpsw_common *cpsw = ndev_to_cpsw(ndev); 1047d9718546SMugunthan V N u8 *p = data; 1048d9718546SMugunthan V N int i; 1049d9718546SMugunthan V N 1050d9718546SMugunthan V N switch (stringset) { 1051d9718546SMugunthan V N case ETH_SS_STATS: 1052e05107e6SIvan Khoronzhuk for (i = 0; i < CPSW_STATS_COMMON_LEN; i++) { 1053d9718546SMugunthan V N memcpy(p, cpsw_gstrings_stats[i].stat_string, 1054d9718546SMugunthan V N ETH_GSTRING_LEN); 1055d9718546SMugunthan V N p += ETH_GSTRING_LEN; 1056d9718546SMugunthan V N } 1057e05107e6SIvan Khoronzhuk 1058e05107e6SIvan Khoronzhuk cpsw_add_ch_strings(&p, cpsw->rx_ch_num, 1); 1059e05107e6SIvan Khoronzhuk cpsw_add_ch_strings(&p, cpsw->tx_ch_num, 0); 1060d9718546SMugunthan V N break; 1061d9718546SMugunthan V N } 1062d9718546SMugunthan V N } 1063d9718546SMugunthan V N 1064d9718546SMugunthan V N static void cpsw_get_ethtool_stats(struct net_device *ndev, 1065d9718546SMugunthan V N struct ethtool_stats *stats, u64 *data) 1066d9718546SMugunthan V N { 1067d9718546SMugunthan V N u8 *p; 10682c836bd9SIvan Khoronzhuk struct cpsw_common *cpsw = ndev_to_cpsw(ndev); 1069e05107e6SIvan Khoronzhuk struct cpdma_chan_stats ch_stats; 1070e05107e6SIvan Khoronzhuk int i, l, ch; 1071d9718546SMugunthan V N 1072d9718546SMugunthan V N /* Collect Davinci CPDMA stats for Rx and Tx Channel */ 1073e05107e6SIvan Khoronzhuk for (l = 0; l < CPSW_STATS_COMMON_LEN; l++) 1074e05107e6SIvan Khoronzhuk data[l] = readl(cpsw->hw_stats + 1075e05107e6SIvan Khoronzhuk cpsw_gstrings_stats[l].stat_offset); 1076d9718546SMugunthan V N 1077e05107e6SIvan Khoronzhuk for (ch = 0; ch < cpsw->rx_ch_num; ch++) { 1078e05107e6SIvan Khoronzhuk cpdma_chan_get_stats(cpsw->rxch[ch], &ch_stats); 1079e05107e6SIvan Khoronzhuk for (i = 0; i < CPSW_STATS_CH_LEN; i++, l++) { 1080e05107e6SIvan Khoronzhuk p = (u8 *)&ch_stats + 1081e05107e6SIvan Khoronzhuk cpsw_gstrings_ch_stats[i].stat_offset; 1082e05107e6SIvan Khoronzhuk data[l] = *(u32 *)p; 1083e05107e6SIvan Khoronzhuk } 1084e05107e6SIvan Khoronzhuk } 1085d9718546SMugunthan V N 1086e05107e6SIvan Khoronzhuk for (ch = 0; ch < cpsw->tx_ch_num; ch++) { 1087e05107e6SIvan Khoronzhuk cpdma_chan_get_stats(cpsw->txch[ch], &ch_stats); 1088e05107e6SIvan Khoronzhuk for (i = 0; i < CPSW_STATS_CH_LEN; i++, l++) { 1089e05107e6SIvan Khoronzhuk p = (u8 *)&ch_stats + 1090e05107e6SIvan Khoronzhuk cpsw_gstrings_ch_stats[i].stat_offset; 1091e05107e6SIvan Khoronzhuk data[l] = *(u32 *)p; 1092d9718546SMugunthan V N } 1093d9718546SMugunthan V N } 1094d9718546SMugunthan V N } 1095d9718546SMugunthan V N 1096606f3993SIvan Khoronzhuk static int cpsw_common_res_usage_state(struct cpsw_common *cpsw) 1097d9ba8f9eSMugunthan V N { 1098d9ba8f9eSMugunthan V N u32 i; 1099d9ba8f9eSMugunthan V N u32 usage_count = 0; 1100d9ba8f9eSMugunthan V N 1101606f3993SIvan Khoronzhuk if (!cpsw->data.dual_emac) 1102d9ba8f9eSMugunthan V N return 0; 1103d9ba8f9eSMugunthan V N 1104606f3993SIvan Khoronzhuk for (i = 0; i < cpsw->data.slaves; i++) 1105606f3993SIvan Khoronzhuk if (cpsw->slaves[i].open_stat) 1106d9ba8f9eSMugunthan V N usage_count++; 1107d9ba8f9eSMugunthan V N 1108d9ba8f9eSMugunthan V N return usage_count; 1109d9ba8f9eSMugunthan V N } 1110d9ba8f9eSMugunthan V N 111127e9e103SIvan Khoronzhuk static inline int cpsw_tx_packet_submit(struct cpsw_priv *priv, 1112e05107e6SIvan Khoronzhuk struct sk_buff *skb, 1113e05107e6SIvan Khoronzhuk struct cpdma_chan *txch) 1114d9ba8f9eSMugunthan V N { 11152c836bd9SIvan Khoronzhuk struct cpsw_common *cpsw = priv->cpsw; 11162c836bd9SIvan Khoronzhuk 1117e05107e6SIvan Khoronzhuk return cpdma_chan_submit(txch, skb, skb->data, skb->len, 1118606f3993SIvan Khoronzhuk priv->emac_port + cpsw->data.dual_emac); 1119d9ba8f9eSMugunthan V N } 1120d9ba8f9eSMugunthan V N 1121d9ba8f9eSMugunthan V N static inline void cpsw_add_dual_emac_def_ale_entries( 1122d9ba8f9eSMugunthan V N struct cpsw_priv *priv, struct cpsw_slave *slave, 1123d9ba8f9eSMugunthan V N u32 slave_port) 1124d9ba8f9eSMugunthan V N { 11252a05a622SIvan Khoronzhuk struct cpsw_common *cpsw = priv->cpsw; 112671a2cbb7SGrygorii Strashko u32 port_mask = 1 << slave_port | ALE_PORT_HOST; 1127d9ba8f9eSMugunthan V N 11282a05a622SIvan Khoronzhuk if (cpsw->version == CPSW_VERSION_1) 1129d9ba8f9eSMugunthan V N slave_write(slave, slave->port_vlan, CPSW1_PORT_VLAN); 1130d9ba8f9eSMugunthan V N else 1131d9ba8f9eSMugunthan V N slave_write(slave, slave->port_vlan, CPSW2_PORT_VLAN); 11322a05a622SIvan Khoronzhuk cpsw_ale_add_vlan(cpsw->ale, slave->port_vlan, port_mask, 1133d9ba8f9eSMugunthan V N port_mask, port_mask, 0); 11342a05a622SIvan Khoronzhuk cpsw_ale_add_mcast(cpsw->ale, priv->ndev->broadcast, 1135d9ba8f9eSMugunthan V N port_mask, ALE_VLAN, slave->port_vlan, 0); 11362a05a622SIvan Khoronzhuk cpsw_ale_add_ucast(cpsw->ale, priv->mac_addr, 11372a05a622SIvan Khoronzhuk HOST_PORT_NUM, ALE_VLAN | 11382a05a622SIvan Khoronzhuk ALE_SECURE, slave->port_vlan); 1139d9ba8f9eSMugunthan V N } 1140d9ba8f9eSMugunthan V N 11411e7a2e21SDaniel Mack static void soft_reset_slave(struct cpsw_slave *slave) 1142df828598SMugunthan V N { 1143df828598SMugunthan V N char name[32]; 11441e7a2e21SDaniel Mack 11451e7a2e21SDaniel Mack snprintf(name, sizeof(name), "slave-%d", slave->slave_num); 11461e7a2e21SDaniel Mack soft_reset(name, &slave->sliver->soft_reset); 11471e7a2e21SDaniel Mack } 11481e7a2e21SDaniel Mack 11491e7a2e21SDaniel Mack static void cpsw_slave_open(struct cpsw_slave *slave, struct cpsw_priv *priv) 11501e7a2e21SDaniel Mack { 1151df828598SMugunthan V N u32 slave_port; 1152649a1688SIvan Khoronzhuk struct cpsw_common *cpsw = priv->cpsw; 1153df828598SMugunthan V N 11541e7a2e21SDaniel Mack soft_reset_slave(slave); 1155df828598SMugunthan V N 1156df828598SMugunthan V N /* setup priority mapping */ 1157df828598SMugunthan V N __raw_writel(RX_PRIORITY_MAPPING, &slave->sliver->rx_pri_map); 11589750a3adSRichard Cochran 11592a05a622SIvan Khoronzhuk switch (cpsw->version) { 11609750a3adSRichard Cochran case CPSW_VERSION_1: 11619750a3adSRichard Cochran slave_write(slave, TX_PRIORITY_MAPPING, CPSW1_TX_PRI_MAP); 11629750a3adSRichard Cochran break; 11639750a3adSRichard Cochran case CPSW_VERSION_2: 1164c193f365SMugunthan V N case CPSW_VERSION_3: 1165926489beSMugunthan V N case CPSW_VERSION_4: 11669750a3adSRichard Cochran slave_write(slave, TX_PRIORITY_MAPPING, CPSW2_TX_PRI_MAP); 11679750a3adSRichard Cochran break; 11689750a3adSRichard Cochran } 1169df828598SMugunthan V N 1170df828598SMugunthan V N /* setup max packet size, and mac address */ 11712a05a622SIvan Khoronzhuk __raw_writel(cpsw->rx_packet_max, &slave->sliver->rx_maxlen); 1172df828598SMugunthan V N cpsw_set_slave_mac(slave, priv); 1173df828598SMugunthan V N 1174df828598SMugunthan V N slave->mac_control = 0; /* no link yet */ 1175df828598SMugunthan V N 11766f1f5836SIvan Khoronzhuk slave_port = cpsw_get_slave_port(slave->slave_num); 1177df828598SMugunthan V N 1178606f3993SIvan Khoronzhuk if (cpsw->data.dual_emac) 1179d9ba8f9eSMugunthan V N cpsw_add_dual_emac_def_ale_entries(priv, slave, slave_port); 1180d9ba8f9eSMugunthan V N else 11812a05a622SIvan Khoronzhuk cpsw_ale_add_mcast(cpsw->ale, priv->ndev->broadcast, 1182e11b220fSMugunthan V N 1 << slave_port, 0, 0, ALE_MCAST_FWD_2); 1183df828598SMugunthan V N 1184d733f754SDavid Rivshin if (slave->data->phy_node) { 1185552165bcSDavid Rivshin slave->phy = of_phy_connect(priv->ndev, slave->data->phy_node, 11869e42f715SHeiko Schocher &cpsw_adjust_link, 0, slave->data->phy_if); 1187d733f754SDavid Rivshin if (!slave->phy) { 1188d733f754SDavid Rivshin dev_err(priv->dev, "phy \"%s\" not found on slave %d\n", 1189d733f754SDavid Rivshin slave->data->phy_node->full_name, 1190d733f754SDavid Rivshin slave->slave_num); 1191d733f754SDavid Rivshin return; 1192d733f754SDavid Rivshin } 1193d733f754SDavid Rivshin } else { 1194df828598SMugunthan V N slave->phy = phy_connect(priv->ndev, slave->data->phy_id, 1195f9a8f83bSFlorian Fainelli &cpsw_adjust_link, slave->data->phy_if); 1196df828598SMugunthan V N if (IS_ERR(slave->phy)) { 1197d733f754SDavid Rivshin dev_err(priv->dev, 1198d733f754SDavid Rivshin "phy \"%s\" not found on slave %d, err %ld\n", 1199d733f754SDavid Rivshin slave->data->phy_id, slave->slave_num, 1200d733f754SDavid Rivshin PTR_ERR(slave->phy)); 1201df828598SMugunthan V N slave->phy = NULL; 1202d733f754SDavid Rivshin return; 1203d733f754SDavid Rivshin } 1204d733f754SDavid Rivshin } 1205d733f754SDavid Rivshin 12062220943aSAndrew Lunn phy_attached_info(slave->phy); 12072220943aSAndrew Lunn 1208df828598SMugunthan V N phy_start(slave->phy); 1209388367a5SMugunthan V N 1210388367a5SMugunthan V N /* Configure GMII_SEL register */ 121156e31bd8SIvan Khoronzhuk cpsw_phy_sel(cpsw->dev, slave->phy->interface, slave->slave_num); 1212df828598SMugunthan V N } 1213df828598SMugunthan V N 12143b72c2feSMugunthan V N static inline void cpsw_add_default_vlan(struct cpsw_priv *priv) 12153b72c2feSMugunthan V N { 1216606f3993SIvan Khoronzhuk struct cpsw_common *cpsw = priv->cpsw; 1217606f3993SIvan Khoronzhuk const int vlan = cpsw->data.default_vlan; 12183b72c2feSMugunthan V N u32 reg; 12193b72c2feSMugunthan V N int i; 12201e5c4bc4SLennart Sorensen int unreg_mcast_mask; 12213b72c2feSMugunthan V N 12222a05a622SIvan Khoronzhuk reg = (cpsw->version == CPSW_VERSION_1) ? CPSW1_PORT_VLAN : 12233b72c2feSMugunthan V N CPSW2_PORT_VLAN; 12243b72c2feSMugunthan V N 12255d8d0d4dSIvan Khoronzhuk writel(vlan, &cpsw->host_port_regs->port_vlan); 12263b72c2feSMugunthan V N 1227606f3993SIvan Khoronzhuk for (i = 0; i < cpsw->data.slaves; i++) 1228606f3993SIvan Khoronzhuk slave_write(cpsw->slaves + i, vlan, reg); 12293b72c2feSMugunthan V N 12301e5c4bc4SLennart Sorensen if (priv->ndev->flags & IFF_ALLMULTI) 12311e5c4bc4SLennart Sorensen unreg_mcast_mask = ALE_ALL_PORTS; 12321e5c4bc4SLennart Sorensen else 12331e5c4bc4SLennart Sorensen unreg_mcast_mask = ALE_PORT_1 | ALE_PORT_2; 12341e5c4bc4SLennart Sorensen 12352a05a622SIvan Khoronzhuk cpsw_ale_add_vlan(cpsw->ale, vlan, ALE_ALL_PORTS, 123661f1cef9SGrygorii Strashko ALE_ALL_PORTS, ALE_ALL_PORTS, 123761f1cef9SGrygorii Strashko unreg_mcast_mask); 12383b72c2feSMugunthan V N } 12393b72c2feSMugunthan V N 1240df828598SMugunthan V N static void cpsw_init_host_port(struct cpsw_priv *priv) 1241df828598SMugunthan V N { 1242d9ba8f9eSMugunthan V N u32 fifo_mode; 12435d8d0d4dSIvan Khoronzhuk u32 control_reg; 12445d8d0d4dSIvan Khoronzhuk struct cpsw_common *cpsw = priv->cpsw; 12453b72c2feSMugunthan V N 1246df828598SMugunthan V N /* soft reset the controller and initialize ale */ 12475d8d0d4dSIvan Khoronzhuk soft_reset("cpsw", &cpsw->regs->soft_reset); 12482a05a622SIvan Khoronzhuk cpsw_ale_start(cpsw->ale); 1249df828598SMugunthan V N 1250df828598SMugunthan V N /* switch to vlan unaware mode */ 12512a05a622SIvan Khoronzhuk cpsw_ale_control_set(cpsw->ale, HOST_PORT_NUM, ALE_VLAN_AWARE, 12523b72c2feSMugunthan V N CPSW_ALE_VLAN_AWARE); 12535d8d0d4dSIvan Khoronzhuk control_reg = readl(&cpsw->regs->control); 12543b72c2feSMugunthan V N control_reg |= CPSW_VLAN_AWARE; 12555d8d0d4dSIvan Khoronzhuk writel(control_reg, &cpsw->regs->control); 1256606f3993SIvan Khoronzhuk fifo_mode = (cpsw->data.dual_emac) ? CPSW_FIFO_DUAL_MAC_MODE : 1257d9ba8f9eSMugunthan V N CPSW_FIFO_NORMAL_MODE; 12585d8d0d4dSIvan Khoronzhuk writel(fifo_mode, &cpsw->host_port_regs->tx_in_ctl); 1259df828598SMugunthan V N 1260df828598SMugunthan V N /* setup host port priority mapping */ 1261df828598SMugunthan V N __raw_writel(CPDMA_TX_PRIORITY_MAP, 12625d8d0d4dSIvan Khoronzhuk &cpsw->host_port_regs->cpdma_tx_pri_map); 12635d8d0d4dSIvan Khoronzhuk __raw_writel(0, &cpsw->host_port_regs->cpdma_rx_chan_map); 1264df828598SMugunthan V N 12652a05a622SIvan Khoronzhuk cpsw_ale_control_set(cpsw->ale, HOST_PORT_NUM, 1266df828598SMugunthan V N ALE_PORT_STATE, ALE_PORT_STATE_FORWARD); 1267df828598SMugunthan V N 1268606f3993SIvan Khoronzhuk if (!cpsw->data.dual_emac) { 12692a05a622SIvan Khoronzhuk cpsw_ale_add_ucast(cpsw->ale, priv->mac_addr, HOST_PORT_NUM, 1270d9ba8f9eSMugunthan V N 0, 0); 12712a05a622SIvan Khoronzhuk cpsw_ale_add_mcast(cpsw->ale, priv->ndev->broadcast, 127271a2cbb7SGrygorii Strashko ALE_PORT_HOST, 0, 0, ALE_MCAST_FWD_2); 1273df828598SMugunthan V N } 1274d9ba8f9eSMugunthan V N } 1275df828598SMugunthan V N 12763802dce1SIvan Khoronzhuk static int cpsw_fill_rx_channels(struct cpsw_priv *priv) 12773802dce1SIvan Khoronzhuk { 12783802dce1SIvan Khoronzhuk struct cpsw_common *cpsw = priv->cpsw; 12793802dce1SIvan Khoronzhuk struct sk_buff *skb; 12803802dce1SIvan Khoronzhuk int ch_buf_num; 1281e05107e6SIvan Khoronzhuk int ch, i, ret; 12823802dce1SIvan Khoronzhuk 1283e05107e6SIvan Khoronzhuk for (ch = 0; ch < cpsw->rx_ch_num; ch++) { 1284e05107e6SIvan Khoronzhuk ch_buf_num = cpdma_chan_get_rx_buf_num(cpsw->rxch[ch]); 12853802dce1SIvan Khoronzhuk for (i = 0; i < ch_buf_num; i++) { 12863802dce1SIvan Khoronzhuk skb = __netdev_alloc_skb_ip_align(priv->ndev, 12873802dce1SIvan Khoronzhuk cpsw->rx_packet_max, 12883802dce1SIvan Khoronzhuk GFP_KERNEL); 12893802dce1SIvan Khoronzhuk if (!skb) { 12903802dce1SIvan Khoronzhuk cpsw_err(priv, ifup, "cannot allocate skb\n"); 12913802dce1SIvan Khoronzhuk return -ENOMEM; 12923802dce1SIvan Khoronzhuk } 12933802dce1SIvan Khoronzhuk 1294e05107e6SIvan Khoronzhuk skb_set_queue_mapping(skb, ch); 1295e05107e6SIvan Khoronzhuk ret = cpdma_chan_submit(cpsw->rxch[ch], skb, skb->data, 12963802dce1SIvan Khoronzhuk skb_tailroom(skb), 0); 12973802dce1SIvan Khoronzhuk if (ret < 0) { 12983802dce1SIvan Khoronzhuk cpsw_err(priv, ifup, 1299e05107e6SIvan Khoronzhuk "cannot submit skb to channel %d rx, error %d\n", 1300e05107e6SIvan Khoronzhuk ch, ret); 13013802dce1SIvan Khoronzhuk kfree_skb(skb); 13023802dce1SIvan Khoronzhuk return ret; 13033802dce1SIvan Khoronzhuk } 13043802dce1SIvan Khoronzhuk kmemleak_not_leak(skb); 13053802dce1SIvan Khoronzhuk } 13063802dce1SIvan Khoronzhuk 1307e05107e6SIvan Khoronzhuk cpsw_info(priv, ifup, "ch %d rx, submitted %d descriptors\n", 1308e05107e6SIvan Khoronzhuk ch, ch_buf_num); 1309e05107e6SIvan Khoronzhuk } 13103802dce1SIvan Khoronzhuk 1311e05107e6SIvan Khoronzhuk return 0; 13123802dce1SIvan Khoronzhuk } 13133802dce1SIvan Khoronzhuk 13142a05a622SIvan Khoronzhuk static void cpsw_slave_stop(struct cpsw_slave *slave, struct cpsw_common *cpsw) 1315aacebbf8SSebastian Siewior { 13163995d265SSchuyler Patton u32 slave_port; 13173995d265SSchuyler Patton 13186f1f5836SIvan Khoronzhuk slave_port = cpsw_get_slave_port(slave->slave_num); 13193995d265SSchuyler Patton 1320aacebbf8SSebastian Siewior if (!slave->phy) 1321aacebbf8SSebastian Siewior return; 1322aacebbf8SSebastian Siewior phy_stop(slave->phy); 1323aacebbf8SSebastian Siewior phy_disconnect(slave->phy); 1324aacebbf8SSebastian Siewior slave->phy = NULL; 13252a05a622SIvan Khoronzhuk cpsw_ale_control_set(cpsw->ale, slave_port, 13263995d265SSchuyler Patton ALE_PORT_STATE, ALE_PORT_STATE_DISABLE); 13271f95ba00SGrygorii Strashko soft_reset_slave(slave); 1328aacebbf8SSebastian Siewior } 1329aacebbf8SSebastian Siewior 1330df828598SMugunthan V N static int cpsw_ndo_open(struct net_device *ndev) 1331df828598SMugunthan V N { 1332df828598SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 1333649a1688SIvan Khoronzhuk struct cpsw_common *cpsw = priv->cpsw; 13343802dce1SIvan Khoronzhuk int ret; 1335df828598SMugunthan V N u32 reg; 1336df828598SMugunthan V N 133756e31bd8SIvan Khoronzhuk ret = pm_runtime_get_sync(cpsw->dev); 1338108a6537SGrygorii Strashko if (ret < 0) { 133956e31bd8SIvan Khoronzhuk pm_runtime_put_noidle(cpsw->dev); 1340108a6537SGrygorii Strashko return ret; 1341108a6537SGrygorii Strashko } 13423fa88c51SGrygorii Strashko 1343606f3993SIvan Khoronzhuk if (!cpsw_common_res_usage_state(cpsw)) 13442c836bd9SIvan Khoronzhuk cpsw_intr_disable(cpsw); 1345df828598SMugunthan V N netif_carrier_off(ndev); 1346df828598SMugunthan V N 1347e05107e6SIvan Khoronzhuk /* Notify the stack of the actual queue counts. */ 1348e05107e6SIvan Khoronzhuk ret = netif_set_real_num_tx_queues(ndev, cpsw->tx_ch_num); 1349e05107e6SIvan Khoronzhuk if (ret) { 1350e05107e6SIvan Khoronzhuk dev_err(priv->dev, "cannot set real number of tx queues\n"); 1351e05107e6SIvan Khoronzhuk goto err_cleanup; 1352e05107e6SIvan Khoronzhuk } 1353e05107e6SIvan Khoronzhuk 1354e05107e6SIvan Khoronzhuk ret = netif_set_real_num_rx_queues(ndev, cpsw->rx_ch_num); 1355e05107e6SIvan Khoronzhuk if (ret) { 1356e05107e6SIvan Khoronzhuk dev_err(priv->dev, "cannot set real number of rx queues\n"); 1357e05107e6SIvan Khoronzhuk goto err_cleanup; 1358e05107e6SIvan Khoronzhuk } 1359e05107e6SIvan Khoronzhuk 13602a05a622SIvan Khoronzhuk reg = cpsw->version; 1361df828598SMugunthan V N 1362df828598SMugunthan V N dev_info(priv->dev, "initializing cpsw version %d.%d (%d)\n", 1363df828598SMugunthan V N CPSW_MAJOR_VERSION(reg), CPSW_MINOR_VERSION(reg), 1364df828598SMugunthan V N CPSW_RTL_VERSION(reg)); 1365df828598SMugunthan V N 1366df828598SMugunthan V N /* initialize host and slave ports */ 1367606f3993SIvan Khoronzhuk if (!cpsw_common_res_usage_state(cpsw)) 1368df828598SMugunthan V N cpsw_init_host_port(priv); 1369df828598SMugunthan V N for_each_slave(priv, cpsw_slave_open, priv); 1370df828598SMugunthan V N 13713b72c2feSMugunthan V N /* Add default VLAN */ 1372606f3993SIvan Khoronzhuk if (!cpsw->data.dual_emac) 13733b72c2feSMugunthan V N cpsw_add_default_vlan(priv); 1374e6afea0bSMugunthan V N else 13752a05a622SIvan Khoronzhuk cpsw_ale_add_vlan(cpsw->ale, cpsw->data.default_vlan, 137661f1cef9SGrygorii Strashko ALE_ALL_PORTS, ALE_ALL_PORTS, 0, 0); 13773b72c2feSMugunthan V N 1378606f3993SIvan Khoronzhuk if (!cpsw_common_res_usage_state(cpsw)) { 1379df828598SMugunthan V N /* setup tx dma to fixed prio and zero offset */ 13802c836bd9SIvan Khoronzhuk cpdma_control_set(cpsw->dma, CPDMA_TX_PRIO_FIXED, 1); 13812c836bd9SIvan Khoronzhuk cpdma_control_set(cpsw->dma, CPDMA_RX_BUFFER_OFFSET, 0); 1382df828598SMugunthan V N 1383d9ba8f9eSMugunthan V N /* disable priority elevation */ 13845d8d0d4dSIvan Khoronzhuk __raw_writel(0, &cpsw->regs->ptype); 1385df828598SMugunthan V N 1386d9ba8f9eSMugunthan V N /* enable statistics collection only on all ports */ 13875d8d0d4dSIvan Khoronzhuk __raw_writel(0x7, &cpsw->regs->stat_port_en); 1388df828598SMugunthan V N 13891923d6e4SMugunthan V N /* Enable internal fifo flow control */ 13905d8d0d4dSIvan Khoronzhuk writel(0x7, &cpsw->regs->flow_control); 13911923d6e4SMugunthan V N 1392dbc4ec52SIvan Khoronzhuk napi_enable(&cpsw->napi_rx); 1393dbc4ec52SIvan Khoronzhuk napi_enable(&cpsw->napi_tx); 1394d354eb85SMugunthan V N 1395e38b5a3dSIvan Khoronzhuk if (cpsw->tx_irq_disabled) { 1396e38b5a3dSIvan Khoronzhuk cpsw->tx_irq_disabled = false; 1397e38b5a3dSIvan Khoronzhuk enable_irq(cpsw->irqs_table[1]); 13987da11600SMugunthan V N } 13997da11600SMugunthan V N 1400e38b5a3dSIvan Khoronzhuk if (cpsw->rx_irq_disabled) { 1401e38b5a3dSIvan Khoronzhuk cpsw->rx_irq_disabled = false; 1402e38b5a3dSIvan Khoronzhuk enable_irq(cpsw->irqs_table[0]); 14037da11600SMugunthan V N } 14047da11600SMugunthan V N 14053802dce1SIvan Khoronzhuk ret = cpsw_fill_rx_channels(priv); 14063802dce1SIvan Khoronzhuk if (ret < 0) 1407aacebbf8SSebastian Siewior goto err_cleanup; 1408f280e89aSMugunthan V N 14092a05a622SIvan Khoronzhuk if (cpts_register(cpsw->dev, cpsw->cpts, 1410606f3993SIvan Khoronzhuk cpsw->data.cpts_clock_mult, 1411606f3993SIvan Khoronzhuk cpsw->data.cpts_clock_shift)) 1412f280e89aSMugunthan V N dev_err(priv->dev, "error registering cpts device\n"); 1413f280e89aSMugunthan V N 1414d9ba8f9eSMugunthan V N } 1415df828598SMugunthan V N 1416ff5b8ef2SMugunthan V N /* Enable Interrupt pacing if configured */ 14172a05a622SIvan Khoronzhuk if (cpsw->coal_intvl != 0) { 1418ff5b8ef2SMugunthan V N struct ethtool_coalesce coal; 1419ff5b8ef2SMugunthan V N 14202a05a622SIvan Khoronzhuk coal.rx_coalesce_usecs = cpsw->coal_intvl; 1421ff5b8ef2SMugunthan V N cpsw_set_coalesce(ndev, &coal); 1422ff5b8ef2SMugunthan V N } 1423ff5b8ef2SMugunthan V N 14242c836bd9SIvan Khoronzhuk cpdma_ctlr_start(cpsw->dma); 14252c836bd9SIvan Khoronzhuk cpsw_intr_enable(cpsw); 1426f63a975eSMugunthan V N 1427606f3993SIvan Khoronzhuk if (cpsw->data.dual_emac) 1428606f3993SIvan Khoronzhuk cpsw->slaves[priv->emac_port].open_stat = true; 1429e05107e6SIvan Khoronzhuk 1430e05107e6SIvan Khoronzhuk netif_tx_start_all_queues(ndev); 1431e05107e6SIvan Khoronzhuk 1432df828598SMugunthan V N return 0; 1433df828598SMugunthan V N 1434aacebbf8SSebastian Siewior err_cleanup: 14352c836bd9SIvan Khoronzhuk cpdma_ctlr_stop(cpsw->dma); 14362a05a622SIvan Khoronzhuk for_each_slave(priv, cpsw_slave_stop, cpsw); 143756e31bd8SIvan Khoronzhuk pm_runtime_put_sync(cpsw->dev); 1438aacebbf8SSebastian Siewior netif_carrier_off(priv->ndev); 1439aacebbf8SSebastian Siewior return ret; 1440df828598SMugunthan V N } 1441df828598SMugunthan V N 1442df828598SMugunthan V N static int cpsw_ndo_stop(struct net_device *ndev) 1443df828598SMugunthan V N { 1444df828598SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 1445649a1688SIvan Khoronzhuk struct cpsw_common *cpsw = priv->cpsw; 1446df828598SMugunthan V N 1447df828598SMugunthan V N cpsw_info(priv, ifdown, "shutting down cpsw device\n"); 1448e05107e6SIvan Khoronzhuk netif_tx_stop_all_queues(priv->ndev); 1449df828598SMugunthan V N netif_carrier_off(priv->ndev); 1450d9ba8f9eSMugunthan V N 1451606f3993SIvan Khoronzhuk if (cpsw_common_res_usage_state(cpsw) <= 1) { 1452dbc4ec52SIvan Khoronzhuk napi_disable(&cpsw->napi_rx); 1453dbc4ec52SIvan Khoronzhuk napi_disable(&cpsw->napi_tx); 14542a05a622SIvan Khoronzhuk cpts_unregister(cpsw->cpts); 14552c836bd9SIvan Khoronzhuk cpsw_intr_disable(cpsw); 14562c836bd9SIvan Khoronzhuk cpdma_ctlr_stop(cpsw->dma); 14572a05a622SIvan Khoronzhuk cpsw_ale_stop(cpsw->ale); 1458d9ba8f9eSMugunthan V N } 14592a05a622SIvan Khoronzhuk for_each_slave(priv, cpsw_slave_stop, cpsw); 146056e31bd8SIvan Khoronzhuk pm_runtime_put_sync(cpsw->dev); 1461606f3993SIvan Khoronzhuk if (cpsw->data.dual_emac) 1462606f3993SIvan Khoronzhuk cpsw->slaves[priv->emac_port].open_stat = false; 1463df828598SMugunthan V N return 0; 1464df828598SMugunthan V N } 1465df828598SMugunthan V N 1466df828598SMugunthan V N static netdev_tx_t cpsw_ndo_start_xmit(struct sk_buff *skb, 1467df828598SMugunthan V N struct net_device *ndev) 1468df828598SMugunthan V N { 1469df828598SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 14702c836bd9SIvan Khoronzhuk struct cpsw_common *cpsw = priv->cpsw; 1471e05107e6SIvan Khoronzhuk struct netdev_queue *txq; 1472e05107e6SIvan Khoronzhuk struct cpdma_chan *txch; 1473e05107e6SIvan Khoronzhuk int ret, q_idx; 1474df828598SMugunthan V N 1475860e9538SFlorian Westphal netif_trans_update(ndev); 1476df828598SMugunthan V N 1477df828598SMugunthan V N if (skb_padto(skb, CPSW_MIN_PACKET_SIZE)) { 1478df828598SMugunthan V N cpsw_err(priv, tx_err, "packet pad failed\n"); 14798dc43ddcSTobias Klauser ndev->stats.tx_dropped++; 1480df828598SMugunthan V N return NETDEV_TX_OK; 1481df828598SMugunthan V N } 1482df828598SMugunthan V N 14839232b16dSMugunthan V N if (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP && 14842a05a622SIvan Khoronzhuk cpsw->cpts->tx_enable) 14852e5b38abSRichard Cochran skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 14862e5b38abSRichard Cochran 14872e5b38abSRichard Cochran skb_tx_timestamp(skb); 14882e5b38abSRichard Cochran 1489e05107e6SIvan Khoronzhuk q_idx = skb_get_queue_mapping(skb); 1490e05107e6SIvan Khoronzhuk if (q_idx >= cpsw->tx_ch_num) 1491e05107e6SIvan Khoronzhuk q_idx = q_idx % cpsw->tx_ch_num; 1492e05107e6SIvan Khoronzhuk 1493e05107e6SIvan Khoronzhuk txch = cpsw->txch[q_idx]; 1494e05107e6SIvan Khoronzhuk ret = cpsw_tx_packet_submit(priv, skb, txch); 1495df828598SMugunthan V N if (unlikely(ret != 0)) { 1496df828598SMugunthan V N cpsw_err(priv, tx_err, "desc submit failed\n"); 1497df828598SMugunthan V N goto fail; 1498df828598SMugunthan V N } 1499df828598SMugunthan V N 1500fae50823SMugunthan V N /* If there is no more tx desc left free then we need to 1501fae50823SMugunthan V N * tell the kernel to stop sending us tx frames. 1502fae50823SMugunthan V N */ 1503e05107e6SIvan Khoronzhuk if (unlikely(!cpdma_check_free_tx_desc(txch))) { 1504e05107e6SIvan Khoronzhuk txq = netdev_get_tx_queue(ndev, q_idx); 1505e05107e6SIvan Khoronzhuk netif_tx_stop_queue(txq); 1506e05107e6SIvan Khoronzhuk } 1507fae50823SMugunthan V N 1508df828598SMugunthan V N return NETDEV_TX_OK; 1509df828598SMugunthan V N fail: 15108dc43ddcSTobias Klauser ndev->stats.tx_dropped++; 1511e05107e6SIvan Khoronzhuk txq = netdev_get_tx_queue(ndev, skb_get_queue_mapping(skb)); 1512e05107e6SIvan Khoronzhuk netif_tx_stop_queue(txq); 1513df828598SMugunthan V N return NETDEV_TX_BUSY; 1514df828598SMugunthan V N } 1515df828598SMugunthan V N 15162e5b38abSRichard Cochran #ifdef CONFIG_TI_CPTS 15172e5b38abSRichard Cochran 15182a05a622SIvan Khoronzhuk static void cpsw_hwtstamp_v1(struct cpsw_common *cpsw) 15192e5b38abSRichard Cochran { 1520606f3993SIvan Khoronzhuk struct cpsw_slave *slave = &cpsw->slaves[cpsw->data.active_slave]; 15212e5b38abSRichard Cochran u32 ts_en, seq_id; 15222e5b38abSRichard Cochran 15232a05a622SIvan Khoronzhuk if (!cpsw->cpts->tx_enable && !cpsw->cpts->rx_enable) { 15242e5b38abSRichard Cochran slave_write(slave, 0, CPSW1_TS_CTL); 15252e5b38abSRichard Cochran return; 15262e5b38abSRichard Cochran } 15272e5b38abSRichard Cochran 15282e5b38abSRichard Cochran seq_id = (30 << CPSW_V1_SEQ_ID_OFS_SHIFT) | ETH_P_1588; 15292e5b38abSRichard Cochran ts_en = EVENT_MSG_BITS << CPSW_V1_MSG_TYPE_OFS; 15302e5b38abSRichard Cochran 15312a05a622SIvan Khoronzhuk if (cpsw->cpts->tx_enable) 15322e5b38abSRichard Cochran ts_en |= CPSW_V1_TS_TX_EN; 15332e5b38abSRichard Cochran 15342a05a622SIvan Khoronzhuk if (cpsw->cpts->rx_enable) 15352e5b38abSRichard Cochran ts_en |= CPSW_V1_TS_RX_EN; 15362e5b38abSRichard Cochran 15372e5b38abSRichard Cochran slave_write(slave, ts_en, CPSW1_TS_CTL); 15382e5b38abSRichard Cochran slave_write(slave, seq_id, CPSW1_TS_SEQ_LTYPE); 15392e5b38abSRichard Cochran } 15402e5b38abSRichard Cochran 15412e5b38abSRichard Cochran static void cpsw_hwtstamp_v2(struct cpsw_priv *priv) 15422e5b38abSRichard Cochran { 1543d9ba8f9eSMugunthan V N struct cpsw_slave *slave; 15445d8d0d4dSIvan Khoronzhuk struct cpsw_common *cpsw = priv->cpsw; 15452e5b38abSRichard Cochran u32 ctrl, mtype; 15462e5b38abSRichard Cochran 1547606f3993SIvan Khoronzhuk if (cpsw->data.dual_emac) 1548606f3993SIvan Khoronzhuk slave = &cpsw->slaves[priv->emac_port]; 1549d9ba8f9eSMugunthan V N else 1550606f3993SIvan Khoronzhuk slave = &cpsw->slaves[cpsw->data.active_slave]; 1551d9ba8f9eSMugunthan V N 15522e5b38abSRichard Cochran ctrl = slave_read(slave, CPSW2_CONTROL); 15532a05a622SIvan Khoronzhuk switch (cpsw->version) { 155409c55372SGeorge Cherian case CPSW_VERSION_2: 155509c55372SGeorge Cherian ctrl &= ~CTRL_V2_ALL_TS_MASK; 15562e5b38abSRichard Cochran 15572a05a622SIvan Khoronzhuk if (cpsw->cpts->tx_enable) 155809c55372SGeorge Cherian ctrl |= CTRL_V2_TX_TS_BITS; 15592e5b38abSRichard Cochran 15602a05a622SIvan Khoronzhuk if (cpsw->cpts->rx_enable) 156109c55372SGeorge Cherian ctrl |= CTRL_V2_RX_TS_BITS; 156209c55372SGeorge Cherian break; 156309c55372SGeorge Cherian case CPSW_VERSION_3: 156409c55372SGeorge Cherian default: 156509c55372SGeorge Cherian ctrl &= ~CTRL_V3_ALL_TS_MASK; 156609c55372SGeorge Cherian 15672a05a622SIvan Khoronzhuk if (cpsw->cpts->tx_enable) 156809c55372SGeorge Cherian ctrl |= CTRL_V3_TX_TS_BITS; 156909c55372SGeorge Cherian 15702a05a622SIvan Khoronzhuk if (cpsw->cpts->rx_enable) 157109c55372SGeorge Cherian ctrl |= CTRL_V3_RX_TS_BITS; 157209c55372SGeorge Cherian break; 157309c55372SGeorge Cherian } 15742e5b38abSRichard Cochran 15752e5b38abSRichard Cochran mtype = (30 << TS_SEQ_ID_OFFSET_SHIFT) | EVENT_MSG_BITS; 15762e5b38abSRichard Cochran 15772e5b38abSRichard Cochran slave_write(slave, mtype, CPSW2_TS_SEQ_MTYPE); 15782e5b38abSRichard Cochran slave_write(slave, ctrl, CPSW2_CONTROL); 15795d8d0d4dSIvan Khoronzhuk __raw_writel(ETH_P_1588, &cpsw->regs->ts_ltype); 15802e5b38abSRichard Cochran } 15812e5b38abSRichard Cochran 1582a5b4145bSBen Hutchings static int cpsw_hwtstamp_set(struct net_device *dev, struct ifreq *ifr) 15832e5b38abSRichard Cochran { 15843177bf6fSMugunthan V N struct cpsw_priv *priv = netdev_priv(dev); 15852e5b38abSRichard Cochran struct hwtstamp_config cfg; 15862a05a622SIvan Khoronzhuk struct cpsw_common *cpsw = priv->cpsw; 15872a05a622SIvan Khoronzhuk struct cpts *cpts = cpsw->cpts; 15882e5b38abSRichard Cochran 15892a05a622SIvan Khoronzhuk if (cpsw->version != CPSW_VERSION_1 && 15902a05a622SIvan Khoronzhuk cpsw->version != CPSW_VERSION_2 && 15912a05a622SIvan Khoronzhuk cpsw->version != CPSW_VERSION_3) 15922ee91e54SBen Hutchings return -EOPNOTSUPP; 15932ee91e54SBen Hutchings 15942e5b38abSRichard Cochran if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg))) 15952e5b38abSRichard Cochran return -EFAULT; 15962e5b38abSRichard Cochran 15972e5b38abSRichard Cochran /* reserved for future extensions */ 15982e5b38abSRichard Cochran if (cfg.flags) 15992e5b38abSRichard Cochran return -EINVAL; 16002e5b38abSRichard Cochran 16012ee91e54SBen Hutchings if (cfg.tx_type != HWTSTAMP_TX_OFF && cfg.tx_type != HWTSTAMP_TX_ON) 16022e5b38abSRichard Cochran return -ERANGE; 16032e5b38abSRichard Cochran 16042e5b38abSRichard Cochran switch (cfg.rx_filter) { 16052e5b38abSRichard Cochran case HWTSTAMP_FILTER_NONE: 16062e5b38abSRichard Cochran cpts->rx_enable = 0; 16072e5b38abSRichard Cochran break; 16082e5b38abSRichard Cochran case HWTSTAMP_FILTER_ALL: 16092e5b38abSRichard Cochran case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: 16102e5b38abSRichard Cochran case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: 16112e5b38abSRichard Cochran case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: 16122e5b38abSRichard Cochran return -ERANGE; 16132e5b38abSRichard Cochran case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: 16142e5b38abSRichard Cochran case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 16152e5b38abSRichard Cochran case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 16162e5b38abSRichard Cochran case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: 16172e5b38abSRichard Cochran case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: 16182e5b38abSRichard Cochran case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: 16192e5b38abSRichard Cochran case HWTSTAMP_FILTER_PTP_V2_EVENT: 16202e5b38abSRichard Cochran case HWTSTAMP_FILTER_PTP_V2_SYNC: 16212e5b38abSRichard Cochran case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 16222e5b38abSRichard Cochran cpts->rx_enable = 1; 16232e5b38abSRichard Cochran cfg.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT; 16242e5b38abSRichard Cochran break; 16252e5b38abSRichard Cochran default: 16262e5b38abSRichard Cochran return -ERANGE; 16272e5b38abSRichard Cochran } 16282e5b38abSRichard Cochran 16292ee91e54SBen Hutchings cpts->tx_enable = cfg.tx_type == HWTSTAMP_TX_ON; 16302ee91e54SBen Hutchings 16312a05a622SIvan Khoronzhuk switch (cpsw->version) { 16322e5b38abSRichard Cochran case CPSW_VERSION_1: 16332a05a622SIvan Khoronzhuk cpsw_hwtstamp_v1(cpsw); 16342e5b38abSRichard Cochran break; 16352e5b38abSRichard Cochran case CPSW_VERSION_2: 1636f7d403cbSGeorge Cherian case CPSW_VERSION_3: 16372e5b38abSRichard Cochran cpsw_hwtstamp_v2(priv); 16382e5b38abSRichard Cochran break; 16392e5b38abSRichard Cochran default: 16402ee91e54SBen Hutchings WARN_ON(1); 16412e5b38abSRichard Cochran } 16422e5b38abSRichard Cochran 16432e5b38abSRichard Cochran return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0; 16442e5b38abSRichard Cochran } 16452e5b38abSRichard Cochran 1646a5b4145bSBen Hutchings static int cpsw_hwtstamp_get(struct net_device *dev, struct ifreq *ifr) 1647a5b4145bSBen Hutchings { 16482a05a622SIvan Khoronzhuk struct cpsw_common *cpsw = ndev_to_cpsw(dev); 16492a05a622SIvan Khoronzhuk struct cpts *cpts = cpsw->cpts; 1650a5b4145bSBen Hutchings struct hwtstamp_config cfg; 1651a5b4145bSBen Hutchings 16522a05a622SIvan Khoronzhuk if (cpsw->version != CPSW_VERSION_1 && 16532a05a622SIvan Khoronzhuk cpsw->version != CPSW_VERSION_2 && 16542a05a622SIvan Khoronzhuk cpsw->version != CPSW_VERSION_3) 1655a5b4145bSBen Hutchings return -EOPNOTSUPP; 1656a5b4145bSBen Hutchings 1657a5b4145bSBen Hutchings cfg.flags = 0; 1658a5b4145bSBen Hutchings cfg.tx_type = cpts->tx_enable ? HWTSTAMP_TX_ON : HWTSTAMP_TX_OFF; 1659a5b4145bSBen Hutchings cfg.rx_filter = (cpts->rx_enable ? 1660a5b4145bSBen Hutchings HWTSTAMP_FILTER_PTP_V2_EVENT : HWTSTAMP_FILTER_NONE); 1661a5b4145bSBen Hutchings 1662a5b4145bSBen Hutchings return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0; 1663a5b4145bSBen Hutchings } 1664a5b4145bSBen Hutchings 16652e5b38abSRichard Cochran #endif /*CONFIG_TI_CPTS*/ 16662e5b38abSRichard Cochran 16672e5b38abSRichard Cochran static int cpsw_ndo_ioctl(struct net_device *dev, struct ifreq *req, int cmd) 16682e5b38abSRichard Cochran { 166911f2c988SMugunthan V N struct cpsw_priv *priv = netdev_priv(dev); 1670606f3993SIvan Khoronzhuk struct cpsw_common *cpsw = priv->cpsw; 1671606f3993SIvan Khoronzhuk int slave_no = cpsw_slave_index(cpsw, priv); 167211f2c988SMugunthan V N 16732e5b38abSRichard Cochran if (!netif_running(dev)) 16742e5b38abSRichard Cochran return -EINVAL; 16752e5b38abSRichard Cochran 167611f2c988SMugunthan V N switch (cmd) { 16772e5b38abSRichard Cochran #ifdef CONFIG_TI_CPTS 167811f2c988SMugunthan V N case SIOCSHWTSTAMP: 1679a5b4145bSBen Hutchings return cpsw_hwtstamp_set(dev, req); 1680a5b4145bSBen Hutchings case SIOCGHWTSTAMP: 1681a5b4145bSBen Hutchings return cpsw_hwtstamp_get(dev, req); 16822e5b38abSRichard Cochran #endif 16832e5b38abSRichard Cochran } 16842e5b38abSRichard Cochran 1685606f3993SIvan Khoronzhuk if (!cpsw->slaves[slave_no].phy) 1686c1b59947SStefan Sørensen return -EOPNOTSUPP; 1687606f3993SIvan Khoronzhuk return phy_mii_ioctl(cpsw->slaves[slave_no].phy, req, cmd); 168811f2c988SMugunthan V N } 168911f2c988SMugunthan V N 1690df828598SMugunthan V N static void cpsw_ndo_tx_timeout(struct net_device *ndev) 1691df828598SMugunthan V N { 1692df828598SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 16932c836bd9SIvan Khoronzhuk struct cpsw_common *cpsw = priv->cpsw; 1694e05107e6SIvan Khoronzhuk int ch; 1695df828598SMugunthan V N 1696df828598SMugunthan V N cpsw_err(priv, tx_err, "transmit timeout, restarting dma\n"); 16978dc43ddcSTobias Klauser ndev->stats.tx_errors++; 16982c836bd9SIvan Khoronzhuk cpsw_intr_disable(cpsw); 1699e05107e6SIvan Khoronzhuk for (ch = 0; ch < cpsw->tx_ch_num; ch++) { 1700e05107e6SIvan Khoronzhuk cpdma_chan_stop(cpsw->txch[ch]); 1701e05107e6SIvan Khoronzhuk cpdma_chan_start(cpsw->txch[ch]); 1702e05107e6SIvan Khoronzhuk } 1703e05107e6SIvan Khoronzhuk 17042c836bd9SIvan Khoronzhuk cpsw_intr_enable(cpsw); 1705df828598SMugunthan V N } 1706df828598SMugunthan V N 1707dcfd8d58SMugunthan V N static int cpsw_ndo_set_mac_address(struct net_device *ndev, void *p) 1708dcfd8d58SMugunthan V N { 1709dcfd8d58SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 1710dcfd8d58SMugunthan V N struct sockaddr *addr = (struct sockaddr *)p; 1711649a1688SIvan Khoronzhuk struct cpsw_common *cpsw = priv->cpsw; 1712dcfd8d58SMugunthan V N int flags = 0; 1713dcfd8d58SMugunthan V N u16 vid = 0; 1714a6c5d14fSGrygorii Strashko int ret; 1715dcfd8d58SMugunthan V N 1716dcfd8d58SMugunthan V N if (!is_valid_ether_addr(addr->sa_data)) 1717dcfd8d58SMugunthan V N return -EADDRNOTAVAIL; 1718dcfd8d58SMugunthan V N 171956e31bd8SIvan Khoronzhuk ret = pm_runtime_get_sync(cpsw->dev); 1720a6c5d14fSGrygorii Strashko if (ret < 0) { 172156e31bd8SIvan Khoronzhuk pm_runtime_put_noidle(cpsw->dev); 1722a6c5d14fSGrygorii Strashko return ret; 1723a6c5d14fSGrygorii Strashko } 1724a6c5d14fSGrygorii Strashko 1725606f3993SIvan Khoronzhuk if (cpsw->data.dual_emac) { 1726606f3993SIvan Khoronzhuk vid = cpsw->slaves[priv->emac_port].port_vlan; 1727dcfd8d58SMugunthan V N flags = ALE_VLAN; 1728dcfd8d58SMugunthan V N } 1729dcfd8d58SMugunthan V N 17302a05a622SIvan Khoronzhuk cpsw_ale_del_ucast(cpsw->ale, priv->mac_addr, HOST_PORT_NUM, 1731dcfd8d58SMugunthan V N flags, vid); 17322a05a622SIvan Khoronzhuk cpsw_ale_add_ucast(cpsw->ale, addr->sa_data, HOST_PORT_NUM, 1733dcfd8d58SMugunthan V N flags, vid); 1734dcfd8d58SMugunthan V N 1735dcfd8d58SMugunthan V N memcpy(priv->mac_addr, addr->sa_data, ETH_ALEN); 1736dcfd8d58SMugunthan V N memcpy(ndev->dev_addr, priv->mac_addr, ETH_ALEN); 1737dcfd8d58SMugunthan V N for_each_slave(priv, cpsw_set_slave_mac, priv); 1738dcfd8d58SMugunthan V N 173956e31bd8SIvan Khoronzhuk pm_runtime_put(cpsw->dev); 1740a6c5d14fSGrygorii Strashko 1741dcfd8d58SMugunthan V N return 0; 1742dcfd8d58SMugunthan V N } 1743dcfd8d58SMugunthan V N 1744df828598SMugunthan V N #ifdef CONFIG_NET_POLL_CONTROLLER 1745df828598SMugunthan V N static void cpsw_ndo_poll_controller(struct net_device *ndev) 1746df828598SMugunthan V N { 1747dbc4ec52SIvan Khoronzhuk struct cpsw_common *cpsw = ndev_to_cpsw(ndev); 1748df828598SMugunthan V N 1749dbc4ec52SIvan Khoronzhuk cpsw_intr_disable(cpsw); 1750dbc4ec52SIvan Khoronzhuk cpsw_rx_interrupt(cpsw->irqs_table[0], cpsw); 1751dbc4ec52SIvan Khoronzhuk cpsw_tx_interrupt(cpsw->irqs_table[1], cpsw); 1752dbc4ec52SIvan Khoronzhuk cpsw_intr_enable(cpsw); 1753df828598SMugunthan V N } 1754df828598SMugunthan V N #endif 1755df828598SMugunthan V N 17563b72c2feSMugunthan V N static inline int cpsw_add_vlan_ale_entry(struct cpsw_priv *priv, 17573b72c2feSMugunthan V N unsigned short vid) 17583b72c2feSMugunthan V N { 17593b72c2feSMugunthan V N int ret; 17609f6bd8faSMugunthan V N int unreg_mcast_mask = 0; 17619f6bd8faSMugunthan V N u32 port_mask; 1762606f3993SIvan Khoronzhuk struct cpsw_common *cpsw = priv->cpsw; 17639f6bd8faSMugunthan V N 1764606f3993SIvan Khoronzhuk if (cpsw->data.dual_emac) { 17659f6bd8faSMugunthan V N port_mask = (1 << (priv->emac_port + 1)) | ALE_PORT_HOST; 17669f6bd8faSMugunthan V N 17679f6bd8faSMugunthan V N if (priv->ndev->flags & IFF_ALLMULTI) 17689f6bd8faSMugunthan V N unreg_mcast_mask = port_mask; 17699f6bd8faSMugunthan V N } else { 17709f6bd8faSMugunthan V N port_mask = ALE_ALL_PORTS; 17711e5c4bc4SLennart Sorensen 17721e5c4bc4SLennart Sorensen if (priv->ndev->flags & IFF_ALLMULTI) 17731e5c4bc4SLennart Sorensen unreg_mcast_mask = ALE_ALL_PORTS; 17741e5c4bc4SLennart Sorensen else 17751e5c4bc4SLennart Sorensen unreg_mcast_mask = ALE_PORT_1 | ALE_PORT_2; 17769f6bd8faSMugunthan V N } 17773b72c2feSMugunthan V N 17782a05a622SIvan Khoronzhuk ret = cpsw_ale_add_vlan(cpsw->ale, vid, port_mask, 0, port_mask, 177961f1cef9SGrygorii Strashko unreg_mcast_mask); 17803b72c2feSMugunthan V N if (ret != 0) 17813b72c2feSMugunthan V N return ret; 17823b72c2feSMugunthan V N 17832a05a622SIvan Khoronzhuk ret = cpsw_ale_add_ucast(cpsw->ale, priv->mac_addr, 178471a2cbb7SGrygorii Strashko HOST_PORT_NUM, ALE_VLAN, vid); 17853b72c2feSMugunthan V N if (ret != 0) 17863b72c2feSMugunthan V N goto clean_vid; 17873b72c2feSMugunthan V N 17882a05a622SIvan Khoronzhuk ret = cpsw_ale_add_mcast(cpsw->ale, priv->ndev->broadcast, 17899f6bd8faSMugunthan V N port_mask, ALE_VLAN, vid, 0); 17903b72c2feSMugunthan V N if (ret != 0) 17913b72c2feSMugunthan V N goto clean_vlan_ucast; 17923b72c2feSMugunthan V N return 0; 17933b72c2feSMugunthan V N 17943b72c2feSMugunthan V N clean_vlan_ucast: 17952a05a622SIvan Khoronzhuk cpsw_ale_del_ucast(cpsw->ale, priv->mac_addr, 179671a2cbb7SGrygorii Strashko HOST_PORT_NUM, ALE_VLAN, vid); 17973b72c2feSMugunthan V N clean_vid: 17982a05a622SIvan Khoronzhuk cpsw_ale_del_vlan(cpsw->ale, vid, 0); 17993b72c2feSMugunthan V N return ret; 18003b72c2feSMugunthan V N } 18013b72c2feSMugunthan V N 18023b72c2feSMugunthan V N static int cpsw_ndo_vlan_rx_add_vid(struct net_device *ndev, 180380d5c368SPatrick McHardy __be16 proto, u16 vid) 18043b72c2feSMugunthan V N { 18053b72c2feSMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 1806649a1688SIvan Khoronzhuk struct cpsw_common *cpsw = priv->cpsw; 1807a6c5d14fSGrygorii Strashko int ret; 18083b72c2feSMugunthan V N 1809606f3993SIvan Khoronzhuk if (vid == cpsw->data.default_vlan) 18103b72c2feSMugunthan V N return 0; 18113b72c2feSMugunthan V N 181256e31bd8SIvan Khoronzhuk ret = pm_runtime_get_sync(cpsw->dev); 1813a6c5d14fSGrygorii Strashko if (ret < 0) { 181456e31bd8SIvan Khoronzhuk pm_runtime_put_noidle(cpsw->dev); 1815a6c5d14fSGrygorii Strashko return ret; 1816a6c5d14fSGrygorii Strashko } 1817a6c5d14fSGrygorii Strashko 1818606f3993SIvan Khoronzhuk if (cpsw->data.dual_emac) { 181902a54164SMugunthan V N /* In dual EMAC, reserved VLAN id should not be used for 182002a54164SMugunthan V N * creating VLAN interfaces as this can break the dual 182102a54164SMugunthan V N * EMAC port separation 182202a54164SMugunthan V N */ 182302a54164SMugunthan V N int i; 182402a54164SMugunthan V N 1825606f3993SIvan Khoronzhuk for (i = 0; i < cpsw->data.slaves; i++) { 1826606f3993SIvan Khoronzhuk if (vid == cpsw->slaves[i].port_vlan) 182702a54164SMugunthan V N return -EINVAL; 182802a54164SMugunthan V N } 182902a54164SMugunthan V N } 183002a54164SMugunthan V N 18313b72c2feSMugunthan V N dev_info(priv->dev, "Adding vlanid %d to vlan filter\n", vid); 1832a6c5d14fSGrygorii Strashko ret = cpsw_add_vlan_ale_entry(priv, vid); 1833a6c5d14fSGrygorii Strashko 183456e31bd8SIvan Khoronzhuk pm_runtime_put(cpsw->dev); 1835a6c5d14fSGrygorii Strashko return ret; 18363b72c2feSMugunthan V N } 18373b72c2feSMugunthan V N 18383b72c2feSMugunthan V N static int cpsw_ndo_vlan_rx_kill_vid(struct net_device *ndev, 183980d5c368SPatrick McHardy __be16 proto, u16 vid) 18403b72c2feSMugunthan V N { 18413b72c2feSMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 1842649a1688SIvan Khoronzhuk struct cpsw_common *cpsw = priv->cpsw; 18433b72c2feSMugunthan V N int ret; 18443b72c2feSMugunthan V N 1845606f3993SIvan Khoronzhuk if (vid == cpsw->data.default_vlan) 18463b72c2feSMugunthan V N return 0; 18473b72c2feSMugunthan V N 184856e31bd8SIvan Khoronzhuk ret = pm_runtime_get_sync(cpsw->dev); 1849a6c5d14fSGrygorii Strashko if (ret < 0) { 185056e31bd8SIvan Khoronzhuk pm_runtime_put_noidle(cpsw->dev); 1851a6c5d14fSGrygorii Strashko return ret; 1852a6c5d14fSGrygorii Strashko } 1853a6c5d14fSGrygorii Strashko 1854606f3993SIvan Khoronzhuk if (cpsw->data.dual_emac) { 185502a54164SMugunthan V N int i; 185602a54164SMugunthan V N 1857606f3993SIvan Khoronzhuk for (i = 0; i < cpsw->data.slaves; i++) { 1858606f3993SIvan Khoronzhuk if (vid == cpsw->slaves[i].port_vlan) 185902a54164SMugunthan V N return -EINVAL; 186002a54164SMugunthan V N } 186102a54164SMugunthan V N } 186202a54164SMugunthan V N 18633b72c2feSMugunthan V N dev_info(priv->dev, "removing vlanid %d from vlan filter\n", vid); 18642a05a622SIvan Khoronzhuk ret = cpsw_ale_del_vlan(cpsw->ale, vid, 0); 18653b72c2feSMugunthan V N if (ret != 0) 18663b72c2feSMugunthan V N return ret; 18673b72c2feSMugunthan V N 18682a05a622SIvan Khoronzhuk ret = cpsw_ale_del_ucast(cpsw->ale, priv->mac_addr, 186961f1cef9SGrygorii Strashko HOST_PORT_NUM, ALE_VLAN, vid); 18703b72c2feSMugunthan V N if (ret != 0) 18713b72c2feSMugunthan V N return ret; 18723b72c2feSMugunthan V N 18732a05a622SIvan Khoronzhuk ret = cpsw_ale_del_mcast(cpsw->ale, priv->ndev->broadcast, 18743b72c2feSMugunthan V N 0, ALE_VLAN, vid); 187556e31bd8SIvan Khoronzhuk pm_runtime_put(cpsw->dev); 1876a6c5d14fSGrygorii Strashko return ret; 18773b72c2feSMugunthan V N } 18783b72c2feSMugunthan V N 1879df828598SMugunthan V N static const struct net_device_ops cpsw_netdev_ops = { 1880df828598SMugunthan V N .ndo_open = cpsw_ndo_open, 1881df828598SMugunthan V N .ndo_stop = cpsw_ndo_stop, 1882df828598SMugunthan V N .ndo_start_xmit = cpsw_ndo_start_xmit, 1883dcfd8d58SMugunthan V N .ndo_set_mac_address = cpsw_ndo_set_mac_address, 18842e5b38abSRichard Cochran .ndo_do_ioctl = cpsw_ndo_ioctl, 1885df828598SMugunthan V N .ndo_validate_addr = eth_validate_addr, 18865c473ed2SDavid S. Miller .ndo_change_mtu = eth_change_mtu, 1887df828598SMugunthan V N .ndo_tx_timeout = cpsw_ndo_tx_timeout, 18885c50a856SMugunthan V N .ndo_set_rx_mode = cpsw_ndo_set_rx_mode, 1889df828598SMugunthan V N #ifdef CONFIG_NET_POLL_CONTROLLER 1890df828598SMugunthan V N .ndo_poll_controller = cpsw_ndo_poll_controller, 1891df828598SMugunthan V N #endif 18923b72c2feSMugunthan V N .ndo_vlan_rx_add_vid = cpsw_ndo_vlan_rx_add_vid, 18933b72c2feSMugunthan V N .ndo_vlan_rx_kill_vid = cpsw_ndo_vlan_rx_kill_vid, 1894df828598SMugunthan V N }; 1895df828598SMugunthan V N 189652c4f0ecSMugunthan V N static int cpsw_get_regs_len(struct net_device *ndev) 189752c4f0ecSMugunthan V N { 1898606f3993SIvan Khoronzhuk struct cpsw_common *cpsw = ndev_to_cpsw(ndev); 189952c4f0ecSMugunthan V N 1900606f3993SIvan Khoronzhuk return cpsw->data.ale_entries * ALE_ENTRY_WORDS * sizeof(u32); 190152c4f0ecSMugunthan V N } 190252c4f0ecSMugunthan V N 190352c4f0ecSMugunthan V N static void cpsw_get_regs(struct net_device *ndev, 190452c4f0ecSMugunthan V N struct ethtool_regs *regs, void *p) 190552c4f0ecSMugunthan V N { 190652c4f0ecSMugunthan V N u32 *reg = p; 19072a05a622SIvan Khoronzhuk struct cpsw_common *cpsw = ndev_to_cpsw(ndev); 190852c4f0ecSMugunthan V N 190952c4f0ecSMugunthan V N /* update CPSW IP version */ 19102a05a622SIvan Khoronzhuk regs->version = cpsw->version; 191152c4f0ecSMugunthan V N 19122a05a622SIvan Khoronzhuk cpsw_ale_dump(cpsw->ale, reg); 191352c4f0ecSMugunthan V N } 191452c4f0ecSMugunthan V N 1915df828598SMugunthan V N static void cpsw_get_drvinfo(struct net_device *ndev, 1916df828598SMugunthan V N struct ethtool_drvinfo *info) 1917df828598SMugunthan V N { 1918649a1688SIvan Khoronzhuk struct cpsw_common *cpsw = ndev_to_cpsw(ndev); 191956e31bd8SIvan Khoronzhuk struct platform_device *pdev = to_platform_device(cpsw->dev); 19207826d43fSJiri Pirko 192152c4f0ecSMugunthan V N strlcpy(info->driver, "cpsw", sizeof(info->driver)); 19227826d43fSJiri Pirko strlcpy(info->version, "1.0", sizeof(info->version)); 192356e31bd8SIvan Khoronzhuk strlcpy(info->bus_info, pdev->name, sizeof(info->bus_info)); 1924df828598SMugunthan V N } 1925df828598SMugunthan V N 1926df828598SMugunthan V N static u32 cpsw_get_msglevel(struct net_device *ndev) 1927df828598SMugunthan V N { 1928df828598SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 1929df828598SMugunthan V N return priv->msg_enable; 1930df828598SMugunthan V N } 1931df828598SMugunthan V N 1932df828598SMugunthan V N static void cpsw_set_msglevel(struct net_device *ndev, u32 value) 1933df828598SMugunthan V N { 1934df828598SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 1935df828598SMugunthan V N priv->msg_enable = value; 1936df828598SMugunthan V N } 1937df828598SMugunthan V N 19382e5b38abSRichard Cochran static int cpsw_get_ts_info(struct net_device *ndev, 19392e5b38abSRichard Cochran struct ethtool_ts_info *info) 19402e5b38abSRichard Cochran { 19412e5b38abSRichard Cochran #ifdef CONFIG_TI_CPTS 19422a05a622SIvan Khoronzhuk struct cpsw_common *cpsw = ndev_to_cpsw(ndev); 19432e5b38abSRichard Cochran 19442e5b38abSRichard Cochran info->so_timestamping = 19452e5b38abSRichard Cochran SOF_TIMESTAMPING_TX_HARDWARE | 19462e5b38abSRichard Cochran SOF_TIMESTAMPING_TX_SOFTWARE | 19472e5b38abSRichard Cochran SOF_TIMESTAMPING_RX_HARDWARE | 19482e5b38abSRichard Cochran SOF_TIMESTAMPING_RX_SOFTWARE | 19492e5b38abSRichard Cochran SOF_TIMESTAMPING_SOFTWARE | 19502e5b38abSRichard Cochran SOF_TIMESTAMPING_RAW_HARDWARE; 19512a05a622SIvan Khoronzhuk info->phc_index = cpsw->cpts->phc_index; 19522e5b38abSRichard Cochran info->tx_types = 19532e5b38abSRichard Cochran (1 << HWTSTAMP_TX_OFF) | 19542e5b38abSRichard Cochran (1 << HWTSTAMP_TX_ON); 19552e5b38abSRichard Cochran info->rx_filters = 19562e5b38abSRichard Cochran (1 << HWTSTAMP_FILTER_NONE) | 19572e5b38abSRichard Cochran (1 << HWTSTAMP_FILTER_PTP_V2_EVENT); 19582e5b38abSRichard Cochran #else 19592e5b38abSRichard Cochran info->so_timestamping = 19602e5b38abSRichard Cochran SOF_TIMESTAMPING_TX_SOFTWARE | 19612e5b38abSRichard Cochran SOF_TIMESTAMPING_RX_SOFTWARE | 19622e5b38abSRichard Cochran SOF_TIMESTAMPING_SOFTWARE; 19632e5b38abSRichard Cochran info->phc_index = -1; 19642e5b38abSRichard Cochran info->tx_types = 0; 19652e5b38abSRichard Cochran info->rx_filters = 0; 19662e5b38abSRichard Cochran #endif 19672e5b38abSRichard Cochran return 0; 19682e5b38abSRichard Cochran } 19692e5b38abSRichard Cochran 1970d3bb9c58SMugunthan V N static int cpsw_get_settings(struct net_device *ndev, 1971d3bb9c58SMugunthan V N struct ethtool_cmd *ecmd) 1972d3bb9c58SMugunthan V N { 1973d3bb9c58SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 1974606f3993SIvan Khoronzhuk struct cpsw_common *cpsw = priv->cpsw; 1975606f3993SIvan Khoronzhuk int slave_no = cpsw_slave_index(cpsw, priv); 1976d3bb9c58SMugunthan V N 1977606f3993SIvan Khoronzhuk if (cpsw->slaves[slave_no].phy) 1978606f3993SIvan Khoronzhuk return phy_ethtool_gset(cpsw->slaves[slave_no].phy, ecmd); 1979d3bb9c58SMugunthan V N else 1980d3bb9c58SMugunthan V N return -EOPNOTSUPP; 1981d3bb9c58SMugunthan V N } 1982d3bb9c58SMugunthan V N 1983d3bb9c58SMugunthan V N static int cpsw_set_settings(struct net_device *ndev, struct ethtool_cmd *ecmd) 1984d3bb9c58SMugunthan V N { 1985d3bb9c58SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 1986606f3993SIvan Khoronzhuk struct cpsw_common *cpsw = priv->cpsw; 1987606f3993SIvan Khoronzhuk int slave_no = cpsw_slave_index(cpsw, priv); 1988d3bb9c58SMugunthan V N 1989606f3993SIvan Khoronzhuk if (cpsw->slaves[slave_no].phy) 1990606f3993SIvan Khoronzhuk return phy_ethtool_sset(cpsw->slaves[slave_no].phy, ecmd); 1991d3bb9c58SMugunthan V N else 1992d3bb9c58SMugunthan V N return -EOPNOTSUPP; 1993d3bb9c58SMugunthan V N } 1994d3bb9c58SMugunthan V N 1995d8a64420SMatus Ujhelyi static void cpsw_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol) 1996d8a64420SMatus Ujhelyi { 1997d8a64420SMatus Ujhelyi struct cpsw_priv *priv = netdev_priv(ndev); 1998606f3993SIvan Khoronzhuk struct cpsw_common *cpsw = priv->cpsw; 1999606f3993SIvan Khoronzhuk int slave_no = cpsw_slave_index(cpsw, priv); 2000d8a64420SMatus Ujhelyi 2001d8a64420SMatus Ujhelyi wol->supported = 0; 2002d8a64420SMatus Ujhelyi wol->wolopts = 0; 2003d8a64420SMatus Ujhelyi 2004606f3993SIvan Khoronzhuk if (cpsw->slaves[slave_no].phy) 2005606f3993SIvan Khoronzhuk phy_ethtool_get_wol(cpsw->slaves[slave_no].phy, wol); 2006d8a64420SMatus Ujhelyi } 2007d8a64420SMatus Ujhelyi 2008d8a64420SMatus Ujhelyi static int cpsw_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol) 2009d8a64420SMatus Ujhelyi { 2010d8a64420SMatus Ujhelyi struct cpsw_priv *priv = netdev_priv(ndev); 2011606f3993SIvan Khoronzhuk struct cpsw_common *cpsw = priv->cpsw; 2012606f3993SIvan Khoronzhuk int slave_no = cpsw_slave_index(cpsw, priv); 2013d8a64420SMatus Ujhelyi 2014606f3993SIvan Khoronzhuk if (cpsw->slaves[slave_no].phy) 2015606f3993SIvan Khoronzhuk return phy_ethtool_set_wol(cpsw->slaves[slave_no].phy, wol); 2016d8a64420SMatus Ujhelyi else 2017d8a64420SMatus Ujhelyi return -EOPNOTSUPP; 2018d8a64420SMatus Ujhelyi } 2019d8a64420SMatus Ujhelyi 20201923d6e4SMugunthan V N static void cpsw_get_pauseparam(struct net_device *ndev, 20211923d6e4SMugunthan V N struct ethtool_pauseparam *pause) 20221923d6e4SMugunthan V N { 20231923d6e4SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 20241923d6e4SMugunthan V N 20251923d6e4SMugunthan V N pause->autoneg = AUTONEG_DISABLE; 20261923d6e4SMugunthan V N pause->rx_pause = priv->rx_pause ? true : false; 20271923d6e4SMugunthan V N pause->tx_pause = priv->tx_pause ? true : false; 20281923d6e4SMugunthan V N } 20291923d6e4SMugunthan V N 20301923d6e4SMugunthan V N static int cpsw_set_pauseparam(struct net_device *ndev, 20311923d6e4SMugunthan V N struct ethtool_pauseparam *pause) 20321923d6e4SMugunthan V N { 20331923d6e4SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 20341923d6e4SMugunthan V N bool link; 20351923d6e4SMugunthan V N 20361923d6e4SMugunthan V N priv->rx_pause = pause->rx_pause ? true : false; 20371923d6e4SMugunthan V N priv->tx_pause = pause->tx_pause ? true : false; 20381923d6e4SMugunthan V N 20391923d6e4SMugunthan V N for_each_slave(priv, _cpsw_adjust_link, priv, &link); 20401923d6e4SMugunthan V N return 0; 20411923d6e4SMugunthan V N } 20421923d6e4SMugunthan V N 20437898b1daSGrygorii Strashko static int cpsw_ethtool_op_begin(struct net_device *ndev) 20447898b1daSGrygorii Strashko { 20457898b1daSGrygorii Strashko struct cpsw_priv *priv = netdev_priv(ndev); 2046649a1688SIvan Khoronzhuk struct cpsw_common *cpsw = priv->cpsw; 20477898b1daSGrygorii Strashko int ret; 20487898b1daSGrygorii Strashko 204956e31bd8SIvan Khoronzhuk ret = pm_runtime_get_sync(cpsw->dev); 20507898b1daSGrygorii Strashko if (ret < 0) { 20517898b1daSGrygorii Strashko cpsw_err(priv, drv, "ethtool begin failed %d\n", ret); 205256e31bd8SIvan Khoronzhuk pm_runtime_put_noidle(cpsw->dev); 20537898b1daSGrygorii Strashko } 20547898b1daSGrygorii Strashko 20557898b1daSGrygorii Strashko return ret; 20567898b1daSGrygorii Strashko } 20577898b1daSGrygorii Strashko 20587898b1daSGrygorii Strashko static void cpsw_ethtool_op_complete(struct net_device *ndev) 20597898b1daSGrygorii Strashko { 20607898b1daSGrygorii Strashko struct cpsw_priv *priv = netdev_priv(ndev); 20617898b1daSGrygorii Strashko int ret; 20627898b1daSGrygorii Strashko 206356e31bd8SIvan Khoronzhuk ret = pm_runtime_put(priv->cpsw->dev); 20647898b1daSGrygorii Strashko if (ret < 0) 20657898b1daSGrygorii Strashko cpsw_err(priv, drv, "ethtool complete failed %d\n", ret); 20667898b1daSGrygorii Strashko } 20677898b1daSGrygorii Strashko 2068ce52c744SIvan Khoronzhuk static void cpsw_get_channels(struct net_device *ndev, 2069ce52c744SIvan Khoronzhuk struct ethtool_channels *ch) 2070ce52c744SIvan Khoronzhuk { 2071ce52c744SIvan Khoronzhuk struct cpsw_common *cpsw = ndev_to_cpsw(ndev); 2072ce52c744SIvan Khoronzhuk 2073ce52c744SIvan Khoronzhuk ch->max_combined = 0; 2074ce52c744SIvan Khoronzhuk ch->max_rx = CPSW_MAX_QUEUES; 2075ce52c744SIvan Khoronzhuk ch->max_tx = CPSW_MAX_QUEUES; 2076ce52c744SIvan Khoronzhuk ch->max_other = 0; 2077ce52c744SIvan Khoronzhuk ch->other_count = 0; 2078ce52c744SIvan Khoronzhuk ch->rx_count = cpsw->rx_ch_num; 2079ce52c744SIvan Khoronzhuk ch->tx_count = cpsw->tx_ch_num; 2080ce52c744SIvan Khoronzhuk ch->combined_count = 0; 2081ce52c744SIvan Khoronzhuk } 2082ce52c744SIvan Khoronzhuk 2083ce52c744SIvan Khoronzhuk static int cpsw_check_ch_settings(struct cpsw_common *cpsw, 2084ce52c744SIvan Khoronzhuk struct ethtool_channels *ch) 2085ce52c744SIvan Khoronzhuk { 2086ce52c744SIvan Khoronzhuk if (ch->combined_count) 2087ce52c744SIvan Khoronzhuk return -EINVAL; 2088ce52c744SIvan Khoronzhuk 2089ce52c744SIvan Khoronzhuk /* verify we have at least one channel in each direction */ 2090ce52c744SIvan Khoronzhuk if (!ch->rx_count || !ch->tx_count) 2091ce52c744SIvan Khoronzhuk return -EINVAL; 2092ce52c744SIvan Khoronzhuk 2093ce52c744SIvan Khoronzhuk if (ch->rx_count > cpsw->data.channels || 2094ce52c744SIvan Khoronzhuk ch->tx_count > cpsw->data.channels) 2095ce52c744SIvan Khoronzhuk return -EINVAL; 2096ce52c744SIvan Khoronzhuk 2097ce52c744SIvan Khoronzhuk return 0; 2098ce52c744SIvan Khoronzhuk } 2099ce52c744SIvan Khoronzhuk 2100ce52c744SIvan Khoronzhuk static int cpsw_update_channels_res(struct cpsw_priv *priv, int ch_num, int rx) 2101ce52c744SIvan Khoronzhuk { 2102ce52c744SIvan Khoronzhuk int (*poll)(struct napi_struct *, int); 2103ce52c744SIvan Khoronzhuk struct cpsw_common *cpsw = priv->cpsw; 2104ce52c744SIvan Khoronzhuk void (*handler)(void *, int, int); 2105ce52c744SIvan Khoronzhuk struct cpdma_chan **chan; 2106ce52c744SIvan Khoronzhuk int ret, *ch; 2107ce52c744SIvan Khoronzhuk 2108ce52c744SIvan Khoronzhuk if (rx) { 2109ce52c744SIvan Khoronzhuk ch = &cpsw->rx_ch_num; 2110ce52c744SIvan Khoronzhuk chan = cpsw->rxch; 2111ce52c744SIvan Khoronzhuk handler = cpsw_rx_handler; 2112ce52c744SIvan Khoronzhuk poll = cpsw_rx_poll; 2113ce52c744SIvan Khoronzhuk } else { 2114ce52c744SIvan Khoronzhuk ch = &cpsw->tx_ch_num; 2115ce52c744SIvan Khoronzhuk chan = cpsw->txch; 2116ce52c744SIvan Khoronzhuk handler = cpsw_tx_handler; 2117ce52c744SIvan Khoronzhuk poll = cpsw_tx_poll; 2118ce52c744SIvan Khoronzhuk } 2119ce52c744SIvan Khoronzhuk 2120ce52c744SIvan Khoronzhuk while (*ch < ch_num) { 2121ce52c744SIvan Khoronzhuk chan[*ch] = cpdma_chan_create(cpsw->dma, *ch, handler, rx); 2122ce52c744SIvan Khoronzhuk 2123ce52c744SIvan Khoronzhuk if (IS_ERR(chan[*ch])) 2124ce52c744SIvan Khoronzhuk return PTR_ERR(chan[*ch]); 2125ce52c744SIvan Khoronzhuk 2126ce52c744SIvan Khoronzhuk if (!chan[*ch]) 2127ce52c744SIvan Khoronzhuk return -EINVAL; 2128ce52c744SIvan Khoronzhuk 2129ce52c744SIvan Khoronzhuk cpsw_info(priv, ifup, "created new %d %s channel\n", *ch, 2130ce52c744SIvan Khoronzhuk (rx ? "rx" : "tx")); 2131ce52c744SIvan Khoronzhuk (*ch)++; 2132ce52c744SIvan Khoronzhuk } 2133ce52c744SIvan Khoronzhuk 2134ce52c744SIvan Khoronzhuk while (*ch > ch_num) { 2135ce52c744SIvan Khoronzhuk (*ch)--; 2136ce52c744SIvan Khoronzhuk 2137ce52c744SIvan Khoronzhuk ret = cpdma_chan_destroy(chan[*ch]); 2138ce52c744SIvan Khoronzhuk if (ret) 2139ce52c744SIvan Khoronzhuk return ret; 2140ce52c744SIvan Khoronzhuk 2141ce52c744SIvan Khoronzhuk cpsw_info(priv, ifup, "destroyed %d %s channel\n", *ch, 2142ce52c744SIvan Khoronzhuk (rx ? "rx" : "tx")); 2143ce52c744SIvan Khoronzhuk } 2144ce52c744SIvan Khoronzhuk 2145ce52c744SIvan Khoronzhuk return 0; 2146ce52c744SIvan Khoronzhuk } 2147ce52c744SIvan Khoronzhuk 2148ce52c744SIvan Khoronzhuk static int cpsw_update_channels(struct cpsw_priv *priv, 2149ce52c744SIvan Khoronzhuk struct ethtool_channels *ch) 2150ce52c744SIvan Khoronzhuk { 2151ce52c744SIvan Khoronzhuk int ret; 2152ce52c744SIvan Khoronzhuk 2153ce52c744SIvan Khoronzhuk ret = cpsw_update_channels_res(priv, ch->rx_count, 1); 2154ce52c744SIvan Khoronzhuk if (ret) 2155ce52c744SIvan Khoronzhuk return ret; 2156ce52c744SIvan Khoronzhuk 2157ce52c744SIvan Khoronzhuk ret = cpsw_update_channels_res(priv, ch->tx_count, 0); 2158ce52c744SIvan Khoronzhuk if (ret) 2159ce52c744SIvan Khoronzhuk return ret; 2160ce52c744SIvan Khoronzhuk 2161ce52c744SIvan Khoronzhuk return 0; 2162ce52c744SIvan Khoronzhuk } 2163ce52c744SIvan Khoronzhuk 2164ce52c744SIvan Khoronzhuk static int cpsw_set_channels(struct net_device *ndev, 2165ce52c744SIvan Khoronzhuk struct ethtool_channels *chs) 2166ce52c744SIvan Khoronzhuk { 2167ce52c744SIvan Khoronzhuk struct cpsw_priv *priv = netdev_priv(ndev); 2168ce52c744SIvan Khoronzhuk struct cpsw_common *cpsw = priv->cpsw; 2169ce52c744SIvan Khoronzhuk struct cpsw_slave *slave; 2170ce52c744SIvan Khoronzhuk int i, ret; 2171ce52c744SIvan Khoronzhuk 2172ce52c744SIvan Khoronzhuk ret = cpsw_check_ch_settings(cpsw, chs); 2173ce52c744SIvan Khoronzhuk if (ret < 0) 2174ce52c744SIvan Khoronzhuk return ret; 2175ce52c744SIvan Khoronzhuk 2176ce52c744SIvan Khoronzhuk /* Disable NAPI scheduling */ 2177ce52c744SIvan Khoronzhuk cpsw_intr_disable(cpsw); 2178ce52c744SIvan Khoronzhuk 2179ce52c744SIvan Khoronzhuk /* Stop all transmit queues for every network device. 2180ce52c744SIvan Khoronzhuk * Disable re-using rx descriptors with dormant_on. 2181ce52c744SIvan Khoronzhuk */ 2182ce52c744SIvan Khoronzhuk for (i = cpsw->data.slaves, slave = cpsw->slaves; i; i--, slave++) { 2183ce52c744SIvan Khoronzhuk if (!(slave->ndev && netif_running(slave->ndev))) 2184ce52c744SIvan Khoronzhuk continue; 2185ce52c744SIvan Khoronzhuk 2186ce52c744SIvan Khoronzhuk netif_tx_stop_all_queues(slave->ndev); 2187ce52c744SIvan Khoronzhuk netif_dormant_on(slave->ndev); 2188ce52c744SIvan Khoronzhuk } 2189ce52c744SIvan Khoronzhuk 2190ce52c744SIvan Khoronzhuk /* Handle rest of tx packets and stop cpdma channels */ 2191ce52c744SIvan Khoronzhuk cpdma_ctlr_stop(cpsw->dma); 2192ce52c744SIvan Khoronzhuk ret = cpsw_update_channels(priv, chs); 2193ce52c744SIvan Khoronzhuk if (ret) 2194ce52c744SIvan Khoronzhuk goto err; 2195ce52c744SIvan Khoronzhuk 2196ce52c744SIvan Khoronzhuk for (i = cpsw->data.slaves, slave = cpsw->slaves; i; i--, slave++) { 2197ce52c744SIvan Khoronzhuk if (!(slave->ndev && netif_running(slave->ndev))) 2198ce52c744SIvan Khoronzhuk continue; 2199ce52c744SIvan Khoronzhuk 2200ce52c744SIvan Khoronzhuk /* Inform stack about new count of queues */ 2201ce52c744SIvan Khoronzhuk ret = netif_set_real_num_tx_queues(slave->ndev, 2202ce52c744SIvan Khoronzhuk cpsw->tx_ch_num); 2203ce52c744SIvan Khoronzhuk if (ret) { 2204ce52c744SIvan Khoronzhuk dev_err(priv->dev, "cannot set real number of tx queues\n"); 2205ce52c744SIvan Khoronzhuk goto err; 2206ce52c744SIvan Khoronzhuk } 2207ce52c744SIvan Khoronzhuk 2208ce52c744SIvan Khoronzhuk ret = netif_set_real_num_rx_queues(slave->ndev, 2209ce52c744SIvan Khoronzhuk cpsw->rx_ch_num); 2210ce52c744SIvan Khoronzhuk if (ret) { 2211ce52c744SIvan Khoronzhuk dev_err(priv->dev, "cannot set real number of rx queues\n"); 2212ce52c744SIvan Khoronzhuk goto err; 2213ce52c744SIvan Khoronzhuk } 2214ce52c744SIvan Khoronzhuk 2215ce52c744SIvan Khoronzhuk /* Enable rx packets handling */ 2216ce52c744SIvan Khoronzhuk netif_dormant_off(slave->ndev); 2217ce52c744SIvan Khoronzhuk } 2218ce52c744SIvan Khoronzhuk 2219ce52c744SIvan Khoronzhuk if (cpsw_common_res_usage_state(cpsw)) { 2220e19ac157SWei Yongjun ret = cpsw_fill_rx_channels(priv); 2221e19ac157SWei Yongjun if (ret) 2222ce52c744SIvan Khoronzhuk goto err; 2223ce52c744SIvan Khoronzhuk 2224ce52c744SIvan Khoronzhuk /* After this receive is started */ 2225ce52c744SIvan Khoronzhuk cpdma_ctlr_start(cpsw->dma); 2226ce52c744SIvan Khoronzhuk cpsw_intr_enable(cpsw); 2227ce52c744SIvan Khoronzhuk } 2228ce52c744SIvan Khoronzhuk 2229ce52c744SIvan Khoronzhuk /* Resume transmit for every affected interface */ 2230ce52c744SIvan Khoronzhuk for (i = cpsw->data.slaves, slave = cpsw->slaves; i; i--, slave++) { 2231ce52c744SIvan Khoronzhuk if (!(slave->ndev && netif_running(slave->ndev))) 2232ce52c744SIvan Khoronzhuk continue; 2233ce52c744SIvan Khoronzhuk netif_tx_start_all_queues(slave->ndev); 2234ce52c744SIvan Khoronzhuk } 2235ce52c744SIvan Khoronzhuk return 0; 2236ce52c744SIvan Khoronzhuk err: 2237ce52c744SIvan Khoronzhuk dev_err(priv->dev, "cannot update channels number, closing device\n"); 2238ce52c744SIvan Khoronzhuk dev_close(ndev); 2239ce52c744SIvan Khoronzhuk return ret; 2240ce52c744SIvan Khoronzhuk } 2241ce52c744SIvan Khoronzhuk 2242df828598SMugunthan V N static const struct ethtool_ops cpsw_ethtool_ops = { 2243df828598SMugunthan V N .get_drvinfo = cpsw_get_drvinfo, 2244df828598SMugunthan V N .get_msglevel = cpsw_get_msglevel, 2245df828598SMugunthan V N .set_msglevel = cpsw_set_msglevel, 2246df828598SMugunthan V N .get_link = ethtool_op_get_link, 22472e5b38abSRichard Cochran .get_ts_info = cpsw_get_ts_info, 2248d3bb9c58SMugunthan V N .get_settings = cpsw_get_settings, 2249d3bb9c58SMugunthan V N .set_settings = cpsw_set_settings, 2250ff5b8ef2SMugunthan V N .get_coalesce = cpsw_get_coalesce, 2251ff5b8ef2SMugunthan V N .set_coalesce = cpsw_set_coalesce, 2252d9718546SMugunthan V N .get_sset_count = cpsw_get_sset_count, 2253d9718546SMugunthan V N .get_strings = cpsw_get_strings, 2254d9718546SMugunthan V N .get_ethtool_stats = cpsw_get_ethtool_stats, 22551923d6e4SMugunthan V N .get_pauseparam = cpsw_get_pauseparam, 22561923d6e4SMugunthan V N .set_pauseparam = cpsw_set_pauseparam, 2257d8a64420SMatus Ujhelyi .get_wol = cpsw_get_wol, 2258d8a64420SMatus Ujhelyi .set_wol = cpsw_set_wol, 225952c4f0ecSMugunthan V N .get_regs_len = cpsw_get_regs_len, 226052c4f0ecSMugunthan V N .get_regs = cpsw_get_regs, 22617898b1daSGrygorii Strashko .begin = cpsw_ethtool_op_begin, 22627898b1daSGrygorii Strashko .complete = cpsw_ethtool_op_complete, 2263ce52c744SIvan Khoronzhuk .get_channels = cpsw_get_channels, 2264ce52c744SIvan Khoronzhuk .set_channels = cpsw_set_channels, 2265df828598SMugunthan V N }; 2266df828598SMugunthan V N 2267606f3993SIvan Khoronzhuk static void cpsw_slave_init(struct cpsw_slave *slave, struct cpsw_common *cpsw, 2268549985eeSRichard Cochran u32 slave_reg_ofs, u32 sliver_reg_ofs) 2269df828598SMugunthan V N { 22705d8d0d4dSIvan Khoronzhuk void __iomem *regs = cpsw->regs; 2271df828598SMugunthan V N int slave_num = slave->slave_num; 2272606f3993SIvan Khoronzhuk struct cpsw_slave_data *data = cpsw->data.slave_data + slave_num; 2273df828598SMugunthan V N 2274df828598SMugunthan V N slave->data = data; 2275549985eeSRichard Cochran slave->regs = regs + slave_reg_ofs; 2276549985eeSRichard Cochran slave->sliver = regs + sliver_reg_ofs; 2277d9ba8f9eSMugunthan V N slave->port_vlan = data->dual_emac_res_vlan; 2278df828598SMugunthan V N } 2279df828598SMugunthan V N 2280552165bcSDavid Rivshin static int cpsw_probe_dt(struct cpsw_platform_data *data, 22812eb32b0aSMugunthan V N struct platform_device *pdev) 22822eb32b0aSMugunthan V N { 22832eb32b0aSMugunthan V N struct device_node *node = pdev->dev.of_node; 22842eb32b0aSMugunthan V N struct device_node *slave_node; 22852eb32b0aSMugunthan V N int i = 0, ret; 22862eb32b0aSMugunthan V N u32 prop; 22872eb32b0aSMugunthan V N 22882eb32b0aSMugunthan V N if (!node) 22892eb32b0aSMugunthan V N return -EINVAL; 22902eb32b0aSMugunthan V N 22912eb32b0aSMugunthan V N if (of_property_read_u32(node, "slaves", &prop)) { 229288c99ff6SGeorge Cherian dev_err(&pdev->dev, "Missing slaves property in the DT.\n"); 22932eb32b0aSMugunthan V N return -EINVAL; 22942eb32b0aSMugunthan V N } 22952eb32b0aSMugunthan V N data->slaves = prop; 22962eb32b0aSMugunthan V N 2297e86ac13bSMugunthan V N if (of_property_read_u32(node, "active_slave", &prop)) { 229888c99ff6SGeorge Cherian dev_err(&pdev->dev, "Missing active_slave property in the DT.\n"); 2299aa1a15e2SDaniel Mack return -EINVAL; 230078ca0b28SRichard Cochran } 2301e86ac13bSMugunthan V N data->active_slave = prop; 230278ca0b28SRichard Cochran 230300ab94eeSRichard Cochran if (of_property_read_u32(node, "cpts_clock_mult", &prop)) { 230488c99ff6SGeorge Cherian dev_err(&pdev->dev, "Missing cpts_clock_mult property in the DT.\n"); 2305aa1a15e2SDaniel Mack return -EINVAL; 230600ab94eeSRichard Cochran } 230700ab94eeSRichard Cochran data->cpts_clock_mult = prop; 230800ab94eeSRichard Cochran 230900ab94eeSRichard Cochran if (of_property_read_u32(node, "cpts_clock_shift", &prop)) { 231088c99ff6SGeorge Cherian dev_err(&pdev->dev, "Missing cpts_clock_shift property in the DT.\n"); 2311aa1a15e2SDaniel Mack return -EINVAL; 231200ab94eeSRichard Cochran } 231300ab94eeSRichard Cochran data->cpts_clock_shift = prop; 231400ab94eeSRichard Cochran 2315aa1a15e2SDaniel Mack data->slave_data = devm_kzalloc(&pdev->dev, data->slaves 2316aa1a15e2SDaniel Mack * sizeof(struct cpsw_slave_data), 2317b2adaca9SJoe Perches GFP_KERNEL); 2318b2adaca9SJoe Perches if (!data->slave_data) 2319aa1a15e2SDaniel Mack return -ENOMEM; 23202eb32b0aSMugunthan V N 23212eb32b0aSMugunthan V N if (of_property_read_u32(node, "cpdma_channels", &prop)) { 232288c99ff6SGeorge Cherian dev_err(&pdev->dev, "Missing cpdma_channels property in the DT.\n"); 2323aa1a15e2SDaniel Mack return -EINVAL; 23242eb32b0aSMugunthan V N } 23252eb32b0aSMugunthan V N data->channels = prop; 23262eb32b0aSMugunthan V N 23272eb32b0aSMugunthan V N if (of_property_read_u32(node, "ale_entries", &prop)) { 232888c99ff6SGeorge Cherian dev_err(&pdev->dev, "Missing ale_entries property in the DT.\n"); 2329aa1a15e2SDaniel Mack return -EINVAL; 23302eb32b0aSMugunthan V N } 23312eb32b0aSMugunthan V N data->ale_entries = prop; 23322eb32b0aSMugunthan V N 23332eb32b0aSMugunthan V N if (of_property_read_u32(node, "bd_ram_size", &prop)) { 233488c99ff6SGeorge Cherian dev_err(&pdev->dev, "Missing bd_ram_size property in the DT.\n"); 2335aa1a15e2SDaniel Mack return -EINVAL; 23362eb32b0aSMugunthan V N } 23372eb32b0aSMugunthan V N data->bd_ram_size = prop; 23382eb32b0aSMugunthan V N 23392eb32b0aSMugunthan V N if (of_property_read_u32(node, "mac_control", &prop)) { 234088c99ff6SGeorge Cherian dev_err(&pdev->dev, "Missing mac_control property in the DT.\n"); 2341aa1a15e2SDaniel Mack return -EINVAL; 23422eb32b0aSMugunthan V N } 23432eb32b0aSMugunthan V N data->mac_control = prop; 23442eb32b0aSMugunthan V N 2345281abd96SMarkus Pargmann if (of_property_read_bool(node, "dual_emac")) 2346281abd96SMarkus Pargmann data->dual_emac = 1; 2347d9ba8f9eSMugunthan V N 23481fb19aa7SVaibhav Hiremath /* 23491fb19aa7SVaibhav Hiremath * Populate all the child nodes here... 23501fb19aa7SVaibhav Hiremath */ 23511fb19aa7SVaibhav Hiremath ret = of_platform_populate(node, NULL, NULL, &pdev->dev); 23521fb19aa7SVaibhav Hiremath /* We do not want to force this, as in some cases may not have child */ 23531fb19aa7SVaibhav Hiremath if (ret) 235488c99ff6SGeorge Cherian dev_warn(&pdev->dev, "Doesn't have any child node\n"); 23551fb19aa7SVaibhav Hiremath 23568658aaf2SBen Hutchings for_each_available_child_of_node(node, slave_node) { 2357549985eeSRichard Cochran struct cpsw_slave_data *slave_data = data->slave_data + i; 2358549985eeSRichard Cochran const void *mac_addr = NULL; 2359549985eeSRichard Cochran int lenp; 2360549985eeSRichard Cochran const __be32 *parp; 2361549985eeSRichard Cochran 2362f468b10eSMarkus Pargmann /* This is no slave child node, continue */ 2363f468b10eSMarkus Pargmann if (strcmp(slave_node->name, "slave")) 2364f468b10eSMarkus Pargmann continue; 2365f468b10eSMarkus Pargmann 2366552165bcSDavid Rivshin slave_data->phy_node = of_parse_phandle(slave_node, 2367552165bcSDavid Rivshin "phy-handle", 0); 2368f1eea5c1SDavid Rivshin parp = of_get_property(slave_node, "phy_id", &lenp); 2369ae092b5bSDavid Rivshin if (slave_data->phy_node) { 2370ae092b5bSDavid Rivshin dev_dbg(&pdev->dev, 2371ae092b5bSDavid Rivshin "slave[%d] using phy-handle=\"%s\"\n", 2372ae092b5bSDavid Rivshin i, slave_data->phy_node->full_name); 2373ae092b5bSDavid Rivshin } else if (of_phy_is_fixed_link(slave_node)) { 2374dfc0a6d3SDavid Rivshin /* In the case of a fixed PHY, the DT node associated 2375dfc0a6d3SDavid Rivshin * to the PHY is the Ethernet MAC DT node. 2376dfc0a6d3SDavid Rivshin */ 23771f71e8c9SMarkus Brunner ret = of_phy_register_fixed_link(slave_node); 237823a09873SJohan Hovold if (ret) { 237923a09873SJohan Hovold if (ret != -EPROBE_DEFER) 238023a09873SJohan Hovold dev_err(&pdev->dev, "failed to register fixed-link phy: %d\n", ret); 23811f71e8c9SMarkus Brunner return ret; 238223a09873SJohan Hovold } 238306cd6d6eSDavid Rivshin slave_data->phy_node = of_node_get(slave_node); 2384f1eea5c1SDavid Rivshin } else if (parp) { 2385f1eea5c1SDavid Rivshin u32 phyid; 2386f1eea5c1SDavid Rivshin struct device_node *mdio_node; 2387f1eea5c1SDavid Rivshin struct platform_device *mdio; 2388f1eea5c1SDavid Rivshin 2389f1eea5c1SDavid Rivshin if (lenp != (sizeof(__be32) * 2)) { 2390f1eea5c1SDavid Rivshin dev_err(&pdev->dev, "Invalid slave[%d] phy_id property\n", i); 239147276fccSMugunthan V N goto no_phy_slave; 2392549985eeSRichard Cochran } 2393549985eeSRichard Cochran mdio_node = of_find_node_by_phandle(be32_to_cpup(parp)); 2394549985eeSRichard Cochran phyid = be32_to_cpup(parp+1); 2395549985eeSRichard Cochran mdio = of_find_device_by_node(mdio_node); 239660e71ab5SJohan Hovold of_node_put(mdio_node); 23976954cc1fSJohan Hovold if (!mdio) { 239856fdb2e0SMarkus Pargmann dev_err(&pdev->dev, "Missing mdio platform device\n"); 23996954cc1fSJohan Hovold return -EINVAL; 24006954cc1fSJohan Hovold } 2401549985eeSRichard Cochran snprintf(slave_data->phy_id, sizeof(slave_data->phy_id), 2402549985eeSRichard Cochran PHY_ID_FMT, mdio->name, phyid); 240386e1d5adSJohan Hovold put_device(&mdio->dev); 2404f1eea5c1SDavid Rivshin } else { 2405ae092b5bSDavid Rivshin dev_err(&pdev->dev, 2406ae092b5bSDavid Rivshin "No slave[%d] phy_id, phy-handle, or fixed-link property\n", 2407ae092b5bSDavid Rivshin i); 2408f1eea5c1SDavid Rivshin goto no_phy_slave; 2409f1eea5c1SDavid Rivshin } 241047276fccSMugunthan V N slave_data->phy_if = of_get_phy_mode(slave_node); 241147276fccSMugunthan V N if (slave_data->phy_if < 0) { 241247276fccSMugunthan V N dev_err(&pdev->dev, "Missing or malformed slave[%d] phy-mode property\n", 241347276fccSMugunthan V N i); 241447276fccSMugunthan V N return slave_data->phy_if; 241547276fccSMugunthan V N } 241647276fccSMugunthan V N 241747276fccSMugunthan V N no_phy_slave: 2418549985eeSRichard Cochran mac_addr = of_get_mac_address(slave_node); 24190ba517b1SMarkus Pargmann if (mac_addr) { 2420549985eeSRichard Cochran memcpy(slave_data->mac_addr, mac_addr, ETH_ALEN); 24210ba517b1SMarkus Pargmann } else { 2422b6745f6eSMugunthan V N ret = ti_cm_get_macid(&pdev->dev, i, 24230ba517b1SMarkus Pargmann slave_data->mac_addr); 24240ba517b1SMarkus Pargmann if (ret) 24250ba517b1SMarkus Pargmann return ret; 24260ba517b1SMarkus Pargmann } 2427d9ba8f9eSMugunthan V N if (data->dual_emac) { 242891c4166cSMugunthan V N if (of_property_read_u32(slave_node, "dual_emac_res_vlan", 2429d9ba8f9eSMugunthan V N &prop)) { 243088c99ff6SGeorge Cherian dev_err(&pdev->dev, "Missing dual_emac_res_vlan in DT.\n"); 2431d9ba8f9eSMugunthan V N slave_data->dual_emac_res_vlan = i+1; 243288c99ff6SGeorge Cherian dev_err(&pdev->dev, "Using %d as Reserved VLAN for %d slave\n", 2433d9ba8f9eSMugunthan V N slave_data->dual_emac_res_vlan, i); 2434d9ba8f9eSMugunthan V N } else { 2435d9ba8f9eSMugunthan V N slave_data->dual_emac_res_vlan = prop; 2436d9ba8f9eSMugunthan V N } 2437d9ba8f9eSMugunthan V N } 2438d9ba8f9eSMugunthan V N 2439549985eeSRichard Cochran i++; 24403a27bfacSMugunthan V N if (i == data->slaves) 24413a27bfacSMugunthan V N break; 2442549985eeSRichard Cochran } 2443549985eeSRichard Cochran 24442eb32b0aSMugunthan V N return 0; 24452eb32b0aSMugunthan V N } 24462eb32b0aSMugunthan V N 2447a4e32b0dSJohan Hovold static void cpsw_remove_dt(struct platform_device *pdev) 2448a4e32b0dSJohan Hovold { 24498cbcc466SJohan Hovold struct net_device *ndev = platform_get_drvdata(pdev); 24508cbcc466SJohan Hovold struct cpsw_common *cpsw = ndev_to_cpsw(ndev); 24518cbcc466SJohan Hovold struct cpsw_platform_data *data = &cpsw->data; 24528cbcc466SJohan Hovold struct device_node *node = pdev->dev.of_node; 24538cbcc466SJohan Hovold struct device_node *slave_node; 24548cbcc466SJohan Hovold int i = 0; 24558cbcc466SJohan Hovold 24568cbcc466SJohan Hovold for_each_available_child_of_node(node, slave_node) { 24578cbcc466SJohan Hovold struct cpsw_slave_data *slave_data = &data->slave_data[i]; 24588cbcc466SJohan Hovold 24598cbcc466SJohan Hovold if (strcmp(slave_node->name, "slave")) 24608cbcc466SJohan Hovold continue; 24618cbcc466SJohan Hovold 24628cbcc466SJohan Hovold if (of_phy_is_fixed_link(slave_node)) { 24638cbcc466SJohan Hovold struct phy_device *phydev; 24648cbcc466SJohan Hovold 24658cbcc466SJohan Hovold phydev = of_phy_find_device(slave_node); 24668cbcc466SJohan Hovold if (phydev) { 24678cbcc466SJohan Hovold fixed_phy_unregister(phydev); 24688cbcc466SJohan Hovold /* Put references taken by 24698cbcc466SJohan Hovold * of_phy_find_device() and 24708cbcc466SJohan Hovold * of_phy_register_fixed_link(). 24718cbcc466SJohan Hovold */ 24728cbcc466SJohan Hovold phy_device_free(phydev); 24738cbcc466SJohan Hovold phy_device_free(phydev); 24748cbcc466SJohan Hovold } 24758cbcc466SJohan Hovold } 24768cbcc466SJohan Hovold 24778cbcc466SJohan Hovold of_node_put(slave_data->phy_node); 24788cbcc466SJohan Hovold 24798cbcc466SJohan Hovold i++; 24808cbcc466SJohan Hovold if (i == data->slaves) 24818cbcc466SJohan Hovold break; 24828cbcc466SJohan Hovold } 24838cbcc466SJohan Hovold 2484a4e32b0dSJohan Hovold of_platform_depopulate(&pdev->dev); 2485a4e32b0dSJohan Hovold } 2486a4e32b0dSJohan Hovold 248756e31bd8SIvan Khoronzhuk static int cpsw_probe_dual_emac(struct cpsw_priv *priv) 2488d9ba8f9eSMugunthan V N { 2489606f3993SIvan Khoronzhuk struct cpsw_common *cpsw = priv->cpsw; 2490606f3993SIvan Khoronzhuk struct cpsw_platform_data *data = &cpsw->data; 2491d9ba8f9eSMugunthan V N struct net_device *ndev; 2492d9ba8f9eSMugunthan V N struct cpsw_priv *priv_sl2; 2493e38b5a3dSIvan Khoronzhuk int ret = 0; 2494d9ba8f9eSMugunthan V N 2495e05107e6SIvan Khoronzhuk ndev = alloc_etherdev_mq(sizeof(struct cpsw_priv), CPSW_MAX_QUEUES); 2496d9ba8f9eSMugunthan V N if (!ndev) { 249756e31bd8SIvan Khoronzhuk dev_err(cpsw->dev, "cpsw: error allocating net_device\n"); 2498d9ba8f9eSMugunthan V N return -ENOMEM; 2499d9ba8f9eSMugunthan V N } 2500d9ba8f9eSMugunthan V N 2501d9ba8f9eSMugunthan V N priv_sl2 = netdev_priv(ndev); 2502606f3993SIvan Khoronzhuk priv_sl2->cpsw = cpsw; 2503d9ba8f9eSMugunthan V N priv_sl2->ndev = ndev; 2504d9ba8f9eSMugunthan V N priv_sl2->dev = &ndev->dev; 2505d9ba8f9eSMugunthan V N priv_sl2->msg_enable = netif_msg_init(debug_level, CPSW_DEBUG); 2506d9ba8f9eSMugunthan V N 2507d9ba8f9eSMugunthan V N if (is_valid_ether_addr(data->slave_data[1].mac_addr)) { 2508d9ba8f9eSMugunthan V N memcpy(priv_sl2->mac_addr, data->slave_data[1].mac_addr, 2509d9ba8f9eSMugunthan V N ETH_ALEN); 251056e31bd8SIvan Khoronzhuk dev_info(cpsw->dev, "cpsw: Detected MACID = %pM\n", 251156e31bd8SIvan Khoronzhuk priv_sl2->mac_addr); 2512d9ba8f9eSMugunthan V N } else { 2513d9ba8f9eSMugunthan V N random_ether_addr(priv_sl2->mac_addr); 251456e31bd8SIvan Khoronzhuk dev_info(cpsw->dev, "cpsw: Random MACID = %pM\n", 251556e31bd8SIvan Khoronzhuk priv_sl2->mac_addr); 2516d9ba8f9eSMugunthan V N } 2517d9ba8f9eSMugunthan V N memcpy(ndev->dev_addr, priv_sl2->mac_addr, ETH_ALEN); 2518d9ba8f9eSMugunthan V N 2519d9ba8f9eSMugunthan V N priv_sl2->emac_port = 1; 2520606f3993SIvan Khoronzhuk cpsw->slaves[1].ndev = ndev; 2521f646968fSPatrick McHardy ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER; 2522d9ba8f9eSMugunthan V N 2523d9ba8f9eSMugunthan V N ndev->netdev_ops = &cpsw_netdev_ops; 25247ad24ea4SWilfried Klaebe ndev->ethtool_ops = &cpsw_ethtool_ops; 2525d9ba8f9eSMugunthan V N 2526d9ba8f9eSMugunthan V N /* register the network device */ 252756e31bd8SIvan Khoronzhuk SET_NETDEV_DEV(ndev, cpsw->dev); 2528d9ba8f9eSMugunthan V N ret = register_netdev(ndev); 2529d9ba8f9eSMugunthan V N if (ret) { 253056e31bd8SIvan Khoronzhuk dev_err(cpsw->dev, "cpsw: error registering net device\n"); 2531d9ba8f9eSMugunthan V N free_netdev(ndev); 2532d9ba8f9eSMugunthan V N ret = -ENODEV; 2533d9ba8f9eSMugunthan V N } 2534d9ba8f9eSMugunthan V N 2535d9ba8f9eSMugunthan V N return ret; 2536d9ba8f9eSMugunthan V N } 2537d9ba8f9eSMugunthan V N 25387da11600SMugunthan V N #define CPSW_QUIRK_IRQ BIT(0) 25397da11600SMugunthan V N 25407da11600SMugunthan V N static struct platform_device_id cpsw_devtype[] = { 25417da11600SMugunthan V N { 25427da11600SMugunthan V N /* keep it for existing comaptibles */ 25437da11600SMugunthan V N .name = "cpsw", 25447da11600SMugunthan V N .driver_data = CPSW_QUIRK_IRQ, 25457da11600SMugunthan V N }, { 25467da11600SMugunthan V N .name = "am335x-cpsw", 25477da11600SMugunthan V N .driver_data = CPSW_QUIRK_IRQ, 25487da11600SMugunthan V N }, { 25497da11600SMugunthan V N .name = "am4372-cpsw", 25507da11600SMugunthan V N .driver_data = 0, 25517da11600SMugunthan V N }, { 25527da11600SMugunthan V N .name = "dra7-cpsw", 25537da11600SMugunthan V N .driver_data = 0, 25547da11600SMugunthan V N }, { 25557da11600SMugunthan V N /* sentinel */ 25567da11600SMugunthan V N } 25577da11600SMugunthan V N }; 25587da11600SMugunthan V N MODULE_DEVICE_TABLE(platform, cpsw_devtype); 25597da11600SMugunthan V N 25607da11600SMugunthan V N enum ti_cpsw_type { 25617da11600SMugunthan V N CPSW = 0, 25627da11600SMugunthan V N AM335X_CPSW, 25637da11600SMugunthan V N AM4372_CPSW, 25647da11600SMugunthan V N DRA7_CPSW, 25657da11600SMugunthan V N }; 25667da11600SMugunthan V N 25677da11600SMugunthan V N static const struct of_device_id cpsw_of_mtable[] = { 25687da11600SMugunthan V N { .compatible = "ti,cpsw", .data = &cpsw_devtype[CPSW], }, 25697da11600SMugunthan V N { .compatible = "ti,am335x-cpsw", .data = &cpsw_devtype[AM335X_CPSW], }, 25707da11600SMugunthan V N { .compatible = "ti,am4372-cpsw", .data = &cpsw_devtype[AM4372_CPSW], }, 25717da11600SMugunthan V N { .compatible = "ti,dra7-cpsw", .data = &cpsw_devtype[DRA7_CPSW], }, 25727da11600SMugunthan V N { /* sentinel */ }, 25737da11600SMugunthan V N }; 25747da11600SMugunthan V N MODULE_DEVICE_TABLE(of, cpsw_of_mtable); 25757da11600SMugunthan V N 2576663e12e6SBill Pemberton static int cpsw_probe(struct platform_device *pdev) 2577df828598SMugunthan V N { 2578ef4183a1SIvan Khoronzhuk struct clk *clk; 2579d1bd9acfSSebastian Siewior struct cpsw_platform_data *data; 2580df828598SMugunthan V N struct net_device *ndev; 2581df828598SMugunthan V N struct cpsw_priv *priv; 2582df828598SMugunthan V N struct cpdma_params dma_params; 2583df828598SMugunthan V N struct cpsw_ale_params ale_params; 2584aa1a15e2SDaniel Mack void __iomem *ss_regs; 2585aa1a15e2SDaniel Mack struct resource *res, *ss_res; 25867da11600SMugunthan V N const struct of_device_id *of_id; 25871d147ccbSMugunthan V N struct gpio_descs *mode; 2588549985eeSRichard Cochran u32 slave_offset, sliver_offset, slave_size; 2589649a1688SIvan Khoronzhuk struct cpsw_common *cpsw; 25905087b915SFelipe Balbi int ret = 0, i; 25915087b915SFelipe Balbi int irq; 2592df828598SMugunthan V N 2593649a1688SIvan Khoronzhuk cpsw = devm_kzalloc(&pdev->dev, sizeof(struct cpsw_common), GFP_KERNEL); 25943420ea88SJohan Hovold if (!cpsw) 25953420ea88SJohan Hovold return -ENOMEM; 25963420ea88SJohan Hovold 259756e31bd8SIvan Khoronzhuk cpsw->dev = &pdev->dev; 2598649a1688SIvan Khoronzhuk 2599e05107e6SIvan Khoronzhuk ndev = alloc_etherdev_mq(sizeof(struct cpsw_priv), CPSW_MAX_QUEUES); 2600df828598SMugunthan V N if (!ndev) { 260188c99ff6SGeorge Cherian dev_err(&pdev->dev, "error allocating net_device\n"); 2602df828598SMugunthan V N return -ENOMEM; 2603df828598SMugunthan V N } 2604df828598SMugunthan V N 2605df828598SMugunthan V N platform_set_drvdata(pdev, ndev); 2606df828598SMugunthan V N priv = netdev_priv(ndev); 2607649a1688SIvan Khoronzhuk priv->cpsw = cpsw; 2608df828598SMugunthan V N priv->ndev = ndev; 2609df828598SMugunthan V N priv->dev = &ndev->dev; 2610df828598SMugunthan V N priv->msg_enable = netif_msg_init(debug_level, CPSW_DEBUG); 26112a05a622SIvan Khoronzhuk cpsw->rx_packet_max = max(rx_packet_max, 128); 26122a05a622SIvan Khoronzhuk cpsw->cpts = devm_kzalloc(&pdev->dev, sizeof(struct cpts), GFP_KERNEL); 26132a05a622SIvan Khoronzhuk if (!cpsw->cpts) { 261488c99ff6SGeorge Cherian dev_err(&pdev->dev, "error allocating cpts\n"); 26154d507dffSMarkus Pargmann ret = -ENOMEM; 26169232b16dSMugunthan V N goto clean_ndev_ret; 26179232b16dSMugunthan V N } 2618df828598SMugunthan V N 26191d147ccbSMugunthan V N mode = devm_gpiod_get_array_optional(&pdev->dev, "mode", GPIOD_OUT_LOW); 26201d147ccbSMugunthan V N if (IS_ERR(mode)) { 26211d147ccbSMugunthan V N ret = PTR_ERR(mode); 26221d147ccbSMugunthan V N dev_err(&pdev->dev, "gpio request failed, ret %d\n", ret); 26231d147ccbSMugunthan V N goto clean_ndev_ret; 26241d147ccbSMugunthan V N } 26251d147ccbSMugunthan V N 26261fb19aa7SVaibhav Hiremath /* 26271fb19aa7SVaibhav Hiremath * This may be required here for child devices. 26281fb19aa7SVaibhav Hiremath */ 26291fb19aa7SVaibhav Hiremath pm_runtime_enable(&pdev->dev); 26301fb19aa7SVaibhav Hiremath 2631739683b4SMugunthan V N /* Select default pin state */ 2632739683b4SMugunthan V N pinctrl_pm_select_default_state(&pdev->dev); 2633739683b4SMugunthan V N 2634a4e32b0dSJohan Hovold /* Need to enable clocks with runtime PM api to access module 2635a4e32b0dSJohan Hovold * registers 2636a4e32b0dSJohan Hovold */ 2637a4e32b0dSJohan Hovold ret = pm_runtime_get_sync(&pdev->dev); 2638a4e32b0dSJohan Hovold if (ret < 0) { 2639a4e32b0dSJohan Hovold pm_runtime_put_noidle(&pdev->dev); 2640a4e32b0dSJohan Hovold goto clean_runtime_disable_ret; 2641a4e32b0dSJohan Hovold } 2642a4e32b0dSJohan Hovold 264323a09873SJohan Hovold ret = cpsw_probe_dt(&cpsw->data, pdev); 264423a09873SJohan Hovold if (ret) 2645a4e32b0dSJohan Hovold goto clean_dt_ret; 264623a09873SJohan Hovold 2647606f3993SIvan Khoronzhuk data = &cpsw->data; 2648e05107e6SIvan Khoronzhuk cpsw->rx_ch_num = 1; 2649e05107e6SIvan Khoronzhuk cpsw->tx_ch_num = 1; 26502eb32b0aSMugunthan V N 2651df828598SMugunthan V N if (is_valid_ether_addr(data->slave_data[0].mac_addr)) { 2652df828598SMugunthan V N memcpy(priv->mac_addr, data->slave_data[0].mac_addr, ETH_ALEN); 265388c99ff6SGeorge Cherian dev_info(&pdev->dev, "Detected MACID = %pM\n", priv->mac_addr); 2654df828598SMugunthan V N } else { 26557efd26d0SJoe Perches eth_random_addr(priv->mac_addr); 265688c99ff6SGeorge Cherian dev_info(&pdev->dev, "Random MACID = %pM\n", priv->mac_addr); 2657df828598SMugunthan V N } 2658df828598SMugunthan V N 2659df828598SMugunthan V N memcpy(ndev->dev_addr, priv->mac_addr, ETH_ALEN); 2660df828598SMugunthan V N 2661606f3993SIvan Khoronzhuk cpsw->slaves = devm_kzalloc(&pdev->dev, 2662aa1a15e2SDaniel Mack sizeof(struct cpsw_slave) * data->slaves, 2663df828598SMugunthan V N GFP_KERNEL); 2664606f3993SIvan Khoronzhuk if (!cpsw->slaves) { 2665aa1a15e2SDaniel Mack ret = -ENOMEM; 2666a4e32b0dSJohan Hovold goto clean_dt_ret; 2667df828598SMugunthan V N } 2668df828598SMugunthan V N for (i = 0; i < data->slaves; i++) 2669606f3993SIvan Khoronzhuk cpsw->slaves[i].slave_num = i; 2670df828598SMugunthan V N 2671606f3993SIvan Khoronzhuk cpsw->slaves[0].ndev = ndev; 2672d9ba8f9eSMugunthan V N priv->emac_port = 0; 2673d9ba8f9eSMugunthan V N 2674ef4183a1SIvan Khoronzhuk clk = devm_clk_get(&pdev->dev, "fck"); 2675ef4183a1SIvan Khoronzhuk if (IS_ERR(clk)) { 2676aa1a15e2SDaniel Mack dev_err(priv->dev, "fck is not found\n"); 2677f150bd7fSMugunthan V N ret = -ENODEV; 2678a4e32b0dSJohan Hovold goto clean_dt_ret; 2679df828598SMugunthan V N } 26802a05a622SIvan Khoronzhuk cpsw->bus_freq_mhz = clk_get_rate(clk) / 1000000; 2681df828598SMugunthan V N 2682aa1a15e2SDaniel Mack ss_res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2683aa1a15e2SDaniel Mack ss_regs = devm_ioremap_resource(&pdev->dev, ss_res); 2684aa1a15e2SDaniel Mack if (IS_ERR(ss_regs)) { 2685aa1a15e2SDaniel Mack ret = PTR_ERR(ss_regs); 2686a4e32b0dSJohan Hovold goto clean_dt_ret; 2687df828598SMugunthan V N } 26885d8d0d4dSIvan Khoronzhuk cpsw->regs = ss_regs; 2689df828598SMugunthan V N 26902a05a622SIvan Khoronzhuk cpsw->version = readl(&cpsw->regs->id_ver); 2691f280e89aSMugunthan V N 2692aa1a15e2SDaniel Mack res = platform_get_resource(pdev, IORESOURCE_MEM, 1); 26935d8d0d4dSIvan Khoronzhuk cpsw->wr_regs = devm_ioremap_resource(&pdev->dev, res); 26945d8d0d4dSIvan Khoronzhuk if (IS_ERR(cpsw->wr_regs)) { 26955d8d0d4dSIvan Khoronzhuk ret = PTR_ERR(cpsw->wr_regs); 2696a4e32b0dSJohan Hovold goto clean_dt_ret; 2697df828598SMugunthan V N } 2698df828598SMugunthan V N 2699df828598SMugunthan V N memset(&dma_params, 0, sizeof(dma_params)); 2700549985eeSRichard Cochran memset(&ale_params, 0, sizeof(ale_params)); 2701549985eeSRichard Cochran 27022a05a622SIvan Khoronzhuk switch (cpsw->version) { 2703549985eeSRichard Cochran case CPSW_VERSION_1: 27045d8d0d4dSIvan Khoronzhuk cpsw->host_port_regs = ss_regs + CPSW1_HOST_PORT_OFFSET; 27052a05a622SIvan Khoronzhuk cpsw->cpts->reg = ss_regs + CPSW1_CPTS_OFFSET; 27065d8d0d4dSIvan Khoronzhuk cpsw->hw_stats = ss_regs + CPSW1_HW_STATS; 2707549985eeSRichard Cochran dma_params.dmaregs = ss_regs + CPSW1_CPDMA_OFFSET; 2708549985eeSRichard Cochran dma_params.txhdp = ss_regs + CPSW1_STATERAM_OFFSET; 2709549985eeSRichard Cochran ale_params.ale_regs = ss_regs + CPSW1_ALE_OFFSET; 2710549985eeSRichard Cochran slave_offset = CPSW1_SLAVE_OFFSET; 2711549985eeSRichard Cochran slave_size = CPSW1_SLAVE_SIZE; 2712549985eeSRichard Cochran sliver_offset = CPSW1_SLIVER_OFFSET; 2713549985eeSRichard Cochran dma_params.desc_mem_phys = 0; 2714549985eeSRichard Cochran break; 2715549985eeSRichard Cochran case CPSW_VERSION_2: 2716c193f365SMugunthan V N case CPSW_VERSION_3: 2717926489beSMugunthan V N case CPSW_VERSION_4: 27185d8d0d4dSIvan Khoronzhuk cpsw->host_port_regs = ss_regs + CPSW2_HOST_PORT_OFFSET; 27192a05a622SIvan Khoronzhuk cpsw->cpts->reg = ss_regs + CPSW2_CPTS_OFFSET; 27205d8d0d4dSIvan Khoronzhuk cpsw->hw_stats = ss_regs + CPSW2_HW_STATS; 2721549985eeSRichard Cochran dma_params.dmaregs = ss_regs + CPSW2_CPDMA_OFFSET; 2722549985eeSRichard Cochran dma_params.txhdp = ss_regs + CPSW2_STATERAM_OFFSET; 2723549985eeSRichard Cochran ale_params.ale_regs = ss_regs + CPSW2_ALE_OFFSET; 2724549985eeSRichard Cochran slave_offset = CPSW2_SLAVE_OFFSET; 2725549985eeSRichard Cochran slave_size = CPSW2_SLAVE_SIZE; 2726549985eeSRichard Cochran sliver_offset = CPSW2_SLIVER_OFFSET; 2727549985eeSRichard Cochran dma_params.desc_mem_phys = 2728aa1a15e2SDaniel Mack (u32 __force) ss_res->start + CPSW2_BD_OFFSET; 2729549985eeSRichard Cochran break; 2730549985eeSRichard Cochran default: 27312a05a622SIvan Khoronzhuk dev_err(priv->dev, "unknown version 0x%08x\n", cpsw->version); 2732549985eeSRichard Cochran ret = -ENODEV; 2733a4e32b0dSJohan Hovold goto clean_dt_ret; 2734549985eeSRichard Cochran } 2735606f3993SIvan Khoronzhuk for (i = 0; i < cpsw->data.slaves; i++) { 2736606f3993SIvan Khoronzhuk struct cpsw_slave *slave = &cpsw->slaves[i]; 2737606f3993SIvan Khoronzhuk 2738606f3993SIvan Khoronzhuk cpsw_slave_init(slave, cpsw, slave_offset, sliver_offset); 2739549985eeSRichard Cochran slave_offset += slave_size; 2740549985eeSRichard Cochran sliver_offset += SLIVER_SIZE; 2741549985eeSRichard Cochran } 2742549985eeSRichard Cochran 2743df828598SMugunthan V N dma_params.dev = &pdev->dev; 2744549985eeSRichard Cochran dma_params.rxthresh = dma_params.dmaregs + CPDMA_RXTHRESH; 2745549985eeSRichard Cochran dma_params.rxfree = dma_params.dmaregs + CPDMA_RXFREE; 2746549985eeSRichard Cochran dma_params.rxhdp = dma_params.txhdp + CPDMA_RXHDP; 2747549985eeSRichard Cochran dma_params.txcp = dma_params.txhdp + CPDMA_TXCP; 2748549985eeSRichard Cochran dma_params.rxcp = dma_params.txhdp + CPDMA_RXCP; 2749df828598SMugunthan V N 2750df828598SMugunthan V N dma_params.num_chan = data->channels; 2751df828598SMugunthan V N dma_params.has_soft_reset = true; 2752df828598SMugunthan V N dma_params.min_packet_size = CPSW_MIN_PACKET_SIZE; 2753df828598SMugunthan V N dma_params.desc_mem_size = data->bd_ram_size; 2754df828598SMugunthan V N dma_params.desc_align = 16; 2755df828598SMugunthan V N dma_params.has_ext_regs = true; 2756549985eeSRichard Cochran dma_params.desc_hw_addr = dma_params.desc_mem_phys; 2757df828598SMugunthan V N 27582c836bd9SIvan Khoronzhuk cpsw->dma = cpdma_ctlr_create(&dma_params); 27592c836bd9SIvan Khoronzhuk if (!cpsw->dma) { 2760df828598SMugunthan V N dev_err(priv->dev, "error initializing dma\n"); 2761df828598SMugunthan V N ret = -ENOMEM; 2762a4e32b0dSJohan Hovold goto clean_dt_ret; 2763df828598SMugunthan V N } 2764df828598SMugunthan V N 2765925d65e6SIvan Khoronzhuk cpsw->txch[0] = cpdma_chan_create(cpsw->dma, 0, cpsw_tx_handler, 0); 2766925d65e6SIvan Khoronzhuk cpsw->rxch[0] = cpdma_chan_create(cpsw->dma, 0, cpsw_rx_handler, 1); 2767e05107e6SIvan Khoronzhuk if (WARN_ON(!cpsw->rxch[0] || !cpsw->txch[0])) { 2768df828598SMugunthan V N dev_err(priv->dev, "error initializing dma channels\n"); 2769df828598SMugunthan V N ret = -ENOMEM; 2770df828598SMugunthan V N goto clean_dma_ret; 2771df828598SMugunthan V N } 2772df828598SMugunthan V N 2773df828598SMugunthan V N ale_params.dev = &ndev->dev; 2774df828598SMugunthan V N ale_params.ale_ageout = ale_ageout; 2775df828598SMugunthan V N ale_params.ale_entries = data->ale_entries; 2776df828598SMugunthan V N ale_params.ale_ports = data->slaves; 2777df828598SMugunthan V N 27782a05a622SIvan Khoronzhuk cpsw->ale = cpsw_ale_create(&ale_params); 27792a05a622SIvan Khoronzhuk if (!cpsw->ale) { 2780df828598SMugunthan V N dev_err(priv->dev, "error initializing ale engine\n"); 2781df828598SMugunthan V N ret = -ENODEV; 2782df828598SMugunthan V N goto clean_dma_ret; 2783df828598SMugunthan V N } 2784df828598SMugunthan V N 2785c03abd84SFelipe Balbi ndev->irq = platform_get_irq(pdev, 1); 2786df828598SMugunthan V N if (ndev->irq < 0) { 2787df828598SMugunthan V N dev_err(priv->dev, "error getting irq resource\n"); 2788c1e3334fSJulia Lawall ret = ndev->irq; 2789df828598SMugunthan V N goto clean_ale_ret; 2790df828598SMugunthan V N } 2791df828598SMugunthan V N 27927da11600SMugunthan V N of_id = of_match_device(cpsw_of_mtable, &pdev->dev); 27937da11600SMugunthan V N if (of_id) { 27947da11600SMugunthan V N pdev->id_entry = of_id->data; 27957da11600SMugunthan V N if (pdev->id_entry->driver_data) 2796e38b5a3dSIvan Khoronzhuk cpsw->quirk_irq = true; 27977da11600SMugunthan V N } 27987da11600SMugunthan V N 2799c03abd84SFelipe Balbi /* Grab RX and TX IRQs. Note that we also have RX_THRESHOLD and 2800c03abd84SFelipe Balbi * MISC IRQs which are always kept disabled with this driver so 2801c03abd84SFelipe Balbi * we will not request them. 2802c03abd84SFelipe Balbi * 2803c03abd84SFelipe Balbi * If anyone wants to implement support for those, make sure to 2804c03abd84SFelipe Balbi * first request and append them to irqs_table array. 2805c03abd84SFelipe Balbi */ 2806c2b32e58SDaniel Mack 2807c03abd84SFelipe Balbi /* RX IRQ */ 28085087b915SFelipe Balbi irq = platform_get_irq(pdev, 1); 2809c1e3334fSJulia Lawall if (irq < 0) { 2810c1e3334fSJulia Lawall ret = irq; 28115087b915SFelipe Balbi goto clean_ale_ret; 2812c1e3334fSJulia Lawall } 28135087b915SFelipe Balbi 2814e38b5a3dSIvan Khoronzhuk cpsw->irqs_table[0] = irq; 2815c03abd84SFelipe Balbi ret = devm_request_irq(&pdev->dev, irq, cpsw_rx_interrupt, 2816dbc4ec52SIvan Khoronzhuk 0, dev_name(&pdev->dev), cpsw); 28175087b915SFelipe Balbi if (ret < 0) { 28185087b915SFelipe Balbi dev_err(priv->dev, "error attaching irq (%d)\n", ret); 28195087b915SFelipe Balbi goto clean_ale_ret; 2820df828598SMugunthan V N } 2821df828598SMugunthan V N 2822c03abd84SFelipe Balbi /* TX IRQ */ 28235087b915SFelipe Balbi irq = platform_get_irq(pdev, 2); 2824c1e3334fSJulia Lawall if (irq < 0) { 2825c1e3334fSJulia Lawall ret = irq; 28265087b915SFelipe Balbi goto clean_ale_ret; 2827c1e3334fSJulia Lawall } 28285087b915SFelipe Balbi 2829e38b5a3dSIvan Khoronzhuk cpsw->irqs_table[1] = irq; 2830c03abd84SFelipe Balbi ret = devm_request_irq(&pdev->dev, irq, cpsw_tx_interrupt, 2831dbc4ec52SIvan Khoronzhuk 0, dev_name(&pdev->dev), cpsw); 28325087b915SFelipe Balbi if (ret < 0) { 28335087b915SFelipe Balbi dev_err(priv->dev, "error attaching irq (%d)\n", ret); 28345087b915SFelipe Balbi goto clean_ale_ret; 28355087b915SFelipe Balbi } 2836c2b32e58SDaniel Mack 2837f646968fSPatrick McHardy ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER; 2838df828598SMugunthan V N 2839df828598SMugunthan V N ndev->netdev_ops = &cpsw_netdev_ops; 28407ad24ea4SWilfried Klaebe ndev->ethtool_ops = &cpsw_ethtool_ops; 2841dbc4ec52SIvan Khoronzhuk netif_napi_add(ndev, &cpsw->napi_rx, cpsw_rx_poll, CPSW_POLL_WEIGHT); 2842dbc4ec52SIvan Khoronzhuk netif_tx_napi_add(ndev, &cpsw->napi_tx, cpsw_tx_poll, CPSW_POLL_WEIGHT); 2843df828598SMugunthan V N 2844df828598SMugunthan V N /* register the network device */ 2845df828598SMugunthan V N SET_NETDEV_DEV(ndev, &pdev->dev); 2846df828598SMugunthan V N ret = register_netdev(ndev); 2847df828598SMugunthan V N if (ret) { 2848df828598SMugunthan V N dev_err(priv->dev, "error registering net device\n"); 2849df828598SMugunthan V N ret = -ENODEV; 2850aa1a15e2SDaniel Mack goto clean_ale_ret; 2851df828598SMugunthan V N } 2852df828598SMugunthan V N 28531a3b5056SOlof Johansson cpsw_notice(priv, probe, "initialized device (regs %pa, irq %d)\n", 28541a3b5056SOlof Johansson &ss_res->start, ndev->irq); 2855df828598SMugunthan V N 2856606f3993SIvan Khoronzhuk if (cpsw->data.dual_emac) { 285756e31bd8SIvan Khoronzhuk ret = cpsw_probe_dual_emac(priv); 2858d9ba8f9eSMugunthan V N if (ret) { 2859d9ba8f9eSMugunthan V N cpsw_err(priv, probe, "error probe slave 2 emac interface\n"); 2860a7fe9d46SJohan Hovold goto clean_unregister_netdev_ret; 2861d9ba8f9eSMugunthan V N } 2862d9ba8f9eSMugunthan V N } 2863d9ba8f9eSMugunthan V N 2864c46ab7e0SJohan Hovold pm_runtime_put(&pdev->dev); 2865c46ab7e0SJohan Hovold 2866df828598SMugunthan V N return 0; 2867df828598SMugunthan V N 2868a7fe9d46SJohan Hovold clean_unregister_netdev_ret: 2869a7fe9d46SJohan Hovold unregister_netdev(ndev); 2870df828598SMugunthan V N clean_ale_ret: 28712a05a622SIvan Khoronzhuk cpsw_ale_destroy(cpsw->ale); 2872df828598SMugunthan V N clean_dma_ret: 28732c836bd9SIvan Khoronzhuk cpdma_ctlr_destroy(cpsw->dma); 2874a4e32b0dSJohan Hovold clean_dt_ret: 2875a4e32b0dSJohan Hovold cpsw_remove_dt(pdev); 2876c46ab7e0SJohan Hovold pm_runtime_put_sync(&pdev->dev); 2877aa1a15e2SDaniel Mack clean_runtime_disable_ret: 2878f150bd7fSMugunthan V N pm_runtime_disable(&pdev->dev); 2879df828598SMugunthan V N clean_ndev_ret: 2880d1bd9acfSSebastian Siewior free_netdev(priv->ndev); 2881df828598SMugunthan V N return ret; 2882df828598SMugunthan V N } 2883df828598SMugunthan V N 2884663e12e6SBill Pemberton static int cpsw_remove(struct platform_device *pdev) 2885df828598SMugunthan V N { 2886df828598SMugunthan V N struct net_device *ndev = platform_get_drvdata(pdev); 28872a05a622SIvan Khoronzhuk struct cpsw_common *cpsw = ndev_to_cpsw(ndev); 28888a0b6dc9SGrygorii Strashko int ret; 28898a0b6dc9SGrygorii Strashko 28908a0b6dc9SGrygorii Strashko ret = pm_runtime_get_sync(&pdev->dev); 28918a0b6dc9SGrygorii Strashko if (ret < 0) { 28928a0b6dc9SGrygorii Strashko pm_runtime_put_noidle(&pdev->dev); 28938a0b6dc9SGrygorii Strashko return ret; 28948a0b6dc9SGrygorii Strashko } 2895df828598SMugunthan V N 2896606f3993SIvan Khoronzhuk if (cpsw->data.dual_emac) 2897606f3993SIvan Khoronzhuk unregister_netdev(cpsw->slaves[1].ndev); 2898d1bd9acfSSebastian Siewior unregister_netdev(ndev); 2899df828598SMugunthan V N 29002a05a622SIvan Khoronzhuk cpsw_ale_destroy(cpsw->ale); 29012c836bd9SIvan Khoronzhuk cpdma_ctlr_destroy(cpsw->dma); 2902a4e32b0dSJohan Hovold cpsw_remove_dt(pdev); 29038a0b6dc9SGrygorii Strashko pm_runtime_put_sync(&pdev->dev); 29048a0b6dc9SGrygorii Strashko pm_runtime_disable(&pdev->dev); 2905606f3993SIvan Khoronzhuk if (cpsw->data.dual_emac) 2906606f3993SIvan Khoronzhuk free_netdev(cpsw->slaves[1].ndev); 2907df828598SMugunthan V N free_netdev(ndev); 2908df828598SMugunthan V N return 0; 2909df828598SMugunthan V N } 2910df828598SMugunthan V N 29118963a504SGrygorii Strashko #ifdef CONFIG_PM_SLEEP 2912df828598SMugunthan V N static int cpsw_suspend(struct device *dev) 2913df828598SMugunthan V N { 2914df828598SMugunthan V N struct platform_device *pdev = to_platform_device(dev); 2915df828598SMugunthan V N struct net_device *ndev = platform_get_drvdata(pdev); 2916606f3993SIvan Khoronzhuk struct cpsw_common *cpsw = ndev_to_cpsw(ndev); 2917df828598SMugunthan V N 2918606f3993SIvan Khoronzhuk if (cpsw->data.dual_emac) { 2919618073e3SMugunthan V N int i; 2920618073e3SMugunthan V N 2921606f3993SIvan Khoronzhuk for (i = 0; i < cpsw->data.slaves; i++) { 2922606f3993SIvan Khoronzhuk if (netif_running(cpsw->slaves[i].ndev)) 2923606f3993SIvan Khoronzhuk cpsw_ndo_stop(cpsw->slaves[i].ndev); 2924618073e3SMugunthan V N } 2925618073e3SMugunthan V N } else { 2926df828598SMugunthan V N if (netif_running(ndev)) 2927df828598SMugunthan V N cpsw_ndo_stop(ndev); 2928618073e3SMugunthan V N } 29291e7a2e21SDaniel Mack 2930739683b4SMugunthan V N /* Select sleep pin state */ 293156e31bd8SIvan Khoronzhuk pinctrl_pm_select_sleep_state(dev); 2932739683b4SMugunthan V N 2933df828598SMugunthan V N return 0; 2934df828598SMugunthan V N } 2935df828598SMugunthan V N 2936df828598SMugunthan V N static int cpsw_resume(struct device *dev) 2937df828598SMugunthan V N { 2938df828598SMugunthan V N struct platform_device *pdev = to_platform_device(dev); 2939df828598SMugunthan V N struct net_device *ndev = platform_get_drvdata(pdev); 2940606f3993SIvan Khoronzhuk struct cpsw_common *cpsw = netdev_priv(ndev); 2941df828598SMugunthan V N 2942739683b4SMugunthan V N /* Select default pin state */ 294356e31bd8SIvan Khoronzhuk pinctrl_pm_select_default_state(dev); 2944739683b4SMugunthan V N 2945606f3993SIvan Khoronzhuk if (cpsw->data.dual_emac) { 2946618073e3SMugunthan V N int i; 2947618073e3SMugunthan V N 2948606f3993SIvan Khoronzhuk for (i = 0; i < cpsw->data.slaves; i++) { 2949606f3993SIvan Khoronzhuk if (netif_running(cpsw->slaves[i].ndev)) 2950606f3993SIvan Khoronzhuk cpsw_ndo_open(cpsw->slaves[i].ndev); 2951618073e3SMugunthan V N } 2952618073e3SMugunthan V N } else { 2953df828598SMugunthan V N if (netif_running(ndev)) 2954df828598SMugunthan V N cpsw_ndo_open(ndev); 2955618073e3SMugunthan V N } 2956df828598SMugunthan V N return 0; 2957df828598SMugunthan V N } 29588963a504SGrygorii Strashko #endif 2959df828598SMugunthan V N 29608963a504SGrygorii Strashko static SIMPLE_DEV_PM_OPS(cpsw_pm_ops, cpsw_suspend, cpsw_resume); 2961df828598SMugunthan V N 2962df828598SMugunthan V N static struct platform_driver cpsw_driver = { 2963df828598SMugunthan V N .driver = { 2964df828598SMugunthan V N .name = "cpsw", 2965df828598SMugunthan V N .pm = &cpsw_pm_ops, 29661e5c76d4SSachin Kamat .of_match_table = cpsw_of_mtable, 2967df828598SMugunthan V N }, 2968df828598SMugunthan V N .probe = cpsw_probe, 2969663e12e6SBill Pemberton .remove = cpsw_remove, 2970df828598SMugunthan V N }; 2971df828598SMugunthan V N 29726fb3b6b5SGrygorii Strashko module_platform_driver(cpsw_driver); 2973df828598SMugunthan V N 2974df828598SMugunthan V N MODULE_LICENSE("GPL"); 2975df828598SMugunthan V N MODULE_AUTHOR("Cyril Chemparathy <cyril@ti.com>"); 2976df828598SMugunthan V N MODULE_AUTHOR("Mugunthan V N <mugunthanvnm@ti.com>"); 2977df828598SMugunthan V N MODULE_DESCRIPTION("TI CPSW Ethernet driver"); 2978