1df828598SMugunthan V N /* 2df828598SMugunthan V N * Texas Instruments Ethernet Switch Driver 3df828598SMugunthan V N * 4df828598SMugunthan V N * Copyright (C) 2012 Texas Instruments 5df828598SMugunthan V N * 6df828598SMugunthan V N * This program is free software; you can redistribute it and/or 7df828598SMugunthan V N * modify it under the terms of the GNU General Public License as 8df828598SMugunthan V N * published by the Free Software Foundation version 2. 9df828598SMugunthan V N * 10df828598SMugunthan V N * This program is distributed "as is" WITHOUT ANY WARRANTY of any 11df828598SMugunthan V N * kind, whether express or implied; without even the implied warranty 12df828598SMugunthan V N * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13df828598SMugunthan V N * GNU General Public License for more details. 14df828598SMugunthan V N */ 15df828598SMugunthan V N 16df828598SMugunthan V N #include <linux/kernel.h> 17df828598SMugunthan V N #include <linux/io.h> 18df828598SMugunthan V N #include <linux/clk.h> 19df828598SMugunthan V N #include <linux/timer.h> 20df828598SMugunthan V N #include <linux/module.h> 21df828598SMugunthan V N #include <linux/platform_device.h> 22df828598SMugunthan V N #include <linux/irqreturn.h> 23df828598SMugunthan V N #include <linux/interrupt.h> 24df828598SMugunthan V N #include <linux/if_ether.h> 25df828598SMugunthan V N #include <linux/etherdevice.h> 26df828598SMugunthan V N #include <linux/netdevice.h> 272e5b38abSRichard Cochran #include <linux/net_tstamp.h> 28df828598SMugunthan V N #include <linux/phy.h> 29df828598SMugunthan V N #include <linux/workqueue.h> 30df828598SMugunthan V N #include <linux/delay.h> 31f150bd7fSMugunthan V N #include <linux/pm_runtime.h> 322eb32b0aSMugunthan V N #include <linux/of.h> 332eb32b0aSMugunthan V N #include <linux/of_net.h> 342eb32b0aSMugunthan V N #include <linux/of_device.h> 353b72c2feSMugunthan V N #include <linux/if_vlan.h> 36df828598SMugunthan V N 37739683b4SMugunthan V N #include <linux/pinctrl/consumer.h> 38df828598SMugunthan V N 39dbe34724SMugunthan V N #include "cpsw.h" 40df828598SMugunthan V N #include "cpsw_ale.h" 412e5b38abSRichard Cochran #include "cpts.h" 42df828598SMugunthan V N #include "davinci_cpdma.h" 43df828598SMugunthan V N 44df828598SMugunthan V N #define CPSW_DEBUG (NETIF_MSG_HW | NETIF_MSG_WOL | \ 45df828598SMugunthan V N NETIF_MSG_DRV | NETIF_MSG_LINK | \ 46df828598SMugunthan V N NETIF_MSG_IFUP | NETIF_MSG_INTR | \ 47df828598SMugunthan V N NETIF_MSG_PROBE | NETIF_MSG_TIMER | \ 48df828598SMugunthan V N NETIF_MSG_IFDOWN | NETIF_MSG_RX_ERR | \ 49df828598SMugunthan V N NETIF_MSG_TX_ERR | NETIF_MSG_TX_DONE | \ 50df828598SMugunthan V N NETIF_MSG_PKTDATA | NETIF_MSG_TX_QUEUED | \ 51df828598SMugunthan V N NETIF_MSG_RX_STATUS) 52df828598SMugunthan V N 53df828598SMugunthan V N #define cpsw_info(priv, type, format, ...) \ 54df828598SMugunthan V N do { \ 55df828598SMugunthan V N if (netif_msg_##type(priv) && net_ratelimit()) \ 56df828598SMugunthan V N dev_info(priv->dev, format, ## __VA_ARGS__); \ 57df828598SMugunthan V N } while (0) 58df828598SMugunthan V N 59df828598SMugunthan V N #define cpsw_err(priv, type, format, ...) \ 60df828598SMugunthan V N do { \ 61df828598SMugunthan V N if (netif_msg_##type(priv) && net_ratelimit()) \ 62df828598SMugunthan V N dev_err(priv->dev, format, ## __VA_ARGS__); \ 63df828598SMugunthan V N } while (0) 64df828598SMugunthan V N 65df828598SMugunthan V N #define cpsw_dbg(priv, type, format, ...) \ 66df828598SMugunthan V N do { \ 67df828598SMugunthan V N if (netif_msg_##type(priv) && net_ratelimit()) \ 68df828598SMugunthan V N dev_dbg(priv->dev, format, ## __VA_ARGS__); \ 69df828598SMugunthan V N } while (0) 70df828598SMugunthan V N 71df828598SMugunthan V N #define cpsw_notice(priv, type, format, ...) \ 72df828598SMugunthan V N do { \ 73df828598SMugunthan V N if (netif_msg_##type(priv) && net_ratelimit()) \ 74df828598SMugunthan V N dev_notice(priv->dev, format, ## __VA_ARGS__); \ 75df828598SMugunthan V N } while (0) 76df828598SMugunthan V N 775c50a856SMugunthan V N #define ALE_ALL_PORTS 0x7 785c50a856SMugunthan V N 79df828598SMugunthan V N #define CPSW_MAJOR_VERSION(reg) (reg >> 8 & 0x7) 80df828598SMugunthan V N #define CPSW_MINOR_VERSION(reg) (reg & 0xff) 81df828598SMugunthan V N #define CPSW_RTL_VERSION(reg) ((reg >> 11) & 0x1f) 82df828598SMugunthan V N 83e90cfac6SRichard Cochran #define CPSW_VERSION_1 0x19010a 84e90cfac6SRichard Cochran #define CPSW_VERSION_2 0x19010c 85c193f365SMugunthan V N #define CPSW_VERSION_3 0x19010f 86926489beSMugunthan V N #define CPSW_VERSION_4 0x190112 87549985eeSRichard Cochran 88549985eeSRichard Cochran #define HOST_PORT_NUM 0 89549985eeSRichard Cochran #define SLIVER_SIZE 0x40 90549985eeSRichard Cochran 91549985eeSRichard Cochran #define CPSW1_HOST_PORT_OFFSET 0x028 92549985eeSRichard Cochran #define CPSW1_SLAVE_OFFSET 0x050 93549985eeSRichard Cochran #define CPSW1_SLAVE_SIZE 0x040 94549985eeSRichard Cochran #define CPSW1_CPDMA_OFFSET 0x100 95549985eeSRichard Cochran #define CPSW1_STATERAM_OFFSET 0x200 96d9718546SMugunthan V N #define CPSW1_HW_STATS 0x400 97549985eeSRichard Cochran #define CPSW1_CPTS_OFFSET 0x500 98549985eeSRichard Cochran #define CPSW1_ALE_OFFSET 0x600 99549985eeSRichard Cochran #define CPSW1_SLIVER_OFFSET 0x700 100549985eeSRichard Cochran 101549985eeSRichard Cochran #define CPSW2_HOST_PORT_OFFSET 0x108 102549985eeSRichard Cochran #define CPSW2_SLAVE_OFFSET 0x200 103549985eeSRichard Cochran #define CPSW2_SLAVE_SIZE 0x100 104549985eeSRichard Cochran #define CPSW2_CPDMA_OFFSET 0x800 105d9718546SMugunthan V N #define CPSW2_HW_STATS 0x900 106549985eeSRichard Cochran #define CPSW2_STATERAM_OFFSET 0xa00 107549985eeSRichard Cochran #define CPSW2_CPTS_OFFSET 0xc00 108549985eeSRichard Cochran #define CPSW2_ALE_OFFSET 0xd00 109549985eeSRichard Cochran #define CPSW2_SLIVER_OFFSET 0xd80 110549985eeSRichard Cochran #define CPSW2_BD_OFFSET 0x2000 111549985eeSRichard Cochran 112df828598SMugunthan V N #define CPDMA_RXTHRESH 0x0c0 113df828598SMugunthan V N #define CPDMA_RXFREE 0x0e0 114df828598SMugunthan V N #define CPDMA_TXHDP 0x00 115df828598SMugunthan V N #define CPDMA_RXHDP 0x20 116df828598SMugunthan V N #define CPDMA_TXCP 0x40 117df828598SMugunthan V N #define CPDMA_RXCP 0x60 118df828598SMugunthan V N 119df828598SMugunthan V N #define CPSW_POLL_WEIGHT 64 120df828598SMugunthan V N #define CPSW_MIN_PACKET_SIZE 60 121df828598SMugunthan V N #define CPSW_MAX_PACKET_SIZE (1500 + 14 + 4 + 4) 122df828598SMugunthan V N 123df828598SMugunthan V N #define RX_PRIORITY_MAPPING 0x76543210 124df828598SMugunthan V N #define TX_PRIORITY_MAPPING 0x33221100 125df828598SMugunthan V N #define CPDMA_TX_PRIORITY_MAP 0x76543210 126df828598SMugunthan V N 1273b72c2feSMugunthan V N #define CPSW_VLAN_AWARE BIT(1) 1283b72c2feSMugunthan V N #define CPSW_ALE_VLAN_AWARE 1 1293b72c2feSMugunthan V N 13035717d8dSJohn Ogness #define CPSW_FIFO_NORMAL_MODE (0 << 16) 13135717d8dSJohn Ogness #define CPSW_FIFO_DUAL_MAC_MODE (1 << 16) 13235717d8dSJohn Ogness #define CPSW_FIFO_RATE_LIMIT_MODE (2 << 16) 133d9ba8f9eSMugunthan V N 134ff5b8ef2SMugunthan V N #define CPSW_INTPACEEN (0x3f << 16) 135ff5b8ef2SMugunthan V N #define CPSW_INTPRESCALE_MASK (0x7FF << 0) 136ff5b8ef2SMugunthan V N #define CPSW_CMINTMAX_CNT 63 137ff5b8ef2SMugunthan V N #define CPSW_CMINTMIN_CNT 2 138ff5b8ef2SMugunthan V N #define CPSW_CMINTMAX_INTVL (1000 / CPSW_CMINTMIN_CNT) 139ff5b8ef2SMugunthan V N #define CPSW_CMINTMIN_INTVL ((1000 / CPSW_CMINTMAX_CNT) + 1) 140ff5b8ef2SMugunthan V N 141d3bb9c58SMugunthan V N #define cpsw_slave_index(priv) \ 142d3bb9c58SMugunthan V N ((priv->data.dual_emac) ? priv->emac_port : \ 143d3bb9c58SMugunthan V N priv->data.active_slave) 144d3bb9c58SMugunthan V N 145df828598SMugunthan V N static int debug_level; 146df828598SMugunthan V N module_param(debug_level, int, 0); 147df828598SMugunthan V N MODULE_PARM_DESC(debug_level, "cpsw debug level (NETIF_MSG bits)"); 148df828598SMugunthan V N 149df828598SMugunthan V N static int ale_ageout = 10; 150df828598SMugunthan V N module_param(ale_ageout, int, 0); 151df828598SMugunthan V N MODULE_PARM_DESC(ale_ageout, "cpsw ale ageout interval (seconds)"); 152df828598SMugunthan V N 153df828598SMugunthan V N static int rx_packet_max = CPSW_MAX_PACKET_SIZE; 154df828598SMugunthan V N module_param(rx_packet_max, int, 0); 155df828598SMugunthan V N MODULE_PARM_DESC(rx_packet_max, "maximum receive packet size (bytes)"); 156df828598SMugunthan V N 157996a5c27SRichard Cochran struct cpsw_wr_regs { 158df828598SMugunthan V N u32 id_ver; 159df828598SMugunthan V N u32 soft_reset; 160df828598SMugunthan V N u32 control; 161df828598SMugunthan V N u32 int_control; 162df828598SMugunthan V N u32 rx_thresh_en; 163df828598SMugunthan V N u32 rx_en; 164df828598SMugunthan V N u32 tx_en; 165df828598SMugunthan V N u32 misc_en; 166ff5b8ef2SMugunthan V N u32 mem_allign1[8]; 167ff5b8ef2SMugunthan V N u32 rx_thresh_stat; 168ff5b8ef2SMugunthan V N u32 rx_stat; 169ff5b8ef2SMugunthan V N u32 tx_stat; 170ff5b8ef2SMugunthan V N u32 misc_stat; 171ff5b8ef2SMugunthan V N u32 mem_allign2[8]; 172ff5b8ef2SMugunthan V N u32 rx_imax; 173ff5b8ef2SMugunthan V N u32 tx_imax; 174ff5b8ef2SMugunthan V N 175df828598SMugunthan V N }; 176df828598SMugunthan V N 177996a5c27SRichard Cochran struct cpsw_ss_regs { 178df828598SMugunthan V N u32 id_ver; 179df828598SMugunthan V N u32 control; 180df828598SMugunthan V N u32 soft_reset; 181df828598SMugunthan V N u32 stat_port_en; 182df828598SMugunthan V N u32 ptype; 183bd357af2SRichard Cochran u32 soft_idle; 184bd357af2SRichard Cochran u32 thru_rate; 185bd357af2SRichard Cochran u32 gap_thresh; 186bd357af2SRichard Cochran u32 tx_start_wds; 187bd357af2SRichard Cochran u32 flow_control; 188bd357af2SRichard Cochran u32 vlan_ltype; 189bd357af2SRichard Cochran u32 ts_ltype; 190bd357af2SRichard Cochran u32 dlr_ltype; 191df828598SMugunthan V N }; 192df828598SMugunthan V N 1939750a3adSRichard Cochran /* CPSW_PORT_V1 */ 1949750a3adSRichard Cochran #define CPSW1_MAX_BLKS 0x00 /* Maximum FIFO Blocks */ 1959750a3adSRichard Cochran #define CPSW1_BLK_CNT 0x04 /* FIFO Block Usage Count (Read Only) */ 1969750a3adSRichard Cochran #define CPSW1_TX_IN_CTL 0x08 /* Transmit FIFO Control */ 1979750a3adSRichard Cochran #define CPSW1_PORT_VLAN 0x0c /* VLAN Register */ 1989750a3adSRichard Cochran #define CPSW1_TX_PRI_MAP 0x10 /* Tx Header Priority to Switch Pri Mapping */ 1999750a3adSRichard Cochran #define CPSW1_TS_CTL 0x14 /* Time Sync Control */ 2009750a3adSRichard Cochran #define CPSW1_TS_SEQ_LTYPE 0x18 /* Time Sync Sequence ID Offset and Msg Type */ 2019750a3adSRichard Cochran #define CPSW1_TS_VLAN 0x1c /* Time Sync VLAN1 and VLAN2 */ 2029750a3adSRichard Cochran 2039750a3adSRichard Cochran /* CPSW_PORT_V2 */ 2049750a3adSRichard Cochran #define CPSW2_CONTROL 0x00 /* Control Register */ 2059750a3adSRichard Cochran #define CPSW2_MAX_BLKS 0x08 /* Maximum FIFO Blocks */ 2069750a3adSRichard Cochran #define CPSW2_BLK_CNT 0x0c /* FIFO Block Usage Count (Read Only) */ 2079750a3adSRichard Cochran #define CPSW2_TX_IN_CTL 0x10 /* Transmit FIFO Control */ 2089750a3adSRichard Cochran #define CPSW2_PORT_VLAN 0x14 /* VLAN Register */ 2099750a3adSRichard Cochran #define CPSW2_TX_PRI_MAP 0x18 /* Tx Header Priority to Switch Pri Mapping */ 2109750a3adSRichard Cochran #define CPSW2_TS_SEQ_MTYPE 0x1c /* Time Sync Sequence ID Offset and Msg Type */ 2119750a3adSRichard Cochran 2129750a3adSRichard Cochran /* CPSW_PORT_V1 and V2 */ 2139750a3adSRichard Cochran #define SA_LO 0x20 /* CPGMAC_SL Source Address Low */ 2149750a3adSRichard Cochran #define SA_HI 0x24 /* CPGMAC_SL Source Address High */ 2159750a3adSRichard Cochran #define SEND_PERCENT 0x28 /* Transmit Queue Send Percentages */ 2169750a3adSRichard Cochran 2179750a3adSRichard Cochran /* CPSW_PORT_V2 only */ 2189750a3adSRichard Cochran #define RX_DSCP_PRI_MAP0 0x30 /* Rx DSCP Priority to Rx Packet Mapping */ 2199750a3adSRichard Cochran #define RX_DSCP_PRI_MAP1 0x34 /* Rx DSCP Priority to Rx Packet Mapping */ 2209750a3adSRichard Cochran #define RX_DSCP_PRI_MAP2 0x38 /* Rx DSCP Priority to Rx Packet Mapping */ 2219750a3adSRichard Cochran #define RX_DSCP_PRI_MAP3 0x3c /* Rx DSCP Priority to Rx Packet Mapping */ 2229750a3adSRichard Cochran #define RX_DSCP_PRI_MAP4 0x40 /* Rx DSCP Priority to Rx Packet Mapping */ 2239750a3adSRichard Cochran #define RX_DSCP_PRI_MAP5 0x44 /* Rx DSCP Priority to Rx Packet Mapping */ 2249750a3adSRichard Cochran #define RX_DSCP_PRI_MAP6 0x48 /* Rx DSCP Priority to Rx Packet Mapping */ 2259750a3adSRichard Cochran #define RX_DSCP_PRI_MAP7 0x4c /* Rx DSCP Priority to Rx Packet Mapping */ 2269750a3adSRichard Cochran 2279750a3adSRichard Cochran /* Bit definitions for the CPSW2_CONTROL register */ 2289750a3adSRichard Cochran #define PASS_PRI_TAGGED (1<<24) /* Pass Priority Tagged */ 2299750a3adSRichard Cochran #define VLAN_LTYPE2_EN (1<<21) /* VLAN LTYPE 2 enable */ 2309750a3adSRichard Cochran #define VLAN_LTYPE1_EN (1<<20) /* VLAN LTYPE 1 enable */ 2319750a3adSRichard Cochran #define DSCP_PRI_EN (1<<16) /* DSCP Priority Enable */ 2329750a3adSRichard Cochran #define TS_320 (1<<14) /* Time Sync Dest Port 320 enable */ 2339750a3adSRichard Cochran #define TS_319 (1<<13) /* Time Sync Dest Port 319 enable */ 2349750a3adSRichard Cochran #define TS_132 (1<<12) /* Time Sync Dest IP Addr 132 enable */ 2359750a3adSRichard Cochran #define TS_131 (1<<11) /* Time Sync Dest IP Addr 131 enable */ 2369750a3adSRichard Cochran #define TS_130 (1<<10) /* Time Sync Dest IP Addr 130 enable */ 2379750a3adSRichard Cochran #define TS_129 (1<<9) /* Time Sync Dest IP Addr 129 enable */ 23809c55372SGeorge Cherian #define TS_TTL_NONZERO (1<<8) /* Time Sync Time To Live Non-zero enable */ 23909c55372SGeorge Cherian #define TS_ANNEX_F_EN (1<<6) /* Time Sync Annex F enable */ 2409750a3adSRichard Cochran #define TS_ANNEX_D_EN (1<<4) /* Time Sync Annex D enable */ 2419750a3adSRichard Cochran #define TS_LTYPE2_EN (1<<3) /* Time Sync LTYPE 2 enable */ 2429750a3adSRichard Cochran #define TS_LTYPE1_EN (1<<2) /* Time Sync LTYPE 1 enable */ 2439750a3adSRichard Cochran #define TS_TX_EN (1<<1) /* Time Sync Transmit Enable */ 2449750a3adSRichard Cochran #define TS_RX_EN (1<<0) /* Time Sync Receive Enable */ 2459750a3adSRichard Cochran 24609c55372SGeorge Cherian #define CTRL_V2_TS_BITS \ 24709c55372SGeorge Cherian (TS_320 | TS_319 | TS_132 | TS_131 | TS_130 | TS_129 |\ 24809c55372SGeorge Cherian TS_TTL_NONZERO | TS_ANNEX_D_EN | TS_LTYPE1_EN) 2499750a3adSRichard Cochran 25009c55372SGeorge Cherian #define CTRL_V2_ALL_TS_MASK (CTRL_V2_TS_BITS | TS_TX_EN | TS_RX_EN) 25109c55372SGeorge Cherian #define CTRL_V2_TX_TS_BITS (CTRL_V2_TS_BITS | TS_TX_EN) 25209c55372SGeorge Cherian #define CTRL_V2_RX_TS_BITS (CTRL_V2_TS_BITS | TS_RX_EN) 25309c55372SGeorge Cherian 25409c55372SGeorge Cherian 25509c55372SGeorge Cherian #define CTRL_V3_TS_BITS \ 25609c55372SGeorge Cherian (TS_320 | TS_319 | TS_132 | TS_131 | TS_130 | TS_129 |\ 25709c55372SGeorge Cherian TS_TTL_NONZERO | TS_ANNEX_F_EN | TS_ANNEX_D_EN |\ 25809c55372SGeorge Cherian TS_LTYPE1_EN) 25909c55372SGeorge Cherian 26009c55372SGeorge Cherian #define CTRL_V3_ALL_TS_MASK (CTRL_V3_TS_BITS | TS_TX_EN | TS_RX_EN) 26109c55372SGeorge Cherian #define CTRL_V3_TX_TS_BITS (CTRL_V3_TS_BITS | TS_TX_EN) 26209c55372SGeorge Cherian #define CTRL_V3_RX_TS_BITS (CTRL_V3_TS_BITS | TS_RX_EN) 2639750a3adSRichard Cochran 2649750a3adSRichard Cochran /* Bit definitions for the CPSW2_TS_SEQ_MTYPE register */ 2659750a3adSRichard Cochran #define TS_SEQ_ID_OFFSET_SHIFT (16) /* Time Sync Sequence ID Offset */ 2669750a3adSRichard Cochran #define TS_SEQ_ID_OFFSET_MASK (0x3f) 2679750a3adSRichard Cochran #define TS_MSG_TYPE_EN_SHIFT (0) /* Time Sync Message Type Enable */ 2689750a3adSRichard Cochran #define TS_MSG_TYPE_EN_MASK (0xffff) 2699750a3adSRichard Cochran 2709750a3adSRichard Cochran /* The PTP event messages - Sync, Delay_Req, Pdelay_Req, and Pdelay_Resp. */ 2719750a3adSRichard Cochran #define EVENT_MSG_BITS ((1<<0) | (1<<1) | (1<<2) | (1<<3)) 272df828598SMugunthan V N 2732e5b38abSRichard Cochran /* Bit definitions for the CPSW1_TS_CTL register */ 2742e5b38abSRichard Cochran #define CPSW_V1_TS_RX_EN BIT(0) 2752e5b38abSRichard Cochran #define CPSW_V1_TS_TX_EN BIT(4) 2762e5b38abSRichard Cochran #define CPSW_V1_MSG_TYPE_OFS 16 2772e5b38abSRichard Cochran 2782e5b38abSRichard Cochran /* Bit definitions for the CPSW1_TS_SEQ_LTYPE register */ 2792e5b38abSRichard Cochran #define CPSW_V1_SEQ_ID_OFS_SHIFT 16 2802e5b38abSRichard Cochran 281df828598SMugunthan V N struct cpsw_host_regs { 282df828598SMugunthan V N u32 max_blks; 283df828598SMugunthan V N u32 blk_cnt; 284d9ba8f9eSMugunthan V N u32 tx_in_ctl; 285df828598SMugunthan V N u32 port_vlan; 286df828598SMugunthan V N u32 tx_pri_map; 287df828598SMugunthan V N u32 cpdma_tx_pri_map; 288df828598SMugunthan V N u32 cpdma_rx_chan_map; 289df828598SMugunthan V N }; 290df828598SMugunthan V N 291df828598SMugunthan V N struct cpsw_sliver_regs { 292df828598SMugunthan V N u32 id_ver; 293df828598SMugunthan V N u32 mac_control; 294df828598SMugunthan V N u32 mac_status; 295df828598SMugunthan V N u32 soft_reset; 296df828598SMugunthan V N u32 rx_maxlen; 297df828598SMugunthan V N u32 __reserved_0; 298df828598SMugunthan V N u32 rx_pause; 299df828598SMugunthan V N u32 tx_pause; 300df828598SMugunthan V N u32 __reserved_1; 301df828598SMugunthan V N u32 rx_pri_map; 302df828598SMugunthan V N }; 303df828598SMugunthan V N 304d9718546SMugunthan V N struct cpsw_hw_stats { 305d9718546SMugunthan V N u32 rxgoodframes; 306d9718546SMugunthan V N u32 rxbroadcastframes; 307d9718546SMugunthan V N u32 rxmulticastframes; 308d9718546SMugunthan V N u32 rxpauseframes; 309d9718546SMugunthan V N u32 rxcrcerrors; 310d9718546SMugunthan V N u32 rxaligncodeerrors; 311d9718546SMugunthan V N u32 rxoversizedframes; 312d9718546SMugunthan V N u32 rxjabberframes; 313d9718546SMugunthan V N u32 rxundersizedframes; 314d9718546SMugunthan V N u32 rxfragments; 315d9718546SMugunthan V N u32 __pad_0[2]; 316d9718546SMugunthan V N u32 rxoctets; 317d9718546SMugunthan V N u32 txgoodframes; 318d9718546SMugunthan V N u32 txbroadcastframes; 319d9718546SMugunthan V N u32 txmulticastframes; 320d9718546SMugunthan V N u32 txpauseframes; 321d9718546SMugunthan V N u32 txdeferredframes; 322d9718546SMugunthan V N u32 txcollisionframes; 323d9718546SMugunthan V N u32 txsinglecollframes; 324d9718546SMugunthan V N u32 txmultcollframes; 325d9718546SMugunthan V N u32 txexcessivecollisions; 326d9718546SMugunthan V N u32 txlatecollisions; 327d9718546SMugunthan V N u32 txunderrun; 328d9718546SMugunthan V N u32 txcarriersenseerrors; 329d9718546SMugunthan V N u32 txoctets; 330d9718546SMugunthan V N u32 octetframes64; 331d9718546SMugunthan V N u32 octetframes65t127; 332d9718546SMugunthan V N u32 octetframes128t255; 333d9718546SMugunthan V N u32 octetframes256t511; 334d9718546SMugunthan V N u32 octetframes512t1023; 335d9718546SMugunthan V N u32 octetframes1024tup; 336d9718546SMugunthan V N u32 netoctets; 337d9718546SMugunthan V N u32 rxsofoverruns; 338d9718546SMugunthan V N u32 rxmofoverruns; 339d9718546SMugunthan V N u32 rxdmaoverruns; 340d9718546SMugunthan V N }; 341d9718546SMugunthan V N 342df828598SMugunthan V N struct cpsw_slave { 3439750a3adSRichard Cochran void __iomem *regs; 344df828598SMugunthan V N struct cpsw_sliver_regs __iomem *sliver; 345df828598SMugunthan V N int slave_num; 346df828598SMugunthan V N u32 mac_control; 347df828598SMugunthan V N struct cpsw_slave_data *data; 348df828598SMugunthan V N struct phy_device *phy; 349d9ba8f9eSMugunthan V N struct net_device *ndev; 350d9ba8f9eSMugunthan V N u32 port_vlan; 351d9ba8f9eSMugunthan V N u32 open_stat; 352df828598SMugunthan V N }; 353df828598SMugunthan V N 3549750a3adSRichard Cochran static inline u32 slave_read(struct cpsw_slave *slave, u32 offset) 3559750a3adSRichard Cochran { 3569750a3adSRichard Cochran return __raw_readl(slave->regs + offset); 3579750a3adSRichard Cochran } 3589750a3adSRichard Cochran 3599750a3adSRichard Cochran static inline void slave_write(struct cpsw_slave *slave, u32 val, u32 offset) 3609750a3adSRichard Cochran { 3619750a3adSRichard Cochran __raw_writel(val, slave->regs + offset); 3629750a3adSRichard Cochran } 3639750a3adSRichard Cochran 364df828598SMugunthan V N struct cpsw_priv { 365df828598SMugunthan V N spinlock_t lock; 366df828598SMugunthan V N struct platform_device *pdev; 367df828598SMugunthan V N struct net_device *ndev; 368df828598SMugunthan V N struct napi_struct napi; 369df828598SMugunthan V N struct device *dev; 370df828598SMugunthan V N struct cpsw_platform_data data; 371996a5c27SRichard Cochran struct cpsw_ss_regs __iomem *regs; 372996a5c27SRichard Cochran struct cpsw_wr_regs __iomem *wr_regs; 373d9718546SMugunthan V N u8 __iomem *hw_stats; 374df828598SMugunthan V N struct cpsw_host_regs __iomem *host_port_regs; 375df828598SMugunthan V N u32 msg_enable; 376e90cfac6SRichard Cochran u32 version; 377ff5b8ef2SMugunthan V N u32 coal_intvl; 378ff5b8ef2SMugunthan V N u32 bus_freq_mhz; 379df828598SMugunthan V N int rx_packet_max; 380df828598SMugunthan V N int host_port; 381df828598SMugunthan V N struct clk *clk; 382df828598SMugunthan V N u8 mac_addr[ETH_ALEN]; 383df828598SMugunthan V N struct cpsw_slave *slaves; 384df828598SMugunthan V N struct cpdma_ctlr *dma; 385df828598SMugunthan V N struct cpdma_chan *txch, *rxch; 386df828598SMugunthan V N struct cpsw_ale *ale; 3871923d6e4SMugunthan V N bool rx_pause; 3881923d6e4SMugunthan V N bool tx_pause; 389df828598SMugunthan V N /* snapshot of IRQ numbers */ 390df828598SMugunthan V N u32 irqs_table[4]; 391df828598SMugunthan V N u32 num_irqs; 392a11fbba9SSebastian Siewior bool irq_enabled; 3939232b16dSMugunthan V N struct cpts *cpts; 394d9ba8f9eSMugunthan V N u32 emac_port; 395df828598SMugunthan V N }; 396df828598SMugunthan V N 397d9718546SMugunthan V N struct cpsw_stats { 398d9718546SMugunthan V N char stat_string[ETH_GSTRING_LEN]; 399d9718546SMugunthan V N int type; 400d9718546SMugunthan V N int sizeof_stat; 401d9718546SMugunthan V N int stat_offset; 402d9718546SMugunthan V N }; 403d9718546SMugunthan V N 404d9718546SMugunthan V N enum { 405d9718546SMugunthan V N CPSW_STATS, 406d9718546SMugunthan V N CPDMA_RX_STATS, 407d9718546SMugunthan V N CPDMA_TX_STATS, 408d9718546SMugunthan V N }; 409d9718546SMugunthan V N 410d9718546SMugunthan V N #define CPSW_STAT(m) CPSW_STATS, \ 411d9718546SMugunthan V N sizeof(((struct cpsw_hw_stats *)0)->m), \ 412d9718546SMugunthan V N offsetof(struct cpsw_hw_stats, m) 413d9718546SMugunthan V N #define CPDMA_RX_STAT(m) CPDMA_RX_STATS, \ 414d9718546SMugunthan V N sizeof(((struct cpdma_chan_stats *)0)->m), \ 415d9718546SMugunthan V N offsetof(struct cpdma_chan_stats, m) 416d9718546SMugunthan V N #define CPDMA_TX_STAT(m) CPDMA_TX_STATS, \ 417d9718546SMugunthan V N sizeof(((struct cpdma_chan_stats *)0)->m), \ 418d9718546SMugunthan V N offsetof(struct cpdma_chan_stats, m) 419d9718546SMugunthan V N 420d9718546SMugunthan V N static const struct cpsw_stats cpsw_gstrings_stats[] = { 421d9718546SMugunthan V N { "Good Rx Frames", CPSW_STAT(rxgoodframes) }, 422d9718546SMugunthan V N { "Broadcast Rx Frames", CPSW_STAT(rxbroadcastframes) }, 423d9718546SMugunthan V N { "Multicast Rx Frames", CPSW_STAT(rxmulticastframes) }, 424d9718546SMugunthan V N { "Pause Rx Frames", CPSW_STAT(rxpauseframes) }, 425d9718546SMugunthan V N { "Rx CRC Errors", CPSW_STAT(rxcrcerrors) }, 426d9718546SMugunthan V N { "Rx Align/Code Errors", CPSW_STAT(rxaligncodeerrors) }, 427d9718546SMugunthan V N { "Oversize Rx Frames", CPSW_STAT(rxoversizedframes) }, 428d9718546SMugunthan V N { "Rx Jabbers", CPSW_STAT(rxjabberframes) }, 429d9718546SMugunthan V N { "Undersize (Short) Rx Frames", CPSW_STAT(rxundersizedframes) }, 430d9718546SMugunthan V N { "Rx Fragments", CPSW_STAT(rxfragments) }, 431d9718546SMugunthan V N { "Rx Octets", CPSW_STAT(rxoctets) }, 432d9718546SMugunthan V N { "Good Tx Frames", CPSW_STAT(txgoodframes) }, 433d9718546SMugunthan V N { "Broadcast Tx Frames", CPSW_STAT(txbroadcastframes) }, 434d9718546SMugunthan V N { "Multicast Tx Frames", CPSW_STAT(txmulticastframes) }, 435d9718546SMugunthan V N { "Pause Tx Frames", CPSW_STAT(txpauseframes) }, 436d9718546SMugunthan V N { "Deferred Tx Frames", CPSW_STAT(txdeferredframes) }, 437d9718546SMugunthan V N { "Collisions", CPSW_STAT(txcollisionframes) }, 438d9718546SMugunthan V N { "Single Collision Tx Frames", CPSW_STAT(txsinglecollframes) }, 439d9718546SMugunthan V N { "Multiple Collision Tx Frames", CPSW_STAT(txmultcollframes) }, 440d9718546SMugunthan V N { "Excessive Collisions", CPSW_STAT(txexcessivecollisions) }, 441d9718546SMugunthan V N { "Late Collisions", CPSW_STAT(txlatecollisions) }, 442d9718546SMugunthan V N { "Tx Underrun", CPSW_STAT(txunderrun) }, 443d9718546SMugunthan V N { "Carrier Sense Errors", CPSW_STAT(txcarriersenseerrors) }, 444d9718546SMugunthan V N { "Tx Octets", CPSW_STAT(txoctets) }, 445d9718546SMugunthan V N { "Rx + Tx 64 Octet Frames", CPSW_STAT(octetframes64) }, 446d9718546SMugunthan V N { "Rx + Tx 65-127 Octet Frames", CPSW_STAT(octetframes65t127) }, 447d9718546SMugunthan V N { "Rx + Tx 128-255 Octet Frames", CPSW_STAT(octetframes128t255) }, 448d9718546SMugunthan V N { "Rx + Tx 256-511 Octet Frames", CPSW_STAT(octetframes256t511) }, 449d9718546SMugunthan V N { "Rx + Tx 512-1023 Octet Frames", CPSW_STAT(octetframes512t1023) }, 450d9718546SMugunthan V N { "Rx + Tx 1024-Up Octet Frames", CPSW_STAT(octetframes1024tup) }, 451d9718546SMugunthan V N { "Net Octets", CPSW_STAT(netoctets) }, 452d9718546SMugunthan V N { "Rx Start of Frame Overruns", CPSW_STAT(rxsofoverruns) }, 453d9718546SMugunthan V N { "Rx Middle of Frame Overruns", CPSW_STAT(rxmofoverruns) }, 454d9718546SMugunthan V N { "Rx DMA Overruns", CPSW_STAT(rxdmaoverruns) }, 455d9718546SMugunthan V N { "Rx DMA chan: head_enqueue", CPDMA_RX_STAT(head_enqueue) }, 456d9718546SMugunthan V N { "Rx DMA chan: tail_enqueue", CPDMA_RX_STAT(tail_enqueue) }, 457d9718546SMugunthan V N { "Rx DMA chan: pad_enqueue", CPDMA_RX_STAT(pad_enqueue) }, 458d9718546SMugunthan V N { "Rx DMA chan: misqueued", CPDMA_RX_STAT(misqueued) }, 459d9718546SMugunthan V N { "Rx DMA chan: desc_alloc_fail", CPDMA_RX_STAT(desc_alloc_fail) }, 460d9718546SMugunthan V N { "Rx DMA chan: pad_alloc_fail", CPDMA_RX_STAT(pad_alloc_fail) }, 461d9718546SMugunthan V N { "Rx DMA chan: runt_receive_buf", CPDMA_RX_STAT(runt_receive_buff) }, 462d9718546SMugunthan V N { "Rx DMA chan: runt_transmit_buf", CPDMA_RX_STAT(runt_transmit_buff) }, 463d9718546SMugunthan V N { "Rx DMA chan: empty_dequeue", CPDMA_RX_STAT(empty_dequeue) }, 464d9718546SMugunthan V N { "Rx DMA chan: busy_dequeue", CPDMA_RX_STAT(busy_dequeue) }, 465d9718546SMugunthan V N { "Rx DMA chan: good_dequeue", CPDMA_RX_STAT(good_dequeue) }, 466d9718546SMugunthan V N { "Rx DMA chan: requeue", CPDMA_RX_STAT(requeue) }, 467d9718546SMugunthan V N { "Rx DMA chan: teardown_dequeue", CPDMA_RX_STAT(teardown_dequeue) }, 468d9718546SMugunthan V N { "Tx DMA chan: head_enqueue", CPDMA_TX_STAT(head_enqueue) }, 469d9718546SMugunthan V N { "Tx DMA chan: tail_enqueue", CPDMA_TX_STAT(tail_enqueue) }, 470d9718546SMugunthan V N { "Tx DMA chan: pad_enqueue", CPDMA_TX_STAT(pad_enqueue) }, 471d9718546SMugunthan V N { "Tx DMA chan: misqueued", CPDMA_TX_STAT(misqueued) }, 472d9718546SMugunthan V N { "Tx DMA chan: desc_alloc_fail", CPDMA_TX_STAT(desc_alloc_fail) }, 473d9718546SMugunthan V N { "Tx DMA chan: pad_alloc_fail", CPDMA_TX_STAT(pad_alloc_fail) }, 474d9718546SMugunthan V N { "Tx DMA chan: runt_receive_buf", CPDMA_TX_STAT(runt_receive_buff) }, 475d9718546SMugunthan V N { "Tx DMA chan: runt_transmit_buf", CPDMA_TX_STAT(runt_transmit_buff) }, 476d9718546SMugunthan V N { "Tx DMA chan: empty_dequeue", CPDMA_TX_STAT(empty_dequeue) }, 477d9718546SMugunthan V N { "Tx DMA chan: busy_dequeue", CPDMA_TX_STAT(busy_dequeue) }, 478d9718546SMugunthan V N { "Tx DMA chan: good_dequeue", CPDMA_TX_STAT(good_dequeue) }, 479d9718546SMugunthan V N { "Tx DMA chan: requeue", CPDMA_TX_STAT(requeue) }, 480d9718546SMugunthan V N { "Tx DMA chan: teardown_dequeue", CPDMA_TX_STAT(teardown_dequeue) }, 481d9718546SMugunthan V N }; 482d9718546SMugunthan V N 483d9718546SMugunthan V N #define CPSW_STATS_LEN ARRAY_SIZE(cpsw_gstrings_stats) 484d9718546SMugunthan V N 485df828598SMugunthan V N #define napi_to_priv(napi) container_of(napi, struct cpsw_priv, napi) 486df828598SMugunthan V N #define for_each_slave(priv, func, arg...) \ 487df828598SMugunthan V N do { \ 4886e6ceaedSSebastian Siewior struct cpsw_slave *slave; \ 4896e6ceaedSSebastian Siewior int n; \ 490d9ba8f9eSMugunthan V N if (priv->data.dual_emac) \ 491d9ba8f9eSMugunthan V N (func)((priv)->slaves + priv->emac_port, ##arg);\ 492d9ba8f9eSMugunthan V N else \ 4936e6ceaedSSebastian Siewior for (n = (priv)->data.slaves, \ 4946e6ceaedSSebastian Siewior slave = (priv)->slaves; \ 4956e6ceaedSSebastian Siewior n; n--) \ 4966e6ceaedSSebastian Siewior (func)(slave++, ##arg); \ 497df828598SMugunthan V N } while (0) 498d9ba8f9eSMugunthan V N #define cpsw_get_slave_ndev(priv, __slave_no__) \ 4991973db0dSMugunthan V N ((__slave_no__ < priv->data.slaves) ? \ 5001973db0dSMugunthan V N priv->slaves[__slave_no__].ndev : NULL) 501d9ba8f9eSMugunthan V N #define cpsw_get_slave_priv(priv, __slave_no__) \ 5021973db0dSMugunthan V N (((__slave_no__ < priv->data.slaves) && \ 5031973db0dSMugunthan V N (priv->slaves[__slave_no__].ndev)) ? \ 504d9ba8f9eSMugunthan V N netdev_priv(priv->slaves[__slave_no__].ndev) : NULL) \ 505d9ba8f9eSMugunthan V N 506d9ba8f9eSMugunthan V N #define cpsw_dual_emac_src_port_detect(status, priv, ndev, skb) \ 507d9ba8f9eSMugunthan V N do { \ 508d9ba8f9eSMugunthan V N if (!priv->data.dual_emac) \ 509d9ba8f9eSMugunthan V N break; \ 510d9ba8f9eSMugunthan V N if (CPDMA_RX_SOURCE_PORT(status) == 1) { \ 511d9ba8f9eSMugunthan V N ndev = cpsw_get_slave_ndev(priv, 0); \ 512d9ba8f9eSMugunthan V N priv = netdev_priv(ndev); \ 513d9ba8f9eSMugunthan V N skb->dev = ndev; \ 514d9ba8f9eSMugunthan V N } else if (CPDMA_RX_SOURCE_PORT(status) == 2) { \ 515d9ba8f9eSMugunthan V N ndev = cpsw_get_slave_ndev(priv, 1); \ 516d9ba8f9eSMugunthan V N priv = netdev_priv(ndev); \ 517d9ba8f9eSMugunthan V N skb->dev = ndev; \ 518d9ba8f9eSMugunthan V N } \ 519d9ba8f9eSMugunthan V N } while (0) 520d9ba8f9eSMugunthan V N #define cpsw_add_mcast(priv, addr) \ 521d9ba8f9eSMugunthan V N do { \ 522d9ba8f9eSMugunthan V N if (priv->data.dual_emac) { \ 523d9ba8f9eSMugunthan V N struct cpsw_slave *slave = priv->slaves + \ 524d9ba8f9eSMugunthan V N priv->emac_port; \ 525d9ba8f9eSMugunthan V N int slave_port = cpsw_get_slave_port(priv, \ 526d9ba8f9eSMugunthan V N slave->slave_num); \ 527d9ba8f9eSMugunthan V N cpsw_ale_add_mcast(priv->ale, addr, \ 528d9ba8f9eSMugunthan V N 1 << slave_port | 1 << priv->host_port, \ 529d9ba8f9eSMugunthan V N ALE_VLAN, slave->port_vlan, 0); \ 530d9ba8f9eSMugunthan V N } else { \ 531d9ba8f9eSMugunthan V N cpsw_ale_add_mcast(priv->ale, addr, \ 532d9ba8f9eSMugunthan V N ALE_ALL_PORTS << priv->host_port, \ 533d9ba8f9eSMugunthan V N 0, 0, 0); \ 534d9ba8f9eSMugunthan V N } \ 535d9ba8f9eSMugunthan V N } while (0) 536d9ba8f9eSMugunthan V N 537d9ba8f9eSMugunthan V N static inline int cpsw_get_slave_port(struct cpsw_priv *priv, u32 slave_num) 538d9ba8f9eSMugunthan V N { 539d9ba8f9eSMugunthan V N if (priv->host_port == 0) 540d9ba8f9eSMugunthan V N return slave_num + 1; 541d9ba8f9eSMugunthan V N else 542d9ba8f9eSMugunthan V N return slave_num; 543d9ba8f9eSMugunthan V N } 544df828598SMugunthan V N 5450cd8f9ccSMugunthan V N static void cpsw_set_promiscious(struct net_device *ndev, bool enable) 5460cd8f9ccSMugunthan V N { 5470cd8f9ccSMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 5480cd8f9ccSMugunthan V N struct cpsw_ale *ale = priv->ale; 5490cd8f9ccSMugunthan V N int i; 5500cd8f9ccSMugunthan V N 5510cd8f9ccSMugunthan V N if (priv->data.dual_emac) { 5520cd8f9ccSMugunthan V N bool flag = false; 5530cd8f9ccSMugunthan V N 5540cd8f9ccSMugunthan V N /* Enabling promiscuous mode for one interface will be 5550cd8f9ccSMugunthan V N * common for both the interface as the interface shares 5560cd8f9ccSMugunthan V N * the same hardware resource. 5570cd8f9ccSMugunthan V N */ 5580d961b3bSHeiko Schocher for (i = 0; i < priv->data.slaves; i++) 5590cd8f9ccSMugunthan V N if (priv->slaves[i].ndev->flags & IFF_PROMISC) 5600cd8f9ccSMugunthan V N flag = true; 5610cd8f9ccSMugunthan V N 5620cd8f9ccSMugunthan V N if (!enable && flag) { 5630cd8f9ccSMugunthan V N enable = true; 5640cd8f9ccSMugunthan V N dev_err(&ndev->dev, "promiscuity not disabled as the other interface is still in promiscuity mode\n"); 5650cd8f9ccSMugunthan V N } 5660cd8f9ccSMugunthan V N 5670cd8f9ccSMugunthan V N if (enable) { 5680cd8f9ccSMugunthan V N /* Enable Bypass */ 5690cd8f9ccSMugunthan V N cpsw_ale_control_set(ale, 0, ALE_BYPASS, 1); 5700cd8f9ccSMugunthan V N 5710cd8f9ccSMugunthan V N dev_dbg(&ndev->dev, "promiscuity enabled\n"); 5720cd8f9ccSMugunthan V N } else { 5730cd8f9ccSMugunthan V N /* Disable Bypass */ 5740cd8f9ccSMugunthan V N cpsw_ale_control_set(ale, 0, ALE_BYPASS, 0); 5750cd8f9ccSMugunthan V N dev_dbg(&ndev->dev, "promiscuity disabled\n"); 5760cd8f9ccSMugunthan V N } 5770cd8f9ccSMugunthan V N } else { 5780cd8f9ccSMugunthan V N if (enable) { 5790cd8f9ccSMugunthan V N unsigned long timeout = jiffies + HZ; 5800cd8f9ccSMugunthan V N 5816f979eb3SLennart Sorensen /* Disable Learn for all ports (host is port 0 and slaves are port 1 and up */ 5826f979eb3SLennart Sorensen for (i = 0; i <= priv->data.slaves; i++) { 5830cd8f9ccSMugunthan V N cpsw_ale_control_set(ale, i, 5840cd8f9ccSMugunthan V N ALE_PORT_NOLEARN, 1); 5850cd8f9ccSMugunthan V N cpsw_ale_control_set(ale, i, 5860cd8f9ccSMugunthan V N ALE_PORT_NO_SA_UPDATE, 1); 5870cd8f9ccSMugunthan V N } 5880cd8f9ccSMugunthan V N 5890cd8f9ccSMugunthan V N /* Clear All Untouched entries */ 5900cd8f9ccSMugunthan V N cpsw_ale_control_set(ale, 0, ALE_AGEOUT, 1); 5910cd8f9ccSMugunthan V N do { 5920cd8f9ccSMugunthan V N cpu_relax(); 5930cd8f9ccSMugunthan V N if (cpsw_ale_control_get(ale, 0, ALE_AGEOUT)) 5940cd8f9ccSMugunthan V N break; 5950cd8f9ccSMugunthan V N } while (time_after(timeout, jiffies)); 5960cd8f9ccSMugunthan V N cpsw_ale_control_set(ale, 0, ALE_AGEOUT, 1); 5970cd8f9ccSMugunthan V N 5980cd8f9ccSMugunthan V N /* Clear all mcast from ALE */ 5990cd8f9ccSMugunthan V N cpsw_ale_flush_multicast(ale, ALE_ALL_PORTS << 60025906052SMugunthan V N priv->host_port, -1); 6010cd8f9ccSMugunthan V N 6020cd8f9ccSMugunthan V N /* Flood All Unicast Packets to Host port */ 6030cd8f9ccSMugunthan V N cpsw_ale_control_set(ale, 0, ALE_P0_UNI_FLOOD, 1); 6040cd8f9ccSMugunthan V N dev_dbg(&ndev->dev, "promiscuity enabled\n"); 6050cd8f9ccSMugunthan V N } else { 6066f979eb3SLennart Sorensen /* Don't Flood All Unicast Packets to Host port */ 6070cd8f9ccSMugunthan V N cpsw_ale_control_set(ale, 0, ALE_P0_UNI_FLOOD, 0); 6080cd8f9ccSMugunthan V N 6096f979eb3SLennart Sorensen /* Enable Learn for all ports (host is port 0 and slaves are port 1 and up */ 6106f979eb3SLennart Sorensen for (i = 0; i <= priv->data.slaves; i++) { 6110cd8f9ccSMugunthan V N cpsw_ale_control_set(ale, i, 6120cd8f9ccSMugunthan V N ALE_PORT_NOLEARN, 0); 6130cd8f9ccSMugunthan V N cpsw_ale_control_set(ale, i, 6140cd8f9ccSMugunthan V N ALE_PORT_NO_SA_UPDATE, 0); 6150cd8f9ccSMugunthan V N } 6160cd8f9ccSMugunthan V N dev_dbg(&ndev->dev, "promiscuity disabled\n"); 6170cd8f9ccSMugunthan V N } 6180cd8f9ccSMugunthan V N } 6190cd8f9ccSMugunthan V N } 6200cd8f9ccSMugunthan V N 6215c50a856SMugunthan V N static void cpsw_ndo_set_rx_mode(struct net_device *ndev) 6225c50a856SMugunthan V N { 6235c50a856SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 62425906052SMugunthan V N int vid; 62525906052SMugunthan V N 62625906052SMugunthan V N if (priv->data.dual_emac) 62725906052SMugunthan V N vid = priv->slaves[priv->emac_port].port_vlan; 62825906052SMugunthan V N else 62925906052SMugunthan V N vid = priv->data.default_vlan; 6305c50a856SMugunthan V N 6315c50a856SMugunthan V N if (ndev->flags & IFF_PROMISC) { 6325c50a856SMugunthan V N /* Enable promiscuous mode */ 6330cd8f9ccSMugunthan V N cpsw_set_promiscious(ndev, true); 6341e5c4bc4SLennart Sorensen cpsw_ale_set_allmulti(priv->ale, IFF_ALLMULTI); 6355c50a856SMugunthan V N return; 6360cd8f9ccSMugunthan V N } else { 6370cd8f9ccSMugunthan V N /* Disable promiscuous mode */ 6380cd8f9ccSMugunthan V N cpsw_set_promiscious(ndev, false); 6395c50a856SMugunthan V N } 6405c50a856SMugunthan V N 6411e5c4bc4SLennart Sorensen /* Restore allmulti on vlans if necessary */ 6421e5c4bc4SLennart Sorensen cpsw_ale_set_allmulti(priv->ale, priv->ndev->flags & IFF_ALLMULTI); 6431e5c4bc4SLennart Sorensen 6445c50a856SMugunthan V N /* Clear all mcast from ALE */ 64525906052SMugunthan V N cpsw_ale_flush_multicast(priv->ale, ALE_ALL_PORTS << priv->host_port, 64625906052SMugunthan V N vid); 6475c50a856SMugunthan V N 6485c50a856SMugunthan V N if (!netdev_mc_empty(ndev)) { 6495c50a856SMugunthan V N struct netdev_hw_addr *ha; 6505c50a856SMugunthan V N 6515c50a856SMugunthan V N /* program multicast address list into ALE register */ 6525c50a856SMugunthan V N netdev_for_each_mc_addr(ha, ndev) { 653d9ba8f9eSMugunthan V N cpsw_add_mcast(priv, (u8 *)ha->addr); 6545c50a856SMugunthan V N } 6555c50a856SMugunthan V N } 6565c50a856SMugunthan V N } 6575c50a856SMugunthan V N 658df828598SMugunthan V N static void cpsw_intr_enable(struct cpsw_priv *priv) 659df828598SMugunthan V N { 660996a5c27SRichard Cochran __raw_writel(0xFF, &priv->wr_regs->tx_en); 661996a5c27SRichard Cochran __raw_writel(0xFF, &priv->wr_regs->rx_en); 662df828598SMugunthan V N 663df828598SMugunthan V N cpdma_ctlr_int_ctrl(priv->dma, true); 664df828598SMugunthan V N return; 665df828598SMugunthan V N } 666df828598SMugunthan V N 667df828598SMugunthan V N static void cpsw_intr_disable(struct cpsw_priv *priv) 668df828598SMugunthan V N { 669996a5c27SRichard Cochran __raw_writel(0, &priv->wr_regs->tx_en); 670996a5c27SRichard Cochran __raw_writel(0, &priv->wr_regs->rx_en); 671df828598SMugunthan V N 672df828598SMugunthan V N cpdma_ctlr_int_ctrl(priv->dma, false); 673df828598SMugunthan V N return; 674df828598SMugunthan V N } 675df828598SMugunthan V N 6761a3b5056SOlof Johansson static void cpsw_tx_handler(void *token, int len, int status) 677df828598SMugunthan V N { 678df828598SMugunthan V N struct sk_buff *skb = token; 679df828598SMugunthan V N struct net_device *ndev = skb->dev; 680df828598SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 681df828598SMugunthan V N 682fae50823SMugunthan V N /* Check whether the queue is stopped due to stalled tx dma, if the 683fae50823SMugunthan V N * queue is stopped then start the queue as we have free desc for tx 684fae50823SMugunthan V N */ 685df828598SMugunthan V N if (unlikely(netif_queue_stopped(ndev))) 686b56d6b3fSMugunthan V N netif_wake_queue(ndev); 6879232b16dSMugunthan V N cpts_tx_timestamp(priv->cpts, skb); 6888dc43ddcSTobias Klauser ndev->stats.tx_packets++; 6898dc43ddcSTobias Klauser ndev->stats.tx_bytes += len; 690df828598SMugunthan V N dev_kfree_skb_any(skb); 691df828598SMugunthan V N } 692df828598SMugunthan V N 6931a3b5056SOlof Johansson static void cpsw_rx_handler(void *token, int len, int status) 694df828598SMugunthan V N { 695df828598SMugunthan V N struct sk_buff *skb = token; 696b4727e69SSebastian Siewior struct sk_buff *new_skb; 697df828598SMugunthan V N struct net_device *ndev = skb->dev; 698df828598SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 699df828598SMugunthan V N int ret = 0; 700df828598SMugunthan V N 701d9ba8f9eSMugunthan V N cpsw_dual_emac_src_port_detect(status, priv, ndev, skb); 702d9ba8f9eSMugunthan V N 70316e5c57dSMugunthan V N if (unlikely(status < 0) || unlikely(!netif_running(ndev))) { 704a0e2c822SMugunthan V N bool ndev_status = false; 705a0e2c822SMugunthan V N struct cpsw_slave *slave = priv->slaves; 706a0e2c822SMugunthan V N int n; 707a0e2c822SMugunthan V N 708a0e2c822SMugunthan V N if (priv->data.dual_emac) { 709a0e2c822SMugunthan V N /* In dual emac mode check for all interfaces */ 710a0e2c822SMugunthan V N for (n = priv->data.slaves; n; n--, slave++) 711a0e2c822SMugunthan V N if (netif_running(slave->ndev)) 712a0e2c822SMugunthan V N ndev_status = true; 713a0e2c822SMugunthan V N } 714a0e2c822SMugunthan V N 715a0e2c822SMugunthan V N if (ndev_status && (status >= 0)) { 716a0e2c822SMugunthan V N /* The packet received is for the interface which 717a0e2c822SMugunthan V N * is already down and the other interface is up 718dbedd44eSJoe Perches * and running, instead of freeing which results 719a0e2c822SMugunthan V N * in reducing of the number of rx descriptor in 720a0e2c822SMugunthan V N * DMA engine, requeue skb back to cpdma. 721a0e2c822SMugunthan V N */ 722a0e2c822SMugunthan V N new_skb = skb; 723a0e2c822SMugunthan V N goto requeue; 724a0e2c822SMugunthan V N } 725a0e2c822SMugunthan V N 726b4727e69SSebastian Siewior /* the interface is going down, skbs are purged */ 727df828598SMugunthan V N dev_kfree_skb_any(skb); 728df828598SMugunthan V N return; 729df828598SMugunthan V N } 730b4727e69SSebastian Siewior 731b4727e69SSebastian Siewior new_skb = netdev_alloc_skb_ip_align(ndev, priv->rx_packet_max); 732b4727e69SSebastian Siewior if (new_skb) { 733df828598SMugunthan V N skb_put(skb, len); 7349232b16dSMugunthan V N cpts_rx_timestamp(priv->cpts, skb); 735df828598SMugunthan V N skb->protocol = eth_type_trans(skb, ndev); 736df828598SMugunthan V N netif_receive_skb(skb); 7378dc43ddcSTobias Klauser ndev->stats.rx_bytes += len; 7388dc43ddcSTobias Klauser ndev->stats.rx_packets++; 739b4727e69SSebastian Siewior } else { 7408dc43ddcSTobias Klauser ndev->stats.rx_dropped++; 741b4727e69SSebastian Siewior new_skb = skb; 742df828598SMugunthan V N } 743df828598SMugunthan V N 744a0e2c822SMugunthan V N requeue: 745b4727e69SSebastian Siewior ret = cpdma_chan_submit(priv->rxch, new_skb, new_skb->data, 746b4727e69SSebastian Siewior skb_tailroom(new_skb), 0); 747b4727e69SSebastian Siewior if (WARN_ON(ret < 0)) 748b4727e69SSebastian Siewior dev_kfree_skb_any(new_skb); 749df828598SMugunthan V N } 750df828598SMugunthan V N 751c03abd84SFelipe Balbi static irqreturn_t cpsw_tx_interrupt(int irq, void *dev_id) 752df828598SMugunthan V N { 753df828598SMugunthan V N struct cpsw_priv *priv = dev_id; 7547ce67a38SFelipe Balbi 755c03abd84SFelipe Balbi cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_TX); 756c03abd84SFelipe Balbi cpdma_chan_process(priv->txch, 128); 757c03abd84SFelipe Balbi 758c03abd84SFelipe Balbi priv = cpsw_get_slave_priv(priv, 1); 759c03abd84SFelipe Balbi if (priv) 760c03abd84SFelipe Balbi cpdma_chan_process(priv->txch, 128); 761c03abd84SFelipe Balbi 762c03abd84SFelipe Balbi return IRQ_HANDLED; 763c03abd84SFelipe Balbi } 764c03abd84SFelipe Balbi 765c03abd84SFelipe Balbi static irqreturn_t cpsw_rx_interrupt(int irq, void *dev_id) 766c03abd84SFelipe Balbi { 767c03abd84SFelipe Balbi struct cpsw_priv *priv = dev_id; 768c03abd84SFelipe Balbi 769c03abd84SFelipe Balbi cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_RX); 770fd51cf19SSebastian Siewior 771df828598SMugunthan V N cpsw_intr_disable(priv); 772a11fbba9SSebastian Siewior if (priv->irq_enabled == true) { 7735a0266afSMugunthan V N disable_irq_nosync(priv->irqs_table[0]); 774a11fbba9SSebastian Siewior priv->irq_enabled = false; 775a11fbba9SSebastian Siewior } 776fd51cf19SSebastian Siewior 777fd51cf19SSebastian Siewior if (netif_running(priv->ndev)) { 778df828598SMugunthan V N napi_schedule(&priv->napi); 779df828598SMugunthan V N return IRQ_HANDLED; 780df828598SMugunthan V N } 781df828598SMugunthan V N 782fd51cf19SSebastian Siewior priv = cpsw_get_slave_priv(priv, 1); 783fd51cf19SSebastian Siewior if (!priv) 784fd51cf19SSebastian Siewior return IRQ_NONE; 785fd51cf19SSebastian Siewior 786fd51cf19SSebastian Siewior if (netif_running(priv->ndev)) { 787fd51cf19SSebastian Siewior napi_schedule(&priv->napi); 788fd51cf19SSebastian Siewior return IRQ_HANDLED; 789fd51cf19SSebastian Siewior } 790fd51cf19SSebastian Siewior return IRQ_NONE; 791fd51cf19SSebastian Siewior } 792fd51cf19SSebastian Siewior 793df828598SMugunthan V N static int cpsw_poll(struct napi_struct *napi, int budget) 794df828598SMugunthan V N { 795df828598SMugunthan V N struct cpsw_priv *priv = napi_to_priv(napi); 7961e353cddSMugunthan V N int num_rx; 797510a1e72SMugunthan V N 798df828598SMugunthan V N num_rx = cpdma_chan_process(priv->rxch, budget); 799510a1e72SMugunthan V N if (num_rx < budget) { 800a11fbba9SSebastian Siewior struct cpsw_priv *prim_cpsw; 801a11fbba9SSebastian Siewior 802510a1e72SMugunthan V N napi_complete(napi); 803510a1e72SMugunthan V N cpsw_intr_enable(priv); 804a11fbba9SSebastian Siewior prim_cpsw = cpsw_get_slave_priv(priv, 0); 805a11fbba9SSebastian Siewior if (prim_cpsw->irq_enabled == false) { 806a11fbba9SSebastian Siewior prim_cpsw->irq_enabled = true; 8075a0266afSMugunthan V N enable_irq(priv->irqs_table[0]); 808a11fbba9SSebastian Siewior } 809510a1e72SMugunthan V N } 810df828598SMugunthan V N 8111e353cddSMugunthan V N if (num_rx) 8121e353cddSMugunthan V N cpsw_dbg(priv, intr, "poll %d rx pkts\n", num_rx); 813df828598SMugunthan V N 814df828598SMugunthan V N return num_rx; 815df828598SMugunthan V N } 816df828598SMugunthan V N 817df828598SMugunthan V N static inline void soft_reset(const char *module, void __iomem *reg) 818df828598SMugunthan V N { 819df828598SMugunthan V N unsigned long timeout = jiffies + HZ; 820df828598SMugunthan V N 821df828598SMugunthan V N __raw_writel(1, reg); 822df828598SMugunthan V N do { 823df828598SMugunthan V N cpu_relax(); 824df828598SMugunthan V N } while ((__raw_readl(reg) & 1) && time_after(timeout, jiffies)); 825df828598SMugunthan V N 826df828598SMugunthan V N WARN(__raw_readl(reg) & 1, "failed to soft-reset %s\n", module); 827df828598SMugunthan V N } 828df828598SMugunthan V N 829df828598SMugunthan V N #define mac_hi(mac) (((mac)[0] << 0) | ((mac)[1] << 8) | \ 830df828598SMugunthan V N ((mac)[2] << 16) | ((mac)[3] << 24)) 831df828598SMugunthan V N #define mac_lo(mac) (((mac)[4] << 0) | ((mac)[5] << 8)) 832df828598SMugunthan V N 833df828598SMugunthan V N static void cpsw_set_slave_mac(struct cpsw_slave *slave, 834df828598SMugunthan V N struct cpsw_priv *priv) 835df828598SMugunthan V N { 8369750a3adSRichard Cochran slave_write(slave, mac_hi(priv->mac_addr), SA_HI); 8379750a3adSRichard Cochran slave_write(slave, mac_lo(priv->mac_addr), SA_LO); 838df828598SMugunthan V N } 839df828598SMugunthan V N 840df828598SMugunthan V N static void _cpsw_adjust_link(struct cpsw_slave *slave, 841df828598SMugunthan V N struct cpsw_priv *priv, bool *link) 842df828598SMugunthan V N { 843df828598SMugunthan V N struct phy_device *phy = slave->phy; 844df828598SMugunthan V N u32 mac_control = 0; 845df828598SMugunthan V N u32 slave_port; 846df828598SMugunthan V N 847df828598SMugunthan V N if (!phy) 848df828598SMugunthan V N return; 849df828598SMugunthan V N 850df828598SMugunthan V N slave_port = cpsw_get_slave_port(priv, slave->slave_num); 851df828598SMugunthan V N 852df828598SMugunthan V N if (phy->link) { 853df828598SMugunthan V N mac_control = priv->data.mac_control; 854df828598SMugunthan V N 855df828598SMugunthan V N /* enable forwarding */ 856df828598SMugunthan V N cpsw_ale_control_set(priv->ale, slave_port, 857df828598SMugunthan V N ALE_PORT_STATE, ALE_PORT_STATE_FORWARD); 858df828598SMugunthan V N 859df828598SMugunthan V N if (phy->speed == 1000) 860df828598SMugunthan V N mac_control |= BIT(7); /* GIGABITEN */ 861df828598SMugunthan V N if (phy->duplex) 862df828598SMugunthan V N mac_control |= BIT(0); /* FULLDUPLEXEN */ 863342b7b74SDaniel Mack 864342b7b74SDaniel Mack /* set speed_in input in case RMII mode is used in 100Mbps */ 865342b7b74SDaniel Mack if (phy->speed == 100) 866342b7b74SDaniel Mack mac_control |= BIT(15); 867a81d8762SMugunthan V N else if (phy->speed == 10) 868a81d8762SMugunthan V N mac_control |= BIT(18); /* In Band mode */ 869342b7b74SDaniel Mack 8701923d6e4SMugunthan V N if (priv->rx_pause) 8711923d6e4SMugunthan V N mac_control |= BIT(3); 8721923d6e4SMugunthan V N 8731923d6e4SMugunthan V N if (priv->tx_pause) 8741923d6e4SMugunthan V N mac_control |= BIT(4); 8751923d6e4SMugunthan V N 876df828598SMugunthan V N *link = true; 877df828598SMugunthan V N } else { 878df828598SMugunthan V N mac_control = 0; 879df828598SMugunthan V N /* disable forwarding */ 880df828598SMugunthan V N cpsw_ale_control_set(priv->ale, slave_port, 881df828598SMugunthan V N ALE_PORT_STATE, ALE_PORT_STATE_DISABLE); 882df828598SMugunthan V N } 883df828598SMugunthan V N 884df828598SMugunthan V N if (mac_control != slave->mac_control) { 885df828598SMugunthan V N phy_print_status(phy); 886df828598SMugunthan V N __raw_writel(mac_control, &slave->sliver->mac_control); 887df828598SMugunthan V N } 888df828598SMugunthan V N 889df828598SMugunthan V N slave->mac_control = mac_control; 890df828598SMugunthan V N } 891df828598SMugunthan V N 892df828598SMugunthan V N static void cpsw_adjust_link(struct net_device *ndev) 893df828598SMugunthan V N { 894df828598SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 895df828598SMugunthan V N bool link = false; 896df828598SMugunthan V N 897df828598SMugunthan V N for_each_slave(priv, _cpsw_adjust_link, priv, &link); 898df828598SMugunthan V N 899df828598SMugunthan V N if (link) { 900df828598SMugunthan V N netif_carrier_on(ndev); 901df828598SMugunthan V N if (netif_running(ndev)) 902df828598SMugunthan V N netif_wake_queue(ndev); 903df828598SMugunthan V N } else { 904df828598SMugunthan V N netif_carrier_off(ndev); 905df828598SMugunthan V N netif_stop_queue(ndev); 906df828598SMugunthan V N } 907df828598SMugunthan V N } 908df828598SMugunthan V N 909ff5b8ef2SMugunthan V N static int cpsw_get_coalesce(struct net_device *ndev, 910ff5b8ef2SMugunthan V N struct ethtool_coalesce *coal) 911ff5b8ef2SMugunthan V N { 912ff5b8ef2SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 913ff5b8ef2SMugunthan V N 914ff5b8ef2SMugunthan V N coal->rx_coalesce_usecs = priv->coal_intvl; 915ff5b8ef2SMugunthan V N return 0; 916ff5b8ef2SMugunthan V N } 917ff5b8ef2SMugunthan V N 918ff5b8ef2SMugunthan V N static int cpsw_set_coalesce(struct net_device *ndev, 919ff5b8ef2SMugunthan V N struct ethtool_coalesce *coal) 920ff5b8ef2SMugunthan V N { 921ff5b8ef2SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 922ff5b8ef2SMugunthan V N u32 int_ctrl; 923ff5b8ef2SMugunthan V N u32 num_interrupts = 0; 924ff5b8ef2SMugunthan V N u32 prescale = 0; 925ff5b8ef2SMugunthan V N u32 addnl_dvdr = 1; 926ff5b8ef2SMugunthan V N u32 coal_intvl = 0; 927ff5b8ef2SMugunthan V N 928ff5b8ef2SMugunthan V N coal_intvl = coal->rx_coalesce_usecs; 929ff5b8ef2SMugunthan V N 930ff5b8ef2SMugunthan V N int_ctrl = readl(&priv->wr_regs->int_control); 931ff5b8ef2SMugunthan V N prescale = priv->bus_freq_mhz * 4; 932ff5b8ef2SMugunthan V N 933a84bc2a9SMugunthan V N if (!coal->rx_coalesce_usecs) { 934a84bc2a9SMugunthan V N int_ctrl &= ~(CPSW_INTPRESCALE_MASK | CPSW_INTPACEEN); 935a84bc2a9SMugunthan V N goto update_return; 936a84bc2a9SMugunthan V N } 937a84bc2a9SMugunthan V N 938ff5b8ef2SMugunthan V N if (coal_intvl < CPSW_CMINTMIN_INTVL) 939ff5b8ef2SMugunthan V N coal_intvl = CPSW_CMINTMIN_INTVL; 940ff5b8ef2SMugunthan V N 941ff5b8ef2SMugunthan V N if (coal_intvl > CPSW_CMINTMAX_INTVL) { 942ff5b8ef2SMugunthan V N /* Interrupt pacer works with 4us Pulse, we can 943ff5b8ef2SMugunthan V N * throttle further by dilating the 4us pulse. 944ff5b8ef2SMugunthan V N */ 945ff5b8ef2SMugunthan V N addnl_dvdr = CPSW_INTPRESCALE_MASK / prescale; 946ff5b8ef2SMugunthan V N 947ff5b8ef2SMugunthan V N if (addnl_dvdr > 1) { 948ff5b8ef2SMugunthan V N prescale *= addnl_dvdr; 949ff5b8ef2SMugunthan V N if (coal_intvl > (CPSW_CMINTMAX_INTVL * addnl_dvdr)) 950ff5b8ef2SMugunthan V N coal_intvl = (CPSW_CMINTMAX_INTVL 951ff5b8ef2SMugunthan V N * addnl_dvdr); 952ff5b8ef2SMugunthan V N } else { 953ff5b8ef2SMugunthan V N addnl_dvdr = 1; 954ff5b8ef2SMugunthan V N coal_intvl = CPSW_CMINTMAX_INTVL; 955ff5b8ef2SMugunthan V N } 956ff5b8ef2SMugunthan V N } 957ff5b8ef2SMugunthan V N 958ff5b8ef2SMugunthan V N num_interrupts = (1000 * addnl_dvdr) / coal_intvl; 959ff5b8ef2SMugunthan V N writel(num_interrupts, &priv->wr_regs->rx_imax); 960ff5b8ef2SMugunthan V N writel(num_interrupts, &priv->wr_regs->tx_imax); 961ff5b8ef2SMugunthan V N 962ff5b8ef2SMugunthan V N int_ctrl |= CPSW_INTPACEEN; 963ff5b8ef2SMugunthan V N int_ctrl &= (~CPSW_INTPRESCALE_MASK); 964ff5b8ef2SMugunthan V N int_ctrl |= (prescale & CPSW_INTPRESCALE_MASK); 965a84bc2a9SMugunthan V N 966a84bc2a9SMugunthan V N update_return: 967ff5b8ef2SMugunthan V N writel(int_ctrl, &priv->wr_regs->int_control); 968ff5b8ef2SMugunthan V N 969ff5b8ef2SMugunthan V N cpsw_notice(priv, timer, "Set coalesce to %d usecs.\n", coal_intvl); 970ff5b8ef2SMugunthan V N if (priv->data.dual_emac) { 971ff5b8ef2SMugunthan V N int i; 972ff5b8ef2SMugunthan V N 973ff5b8ef2SMugunthan V N for (i = 0; i < priv->data.slaves; i++) { 974ff5b8ef2SMugunthan V N priv = netdev_priv(priv->slaves[i].ndev); 975ff5b8ef2SMugunthan V N priv->coal_intvl = coal_intvl; 976ff5b8ef2SMugunthan V N } 977ff5b8ef2SMugunthan V N } else { 978ff5b8ef2SMugunthan V N priv->coal_intvl = coal_intvl; 979ff5b8ef2SMugunthan V N } 980ff5b8ef2SMugunthan V N 981ff5b8ef2SMugunthan V N return 0; 982ff5b8ef2SMugunthan V N } 983ff5b8ef2SMugunthan V N 984d9718546SMugunthan V N static int cpsw_get_sset_count(struct net_device *ndev, int sset) 985d9718546SMugunthan V N { 986d9718546SMugunthan V N switch (sset) { 987d9718546SMugunthan V N case ETH_SS_STATS: 988d9718546SMugunthan V N return CPSW_STATS_LEN; 989d9718546SMugunthan V N default: 990d9718546SMugunthan V N return -EOPNOTSUPP; 991d9718546SMugunthan V N } 992d9718546SMugunthan V N } 993d9718546SMugunthan V N 994d9718546SMugunthan V N static void cpsw_get_strings(struct net_device *ndev, u32 stringset, u8 *data) 995d9718546SMugunthan V N { 996d9718546SMugunthan V N u8 *p = data; 997d9718546SMugunthan V N int i; 998d9718546SMugunthan V N 999d9718546SMugunthan V N switch (stringset) { 1000d9718546SMugunthan V N case ETH_SS_STATS: 1001d9718546SMugunthan V N for (i = 0; i < CPSW_STATS_LEN; i++) { 1002d9718546SMugunthan V N memcpy(p, cpsw_gstrings_stats[i].stat_string, 1003d9718546SMugunthan V N ETH_GSTRING_LEN); 1004d9718546SMugunthan V N p += ETH_GSTRING_LEN; 1005d9718546SMugunthan V N } 1006d9718546SMugunthan V N break; 1007d9718546SMugunthan V N } 1008d9718546SMugunthan V N } 1009d9718546SMugunthan V N 1010d9718546SMugunthan V N static void cpsw_get_ethtool_stats(struct net_device *ndev, 1011d9718546SMugunthan V N struct ethtool_stats *stats, u64 *data) 1012d9718546SMugunthan V N { 1013d9718546SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 1014d9718546SMugunthan V N struct cpdma_chan_stats rx_stats; 1015d9718546SMugunthan V N struct cpdma_chan_stats tx_stats; 1016d9718546SMugunthan V N u32 val; 1017d9718546SMugunthan V N u8 *p; 1018d9718546SMugunthan V N int i; 1019d9718546SMugunthan V N 1020d9718546SMugunthan V N /* Collect Davinci CPDMA stats for Rx and Tx Channel */ 1021d9718546SMugunthan V N cpdma_chan_get_stats(priv->rxch, &rx_stats); 1022d9718546SMugunthan V N cpdma_chan_get_stats(priv->txch, &tx_stats); 1023d9718546SMugunthan V N 1024d9718546SMugunthan V N for (i = 0; i < CPSW_STATS_LEN; i++) { 1025d9718546SMugunthan V N switch (cpsw_gstrings_stats[i].type) { 1026d9718546SMugunthan V N case CPSW_STATS: 1027d9718546SMugunthan V N val = readl(priv->hw_stats + 1028d9718546SMugunthan V N cpsw_gstrings_stats[i].stat_offset); 1029d9718546SMugunthan V N data[i] = val; 1030d9718546SMugunthan V N break; 1031d9718546SMugunthan V N 1032d9718546SMugunthan V N case CPDMA_RX_STATS: 1033d9718546SMugunthan V N p = (u8 *)&rx_stats + 1034d9718546SMugunthan V N cpsw_gstrings_stats[i].stat_offset; 1035d9718546SMugunthan V N data[i] = *(u32 *)p; 1036d9718546SMugunthan V N break; 1037d9718546SMugunthan V N 1038d9718546SMugunthan V N case CPDMA_TX_STATS: 1039d9718546SMugunthan V N p = (u8 *)&tx_stats + 1040d9718546SMugunthan V N cpsw_gstrings_stats[i].stat_offset; 1041d9718546SMugunthan V N data[i] = *(u32 *)p; 1042d9718546SMugunthan V N break; 1043d9718546SMugunthan V N } 1044d9718546SMugunthan V N } 1045d9718546SMugunthan V N } 1046d9718546SMugunthan V N 1047d9ba8f9eSMugunthan V N static int cpsw_common_res_usage_state(struct cpsw_priv *priv) 1048d9ba8f9eSMugunthan V N { 1049d9ba8f9eSMugunthan V N u32 i; 1050d9ba8f9eSMugunthan V N u32 usage_count = 0; 1051d9ba8f9eSMugunthan V N 1052d9ba8f9eSMugunthan V N if (!priv->data.dual_emac) 1053d9ba8f9eSMugunthan V N return 0; 1054d9ba8f9eSMugunthan V N 1055d9ba8f9eSMugunthan V N for (i = 0; i < priv->data.slaves; i++) 1056d9ba8f9eSMugunthan V N if (priv->slaves[i].open_stat) 1057d9ba8f9eSMugunthan V N usage_count++; 1058d9ba8f9eSMugunthan V N 1059d9ba8f9eSMugunthan V N return usage_count; 1060d9ba8f9eSMugunthan V N } 1061d9ba8f9eSMugunthan V N 1062d9ba8f9eSMugunthan V N static inline int cpsw_tx_packet_submit(struct net_device *ndev, 1063d9ba8f9eSMugunthan V N struct cpsw_priv *priv, struct sk_buff *skb) 1064d9ba8f9eSMugunthan V N { 1065d9ba8f9eSMugunthan V N if (!priv->data.dual_emac) 1066d9ba8f9eSMugunthan V N return cpdma_chan_submit(priv->txch, skb, skb->data, 1067aef614e1SSebastian Siewior skb->len, 0); 1068d9ba8f9eSMugunthan V N 1069d9ba8f9eSMugunthan V N if (ndev == cpsw_get_slave_ndev(priv, 0)) 1070d9ba8f9eSMugunthan V N return cpdma_chan_submit(priv->txch, skb, skb->data, 1071aef614e1SSebastian Siewior skb->len, 1); 1072d9ba8f9eSMugunthan V N else 1073d9ba8f9eSMugunthan V N return cpdma_chan_submit(priv->txch, skb, skb->data, 1074aef614e1SSebastian Siewior skb->len, 2); 1075d9ba8f9eSMugunthan V N } 1076d9ba8f9eSMugunthan V N 1077d9ba8f9eSMugunthan V N static inline void cpsw_add_dual_emac_def_ale_entries( 1078d9ba8f9eSMugunthan V N struct cpsw_priv *priv, struct cpsw_slave *slave, 1079d9ba8f9eSMugunthan V N u32 slave_port) 1080d9ba8f9eSMugunthan V N { 1081d9ba8f9eSMugunthan V N u32 port_mask = 1 << slave_port | 1 << priv->host_port; 1082d9ba8f9eSMugunthan V N 1083d9ba8f9eSMugunthan V N if (priv->version == CPSW_VERSION_1) 1084d9ba8f9eSMugunthan V N slave_write(slave, slave->port_vlan, CPSW1_PORT_VLAN); 1085d9ba8f9eSMugunthan V N else 1086d9ba8f9eSMugunthan V N slave_write(slave, slave->port_vlan, CPSW2_PORT_VLAN); 1087d9ba8f9eSMugunthan V N cpsw_ale_add_vlan(priv->ale, slave->port_vlan, port_mask, 1088d9ba8f9eSMugunthan V N port_mask, port_mask, 0); 1089d9ba8f9eSMugunthan V N cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast, 1090d9ba8f9eSMugunthan V N port_mask, ALE_VLAN, slave->port_vlan, 0); 1091d9ba8f9eSMugunthan V N cpsw_ale_add_ucast(priv->ale, priv->mac_addr, 109256887149SGeorge McCollister priv->host_port, ALE_VLAN | ALE_SECURE, slave->port_vlan); 1093d9ba8f9eSMugunthan V N } 1094d9ba8f9eSMugunthan V N 10951e7a2e21SDaniel Mack static void soft_reset_slave(struct cpsw_slave *slave) 1096df828598SMugunthan V N { 1097df828598SMugunthan V N char name[32]; 10981e7a2e21SDaniel Mack 10991e7a2e21SDaniel Mack snprintf(name, sizeof(name), "slave-%d", slave->slave_num); 11001e7a2e21SDaniel Mack soft_reset(name, &slave->sliver->soft_reset); 11011e7a2e21SDaniel Mack } 11021e7a2e21SDaniel Mack 11031e7a2e21SDaniel Mack static void cpsw_slave_open(struct cpsw_slave *slave, struct cpsw_priv *priv) 11041e7a2e21SDaniel Mack { 1105df828598SMugunthan V N u32 slave_port; 1106df828598SMugunthan V N 11071e7a2e21SDaniel Mack soft_reset_slave(slave); 1108df828598SMugunthan V N 1109df828598SMugunthan V N /* setup priority mapping */ 1110df828598SMugunthan V N __raw_writel(RX_PRIORITY_MAPPING, &slave->sliver->rx_pri_map); 11119750a3adSRichard Cochran 11129750a3adSRichard Cochran switch (priv->version) { 11139750a3adSRichard Cochran case CPSW_VERSION_1: 11149750a3adSRichard Cochran slave_write(slave, TX_PRIORITY_MAPPING, CPSW1_TX_PRI_MAP); 11159750a3adSRichard Cochran break; 11169750a3adSRichard Cochran case CPSW_VERSION_2: 1117c193f365SMugunthan V N case CPSW_VERSION_3: 1118926489beSMugunthan V N case CPSW_VERSION_4: 11199750a3adSRichard Cochran slave_write(slave, TX_PRIORITY_MAPPING, CPSW2_TX_PRI_MAP); 11209750a3adSRichard Cochran break; 11219750a3adSRichard Cochran } 1122df828598SMugunthan V N 1123df828598SMugunthan V N /* setup max packet size, and mac address */ 1124df828598SMugunthan V N __raw_writel(priv->rx_packet_max, &slave->sliver->rx_maxlen); 1125df828598SMugunthan V N cpsw_set_slave_mac(slave, priv); 1126df828598SMugunthan V N 1127df828598SMugunthan V N slave->mac_control = 0; /* no link yet */ 1128df828598SMugunthan V N 1129df828598SMugunthan V N slave_port = cpsw_get_slave_port(priv, slave->slave_num); 1130df828598SMugunthan V N 1131d9ba8f9eSMugunthan V N if (priv->data.dual_emac) 1132d9ba8f9eSMugunthan V N cpsw_add_dual_emac_def_ale_entries(priv, slave, slave_port); 1133d9ba8f9eSMugunthan V N else 1134df828598SMugunthan V N cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast, 1135e11b220fSMugunthan V N 1 << slave_port, 0, 0, ALE_MCAST_FWD_2); 1136df828598SMugunthan V N 1137df828598SMugunthan V N slave->phy = phy_connect(priv->ndev, slave->data->phy_id, 1138f9a8f83bSFlorian Fainelli &cpsw_adjust_link, slave->data->phy_if); 1139df828598SMugunthan V N if (IS_ERR(slave->phy)) { 1140df828598SMugunthan V N dev_err(priv->dev, "phy %s not found on slave %d\n", 1141df828598SMugunthan V N slave->data->phy_id, slave->slave_num); 1142df828598SMugunthan V N slave->phy = NULL; 1143df828598SMugunthan V N } else { 1144df828598SMugunthan V N dev_info(priv->dev, "phy found : id is : 0x%x\n", 1145df828598SMugunthan V N slave->phy->phy_id); 1146df828598SMugunthan V N phy_start(slave->phy); 1147388367a5SMugunthan V N 1148388367a5SMugunthan V N /* Configure GMII_SEL register */ 1149388367a5SMugunthan V N cpsw_phy_sel(&priv->pdev->dev, slave->phy->interface, 1150388367a5SMugunthan V N slave->slave_num); 1151df828598SMugunthan V N } 1152df828598SMugunthan V N } 1153df828598SMugunthan V N 11543b72c2feSMugunthan V N static inline void cpsw_add_default_vlan(struct cpsw_priv *priv) 11553b72c2feSMugunthan V N { 11563b72c2feSMugunthan V N const int vlan = priv->data.default_vlan; 11573b72c2feSMugunthan V N const int port = priv->host_port; 11583b72c2feSMugunthan V N u32 reg; 11593b72c2feSMugunthan V N int i; 11601e5c4bc4SLennart Sorensen int unreg_mcast_mask; 11613b72c2feSMugunthan V N 11623b72c2feSMugunthan V N reg = (priv->version == CPSW_VERSION_1) ? CPSW1_PORT_VLAN : 11633b72c2feSMugunthan V N CPSW2_PORT_VLAN; 11643b72c2feSMugunthan V N 11653b72c2feSMugunthan V N writel(vlan, &priv->host_port_regs->port_vlan); 11663b72c2feSMugunthan V N 11670237c110SDaniel Mack for (i = 0; i < priv->data.slaves; i++) 11683b72c2feSMugunthan V N slave_write(priv->slaves + i, vlan, reg); 11693b72c2feSMugunthan V N 11701e5c4bc4SLennart Sorensen if (priv->ndev->flags & IFF_ALLMULTI) 11711e5c4bc4SLennart Sorensen unreg_mcast_mask = ALE_ALL_PORTS; 11721e5c4bc4SLennart Sorensen else 11731e5c4bc4SLennart Sorensen unreg_mcast_mask = ALE_PORT_1 | ALE_PORT_2; 11741e5c4bc4SLennart Sorensen 11753b72c2feSMugunthan V N cpsw_ale_add_vlan(priv->ale, vlan, ALE_ALL_PORTS << port, 11763b72c2feSMugunthan V N ALE_ALL_PORTS << port, ALE_ALL_PORTS << port, 11771e5c4bc4SLennart Sorensen unreg_mcast_mask << port); 11783b72c2feSMugunthan V N } 11793b72c2feSMugunthan V N 1180df828598SMugunthan V N static void cpsw_init_host_port(struct cpsw_priv *priv) 1181df828598SMugunthan V N { 11823b72c2feSMugunthan V N u32 control_reg; 1183d9ba8f9eSMugunthan V N u32 fifo_mode; 11843b72c2feSMugunthan V N 1185df828598SMugunthan V N /* soft reset the controller and initialize ale */ 1186df828598SMugunthan V N soft_reset("cpsw", &priv->regs->soft_reset); 1187df828598SMugunthan V N cpsw_ale_start(priv->ale); 1188df828598SMugunthan V N 1189df828598SMugunthan V N /* switch to vlan unaware mode */ 11903b72c2feSMugunthan V N cpsw_ale_control_set(priv->ale, priv->host_port, ALE_VLAN_AWARE, 11913b72c2feSMugunthan V N CPSW_ALE_VLAN_AWARE); 11923b72c2feSMugunthan V N control_reg = readl(&priv->regs->control); 11933b72c2feSMugunthan V N control_reg |= CPSW_VLAN_AWARE; 11943b72c2feSMugunthan V N writel(control_reg, &priv->regs->control); 1195d9ba8f9eSMugunthan V N fifo_mode = (priv->data.dual_emac) ? CPSW_FIFO_DUAL_MAC_MODE : 1196d9ba8f9eSMugunthan V N CPSW_FIFO_NORMAL_MODE; 1197d9ba8f9eSMugunthan V N writel(fifo_mode, &priv->host_port_regs->tx_in_ctl); 1198df828598SMugunthan V N 1199df828598SMugunthan V N /* setup host port priority mapping */ 1200df828598SMugunthan V N __raw_writel(CPDMA_TX_PRIORITY_MAP, 1201df828598SMugunthan V N &priv->host_port_regs->cpdma_tx_pri_map); 1202df828598SMugunthan V N __raw_writel(0, &priv->host_port_regs->cpdma_rx_chan_map); 1203df828598SMugunthan V N 1204df828598SMugunthan V N cpsw_ale_control_set(priv->ale, priv->host_port, 1205df828598SMugunthan V N ALE_PORT_STATE, ALE_PORT_STATE_FORWARD); 1206df828598SMugunthan V N 1207d9ba8f9eSMugunthan V N if (!priv->data.dual_emac) { 1208d9ba8f9eSMugunthan V N cpsw_ale_add_ucast(priv->ale, priv->mac_addr, priv->host_port, 1209d9ba8f9eSMugunthan V N 0, 0); 1210df828598SMugunthan V N cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast, 1211e11b220fSMugunthan V N 1 << priv->host_port, 0, 0, ALE_MCAST_FWD_2); 1212df828598SMugunthan V N } 1213d9ba8f9eSMugunthan V N } 1214df828598SMugunthan V N 1215aacebbf8SSebastian Siewior static void cpsw_slave_stop(struct cpsw_slave *slave, struct cpsw_priv *priv) 1216aacebbf8SSebastian Siewior { 12173995d265SSchuyler Patton u32 slave_port; 12183995d265SSchuyler Patton 12193995d265SSchuyler Patton slave_port = cpsw_get_slave_port(priv, slave->slave_num); 12203995d265SSchuyler Patton 1221aacebbf8SSebastian Siewior if (!slave->phy) 1222aacebbf8SSebastian Siewior return; 1223aacebbf8SSebastian Siewior phy_stop(slave->phy); 1224aacebbf8SSebastian Siewior phy_disconnect(slave->phy); 1225aacebbf8SSebastian Siewior slave->phy = NULL; 12263995d265SSchuyler Patton cpsw_ale_control_set(priv->ale, slave_port, 12273995d265SSchuyler Patton ALE_PORT_STATE, ALE_PORT_STATE_DISABLE); 1228aacebbf8SSebastian Siewior } 1229aacebbf8SSebastian Siewior 1230df828598SMugunthan V N static int cpsw_ndo_open(struct net_device *ndev) 1231df828598SMugunthan V N { 1232df828598SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 1233a11fbba9SSebastian Siewior struct cpsw_priv *prim_cpsw; 1234df828598SMugunthan V N int i, ret; 1235df828598SMugunthan V N u32 reg; 1236df828598SMugunthan V N 1237d9ba8f9eSMugunthan V N if (!cpsw_common_res_usage_state(priv)) 1238df828598SMugunthan V N cpsw_intr_disable(priv); 1239df828598SMugunthan V N netif_carrier_off(ndev); 1240df828598SMugunthan V N 1241f150bd7fSMugunthan V N pm_runtime_get_sync(&priv->pdev->dev); 1242df828598SMugunthan V N 1243549985eeSRichard Cochran reg = priv->version; 1244df828598SMugunthan V N 1245df828598SMugunthan V N dev_info(priv->dev, "initializing cpsw version %d.%d (%d)\n", 1246df828598SMugunthan V N CPSW_MAJOR_VERSION(reg), CPSW_MINOR_VERSION(reg), 1247df828598SMugunthan V N CPSW_RTL_VERSION(reg)); 1248df828598SMugunthan V N 1249df828598SMugunthan V N /* initialize host and slave ports */ 1250d9ba8f9eSMugunthan V N if (!cpsw_common_res_usage_state(priv)) 1251df828598SMugunthan V N cpsw_init_host_port(priv); 1252df828598SMugunthan V N for_each_slave(priv, cpsw_slave_open, priv); 1253df828598SMugunthan V N 12543b72c2feSMugunthan V N /* Add default VLAN */ 1255e6afea0bSMugunthan V N if (!priv->data.dual_emac) 12563b72c2feSMugunthan V N cpsw_add_default_vlan(priv); 1257e6afea0bSMugunthan V N else 1258e6afea0bSMugunthan V N cpsw_ale_add_vlan(priv->ale, priv->data.default_vlan, 1259e6afea0bSMugunthan V N ALE_ALL_PORTS << priv->host_port, 1260e6afea0bSMugunthan V N ALE_ALL_PORTS << priv->host_port, 0, 0); 12613b72c2feSMugunthan V N 1262d9ba8f9eSMugunthan V N if (!cpsw_common_res_usage_state(priv)) { 1263df828598SMugunthan V N /* setup tx dma to fixed prio and zero offset */ 1264df828598SMugunthan V N cpdma_control_set(priv->dma, CPDMA_TX_PRIO_FIXED, 1); 1265df828598SMugunthan V N cpdma_control_set(priv->dma, CPDMA_RX_BUFFER_OFFSET, 0); 1266df828598SMugunthan V N 1267d9ba8f9eSMugunthan V N /* disable priority elevation */ 1268df828598SMugunthan V N __raw_writel(0, &priv->regs->ptype); 1269df828598SMugunthan V N 1270d9ba8f9eSMugunthan V N /* enable statistics collection only on all ports */ 1271df828598SMugunthan V N __raw_writel(0x7, &priv->regs->stat_port_en); 1272df828598SMugunthan V N 12731923d6e4SMugunthan V N /* Enable internal fifo flow control */ 12741923d6e4SMugunthan V N writel(0x7, &priv->regs->flow_control); 12751923d6e4SMugunthan V N 1276df828598SMugunthan V N if (WARN_ON(!priv->data.rx_descs)) 1277df828598SMugunthan V N priv->data.rx_descs = 128; 1278df828598SMugunthan V N 1279df828598SMugunthan V N for (i = 0; i < priv->data.rx_descs; i++) { 1280df828598SMugunthan V N struct sk_buff *skb; 1281df828598SMugunthan V N 1282df828598SMugunthan V N ret = -ENOMEM; 1283aacebbf8SSebastian Siewior skb = __netdev_alloc_skb_ip_align(priv->ndev, 1284aacebbf8SSebastian Siewior priv->rx_packet_max, GFP_KERNEL); 1285df828598SMugunthan V N if (!skb) 1286aacebbf8SSebastian Siewior goto err_cleanup; 1287df828598SMugunthan V N ret = cpdma_chan_submit(priv->rxch, skb, skb->data, 1288aef614e1SSebastian Siewior skb_tailroom(skb), 0); 1289aacebbf8SSebastian Siewior if (ret < 0) { 1290aacebbf8SSebastian Siewior kfree_skb(skb); 1291aacebbf8SSebastian Siewior goto err_cleanup; 1292aacebbf8SSebastian Siewior } 1293df828598SMugunthan V N } 1294d9ba8f9eSMugunthan V N /* continue even if we didn't manage to submit all 1295d9ba8f9eSMugunthan V N * receive descs 1296d9ba8f9eSMugunthan V N */ 1297df828598SMugunthan V N cpsw_info(priv, ifup, "submitted %d rx descriptors\n", i); 1298f280e89aSMugunthan V N 1299f280e89aSMugunthan V N if (cpts_register(&priv->pdev->dev, priv->cpts, 1300f280e89aSMugunthan V N priv->data.cpts_clock_mult, 1301f280e89aSMugunthan V N priv->data.cpts_clock_shift)) 1302f280e89aSMugunthan V N dev_err(priv->dev, "error registering cpts device\n"); 1303f280e89aSMugunthan V N 1304d9ba8f9eSMugunthan V N } 1305df828598SMugunthan V N 1306ff5b8ef2SMugunthan V N /* Enable Interrupt pacing if configured */ 1307ff5b8ef2SMugunthan V N if (priv->coal_intvl != 0) { 1308ff5b8ef2SMugunthan V N struct ethtool_coalesce coal; 1309ff5b8ef2SMugunthan V N 1310ff5b8ef2SMugunthan V N coal.rx_coalesce_usecs = (priv->coal_intvl << 4); 1311ff5b8ef2SMugunthan V N cpsw_set_coalesce(ndev, &coal); 1312ff5b8ef2SMugunthan V N } 1313ff5b8ef2SMugunthan V N 1314f63a975eSMugunthan V N napi_enable(&priv->napi); 1315f63a975eSMugunthan V N cpdma_ctlr_start(priv->dma); 1316f63a975eSMugunthan V N cpsw_intr_enable(priv); 1317f63a975eSMugunthan V N 1318a11fbba9SSebastian Siewior prim_cpsw = cpsw_get_slave_priv(priv, 0); 1319a11fbba9SSebastian Siewior if (prim_cpsw->irq_enabled == false) { 1320a11fbba9SSebastian Siewior if ((priv == prim_cpsw) || !netif_running(prim_cpsw->ndev)) { 1321a11fbba9SSebastian Siewior prim_cpsw->irq_enabled = true; 13225a0266afSMugunthan V N enable_irq(prim_cpsw->irqs_table[0]); 1323a11fbba9SSebastian Siewior } 1324a11fbba9SSebastian Siewior } 1325a11fbba9SSebastian Siewior 1326d9ba8f9eSMugunthan V N if (priv->data.dual_emac) 1327d9ba8f9eSMugunthan V N priv->slaves[priv->emac_port].open_stat = true; 1328df828598SMugunthan V N return 0; 1329df828598SMugunthan V N 1330aacebbf8SSebastian Siewior err_cleanup: 1331aacebbf8SSebastian Siewior cpdma_ctlr_stop(priv->dma); 1332aacebbf8SSebastian Siewior for_each_slave(priv, cpsw_slave_stop, priv); 1333aacebbf8SSebastian Siewior pm_runtime_put_sync(&priv->pdev->dev); 1334aacebbf8SSebastian Siewior netif_carrier_off(priv->ndev); 1335aacebbf8SSebastian Siewior return ret; 1336df828598SMugunthan V N } 1337df828598SMugunthan V N 1338df828598SMugunthan V N static int cpsw_ndo_stop(struct net_device *ndev) 1339df828598SMugunthan V N { 1340df828598SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 1341df828598SMugunthan V N 1342df828598SMugunthan V N cpsw_info(priv, ifdown, "shutting down cpsw device\n"); 1343df828598SMugunthan V N netif_stop_queue(priv->ndev); 1344df828598SMugunthan V N napi_disable(&priv->napi); 1345df828598SMugunthan V N netif_carrier_off(priv->ndev); 1346d9ba8f9eSMugunthan V N 1347d9ba8f9eSMugunthan V N if (cpsw_common_res_usage_state(priv) <= 1) { 1348f280e89aSMugunthan V N cpts_unregister(priv->cpts); 134971380f9bSMugunthan V N cpsw_intr_disable(priv); 135071380f9bSMugunthan V N cpdma_ctlr_stop(priv->dma); 1351df828598SMugunthan V N cpsw_ale_stop(priv->ale); 1352d9ba8f9eSMugunthan V N } 1353df828598SMugunthan V N for_each_slave(priv, cpsw_slave_stop, priv); 1354f150bd7fSMugunthan V N pm_runtime_put_sync(&priv->pdev->dev); 1355d9ba8f9eSMugunthan V N if (priv->data.dual_emac) 1356d9ba8f9eSMugunthan V N priv->slaves[priv->emac_port].open_stat = false; 1357df828598SMugunthan V N return 0; 1358df828598SMugunthan V N } 1359df828598SMugunthan V N 1360df828598SMugunthan V N static netdev_tx_t cpsw_ndo_start_xmit(struct sk_buff *skb, 1361df828598SMugunthan V N struct net_device *ndev) 1362df828598SMugunthan V N { 1363df828598SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 1364df828598SMugunthan V N int ret; 1365df828598SMugunthan V N 1366df828598SMugunthan V N ndev->trans_start = jiffies; 1367df828598SMugunthan V N 1368df828598SMugunthan V N if (skb_padto(skb, CPSW_MIN_PACKET_SIZE)) { 1369df828598SMugunthan V N cpsw_err(priv, tx_err, "packet pad failed\n"); 13708dc43ddcSTobias Klauser ndev->stats.tx_dropped++; 1371df828598SMugunthan V N return NETDEV_TX_OK; 1372df828598SMugunthan V N } 1373df828598SMugunthan V N 13749232b16dSMugunthan V N if (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP && 13759232b16dSMugunthan V N priv->cpts->tx_enable) 13762e5b38abSRichard Cochran skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 13772e5b38abSRichard Cochran 13782e5b38abSRichard Cochran skb_tx_timestamp(skb); 13792e5b38abSRichard Cochran 1380d9ba8f9eSMugunthan V N ret = cpsw_tx_packet_submit(ndev, priv, skb); 1381df828598SMugunthan V N if (unlikely(ret != 0)) { 1382df828598SMugunthan V N cpsw_err(priv, tx_err, "desc submit failed\n"); 1383df828598SMugunthan V N goto fail; 1384df828598SMugunthan V N } 1385df828598SMugunthan V N 1386fae50823SMugunthan V N /* If there is no more tx desc left free then we need to 1387fae50823SMugunthan V N * tell the kernel to stop sending us tx frames. 1388fae50823SMugunthan V N */ 1389d35162f8SDaniel Mack if (unlikely(!cpdma_check_free_tx_desc(priv->txch))) 1390fae50823SMugunthan V N netif_stop_queue(ndev); 1391fae50823SMugunthan V N 1392df828598SMugunthan V N return NETDEV_TX_OK; 1393df828598SMugunthan V N fail: 13948dc43ddcSTobias Klauser ndev->stats.tx_dropped++; 1395df828598SMugunthan V N netif_stop_queue(ndev); 1396df828598SMugunthan V N return NETDEV_TX_BUSY; 1397df828598SMugunthan V N } 1398df828598SMugunthan V N 13992e5b38abSRichard Cochran #ifdef CONFIG_TI_CPTS 14002e5b38abSRichard Cochran 14012e5b38abSRichard Cochran static void cpsw_hwtstamp_v1(struct cpsw_priv *priv) 14022e5b38abSRichard Cochran { 1403e86ac13bSMugunthan V N struct cpsw_slave *slave = &priv->slaves[priv->data.active_slave]; 14042e5b38abSRichard Cochran u32 ts_en, seq_id; 14052e5b38abSRichard Cochran 14069232b16dSMugunthan V N if (!priv->cpts->tx_enable && !priv->cpts->rx_enable) { 14072e5b38abSRichard Cochran slave_write(slave, 0, CPSW1_TS_CTL); 14082e5b38abSRichard Cochran return; 14092e5b38abSRichard Cochran } 14102e5b38abSRichard Cochran 14112e5b38abSRichard Cochran seq_id = (30 << CPSW_V1_SEQ_ID_OFS_SHIFT) | ETH_P_1588; 14122e5b38abSRichard Cochran ts_en = EVENT_MSG_BITS << CPSW_V1_MSG_TYPE_OFS; 14132e5b38abSRichard Cochran 14149232b16dSMugunthan V N if (priv->cpts->tx_enable) 14152e5b38abSRichard Cochran ts_en |= CPSW_V1_TS_TX_EN; 14162e5b38abSRichard Cochran 14179232b16dSMugunthan V N if (priv->cpts->rx_enable) 14182e5b38abSRichard Cochran ts_en |= CPSW_V1_TS_RX_EN; 14192e5b38abSRichard Cochran 14202e5b38abSRichard Cochran slave_write(slave, ts_en, CPSW1_TS_CTL); 14212e5b38abSRichard Cochran slave_write(slave, seq_id, CPSW1_TS_SEQ_LTYPE); 14222e5b38abSRichard Cochran } 14232e5b38abSRichard Cochran 14242e5b38abSRichard Cochran static void cpsw_hwtstamp_v2(struct cpsw_priv *priv) 14252e5b38abSRichard Cochran { 1426d9ba8f9eSMugunthan V N struct cpsw_slave *slave; 14272e5b38abSRichard Cochran u32 ctrl, mtype; 14282e5b38abSRichard Cochran 1429d9ba8f9eSMugunthan V N if (priv->data.dual_emac) 1430d9ba8f9eSMugunthan V N slave = &priv->slaves[priv->emac_port]; 1431d9ba8f9eSMugunthan V N else 1432e86ac13bSMugunthan V N slave = &priv->slaves[priv->data.active_slave]; 1433d9ba8f9eSMugunthan V N 14342e5b38abSRichard Cochran ctrl = slave_read(slave, CPSW2_CONTROL); 143509c55372SGeorge Cherian switch (priv->version) { 143609c55372SGeorge Cherian case CPSW_VERSION_2: 143709c55372SGeorge Cherian ctrl &= ~CTRL_V2_ALL_TS_MASK; 14382e5b38abSRichard Cochran 14399232b16dSMugunthan V N if (priv->cpts->tx_enable) 144009c55372SGeorge Cherian ctrl |= CTRL_V2_TX_TS_BITS; 14412e5b38abSRichard Cochran 14429232b16dSMugunthan V N if (priv->cpts->rx_enable) 144309c55372SGeorge Cherian ctrl |= CTRL_V2_RX_TS_BITS; 144409c55372SGeorge Cherian break; 144509c55372SGeorge Cherian case CPSW_VERSION_3: 144609c55372SGeorge Cherian default: 144709c55372SGeorge Cherian ctrl &= ~CTRL_V3_ALL_TS_MASK; 144809c55372SGeorge Cherian 144909c55372SGeorge Cherian if (priv->cpts->tx_enable) 145009c55372SGeorge Cherian ctrl |= CTRL_V3_TX_TS_BITS; 145109c55372SGeorge Cherian 145209c55372SGeorge Cherian if (priv->cpts->rx_enable) 145309c55372SGeorge Cherian ctrl |= CTRL_V3_RX_TS_BITS; 145409c55372SGeorge Cherian break; 145509c55372SGeorge Cherian } 14562e5b38abSRichard Cochran 14572e5b38abSRichard Cochran mtype = (30 << TS_SEQ_ID_OFFSET_SHIFT) | EVENT_MSG_BITS; 14582e5b38abSRichard Cochran 14592e5b38abSRichard Cochran slave_write(slave, mtype, CPSW2_TS_SEQ_MTYPE); 14602e5b38abSRichard Cochran slave_write(slave, ctrl, CPSW2_CONTROL); 14612e5b38abSRichard Cochran __raw_writel(ETH_P_1588, &priv->regs->ts_ltype); 14622e5b38abSRichard Cochran } 14632e5b38abSRichard Cochran 1464a5b4145bSBen Hutchings static int cpsw_hwtstamp_set(struct net_device *dev, struct ifreq *ifr) 14652e5b38abSRichard Cochran { 14663177bf6fSMugunthan V N struct cpsw_priv *priv = netdev_priv(dev); 14679232b16dSMugunthan V N struct cpts *cpts = priv->cpts; 14682e5b38abSRichard Cochran struct hwtstamp_config cfg; 14692e5b38abSRichard Cochran 14702ee91e54SBen Hutchings if (priv->version != CPSW_VERSION_1 && 1471f7d403cbSGeorge Cherian priv->version != CPSW_VERSION_2 && 1472f7d403cbSGeorge Cherian priv->version != CPSW_VERSION_3) 14732ee91e54SBen Hutchings return -EOPNOTSUPP; 14742ee91e54SBen Hutchings 14752e5b38abSRichard Cochran if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg))) 14762e5b38abSRichard Cochran return -EFAULT; 14772e5b38abSRichard Cochran 14782e5b38abSRichard Cochran /* reserved for future extensions */ 14792e5b38abSRichard Cochran if (cfg.flags) 14802e5b38abSRichard Cochran return -EINVAL; 14812e5b38abSRichard Cochran 14822ee91e54SBen Hutchings if (cfg.tx_type != HWTSTAMP_TX_OFF && cfg.tx_type != HWTSTAMP_TX_ON) 14832e5b38abSRichard Cochran return -ERANGE; 14842e5b38abSRichard Cochran 14852e5b38abSRichard Cochran switch (cfg.rx_filter) { 14862e5b38abSRichard Cochran case HWTSTAMP_FILTER_NONE: 14872e5b38abSRichard Cochran cpts->rx_enable = 0; 14882e5b38abSRichard Cochran break; 14892e5b38abSRichard Cochran case HWTSTAMP_FILTER_ALL: 14902e5b38abSRichard Cochran case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: 14912e5b38abSRichard Cochran case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: 14922e5b38abSRichard Cochran case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: 14932e5b38abSRichard Cochran return -ERANGE; 14942e5b38abSRichard Cochran case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: 14952e5b38abSRichard Cochran case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 14962e5b38abSRichard Cochran case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 14972e5b38abSRichard Cochran case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: 14982e5b38abSRichard Cochran case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: 14992e5b38abSRichard Cochran case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: 15002e5b38abSRichard Cochran case HWTSTAMP_FILTER_PTP_V2_EVENT: 15012e5b38abSRichard Cochran case HWTSTAMP_FILTER_PTP_V2_SYNC: 15022e5b38abSRichard Cochran case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 15032e5b38abSRichard Cochran cpts->rx_enable = 1; 15042e5b38abSRichard Cochran cfg.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT; 15052e5b38abSRichard Cochran break; 15062e5b38abSRichard Cochran default: 15072e5b38abSRichard Cochran return -ERANGE; 15082e5b38abSRichard Cochran } 15092e5b38abSRichard Cochran 15102ee91e54SBen Hutchings cpts->tx_enable = cfg.tx_type == HWTSTAMP_TX_ON; 15112ee91e54SBen Hutchings 15122e5b38abSRichard Cochran switch (priv->version) { 15132e5b38abSRichard Cochran case CPSW_VERSION_1: 15142e5b38abSRichard Cochran cpsw_hwtstamp_v1(priv); 15152e5b38abSRichard Cochran break; 15162e5b38abSRichard Cochran case CPSW_VERSION_2: 1517f7d403cbSGeorge Cherian case CPSW_VERSION_3: 15182e5b38abSRichard Cochran cpsw_hwtstamp_v2(priv); 15192e5b38abSRichard Cochran break; 15202e5b38abSRichard Cochran default: 15212ee91e54SBen Hutchings WARN_ON(1); 15222e5b38abSRichard Cochran } 15232e5b38abSRichard Cochran 15242e5b38abSRichard Cochran return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0; 15252e5b38abSRichard Cochran } 15262e5b38abSRichard Cochran 1527a5b4145bSBen Hutchings static int cpsw_hwtstamp_get(struct net_device *dev, struct ifreq *ifr) 1528a5b4145bSBen Hutchings { 1529a5b4145bSBen Hutchings struct cpsw_priv *priv = netdev_priv(dev); 1530a5b4145bSBen Hutchings struct cpts *cpts = priv->cpts; 1531a5b4145bSBen Hutchings struct hwtstamp_config cfg; 1532a5b4145bSBen Hutchings 1533a5b4145bSBen Hutchings if (priv->version != CPSW_VERSION_1 && 1534f7d403cbSGeorge Cherian priv->version != CPSW_VERSION_2 && 1535f7d403cbSGeorge Cherian priv->version != CPSW_VERSION_3) 1536a5b4145bSBen Hutchings return -EOPNOTSUPP; 1537a5b4145bSBen Hutchings 1538a5b4145bSBen Hutchings cfg.flags = 0; 1539a5b4145bSBen Hutchings cfg.tx_type = cpts->tx_enable ? HWTSTAMP_TX_ON : HWTSTAMP_TX_OFF; 1540a5b4145bSBen Hutchings cfg.rx_filter = (cpts->rx_enable ? 1541a5b4145bSBen Hutchings HWTSTAMP_FILTER_PTP_V2_EVENT : HWTSTAMP_FILTER_NONE); 1542a5b4145bSBen Hutchings 1543a5b4145bSBen Hutchings return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0; 1544a5b4145bSBen Hutchings } 1545a5b4145bSBen Hutchings 15462e5b38abSRichard Cochran #endif /*CONFIG_TI_CPTS*/ 15472e5b38abSRichard Cochran 15482e5b38abSRichard Cochran static int cpsw_ndo_ioctl(struct net_device *dev, struct ifreq *req, int cmd) 15492e5b38abSRichard Cochran { 155011f2c988SMugunthan V N struct cpsw_priv *priv = netdev_priv(dev); 155111f2c988SMugunthan V N int slave_no = cpsw_slave_index(priv); 155211f2c988SMugunthan V N 15532e5b38abSRichard Cochran if (!netif_running(dev)) 15542e5b38abSRichard Cochran return -EINVAL; 15552e5b38abSRichard Cochran 155611f2c988SMugunthan V N switch (cmd) { 15572e5b38abSRichard Cochran #ifdef CONFIG_TI_CPTS 155811f2c988SMugunthan V N case SIOCSHWTSTAMP: 1559a5b4145bSBen Hutchings return cpsw_hwtstamp_set(dev, req); 1560a5b4145bSBen Hutchings case SIOCGHWTSTAMP: 1561a5b4145bSBen Hutchings return cpsw_hwtstamp_get(dev, req); 15622e5b38abSRichard Cochran #endif 15632e5b38abSRichard Cochran } 15642e5b38abSRichard Cochran 1565c1b59947SStefan Sørensen if (!priv->slaves[slave_no].phy) 1566c1b59947SStefan Sørensen return -EOPNOTSUPP; 1567c1b59947SStefan Sørensen return phy_mii_ioctl(priv->slaves[slave_no].phy, req, cmd); 156811f2c988SMugunthan V N } 156911f2c988SMugunthan V N 1570df828598SMugunthan V N static void cpsw_ndo_tx_timeout(struct net_device *ndev) 1571df828598SMugunthan V N { 1572df828598SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 1573df828598SMugunthan V N 1574df828598SMugunthan V N cpsw_err(priv, tx_err, "transmit timeout, restarting dma\n"); 15758dc43ddcSTobias Klauser ndev->stats.tx_errors++; 1576df828598SMugunthan V N cpsw_intr_disable(priv); 1577df828598SMugunthan V N cpdma_chan_stop(priv->txch); 1578df828598SMugunthan V N cpdma_chan_start(priv->txch); 1579df828598SMugunthan V N cpsw_intr_enable(priv); 1580df828598SMugunthan V N } 1581df828598SMugunthan V N 1582dcfd8d58SMugunthan V N static int cpsw_ndo_set_mac_address(struct net_device *ndev, void *p) 1583dcfd8d58SMugunthan V N { 1584dcfd8d58SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 1585dcfd8d58SMugunthan V N struct sockaddr *addr = (struct sockaddr *)p; 1586dcfd8d58SMugunthan V N int flags = 0; 1587dcfd8d58SMugunthan V N u16 vid = 0; 1588dcfd8d58SMugunthan V N 1589dcfd8d58SMugunthan V N if (!is_valid_ether_addr(addr->sa_data)) 1590dcfd8d58SMugunthan V N return -EADDRNOTAVAIL; 1591dcfd8d58SMugunthan V N 1592dcfd8d58SMugunthan V N if (priv->data.dual_emac) { 1593dcfd8d58SMugunthan V N vid = priv->slaves[priv->emac_port].port_vlan; 1594dcfd8d58SMugunthan V N flags = ALE_VLAN; 1595dcfd8d58SMugunthan V N } 1596dcfd8d58SMugunthan V N 1597dcfd8d58SMugunthan V N cpsw_ale_del_ucast(priv->ale, priv->mac_addr, priv->host_port, 1598dcfd8d58SMugunthan V N flags, vid); 1599dcfd8d58SMugunthan V N cpsw_ale_add_ucast(priv->ale, addr->sa_data, priv->host_port, 1600dcfd8d58SMugunthan V N flags, vid); 1601dcfd8d58SMugunthan V N 1602dcfd8d58SMugunthan V N memcpy(priv->mac_addr, addr->sa_data, ETH_ALEN); 1603dcfd8d58SMugunthan V N memcpy(ndev->dev_addr, priv->mac_addr, ETH_ALEN); 1604dcfd8d58SMugunthan V N for_each_slave(priv, cpsw_set_slave_mac, priv); 1605dcfd8d58SMugunthan V N 1606dcfd8d58SMugunthan V N return 0; 1607dcfd8d58SMugunthan V N } 1608dcfd8d58SMugunthan V N 1609df828598SMugunthan V N #ifdef CONFIG_NET_POLL_CONTROLLER 1610df828598SMugunthan V N static void cpsw_ndo_poll_controller(struct net_device *ndev) 1611df828598SMugunthan V N { 1612df828598SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 1613df828598SMugunthan V N 1614df828598SMugunthan V N cpsw_intr_disable(priv); 161592cb13fbSFelipe Balbi cpsw_rx_interrupt(priv->irqs_table[0], priv); 161692cb13fbSFelipe Balbi cpsw_tx_interrupt(priv->irqs_table[1], priv); 1617df828598SMugunthan V N cpsw_intr_enable(priv); 1618df828598SMugunthan V N } 1619df828598SMugunthan V N #endif 1620df828598SMugunthan V N 16213b72c2feSMugunthan V N static inline int cpsw_add_vlan_ale_entry(struct cpsw_priv *priv, 16223b72c2feSMugunthan V N unsigned short vid) 16233b72c2feSMugunthan V N { 16243b72c2feSMugunthan V N int ret; 16259f6bd8faSMugunthan V N int unreg_mcast_mask = 0; 16269f6bd8faSMugunthan V N u32 port_mask; 16279f6bd8faSMugunthan V N 16289f6bd8faSMugunthan V N if (priv->data.dual_emac) { 16299f6bd8faSMugunthan V N port_mask = (1 << (priv->emac_port + 1)) | ALE_PORT_HOST; 16309f6bd8faSMugunthan V N 16319f6bd8faSMugunthan V N if (priv->ndev->flags & IFF_ALLMULTI) 16329f6bd8faSMugunthan V N unreg_mcast_mask = port_mask; 16339f6bd8faSMugunthan V N } else { 16349f6bd8faSMugunthan V N port_mask = ALE_ALL_PORTS; 16351e5c4bc4SLennart Sorensen 16361e5c4bc4SLennart Sorensen if (priv->ndev->flags & IFF_ALLMULTI) 16371e5c4bc4SLennart Sorensen unreg_mcast_mask = ALE_ALL_PORTS; 16381e5c4bc4SLennart Sorensen else 16391e5c4bc4SLennart Sorensen unreg_mcast_mask = ALE_PORT_1 | ALE_PORT_2; 16409f6bd8faSMugunthan V N } 16413b72c2feSMugunthan V N 16429f6bd8faSMugunthan V N ret = cpsw_ale_add_vlan(priv->ale, vid, port_mask, 0, port_mask, 16431e5c4bc4SLennart Sorensen unreg_mcast_mask << priv->host_port); 16443b72c2feSMugunthan V N if (ret != 0) 16453b72c2feSMugunthan V N return ret; 16463b72c2feSMugunthan V N 16473b72c2feSMugunthan V N ret = cpsw_ale_add_ucast(priv->ale, priv->mac_addr, 16483b72c2feSMugunthan V N priv->host_port, ALE_VLAN, vid); 16493b72c2feSMugunthan V N if (ret != 0) 16503b72c2feSMugunthan V N goto clean_vid; 16513b72c2feSMugunthan V N 16523b72c2feSMugunthan V N ret = cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast, 16539f6bd8faSMugunthan V N port_mask, ALE_VLAN, vid, 0); 16543b72c2feSMugunthan V N if (ret != 0) 16553b72c2feSMugunthan V N goto clean_vlan_ucast; 16563b72c2feSMugunthan V N return 0; 16573b72c2feSMugunthan V N 16583b72c2feSMugunthan V N clean_vlan_ucast: 16593b72c2feSMugunthan V N cpsw_ale_del_ucast(priv->ale, priv->mac_addr, 16603b72c2feSMugunthan V N priv->host_port, ALE_VLAN, vid); 16613b72c2feSMugunthan V N clean_vid: 16623b72c2feSMugunthan V N cpsw_ale_del_vlan(priv->ale, vid, 0); 16633b72c2feSMugunthan V N return ret; 16643b72c2feSMugunthan V N } 16653b72c2feSMugunthan V N 16663b72c2feSMugunthan V N static int cpsw_ndo_vlan_rx_add_vid(struct net_device *ndev, 166780d5c368SPatrick McHardy __be16 proto, u16 vid) 16683b72c2feSMugunthan V N { 16693b72c2feSMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 16703b72c2feSMugunthan V N 16713b72c2feSMugunthan V N if (vid == priv->data.default_vlan) 16723b72c2feSMugunthan V N return 0; 16733b72c2feSMugunthan V N 167402a54164SMugunthan V N if (priv->data.dual_emac) { 167502a54164SMugunthan V N /* In dual EMAC, reserved VLAN id should not be used for 167602a54164SMugunthan V N * creating VLAN interfaces as this can break the dual 167702a54164SMugunthan V N * EMAC port separation 167802a54164SMugunthan V N */ 167902a54164SMugunthan V N int i; 168002a54164SMugunthan V N 168102a54164SMugunthan V N for (i = 0; i < priv->data.slaves; i++) { 168202a54164SMugunthan V N if (vid == priv->slaves[i].port_vlan) 168302a54164SMugunthan V N return -EINVAL; 168402a54164SMugunthan V N } 168502a54164SMugunthan V N } 168602a54164SMugunthan V N 16873b72c2feSMugunthan V N dev_info(priv->dev, "Adding vlanid %d to vlan filter\n", vid); 16883b72c2feSMugunthan V N return cpsw_add_vlan_ale_entry(priv, vid); 16893b72c2feSMugunthan V N } 16903b72c2feSMugunthan V N 16913b72c2feSMugunthan V N static int cpsw_ndo_vlan_rx_kill_vid(struct net_device *ndev, 169280d5c368SPatrick McHardy __be16 proto, u16 vid) 16933b72c2feSMugunthan V N { 16943b72c2feSMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 16953b72c2feSMugunthan V N int ret; 16963b72c2feSMugunthan V N 16973b72c2feSMugunthan V N if (vid == priv->data.default_vlan) 16983b72c2feSMugunthan V N return 0; 16993b72c2feSMugunthan V N 170002a54164SMugunthan V N if (priv->data.dual_emac) { 170102a54164SMugunthan V N int i; 170202a54164SMugunthan V N 170302a54164SMugunthan V N for (i = 0; i < priv->data.slaves; i++) { 170402a54164SMugunthan V N if (vid == priv->slaves[i].port_vlan) 170502a54164SMugunthan V N return -EINVAL; 170602a54164SMugunthan V N } 170702a54164SMugunthan V N } 170802a54164SMugunthan V N 17093b72c2feSMugunthan V N dev_info(priv->dev, "removing vlanid %d from vlan filter\n", vid); 17103b72c2feSMugunthan V N ret = cpsw_ale_del_vlan(priv->ale, vid, 0); 17113b72c2feSMugunthan V N if (ret != 0) 17123b72c2feSMugunthan V N return ret; 17133b72c2feSMugunthan V N 17143b72c2feSMugunthan V N ret = cpsw_ale_del_ucast(priv->ale, priv->mac_addr, 17153b72c2feSMugunthan V N priv->host_port, ALE_VLAN, vid); 17163b72c2feSMugunthan V N if (ret != 0) 17173b72c2feSMugunthan V N return ret; 17183b72c2feSMugunthan V N 17193b72c2feSMugunthan V N return cpsw_ale_del_mcast(priv->ale, priv->ndev->broadcast, 17203b72c2feSMugunthan V N 0, ALE_VLAN, vid); 17213b72c2feSMugunthan V N } 17223b72c2feSMugunthan V N 1723df828598SMugunthan V N static const struct net_device_ops cpsw_netdev_ops = { 1724df828598SMugunthan V N .ndo_open = cpsw_ndo_open, 1725df828598SMugunthan V N .ndo_stop = cpsw_ndo_stop, 1726df828598SMugunthan V N .ndo_start_xmit = cpsw_ndo_start_xmit, 1727dcfd8d58SMugunthan V N .ndo_set_mac_address = cpsw_ndo_set_mac_address, 17282e5b38abSRichard Cochran .ndo_do_ioctl = cpsw_ndo_ioctl, 1729df828598SMugunthan V N .ndo_validate_addr = eth_validate_addr, 17305c473ed2SDavid S. Miller .ndo_change_mtu = eth_change_mtu, 1731df828598SMugunthan V N .ndo_tx_timeout = cpsw_ndo_tx_timeout, 17325c50a856SMugunthan V N .ndo_set_rx_mode = cpsw_ndo_set_rx_mode, 1733df828598SMugunthan V N #ifdef CONFIG_NET_POLL_CONTROLLER 1734df828598SMugunthan V N .ndo_poll_controller = cpsw_ndo_poll_controller, 1735df828598SMugunthan V N #endif 17363b72c2feSMugunthan V N .ndo_vlan_rx_add_vid = cpsw_ndo_vlan_rx_add_vid, 17373b72c2feSMugunthan V N .ndo_vlan_rx_kill_vid = cpsw_ndo_vlan_rx_kill_vid, 1738df828598SMugunthan V N }; 1739df828598SMugunthan V N 174052c4f0ecSMugunthan V N static int cpsw_get_regs_len(struct net_device *ndev) 174152c4f0ecSMugunthan V N { 174252c4f0ecSMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 174352c4f0ecSMugunthan V N 174452c4f0ecSMugunthan V N return priv->data.ale_entries * ALE_ENTRY_WORDS * sizeof(u32); 174552c4f0ecSMugunthan V N } 174652c4f0ecSMugunthan V N 174752c4f0ecSMugunthan V N static void cpsw_get_regs(struct net_device *ndev, 174852c4f0ecSMugunthan V N struct ethtool_regs *regs, void *p) 174952c4f0ecSMugunthan V N { 175052c4f0ecSMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 175152c4f0ecSMugunthan V N u32 *reg = p; 175252c4f0ecSMugunthan V N 175352c4f0ecSMugunthan V N /* update CPSW IP version */ 175452c4f0ecSMugunthan V N regs->version = priv->version; 175552c4f0ecSMugunthan V N 175652c4f0ecSMugunthan V N cpsw_ale_dump(priv->ale, reg); 175752c4f0ecSMugunthan V N } 175852c4f0ecSMugunthan V N 1759df828598SMugunthan V N static void cpsw_get_drvinfo(struct net_device *ndev, 1760df828598SMugunthan V N struct ethtool_drvinfo *info) 1761df828598SMugunthan V N { 1762df828598SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 17637826d43fSJiri Pirko 176452c4f0ecSMugunthan V N strlcpy(info->driver, "cpsw", sizeof(info->driver)); 17657826d43fSJiri Pirko strlcpy(info->version, "1.0", sizeof(info->version)); 17667826d43fSJiri Pirko strlcpy(info->bus_info, priv->pdev->name, sizeof(info->bus_info)); 176752c4f0ecSMugunthan V N info->regdump_len = cpsw_get_regs_len(ndev); 1768df828598SMugunthan V N } 1769df828598SMugunthan V N 1770df828598SMugunthan V N static u32 cpsw_get_msglevel(struct net_device *ndev) 1771df828598SMugunthan V N { 1772df828598SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 1773df828598SMugunthan V N return priv->msg_enable; 1774df828598SMugunthan V N } 1775df828598SMugunthan V N 1776df828598SMugunthan V N static void cpsw_set_msglevel(struct net_device *ndev, u32 value) 1777df828598SMugunthan V N { 1778df828598SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 1779df828598SMugunthan V N priv->msg_enable = value; 1780df828598SMugunthan V N } 1781df828598SMugunthan V N 17822e5b38abSRichard Cochran static int cpsw_get_ts_info(struct net_device *ndev, 17832e5b38abSRichard Cochran struct ethtool_ts_info *info) 17842e5b38abSRichard Cochran { 17852e5b38abSRichard Cochran #ifdef CONFIG_TI_CPTS 17862e5b38abSRichard Cochran struct cpsw_priv *priv = netdev_priv(ndev); 17872e5b38abSRichard Cochran 17882e5b38abSRichard Cochran info->so_timestamping = 17892e5b38abSRichard Cochran SOF_TIMESTAMPING_TX_HARDWARE | 17902e5b38abSRichard Cochran SOF_TIMESTAMPING_TX_SOFTWARE | 17912e5b38abSRichard Cochran SOF_TIMESTAMPING_RX_HARDWARE | 17922e5b38abSRichard Cochran SOF_TIMESTAMPING_RX_SOFTWARE | 17932e5b38abSRichard Cochran SOF_TIMESTAMPING_SOFTWARE | 17942e5b38abSRichard Cochran SOF_TIMESTAMPING_RAW_HARDWARE; 17959232b16dSMugunthan V N info->phc_index = priv->cpts->phc_index; 17962e5b38abSRichard Cochran info->tx_types = 17972e5b38abSRichard Cochran (1 << HWTSTAMP_TX_OFF) | 17982e5b38abSRichard Cochran (1 << HWTSTAMP_TX_ON); 17992e5b38abSRichard Cochran info->rx_filters = 18002e5b38abSRichard Cochran (1 << HWTSTAMP_FILTER_NONE) | 18012e5b38abSRichard Cochran (1 << HWTSTAMP_FILTER_PTP_V2_EVENT); 18022e5b38abSRichard Cochran #else 18032e5b38abSRichard Cochran info->so_timestamping = 18042e5b38abSRichard Cochran SOF_TIMESTAMPING_TX_SOFTWARE | 18052e5b38abSRichard Cochran SOF_TIMESTAMPING_RX_SOFTWARE | 18062e5b38abSRichard Cochran SOF_TIMESTAMPING_SOFTWARE; 18072e5b38abSRichard Cochran info->phc_index = -1; 18082e5b38abSRichard Cochran info->tx_types = 0; 18092e5b38abSRichard Cochran info->rx_filters = 0; 18102e5b38abSRichard Cochran #endif 18112e5b38abSRichard Cochran return 0; 18122e5b38abSRichard Cochran } 18132e5b38abSRichard Cochran 1814d3bb9c58SMugunthan V N static int cpsw_get_settings(struct net_device *ndev, 1815d3bb9c58SMugunthan V N struct ethtool_cmd *ecmd) 1816d3bb9c58SMugunthan V N { 1817d3bb9c58SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 1818d3bb9c58SMugunthan V N int slave_no = cpsw_slave_index(priv); 1819d3bb9c58SMugunthan V N 1820d3bb9c58SMugunthan V N if (priv->slaves[slave_no].phy) 1821d3bb9c58SMugunthan V N return phy_ethtool_gset(priv->slaves[slave_no].phy, ecmd); 1822d3bb9c58SMugunthan V N else 1823d3bb9c58SMugunthan V N return -EOPNOTSUPP; 1824d3bb9c58SMugunthan V N } 1825d3bb9c58SMugunthan V N 1826d3bb9c58SMugunthan V N static int cpsw_set_settings(struct net_device *ndev, struct ethtool_cmd *ecmd) 1827d3bb9c58SMugunthan V N { 1828d3bb9c58SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 1829d3bb9c58SMugunthan V N int slave_no = cpsw_slave_index(priv); 1830d3bb9c58SMugunthan V N 1831d3bb9c58SMugunthan V N if (priv->slaves[slave_no].phy) 1832d3bb9c58SMugunthan V N return phy_ethtool_sset(priv->slaves[slave_no].phy, ecmd); 1833d3bb9c58SMugunthan V N else 1834d3bb9c58SMugunthan V N return -EOPNOTSUPP; 1835d3bb9c58SMugunthan V N } 1836d3bb9c58SMugunthan V N 1837d8a64420SMatus Ujhelyi static void cpsw_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol) 1838d8a64420SMatus Ujhelyi { 1839d8a64420SMatus Ujhelyi struct cpsw_priv *priv = netdev_priv(ndev); 1840d8a64420SMatus Ujhelyi int slave_no = cpsw_slave_index(priv); 1841d8a64420SMatus Ujhelyi 1842d8a64420SMatus Ujhelyi wol->supported = 0; 1843d8a64420SMatus Ujhelyi wol->wolopts = 0; 1844d8a64420SMatus Ujhelyi 1845d8a64420SMatus Ujhelyi if (priv->slaves[slave_no].phy) 1846d8a64420SMatus Ujhelyi phy_ethtool_get_wol(priv->slaves[slave_no].phy, wol); 1847d8a64420SMatus Ujhelyi } 1848d8a64420SMatus Ujhelyi 1849d8a64420SMatus Ujhelyi static int cpsw_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol) 1850d8a64420SMatus Ujhelyi { 1851d8a64420SMatus Ujhelyi struct cpsw_priv *priv = netdev_priv(ndev); 1852d8a64420SMatus Ujhelyi int slave_no = cpsw_slave_index(priv); 1853d8a64420SMatus Ujhelyi 1854d8a64420SMatus Ujhelyi if (priv->slaves[slave_no].phy) 1855d8a64420SMatus Ujhelyi return phy_ethtool_set_wol(priv->slaves[slave_no].phy, wol); 1856d8a64420SMatus Ujhelyi else 1857d8a64420SMatus Ujhelyi return -EOPNOTSUPP; 1858d8a64420SMatus Ujhelyi } 1859d8a64420SMatus Ujhelyi 18601923d6e4SMugunthan V N static void cpsw_get_pauseparam(struct net_device *ndev, 18611923d6e4SMugunthan V N struct ethtool_pauseparam *pause) 18621923d6e4SMugunthan V N { 18631923d6e4SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 18641923d6e4SMugunthan V N 18651923d6e4SMugunthan V N pause->autoneg = AUTONEG_DISABLE; 18661923d6e4SMugunthan V N pause->rx_pause = priv->rx_pause ? true : false; 18671923d6e4SMugunthan V N pause->tx_pause = priv->tx_pause ? true : false; 18681923d6e4SMugunthan V N } 18691923d6e4SMugunthan V N 18701923d6e4SMugunthan V N static int cpsw_set_pauseparam(struct net_device *ndev, 18711923d6e4SMugunthan V N struct ethtool_pauseparam *pause) 18721923d6e4SMugunthan V N { 18731923d6e4SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 18741923d6e4SMugunthan V N bool link; 18751923d6e4SMugunthan V N 18761923d6e4SMugunthan V N priv->rx_pause = pause->rx_pause ? true : false; 18771923d6e4SMugunthan V N priv->tx_pause = pause->tx_pause ? true : false; 18781923d6e4SMugunthan V N 18791923d6e4SMugunthan V N for_each_slave(priv, _cpsw_adjust_link, priv, &link); 18801923d6e4SMugunthan V N 18811923d6e4SMugunthan V N return 0; 18821923d6e4SMugunthan V N } 18831923d6e4SMugunthan V N 1884df828598SMugunthan V N static const struct ethtool_ops cpsw_ethtool_ops = { 1885df828598SMugunthan V N .get_drvinfo = cpsw_get_drvinfo, 1886df828598SMugunthan V N .get_msglevel = cpsw_get_msglevel, 1887df828598SMugunthan V N .set_msglevel = cpsw_set_msglevel, 1888df828598SMugunthan V N .get_link = ethtool_op_get_link, 18892e5b38abSRichard Cochran .get_ts_info = cpsw_get_ts_info, 1890d3bb9c58SMugunthan V N .get_settings = cpsw_get_settings, 1891d3bb9c58SMugunthan V N .set_settings = cpsw_set_settings, 1892ff5b8ef2SMugunthan V N .get_coalesce = cpsw_get_coalesce, 1893ff5b8ef2SMugunthan V N .set_coalesce = cpsw_set_coalesce, 1894d9718546SMugunthan V N .get_sset_count = cpsw_get_sset_count, 1895d9718546SMugunthan V N .get_strings = cpsw_get_strings, 1896d9718546SMugunthan V N .get_ethtool_stats = cpsw_get_ethtool_stats, 18971923d6e4SMugunthan V N .get_pauseparam = cpsw_get_pauseparam, 18981923d6e4SMugunthan V N .set_pauseparam = cpsw_set_pauseparam, 1899d8a64420SMatus Ujhelyi .get_wol = cpsw_get_wol, 1900d8a64420SMatus Ujhelyi .set_wol = cpsw_set_wol, 190152c4f0ecSMugunthan V N .get_regs_len = cpsw_get_regs_len, 190252c4f0ecSMugunthan V N .get_regs = cpsw_get_regs, 1903df828598SMugunthan V N }; 1904df828598SMugunthan V N 1905549985eeSRichard Cochran static void cpsw_slave_init(struct cpsw_slave *slave, struct cpsw_priv *priv, 1906549985eeSRichard Cochran u32 slave_reg_ofs, u32 sliver_reg_ofs) 1907df828598SMugunthan V N { 1908df828598SMugunthan V N void __iomem *regs = priv->regs; 1909df828598SMugunthan V N int slave_num = slave->slave_num; 1910df828598SMugunthan V N struct cpsw_slave_data *data = priv->data.slave_data + slave_num; 1911df828598SMugunthan V N 1912df828598SMugunthan V N slave->data = data; 1913549985eeSRichard Cochran slave->regs = regs + slave_reg_ofs; 1914549985eeSRichard Cochran slave->sliver = regs + sliver_reg_ofs; 1915d9ba8f9eSMugunthan V N slave->port_vlan = data->dual_emac_res_vlan; 1916df828598SMugunthan V N } 1917df828598SMugunthan V N 19182eb32b0aSMugunthan V N static int cpsw_probe_dt(struct cpsw_platform_data *data, 19192eb32b0aSMugunthan V N struct platform_device *pdev) 19202eb32b0aSMugunthan V N { 19212eb32b0aSMugunthan V N struct device_node *node = pdev->dev.of_node; 19222eb32b0aSMugunthan V N struct device_node *slave_node; 19232eb32b0aSMugunthan V N int i = 0, ret; 19242eb32b0aSMugunthan V N u32 prop; 19252eb32b0aSMugunthan V N 19262eb32b0aSMugunthan V N if (!node) 19272eb32b0aSMugunthan V N return -EINVAL; 19282eb32b0aSMugunthan V N 19292eb32b0aSMugunthan V N if (of_property_read_u32(node, "slaves", &prop)) { 193088c99ff6SGeorge Cherian dev_err(&pdev->dev, "Missing slaves property in the DT.\n"); 19312eb32b0aSMugunthan V N return -EINVAL; 19322eb32b0aSMugunthan V N } 19332eb32b0aSMugunthan V N data->slaves = prop; 19342eb32b0aSMugunthan V N 1935e86ac13bSMugunthan V N if (of_property_read_u32(node, "active_slave", &prop)) { 193688c99ff6SGeorge Cherian dev_err(&pdev->dev, "Missing active_slave property in the DT.\n"); 1937aa1a15e2SDaniel Mack return -EINVAL; 193878ca0b28SRichard Cochran } 1939e86ac13bSMugunthan V N data->active_slave = prop; 194078ca0b28SRichard Cochran 194100ab94eeSRichard Cochran if (of_property_read_u32(node, "cpts_clock_mult", &prop)) { 194288c99ff6SGeorge Cherian dev_err(&pdev->dev, "Missing cpts_clock_mult property in the DT.\n"); 1943aa1a15e2SDaniel Mack return -EINVAL; 194400ab94eeSRichard Cochran } 194500ab94eeSRichard Cochran data->cpts_clock_mult = prop; 194600ab94eeSRichard Cochran 194700ab94eeSRichard Cochran if (of_property_read_u32(node, "cpts_clock_shift", &prop)) { 194888c99ff6SGeorge Cherian dev_err(&pdev->dev, "Missing cpts_clock_shift property in the DT.\n"); 1949aa1a15e2SDaniel Mack return -EINVAL; 195000ab94eeSRichard Cochran } 195100ab94eeSRichard Cochran data->cpts_clock_shift = prop; 195200ab94eeSRichard Cochran 1953aa1a15e2SDaniel Mack data->slave_data = devm_kzalloc(&pdev->dev, data->slaves 1954aa1a15e2SDaniel Mack * sizeof(struct cpsw_slave_data), 1955b2adaca9SJoe Perches GFP_KERNEL); 1956b2adaca9SJoe Perches if (!data->slave_data) 1957aa1a15e2SDaniel Mack return -ENOMEM; 19582eb32b0aSMugunthan V N 19592eb32b0aSMugunthan V N if (of_property_read_u32(node, "cpdma_channels", &prop)) { 196088c99ff6SGeorge Cherian dev_err(&pdev->dev, "Missing cpdma_channels property in the DT.\n"); 1961aa1a15e2SDaniel Mack return -EINVAL; 19622eb32b0aSMugunthan V N } 19632eb32b0aSMugunthan V N data->channels = prop; 19642eb32b0aSMugunthan V N 19652eb32b0aSMugunthan V N if (of_property_read_u32(node, "ale_entries", &prop)) { 196688c99ff6SGeorge Cherian dev_err(&pdev->dev, "Missing ale_entries property in the DT.\n"); 1967aa1a15e2SDaniel Mack return -EINVAL; 19682eb32b0aSMugunthan V N } 19692eb32b0aSMugunthan V N data->ale_entries = prop; 19702eb32b0aSMugunthan V N 19712eb32b0aSMugunthan V N if (of_property_read_u32(node, "bd_ram_size", &prop)) { 197288c99ff6SGeorge Cherian dev_err(&pdev->dev, "Missing bd_ram_size property in the DT.\n"); 1973aa1a15e2SDaniel Mack return -EINVAL; 19742eb32b0aSMugunthan V N } 19752eb32b0aSMugunthan V N data->bd_ram_size = prop; 19762eb32b0aSMugunthan V N 19772eb32b0aSMugunthan V N if (of_property_read_u32(node, "rx_descs", &prop)) { 197888c99ff6SGeorge Cherian dev_err(&pdev->dev, "Missing rx_descs property in the DT.\n"); 1979aa1a15e2SDaniel Mack return -EINVAL; 19802eb32b0aSMugunthan V N } 19812eb32b0aSMugunthan V N data->rx_descs = prop; 19822eb32b0aSMugunthan V N 19832eb32b0aSMugunthan V N if (of_property_read_u32(node, "mac_control", &prop)) { 198488c99ff6SGeorge Cherian dev_err(&pdev->dev, "Missing mac_control property in the DT.\n"); 1985aa1a15e2SDaniel Mack return -EINVAL; 19862eb32b0aSMugunthan V N } 19872eb32b0aSMugunthan V N data->mac_control = prop; 19882eb32b0aSMugunthan V N 1989281abd96SMarkus Pargmann if (of_property_read_bool(node, "dual_emac")) 1990281abd96SMarkus Pargmann data->dual_emac = 1; 1991d9ba8f9eSMugunthan V N 19921fb19aa7SVaibhav Hiremath /* 19931fb19aa7SVaibhav Hiremath * Populate all the child nodes here... 19941fb19aa7SVaibhav Hiremath */ 19951fb19aa7SVaibhav Hiremath ret = of_platform_populate(node, NULL, NULL, &pdev->dev); 19961fb19aa7SVaibhav Hiremath /* We do not want to force this, as in some cases may not have child */ 19971fb19aa7SVaibhav Hiremath if (ret) 199888c99ff6SGeorge Cherian dev_warn(&pdev->dev, "Doesn't have any child node\n"); 19991fb19aa7SVaibhav Hiremath 2000f468b10eSMarkus Pargmann for_each_child_of_node(node, slave_node) { 2001549985eeSRichard Cochran struct cpsw_slave_data *slave_data = data->slave_data + i; 2002549985eeSRichard Cochran const void *mac_addr = NULL; 2003549985eeSRichard Cochran u32 phyid; 2004549985eeSRichard Cochran int lenp; 2005549985eeSRichard Cochran const __be32 *parp; 2006549985eeSRichard Cochran struct device_node *mdio_node; 2007549985eeSRichard Cochran struct platform_device *mdio; 2008549985eeSRichard Cochran 2009f468b10eSMarkus Pargmann /* This is no slave child node, continue */ 2010f468b10eSMarkus Pargmann if (strcmp(slave_node->name, "slave")) 2011f468b10eSMarkus Pargmann continue; 2012f468b10eSMarkus Pargmann 2013549985eeSRichard Cochran parp = of_get_property(slave_node, "phy_id", &lenp); 2014ce16294fSLothar Waßmann if ((parp == NULL) || (lenp != (sizeof(void *) * 2))) { 201588c99ff6SGeorge Cherian dev_err(&pdev->dev, "Missing slave[%d] phy_id property\n", i); 201647276fccSMugunthan V N goto no_phy_slave; 2017549985eeSRichard Cochran } 2018549985eeSRichard Cochran mdio_node = of_find_node_by_phandle(be32_to_cpup(parp)); 2019549985eeSRichard Cochran phyid = be32_to_cpup(parp+1); 2020549985eeSRichard Cochran mdio = of_find_device_by_node(mdio_node); 202160e71ab5SJohan Hovold of_node_put(mdio_node); 20226954cc1fSJohan Hovold if (!mdio) { 202356fdb2e0SMarkus Pargmann dev_err(&pdev->dev, "Missing mdio platform device\n"); 20246954cc1fSJohan Hovold return -EINVAL; 20256954cc1fSJohan Hovold } 2026549985eeSRichard Cochran snprintf(slave_data->phy_id, sizeof(slave_data->phy_id), 2027549985eeSRichard Cochran PHY_ID_FMT, mdio->name, phyid); 2028549985eeSRichard Cochran 202947276fccSMugunthan V N slave_data->phy_if = of_get_phy_mode(slave_node); 203047276fccSMugunthan V N if (slave_data->phy_if < 0) { 203147276fccSMugunthan V N dev_err(&pdev->dev, "Missing or malformed slave[%d] phy-mode property\n", 203247276fccSMugunthan V N i); 203347276fccSMugunthan V N return slave_data->phy_if; 203447276fccSMugunthan V N } 203547276fccSMugunthan V N 203647276fccSMugunthan V N no_phy_slave: 2037549985eeSRichard Cochran mac_addr = of_get_mac_address(slave_node); 20380ba517b1SMarkus Pargmann if (mac_addr) { 2039549985eeSRichard Cochran memcpy(slave_data->mac_addr, mac_addr, ETH_ALEN); 20400ba517b1SMarkus Pargmann } else { 20410ba517b1SMarkus Pargmann if (of_machine_is_compatible("ti,am33xx")) { 2042e5a49c1eSTony Lindgren ret = cpsw_am33xx_cm_get_macid(&pdev->dev, 2043e5a49c1eSTony Lindgren 0x630, i, 20440ba517b1SMarkus Pargmann slave_data->mac_addr); 20450ba517b1SMarkus Pargmann if (ret) 20460ba517b1SMarkus Pargmann return ret; 20470ba517b1SMarkus Pargmann } 20480ba517b1SMarkus Pargmann } 2049d9ba8f9eSMugunthan V N if (data->dual_emac) { 205091c4166cSMugunthan V N if (of_property_read_u32(slave_node, "dual_emac_res_vlan", 2051d9ba8f9eSMugunthan V N &prop)) { 205288c99ff6SGeorge Cherian dev_err(&pdev->dev, "Missing dual_emac_res_vlan in DT.\n"); 2053d9ba8f9eSMugunthan V N slave_data->dual_emac_res_vlan = i+1; 205488c99ff6SGeorge Cherian dev_err(&pdev->dev, "Using %d as Reserved VLAN for %d slave\n", 2055d9ba8f9eSMugunthan V N slave_data->dual_emac_res_vlan, i); 2056d9ba8f9eSMugunthan V N } else { 2057d9ba8f9eSMugunthan V N slave_data->dual_emac_res_vlan = prop; 2058d9ba8f9eSMugunthan V N } 2059d9ba8f9eSMugunthan V N } 2060d9ba8f9eSMugunthan V N 2061549985eeSRichard Cochran i++; 20623a27bfacSMugunthan V N if (i == data->slaves) 20633a27bfacSMugunthan V N break; 2064549985eeSRichard Cochran } 2065549985eeSRichard Cochran 20662eb32b0aSMugunthan V N return 0; 20672eb32b0aSMugunthan V N } 20682eb32b0aSMugunthan V N 2069d9ba8f9eSMugunthan V N static int cpsw_probe_dual_emac(struct platform_device *pdev, 2070d9ba8f9eSMugunthan V N struct cpsw_priv *priv) 2071d9ba8f9eSMugunthan V N { 2072d9ba8f9eSMugunthan V N struct cpsw_platform_data *data = &priv->data; 2073d9ba8f9eSMugunthan V N struct net_device *ndev; 2074d9ba8f9eSMugunthan V N struct cpsw_priv *priv_sl2; 2075d9ba8f9eSMugunthan V N int ret = 0, i; 2076d9ba8f9eSMugunthan V N 2077d9ba8f9eSMugunthan V N ndev = alloc_etherdev(sizeof(struct cpsw_priv)); 2078d9ba8f9eSMugunthan V N if (!ndev) { 207988c99ff6SGeorge Cherian dev_err(&pdev->dev, "cpsw: error allocating net_device\n"); 2080d9ba8f9eSMugunthan V N return -ENOMEM; 2081d9ba8f9eSMugunthan V N } 2082d9ba8f9eSMugunthan V N 2083d9ba8f9eSMugunthan V N priv_sl2 = netdev_priv(ndev); 2084d9ba8f9eSMugunthan V N spin_lock_init(&priv_sl2->lock); 2085d9ba8f9eSMugunthan V N priv_sl2->data = *data; 2086d9ba8f9eSMugunthan V N priv_sl2->pdev = pdev; 2087d9ba8f9eSMugunthan V N priv_sl2->ndev = ndev; 2088d9ba8f9eSMugunthan V N priv_sl2->dev = &ndev->dev; 2089d9ba8f9eSMugunthan V N priv_sl2->msg_enable = netif_msg_init(debug_level, CPSW_DEBUG); 2090d9ba8f9eSMugunthan V N priv_sl2->rx_packet_max = max(rx_packet_max, 128); 2091d9ba8f9eSMugunthan V N 2092d9ba8f9eSMugunthan V N if (is_valid_ether_addr(data->slave_data[1].mac_addr)) { 2093d9ba8f9eSMugunthan V N memcpy(priv_sl2->mac_addr, data->slave_data[1].mac_addr, 2094d9ba8f9eSMugunthan V N ETH_ALEN); 209588c99ff6SGeorge Cherian dev_info(&pdev->dev, "cpsw: Detected MACID = %pM\n", priv_sl2->mac_addr); 2096d9ba8f9eSMugunthan V N } else { 2097d9ba8f9eSMugunthan V N random_ether_addr(priv_sl2->mac_addr); 209888c99ff6SGeorge Cherian dev_info(&pdev->dev, "cpsw: Random MACID = %pM\n", priv_sl2->mac_addr); 2099d9ba8f9eSMugunthan V N } 2100d9ba8f9eSMugunthan V N memcpy(ndev->dev_addr, priv_sl2->mac_addr, ETH_ALEN); 2101d9ba8f9eSMugunthan V N 2102d9ba8f9eSMugunthan V N priv_sl2->slaves = priv->slaves; 2103d9ba8f9eSMugunthan V N priv_sl2->clk = priv->clk; 2104d9ba8f9eSMugunthan V N 2105ff5b8ef2SMugunthan V N priv_sl2->coal_intvl = 0; 2106ff5b8ef2SMugunthan V N priv_sl2->bus_freq_mhz = priv->bus_freq_mhz; 2107ff5b8ef2SMugunthan V N 2108d9ba8f9eSMugunthan V N priv_sl2->regs = priv->regs; 2109d9ba8f9eSMugunthan V N priv_sl2->host_port = priv->host_port; 2110d9ba8f9eSMugunthan V N priv_sl2->host_port_regs = priv->host_port_regs; 2111d9ba8f9eSMugunthan V N priv_sl2->wr_regs = priv->wr_regs; 2112d9718546SMugunthan V N priv_sl2->hw_stats = priv->hw_stats; 2113d9ba8f9eSMugunthan V N priv_sl2->dma = priv->dma; 2114d9ba8f9eSMugunthan V N priv_sl2->txch = priv->txch; 2115d9ba8f9eSMugunthan V N priv_sl2->rxch = priv->rxch; 2116d9ba8f9eSMugunthan V N priv_sl2->ale = priv->ale; 2117d9ba8f9eSMugunthan V N priv_sl2->emac_port = 1; 2118d9ba8f9eSMugunthan V N priv->slaves[1].ndev = ndev; 2119d9ba8f9eSMugunthan V N priv_sl2->cpts = priv->cpts; 2120d9ba8f9eSMugunthan V N priv_sl2->version = priv->version; 2121d9ba8f9eSMugunthan V N 2122d9ba8f9eSMugunthan V N for (i = 0; i < priv->num_irqs; i++) { 2123d9ba8f9eSMugunthan V N priv_sl2->irqs_table[i] = priv->irqs_table[i]; 2124d9ba8f9eSMugunthan V N priv_sl2->num_irqs = priv->num_irqs; 2125d9ba8f9eSMugunthan V N } 2126f646968fSPatrick McHardy ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER; 2127d9ba8f9eSMugunthan V N 2128d9ba8f9eSMugunthan V N ndev->netdev_ops = &cpsw_netdev_ops; 21297ad24ea4SWilfried Klaebe ndev->ethtool_ops = &cpsw_ethtool_ops; 2130d9ba8f9eSMugunthan V N netif_napi_add(ndev, &priv_sl2->napi, cpsw_poll, CPSW_POLL_WEIGHT); 2131d9ba8f9eSMugunthan V N 2132d9ba8f9eSMugunthan V N /* register the network device */ 2133d9ba8f9eSMugunthan V N SET_NETDEV_DEV(ndev, &pdev->dev); 2134d9ba8f9eSMugunthan V N ret = register_netdev(ndev); 2135d9ba8f9eSMugunthan V N if (ret) { 213688c99ff6SGeorge Cherian dev_err(&pdev->dev, "cpsw: error registering net device\n"); 2137d9ba8f9eSMugunthan V N free_netdev(ndev); 2138d9ba8f9eSMugunthan V N ret = -ENODEV; 2139d9ba8f9eSMugunthan V N } 2140d9ba8f9eSMugunthan V N 2141d9ba8f9eSMugunthan V N return ret; 2142d9ba8f9eSMugunthan V N } 2143d9ba8f9eSMugunthan V N 2144663e12e6SBill Pemberton static int cpsw_probe(struct platform_device *pdev) 2145df828598SMugunthan V N { 2146d1bd9acfSSebastian Siewior struct cpsw_platform_data *data; 2147df828598SMugunthan V N struct net_device *ndev; 2148df828598SMugunthan V N struct cpsw_priv *priv; 2149df828598SMugunthan V N struct cpdma_params dma_params; 2150df828598SMugunthan V N struct cpsw_ale_params ale_params; 2151aa1a15e2SDaniel Mack void __iomem *ss_regs; 2152aa1a15e2SDaniel Mack struct resource *res, *ss_res; 2153549985eeSRichard Cochran u32 slave_offset, sliver_offset, slave_size; 21545087b915SFelipe Balbi int ret = 0, i; 21555087b915SFelipe Balbi int irq; 2156df828598SMugunthan V N 2157df828598SMugunthan V N ndev = alloc_etherdev(sizeof(struct cpsw_priv)); 2158df828598SMugunthan V N if (!ndev) { 215988c99ff6SGeorge Cherian dev_err(&pdev->dev, "error allocating net_device\n"); 2160df828598SMugunthan V N return -ENOMEM; 2161df828598SMugunthan V N } 2162df828598SMugunthan V N 2163df828598SMugunthan V N platform_set_drvdata(pdev, ndev); 2164df828598SMugunthan V N priv = netdev_priv(ndev); 2165df828598SMugunthan V N spin_lock_init(&priv->lock); 2166df828598SMugunthan V N priv->pdev = pdev; 2167df828598SMugunthan V N priv->ndev = ndev; 2168df828598SMugunthan V N priv->dev = &ndev->dev; 2169df828598SMugunthan V N priv->msg_enable = netif_msg_init(debug_level, CPSW_DEBUG); 2170df828598SMugunthan V N priv->rx_packet_max = max(rx_packet_max, 128); 21719232b16dSMugunthan V N priv->cpts = devm_kzalloc(&pdev->dev, sizeof(struct cpts), GFP_KERNEL); 21727dcf313aSMugunthan V N priv->irq_enabled = true; 2173ab8e99d2SSebastian Siewior if (!priv->cpts) { 217488c99ff6SGeorge Cherian dev_err(&pdev->dev, "error allocating cpts\n"); 21754d507dffSMarkus Pargmann ret = -ENOMEM; 21769232b16dSMugunthan V N goto clean_ndev_ret; 21779232b16dSMugunthan V N } 2178df828598SMugunthan V N 21791fb19aa7SVaibhav Hiremath /* 21801fb19aa7SVaibhav Hiremath * This may be required here for child devices. 21811fb19aa7SVaibhav Hiremath */ 21821fb19aa7SVaibhav Hiremath pm_runtime_enable(&pdev->dev); 21831fb19aa7SVaibhav Hiremath 2184739683b4SMugunthan V N /* Select default pin state */ 2185739683b4SMugunthan V N pinctrl_pm_select_default_state(&pdev->dev); 2186739683b4SMugunthan V N 21872eb32b0aSMugunthan V N if (cpsw_probe_dt(&priv->data, pdev)) { 218888c99ff6SGeorge Cherian dev_err(&pdev->dev, "cpsw: platform data missing\n"); 21892eb32b0aSMugunthan V N ret = -ENODEV; 2190aa1a15e2SDaniel Mack goto clean_runtime_disable_ret; 21912eb32b0aSMugunthan V N } 21922eb32b0aSMugunthan V N data = &priv->data; 21932eb32b0aSMugunthan V N 2194df828598SMugunthan V N if (is_valid_ether_addr(data->slave_data[0].mac_addr)) { 2195df828598SMugunthan V N memcpy(priv->mac_addr, data->slave_data[0].mac_addr, ETH_ALEN); 219688c99ff6SGeorge Cherian dev_info(&pdev->dev, "Detected MACID = %pM\n", priv->mac_addr); 2197df828598SMugunthan V N } else { 21987efd26d0SJoe Perches eth_random_addr(priv->mac_addr); 219988c99ff6SGeorge Cherian dev_info(&pdev->dev, "Random MACID = %pM\n", priv->mac_addr); 2200df828598SMugunthan V N } 2201df828598SMugunthan V N 2202df828598SMugunthan V N memcpy(ndev->dev_addr, priv->mac_addr, ETH_ALEN); 2203df828598SMugunthan V N 2204aa1a15e2SDaniel Mack priv->slaves = devm_kzalloc(&pdev->dev, 2205aa1a15e2SDaniel Mack sizeof(struct cpsw_slave) * data->slaves, 2206df828598SMugunthan V N GFP_KERNEL); 2207df828598SMugunthan V N if (!priv->slaves) { 2208aa1a15e2SDaniel Mack ret = -ENOMEM; 2209aa1a15e2SDaniel Mack goto clean_runtime_disable_ret; 2210df828598SMugunthan V N } 2211df828598SMugunthan V N for (i = 0; i < data->slaves; i++) 2212df828598SMugunthan V N priv->slaves[i].slave_num = i; 2213df828598SMugunthan V N 2214d9ba8f9eSMugunthan V N priv->slaves[0].ndev = ndev; 2215d9ba8f9eSMugunthan V N priv->emac_port = 0; 2216d9ba8f9eSMugunthan V N 2217aa1a15e2SDaniel Mack priv->clk = devm_clk_get(&pdev->dev, "fck"); 2218df828598SMugunthan V N if (IS_ERR(priv->clk)) { 2219aa1a15e2SDaniel Mack dev_err(priv->dev, "fck is not found\n"); 2220f150bd7fSMugunthan V N ret = -ENODEV; 2221aa1a15e2SDaniel Mack goto clean_runtime_disable_ret; 2222df828598SMugunthan V N } 2223ff5b8ef2SMugunthan V N priv->coal_intvl = 0; 2224ff5b8ef2SMugunthan V N priv->bus_freq_mhz = clk_get_rate(priv->clk) / 1000000; 2225df828598SMugunthan V N 2226aa1a15e2SDaniel Mack ss_res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2227aa1a15e2SDaniel Mack ss_regs = devm_ioremap_resource(&pdev->dev, ss_res); 2228aa1a15e2SDaniel Mack if (IS_ERR(ss_regs)) { 2229aa1a15e2SDaniel Mack ret = PTR_ERR(ss_regs); 2230aa1a15e2SDaniel Mack goto clean_runtime_disable_ret; 2231df828598SMugunthan V N } 2232549985eeSRichard Cochran priv->regs = ss_regs; 2233549985eeSRichard Cochran priv->host_port = HOST_PORT_NUM; 2234df828598SMugunthan V N 2235f280e89aSMugunthan V N /* Need to enable clocks with runtime PM api to access module 2236f280e89aSMugunthan V N * registers 2237f280e89aSMugunthan V N */ 2238f280e89aSMugunthan V N pm_runtime_get_sync(&pdev->dev); 2239f280e89aSMugunthan V N priv->version = readl(&priv->regs->id_ver); 2240f280e89aSMugunthan V N pm_runtime_put_sync(&pdev->dev); 2241f280e89aSMugunthan V N 2242aa1a15e2SDaniel Mack res = platform_get_resource(pdev, IORESOURCE_MEM, 1); 2243aa1a15e2SDaniel Mack priv->wr_regs = devm_ioremap_resource(&pdev->dev, res); 2244aa1a15e2SDaniel Mack if (IS_ERR(priv->wr_regs)) { 2245aa1a15e2SDaniel Mack ret = PTR_ERR(priv->wr_regs); 2246aa1a15e2SDaniel Mack goto clean_runtime_disable_ret; 2247df828598SMugunthan V N } 2248df828598SMugunthan V N 2249df828598SMugunthan V N memset(&dma_params, 0, sizeof(dma_params)); 2250549985eeSRichard Cochran memset(&ale_params, 0, sizeof(ale_params)); 2251549985eeSRichard Cochran 2252549985eeSRichard Cochran switch (priv->version) { 2253549985eeSRichard Cochran case CPSW_VERSION_1: 2254549985eeSRichard Cochran priv->host_port_regs = ss_regs + CPSW1_HOST_PORT_OFFSET; 22559232b16dSMugunthan V N priv->cpts->reg = ss_regs + CPSW1_CPTS_OFFSET; 2256d9718546SMugunthan V N priv->hw_stats = ss_regs + CPSW1_HW_STATS; 2257549985eeSRichard Cochran dma_params.dmaregs = ss_regs + CPSW1_CPDMA_OFFSET; 2258549985eeSRichard Cochran dma_params.txhdp = ss_regs + CPSW1_STATERAM_OFFSET; 2259549985eeSRichard Cochran ale_params.ale_regs = ss_regs + CPSW1_ALE_OFFSET; 2260549985eeSRichard Cochran slave_offset = CPSW1_SLAVE_OFFSET; 2261549985eeSRichard Cochran slave_size = CPSW1_SLAVE_SIZE; 2262549985eeSRichard Cochran sliver_offset = CPSW1_SLIVER_OFFSET; 2263549985eeSRichard Cochran dma_params.desc_mem_phys = 0; 2264549985eeSRichard Cochran break; 2265549985eeSRichard Cochran case CPSW_VERSION_2: 2266c193f365SMugunthan V N case CPSW_VERSION_3: 2267926489beSMugunthan V N case CPSW_VERSION_4: 2268549985eeSRichard Cochran priv->host_port_regs = ss_regs + CPSW2_HOST_PORT_OFFSET; 22699232b16dSMugunthan V N priv->cpts->reg = ss_regs + CPSW2_CPTS_OFFSET; 2270d9718546SMugunthan V N priv->hw_stats = ss_regs + CPSW2_HW_STATS; 2271549985eeSRichard Cochran dma_params.dmaregs = ss_regs + CPSW2_CPDMA_OFFSET; 2272549985eeSRichard Cochran dma_params.txhdp = ss_regs + CPSW2_STATERAM_OFFSET; 2273549985eeSRichard Cochran ale_params.ale_regs = ss_regs + CPSW2_ALE_OFFSET; 2274549985eeSRichard Cochran slave_offset = CPSW2_SLAVE_OFFSET; 2275549985eeSRichard Cochran slave_size = CPSW2_SLAVE_SIZE; 2276549985eeSRichard Cochran sliver_offset = CPSW2_SLIVER_OFFSET; 2277549985eeSRichard Cochran dma_params.desc_mem_phys = 2278aa1a15e2SDaniel Mack (u32 __force) ss_res->start + CPSW2_BD_OFFSET; 2279549985eeSRichard Cochran break; 2280549985eeSRichard Cochran default: 2281549985eeSRichard Cochran dev_err(priv->dev, "unknown version 0x%08x\n", priv->version); 2282549985eeSRichard Cochran ret = -ENODEV; 2283aa1a15e2SDaniel Mack goto clean_runtime_disable_ret; 2284549985eeSRichard Cochran } 2285549985eeSRichard Cochran for (i = 0; i < priv->data.slaves; i++) { 2286549985eeSRichard Cochran struct cpsw_slave *slave = &priv->slaves[i]; 2287549985eeSRichard Cochran cpsw_slave_init(slave, priv, slave_offset, sliver_offset); 2288549985eeSRichard Cochran slave_offset += slave_size; 2289549985eeSRichard Cochran sliver_offset += SLIVER_SIZE; 2290549985eeSRichard Cochran } 2291549985eeSRichard Cochran 2292df828598SMugunthan V N dma_params.dev = &pdev->dev; 2293549985eeSRichard Cochran dma_params.rxthresh = dma_params.dmaregs + CPDMA_RXTHRESH; 2294549985eeSRichard Cochran dma_params.rxfree = dma_params.dmaregs + CPDMA_RXFREE; 2295549985eeSRichard Cochran dma_params.rxhdp = dma_params.txhdp + CPDMA_RXHDP; 2296549985eeSRichard Cochran dma_params.txcp = dma_params.txhdp + CPDMA_TXCP; 2297549985eeSRichard Cochran dma_params.rxcp = dma_params.txhdp + CPDMA_RXCP; 2298df828598SMugunthan V N 2299df828598SMugunthan V N dma_params.num_chan = data->channels; 2300df828598SMugunthan V N dma_params.has_soft_reset = true; 2301df828598SMugunthan V N dma_params.min_packet_size = CPSW_MIN_PACKET_SIZE; 2302df828598SMugunthan V N dma_params.desc_mem_size = data->bd_ram_size; 2303df828598SMugunthan V N dma_params.desc_align = 16; 2304df828598SMugunthan V N dma_params.has_ext_regs = true; 2305549985eeSRichard Cochran dma_params.desc_hw_addr = dma_params.desc_mem_phys; 2306df828598SMugunthan V N 2307df828598SMugunthan V N priv->dma = cpdma_ctlr_create(&dma_params); 2308df828598SMugunthan V N if (!priv->dma) { 2309df828598SMugunthan V N dev_err(priv->dev, "error initializing dma\n"); 2310df828598SMugunthan V N ret = -ENOMEM; 2311aa1a15e2SDaniel Mack goto clean_runtime_disable_ret; 2312df828598SMugunthan V N } 2313df828598SMugunthan V N 2314df828598SMugunthan V N priv->txch = cpdma_chan_create(priv->dma, tx_chan_num(0), 2315df828598SMugunthan V N cpsw_tx_handler); 2316df828598SMugunthan V N priv->rxch = cpdma_chan_create(priv->dma, rx_chan_num(0), 2317df828598SMugunthan V N cpsw_rx_handler); 2318df828598SMugunthan V N 2319df828598SMugunthan V N if (WARN_ON(!priv->txch || !priv->rxch)) { 2320df828598SMugunthan V N dev_err(priv->dev, "error initializing dma channels\n"); 2321df828598SMugunthan V N ret = -ENOMEM; 2322df828598SMugunthan V N goto clean_dma_ret; 2323df828598SMugunthan V N } 2324df828598SMugunthan V N 2325df828598SMugunthan V N ale_params.dev = &ndev->dev; 2326df828598SMugunthan V N ale_params.ale_ageout = ale_ageout; 2327df828598SMugunthan V N ale_params.ale_entries = data->ale_entries; 2328df828598SMugunthan V N ale_params.ale_ports = data->slaves; 2329df828598SMugunthan V N 2330df828598SMugunthan V N priv->ale = cpsw_ale_create(&ale_params); 2331df828598SMugunthan V N if (!priv->ale) { 2332df828598SMugunthan V N dev_err(priv->dev, "error initializing ale engine\n"); 2333df828598SMugunthan V N ret = -ENODEV; 2334df828598SMugunthan V N goto clean_dma_ret; 2335df828598SMugunthan V N } 2336df828598SMugunthan V N 2337c03abd84SFelipe Balbi ndev->irq = platform_get_irq(pdev, 1); 2338df828598SMugunthan V N if (ndev->irq < 0) { 2339df828598SMugunthan V N dev_err(priv->dev, "error getting irq resource\n"); 2340df828598SMugunthan V N ret = -ENOENT; 2341df828598SMugunthan V N goto clean_ale_ret; 2342df828598SMugunthan V N } 2343df828598SMugunthan V N 2344c03abd84SFelipe Balbi /* Grab RX and TX IRQs. Note that we also have RX_THRESHOLD and 2345c03abd84SFelipe Balbi * MISC IRQs which are always kept disabled with this driver so 2346c03abd84SFelipe Balbi * we will not request them. 2347c03abd84SFelipe Balbi * 2348c03abd84SFelipe Balbi * If anyone wants to implement support for those, make sure to 2349c03abd84SFelipe Balbi * first request and append them to irqs_table array. 2350c03abd84SFelipe Balbi */ 2351c2b32e58SDaniel Mack 2352c03abd84SFelipe Balbi /* RX IRQ */ 23535087b915SFelipe Balbi irq = platform_get_irq(pdev, 1); 23545087b915SFelipe Balbi if (irq < 0) 23555087b915SFelipe Balbi goto clean_ale_ret; 23565087b915SFelipe Balbi 2357c03abd84SFelipe Balbi priv->irqs_table[0] = irq; 2358c03abd84SFelipe Balbi ret = devm_request_irq(&pdev->dev, irq, cpsw_rx_interrupt, 23595087b915SFelipe Balbi 0, dev_name(&pdev->dev), priv); 23605087b915SFelipe Balbi if (ret < 0) { 23615087b915SFelipe Balbi dev_err(priv->dev, "error attaching irq (%d)\n", ret); 23625087b915SFelipe Balbi goto clean_ale_ret; 2363df828598SMugunthan V N } 2364df828598SMugunthan V N 2365c03abd84SFelipe Balbi /* TX IRQ */ 23665087b915SFelipe Balbi irq = platform_get_irq(pdev, 2); 23675087b915SFelipe Balbi if (irq < 0) 23685087b915SFelipe Balbi goto clean_ale_ret; 23695087b915SFelipe Balbi 2370c03abd84SFelipe Balbi priv->irqs_table[1] = irq; 2371c03abd84SFelipe Balbi ret = devm_request_irq(&pdev->dev, irq, cpsw_tx_interrupt, 23725087b915SFelipe Balbi 0, dev_name(&pdev->dev), priv); 23735087b915SFelipe Balbi if (ret < 0) { 23745087b915SFelipe Balbi dev_err(priv->dev, "error attaching irq (%d)\n", ret); 23755087b915SFelipe Balbi goto clean_ale_ret; 23765087b915SFelipe Balbi } 2377c03abd84SFelipe Balbi priv->num_irqs = 2; 2378c2b32e58SDaniel Mack 2379f646968fSPatrick McHardy ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER; 2380df828598SMugunthan V N 2381df828598SMugunthan V N ndev->netdev_ops = &cpsw_netdev_ops; 23827ad24ea4SWilfried Klaebe ndev->ethtool_ops = &cpsw_ethtool_ops; 2383df828598SMugunthan V N netif_napi_add(ndev, &priv->napi, cpsw_poll, CPSW_POLL_WEIGHT); 2384df828598SMugunthan V N 2385df828598SMugunthan V N /* register the network device */ 2386df828598SMugunthan V N SET_NETDEV_DEV(ndev, &pdev->dev); 2387df828598SMugunthan V N ret = register_netdev(ndev); 2388df828598SMugunthan V N if (ret) { 2389df828598SMugunthan V N dev_err(priv->dev, "error registering net device\n"); 2390df828598SMugunthan V N ret = -ENODEV; 2391aa1a15e2SDaniel Mack goto clean_ale_ret; 2392df828598SMugunthan V N } 2393df828598SMugunthan V N 23941a3b5056SOlof Johansson cpsw_notice(priv, probe, "initialized device (regs %pa, irq %d)\n", 23951a3b5056SOlof Johansson &ss_res->start, ndev->irq); 2396df828598SMugunthan V N 2397d9ba8f9eSMugunthan V N if (priv->data.dual_emac) { 2398d9ba8f9eSMugunthan V N ret = cpsw_probe_dual_emac(pdev, priv); 2399d9ba8f9eSMugunthan V N if (ret) { 2400d9ba8f9eSMugunthan V N cpsw_err(priv, probe, "error probe slave 2 emac interface\n"); 2401aa1a15e2SDaniel Mack goto clean_ale_ret; 2402d9ba8f9eSMugunthan V N } 2403d9ba8f9eSMugunthan V N } 2404d9ba8f9eSMugunthan V N 2405df828598SMugunthan V N return 0; 2406df828598SMugunthan V N 2407df828598SMugunthan V N clean_ale_ret: 2408df828598SMugunthan V N cpsw_ale_destroy(priv->ale); 2409df828598SMugunthan V N clean_dma_ret: 2410df828598SMugunthan V N cpdma_chan_destroy(priv->txch); 2411df828598SMugunthan V N cpdma_chan_destroy(priv->rxch); 2412df828598SMugunthan V N cpdma_ctlr_destroy(priv->dma); 2413aa1a15e2SDaniel Mack clean_runtime_disable_ret: 2414f150bd7fSMugunthan V N pm_runtime_disable(&pdev->dev); 2415df828598SMugunthan V N clean_ndev_ret: 2416d1bd9acfSSebastian Siewior free_netdev(priv->ndev); 2417df828598SMugunthan V N return ret; 2418df828598SMugunthan V N } 2419df828598SMugunthan V N 2420030b16a0SMugunthan V N static int cpsw_remove_child_device(struct device *dev, void *c) 2421030b16a0SMugunthan V N { 2422030b16a0SMugunthan V N struct platform_device *pdev = to_platform_device(dev); 2423030b16a0SMugunthan V N 2424030b16a0SMugunthan V N of_device_unregister(pdev); 2425030b16a0SMugunthan V N 2426030b16a0SMugunthan V N return 0; 2427030b16a0SMugunthan V N } 2428030b16a0SMugunthan V N 2429663e12e6SBill Pemberton static int cpsw_remove(struct platform_device *pdev) 2430df828598SMugunthan V N { 2431df828598SMugunthan V N struct net_device *ndev = platform_get_drvdata(pdev); 2432df828598SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 2433df828598SMugunthan V N 2434d1bd9acfSSebastian Siewior if (priv->data.dual_emac) 2435d1bd9acfSSebastian Siewior unregister_netdev(cpsw_get_slave_ndev(priv, 1)); 2436d1bd9acfSSebastian Siewior unregister_netdev(ndev); 2437df828598SMugunthan V N 2438df828598SMugunthan V N cpsw_ale_destroy(priv->ale); 2439df828598SMugunthan V N cpdma_chan_destroy(priv->txch); 2440df828598SMugunthan V N cpdma_chan_destroy(priv->rxch); 2441df828598SMugunthan V N cpdma_ctlr_destroy(priv->dma); 2442f150bd7fSMugunthan V N pm_runtime_disable(&pdev->dev); 2443030b16a0SMugunthan V N device_for_each_child(&pdev->dev, NULL, cpsw_remove_child_device); 2444d1bd9acfSSebastian Siewior if (priv->data.dual_emac) 2445d1bd9acfSSebastian Siewior free_netdev(cpsw_get_slave_ndev(priv, 1)); 2446df828598SMugunthan V N free_netdev(ndev); 2447df828598SMugunthan V N return 0; 2448df828598SMugunthan V N } 2449df828598SMugunthan V N 24508963a504SGrygorii Strashko #ifdef CONFIG_PM_SLEEP 2451df828598SMugunthan V N static int cpsw_suspend(struct device *dev) 2452df828598SMugunthan V N { 2453df828598SMugunthan V N struct platform_device *pdev = to_platform_device(dev); 2454df828598SMugunthan V N struct net_device *ndev = platform_get_drvdata(pdev); 2455b90fc27aSMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 2456df828598SMugunthan V N 2457618073e3SMugunthan V N if (priv->data.dual_emac) { 2458618073e3SMugunthan V N int i; 2459618073e3SMugunthan V N 2460618073e3SMugunthan V N for (i = 0; i < priv->data.slaves; i++) { 2461618073e3SMugunthan V N if (netif_running(priv->slaves[i].ndev)) 2462618073e3SMugunthan V N cpsw_ndo_stop(priv->slaves[i].ndev); 2463618073e3SMugunthan V N soft_reset_slave(priv->slaves + i); 2464618073e3SMugunthan V N } 2465618073e3SMugunthan V N } else { 2466df828598SMugunthan V N if (netif_running(ndev)) 2467df828598SMugunthan V N cpsw_ndo_stop(ndev); 24681e7a2e21SDaniel Mack for_each_slave(priv, soft_reset_slave); 2469618073e3SMugunthan V N } 24701e7a2e21SDaniel Mack 2471f150bd7fSMugunthan V N pm_runtime_put_sync(&pdev->dev); 2472f150bd7fSMugunthan V N 2473739683b4SMugunthan V N /* Select sleep pin state */ 2474739683b4SMugunthan V N pinctrl_pm_select_sleep_state(&pdev->dev); 2475739683b4SMugunthan V N 2476df828598SMugunthan V N return 0; 2477df828598SMugunthan V N } 2478df828598SMugunthan V N 2479df828598SMugunthan V N static int cpsw_resume(struct device *dev) 2480df828598SMugunthan V N { 2481df828598SMugunthan V N struct platform_device *pdev = to_platform_device(dev); 2482df828598SMugunthan V N struct net_device *ndev = platform_get_drvdata(pdev); 2483618073e3SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 2484df828598SMugunthan V N 2485f150bd7fSMugunthan V N pm_runtime_get_sync(&pdev->dev); 2486739683b4SMugunthan V N 2487739683b4SMugunthan V N /* Select default pin state */ 2488739683b4SMugunthan V N pinctrl_pm_select_default_state(&pdev->dev); 2489739683b4SMugunthan V N 2490618073e3SMugunthan V N if (priv->data.dual_emac) { 2491618073e3SMugunthan V N int i; 2492618073e3SMugunthan V N 2493618073e3SMugunthan V N for (i = 0; i < priv->data.slaves; i++) { 2494618073e3SMugunthan V N if (netif_running(priv->slaves[i].ndev)) 2495618073e3SMugunthan V N cpsw_ndo_open(priv->slaves[i].ndev); 2496618073e3SMugunthan V N } 2497618073e3SMugunthan V N } else { 2498df828598SMugunthan V N if (netif_running(ndev)) 2499df828598SMugunthan V N cpsw_ndo_open(ndev); 2500618073e3SMugunthan V N } 2501df828598SMugunthan V N return 0; 2502df828598SMugunthan V N } 25038963a504SGrygorii Strashko #endif 2504df828598SMugunthan V N 25058963a504SGrygorii Strashko static SIMPLE_DEV_PM_OPS(cpsw_pm_ops, cpsw_suspend, cpsw_resume); 2506df828598SMugunthan V N 25072eb32b0aSMugunthan V N static const struct of_device_id cpsw_of_mtable[] = { 25082eb32b0aSMugunthan V N { .compatible = "ti,cpsw", }, 25092eb32b0aSMugunthan V N { /* sentinel */ }, 25102eb32b0aSMugunthan V N }; 25114bc21d41SSebastian Siewior MODULE_DEVICE_TABLE(of, cpsw_of_mtable); 25122eb32b0aSMugunthan V N 2513df828598SMugunthan V N static struct platform_driver cpsw_driver = { 2514df828598SMugunthan V N .driver = { 2515df828598SMugunthan V N .name = "cpsw", 2516df828598SMugunthan V N .pm = &cpsw_pm_ops, 25171e5c76d4SSachin Kamat .of_match_table = cpsw_of_mtable, 2518df828598SMugunthan V N }, 2519df828598SMugunthan V N .probe = cpsw_probe, 2520663e12e6SBill Pemberton .remove = cpsw_remove, 2521df828598SMugunthan V N }; 2522df828598SMugunthan V N 2523df828598SMugunthan V N static int __init cpsw_init(void) 2524df828598SMugunthan V N { 2525df828598SMugunthan V N return platform_driver_register(&cpsw_driver); 2526df828598SMugunthan V N } 2527df828598SMugunthan V N late_initcall(cpsw_init); 2528df828598SMugunthan V N 2529df828598SMugunthan V N static void __exit cpsw_exit(void) 2530df828598SMugunthan V N { 2531df828598SMugunthan V N platform_driver_unregister(&cpsw_driver); 2532df828598SMugunthan V N } 2533df828598SMugunthan V N module_exit(cpsw_exit); 2534df828598SMugunthan V N 2535df828598SMugunthan V N MODULE_LICENSE("GPL"); 2536df828598SMugunthan V N MODULE_AUTHOR("Cyril Chemparathy <cyril@ti.com>"); 2537df828598SMugunthan V N MODULE_AUTHOR("Mugunthan V N <mugunthanvnm@ti.com>"); 2538df828598SMugunthan V N MODULE_DESCRIPTION("TI CPSW Ethernet driver"); 2539