1df828598SMugunthan V N /* 2df828598SMugunthan V N * Texas Instruments Ethernet Switch Driver 3df828598SMugunthan V N * 4df828598SMugunthan V N * Copyright (C) 2012 Texas Instruments 5df828598SMugunthan V N * 6df828598SMugunthan V N * This program is free software; you can redistribute it and/or 7df828598SMugunthan V N * modify it under the terms of the GNU General Public License as 8df828598SMugunthan V N * published by the Free Software Foundation version 2. 9df828598SMugunthan V N * 10df828598SMugunthan V N * This program is distributed "as is" WITHOUT ANY WARRANTY of any 11df828598SMugunthan V N * kind, whether express or implied; without even the implied warranty 12df828598SMugunthan V N * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13df828598SMugunthan V N * GNU General Public License for more details. 14df828598SMugunthan V N */ 15df828598SMugunthan V N 16df828598SMugunthan V N #include <linux/kernel.h> 17df828598SMugunthan V N #include <linux/io.h> 18df828598SMugunthan V N #include <linux/clk.h> 19df828598SMugunthan V N #include <linux/timer.h> 20df828598SMugunthan V N #include <linux/module.h> 21df828598SMugunthan V N #include <linux/platform_device.h> 22df828598SMugunthan V N #include <linux/irqreturn.h> 23df828598SMugunthan V N #include <linux/interrupt.h> 24df828598SMugunthan V N #include <linux/if_ether.h> 25df828598SMugunthan V N #include <linux/etherdevice.h> 26df828598SMugunthan V N #include <linux/netdevice.h> 272e5b38abSRichard Cochran #include <linux/net_tstamp.h> 28df828598SMugunthan V N #include <linux/phy.h> 29df828598SMugunthan V N #include <linux/workqueue.h> 30df828598SMugunthan V N #include <linux/delay.h> 31f150bd7fSMugunthan V N #include <linux/pm_runtime.h> 322eb32b0aSMugunthan V N #include <linux/of.h> 332eb32b0aSMugunthan V N #include <linux/of_net.h> 342eb32b0aSMugunthan V N #include <linux/of_device.h> 353b72c2feSMugunthan V N #include <linux/if_vlan.h> 36df828598SMugunthan V N 37739683b4SMugunthan V N #include <linux/pinctrl/consumer.h> 38df828598SMugunthan V N 39dbe34724SMugunthan V N #include "cpsw.h" 40df828598SMugunthan V N #include "cpsw_ale.h" 412e5b38abSRichard Cochran #include "cpts.h" 42df828598SMugunthan V N #include "davinci_cpdma.h" 43df828598SMugunthan V N 44df828598SMugunthan V N #define CPSW_DEBUG (NETIF_MSG_HW | NETIF_MSG_WOL | \ 45df828598SMugunthan V N NETIF_MSG_DRV | NETIF_MSG_LINK | \ 46df828598SMugunthan V N NETIF_MSG_IFUP | NETIF_MSG_INTR | \ 47df828598SMugunthan V N NETIF_MSG_PROBE | NETIF_MSG_TIMER | \ 48df828598SMugunthan V N NETIF_MSG_IFDOWN | NETIF_MSG_RX_ERR | \ 49df828598SMugunthan V N NETIF_MSG_TX_ERR | NETIF_MSG_TX_DONE | \ 50df828598SMugunthan V N NETIF_MSG_PKTDATA | NETIF_MSG_TX_QUEUED | \ 51df828598SMugunthan V N NETIF_MSG_RX_STATUS) 52df828598SMugunthan V N 53df828598SMugunthan V N #define cpsw_info(priv, type, format, ...) \ 54df828598SMugunthan V N do { \ 55df828598SMugunthan V N if (netif_msg_##type(priv) && net_ratelimit()) \ 56df828598SMugunthan V N dev_info(priv->dev, format, ## __VA_ARGS__); \ 57df828598SMugunthan V N } while (0) 58df828598SMugunthan V N 59df828598SMugunthan V N #define cpsw_err(priv, type, format, ...) \ 60df828598SMugunthan V N do { \ 61df828598SMugunthan V N if (netif_msg_##type(priv) && net_ratelimit()) \ 62df828598SMugunthan V N dev_err(priv->dev, format, ## __VA_ARGS__); \ 63df828598SMugunthan V N } while (0) 64df828598SMugunthan V N 65df828598SMugunthan V N #define cpsw_dbg(priv, type, format, ...) \ 66df828598SMugunthan V N do { \ 67df828598SMugunthan V N if (netif_msg_##type(priv) && net_ratelimit()) \ 68df828598SMugunthan V N dev_dbg(priv->dev, format, ## __VA_ARGS__); \ 69df828598SMugunthan V N } while (0) 70df828598SMugunthan V N 71df828598SMugunthan V N #define cpsw_notice(priv, type, format, ...) \ 72df828598SMugunthan V N do { \ 73df828598SMugunthan V N if (netif_msg_##type(priv) && net_ratelimit()) \ 74df828598SMugunthan V N dev_notice(priv->dev, format, ## __VA_ARGS__); \ 75df828598SMugunthan V N } while (0) 76df828598SMugunthan V N 775c50a856SMugunthan V N #define ALE_ALL_PORTS 0x7 785c50a856SMugunthan V N 79df828598SMugunthan V N #define CPSW_MAJOR_VERSION(reg) (reg >> 8 & 0x7) 80df828598SMugunthan V N #define CPSW_MINOR_VERSION(reg) (reg & 0xff) 81df828598SMugunthan V N #define CPSW_RTL_VERSION(reg) ((reg >> 11) & 0x1f) 82df828598SMugunthan V N 83e90cfac6SRichard Cochran #define CPSW_VERSION_1 0x19010a 84e90cfac6SRichard Cochran #define CPSW_VERSION_2 0x19010c 85c193f365SMugunthan V N #define CPSW_VERSION_3 0x19010f 86926489beSMugunthan V N #define CPSW_VERSION_4 0x190112 87549985eeSRichard Cochran 88549985eeSRichard Cochran #define HOST_PORT_NUM 0 89549985eeSRichard Cochran #define SLIVER_SIZE 0x40 90549985eeSRichard Cochran 91549985eeSRichard Cochran #define CPSW1_HOST_PORT_OFFSET 0x028 92549985eeSRichard Cochran #define CPSW1_SLAVE_OFFSET 0x050 93549985eeSRichard Cochran #define CPSW1_SLAVE_SIZE 0x040 94549985eeSRichard Cochran #define CPSW1_CPDMA_OFFSET 0x100 95549985eeSRichard Cochran #define CPSW1_STATERAM_OFFSET 0x200 96d9718546SMugunthan V N #define CPSW1_HW_STATS 0x400 97549985eeSRichard Cochran #define CPSW1_CPTS_OFFSET 0x500 98549985eeSRichard Cochran #define CPSW1_ALE_OFFSET 0x600 99549985eeSRichard Cochran #define CPSW1_SLIVER_OFFSET 0x700 100549985eeSRichard Cochran 101549985eeSRichard Cochran #define CPSW2_HOST_PORT_OFFSET 0x108 102549985eeSRichard Cochran #define CPSW2_SLAVE_OFFSET 0x200 103549985eeSRichard Cochran #define CPSW2_SLAVE_SIZE 0x100 104549985eeSRichard Cochran #define CPSW2_CPDMA_OFFSET 0x800 105d9718546SMugunthan V N #define CPSW2_HW_STATS 0x900 106549985eeSRichard Cochran #define CPSW2_STATERAM_OFFSET 0xa00 107549985eeSRichard Cochran #define CPSW2_CPTS_OFFSET 0xc00 108549985eeSRichard Cochran #define CPSW2_ALE_OFFSET 0xd00 109549985eeSRichard Cochran #define CPSW2_SLIVER_OFFSET 0xd80 110549985eeSRichard Cochran #define CPSW2_BD_OFFSET 0x2000 111549985eeSRichard Cochran 112df828598SMugunthan V N #define CPDMA_RXTHRESH 0x0c0 113df828598SMugunthan V N #define CPDMA_RXFREE 0x0e0 114df828598SMugunthan V N #define CPDMA_TXHDP 0x00 115df828598SMugunthan V N #define CPDMA_RXHDP 0x20 116df828598SMugunthan V N #define CPDMA_TXCP 0x40 117df828598SMugunthan V N #define CPDMA_RXCP 0x60 118df828598SMugunthan V N 119df828598SMugunthan V N #define CPSW_POLL_WEIGHT 64 120df828598SMugunthan V N #define CPSW_MIN_PACKET_SIZE 60 121df828598SMugunthan V N #define CPSW_MAX_PACKET_SIZE (1500 + 14 + 4 + 4) 122df828598SMugunthan V N 123df828598SMugunthan V N #define RX_PRIORITY_MAPPING 0x76543210 124df828598SMugunthan V N #define TX_PRIORITY_MAPPING 0x33221100 125df828598SMugunthan V N #define CPDMA_TX_PRIORITY_MAP 0x76543210 126df828598SMugunthan V N 1273b72c2feSMugunthan V N #define CPSW_VLAN_AWARE BIT(1) 1283b72c2feSMugunthan V N #define CPSW_ALE_VLAN_AWARE 1 1293b72c2feSMugunthan V N 13035717d8dSJohn Ogness #define CPSW_FIFO_NORMAL_MODE (0 << 16) 13135717d8dSJohn Ogness #define CPSW_FIFO_DUAL_MAC_MODE (1 << 16) 13235717d8dSJohn Ogness #define CPSW_FIFO_RATE_LIMIT_MODE (2 << 16) 133d9ba8f9eSMugunthan V N 134ff5b8ef2SMugunthan V N #define CPSW_INTPACEEN (0x3f << 16) 135ff5b8ef2SMugunthan V N #define CPSW_INTPRESCALE_MASK (0x7FF << 0) 136ff5b8ef2SMugunthan V N #define CPSW_CMINTMAX_CNT 63 137ff5b8ef2SMugunthan V N #define CPSW_CMINTMIN_CNT 2 138ff5b8ef2SMugunthan V N #define CPSW_CMINTMAX_INTVL (1000 / CPSW_CMINTMIN_CNT) 139ff5b8ef2SMugunthan V N #define CPSW_CMINTMIN_INTVL ((1000 / CPSW_CMINTMAX_CNT) + 1) 140ff5b8ef2SMugunthan V N 141df828598SMugunthan V N #define cpsw_enable_irq(priv) \ 142df828598SMugunthan V N do { \ 143df828598SMugunthan V N u32 i; \ 144df828598SMugunthan V N for (i = 0; i < priv->num_irqs; i++) \ 145df828598SMugunthan V N enable_irq(priv->irqs_table[i]); \ 1465f47dfb4SJoe Perches } while (0) 147df828598SMugunthan V N #define cpsw_disable_irq(priv) \ 148df828598SMugunthan V N do { \ 149df828598SMugunthan V N u32 i; \ 150df828598SMugunthan V N for (i = 0; i < priv->num_irqs; i++) \ 151df828598SMugunthan V N disable_irq_nosync(priv->irqs_table[i]); \ 1525f47dfb4SJoe Perches } while (0) 153df828598SMugunthan V N 154d3bb9c58SMugunthan V N #define cpsw_slave_index(priv) \ 155d3bb9c58SMugunthan V N ((priv->data.dual_emac) ? priv->emac_port : \ 156d3bb9c58SMugunthan V N priv->data.active_slave) 157d3bb9c58SMugunthan V N 158df828598SMugunthan V N static int debug_level; 159df828598SMugunthan V N module_param(debug_level, int, 0); 160df828598SMugunthan V N MODULE_PARM_DESC(debug_level, "cpsw debug level (NETIF_MSG bits)"); 161df828598SMugunthan V N 162df828598SMugunthan V N static int ale_ageout = 10; 163df828598SMugunthan V N module_param(ale_ageout, int, 0); 164df828598SMugunthan V N MODULE_PARM_DESC(ale_ageout, "cpsw ale ageout interval (seconds)"); 165df828598SMugunthan V N 166df828598SMugunthan V N static int rx_packet_max = CPSW_MAX_PACKET_SIZE; 167df828598SMugunthan V N module_param(rx_packet_max, int, 0); 168df828598SMugunthan V N MODULE_PARM_DESC(rx_packet_max, "maximum receive packet size (bytes)"); 169df828598SMugunthan V N 170996a5c27SRichard Cochran struct cpsw_wr_regs { 171df828598SMugunthan V N u32 id_ver; 172df828598SMugunthan V N u32 soft_reset; 173df828598SMugunthan V N u32 control; 174df828598SMugunthan V N u32 int_control; 175df828598SMugunthan V N u32 rx_thresh_en; 176df828598SMugunthan V N u32 rx_en; 177df828598SMugunthan V N u32 tx_en; 178df828598SMugunthan V N u32 misc_en; 179ff5b8ef2SMugunthan V N u32 mem_allign1[8]; 180ff5b8ef2SMugunthan V N u32 rx_thresh_stat; 181ff5b8ef2SMugunthan V N u32 rx_stat; 182ff5b8ef2SMugunthan V N u32 tx_stat; 183ff5b8ef2SMugunthan V N u32 misc_stat; 184ff5b8ef2SMugunthan V N u32 mem_allign2[8]; 185ff5b8ef2SMugunthan V N u32 rx_imax; 186ff5b8ef2SMugunthan V N u32 tx_imax; 187ff5b8ef2SMugunthan V N 188df828598SMugunthan V N }; 189df828598SMugunthan V N 190996a5c27SRichard Cochran struct cpsw_ss_regs { 191df828598SMugunthan V N u32 id_ver; 192df828598SMugunthan V N u32 control; 193df828598SMugunthan V N u32 soft_reset; 194df828598SMugunthan V N u32 stat_port_en; 195df828598SMugunthan V N u32 ptype; 196bd357af2SRichard Cochran u32 soft_idle; 197bd357af2SRichard Cochran u32 thru_rate; 198bd357af2SRichard Cochran u32 gap_thresh; 199bd357af2SRichard Cochran u32 tx_start_wds; 200bd357af2SRichard Cochran u32 flow_control; 201bd357af2SRichard Cochran u32 vlan_ltype; 202bd357af2SRichard Cochran u32 ts_ltype; 203bd357af2SRichard Cochran u32 dlr_ltype; 204df828598SMugunthan V N }; 205df828598SMugunthan V N 2069750a3adSRichard Cochran /* CPSW_PORT_V1 */ 2079750a3adSRichard Cochran #define CPSW1_MAX_BLKS 0x00 /* Maximum FIFO Blocks */ 2089750a3adSRichard Cochran #define CPSW1_BLK_CNT 0x04 /* FIFO Block Usage Count (Read Only) */ 2099750a3adSRichard Cochran #define CPSW1_TX_IN_CTL 0x08 /* Transmit FIFO Control */ 2109750a3adSRichard Cochran #define CPSW1_PORT_VLAN 0x0c /* VLAN Register */ 2119750a3adSRichard Cochran #define CPSW1_TX_PRI_MAP 0x10 /* Tx Header Priority to Switch Pri Mapping */ 2129750a3adSRichard Cochran #define CPSW1_TS_CTL 0x14 /* Time Sync Control */ 2139750a3adSRichard Cochran #define CPSW1_TS_SEQ_LTYPE 0x18 /* Time Sync Sequence ID Offset and Msg Type */ 2149750a3adSRichard Cochran #define CPSW1_TS_VLAN 0x1c /* Time Sync VLAN1 and VLAN2 */ 2159750a3adSRichard Cochran 2169750a3adSRichard Cochran /* CPSW_PORT_V2 */ 2179750a3adSRichard Cochran #define CPSW2_CONTROL 0x00 /* Control Register */ 2189750a3adSRichard Cochran #define CPSW2_MAX_BLKS 0x08 /* Maximum FIFO Blocks */ 2199750a3adSRichard Cochran #define CPSW2_BLK_CNT 0x0c /* FIFO Block Usage Count (Read Only) */ 2209750a3adSRichard Cochran #define CPSW2_TX_IN_CTL 0x10 /* Transmit FIFO Control */ 2219750a3adSRichard Cochran #define CPSW2_PORT_VLAN 0x14 /* VLAN Register */ 2229750a3adSRichard Cochran #define CPSW2_TX_PRI_MAP 0x18 /* Tx Header Priority to Switch Pri Mapping */ 2239750a3adSRichard Cochran #define CPSW2_TS_SEQ_MTYPE 0x1c /* Time Sync Sequence ID Offset and Msg Type */ 2249750a3adSRichard Cochran 2259750a3adSRichard Cochran /* CPSW_PORT_V1 and V2 */ 2269750a3adSRichard Cochran #define SA_LO 0x20 /* CPGMAC_SL Source Address Low */ 2279750a3adSRichard Cochran #define SA_HI 0x24 /* CPGMAC_SL Source Address High */ 2289750a3adSRichard Cochran #define SEND_PERCENT 0x28 /* Transmit Queue Send Percentages */ 2299750a3adSRichard Cochran 2309750a3adSRichard Cochran /* CPSW_PORT_V2 only */ 2319750a3adSRichard Cochran #define RX_DSCP_PRI_MAP0 0x30 /* Rx DSCP Priority to Rx Packet Mapping */ 2329750a3adSRichard Cochran #define RX_DSCP_PRI_MAP1 0x34 /* Rx DSCP Priority to Rx Packet Mapping */ 2339750a3adSRichard Cochran #define RX_DSCP_PRI_MAP2 0x38 /* Rx DSCP Priority to Rx Packet Mapping */ 2349750a3adSRichard Cochran #define RX_DSCP_PRI_MAP3 0x3c /* Rx DSCP Priority to Rx Packet Mapping */ 2359750a3adSRichard Cochran #define RX_DSCP_PRI_MAP4 0x40 /* Rx DSCP Priority to Rx Packet Mapping */ 2369750a3adSRichard Cochran #define RX_DSCP_PRI_MAP5 0x44 /* Rx DSCP Priority to Rx Packet Mapping */ 2379750a3adSRichard Cochran #define RX_DSCP_PRI_MAP6 0x48 /* Rx DSCP Priority to Rx Packet Mapping */ 2389750a3adSRichard Cochran #define RX_DSCP_PRI_MAP7 0x4c /* Rx DSCP Priority to Rx Packet Mapping */ 2399750a3adSRichard Cochran 2409750a3adSRichard Cochran /* Bit definitions for the CPSW2_CONTROL register */ 2419750a3adSRichard Cochran #define PASS_PRI_TAGGED (1<<24) /* Pass Priority Tagged */ 2429750a3adSRichard Cochran #define VLAN_LTYPE2_EN (1<<21) /* VLAN LTYPE 2 enable */ 2439750a3adSRichard Cochran #define VLAN_LTYPE1_EN (1<<20) /* VLAN LTYPE 1 enable */ 2449750a3adSRichard Cochran #define DSCP_PRI_EN (1<<16) /* DSCP Priority Enable */ 2459750a3adSRichard Cochran #define TS_320 (1<<14) /* Time Sync Dest Port 320 enable */ 2469750a3adSRichard Cochran #define TS_319 (1<<13) /* Time Sync Dest Port 319 enable */ 2479750a3adSRichard Cochran #define TS_132 (1<<12) /* Time Sync Dest IP Addr 132 enable */ 2489750a3adSRichard Cochran #define TS_131 (1<<11) /* Time Sync Dest IP Addr 131 enable */ 2499750a3adSRichard Cochran #define TS_130 (1<<10) /* Time Sync Dest IP Addr 130 enable */ 2509750a3adSRichard Cochran #define TS_129 (1<<9) /* Time Sync Dest IP Addr 129 enable */ 25109c55372SGeorge Cherian #define TS_TTL_NONZERO (1<<8) /* Time Sync Time To Live Non-zero enable */ 25209c55372SGeorge Cherian #define TS_ANNEX_F_EN (1<<6) /* Time Sync Annex F enable */ 2539750a3adSRichard Cochran #define TS_ANNEX_D_EN (1<<4) /* Time Sync Annex D enable */ 2549750a3adSRichard Cochran #define TS_LTYPE2_EN (1<<3) /* Time Sync LTYPE 2 enable */ 2559750a3adSRichard Cochran #define TS_LTYPE1_EN (1<<2) /* Time Sync LTYPE 1 enable */ 2569750a3adSRichard Cochran #define TS_TX_EN (1<<1) /* Time Sync Transmit Enable */ 2579750a3adSRichard Cochran #define TS_RX_EN (1<<0) /* Time Sync Receive Enable */ 2589750a3adSRichard Cochran 25909c55372SGeorge Cherian #define CTRL_V2_TS_BITS \ 26009c55372SGeorge Cherian (TS_320 | TS_319 | TS_132 | TS_131 | TS_130 | TS_129 |\ 26109c55372SGeorge Cherian TS_TTL_NONZERO | TS_ANNEX_D_EN | TS_LTYPE1_EN) 2629750a3adSRichard Cochran 26309c55372SGeorge Cherian #define CTRL_V2_ALL_TS_MASK (CTRL_V2_TS_BITS | TS_TX_EN | TS_RX_EN) 26409c55372SGeorge Cherian #define CTRL_V2_TX_TS_BITS (CTRL_V2_TS_BITS | TS_TX_EN) 26509c55372SGeorge Cherian #define CTRL_V2_RX_TS_BITS (CTRL_V2_TS_BITS | TS_RX_EN) 26609c55372SGeorge Cherian 26709c55372SGeorge Cherian 26809c55372SGeorge Cherian #define CTRL_V3_TS_BITS \ 26909c55372SGeorge Cherian (TS_320 | TS_319 | TS_132 | TS_131 | TS_130 | TS_129 |\ 27009c55372SGeorge Cherian TS_TTL_NONZERO | TS_ANNEX_F_EN | TS_ANNEX_D_EN |\ 27109c55372SGeorge Cherian TS_LTYPE1_EN) 27209c55372SGeorge Cherian 27309c55372SGeorge Cherian #define CTRL_V3_ALL_TS_MASK (CTRL_V3_TS_BITS | TS_TX_EN | TS_RX_EN) 27409c55372SGeorge Cherian #define CTRL_V3_TX_TS_BITS (CTRL_V3_TS_BITS | TS_TX_EN) 27509c55372SGeorge Cherian #define CTRL_V3_RX_TS_BITS (CTRL_V3_TS_BITS | TS_RX_EN) 2769750a3adSRichard Cochran 2779750a3adSRichard Cochran /* Bit definitions for the CPSW2_TS_SEQ_MTYPE register */ 2789750a3adSRichard Cochran #define TS_SEQ_ID_OFFSET_SHIFT (16) /* Time Sync Sequence ID Offset */ 2799750a3adSRichard Cochran #define TS_SEQ_ID_OFFSET_MASK (0x3f) 2809750a3adSRichard Cochran #define TS_MSG_TYPE_EN_SHIFT (0) /* Time Sync Message Type Enable */ 2819750a3adSRichard Cochran #define TS_MSG_TYPE_EN_MASK (0xffff) 2829750a3adSRichard Cochran 2839750a3adSRichard Cochran /* The PTP event messages - Sync, Delay_Req, Pdelay_Req, and Pdelay_Resp. */ 2849750a3adSRichard Cochran #define EVENT_MSG_BITS ((1<<0) | (1<<1) | (1<<2) | (1<<3)) 285df828598SMugunthan V N 2862e5b38abSRichard Cochran /* Bit definitions for the CPSW1_TS_CTL register */ 2872e5b38abSRichard Cochran #define CPSW_V1_TS_RX_EN BIT(0) 2882e5b38abSRichard Cochran #define CPSW_V1_TS_TX_EN BIT(4) 2892e5b38abSRichard Cochran #define CPSW_V1_MSG_TYPE_OFS 16 2902e5b38abSRichard Cochran 2912e5b38abSRichard Cochran /* Bit definitions for the CPSW1_TS_SEQ_LTYPE register */ 2922e5b38abSRichard Cochran #define CPSW_V1_SEQ_ID_OFS_SHIFT 16 2932e5b38abSRichard Cochran 294df828598SMugunthan V N struct cpsw_host_regs { 295df828598SMugunthan V N u32 max_blks; 296df828598SMugunthan V N u32 blk_cnt; 297d9ba8f9eSMugunthan V N u32 tx_in_ctl; 298df828598SMugunthan V N u32 port_vlan; 299df828598SMugunthan V N u32 tx_pri_map; 300df828598SMugunthan V N u32 cpdma_tx_pri_map; 301df828598SMugunthan V N u32 cpdma_rx_chan_map; 302df828598SMugunthan V N }; 303df828598SMugunthan V N 304df828598SMugunthan V N struct cpsw_sliver_regs { 305df828598SMugunthan V N u32 id_ver; 306df828598SMugunthan V N u32 mac_control; 307df828598SMugunthan V N u32 mac_status; 308df828598SMugunthan V N u32 soft_reset; 309df828598SMugunthan V N u32 rx_maxlen; 310df828598SMugunthan V N u32 __reserved_0; 311df828598SMugunthan V N u32 rx_pause; 312df828598SMugunthan V N u32 tx_pause; 313df828598SMugunthan V N u32 __reserved_1; 314df828598SMugunthan V N u32 rx_pri_map; 315df828598SMugunthan V N }; 316df828598SMugunthan V N 317d9718546SMugunthan V N struct cpsw_hw_stats { 318d9718546SMugunthan V N u32 rxgoodframes; 319d9718546SMugunthan V N u32 rxbroadcastframes; 320d9718546SMugunthan V N u32 rxmulticastframes; 321d9718546SMugunthan V N u32 rxpauseframes; 322d9718546SMugunthan V N u32 rxcrcerrors; 323d9718546SMugunthan V N u32 rxaligncodeerrors; 324d9718546SMugunthan V N u32 rxoversizedframes; 325d9718546SMugunthan V N u32 rxjabberframes; 326d9718546SMugunthan V N u32 rxundersizedframes; 327d9718546SMugunthan V N u32 rxfragments; 328d9718546SMugunthan V N u32 __pad_0[2]; 329d9718546SMugunthan V N u32 rxoctets; 330d9718546SMugunthan V N u32 txgoodframes; 331d9718546SMugunthan V N u32 txbroadcastframes; 332d9718546SMugunthan V N u32 txmulticastframes; 333d9718546SMugunthan V N u32 txpauseframes; 334d9718546SMugunthan V N u32 txdeferredframes; 335d9718546SMugunthan V N u32 txcollisionframes; 336d9718546SMugunthan V N u32 txsinglecollframes; 337d9718546SMugunthan V N u32 txmultcollframes; 338d9718546SMugunthan V N u32 txexcessivecollisions; 339d9718546SMugunthan V N u32 txlatecollisions; 340d9718546SMugunthan V N u32 txunderrun; 341d9718546SMugunthan V N u32 txcarriersenseerrors; 342d9718546SMugunthan V N u32 txoctets; 343d9718546SMugunthan V N u32 octetframes64; 344d9718546SMugunthan V N u32 octetframes65t127; 345d9718546SMugunthan V N u32 octetframes128t255; 346d9718546SMugunthan V N u32 octetframes256t511; 347d9718546SMugunthan V N u32 octetframes512t1023; 348d9718546SMugunthan V N u32 octetframes1024tup; 349d9718546SMugunthan V N u32 netoctets; 350d9718546SMugunthan V N u32 rxsofoverruns; 351d9718546SMugunthan V N u32 rxmofoverruns; 352d9718546SMugunthan V N u32 rxdmaoverruns; 353d9718546SMugunthan V N }; 354d9718546SMugunthan V N 355df828598SMugunthan V N struct cpsw_slave { 3569750a3adSRichard Cochran void __iomem *regs; 357df828598SMugunthan V N struct cpsw_sliver_regs __iomem *sliver; 358df828598SMugunthan V N int slave_num; 359df828598SMugunthan V N u32 mac_control; 360df828598SMugunthan V N struct cpsw_slave_data *data; 361df828598SMugunthan V N struct phy_device *phy; 362d9ba8f9eSMugunthan V N struct net_device *ndev; 363d9ba8f9eSMugunthan V N u32 port_vlan; 364d9ba8f9eSMugunthan V N u32 open_stat; 365df828598SMugunthan V N }; 366df828598SMugunthan V N 3679750a3adSRichard Cochran static inline u32 slave_read(struct cpsw_slave *slave, u32 offset) 3689750a3adSRichard Cochran { 3699750a3adSRichard Cochran return __raw_readl(slave->regs + offset); 3709750a3adSRichard Cochran } 3719750a3adSRichard Cochran 3729750a3adSRichard Cochran static inline void slave_write(struct cpsw_slave *slave, u32 val, u32 offset) 3739750a3adSRichard Cochran { 3749750a3adSRichard Cochran __raw_writel(val, slave->regs + offset); 3759750a3adSRichard Cochran } 3769750a3adSRichard Cochran 377df828598SMugunthan V N struct cpsw_priv { 378df828598SMugunthan V N spinlock_t lock; 379df828598SMugunthan V N struct platform_device *pdev; 380df828598SMugunthan V N struct net_device *ndev; 381df828598SMugunthan V N struct napi_struct napi; 382df828598SMugunthan V N struct device *dev; 383df828598SMugunthan V N struct cpsw_platform_data data; 384996a5c27SRichard Cochran struct cpsw_ss_regs __iomem *regs; 385996a5c27SRichard Cochran struct cpsw_wr_regs __iomem *wr_regs; 386d9718546SMugunthan V N u8 __iomem *hw_stats; 387df828598SMugunthan V N struct cpsw_host_regs __iomem *host_port_regs; 388df828598SMugunthan V N u32 msg_enable; 389e90cfac6SRichard Cochran u32 version; 390ff5b8ef2SMugunthan V N u32 coal_intvl; 391ff5b8ef2SMugunthan V N u32 bus_freq_mhz; 392df828598SMugunthan V N int rx_packet_max; 393df828598SMugunthan V N int host_port; 394df828598SMugunthan V N struct clk *clk; 395df828598SMugunthan V N u8 mac_addr[ETH_ALEN]; 396df828598SMugunthan V N struct cpsw_slave *slaves; 397df828598SMugunthan V N struct cpdma_ctlr *dma; 398df828598SMugunthan V N struct cpdma_chan *txch, *rxch; 399df828598SMugunthan V N struct cpsw_ale *ale; 4001923d6e4SMugunthan V N bool rx_pause; 4011923d6e4SMugunthan V N bool tx_pause; 402df828598SMugunthan V N /* snapshot of IRQ numbers */ 403df828598SMugunthan V N u32 irqs_table[4]; 404df828598SMugunthan V N u32 num_irqs; 405a11fbba9SSebastian Siewior bool irq_enabled; 4069232b16dSMugunthan V N struct cpts *cpts; 407d9ba8f9eSMugunthan V N u32 emac_port; 408df828598SMugunthan V N }; 409df828598SMugunthan V N 410d9718546SMugunthan V N struct cpsw_stats { 411d9718546SMugunthan V N char stat_string[ETH_GSTRING_LEN]; 412d9718546SMugunthan V N int type; 413d9718546SMugunthan V N int sizeof_stat; 414d9718546SMugunthan V N int stat_offset; 415d9718546SMugunthan V N }; 416d9718546SMugunthan V N 417d9718546SMugunthan V N enum { 418d9718546SMugunthan V N CPSW_STATS, 419d9718546SMugunthan V N CPDMA_RX_STATS, 420d9718546SMugunthan V N CPDMA_TX_STATS, 421d9718546SMugunthan V N }; 422d9718546SMugunthan V N 423d9718546SMugunthan V N #define CPSW_STAT(m) CPSW_STATS, \ 424d9718546SMugunthan V N sizeof(((struct cpsw_hw_stats *)0)->m), \ 425d9718546SMugunthan V N offsetof(struct cpsw_hw_stats, m) 426d9718546SMugunthan V N #define CPDMA_RX_STAT(m) CPDMA_RX_STATS, \ 427d9718546SMugunthan V N sizeof(((struct cpdma_chan_stats *)0)->m), \ 428d9718546SMugunthan V N offsetof(struct cpdma_chan_stats, m) 429d9718546SMugunthan V N #define CPDMA_TX_STAT(m) CPDMA_TX_STATS, \ 430d9718546SMugunthan V N sizeof(((struct cpdma_chan_stats *)0)->m), \ 431d9718546SMugunthan V N offsetof(struct cpdma_chan_stats, m) 432d9718546SMugunthan V N 433d9718546SMugunthan V N static const struct cpsw_stats cpsw_gstrings_stats[] = { 434d9718546SMugunthan V N { "Good Rx Frames", CPSW_STAT(rxgoodframes) }, 435d9718546SMugunthan V N { "Broadcast Rx Frames", CPSW_STAT(rxbroadcastframes) }, 436d9718546SMugunthan V N { "Multicast Rx Frames", CPSW_STAT(rxmulticastframes) }, 437d9718546SMugunthan V N { "Pause Rx Frames", CPSW_STAT(rxpauseframes) }, 438d9718546SMugunthan V N { "Rx CRC Errors", CPSW_STAT(rxcrcerrors) }, 439d9718546SMugunthan V N { "Rx Align/Code Errors", CPSW_STAT(rxaligncodeerrors) }, 440d9718546SMugunthan V N { "Oversize Rx Frames", CPSW_STAT(rxoversizedframes) }, 441d9718546SMugunthan V N { "Rx Jabbers", CPSW_STAT(rxjabberframes) }, 442d9718546SMugunthan V N { "Undersize (Short) Rx Frames", CPSW_STAT(rxundersizedframes) }, 443d9718546SMugunthan V N { "Rx Fragments", CPSW_STAT(rxfragments) }, 444d9718546SMugunthan V N { "Rx Octets", CPSW_STAT(rxoctets) }, 445d9718546SMugunthan V N { "Good Tx Frames", CPSW_STAT(txgoodframes) }, 446d9718546SMugunthan V N { "Broadcast Tx Frames", CPSW_STAT(txbroadcastframes) }, 447d9718546SMugunthan V N { "Multicast Tx Frames", CPSW_STAT(txmulticastframes) }, 448d9718546SMugunthan V N { "Pause Tx Frames", CPSW_STAT(txpauseframes) }, 449d9718546SMugunthan V N { "Deferred Tx Frames", CPSW_STAT(txdeferredframes) }, 450d9718546SMugunthan V N { "Collisions", CPSW_STAT(txcollisionframes) }, 451d9718546SMugunthan V N { "Single Collision Tx Frames", CPSW_STAT(txsinglecollframes) }, 452d9718546SMugunthan V N { "Multiple Collision Tx Frames", CPSW_STAT(txmultcollframes) }, 453d9718546SMugunthan V N { "Excessive Collisions", CPSW_STAT(txexcessivecollisions) }, 454d9718546SMugunthan V N { "Late Collisions", CPSW_STAT(txlatecollisions) }, 455d9718546SMugunthan V N { "Tx Underrun", CPSW_STAT(txunderrun) }, 456d9718546SMugunthan V N { "Carrier Sense Errors", CPSW_STAT(txcarriersenseerrors) }, 457d9718546SMugunthan V N { "Tx Octets", CPSW_STAT(txoctets) }, 458d9718546SMugunthan V N { "Rx + Tx 64 Octet Frames", CPSW_STAT(octetframes64) }, 459d9718546SMugunthan V N { "Rx + Tx 65-127 Octet Frames", CPSW_STAT(octetframes65t127) }, 460d9718546SMugunthan V N { "Rx + Tx 128-255 Octet Frames", CPSW_STAT(octetframes128t255) }, 461d9718546SMugunthan V N { "Rx + Tx 256-511 Octet Frames", CPSW_STAT(octetframes256t511) }, 462d9718546SMugunthan V N { "Rx + Tx 512-1023 Octet Frames", CPSW_STAT(octetframes512t1023) }, 463d9718546SMugunthan V N { "Rx + Tx 1024-Up Octet Frames", CPSW_STAT(octetframes1024tup) }, 464d9718546SMugunthan V N { "Net Octets", CPSW_STAT(netoctets) }, 465d9718546SMugunthan V N { "Rx Start of Frame Overruns", CPSW_STAT(rxsofoverruns) }, 466d9718546SMugunthan V N { "Rx Middle of Frame Overruns", CPSW_STAT(rxmofoverruns) }, 467d9718546SMugunthan V N { "Rx DMA Overruns", CPSW_STAT(rxdmaoverruns) }, 468d9718546SMugunthan V N { "Rx DMA chan: head_enqueue", CPDMA_RX_STAT(head_enqueue) }, 469d9718546SMugunthan V N { "Rx DMA chan: tail_enqueue", CPDMA_RX_STAT(tail_enqueue) }, 470d9718546SMugunthan V N { "Rx DMA chan: pad_enqueue", CPDMA_RX_STAT(pad_enqueue) }, 471d9718546SMugunthan V N { "Rx DMA chan: misqueued", CPDMA_RX_STAT(misqueued) }, 472d9718546SMugunthan V N { "Rx DMA chan: desc_alloc_fail", CPDMA_RX_STAT(desc_alloc_fail) }, 473d9718546SMugunthan V N { "Rx DMA chan: pad_alloc_fail", CPDMA_RX_STAT(pad_alloc_fail) }, 474d9718546SMugunthan V N { "Rx DMA chan: runt_receive_buf", CPDMA_RX_STAT(runt_receive_buff) }, 475d9718546SMugunthan V N { "Rx DMA chan: runt_transmit_buf", CPDMA_RX_STAT(runt_transmit_buff) }, 476d9718546SMugunthan V N { "Rx DMA chan: empty_dequeue", CPDMA_RX_STAT(empty_dequeue) }, 477d9718546SMugunthan V N { "Rx DMA chan: busy_dequeue", CPDMA_RX_STAT(busy_dequeue) }, 478d9718546SMugunthan V N { "Rx DMA chan: good_dequeue", CPDMA_RX_STAT(good_dequeue) }, 479d9718546SMugunthan V N { "Rx DMA chan: requeue", CPDMA_RX_STAT(requeue) }, 480d9718546SMugunthan V N { "Rx DMA chan: teardown_dequeue", CPDMA_RX_STAT(teardown_dequeue) }, 481d9718546SMugunthan V N { "Tx DMA chan: head_enqueue", CPDMA_TX_STAT(head_enqueue) }, 482d9718546SMugunthan V N { "Tx DMA chan: tail_enqueue", CPDMA_TX_STAT(tail_enqueue) }, 483d9718546SMugunthan V N { "Tx DMA chan: pad_enqueue", CPDMA_TX_STAT(pad_enqueue) }, 484d9718546SMugunthan V N { "Tx DMA chan: misqueued", CPDMA_TX_STAT(misqueued) }, 485d9718546SMugunthan V N { "Tx DMA chan: desc_alloc_fail", CPDMA_TX_STAT(desc_alloc_fail) }, 486d9718546SMugunthan V N { "Tx DMA chan: pad_alloc_fail", CPDMA_TX_STAT(pad_alloc_fail) }, 487d9718546SMugunthan V N { "Tx DMA chan: runt_receive_buf", CPDMA_TX_STAT(runt_receive_buff) }, 488d9718546SMugunthan V N { "Tx DMA chan: runt_transmit_buf", CPDMA_TX_STAT(runt_transmit_buff) }, 489d9718546SMugunthan V N { "Tx DMA chan: empty_dequeue", CPDMA_TX_STAT(empty_dequeue) }, 490d9718546SMugunthan V N { "Tx DMA chan: busy_dequeue", CPDMA_TX_STAT(busy_dequeue) }, 491d9718546SMugunthan V N { "Tx DMA chan: good_dequeue", CPDMA_TX_STAT(good_dequeue) }, 492d9718546SMugunthan V N { "Tx DMA chan: requeue", CPDMA_TX_STAT(requeue) }, 493d9718546SMugunthan V N { "Tx DMA chan: teardown_dequeue", CPDMA_TX_STAT(teardown_dequeue) }, 494d9718546SMugunthan V N }; 495d9718546SMugunthan V N 496d9718546SMugunthan V N #define CPSW_STATS_LEN ARRAY_SIZE(cpsw_gstrings_stats) 497d9718546SMugunthan V N 498df828598SMugunthan V N #define napi_to_priv(napi) container_of(napi, struct cpsw_priv, napi) 499df828598SMugunthan V N #define for_each_slave(priv, func, arg...) \ 500df828598SMugunthan V N do { \ 5016e6ceaedSSebastian Siewior struct cpsw_slave *slave; \ 5026e6ceaedSSebastian Siewior int n; \ 503d9ba8f9eSMugunthan V N if (priv->data.dual_emac) \ 504d9ba8f9eSMugunthan V N (func)((priv)->slaves + priv->emac_port, ##arg);\ 505d9ba8f9eSMugunthan V N else \ 5066e6ceaedSSebastian Siewior for (n = (priv)->data.slaves, \ 5076e6ceaedSSebastian Siewior slave = (priv)->slaves; \ 5086e6ceaedSSebastian Siewior n; n--) \ 5096e6ceaedSSebastian Siewior (func)(slave++, ##arg); \ 510df828598SMugunthan V N } while (0) 511d9ba8f9eSMugunthan V N #define cpsw_get_slave_ndev(priv, __slave_no__) \ 5121973db0dSMugunthan V N ((__slave_no__ < priv->data.slaves) ? \ 5131973db0dSMugunthan V N priv->slaves[__slave_no__].ndev : NULL) 514d9ba8f9eSMugunthan V N #define cpsw_get_slave_priv(priv, __slave_no__) \ 5151973db0dSMugunthan V N (((__slave_no__ < priv->data.slaves) && \ 5161973db0dSMugunthan V N (priv->slaves[__slave_no__].ndev)) ? \ 517d9ba8f9eSMugunthan V N netdev_priv(priv->slaves[__slave_no__].ndev) : NULL) \ 518d9ba8f9eSMugunthan V N 519d9ba8f9eSMugunthan V N #define cpsw_dual_emac_src_port_detect(status, priv, ndev, skb) \ 520d9ba8f9eSMugunthan V N do { \ 521d9ba8f9eSMugunthan V N if (!priv->data.dual_emac) \ 522d9ba8f9eSMugunthan V N break; \ 523d9ba8f9eSMugunthan V N if (CPDMA_RX_SOURCE_PORT(status) == 1) { \ 524d9ba8f9eSMugunthan V N ndev = cpsw_get_slave_ndev(priv, 0); \ 525d9ba8f9eSMugunthan V N priv = netdev_priv(ndev); \ 526d9ba8f9eSMugunthan V N skb->dev = ndev; \ 527d9ba8f9eSMugunthan V N } else if (CPDMA_RX_SOURCE_PORT(status) == 2) { \ 528d9ba8f9eSMugunthan V N ndev = cpsw_get_slave_ndev(priv, 1); \ 529d9ba8f9eSMugunthan V N priv = netdev_priv(ndev); \ 530d9ba8f9eSMugunthan V N skb->dev = ndev; \ 531d9ba8f9eSMugunthan V N } \ 532d9ba8f9eSMugunthan V N } while (0) 533d9ba8f9eSMugunthan V N #define cpsw_add_mcast(priv, addr) \ 534d9ba8f9eSMugunthan V N do { \ 535d9ba8f9eSMugunthan V N if (priv->data.dual_emac) { \ 536d9ba8f9eSMugunthan V N struct cpsw_slave *slave = priv->slaves + \ 537d9ba8f9eSMugunthan V N priv->emac_port; \ 538d9ba8f9eSMugunthan V N int slave_port = cpsw_get_slave_port(priv, \ 539d9ba8f9eSMugunthan V N slave->slave_num); \ 540d9ba8f9eSMugunthan V N cpsw_ale_add_mcast(priv->ale, addr, \ 541d9ba8f9eSMugunthan V N 1 << slave_port | 1 << priv->host_port, \ 542d9ba8f9eSMugunthan V N ALE_VLAN, slave->port_vlan, 0); \ 543d9ba8f9eSMugunthan V N } else { \ 544d9ba8f9eSMugunthan V N cpsw_ale_add_mcast(priv->ale, addr, \ 545d9ba8f9eSMugunthan V N ALE_ALL_PORTS << priv->host_port, \ 546d9ba8f9eSMugunthan V N 0, 0, 0); \ 547d9ba8f9eSMugunthan V N } \ 548d9ba8f9eSMugunthan V N } while (0) 549d9ba8f9eSMugunthan V N 550d9ba8f9eSMugunthan V N static inline int cpsw_get_slave_port(struct cpsw_priv *priv, u32 slave_num) 551d9ba8f9eSMugunthan V N { 552d9ba8f9eSMugunthan V N if (priv->host_port == 0) 553d9ba8f9eSMugunthan V N return slave_num + 1; 554d9ba8f9eSMugunthan V N else 555d9ba8f9eSMugunthan V N return slave_num; 556d9ba8f9eSMugunthan V N } 557df828598SMugunthan V N 5580cd8f9ccSMugunthan V N static void cpsw_set_promiscious(struct net_device *ndev, bool enable) 5590cd8f9ccSMugunthan V N { 5600cd8f9ccSMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 5610cd8f9ccSMugunthan V N struct cpsw_ale *ale = priv->ale; 5620cd8f9ccSMugunthan V N int i; 5630cd8f9ccSMugunthan V N 5640cd8f9ccSMugunthan V N if (priv->data.dual_emac) { 5650cd8f9ccSMugunthan V N bool flag = false; 5660cd8f9ccSMugunthan V N 5670cd8f9ccSMugunthan V N /* Enabling promiscuous mode for one interface will be 5680cd8f9ccSMugunthan V N * common for both the interface as the interface shares 5690cd8f9ccSMugunthan V N * the same hardware resource. 5700cd8f9ccSMugunthan V N */ 5710d961b3bSHeiko Schocher for (i = 0; i < priv->data.slaves; i++) 5720cd8f9ccSMugunthan V N if (priv->slaves[i].ndev->flags & IFF_PROMISC) 5730cd8f9ccSMugunthan V N flag = true; 5740cd8f9ccSMugunthan V N 5750cd8f9ccSMugunthan V N if (!enable && flag) { 5760cd8f9ccSMugunthan V N enable = true; 5770cd8f9ccSMugunthan V N dev_err(&ndev->dev, "promiscuity not disabled as the other interface is still in promiscuity mode\n"); 5780cd8f9ccSMugunthan V N } 5790cd8f9ccSMugunthan V N 5800cd8f9ccSMugunthan V N if (enable) { 5810cd8f9ccSMugunthan V N /* Enable Bypass */ 5820cd8f9ccSMugunthan V N cpsw_ale_control_set(ale, 0, ALE_BYPASS, 1); 5830cd8f9ccSMugunthan V N 5840cd8f9ccSMugunthan V N dev_dbg(&ndev->dev, "promiscuity enabled\n"); 5850cd8f9ccSMugunthan V N } else { 5860cd8f9ccSMugunthan V N /* Disable Bypass */ 5870cd8f9ccSMugunthan V N cpsw_ale_control_set(ale, 0, ALE_BYPASS, 0); 5880cd8f9ccSMugunthan V N dev_dbg(&ndev->dev, "promiscuity disabled\n"); 5890cd8f9ccSMugunthan V N } 5900cd8f9ccSMugunthan V N } else { 5910cd8f9ccSMugunthan V N if (enable) { 5920cd8f9ccSMugunthan V N unsigned long timeout = jiffies + HZ; 5930cd8f9ccSMugunthan V N 5946f979eb3SLennart Sorensen /* Disable Learn for all ports (host is port 0 and slaves are port 1 and up */ 5956f979eb3SLennart Sorensen for (i = 0; i <= priv->data.slaves; i++) { 5960cd8f9ccSMugunthan V N cpsw_ale_control_set(ale, i, 5970cd8f9ccSMugunthan V N ALE_PORT_NOLEARN, 1); 5980cd8f9ccSMugunthan V N cpsw_ale_control_set(ale, i, 5990cd8f9ccSMugunthan V N ALE_PORT_NO_SA_UPDATE, 1); 6000cd8f9ccSMugunthan V N } 6010cd8f9ccSMugunthan V N 6020cd8f9ccSMugunthan V N /* Clear All Untouched entries */ 6030cd8f9ccSMugunthan V N cpsw_ale_control_set(ale, 0, ALE_AGEOUT, 1); 6040cd8f9ccSMugunthan V N do { 6050cd8f9ccSMugunthan V N cpu_relax(); 6060cd8f9ccSMugunthan V N if (cpsw_ale_control_get(ale, 0, ALE_AGEOUT)) 6070cd8f9ccSMugunthan V N break; 6080cd8f9ccSMugunthan V N } while (time_after(timeout, jiffies)); 6090cd8f9ccSMugunthan V N cpsw_ale_control_set(ale, 0, ALE_AGEOUT, 1); 6100cd8f9ccSMugunthan V N 6110cd8f9ccSMugunthan V N /* Clear all mcast from ALE */ 6120cd8f9ccSMugunthan V N cpsw_ale_flush_multicast(ale, ALE_ALL_PORTS << 61325906052SMugunthan V N priv->host_port, -1); 6140cd8f9ccSMugunthan V N 6150cd8f9ccSMugunthan V N /* Flood All Unicast Packets to Host port */ 6160cd8f9ccSMugunthan V N cpsw_ale_control_set(ale, 0, ALE_P0_UNI_FLOOD, 1); 6170cd8f9ccSMugunthan V N dev_dbg(&ndev->dev, "promiscuity enabled\n"); 6180cd8f9ccSMugunthan V N } else { 6196f979eb3SLennart Sorensen /* Don't Flood All Unicast Packets to Host port */ 6200cd8f9ccSMugunthan V N cpsw_ale_control_set(ale, 0, ALE_P0_UNI_FLOOD, 0); 6210cd8f9ccSMugunthan V N 6226f979eb3SLennart Sorensen /* Enable Learn for all ports (host is port 0 and slaves are port 1 and up */ 6236f979eb3SLennart Sorensen for (i = 0; i <= priv->data.slaves; i++) { 6240cd8f9ccSMugunthan V N cpsw_ale_control_set(ale, i, 6250cd8f9ccSMugunthan V N ALE_PORT_NOLEARN, 0); 6260cd8f9ccSMugunthan V N cpsw_ale_control_set(ale, i, 6270cd8f9ccSMugunthan V N ALE_PORT_NO_SA_UPDATE, 0); 6280cd8f9ccSMugunthan V N } 6290cd8f9ccSMugunthan V N dev_dbg(&ndev->dev, "promiscuity disabled\n"); 6300cd8f9ccSMugunthan V N } 6310cd8f9ccSMugunthan V N } 6320cd8f9ccSMugunthan V N } 6330cd8f9ccSMugunthan V N 6345c50a856SMugunthan V N static void cpsw_ndo_set_rx_mode(struct net_device *ndev) 6355c50a856SMugunthan V N { 6365c50a856SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 63725906052SMugunthan V N int vid; 63825906052SMugunthan V N 63925906052SMugunthan V N if (priv->data.dual_emac) 64025906052SMugunthan V N vid = priv->slaves[priv->emac_port].port_vlan; 64125906052SMugunthan V N else 64225906052SMugunthan V N vid = priv->data.default_vlan; 6435c50a856SMugunthan V N 6445c50a856SMugunthan V N if (ndev->flags & IFF_PROMISC) { 6455c50a856SMugunthan V N /* Enable promiscuous mode */ 6460cd8f9ccSMugunthan V N cpsw_set_promiscious(ndev, true); 6471e5c4bc4SLennart Sorensen cpsw_ale_set_allmulti(priv->ale, IFF_ALLMULTI); 6485c50a856SMugunthan V N return; 6490cd8f9ccSMugunthan V N } else { 6500cd8f9ccSMugunthan V N /* Disable promiscuous mode */ 6510cd8f9ccSMugunthan V N cpsw_set_promiscious(ndev, false); 6525c50a856SMugunthan V N } 6535c50a856SMugunthan V N 6541e5c4bc4SLennart Sorensen /* Restore allmulti on vlans if necessary */ 6551e5c4bc4SLennart Sorensen cpsw_ale_set_allmulti(priv->ale, priv->ndev->flags & IFF_ALLMULTI); 6561e5c4bc4SLennart Sorensen 6575c50a856SMugunthan V N /* Clear all mcast from ALE */ 65825906052SMugunthan V N cpsw_ale_flush_multicast(priv->ale, ALE_ALL_PORTS << priv->host_port, 65925906052SMugunthan V N vid); 6605c50a856SMugunthan V N 6615c50a856SMugunthan V N if (!netdev_mc_empty(ndev)) { 6625c50a856SMugunthan V N struct netdev_hw_addr *ha; 6635c50a856SMugunthan V N 6645c50a856SMugunthan V N /* program multicast address list into ALE register */ 6655c50a856SMugunthan V N netdev_for_each_mc_addr(ha, ndev) { 666d9ba8f9eSMugunthan V N cpsw_add_mcast(priv, (u8 *)ha->addr); 6675c50a856SMugunthan V N } 6685c50a856SMugunthan V N } 6695c50a856SMugunthan V N } 6705c50a856SMugunthan V N 671df828598SMugunthan V N static void cpsw_intr_enable(struct cpsw_priv *priv) 672df828598SMugunthan V N { 673996a5c27SRichard Cochran __raw_writel(0xFF, &priv->wr_regs->tx_en); 674996a5c27SRichard Cochran __raw_writel(0xFF, &priv->wr_regs->rx_en); 675df828598SMugunthan V N 676df828598SMugunthan V N cpdma_ctlr_int_ctrl(priv->dma, true); 677df828598SMugunthan V N return; 678df828598SMugunthan V N } 679df828598SMugunthan V N 680df828598SMugunthan V N static void cpsw_intr_disable(struct cpsw_priv *priv) 681df828598SMugunthan V N { 682996a5c27SRichard Cochran __raw_writel(0, &priv->wr_regs->tx_en); 683996a5c27SRichard Cochran __raw_writel(0, &priv->wr_regs->rx_en); 684df828598SMugunthan V N 685df828598SMugunthan V N cpdma_ctlr_int_ctrl(priv->dma, false); 686df828598SMugunthan V N return; 687df828598SMugunthan V N } 688df828598SMugunthan V N 6891a3b5056SOlof Johansson static void cpsw_tx_handler(void *token, int len, int status) 690df828598SMugunthan V N { 691df828598SMugunthan V N struct sk_buff *skb = token; 692df828598SMugunthan V N struct net_device *ndev = skb->dev; 693df828598SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 694df828598SMugunthan V N 695fae50823SMugunthan V N /* Check whether the queue is stopped due to stalled tx dma, if the 696fae50823SMugunthan V N * queue is stopped then start the queue as we have free desc for tx 697fae50823SMugunthan V N */ 698df828598SMugunthan V N if (unlikely(netif_queue_stopped(ndev))) 699b56d6b3fSMugunthan V N netif_wake_queue(ndev); 7009232b16dSMugunthan V N cpts_tx_timestamp(priv->cpts, skb); 7018dc43ddcSTobias Klauser ndev->stats.tx_packets++; 7028dc43ddcSTobias Klauser ndev->stats.tx_bytes += len; 703df828598SMugunthan V N dev_kfree_skb_any(skb); 704df828598SMugunthan V N } 705df828598SMugunthan V N 7061a3b5056SOlof Johansson static void cpsw_rx_handler(void *token, int len, int status) 707df828598SMugunthan V N { 708df828598SMugunthan V N struct sk_buff *skb = token; 709b4727e69SSebastian Siewior struct sk_buff *new_skb; 710df828598SMugunthan V N struct net_device *ndev = skb->dev; 711df828598SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 712df828598SMugunthan V N int ret = 0; 713df828598SMugunthan V N 714d9ba8f9eSMugunthan V N cpsw_dual_emac_src_port_detect(status, priv, ndev, skb); 715d9ba8f9eSMugunthan V N 71616e5c57dSMugunthan V N if (unlikely(status < 0) || unlikely(!netif_running(ndev))) { 717a0e2c822SMugunthan V N bool ndev_status = false; 718a0e2c822SMugunthan V N struct cpsw_slave *slave = priv->slaves; 719a0e2c822SMugunthan V N int n; 720a0e2c822SMugunthan V N 721a0e2c822SMugunthan V N if (priv->data.dual_emac) { 722a0e2c822SMugunthan V N /* In dual emac mode check for all interfaces */ 723a0e2c822SMugunthan V N for (n = priv->data.slaves; n; n--, slave++) 724a0e2c822SMugunthan V N if (netif_running(slave->ndev)) 725a0e2c822SMugunthan V N ndev_status = true; 726a0e2c822SMugunthan V N } 727a0e2c822SMugunthan V N 728a0e2c822SMugunthan V N if (ndev_status && (status >= 0)) { 729a0e2c822SMugunthan V N /* The packet received is for the interface which 730a0e2c822SMugunthan V N * is already down and the other interface is up 731dbedd44eSJoe Perches * and running, instead of freeing which results 732a0e2c822SMugunthan V N * in reducing of the number of rx descriptor in 733a0e2c822SMugunthan V N * DMA engine, requeue skb back to cpdma. 734a0e2c822SMugunthan V N */ 735a0e2c822SMugunthan V N new_skb = skb; 736a0e2c822SMugunthan V N goto requeue; 737a0e2c822SMugunthan V N } 738a0e2c822SMugunthan V N 739b4727e69SSebastian Siewior /* the interface is going down, skbs are purged */ 740df828598SMugunthan V N dev_kfree_skb_any(skb); 741df828598SMugunthan V N return; 742df828598SMugunthan V N } 743b4727e69SSebastian Siewior 744b4727e69SSebastian Siewior new_skb = netdev_alloc_skb_ip_align(ndev, priv->rx_packet_max); 745b4727e69SSebastian Siewior if (new_skb) { 746df828598SMugunthan V N skb_put(skb, len); 7479232b16dSMugunthan V N cpts_rx_timestamp(priv->cpts, skb); 748df828598SMugunthan V N skb->protocol = eth_type_trans(skb, ndev); 749df828598SMugunthan V N netif_receive_skb(skb); 7508dc43ddcSTobias Klauser ndev->stats.rx_bytes += len; 7518dc43ddcSTobias Klauser ndev->stats.rx_packets++; 752b4727e69SSebastian Siewior } else { 7538dc43ddcSTobias Klauser ndev->stats.rx_dropped++; 754b4727e69SSebastian Siewior new_skb = skb; 755df828598SMugunthan V N } 756df828598SMugunthan V N 757a0e2c822SMugunthan V N requeue: 758b4727e69SSebastian Siewior ret = cpdma_chan_submit(priv->rxch, new_skb, new_skb->data, 759b4727e69SSebastian Siewior skb_tailroom(new_skb), 0); 760b4727e69SSebastian Siewior if (WARN_ON(ret < 0)) 761b4727e69SSebastian Siewior dev_kfree_skb_any(new_skb); 762df828598SMugunthan V N } 763df828598SMugunthan V N 764c03abd84SFelipe Balbi static irqreturn_t cpsw_tx_interrupt(int irq, void *dev_id) 765df828598SMugunthan V N { 766df828598SMugunthan V N struct cpsw_priv *priv = dev_id; 7677ce67a38SFelipe Balbi 768c03abd84SFelipe Balbi cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_TX); 769c03abd84SFelipe Balbi cpdma_chan_process(priv->txch, 128); 770c03abd84SFelipe Balbi 771c03abd84SFelipe Balbi priv = cpsw_get_slave_priv(priv, 1); 772c03abd84SFelipe Balbi if (priv) 773c03abd84SFelipe Balbi cpdma_chan_process(priv->txch, 128); 774c03abd84SFelipe Balbi 775c03abd84SFelipe Balbi return IRQ_HANDLED; 776c03abd84SFelipe Balbi } 777c03abd84SFelipe Balbi 778c03abd84SFelipe Balbi static irqreturn_t cpsw_rx_interrupt(int irq, void *dev_id) 779c03abd84SFelipe Balbi { 780c03abd84SFelipe Balbi struct cpsw_priv *priv = dev_id; 781c03abd84SFelipe Balbi 782c03abd84SFelipe Balbi cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_RX); 783fd51cf19SSebastian Siewior 784df828598SMugunthan V N cpsw_intr_disable(priv); 785a11fbba9SSebastian Siewior if (priv->irq_enabled == true) { 786df828598SMugunthan V N cpsw_disable_irq(priv); 787a11fbba9SSebastian Siewior priv->irq_enabled = false; 788a11fbba9SSebastian Siewior } 789fd51cf19SSebastian Siewior 790fd51cf19SSebastian Siewior if (netif_running(priv->ndev)) { 791df828598SMugunthan V N napi_schedule(&priv->napi); 792df828598SMugunthan V N return IRQ_HANDLED; 793df828598SMugunthan V N } 794df828598SMugunthan V N 795fd51cf19SSebastian Siewior priv = cpsw_get_slave_priv(priv, 1); 796fd51cf19SSebastian Siewior if (!priv) 797fd51cf19SSebastian Siewior return IRQ_NONE; 798fd51cf19SSebastian Siewior 799fd51cf19SSebastian Siewior if (netif_running(priv->ndev)) { 800fd51cf19SSebastian Siewior napi_schedule(&priv->napi); 801fd51cf19SSebastian Siewior return IRQ_HANDLED; 802fd51cf19SSebastian Siewior } 803fd51cf19SSebastian Siewior return IRQ_NONE; 804fd51cf19SSebastian Siewior } 805fd51cf19SSebastian Siewior 806df828598SMugunthan V N static int cpsw_poll(struct napi_struct *napi, int budget) 807df828598SMugunthan V N { 808df828598SMugunthan V N struct cpsw_priv *priv = napi_to_priv(napi); 809df828598SMugunthan V N int num_tx, num_rx; 810df828598SMugunthan V N 811df828598SMugunthan V N num_tx = cpdma_chan_process(priv->txch, 128); 812510a1e72SMugunthan V N 813df828598SMugunthan V N num_rx = cpdma_chan_process(priv->rxch, budget); 814510a1e72SMugunthan V N if (num_rx < budget) { 815a11fbba9SSebastian Siewior struct cpsw_priv *prim_cpsw; 816a11fbba9SSebastian Siewior 817510a1e72SMugunthan V N napi_complete(napi); 818510a1e72SMugunthan V N cpsw_intr_enable(priv); 819a11fbba9SSebastian Siewior prim_cpsw = cpsw_get_slave_priv(priv, 0); 820a11fbba9SSebastian Siewior if (prim_cpsw->irq_enabled == false) { 821a11fbba9SSebastian Siewior prim_cpsw->irq_enabled = true; 822af5c6df7SMugunthan V N cpsw_enable_irq(priv); 823a11fbba9SSebastian Siewior } 824510a1e72SMugunthan V N } 825df828598SMugunthan V N 826df828598SMugunthan V N if (num_rx || num_tx) 827df828598SMugunthan V N cpsw_dbg(priv, intr, "poll %d rx, %d tx pkts\n", 828df828598SMugunthan V N num_rx, num_tx); 829df828598SMugunthan V N 830df828598SMugunthan V N return num_rx; 831df828598SMugunthan V N } 832df828598SMugunthan V N 833df828598SMugunthan V N static inline void soft_reset(const char *module, void __iomem *reg) 834df828598SMugunthan V N { 835df828598SMugunthan V N unsigned long timeout = jiffies + HZ; 836df828598SMugunthan V N 837df828598SMugunthan V N __raw_writel(1, reg); 838df828598SMugunthan V N do { 839df828598SMugunthan V N cpu_relax(); 840df828598SMugunthan V N } while ((__raw_readl(reg) & 1) && time_after(timeout, jiffies)); 841df828598SMugunthan V N 842df828598SMugunthan V N WARN(__raw_readl(reg) & 1, "failed to soft-reset %s\n", module); 843df828598SMugunthan V N } 844df828598SMugunthan V N 845df828598SMugunthan V N #define mac_hi(mac) (((mac)[0] << 0) | ((mac)[1] << 8) | \ 846df828598SMugunthan V N ((mac)[2] << 16) | ((mac)[3] << 24)) 847df828598SMugunthan V N #define mac_lo(mac) (((mac)[4] << 0) | ((mac)[5] << 8)) 848df828598SMugunthan V N 849df828598SMugunthan V N static void cpsw_set_slave_mac(struct cpsw_slave *slave, 850df828598SMugunthan V N struct cpsw_priv *priv) 851df828598SMugunthan V N { 8529750a3adSRichard Cochran slave_write(slave, mac_hi(priv->mac_addr), SA_HI); 8539750a3adSRichard Cochran slave_write(slave, mac_lo(priv->mac_addr), SA_LO); 854df828598SMugunthan V N } 855df828598SMugunthan V N 856df828598SMugunthan V N static void _cpsw_adjust_link(struct cpsw_slave *slave, 857df828598SMugunthan V N struct cpsw_priv *priv, bool *link) 858df828598SMugunthan V N { 859df828598SMugunthan V N struct phy_device *phy = slave->phy; 860df828598SMugunthan V N u32 mac_control = 0; 861df828598SMugunthan V N u32 slave_port; 862df828598SMugunthan V N 863df828598SMugunthan V N if (!phy) 864df828598SMugunthan V N return; 865df828598SMugunthan V N 866df828598SMugunthan V N slave_port = cpsw_get_slave_port(priv, slave->slave_num); 867df828598SMugunthan V N 868df828598SMugunthan V N if (phy->link) { 869df828598SMugunthan V N mac_control = priv->data.mac_control; 870df828598SMugunthan V N 871df828598SMugunthan V N /* enable forwarding */ 872df828598SMugunthan V N cpsw_ale_control_set(priv->ale, slave_port, 873df828598SMugunthan V N ALE_PORT_STATE, ALE_PORT_STATE_FORWARD); 874df828598SMugunthan V N 875df828598SMugunthan V N if (phy->speed == 1000) 876df828598SMugunthan V N mac_control |= BIT(7); /* GIGABITEN */ 877df828598SMugunthan V N if (phy->duplex) 878df828598SMugunthan V N mac_control |= BIT(0); /* FULLDUPLEXEN */ 879342b7b74SDaniel Mack 880342b7b74SDaniel Mack /* set speed_in input in case RMII mode is used in 100Mbps */ 881342b7b74SDaniel Mack if (phy->speed == 100) 882342b7b74SDaniel Mack mac_control |= BIT(15); 883a81d8762SMugunthan V N else if (phy->speed == 10) 884a81d8762SMugunthan V N mac_control |= BIT(18); /* In Band mode */ 885342b7b74SDaniel Mack 8861923d6e4SMugunthan V N if (priv->rx_pause) 8871923d6e4SMugunthan V N mac_control |= BIT(3); 8881923d6e4SMugunthan V N 8891923d6e4SMugunthan V N if (priv->tx_pause) 8901923d6e4SMugunthan V N mac_control |= BIT(4); 8911923d6e4SMugunthan V N 892df828598SMugunthan V N *link = true; 893df828598SMugunthan V N } else { 894df828598SMugunthan V N mac_control = 0; 895df828598SMugunthan V N /* disable forwarding */ 896df828598SMugunthan V N cpsw_ale_control_set(priv->ale, slave_port, 897df828598SMugunthan V N ALE_PORT_STATE, ALE_PORT_STATE_DISABLE); 898df828598SMugunthan V N } 899df828598SMugunthan V N 900df828598SMugunthan V N if (mac_control != slave->mac_control) { 901df828598SMugunthan V N phy_print_status(phy); 902df828598SMugunthan V N __raw_writel(mac_control, &slave->sliver->mac_control); 903df828598SMugunthan V N } 904df828598SMugunthan V N 905df828598SMugunthan V N slave->mac_control = mac_control; 906df828598SMugunthan V N } 907df828598SMugunthan V N 908df828598SMugunthan V N static void cpsw_adjust_link(struct net_device *ndev) 909df828598SMugunthan V N { 910df828598SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 911df828598SMugunthan V N bool link = false; 912df828598SMugunthan V N 913df828598SMugunthan V N for_each_slave(priv, _cpsw_adjust_link, priv, &link); 914df828598SMugunthan V N 915df828598SMugunthan V N if (link) { 916df828598SMugunthan V N netif_carrier_on(ndev); 917df828598SMugunthan V N if (netif_running(ndev)) 918df828598SMugunthan V N netif_wake_queue(ndev); 919df828598SMugunthan V N } else { 920df828598SMugunthan V N netif_carrier_off(ndev); 921df828598SMugunthan V N netif_stop_queue(ndev); 922df828598SMugunthan V N } 923df828598SMugunthan V N } 924df828598SMugunthan V N 925ff5b8ef2SMugunthan V N static int cpsw_get_coalesce(struct net_device *ndev, 926ff5b8ef2SMugunthan V N struct ethtool_coalesce *coal) 927ff5b8ef2SMugunthan V N { 928ff5b8ef2SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 929ff5b8ef2SMugunthan V N 930ff5b8ef2SMugunthan V N coal->rx_coalesce_usecs = priv->coal_intvl; 931ff5b8ef2SMugunthan V N return 0; 932ff5b8ef2SMugunthan V N } 933ff5b8ef2SMugunthan V N 934ff5b8ef2SMugunthan V N static int cpsw_set_coalesce(struct net_device *ndev, 935ff5b8ef2SMugunthan V N struct ethtool_coalesce *coal) 936ff5b8ef2SMugunthan V N { 937ff5b8ef2SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 938ff5b8ef2SMugunthan V N u32 int_ctrl; 939ff5b8ef2SMugunthan V N u32 num_interrupts = 0; 940ff5b8ef2SMugunthan V N u32 prescale = 0; 941ff5b8ef2SMugunthan V N u32 addnl_dvdr = 1; 942ff5b8ef2SMugunthan V N u32 coal_intvl = 0; 943ff5b8ef2SMugunthan V N 944ff5b8ef2SMugunthan V N coal_intvl = coal->rx_coalesce_usecs; 945ff5b8ef2SMugunthan V N 946ff5b8ef2SMugunthan V N int_ctrl = readl(&priv->wr_regs->int_control); 947ff5b8ef2SMugunthan V N prescale = priv->bus_freq_mhz * 4; 948ff5b8ef2SMugunthan V N 949a84bc2a9SMugunthan V N if (!coal->rx_coalesce_usecs) { 950a84bc2a9SMugunthan V N int_ctrl &= ~(CPSW_INTPRESCALE_MASK | CPSW_INTPACEEN); 951a84bc2a9SMugunthan V N goto update_return; 952a84bc2a9SMugunthan V N } 953a84bc2a9SMugunthan V N 954ff5b8ef2SMugunthan V N if (coal_intvl < CPSW_CMINTMIN_INTVL) 955ff5b8ef2SMugunthan V N coal_intvl = CPSW_CMINTMIN_INTVL; 956ff5b8ef2SMugunthan V N 957ff5b8ef2SMugunthan V N if (coal_intvl > CPSW_CMINTMAX_INTVL) { 958ff5b8ef2SMugunthan V N /* Interrupt pacer works with 4us Pulse, we can 959ff5b8ef2SMugunthan V N * throttle further by dilating the 4us pulse. 960ff5b8ef2SMugunthan V N */ 961ff5b8ef2SMugunthan V N addnl_dvdr = CPSW_INTPRESCALE_MASK / prescale; 962ff5b8ef2SMugunthan V N 963ff5b8ef2SMugunthan V N if (addnl_dvdr > 1) { 964ff5b8ef2SMugunthan V N prescale *= addnl_dvdr; 965ff5b8ef2SMugunthan V N if (coal_intvl > (CPSW_CMINTMAX_INTVL * addnl_dvdr)) 966ff5b8ef2SMugunthan V N coal_intvl = (CPSW_CMINTMAX_INTVL 967ff5b8ef2SMugunthan V N * addnl_dvdr); 968ff5b8ef2SMugunthan V N } else { 969ff5b8ef2SMugunthan V N addnl_dvdr = 1; 970ff5b8ef2SMugunthan V N coal_intvl = CPSW_CMINTMAX_INTVL; 971ff5b8ef2SMugunthan V N } 972ff5b8ef2SMugunthan V N } 973ff5b8ef2SMugunthan V N 974ff5b8ef2SMugunthan V N num_interrupts = (1000 * addnl_dvdr) / coal_intvl; 975ff5b8ef2SMugunthan V N writel(num_interrupts, &priv->wr_regs->rx_imax); 976ff5b8ef2SMugunthan V N writel(num_interrupts, &priv->wr_regs->tx_imax); 977ff5b8ef2SMugunthan V N 978ff5b8ef2SMugunthan V N int_ctrl |= CPSW_INTPACEEN; 979ff5b8ef2SMugunthan V N int_ctrl &= (~CPSW_INTPRESCALE_MASK); 980ff5b8ef2SMugunthan V N int_ctrl |= (prescale & CPSW_INTPRESCALE_MASK); 981a84bc2a9SMugunthan V N 982a84bc2a9SMugunthan V N update_return: 983ff5b8ef2SMugunthan V N writel(int_ctrl, &priv->wr_regs->int_control); 984ff5b8ef2SMugunthan V N 985ff5b8ef2SMugunthan V N cpsw_notice(priv, timer, "Set coalesce to %d usecs.\n", coal_intvl); 986ff5b8ef2SMugunthan V N if (priv->data.dual_emac) { 987ff5b8ef2SMugunthan V N int i; 988ff5b8ef2SMugunthan V N 989ff5b8ef2SMugunthan V N for (i = 0; i < priv->data.slaves; i++) { 990ff5b8ef2SMugunthan V N priv = netdev_priv(priv->slaves[i].ndev); 991ff5b8ef2SMugunthan V N priv->coal_intvl = coal_intvl; 992ff5b8ef2SMugunthan V N } 993ff5b8ef2SMugunthan V N } else { 994ff5b8ef2SMugunthan V N priv->coal_intvl = coal_intvl; 995ff5b8ef2SMugunthan V N } 996ff5b8ef2SMugunthan V N 997ff5b8ef2SMugunthan V N return 0; 998ff5b8ef2SMugunthan V N } 999ff5b8ef2SMugunthan V N 1000d9718546SMugunthan V N static int cpsw_get_sset_count(struct net_device *ndev, int sset) 1001d9718546SMugunthan V N { 1002d9718546SMugunthan V N switch (sset) { 1003d9718546SMugunthan V N case ETH_SS_STATS: 1004d9718546SMugunthan V N return CPSW_STATS_LEN; 1005d9718546SMugunthan V N default: 1006d9718546SMugunthan V N return -EOPNOTSUPP; 1007d9718546SMugunthan V N } 1008d9718546SMugunthan V N } 1009d9718546SMugunthan V N 1010d9718546SMugunthan V N static void cpsw_get_strings(struct net_device *ndev, u32 stringset, u8 *data) 1011d9718546SMugunthan V N { 1012d9718546SMugunthan V N u8 *p = data; 1013d9718546SMugunthan V N int i; 1014d9718546SMugunthan V N 1015d9718546SMugunthan V N switch (stringset) { 1016d9718546SMugunthan V N case ETH_SS_STATS: 1017d9718546SMugunthan V N for (i = 0; i < CPSW_STATS_LEN; i++) { 1018d9718546SMugunthan V N memcpy(p, cpsw_gstrings_stats[i].stat_string, 1019d9718546SMugunthan V N ETH_GSTRING_LEN); 1020d9718546SMugunthan V N p += ETH_GSTRING_LEN; 1021d9718546SMugunthan V N } 1022d9718546SMugunthan V N break; 1023d9718546SMugunthan V N } 1024d9718546SMugunthan V N } 1025d9718546SMugunthan V N 1026d9718546SMugunthan V N static void cpsw_get_ethtool_stats(struct net_device *ndev, 1027d9718546SMugunthan V N struct ethtool_stats *stats, u64 *data) 1028d9718546SMugunthan V N { 1029d9718546SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 1030d9718546SMugunthan V N struct cpdma_chan_stats rx_stats; 1031d9718546SMugunthan V N struct cpdma_chan_stats tx_stats; 1032d9718546SMugunthan V N u32 val; 1033d9718546SMugunthan V N u8 *p; 1034d9718546SMugunthan V N int i; 1035d9718546SMugunthan V N 1036d9718546SMugunthan V N /* Collect Davinci CPDMA stats for Rx and Tx Channel */ 1037d9718546SMugunthan V N cpdma_chan_get_stats(priv->rxch, &rx_stats); 1038d9718546SMugunthan V N cpdma_chan_get_stats(priv->txch, &tx_stats); 1039d9718546SMugunthan V N 1040d9718546SMugunthan V N for (i = 0; i < CPSW_STATS_LEN; i++) { 1041d9718546SMugunthan V N switch (cpsw_gstrings_stats[i].type) { 1042d9718546SMugunthan V N case CPSW_STATS: 1043d9718546SMugunthan V N val = readl(priv->hw_stats + 1044d9718546SMugunthan V N cpsw_gstrings_stats[i].stat_offset); 1045d9718546SMugunthan V N data[i] = val; 1046d9718546SMugunthan V N break; 1047d9718546SMugunthan V N 1048d9718546SMugunthan V N case CPDMA_RX_STATS: 1049d9718546SMugunthan V N p = (u8 *)&rx_stats + 1050d9718546SMugunthan V N cpsw_gstrings_stats[i].stat_offset; 1051d9718546SMugunthan V N data[i] = *(u32 *)p; 1052d9718546SMugunthan V N break; 1053d9718546SMugunthan V N 1054d9718546SMugunthan V N case CPDMA_TX_STATS: 1055d9718546SMugunthan V N p = (u8 *)&tx_stats + 1056d9718546SMugunthan V N cpsw_gstrings_stats[i].stat_offset; 1057d9718546SMugunthan V N data[i] = *(u32 *)p; 1058d9718546SMugunthan V N break; 1059d9718546SMugunthan V N } 1060d9718546SMugunthan V N } 1061d9718546SMugunthan V N } 1062d9718546SMugunthan V N 1063d9ba8f9eSMugunthan V N static int cpsw_common_res_usage_state(struct cpsw_priv *priv) 1064d9ba8f9eSMugunthan V N { 1065d9ba8f9eSMugunthan V N u32 i; 1066d9ba8f9eSMugunthan V N u32 usage_count = 0; 1067d9ba8f9eSMugunthan V N 1068d9ba8f9eSMugunthan V N if (!priv->data.dual_emac) 1069d9ba8f9eSMugunthan V N return 0; 1070d9ba8f9eSMugunthan V N 1071d9ba8f9eSMugunthan V N for (i = 0; i < priv->data.slaves; i++) 1072d9ba8f9eSMugunthan V N if (priv->slaves[i].open_stat) 1073d9ba8f9eSMugunthan V N usage_count++; 1074d9ba8f9eSMugunthan V N 1075d9ba8f9eSMugunthan V N return usage_count; 1076d9ba8f9eSMugunthan V N } 1077d9ba8f9eSMugunthan V N 1078d9ba8f9eSMugunthan V N static inline int cpsw_tx_packet_submit(struct net_device *ndev, 1079d9ba8f9eSMugunthan V N struct cpsw_priv *priv, struct sk_buff *skb) 1080d9ba8f9eSMugunthan V N { 1081d9ba8f9eSMugunthan V N if (!priv->data.dual_emac) 1082d9ba8f9eSMugunthan V N return cpdma_chan_submit(priv->txch, skb, skb->data, 1083aef614e1SSebastian Siewior skb->len, 0); 1084d9ba8f9eSMugunthan V N 1085d9ba8f9eSMugunthan V N if (ndev == cpsw_get_slave_ndev(priv, 0)) 1086d9ba8f9eSMugunthan V N return cpdma_chan_submit(priv->txch, skb, skb->data, 1087aef614e1SSebastian Siewior skb->len, 1); 1088d9ba8f9eSMugunthan V N else 1089d9ba8f9eSMugunthan V N return cpdma_chan_submit(priv->txch, skb, skb->data, 1090aef614e1SSebastian Siewior skb->len, 2); 1091d9ba8f9eSMugunthan V N } 1092d9ba8f9eSMugunthan V N 1093d9ba8f9eSMugunthan V N static inline void cpsw_add_dual_emac_def_ale_entries( 1094d9ba8f9eSMugunthan V N struct cpsw_priv *priv, struct cpsw_slave *slave, 1095d9ba8f9eSMugunthan V N u32 slave_port) 1096d9ba8f9eSMugunthan V N { 1097d9ba8f9eSMugunthan V N u32 port_mask = 1 << slave_port | 1 << priv->host_port; 1098d9ba8f9eSMugunthan V N 1099d9ba8f9eSMugunthan V N if (priv->version == CPSW_VERSION_1) 1100d9ba8f9eSMugunthan V N slave_write(slave, slave->port_vlan, CPSW1_PORT_VLAN); 1101d9ba8f9eSMugunthan V N else 1102d9ba8f9eSMugunthan V N slave_write(slave, slave->port_vlan, CPSW2_PORT_VLAN); 1103d9ba8f9eSMugunthan V N cpsw_ale_add_vlan(priv->ale, slave->port_vlan, port_mask, 1104d9ba8f9eSMugunthan V N port_mask, port_mask, 0); 1105d9ba8f9eSMugunthan V N cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast, 1106d9ba8f9eSMugunthan V N port_mask, ALE_VLAN, slave->port_vlan, 0); 1107d9ba8f9eSMugunthan V N cpsw_ale_add_ucast(priv->ale, priv->mac_addr, 110856887149SGeorge McCollister priv->host_port, ALE_VLAN | ALE_SECURE, slave->port_vlan); 1109d9ba8f9eSMugunthan V N } 1110d9ba8f9eSMugunthan V N 11111e7a2e21SDaniel Mack static void soft_reset_slave(struct cpsw_slave *slave) 1112df828598SMugunthan V N { 1113df828598SMugunthan V N char name[32]; 11141e7a2e21SDaniel Mack 11151e7a2e21SDaniel Mack snprintf(name, sizeof(name), "slave-%d", slave->slave_num); 11161e7a2e21SDaniel Mack soft_reset(name, &slave->sliver->soft_reset); 11171e7a2e21SDaniel Mack } 11181e7a2e21SDaniel Mack 11191e7a2e21SDaniel Mack static void cpsw_slave_open(struct cpsw_slave *slave, struct cpsw_priv *priv) 11201e7a2e21SDaniel Mack { 1121df828598SMugunthan V N u32 slave_port; 1122df828598SMugunthan V N 11231e7a2e21SDaniel Mack soft_reset_slave(slave); 1124df828598SMugunthan V N 1125df828598SMugunthan V N /* setup priority mapping */ 1126df828598SMugunthan V N __raw_writel(RX_PRIORITY_MAPPING, &slave->sliver->rx_pri_map); 11279750a3adSRichard Cochran 11289750a3adSRichard Cochran switch (priv->version) { 11299750a3adSRichard Cochran case CPSW_VERSION_1: 11309750a3adSRichard Cochran slave_write(slave, TX_PRIORITY_MAPPING, CPSW1_TX_PRI_MAP); 11319750a3adSRichard Cochran break; 11329750a3adSRichard Cochran case CPSW_VERSION_2: 1133c193f365SMugunthan V N case CPSW_VERSION_3: 1134926489beSMugunthan V N case CPSW_VERSION_4: 11359750a3adSRichard Cochran slave_write(slave, TX_PRIORITY_MAPPING, CPSW2_TX_PRI_MAP); 11369750a3adSRichard Cochran break; 11379750a3adSRichard Cochran } 1138df828598SMugunthan V N 1139df828598SMugunthan V N /* setup max packet size, and mac address */ 1140df828598SMugunthan V N __raw_writel(priv->rx_packet_max, &slave->sliver->rx_maxlen); 1141df828598SMugunthan V N cpsw_set_slave_mac(slave, priv); 1142df828598SMugunthan V N 1143df828598SMugunthan V N slave->mac_control = 0; /* no link yet */ 1144df828598SMugunthan V N 1145df828598SMugunthan V N slave_port = cpsw_get_slave_port(priv, slave->slave_num); 1146df828598SMugunthan V N 1147d9ba8f9eSMugunthan V N if (priv->data.dual_emac) 1148d9ba8f9eSMugunthan V N cpsw_add_dual_emac_def_ale_entries(priv, slave, slave_port); 1149d9ba8f9eSMugunthan V N else 1150df828598SMugunthan V N cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast, 1151e11b220fSMugunthan V N 1 << slave_port, 0, 0, ALE_MCAST_FWD_2); 1152df828598SMugunthan V N 1153df828598SMugunthan V N slave->phy = phy_connect(priv->ndev, slave->data->phy_id, 1154f9a8f83bSFlorian Fainelli &cpsw_adjust_link, slave->data->phy_if); 1155df828598SMugunthan V N if (IS_ERR(slave->phy)) { 1156df828598SMugunthan V N dev_err(priv->dev, "phy %s not found on slave %d\n", 1157df828598SMugunthan V N slave->data->phy_id, slave->slave_num); 1158df828598SMugunthan V N slave->phy = NULL; 1159df828598SMugunthan V N } else { 1160df828598SMugunthan V N dev_info(priv->dev, "phy found : id is : 0x%x\n", 1161df828598SMugunthan V N slave->phy->phy_id); 1162df828598SMugunthan V N phy_start(slave->phy); 1163388367a5SMugunthan V N 1164388367a5SMugunthan V N /* Configure GMII_SEL register */ 1165388367a5SMugunthan V N cpsw_phy_sel(&priv->pdev->dev, slave->phy->interface, 1166388367a5SMugunthan V N slave->slave_num); 1167df828598SMugunthan V N } 1168df828598SMugunthan V N } 1169df828598SMugunthan V N 11703b72c2feSMugunthan V N static inline void cpsw_add_default_vlan(struct cpsw_priv *priv) 11713b72c2feSMugunthan V N { 11723b72c2feSMugunthan V N const int vlan = priv->data.default_vlan; 11733b72c2feSMugunthan V N const int port = priv->host_port; 11743b72c2feSMugunthan V N u32 reg; 11753b72c2feSMugunthan V N int i; 11761e5c4bc4SLennart Sorensen int unreg_mcast_mask; 11773b72c2feSMugunthan V N 11783b72c2feSMugunthan V N reg = (priv->version == CPSW_VERSION_1) ? CPSW1_PORT_VLAN : 11793b72c2feSMugunthan V N CPSW2_PORT_VLAN; 11803b72c2feSMugunthan V N 11813b72c2feSMugunthan V N writel(vlan, &priv->host_port_regs->port_vlan); 11823b72c2feSMugunthan V N 11830237c110SDaniel Mack for (i = 0; i < priv->data.slaves; i++) 11843b72c2feSMugunthan V N slave_write(priv->slaves + i, vlan, reg); 11853b72c2feSMugunthan V N 11861e5c4bc4SLennart Sorensen if (priv->ndev->flags & IFF_ALLMULTI) 11871e5c4bc4SLennart Sorensen unreg_mcast_mask = ALE_ALL_PORTS; 11881e5c4bc4SLennart Sorensen else 11891e5c4bc4SLennart Sorensen unreg_mcast_mask = ALE_PORT_1 | ALE_PORT_2; 11901e5c4bc4SLennart Sorensen 11913b72c2feSMugunthan V N cpsw_ale_add_vlan(priv->ale, vlan, ALE_ALL_PORTS << port, 11923b72c2feSMugunthan V N ALE_ALL_PORTS << port, ALE_ALL_PORTS << port, 11931e5c4bc4SLennart Sorensen unreg_mcast_mask << port); 11943b72c2feSMugunthan V N } 11953b72c2feSMugunthan V N 1196df828598SMugunthan V N static void cpsw_init_host_port(struct cpsw_priv *priv) 1197df828598SMugunthan V N { 11983b72c2feSMugunthan V N u32 control_reg; 1199d9ba8f9eSMugunthan V N u32 fifo_mode; 12003b72c2feSMugunthan V N 1201df828598SMugunthan V N /* soft reset the controller and initialize ale */ 1202df828598SMugunthan V N soft_reset("cpsw", &priv->regs->soft_reset); 1203df828598SMugunthan V N cpsw_ale_start(priv->ale); 1204df828598SMugunthan V N 1205df828598SMugunthan V N /* switch to vlan unaware mode */ 12063b72c2feSMugunthan V N cpsw_ale_control_set(priv->ale, priv->host_port, ALE_VLAN_AWARE, 12073b72c2feSMugunthan V N CPSW_ALE_VLAN_AWARE); 12083b72c2feSMugunthan V N control_reg = readl(&priv->regs->control); 12093b72c2feSMugunthan V N control_reg |= CPSW_VLAN_AWARE; 12103b72c2feSMugunthan V N writel(control_reg, &priv->regs->control); 1211d9ba8f9eSMugunthan V N fifo_mode = (priv->data.dual_emac) ? CPSW_FIFO_DUAL_MAC_MODE : 1212d9ba8f9eSMugunthan V N CPSW_FIFO_NORMAL_MODE; 1213d9ba8f9eSMugunthan V N writel(fifo_mode, &priv->host_port_regs->tx_in_ctl); 1214df828598SMugunthan V N 1215df828598SMugunthan V N /* setup host port priority mapping */ 1216df828598SMugunthan V N __raw_writel(CPDMA_TX_PRIORITY_MAP, 1217df828598SMugunthan V N &priv->host_port_regs->cpdma_tx_pri_map); 1218df828598SMugunthan V N __raw_writel(0, &priv->host_port_regs->cpdma_rx_chan_map); 1219df828598SMugunthan V N 1220df828598SMugunthan V N cpsw_ale_control_set(priv->ale, priv->host_port, 1221df828598SMugunthan V N ALE_PORT_STATE, ALE_PORT_STATE_FORWARD); 1222df828598SMugunthan V N 1223d9ba8f9eSMugunthan V N if (!priv->data.dual_emac) { 1224d9ba8f9eSMugunthan V N cpsw_ale_add_ucast(priv->ale, priv->mac_addr, priv->host_port, 1225d9ba8f9eSMugunthan V N 0, 0); 1226df828598SMugunthan V N cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast, 1227e11b220fSMugunthan V N 1 << priv->host_port, 0, 0, ALE_MCAST_FWD_2); 1228df828598SMugunthan V N } 1229d9ba8f9eSMugunthan V N } 1230df828598SMugunthan V N 1231aacebbf8SSebastian Siewior static void cpsw_slave_stop(struct cpsw_slave *slave, struct cpsw_priv *priv) 1232aacebbf8SSebastian Siewior { 12333995d265SSchuyler Patton u32 slave_port; 12343995d265SSchuyler Patton 12353995d265SSchuyler Patton slave_port = cpsw_get_slave_port(priv, slave->slave_num); 12363995d265SSchuyler Patton 1237aacebbf8SSebastian Siewior if (!slave->phy) 1238aacebbf8SSebastian Siewior return; 1239aacebbf8SSebastian Siewior phy_stop(slave->phy); 1240aacebbf8SSebastian Siewior phy_disconnect(slave->phy); 1241aacebbf8SSebastian Siewior slave->phy = NULL; 12423995d265SSchuyler Patton cpsw_ale_control_set(priv->ale, slave_port, 12433995d265SSchuyler Patton ALE_PORT_STATE, ALE_PORT_STATE_DISABLE); 1244aacebbf8SSebastian Siewior } 1245aacebbf8SSebastian Siewior 1246df828598SMugunthan V N static int cpsw_ndo_open(struct net_device *ndev) 1247df828598SMugunthan V N { 1248df828598SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 1249a11fbba9SSebastian Siewior struct cpsw_priv *prim_cpsw; 1250df828598SMugunthan V N int i, ret; 1251df828598SMugunthan V N u32 reg; 1252df828598SMugunthan V N 1253d9ba8f9eSMugunthan V N if (!cpsw_common_res_usage_state(priv)) 1254df828598SMugunthan V N cpsw_intr_disable(priv); 1255df828598SMugunthan V N netif_carrier_off(ndev); 1256df828598SMugunthan V N 1257f150bd7fSMugunthan V N pm_runtime_get_sync(&priv->pdev->dev); 1258df828598SMugunthan V N 1259549985eeSRichard Cochran reg = priv->version; 1260df828598SMugunthan V N 1261df828598SMugunthan V N dev_info(priv->dev, "initializing cpsw version %d.%d (%d)\n", 1262df828598SMugunthan V N CPSW_MAJOR_VERSION(reg), CPSW_MINOR_VERSION(reg), 1263df828598SMugunthan V N CPSW_RTL_VERSION(reg)); 1264df828598SMugunthan V N 1265df828598SMugunthan V N /* initialize host and slave ports */ 1266d9ba8f9eSMugunthan V N if (!cpsw_common_res_usage_state(priv)) 1267df828598SMugunthan V N cpsw_init_host_port(priv); 1268df828598SMugunthan V N for_each_slave(priv, cpsw_slave_open, priv); 1269df828598SMugunthan V N 12703b72c2feSMugunthan V N /* Add default VLAN */ 1271e6afea0bSMugunthan V N if (!priv->data.dual_emac) 12723b72c2feSMugunthan V N cpsw_add_default_vlan(priv); 1273e6afea0bSMugunthan V N else 1274e6afea0bSMugunthan V N cpsw_ale_add_vlan(priv->ale, priv->data.default_vlan, 1275e6afea0bSMugunthan V N ALE_ALL_PORTS << priv->host_port, 1276e6afea0bSMugunthan V N ALE_ALL_PORTS << priv->host_port, 0, 0); 12773b72c2feSMugunthan V N 1278d9ba8f9eSMugunthan V N if (!cpsw_common_res_usage_state(priv)) { 1279df828598SMugunthan V N /* setup tx dma to fixed prio and zero offset */ 1280df828598SMugunthan V N cpdma_control_set(priv->dma, CPDMA_TX_PRIO_FIXED, 1); 1281df828598SMugunthan V N cpdma_control_set(priv->dma, CPDMA_RX_BUFFER_OFFSET, 0); 1282df828598SMugunthan V N 1283d9ba8f9eSMugunthan V N /* disable priority elevation */ 1284df828598SMugunthan V N __raw_writel(0, &priv->regs->ptype); 1285df828598SMugunthan V N 1286d9ba8f9eSMugunthan V N /* enable statistics collection only on all ports */ 1287df828598SMugunthan V N __raw_writel(0x7, &priv->regs->stat_port_en); 1288df828598SMugunthan V N 12891923d6e4SMugunthan V N /* Enable internal fifo flow control */ 12901923d6e4SMugunthan V N writel(0x7, &priv->regs->flow_control); 12911923d6e4SMugunthan V N 1292df828598SMugunthan V N if (WARN_ON(!priv->data.rx_descs)) 1293df828598SMugunthan V N priv->data.rx_descs = 128; 1294df828598SMugunthan V N 1295df828598SMugunthan V N for (i = 0; i < priv->data.rx_descs; i++) { 1296df828598SMugunthan V N struct sk_buff *skb; 1297df828598SMugunthan V N 1298df828598SMugunthan V N ret = -ENOMEM; 1299aacebbf8SSebastian Siewior skb = __netdev_alloc_skb_ip_align(priv->ndev, 1300aacebbf8SSebastian Siewior priv->rx_packet_max, GFP_KERNEL); 1301df828598SMugunthan V N if (!skb) 1302aacebbf8SSebastian Siewior goto err_cleanup; 1303df828598SMugunthan V N ret = cpdma_chan_submit(priv->rxch, skb, skb->data, 1304aef614e1SSebastian Siewior skb_tailroom(skb), 0); 1305aacebbf8SSebastian Siewior if (ret < 0) { 1306aacebbf8SSebastian Siewior kfree_skb(skb); 1307aacebbf8SSebastian Siewior goto err_cleanup; 1308aacebbf8SSebastian Siewior } 1309df828598SMugunthan V N } 1310d9ba8f9eSMugunthan V N /* continue even if we didn't manage to submit all 1311d9ba8f9eSMugunthan V N * receive descs 1312d9ba8f9eSMugunthan V N */ 1313df828598SMugunthan V N cpsw_info(priv, ifup, "submitted %d rx descriptors\n", i); 1314f280e89aSMugunthan V N 1315f280e89aSMugunthan V N if (cpts_register(&priv->pdev->dev, priv->cpts, 1316f280e89aSMugunthan V N priv->data.cpts_clock_mult, 1317f280e89aSMugunthan V N priv->data.cpts_clock_shift)) 1318f280e89aSMugunthan V N dev_err(priv->dev, "error registering cpts device\n"); 1319f280e89aSMugunthan V N 1320d9ba8f9eSMugunthan V N } 1321df828598SMugunthan V N 1322ff5b8ef2SMugunthan V N /* Enable Interrupt pacing if configured */ 1323ff5b8ef2SMugunthan V N if (priv->coal_intvl != 0) { 1324ff5b8ef2SMugunthan V N struct ethtool_coalesce coal; 1325ff5b8ef2SMugunthan V N 1326ff5b8ef2SMugunthan V N coal.rx_coalesce_usecs = (priv->coal_intvl << 4); 1327ff5b8ef2SMugunthan V N cpsw_set_coalesce(ndev, &coal); 1328ff5b8ef2SMugunthan V N } 1329ff5b8ef2SMugunthan V N 1330f63a975eSMugunthan V N napi_enable(&priv->napi); 1331f63a975eSMugunthan V N cpdma_ctlr_start(priv->dma); 1332f63a975eSMugunthan V N cpsw_intr_enable(priv); 1333f63a975eSMugunthan V N 1334a11fbba9SSebastian Siewior prim_cpsw = cpsw_get_slave_priv(priv, 0); 1335a11fbba9SSebastian Siewior if (prim_cpsw->irq_enabled == false) { 1336a11fbba9SSebastian Siewior if ((priv == prim_cpsw) || !netif_running(prim_cpsw->ndev)) { 1337a11fbba9SSebastian Siewior prim_cpsw->irq_enabled = true; 1338a11fbba9SSebastian Siewior cpsw_enable_irq(prim_cpsw); 1339a11fbba9SSebastian Siewior } 1340a11fbba9SSebastian Siewior } 1341a11fbba9SSebastian Siewior 1342d9ba8f9eSMugunthan V N if (priv->data.dual_emac) 1343d9ba8f9eSMugunthan V N priv->slaves[priv->emac_port].open_stat = true; 1344df828598SMugunthan V N return 0; 1345df828598SMugunthan V N 1346aacebbf8SSebastian Siewior err_cleanup: 1347aacebbf8SSebastian Siewior cpdma_ctlr_stop(priv->dma); 1348aacebbf8SSebastian Siewior for_each_slave(priv, cpsw_slave_stop, priv); 1349aacebbf8SSebastian Siewior pm_runtime_put_sync(&priv->pdev->dev); 1350aacebbf8SSebastian Siewior netif_carrier_off(priv->ndev); 1351aacebbf8SSebastian Siewior return ret; 1352df828598SMugunthan V N } 1353df828598SMugunthan V N 1354df828598SMugunthan V N static int cpsw_ndo_stop(struct net_device *ndev) 1355df828598SMugunthan V N { 1356df828598SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 1357df828598SMugunthan V N 1358df828598SMugunthan V N cpsw_info(priv, ifdown, "shutting down cpsw device\n"); 1359df828598SMugunthan V N netif_stop_queue(priv->ndev); 1360df828598SMugunthan V N napi_disable(&priv->napi); 1361df828598SMugunthan V N netif_carrier_off(priv->ndev); 1362d9ba8f9eSMugunthan V N 1363d9ba8f9eSMugunthan V N if (cpsw_common_res_usage_state(priv) <= 1) { 1364f280e89aSMugunthan V N cpts_unregister(priv->cpts); 136571380f9bSMugunthan V N cpsw_intr_disable(priv); 136671380f9bSMugunthan V N cpdma_ctlr_stop(priv->dma); 1367df828598SMugunthan V N cpsw_ale_stop(priv->ale); 1368d9ba8f9eSMugunthan V N } 1369df828598SMugunthan V N for_each_slave(priv, cpsw_slave_stop, priv); 1370f150bd7fSMugunthan V N pm_runtime_put_sync(&priv->pdev->dev); 1371d9ba8f9eSMugunthan V N if (priv->data.dual_emac) 1372d9ba8f9eSMugunthan V N priv->slaves[priv->emac_port].open_stat = false; 1373df828598SMugunthan V N return 0; 1374df828598SMugunthan V N } 1375df828598SMugunthan V N 1376df828598SMugunthan V N static netdev_tx_t cpsw_ndo_start_xmit(struct sk_buff *skb, 1377df828598SMugunthan V N struct net_device *ndev) 1378df828598SMugunthan V N { 1379df828598SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 1380df828598SMugunthan V N int ret; 1381df828598SMugunthan V N 1382df828598SMugunthan V N ndev->trans_start = jiffies; 1383df828598SMugunthan V N 1384df828598SMugunthan V N if (skb_padto(skb, CPSW_MIN_PACKET_SIZE)) { 1385df828598SMugunthan V N cpsw_err(priv, tx_err, "packet pad failed\n"); 13868dc43ddcSTobias Klauser ndev->stats.tx_dropped++; 1387df828598SMugunthan V N return NETDEV_TX_OK; 1388df828598SMugunthan V N } 1389df828598SMugunthan V N 13909232b16dSMugunthan V N if (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP && 13919232b16dSMugunthan V N priv->cpts->tx_enable) 13922e5b38abSRichard Cochran skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 13932e5b38abSRichard Cochran 13942e5b38abSRichard Cochran skb_tx_timestamp(skb); 13952e5b38abSRichard Cochran 1396d9ba8f9eSMugunthan V N ret = cpsw_tx_packet_submit(ndev, priv, skb); 1397df828598SMugunthan V N if (unlikely(ret != 0)) { 1398df828598SMugunthan V N cpsw_err(priv, tx_err, "desc submit failed\n"); 1399df828598SMugunthan V N goto fail; 1400df828598SMugunthan V N } 1401df828598SMugunthan V N 1402fae50823SMugunthan V N /* If there is no more tx desc left free then we need to 1403fae50823SMugunthan V N * tell the kernel to stop sending us tx frames. 1404fae50823SMugunthan V N */ 1405d35162f8SDaniel Mack if (unlikely(!cpdma_check_free_tx_desc(priv->txch))) 1406fae50823SMugunthan V N netif_stop_queue(ndev); 1407fae50823SMugunthan V N 1408df828598SMugunthan V N return NETDEV_TX_OK; 1409df828598SMugunthan V N fail: 14108dc43ddcSTobias Klauser ndev->stats.tx_dropped++; 1411df828598SMugunthan V N netif_stop_queue(ndev); 1412df828598SMugunthan V N return NETDEV_TX_BUSY; 1413df828598SMugunthan V N } 1414df828598SMugunthan V N 14152e5b38abSRichard Cochran #ifdef CONFIG_TI_CPTS 14162e5b38abSRichard Cochran 14172e5b38abSRichard Cochran static void cpsw_hwtstamp_v1(struct cpsw_priv *priv) 14182e5b38abSRichard Cochran { 1419e86ac13bSMugunthan V N struct cpsw_slave *slave = &priv->slaves[priv->data.active_slave]; 14202e5b38abSRichard Cochran u32 ts_en, seq_id; 14212e5b38abSRichard Cochran 14229232b16dSMugunthan V N if (!priv->cpts->tx_enable && !priv->cpts->rx_enable) { 14232e5b38abSRichard Cochran slave_write(slave, 0, CPSW1_TS_CTL); 14242e5b38abSRichard Cochran return; 14252e5b38abSRichard Cochran } 14262e5b38abSRichard Cochran 14272e5b38abSRichard Cochran seq_id = (30 << CPSW_V1_SEQ_ID_OFS_SHIFT) | ETH_P_1588; 14282e5b38abSRichard Cochran ts_en = EVENT_MSG_BITS << CPSW_V1_MSG_TYPE_OFS; 14292e5b38abSRichard Cochran 14309232b16dSMugunthan V N if (priv->cpts->tx_enable) 14312e5b38abSRichard Cochran ts_en |= CPSW_V1_TS_TX_EN; 14322e5b38abSRichard Cochran 14339232b16dSMugunthan V N if (priv->cpts->rx_enable) 14342e5b38abSRichard Cochran ts_en |= CPSW_V1_TS_RX_EN; 14352e5b38abSRichard Cochran 14362e5b38abSRichard Cochran slave_write(slave, ts_en, CPSW1_TS_CTL); 14372e5b38abSRichard Cochran slave_write(slave, seq_id, CPSW1_TS_SEQ_LTYPE); 14382e5b38abSRichard Cochran } 14392e5b38abSRichard Cochran 14402e5b38abSRichard Cochran static void cpsw_hwtstamp_v2(struct cpsw_priv *priv) 14412e5b38abSRichard Cochran { 1442d9ba8f9eSMugunthan V N struct cpsw_slave *slave; 14432e5b38abSRichard Cochran u32 ctrl, mtype; 14442e5b38abSRichard Cochran 1445d9ba8f9eSMugunthan V N if (priv->data.dual_emac) 1446d9ba8f9eSMugunthan V N slave = &priv->slaves[priv->emac_port]; 1447d9ba8f9eSMugunthan V N else 1448e86ac13bSMugunthan V N slave = &priv->slaves[priv->data.active_slave]; 1449d9ba8f9eSMugunthan V N 14502e5b38abSRichard Cochran ctrl = slave_read(slave, CPSW2_CONTROL); 145109c55372SGeorge Cherian switch (priv->version) { 145209c55372SGeorge Cherian case CPSW_VERSION_2: 145309c55372SGeorge Cherian ctrl &= ~CTRL_V2_ALL_TS_MASK; 14542e5b38abSRichard Cochran 14559232b16dSMugunthan V N if (priv->cpts->tx_enable) 145609c55372SGeorge Cherian ctrl |= CTRL_V2_TX_TS_BITS; 14572e5b38abSRichard Cochran 14589232b16dSMugunthan V N if (priv->cpts->rx_enable) 145909c55372SGeorge Cherian ctrl |= CTRL_V2_RX_TS_BITS; 146009c55372SGeorge Cherian break; 146109c55372SGeorge Cherian case CPSW_VERSION_3: 146209c55372SGeorge Cherian default: 146309c55372SGeorge Cherian ctrl &= ~CTRL_V3_ALL_TS_MASK; 146409c55372SGeorge Cherian 146509c55372SGeorge Cherian if (priv->cpts->tx_enable) 146609c55372SGeorge Cherian ctrl |= CTRL_V3_TX_TS_BITS; 146709c55372SGeorge Cherian 146809c55372SGeorge Cherian if (priv->cpts->rx_enable) 146909c55372SGeorge Cherian ctrl |= CTRL_V3_RX_TS_BITS; 147009c55372SGeorge Cherian break; 147109c55372SGeorge Cherian } 14722e5b38abSRichard Cochran 14732e5b38abSRichard Cochran mtype = (30 << TS_SEQ_ID_OFFSET_SHIFT) | EVENT_MSG_BITS; 14742e5b38abSRichard Cochran 14752e5b38abSRichard Cochran slave_write(slave, mtype, CPSW2_TS_SEQ_MTYPE); 14762e5b38abSRichard Cochran slave_write(slave, ctrl, CPSW2_CONTROL); 14772e5b38abSRichard Cochran __raw_writel(ETH_P_1588, &priv->regs->ts_ltype); 14782e5b38abSRichard Cochran } 14792e5b38abSRichard Cochran 1480a5b4145bSBen Hutchings static int cpsw_hwtstamp_set(struct net_device *dev, struct ifreq *ifr) 14812e5b38abSRichard Cochran { 14823177bf6fSMugunthan V N struct cpsw_priv *priv = netdev_priv(dev); 14839232b16dSMugunthan V N struct cpts *cpts = priv->cpts; 14842e5b38abSRichard Cochran struct hwtstamp_config cfg; 14852e5b38abSRichard Cochran 14862ee91e54SBen Hutchings if (priv->version != CPSW_VERSION_1 && 1487f7d403cbSGeorge Cherian priv->version != CPSW_VERSION_2 && 1488f7d403cbSGeorge Cherian priv->version != CPSW_VERSION_3) 14892ee91e54SBen Hutchings return -EOPNOTSUPP; 14902ee91e54SBen Hutchings 14912e5b38abSRichard Cochran if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg))) 14922e5b38abSRichard Cochran return -EFAULT; 14932e5b38abSRichard Cochran 14942e5b38abSRichard Cochran /* reserved for future extensions */ 14952e5b38abSRichard Cochran if (cfg.flags) 14962e5b38abSRichard Cochran return -EINVAL; 14972e5b38abSRichard Cochran 14982ee91e54SBen Hutchings if (cfg.tx_type != HWTSTAMP_TX_OFF && cfg.tx_type != HWTSTAMP_TX_ON) 14992e5b38abSRichard Cochran return -ERANGE; 15002e5b38abSRichard Cochran 15012e5b38abSRichard Cochran switch (cfg.rx_filter) { 15022e5b38abSRichard Cochran case HWTSTAMP_FILTER_NONE: 15032e5b38abSRichard Cochran cpts->rx_enable = 0; 15042e5b38abSRichard Cochran break; 15052e5b38abSRichard Cochran case HWTSTAMP_FILTER_ALL: 15062e5b38abSRichard Cochran case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: 15072e5b38abSRichard Cochran case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: 15082e5b38abSRichard Cochran case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: 15092e5b38abSRichard Cochran return -ERANGE; 15102e5b38abSRichard Cochran case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: 15112e5b38abSRichard Cochran case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 15122e5b38abSRichard Cochran case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 15132e5b38abSRichard Cochran case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: 15142e5b38abSRichard Cochran case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: 15152e5b38abSRichard Cochran case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: 15162e5b38abSRichard Cochran case HWTSTAMP_FILTER_PTP_V2_EVENT: 15172e5b38abSRichard Cochran case HWTSTAMP_FILTER_PTP_V2_SYNC: 15182e5b38abSRichard Cochran case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 15192e5b38abSRichard Cochran cpts->rx_enable = 1; 15202e5b38abSRichard Cochran cfg.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT; 15212e5b38abSRichard Cochran break; 15222e5b38abSRichard Cochran default: 15232e5b38abSRichard Cochran return -ERANGE; 15242e5b38abSRichard Cochran } 15252e5b38abSRichard Cochran 15262ee91e54SBen Hutchings cpts->tx_enable = cfg.tx_type == HWTSTAMP_TX_ON; 15272ee91e54SBen Hutchings 15282e5b38abSRichard Cochran switch (priv->version) { 15292e5b38abSRichard Cochran case CPSW_VERSION_1: 15302e5b38abSRichard Cochran cpsw_hwtstamp_v1(priv); 15312e5b38abSRichard Cochran break; 15322e5b38abSRichard Cochran case CPSW_VERSION_2: 1533f7d403cbSGeorge Cherian case CPSW_VERSION_3: 15342e5b38abSRichard Cochran cpsw_hwtstamp_v2(priv); 15352e5b38abSRichard Cochran break; 15362e5b38abSRichard Cochran default: 15372ee91e54SBen Hutchings WARN_ON(1); 15382e5b38abSRichard Cochran } 15392e5b38abSRichard Cochran 15402e5b38abSRichard Cochran return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0; 15412e5b38abSRichard Cochran } 15422e5b38abSRichard Cochran 1543a5b4145bSBen Hutchings static int cpsw_hwtstamp_get(struct net_device *dev, struct ifreq *ifr) 1544a5b4145bSBen Hutchings { 1545a5b4145bSBen Hutchings struct cpsw_priv *priv = netdev_priv(dev); 1546a5b4145bSBen Hutchings struct cpts *cpts = priv->cpts; 1547a5b4145bSBen Hutchings struct hwtstamp_config cfg; 1548a5b4145bSBen Hutchings 1549a5b4145bSBen Hutchings if (priv->version != CPSW_VERSION_1 && 1550f7d403cbSGeorge Cherian priv->version != CPSW_VERSION_2 && 1551f7d403cbSGeorge Cherian priv->version != CPSW_VERSION_3) 1552a5b4145bSBen Hutchings return -EOPNOTSUPP; 1553a5b4145bSBen Hutchings 1554a5b4145bSBen Hutchings cfg.flags = 0; 1555a5b4145bSBen Hutchings cfg.tx_type = cpts->tx_enable ? HWTSTAMP_TX_ON : HWTSTAMP_TX_OFF; 1556a5b4145bSBen Hutchings cfg.rx_filter = (cpts->rx_enable ? 1557a5b4145bSBen Hutchings HWTSTAMP_FILTER_PTP_V2_EVENT : HWTSTAMP_FILTER_NONE); 1558a5b4145bSBen Hutchings 1559a5b4145bSBen Hutchings return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0; 1560a5b4145bSBen Hutchings } 1561a5b4145bSBen Hutchings 15622e5b38abSRichard Cochran #endif /*CONFIG_TI_CPTS*/ 15632e5b38abSRichard Cochran 15642e5b38abSRichard Cochran static int cpsw_ndo_ioctl(struct net_device *dev, struct ifreq *req, int cmd) 15652e5b38abSRichard Cochran { 156611f2c988SMugunthan V N struct cpsw_priv *priv = netdev_priv(dev); 156711f2c988SMugunthan V N int slave_no = cpsw_slave_index(priv); 156811f2c988SMugunthan V N 15692e5b38abSRichard Cochran if (!netif_running(dev)) 15702e5b38abSRichard Cochran return -EINVAL; 15712e5b38abSRichard Cochran 157211f2c988SMugunthan V N switch (cmd) { 15732e5b38abSRichard Cochran #ifdef CONFIG_TI_CPTS 157411f2c988SMugunthan V N case SIOCSHWTSTAMP: 1575a5b4145bSBen Hutchings return cpsw_hwtstamp_set(dev, req); 1576a5b4145bSBen Hutchings case SIOCGHWTSTAMP: 1577a5b4145bSBen Hutchings return cpsw_hwtstamp_get(dev, req); 15782e5b38abSRichard Cochran #endif 15792e5b38abSRichard Cochran } 15802e5b38abSRichard Cochran 1581c1b59947SStefan Sørensen if (!priv->slaves[slave_no].phy) 1582c1b59947SStefan Sørensen return -EOPNOTSUPP; 1583c1b59947SStefan Sørensen return phy_mii_ioctl(priv->slaves[slave_no].phy, req, cmd); 158411f2c988SMugunthan V N } 158511f2c988SMugunthan V N 1586df828598SMugunthan V N static void cpsw_ndo_tx_timeout(struct net_device *ndev) 1587df828598SMugunthan V N { 1588df828598SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 1589df828598SMugunthan V N 1590df828598SMugunthan V N cpsw_err(priv, tx_err, "transmit timeout, restarting dma\n"); 15918dc43ddcSTobias Klauser ndev->stats.tx_errors++; 1592df828598SMugunthan V N cpsw_intr_disable(priv); 1593df828598SMugunthan V N cpdma_chan_stop(priv->txch); 1594df828598SMugunthan V N cpdma_chan_start(priv->txch); 1595df828598SMugunthan V N cpsw_intr_enable(priv); 1596df828598SMugunthan V N } 1597df828598SMugunthan V N 1598dcfd8d58SMugunthan V N static int cpsw_ndo_set_mac_address(struct net_device *ndev, void *p) 1599dcfd8d58SMugunthan V N { 1600dcfd8d58SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 1601dcfd8d58SMugunthan V N struct sockaddr *addr = (struct sockaddr *)p; 1602dcfd8d58SMugunthan V N int flags = 0; 1603dcfd8d58SMugunthan V N u16 vid = 0; 1604dcfd8d58SMugunthan V N 1605dcfd8d58SMugunthan V N if (!is_valid_ether_addr(addr->sa_data)) 1606dcfd8d58SMugunthan V N return -EADDRNOTAVAIL; 1607dcfd8d58SMugunthan V N 1608dcfd8d58SMugunthan V N if (priv->data.dual_emac) { 1609dcfd8d58SMugunthan V N vid = priv->slaves[priv->emac_port].port_vlan; 1610dcfd8d58SMugunthan V N flags = ALE_VLAN; 1611dcfd8d58SMugunthan V N } 1612dcfd8d58SMugunthan V N 1613dcfd8d58SMugunthan V N cpsw_ale_del_ucast(priv->ale, priv->mac_addr, priv->host_port, 1614dcfd8d58SMugunthan V N flags, vid); 1615dcfd8d58SMugunthan V N cpsw_ale_add_ucast(priv->ale, addr->sa_data, priv->host_port, 1616dcfd8d58SMugunthan V N flags, vid); 1617dcfd8d58SMugunthan V N 1618dcfd8d58SMugunthan V N memcpy(priv->mac_addr, addr->sa_data, ETH_ALEN); 1619dcfd8d58SMugunthan V N memcpy(ndev->dev_addr, priv->mac_addr, ETH_ALEN); 1620dcfd8d58SMugunthan V N for_each_slave(priv, cpsw_set_slave_mac, priv); 1621dcfd8d58SMugunthan V N 1622dcfd8d58SMugunthan V N return 0; 1623dcfd8d58SMugunthan V N } 1624dcfd8d58SMugunthan V N 1625df828598SMugunthan V N #ifdef CONFIG_NET_POLL_CONTROLLER 1626df828598SMugunthan V N static void cpsw_ndo_poll_controller(struct net_device *ndev) 1627df828598SMugunthan V N { 1628df828598SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 1629df828598SMugunthan V N 1630df828598SMugunthan V N cpsw_intr_disable(priv); 163192cb13fbSFelipe Balbi cpsw_rx_interrupt(priv->irqs_table[0], priv); 163292cb13fbSFelipe Balbi cpsw_tx_interrupt(priv->irqs_table[1], priv); 1633df828598SMugunthan V N cpsw_intr_enable(priv); 1634df828598SMugunthan V N } 1635df828598SMugunthan V N #endif 1636df828598SMugunthan V N 16373b72c2feSMugunthan V N static inline int cpsw_add_vlan_ale_entry(struct cpsw_priv *priv, 16383b72c2feSMugunthan V N unsigned short vid) 16393b72c2feSMugunthan V N { 16403b72c2feSMugunthan V N int ret; 16419f6bd8faSMugunthan V N int unreg_mcast_mask = 0; 16429f6bd8faSMugunthan V N u32 port_mask; 16439f6bd8faSMugunthan V N 16449f6bd8faSMugunthan V N if (priv->data.dual_emac) { 16459f6bd8faSMugunthan V N port_mask = (1 << (priv->emac_port + 1)) | ALE_PORT_HOST; 16469f6bd8faSMugunthan V N 16479f6bd8faSMugunthan V N if (priv->ndev->flags & IFF_ALLMULTI) 16489f6bd8faSMugunthan V N unreg_mcast_mask = port_mask; 16499f6bd8faSMugunthan V N } else { 16509f6bd8faSMugunthan V N port_mask = ALE_ALL_PORTS; 16511e5c4bc4SLennart Sorensen 16521e5c4bc4SLennart Sorensen if (priv->ndev->flags & IFF_ALLMULTI) 16531e5c4bc4SLennart Sorensen unreg_mcast_mask = ALE_ALL_PORTS; 16541e5c4bc4SLennart Sorensen else 16551e5c4bc4SLennart Sorensen unreg_mcast_mask = ALE_PORT_1 | ALE_PORT_2; 16569f6bd8faSMugunthan V N } 16573b72c2feSMugunthan V N 16589f6bd8faSMugunthan V N ret = cpsw_ale_add_vlan(priv->ale, vid, port_mask, 0, port_mask, 16591e5c4bc4SLennart Sorensen unreg_mcast_mask << priv->host_port); 16603b72c2feSMugunthan V N if (ret != 0) 16613b72c2feSMugunthan V N return ret; 16623b72c2feSMugunthan V N 16633b72c2feSMugunthan V N ret = cpsw_ale_add_ucast(priv->ale, priv->mac_addr, 16643b72c2feSMugunthan V N priv->host_port, ALE_VLAN, vid); 16653b72c2feSMugunthan V N if (ret != 0) 16663b72c2feSMugunthan V N goto clean_vid; 16673b72c2feSMugunthan V N 16683b72c2feSMugunthan V N ret = cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast, 16699f6bd8faSMugunthan V N port_mask, ALE_VLAN, vid, 0); 16703b72c2feSMugunthan V N if (ret != 0) 16713b72c2feSMugunthan V N goto clean_vlan_ucast; 16723b72c2feSMugunthan V N return 0; 16733b72c2feSMugunthan V N 16743b72c2feSMugunthan V N clean_vlan_ucast: 16753b72c2feSMugunthan V N cpsw_ale_del_ucast(priv->ale, priv->mac_addr, 16763b72c2feSMugunthan V N priv->host_port, ALE_VLAN, vid); 16773b72c2feSMugunthan V N clean_vid: 16783b72c2feSMugunthan V N cpsw_ale_del_vlan(priv->ale, vid, 0); 16793b72c2feSMugunthan V N return ret; 16803b72c2feSMugunthan V N } 16813b72c2feSMugunthan V N 16823b72c2feSMugunthan V N static int cpsw_ndo_vlan_rx_add_vid(struct net_device *ndev, 168380d5c368SPatrick McHardy __be16 proto, u16 vid) 16843b72c2feSMugunthan V N { 16853b72c2feSMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 16863b72c2feSMugunthan V N 16873b72c2feSMugunthan V N if (vid == priv->data.default_vlan) 16883b72c2feSMugunthan V N return 0; 16893b72c2feSMugunthan V N 169002a54164SMugunthan V N if (priv->data.dual_emac) { 169102a54164SMugunthan V N /* In dual EMAC, reserved VLAN id should not be used for 169202a54164SMugunthan V N * creating VLAN interfaces as this can break the dual 169302a54164SMugunthan V N * EMAC port separation 169402a54164SMugunthan V N */ 169502a54164SMugunthan V N int i; 169602a54164SMugunthan V N 169702a54164SMugunthan V N for (i = 0; i < priv->data.slaves; i++) { 169802a54164SMugunthan V N if (vid == priv->slaves[i].port_vlan) 169902a54164SMugunthan V N return -EINVAL; 170002a54164SMugunthan V N } 170102a54164SMugunthan V N } 170202a54164SMugunthan V N 17033b72c2feSMugunthan V N dev_info(priv->dev, "Adding vlanid %d to vlan filter\n", vid); 17043b72c2feSMugunthan V N return cpsw_add_vlan_ale_entry(priv, vid); 17053b72c2feSMugunthan V N } 17063b72c2feSMugunthan V N 17073b72c2feSMugunthan V N static int cpsw_ndo_vlan_rx_kill_vid(struct net_device *ndev, 170880d5c368SPatrick McHardy __be16 proto, u16 vid) 17093b72c2feSMugunthan V N { 17103b72c2feSMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 17113b72c2feSMugunthan V N int ret; 17123b72c2feSMugunthan V N 17133b72c2feSMugunthan V N if (vid == priv->data.default_vlan) 17143b72c2feSMugunthan V N return 0; 17153b72c2feSMugunthan V N 171602a54164SMugunthan V N if (priv->data.dual_emac) { 171702a54164SMugunthan V N int i; 171802a54164SMugunthan V N 171902a54164SMugunthan V N for (i = 0; i < priv->data.slaves; i++) { 172002a54164SMugunthan V N if (vid == priv->slaves[i].port_vlan) 172102a54164SMugunthan V N return -EINVAL; 172202a54164SMugunthan V N } 172302a54164SMugunthan V N } 172402a54164SMugunthan V N 17253b72c2feSMugunthan V N dev_info(priv->dev, "removing vlanid %d from vlan filter\n", vid); 17263b72c2feSMugunthan V N ret = cpsw_ale_del_vlan(priv->ale, vid, 0); 17273b72c2feSMugunthan V N if (ret != 0) 17283b72c2feSMugunthan V N return ret; 17293b72c2feSMugunthan V N 17303b72c2feSMugunthan V N ret = cpsw_ale_del_ucast(priv->ale, priv->mac_addr, 17313b72c2feSMugunthan V N priv->host_port, ALE_VLAN, vid); 17323b72c2feSMugunthan V N if (ret != 0) 17333b72c2feSMugunthan V N return ret; 17343b72c2feSMugunthan V N 17353b72c2feSMugunthan V N return cpsw_ale_del_mcast(priv->ale, priv->ndev->broadcast, 17363b72c2feSMugunthan V N 0, ALE_VLAN, vid); 17373b72c2feSMugunthan V N } 17383b72c2feSMugunthan V N 1739df828598SMugunthan V N static const struct net_device_ops cpsw_netdev_ops = { 1740df828598SMugunthan V N .ndo_open = cpsw_ndo_open, 1741df828598SMugunthan V N .ndo_stop = cpsw_ndo_stop, 1742df828598SMugunthan V N .ndo_start_xmit = cpsw_ndo_start_xmit, 1743dcfd8d58SMugunthan V N .ndo_set_mac_address = cpsw_ndo_set_mac_address, 17442e5b38abSRichard Cochran .ndo_do_ioctl = cpsw_ndo_ioctl, 1745df828598SMugunthan V N .ndo_validate_addr = eth_validate_addr, 17465c473ed2SDavid S. Miller .ndo_change_mtu = eth_change_mtu, 1747df828598SMugunthan V N .ndo_tx_timeout = cpsw_ndo_tx_timeout, 17485c50a856SMugunthan V N .ndo_set_rx_mode = cpsw_ndo_set_rx_mode, 1749df828598SMugunthan V N #ifdef CONFIG_NET_POLL_CONTROLLER 1750df828598SMugunthan V N .ndo_poll_controller = cpsw_ndo_poll_controller, 1751df828598SMugunthan V N #endif 17523b72c2feSMugunthan V N .ndo_vlan_rx_add_vid = cpsw_ndo_vlan_rx_add_vid, 17533b72c2feSMugunthan V N .ndo_vlan_rx_kill_vid = cpsw_ndo_vlan_rx_kill_vid, 1754df828598SMugunthan V N }; 1755df828598SMugunthan V N 175652c4f0ecSMugunthan V N static int cpsw_get_regs_len(struct net_device *ndev) 175752c4f0ecSMugunthan V N { 175852c4f0ecSMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 175952c4f0ecSMugunthan V N 176052c4f0ecSMugunthan V N return priv->data.ale_entries * ALE_ENTRY_WORDS * sizeof(u32); 176152c4f0ecSMugunthan V N } 176252c4f0ecSMugunthan V N 176352c4f0ecSMugunthan V N static void cpsw_get_regs(struct net_device *ndev, 176452c4f0ecSMugunthan V N struct ethtool_regs *regs, void *p) 176552c4f0ecSMugunthan V N { 176652c4f0ecSMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 176752c4f0ecSMugunthan V N u32 *reg = p; 176852c4f0ecSMugunthan V N 176952c4f0ecSMugunthan V N /* update CPSW IP version */ 177052c4f0ecSMugunthan V N regs->version = priv->version; 177152c4f0ecSMugunthan V N 177252c4f0ecSMugunthan V N cpsw_ale_dump(priv->ale, reg); 177352c4f0ecSMugunthan V N } 177452c4f0ecSMugunthan V N 1775df828598SMugunthan V N static void cpsw_get_drvinfo(struct net_device *ndev, 1776df828598SMugunthan V N struct ethtool_drvinfo *info) 1777df828598SMugunthan V N { 1778df828598SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 17797826d43fSJiri Pirko 178052c4f0ecSMugunthan V N strlcpy(info->driver, "cpsw", sizeof(info->driver)); 17817826d43fSJiri Pirko strlcpy(info->version, "1.0", sizeof(info->version)); 17827826d43fSJiri Pirko strlcpy(info->bus_info, priv->pdev->name, sizeof(info->bus_info)); 178352c4f0ecSMugunthan V N info->regdump_len = cpsw_get_regs_len(ndev); 1784df828598SMugunthan V N } 1785df828598SMugunthan V N 1786df828598SMugunthan V N static u32 cpsw_get_msglevel(struct net_device *ndev) 1787df828598SMugunthan V N { 1788df828598SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 1789df828598SMugunthan V N return priv->msg_enable; 1790df828598SMugunthan V N } 1791df828598SMugunthan V N 1792df828598SMugunthan V N static void cpsw_set_msglevel(struct net_device *ndev, u32 value) 1793df828598SMugunthan V N { 1794df828598SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 1795df828598SMugunthan V N priv->msg_enable = value; 1796df828598SMugunthan V N } 1797df828598SMugunthan V N 17982e5b38abSRichard Cochran static int cpsw_get_ts_info(struct net_device *ndev, 17992e5b38abSRichard Cochran struct ethtool_ts_info *info) 18002e5b38abSRichard Cochran { 18012e5b38abSRichard Cochran #ifdef CONFIG_TI_CPTS 18022e5b38abSRichard Cochran struct cpsw_priv *priv = netdev_priv(ndev); 18032e5b38abSRichard Cochran 18042e5b38abSRichard Cochran info->so_timestamping = 18052e5b38abSRichard Cochran SOF_TIMESTAMPING_TX_HARDWARE | 18062e5b38abSRichard Cochran SOF_TIMESTAMPING_TX_SOFTWARE | 18072e5b38abSRichard Cochran SOF_TIMESTAMPING_RX_HARDWARE | 18082e5b38abSRichard Cochran SOF_TIMESTAMPING_RX_SOFTWARE | 18092e5b38abSRichard Cochran SOF_TIMESTAMPING_SOFTWARE | 18102e5b38abSRichard Cochran SOF_TIMESTAMPING_RAW_HARDWARE; 18119232b16dSMugunthan V N info->phc_index = priv->cpts->phc_index; 18122e5b38abSRichard Cochran info->tx_types = 18132e5b38abSRichard Cochran (1 << HWTSTAMP_TX_OFF) | 18142e5b38abSRichard Cochran (1 << HWTSTAMP_TX_ON); 18152e5b38abSRichard Cochran info->rx_filters = 18162e5b38abSRichard Cochran (1 << HWTSTAMP_FILTER_NONE) | 18172e5b38abSRichard Cochran (1 << HWTSTAMP_FILTER_PTP_V2_EVENT); 18182e5b38abSRichard Cochran #else 18192e5b38abSRichard Cochran info->so_timestamping = 18202e5b38abSRichard Cochran SOF_TIMESTAMPING_TX_SOFTWARE | 18212e5b38abSRichard Cochran SOF_TIMESTAMPING_RX_SOFTWARE | 18222e5b38abSRichard Cochran SOF_TIMESTAMPING_SOFTWARE; 18232e5b38abSRichard Cochran info->phc_index = -1; 18242e5b38abSRichard Cochran info->tx_types = 0; 18252e5b38abSRichard Cochran info->rx_filters = 0; 18262e5b38abSRichard Cochran #endif 18272e5b38abSRichard Cochran return 0; 18282e5b38abSRichard Cochran } 18292e5b38abSRichard Cochran 1830d3bb9c58SMugunthan V N static int cpsw_get_settings(struct net_device *ndev, 1831d3bb9c58SMugunthan V N struct ethtool_cmd *ecmd) 1832d3bb9c58SMugunthan V N { 1833d3bb9c58SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 1834d3bb9c58SMugunthan V N int slave_no = cpsw_slave_index(priv); 1835d3bb9c58SMugunthan V N 1836d3bb9c58SMugunthan V N if (priv->slaves[slave_no].phy) 1837d3bb9c58SMugunthan V N return phy_ethtool_gset(priv->slaves[slave_no].phy, ecmd); 1838d3bb9c58SMugunthan V N else 1839d3bb9c58SMugunthan V N return -EOPNOTSUPP; 1840d3bb9c58SMugunthan V N } 1841d3bb9c58SMugunthan V N 1842d3bb9c58SMugunthan V N static int cpsw_set_settings(struct net_device *ndev, struct ethtool_cmd *ecmd) 1843d3bb9c58SMugunthan V N { 1844d3bb9c58SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 1845d3bb9c58SMugunthan V N int slave_no = cpsw_slave_index(priv); 1846d3bb9c58SMugunthan V N 1847d3bb9c58SMugunthan V N if (priv->slaves[slave_no].phy) 1848d3bb9c58SMugunthan V N return phy_ethtool_sset(priv->slaves[slave_no].phy, ecmd); 1849d3bb9c58SMugunthan V N else 1850d3bb9c58SMugunthan V N return -EOPNOTSUPP; 1851d3bb9c58SMugunthan V N } 1852d3bb9c58SMugunthan V N 1853d8a64420SMatus Ujhelyi static void cpsw_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol) 1854d8a64420SMatus Ujhelyi { 1855d8a64420SMatus Ujhelyi struct cpsw_priv *priv = netdev_priv(ndev); 1856d8a64420SMatus Ujhelyi int slave_no = cpsw_slave_index(priv); 1857d8a64420SMatus Ujhelyi 1858d8a64420SMatus Ujhelyi wol->supported = 0; 1859d8a64420SMatus Ujhelyi wol->wolopts = 0; 1860d8a64420SMatus Ujhelyi 1861d8a64420SMatus Ujhelyi if (priv->slaves[slave_no].phy) 1862d8a64420SMatus Ujhelyi phy_ethtool_get_wol(priv->slaves[slave_no].phy, wol); 1863d8a64420SMatus Ujhelyi } 1864d8a64420SMatus Ujhelyi 1865d8a64420SMatus Ujhelyi static int cpsw_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol) 1866d8a64420SMatus Ujhelyi { 1867d8a64420SMatus Ujhelyi struct cpsw_priv *priv = netdev_priv(ndev); 1868d8a64420SMatus Ujhelyi int slave_no = cpsw_slave_index(priv); 1869d8a64420SMatus Ujhelyi 1870d8a64420SMatus Ujhelyi if (priv->slaves[slave_no].phy) 1871d8a64420SMatus Ujhelyi return phy_ethtool_set_wol(priv->slaves[slave_no].phy, wol); 1872d8a64420SMatus Ujhelyi else 1873d8a64420SMatus Ujhelyi return -EOPNOTSUPP; 1874d8a64420SMatus Ujhelyi } 1875d8a64420SMatus Ujhelyi 18761923d6e4SMugunthan V N static void cpsw_get_pauseparam(struct net_device *ndev, 18771923d6e4SMugunthan V N struct ethtool_pauseparam *pause) 18781923d6e4SMugunthan V N { 18791923d6e4SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 18801923d6e4SMugunthan V N 18811923d6e4SMugunthan V N pause->autoneg = AUTONEG_DISABLE; 18821923d6e4SMugunthan V N pause->rx_pause = priv->rx_pause ? true : false; 18831923d6e4SMugunthan V N pause->tx_pause = priv->tx_pause ? true : false; 18841923d6e4SMugunthan V N } 18851923d6e4SMugunthan V N 18861923d6e4SMugunthan V N static int cpsw_set_pauseparam(struct net_device *ndev, 18871923d6e4SMugunthan V N struct ethtool_pauseparam *pause) 18881923d6e4SMugunthan V N { 18891923d6e4SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 18901923d6e4SMugunthan V N bool link; 18911923d6e4SMugunthan V N 18921923d6e4SMugunthan V N priv->rx_pause = pause->rx_pause ? true : false; 18931923d6e4SMugunthan V N priv->tx_pause = pause->tx_pause ? true : false; 18941923d6e4SMugunthan V N 18951923d6e4SMugunthan V N for_each_slave(priv, _cpsw_adjust_link, priv, &link); 18961923d6e4SMugunthan V N 18971923d6e4SMugunthan V N return 0; 18981923d6e4SMugunthan V N } 18991923d6e4SMugunthan V N 1900df828598SMugunthan V N static const struct ethtool_ops cpsw_ethtool_ops = { 1901df828598SMugunthan V N .get_drvinfo = cpsw_get_drvinfo, 1902df828598SMugunthan V N .get_msglevel = cpsw_get_msglevel, 1903df828598SMugunthan V N .set_msglevel = cpsw_set_msglevel, 1904df828598SMugunthan V N .get_link = ethtool_op_get_link, 19052e5b38abSRichard Cochran .get_ts_info = cpsw_get_ts_info, 1906d3bb9c58SMugunthan V N .get_settings = cpsw_get_settings, 1907d3bb9c58SMugunthan V N .set_settings = cpsw_set_settings, 1908ff5b8ef2SMugunthan V N .get_coalesce = cpsw_get_coalesce, 1909ff5b8ef2SMugunthan V N .set_coalesce = cpsw_set_coalesce, 1910d9718546SMugunthan V N .get_sset_count = cpsw_get_sset_count, 1911d9718546SMugunthan V N .get_strings = cpsw_get_strings, 1912d9718546SMugunthan V N .get_ethtool_stats = cpsw_get_ethtool_stats, 19131923d6e4SMugunthan V N .get_pauseparam = cpsw_get_pauseparam, 19141923d6e4SMugunthan V N .set_pauseparam = cpsw_set_pauseparam, 1915d8a64420SMatus Ujhelyi .get_wol = cpsw_get_wol, 1916d8a64420SMatus Ujhelyi .set_wol = cpsw_set_wol, 191752c4f0ecSMugunthan V N .get_regs_len = cpsw_get_regs_len, 191852c4f0ecSMugunthan V N .get_regs = cpsw_get_regs, 1919df828598SMugunthan V N }; 1920df828598SMugunthan V N 1921549985eeSRichard Cochran static void cpsw_slave_init(struct cpsw_slave *slave, struct cpsw_priv *priv, 1922549985eeSRichard Cochran u32 slave_reg_ofs, u32 sliver_reg_ofs) 1923df828598SMugunthan V N { 1924df828598SMugunthan V N void __iomem *regs = priv->regs; 1925df828598SMugunthan V N int slave_num = slave->slave_num; 1926df828598SMugunthan V N struct cpsw_slave_data *data = priv->data.slave_data + slave_num; 1927df828598SMugunthan V N 1928df828598SMugunthan V N slave->data = data; 1929549985eeSRichard Cochran slave->regs = regs + slave_reg_ofs; 1930549985eeSRichard Cochran slave->sliver = regs + sliver_reg_ofs; 1931d9ba8f9eSMugunthan V N slave->port_vlan = data->dual_emac_res_vlan; 1932df828598SMugunthan V N } 1933df828598SMugunthan V N 19342eb32b0aSMugunthan V N static int cpsw_probe_dt(struct cpsw_platform_data *data, 19352eb32b0aSMugunthan V N struct platform_device *pdev) 19362eb32b0aSMugunthan V N { 19372eb32b0aSMugunthan V N struct device_node *node = pdev->dev.of_node; 19382eb32b0aSMugunthan V N struct device_node *slave_node; 19392eb32b0aSMugunthan V N int i = 0, ret; 19402eb32b0aSMugunthan V N u32 prop; 19412eb32b0aSMugunthan V N 19422eb32b0aSMugunthan V N if (!node) 19432eb32b0aSMugunthan V N return -EINVAL; 19442eb32b0aSMugunthan V N 19452eb32b0aSMugunthan V N if (of_property_read_u32(node, "slaves", &prop)) { 194688c99ff6SGeorge Cherian dev_err(&pdev->dev, "Missing slaves property in the DT.\n"); 19472eb32b0aSMugunthan V N return -EINVAL; 19482eb32b0aSMugunthan V N } 19492eb32b0aSMugunthan V N data->slaves = prop; 19502eb32b0aSMugunthan V N 1951e86ac13bSMugunthan V N if (of_property_read_u32(node, "active_slave", &prop)) { 195288c99ff6SGeorge Cherian dev_err(&pdev->dev, "Missing active_slave property in the DT.\n"); 1953aa1a15e2SDaniel Mack return -EINVAL; 195478ca0b28SRichard Cochran } 1955e86ac13bSMugunthan V N data->active_slave = prop; 195678ca0b28SRichard Cochran 195700ab94eeSRichard Cochran if (of_property_read_u32(node, "cpts_clock_mult", &prop)) { 195888c99ff6SGeorge Cherian dev_err(&pdev->dev, "Missing cpts_clock_mult property in the DT.\n"); 1959aa1a15e2SDaniel Mack return -EINVAL; 196000ab94eeSRichard Cochran } 196100ab94eeSRichard Cochran data->cpts_clock_mult = prop; 196200ab94eeSRichard Cochran 196300ab94eeSRichard Cochran if (of_property_read_u32(node, "cpts_clock_shift", &prop)) { 196488c99ff6SGeorge Cherian dev_err(&pdev->dev, "Missing cpts_clock_shift property in the DT.\n"); 1965aa1a15e2SDaniel Mack return -EINVAL; 196600ab94eeSRichard Cochran } 196700ab94eeSRichard Cochran data->cpts_clock_shift = prop; 196800ab94eeSRichard Cochran 1969aa1a15e2SDaniel Mack data->slave_data = devm_kzalloc(&pdev->dev, data->slaves 1970aa1a15e2SDaniel Mack * sizeof(struct cpsw_slave_data), 1971b2adaca9SJoe Perches GFP_KERNEL); 1972b2adaca9SJoe Perches if (!data->slave_data) 1973aa1a15e2SDaniel Mack return -ENOMEM; 19742eb32b0aSMugunthan V N 19752eb32b0aSMugunthan V N if (of_property_read_u32(node, "cpdma_channels", &prop)) { 197688c99ff6SGeorge Cherian dev_err(&pdev->dev, "Missing cpdma_channels property in the DT.\n"); 1977aa1a15e2SDaniel Mack return -EINVAL; 19782eb32b0aSMugunthan V N } 19792eb32b0aSMugunthan V N data->channels = prop; 19802eb32b0aSMugunthan V N 19812eb32b0aSMugunthan V N if (of_property_read_u32(node, "ale_entries", &prop)) { 198288c99ff6SGeorge Cherian dev_err(&pdev->dev, "Missing ale_entries property in the DT.\n"); 1983aa1a15e2SDaniel Mack return -EINVAL; 19842eb32b0aSMugunthan V N } 19852eb32b0aSMugunthan V N data->ale_entries = prop; 19862eb32b0aSMugunthan V N 19872eb32b0aSMugunthan V N if (of_property_read_u32(node, "bd_ram_size", &prop)) { 198888c99ff6SGeorge Cherian dev_err(&pdev->dev, "Missing bd_ram_size property in the DT.\n"); 1989aa1a15e2SDaniel Mack return -EINVAL; 19902eb32b0aSMugunthan V N } 19912eb32b0aSMugunthan V N data->bd_ram_size = prop; 19922eb32b0aSMugunthan V N 19932eb32b0aSMugunthan V N if (of_property_read_u32(node, "rx_descs", &prop)) { 199488c99ff6SGeorge Cherian dev_err(&pdev->dev, "Missing rx_descs property in the DT.\n"); 1995aa1a15e2SDaniel Mack return -EINVAL; 19962eb32b0aSMugunthan V N } 19972eb32b0aSMugunthan V N data->rx_descs = prop; 19982eb32b0aSMugunthan V N 19992eb32b0aSMugunthan V N if (of_property_read_u32(node, "mac_control", &prop)) { 200088c99ff6SGeorge Cherian dev_err(&pdev->dev, "Missing mac_control property in the DT.\n"); 2001aa1a15e2SDaniel Mack return -EINVAL; 20022eb32b0aSMugunthan V N } 20032eb32b0aSMugunthan V N data->mac_control = prop; 20042eb32b0aSMugunthan V N 2005281abd96SMarkus Pargmann if (of_property_read_bool(node, "dual_emac")) 2006281abd96SMarkus Pargmann data->dual_emac = 1; 2007d9ba8f9eSMugunthan V N 20081fb19aa7SVaibhav Hiremath /* 20091fb19aa7SVaibhav Hiremath * Populate all the child nodes here... 20101fb19aa7SVaibhav Hiremath */ 20111fb19aa7SVaibhav Hiremath ret = of_platform_populate(node, NULL, NULL, &pdev->dev); 20121fb19aa7SVaibhav Hiremath /* We do not want to force this, as in some cases may not have child */ 20131fb19aa7SVaibhav Hiremath if (ret) 201488c99ff6SGeorge Cherian dev_warn(&pdev->dev, "Doesn't have any child node\n"); 20151fb19aa7SVaibhav Hiremath 2016f468b10eSMarkus Pargmann for_each_child_of_node(node, slave_node) { 2017549985eeSRichard Cochran struct cpsw_slave_data *slave_data = data->slave_data + i; 2018549985eeSRichard Cochran const void *mac_addr = NULL; 2019549985eeSRichard Cochran u32 phyid; 2020549985eeSRichard Cochran int lenp; 2021549985eeSRichard Cochran const __be32 *parp; 2022549985eeSRichard Cochran struct device_node *mdio_node; 2023549985eeSRichard Cochran struct platform_device *mdio; 2024549985eeSRichard Cochran 2025f468b10eSMarkus Pargmann /* This is no slave child node, continue */ 2026f468b10eSMarkus Pargmann if (strcmp(slave_node->name, "slave")) 2027f468b10eSMarkus Pargmann continue; 2028f468b10eSMarkus Pargmann 2029549985eeSRichard Cochran parp = of_get_property(slave_node, "phy_id", &lenp); 2030ce16294fSLothar Waßmann if ((parp == NULL) || (lenp != (sizeof(void *) * 2))) { 203188c99ff6SGeorge Cherian dev_err(&pdev->dev, "Missing slave[%d] phy_id property\n", i); 203247276fccSMugunthan V N goto no_phy_slave; 2033549985eeSRichard Cochran } 2034549985eeSRichard Cochran mdio_node = of_find_node_by_phandle(be32_to_cpup(parp)); 2035549985eeSRichard Cochran phyid = be32_to_cpup(parp+1); 2036549985eeSRichard Cochran mdio = of_find_device_by_node(mdio_node); 203760e71ab5SJohan Hovold of_node_put(mdio_node); 20386954cc1fSJohan Hovold if (!mdio) { 203956fdb2e0SMarkus Pargmann dev_err(&pdev->dev, "Missing mdio platform device\n"); 20406954cc1fSJohan Hovold return -EINVAL; 20416954cc1fSJohan Hovold } 2042549985eeSRichard Cochran snprintf(slave_data->phy_id, sizeof(slave_data->phy_id), 2043549985eeSRichard Cochran PHY_ID_FMT, mdio->name, phyid); 2044549985eeSRichard Cochran 204547276fccSMugunthan V N slave_data->phy_if = of_get_phy_mode(slave_node); 204647276fccSMugunthan V N if (slave_data->phy_if < 0) { 204747276fccSMugunthan V N dev_err(&pdev->dev, "Missing or malformed slave[%d] phy-mode property\n", 204847276fccSMugunthan V N i); 204947276fccSMugunthan V N return slave_data->phy_if; 205047276fccSMugunthan V N } 205147276fccSMugunthan V N 205247276fccSMugunthan V N no_phy_slave: 2053549985eeSRichard Cochran mac_addr = of_get_mac_address(slave_node); 20540ba517b1SMarkus Pargmann if (mac_addr) { 2055549985eeSRichard Cochran memcpy(slave_data->mac_addr, mac_addr, ETH_ALEN); 20560ba517b1SMarkus Pargmann } else { 20570ba517b1SMarkus Pargmann if (of_machine_is_compatible("ti,am33xx")) { 2058e5a49c1eSTony Lindgren ret = cpsw_am33xx_cm_get_macid(&pdev->dev, 2059e5a49c1eSTony Lindgren 0x630, i, 20600ba517b1SMarkus Pargmann slave_data->mac_addr); 20610ba517b1SMarkus Pargmann if (ret) 20620ba517b1SMarkus Pargmann return ret; 20630ba517b1SMarkus Pargmann } 20640ba517b1SMarkus Pargmann } 2065d9ba8f9eSMugunthan V N if (data->dual_emac) { 206691c4166cSMugunthan V N if (of_property_read_u32(slave_node, "dual_emac_res_vlan", 2067d9ba8f9eSMugunthan V N &prop)) { 206888c99ff6SGeorge Cherian dev_err(&pdev->dev, "Missing dual_emac_res_vlan in DT.\n"); 2069d9ba8f9eSMugunthan V N slave_data->dual_emac_res_vlan = i+1; 207088c99ff6SGeorge Cherian dev_err(&pdev->dev, "Using %d as Reserved VLAN for %d slave\n", 2071d9ba8f9eSMugunthan V N slave_data->dual_emac_res_vlan, i); 2072d9ba8f9eSMugunthan V N } else { 2073d9ba8f9eSMugunthan V N slave_data->dual_emac_res_vlan = prop; 2074d9ba8f9eSMugunthan V N } 2075d9ba8f9eSMugunthan V N } 2076d9ba8f9eSMugunthan V N 2077549985eeSRichard Cochran i++; 20783a27bfacSMugunthan V N if (i == data->slaves) 20793a27bfacSMugunthan V N break; 2080549985eeSRichard Cochran } 2081549985eeSRichard Cochran 20822eb32b0aSMugunthan V N return 0; 20832eb32b0aSMugunthan V N } 20842eb32b0aSMugunthan V N 2085d9ba8f9eSMugunthan V N static int cpsw_probe_dual_emac(struct platform_device *pdev, 2086d9ba8f9eSMugunthan V N struct cpsw_priv *priv) 2087d9ba8f9eSMugunthan V N { 2088d9ba8f9eSMugunthan V N struct cpsw_platform_data *data = &priv->data; 2089d9ba8f9eSMugunthan V N struct net_device *ndev; 2090d9ba8f9eSMugunthan V N struct cpsw_priv *priv_sl2; 2091d9ba8f9eSMugunthan V N int ret = 0, i; 2092d9ba8f9eSMugunthan V N 2093d9ba8f9eSMugunthan V N ndev = alloc_etherdev(sizeof(struct cpsw_priv)); 2094d9ba8f9eSMugunthan V N if (!ndev) { 209588c99ff6SGeorge Cherian dev_err(&pdev->dev, "cpsw: error allocating net_device\n"); 2096d9ba8f9eSMugunthan V N return -ENOMEM; 2097d9ba8f9eSMugunthan V N } 2098d9ba8f9eSMugunthan V N 2099d9ba8f9eSMugunthan V N priv_sl2 = netdev_priv(ndev); 2100d9ba8f9eSMugunthan V N spin_lock_init(&priv_sl2->lock); 2101d9ba8f9eSMugunthan V N priv_sl2->data = *data; 2102d9ba8f9eSMugunthan V N priv_sl2->pdev = pdev; 2103d9ba8f9eSMugunthan V N priv_sl2->ndev = ndev; 2104d9ba8f9eSMugunthan V N priv_sl2->dev = &ndev->dev; 2105d9ba8f9eSMugunthan V N priv_sl2->msg_enable = netif_msg_init(debug_level, CPSW_DEBUG); 2106d9ba8f9eSMugunthan V N priv_sl2->rx_packet_max = max(rx_packet_max, 128); 2107d9ba8f9eSMugunthan V N 2108d9ba8f9eSMugunthan V N if (is_valid_ether_addr(data->slave_data[1].mac_addr)) { 2109d9ba8f9eSMugunthan V N memcpy(priv_sl2->mac_addr, data->slave_data[1].mac_addr, 2110d9ba8f9eSMugunthan V N ETH_ALEN); 211188c99ff6SGeorge Cherian dev_info(&pdev->dev, "cpsw: Detected MACID = %pM\n", priv_sl2->mac_addr); 2112d9ba8f9eSMugunthan V N } else { 2113d9ba8f9eSMugunthan V N random_ether_addr(priv_sl2->mac_addr); 211488c99ff6SGeorge Cherian dev_info(&pdev->dev, "cpsw: Random MACID = %pM\n", priv_sl2->mac_addr); 2115d9ba8f9eSMugunthan V N } 2116d9ba8f9eSMugunthan V N memcpy(ndev->dev_addr, priv_sl2->mac_addr, ETH_ALEN); 2117d9ba8f9eSMugunthan V N 2118d9ba8f9eSMugunthan V N priv_sl2->slaves = priv->slaves; 2119d9ba8f9eSMugunthan V N priv_sl2->clk = priv->clk; 2120d9ba8f9eSMugunthan V N 2121ff5b8ef2SMugunthan V N priv_sl2->coal_intvl = 0; 2122ff5b8ef2SMugunthan V N priv_sl2->bus_freq_mhz = priv->bus_freq_mhz; 2123ff5b8ef2SMugunthan V N 2124d9ba8f9eSMugunthan V N priv_sl2->regs = priv->regs; 2125d9ba8f9eSMugunthan V N priv_sl2->host_port = priv->host_port; 2126d9ba8f9eSMugunthan V N priv_sl2->host_port_regs = priv->host_port_regs; 2127d9ba8f9eSMugunthan V N priv_sl2->wr_regs = priv->wr_regs; 2128d9718546SMugunthan V N priv_sl2->hw_stats = priv->hw_stats; 2129d9ba8f9eSMugunthan V N priv_sl2->dma = priv->dma; 2130d9ba8f9eSMugunthan V N priv_sl2->txch = priv->txch; 2131d9ba8f9eSMugunthan V N priv_sl2->rxch = priv->rxch; 2132d9ba8f9eSMugunthan V N priv_sl2->ale = priv->ale; 2133d9ba8f9eSMugunthan V N priv_sl2->emac_port = 1; 2134d9ba8f9eSMugunthan V N priv->slaves[1].ndev = ndev; 2135d9ba8f9eSMugunthan V N priv_sl2->cpts = priv->cpts; 2136d9ba8f9eSMugunthan V N priv_sl2->version = priv->version; 2137d9ba8f9eSMugunthan V N 2138d9ba8f9eSMugunthan V N for (i = 0; i < priv->num_irqs; i++) { 2139d9ba8f9eSMugunthan V N priv_sl2->irqs_table[i] = priv->irqs_table[i]; 2140d9ba8f9eSMugunthan V N priv_sl2->num_irqs = priv->num_irqs; 2141d9ba8f9eSMugunthan V N } 2142f646968fSPatrick McHardy ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER; 2143d9ba8f9eSMugunthan V N 2144d9ba8f9eSMugunthan V N ndev->netdev_ops = &cpsw_netdev_ops; 21457ad24ea4SWilfried Klaebe ndev->ethtool_ops = &cpsw_ethtool_ops; 2146d9ba8f9eSMugunthan V N netif_napi_add(ndev, &priv_sl2->napi, cpsw_poll, CPSW_POLL_WEIGHT); 2147d9ba8f9eSMugunthan V N 2148d9ba8f9eSMugunthan V N /* register the network device */ 2149d9ba8f9eSMugunthan V N SET_NETDEV_DEV(ndev, &pdev->dev); 2150d9ba8f9eSMugunthan V N ret = register_netdev(ndev); 2151d9ba8f9eSMugunthan V N if (ret) { 215288c99ff6SGeorge Cherian dev_err(&pdev->dev, "cpsw: error registering net device\n"); 2153d9ba8f9eSMugunthan V N free_netdev(ndev); 2154d9ba8f9eSMugunthan V N ret = -ENODEV; 2155d9ba8f9eSMugunthan V N } 2156d9ba8f9eSMugunthan V N 2157d9ba8f9eSMugunthan V N return ret; 2158d9ba8f9eSMugunthan V N } 2159d9ba8f9eSMugunthan V N 2160663e12e6SBill Pemberton static int cpsw_probe(struct platform_device *pdev) 2161df828598SMugunthan V N { 2162d1bd9acfSSebastian Siewior struct cpsw_platform_data *data; 2163df828598SMugunthan V N struct net_device *ndev; 2164df828598SMugunthan V N struct cpsw_priv *priv; 2165df828598SMugunthan V N struct cpdma_params dma_params; 2166df828598SMugunthan V N struct cpsw_ale_params ale_params; 2167aa1a15e2SDaniel Mack void __iomem *ss_regs; 2168aa1a15e2SDaniel Mack struct resource *res, *ss_res; 2169549985eeSRichard Cochran u32 slave_offset, sliver_offset, slave_size; 21705087b915SFelipe Balbi int ret = 0, i; 21715087b915SFelipe Balbi int irq; 2172df828598SMugunthan V N 2173df828598SMugunthan V N ndev = alloc_etherdev(sizeof(struct cpsw_priv)); 2174df828598SMugunthan V N if (!ndev) { 217588c99ff6SGeorge Cherian dev_err(&pdev->dev, "error allocating net_device\n"); 2176df828598SMugunthan V N return -ENOMEM; 2177df828598SMugunthan V N } 2178df828598SMugunthan V N 2179df828598SMugunthan V N platform_set_drvdata(pdev, ndev); 2180df828598SMugunthan V N priv = netdev_priv(ndev); 2181df828598SMugunthan V N spin_lock_init(&priv->lock); 2182df828598SMugunthan V N priv->pdev = pdev; 2183df828598SMugunthan V N priv->ndev = ndev; 2184df828598SMugunthan V N priv->dev = &ndev->dev; 2185df828598SMugunthan V N priv->msg_enable = netif_msg_init(debug_level, CPSW_DEBUG); 2186df828598SMugunthan V N priv->rx_packet_max = max(rx_packet_max, 128); 21879232b16dSMugunthan V N priv->cpts = devm_kzalloc(&pdev->dev, sizeof(struct cpts), GFP_KERNEL); 21887dcf313aSMugunthan V N priv->irq_enabled = true; 2189ab8e99d2SSebastian Siewior if (!priv->cpts) { 219088c99ff6SGeorge Cherian dev_err(&pdev->dev, "error allocating cpts\n"); 21914d507dffSMarkus Pargmann ret = -ENOMEM; 21929232b16dSMugunthan V N goto clean_ndev_ret; 21939232b16dSMugunthan V N } 2194df828598SMugunthan V N 21951fb19aa7SVaibhav Hiremath /* 21961fb19aa7SVaibhav Hiremath * This may be required here for child devices. 21971fb19aa7SVaibhav Hiremath */ 21981fb19aa7SVaibhav Hiremath pm_runtime_enable(&pdev->dev); 21991fb19aa7SVaibhav Hiremath 2200739683b4SMugunthan V N /* Select default pin state */ 2201739683b4SMugunthan V N pinctrl_pm_select_default_state(&pdev->dev); 2202739683b4SMugunthan V N 22032eb32b0aSMugunthan V N if (cpsw_probe_dt(&priv->data, pdev)) { 220488c99ff6SGeorge Cherian dev_err(&pdev->dev, "cpsw: platform data missing\n"); 22052eb32b0aSMugunthan V N ret = -ENODEV; 2206aa1a15e2SDaniel Mack goto clean_runtime_disable_ret; 22072eb32b0aSMugunthan V N } 22082eb32b0aSMugunthan V N data = &priv->data; 22092eb32b0aSMugunthan V N 2210df828598SMugunthan V N if (is_valid_ether_addr(data->slave_data[0].mac_addr)) { 2211df828598SMugunthan V N memcpy(priv->mac_addr, data->slave_data[0].mac_addr, ETH_ALEN); 221288c99ff6SGeorge Cherian dev_info(&pdev->dev, "Detected MACID = %pM\n", priv->mac_addr); 2213df828598SMugunthan V N } else { 22147efd26d0SJoe Perches eth_random_addr(priv->mac_addr); 221588c99ff6SGeorge Cherian dev_info(&pdev->dev, "Random MACID = %pM\n", priv->mac_addr); 2216df828598SMugunthan V N } 2217df828598SMugunthan V N 2218df828598SMugunthan V N memcpy(ndev->dev_addr, priv->mac_addr, ETH_ALEN); 2219df828598SMugunthan V N 2220aa1a15e2SDaniel Mack priv->slaves = devm_kzalloc(&pdev->dev, 2221aa1a15e2SDaniel Mack sizeof(struct cpsw_slave) * data->slaves, 2222df828598SMugunthan V N GFP_KERNEL); 2223df828598SMugunthan V N if (!priv->slaves) { 2224aa1a15e2SDaniel Mack ret = -ENOMEM; 2225aa1a15e2SDaniel Mack goto clean_runtime_disable_ret; 2226df828598SMugunthan V N } 2227df828598SMugunthan V N for (i = 0; i < data->slaves; i++) 2228df828598SMugunthan V N priv->slaves[i].slave_num = i; 2229df828598SMugunthan V N 2230d9ba8f9eSMugunthan V N priv->slaves[0].ndev = ndev; 2231d9ba8f9eSMugunthan V N priv->emac_port = 0; 2232d9ba8f9eSMugunthan V N 2233aa1a15e2SDaniel Mack priv->clk = devm_clk_get(&pdev->dev, "fck"); 2234df828598SMugunthan V N if (IS_ERR(priv->clk)) { 2235aa1a15e2SDaniel Mack dev_err(priv->dev, "fck is not found\n"); 2236f150bd7fSMugunthan V N ret = -ENODEV; 2237aa1a15e2SDaniel Mack goto clean_runtime_disable_ret; 2238df828598SMugunthan V N } 2239ff5b8ef2SMugunthan V N priv->coal_intvl = 0; 2240ff5b8ef2SMugunthan V N priv->bus_freq_mhz = clk_get_rate(priv->clk) / 1000000; 2241df828598SMugunthan V N 2242aa1a15e2SDaniel Mack ss_res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2243aa1a15e2SDaniel Mack ss_regs = devm_ioremap_resource(&pdev->dev, ss_res); 2244aa1a15e2SDaniel Mack if (IS_ERR(ss_regs)) { 2245aa1a15e2SDaniel Mack ret = PTR_ERR(ss_regs); 2246aa1a15e2SDaniel Mack goto clean_runtime_disable_ret; 2247df828598SMugunthan V N } 2248549985eeSRichard Cochran priv->regs = ss_regs; 2249549985eeSRichard Cochran priv->host_port = HOST_PORT_NUM; 2250df828598SMugunthan V N 2251f280e89aSMugunthan V N /* Need to enable clocks with runtime PM api to access module 2252f280e89aSMugunthan V N * registers 2253f280e89aSMugunthan V N */ 2254f280e89aSMugunthan V N pm_runtime_get_sync(&pdev->dev); 2255f280e89aSMugunthan V N priv->version = readl(&priv->regs->id_ver); 2256f280e89aSMugunthan V N pm_runtime_put_sync(&pdev->dev); 2257f280e89aSMugunthan V N 2258aa1a15e2SDaniel Mack res = platform_get_resource(pdev, IORESOURCE_MEM, 1); 2259aa1a15e2SDaniel Mack priv->wr_regs = devm_ioremap_resource(&pdev->dev, res); 2260aa1a15e2SDaniel Mack if (IS_ERR(priv->wr_regs)) { 2261aa1a15e2SDaniel Mack ret = PTR_ERR(priv->wr_regs); 2262aa1a15e2SDaniel Mack goto clean_runtime_disable_ret; 2263df828598SMugunthan V N } 2264df828598SMugunthan V N 2265df828598SMugunthan V N memset(&dma_params, 0, sizeof(dma_params)); 2266549985eeSRichard Cochran memset(&ale_params, 0, sizeof(ale_params)); 2267549985eeSRichard Cochran 2268549985eeSRichard Cochran switch (priv->version) { 2269549985eeSRichard Cochran case CPSW_VERSION_1: 2270549985eeSRichard Cochran priv->host_port_regs = ss_regs + CPSW1_HOST_PORT_OFFSET; 22719232b16dSMugunthan V N priv->cpts->reg = ss_regs + CPSW1_CPTS_OFFSET; 2272d9718546SMugunthan V N priv->hw_stats = ss_regs + CPSW1_HW_STATS; 2273549985eeSRichard Cochran dma_params.dmaregs = ss_regs + CPSW1_CPDMA_OFFSET; 2274549985eeSRichard Cochran dma_params.txhdp = ss_regs + CPSW1_STATERAM_OFFSET; 2275549985eeSRichard Cochran ale_params.ale_regs = ss_regs + CPSW1_ALE_OFFSET; 2276549985eeSRichard Cochran slave_offset = CPSW1_SLAVE_OFFSET; 2277549985eeSRichard Cochran slave_size = CPSW1_SLAVE_SIZE; 2278549985eeSRichard Cochran sliver_offset = CPSW1_SLIVER_OFFSET; 2279549985eeSRichard Cochran dma_params.desc_mem_phys = 0; 2280549985eeSRichard Cochran break; 2281549985eeSRichard Cochran case CPSW_VERSION_2: 2282c193f365SMugunthan V N case CPSW_VERSION_3: 2283926489beSMugunthan V N case CPSW_VERSION_4: 2284549985eeSRichard Cochran priv->host_port_regs = ss_regs + CPSW2_HOST_PORT_OFFSET; 22859232b16dSMugunthan V N priv->cpts->reg = ss_regs + CPSW2_CPTS_OFFSET; 2286d9718546SMugunthan V N priv->hw_stats = ss_regs + CPSW2_HW_STATS; 2287549985eeSRichard Cochran dma_params.dmaregs = ss_regs + CPSW2_CPDMA_OFFSET; 2288549985eeSRichard Cochran dma_params.txhdp = ss_regs + CPSW2_STATERAM_OFFSET; 2289549985eeSRichard Cochran ale_params.ale_regs = ss_regs + CPSW2_ALE_OFFSET; 2290549985eeSRichard Cochran slave_offset = CPSW2_SLAVE_OFFSET; 2291549985eeSRichard Cochran slave_size = CPSW2_SLAVE_SIZE; 2292549985eeSRichard Cochran sliver_offset = CPSW2_SLIVER_OFFSET; 2293549985eeSRichard Cochran dma_params.desc_mem_phys = 2294aa1a15e2SDaniel Mack (u32 __force) ss_res->start + CPSW2_BD_OFFSET; 2295549985eeSRichard Cochran break; 2296549985eeSRichard Cochran default: 2297549985eeSRichard Cochran dev_err(priv->dev, "unknown version 0x%08x\n", priv->version); 2298549985eeSRichard Cochran ret = -ENODEV; 2299aa1a15e2SDaniel Mack goto clean_runtime_disable_ret; 2300549985eeSRichard Cochran } 2301549985eeSRichard Cochran for (i = 0; i < priv->data.slaves; i++) { 2302549985eeSRichard Cochran struct cpsw_slave *slave = &priv->slaves[i]; 2303549985eeSRichard Cochran cpsw_slave_init(slave, priv, slave_offset, sliver_offset); 2304549985eeSRichard Cochran slave_offset += slave_size; 2305549985eeSRichard Cochran sliver_offset += SLIVER_SIZE; 2306549985eeSRichard Cochran } 2307549985eeSRichard Cochran 2308df828598SMugunthan V N dma_params.dev = &pdev->dev; 2309549985eeSRichard Cochran dma_params.rxthresh = dma_params.dmaregs + CPDMA_RXTHRESH; 2310549985eeSRichard Cochran dma_params.rxfree = dma_params.dmaregs + CPDMA_RXFREE; 2311549985eeSRichard Cochran dma_params.rxhdp = dma_params.txhdp + CPDMA_RXHDP; 2312549985eeSRichard Cochran dma_params.txcp = dma_params.txhdp + CPDMA_TXCP; 2313549985eeSRichard Cochran dma_params.rxcp = dma_params.txhdp + CPDMA_RXCP; 2314df828598SMugunthan V N 2315df828598SMugunthan V N dma_params.num_chan = data->channels; 2316df828598SMugunthan V N dma_params.has_soft_reset = true; 2317df828598SMugunthan V N dma_params.min_packet_size = CPSW_MIN_PACKET_SIZE; 2318df828598SMugunthan V N dma_params.desc_mem_size = data->bd_ram_size; 2319df828598SMugunthan V N dma_params.desc_align = 16; 2320df828598SMugunthan V N dma_params.has_ext_regs = true; 2321549985eeSRichard Cochran dma_params.desc_hw_addr = dma_params.desc_mem_phys; 2322df828598SMugunthan V N 2323df828598SMugunthan V N priv->dma = cpdma_ctlr_create(&dma_params); 2324df828598SMugunthan V N if (!priv->dma) { 2325df828598SMugunthan V N dev_err(priv->dev, "error initializing dma\n"); 2326df828598SMugunthan V N ret = -ENOMEM; 2327aa1a15e2SDaniel Mack goto clean_runtime_disable_ret; 2328df828598SMugunthan V N } 2329df828598SMugunthan V N 2330df828598SMugunthan V N priv->txch = cpdma_chan_create(priv->dma, tx_chan_num(0), 2331df828598SMugunthan V N cpsw_tx_handler); 2332df828598SMugunthan V N priv->rxch = cpdma_chan_create(priv->dma, rx_chan_num(0), 2333df828598SMugunthan V N cpsw_rx_handler); 2334df828598SMugunthan V N 2335df828598SMugunthan V N if (WARN_ON(!priv->txch || !priv->rxch)) { 2336df828598SMugunthan V N dev_err(priv->dev, "error initializing dma channels\n"); 2337df828598SMugunthan V N ret = -ENOMEM; 2338df828598SMugunthan V N goto clean_dma_ret; 2339df828598SMugunthan V N } 2340df828598SMugunthan V N 2341df828598SMugunthan V N ale_params.dev = &ndev->dev; 2342df828598SMugunthan V N ale_params.ale_ageout = ale_ageout; 2343df828598SMugunthan V N ale_params.ale_entries = data->ale_entries; 2344df828598SMugunthan V N ale_params.ale_ports = data->slaves; 2345df828598SMugunthan V N 2346df828598SMugunthan V N priv->ale = cpsw_ale_create(&ale_params); 2347df828598SMugunthan V N if (!priv->ale) { 2348df828598SMugunthan V N dev_err(priv->dev, "error initializing ale engine\n"); 2349df828598SMugunthan V N ret = -ENODEV; 2350df828598SMugunthan V N goto clean_dma_ret; 2351df828598SMugunthan V N } 2352df828598SMugunthan V N 2353c03abd84SFelipe Balbi ndev->irq = platform_get_irq(pdev, 1); 2354df828598SMugunthan V N if (ndev->irq < 0) { 2355df828598SMugunthan V N dev_err(priv->dev, "error getting irq resource\n"); 2356df828598SMugunthan V N ret = -ENOENT; 2357df828598SMugunthan V N goto clean_ale_ret; 2358df828598SMugunthan V N } 2359df828598SMugunthan V N 2360c03abd84SFelipe Balbi /* Grab RX and TX IRQs. Note that we also have RX_THRESHOLD and 2361c03abd84SFelipe Balbi * MISC IRQs which are always kept disabled with this driver so 2362c03abd84SFelipe Balbi * we will not request them. 2363c03abd84SFelipe Balbi * 2364c03abd84SFelipe Balbi * If anyone wants to implement support for those, make sure to 2365c03abd84SFelipe Balbi * first request and append them to irqs_table array. 2366c03abd84SFelipe Balbi */ 2367c2b32e58SDaniel Mack 2368c03abd84SFelipe Balbi /* RX IRQ */ 23695087b915SFelipe Balbi irq = platform_get_irq(pdev, 1); 23705087b915SFelipe Balbi if (irq < 0) 23715087b915SFelipe Balbi goto clean_ale_ret; 23725087b915SFelipe Balbi 2373c03abd84SFelipe Balbi priv->irqs_table[0] = irq; 2374c03abd84SFelipe Balbi ret = devm_request_irq(&pdev->dev, irq, cpsw_rx_interrupt, 23755087b915SFelipe Balbi 0, dev_name(&pdev->dev), priv); 23765087b915SFelipe Balbi if (ret < 0) { 23775087b915SFelipe Balbi dev_err(priv->dev, "error attaching irq (%d)\n", ret); 23785087b915SFelipe Balbi goto clean_ale_ret; 2379df828598SMugunthan V N } 2380df828598SMugunthan V N 2381c03abd84SFelipe Balbi /* TX IRQ */ 23825087b915SFelipe Balbi irq = platform_get_irq(pdev, 2); 23835087b915SFelipe Balbi if (irq < 0) 23845087b915SFelipe Balbi goto clean_ale_ret; 23855087b915SFelipe Balbi 2386c03abd84SFelipe Balbi priv->irqs_table[1] = irq; 2387c03abd84SFelipe Balbi ret = devm_request_irq(&pdev->dev, irq, cpsw_tx_interrupt, 23885087b915SFelipe Balbi 0, dev_name(&pdev->dev), priv); 23895087b915SFelipe Balbi if (ret < 0) { 23905087b915SFelipe Balbi dev_err(priv->dev, "error attaching irq (%d)\n", ret); 23915087b915SFelipe Balbi goto clean_ale_ret; 23925087b915SFelipe Balbi } 2393c03abd84SFelipe Balbi priv->num_irqs = 2; 2394c2b32e58SDaniel Mack 2395f646968fSPatrick McHardy ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER; 2396df828598SMugunthan V N 2397df828598SMugunthan V N ndev->netdev_ops = &cpsw_netdev_ops; 23987ad24ea4SWilfried Klaebe ndev->ethtool_ops = &cpsw_ethtool_ops; 2399df828598SMugunthan V N netif_napi_add(ndev, &priv->napi, cpsw_poll, CPSW_POLL_WEIGHT); 2400df828598SMugunthan V N 2401df828598SMugunthan V N /* register the network device */ 2402df828598SMugunthan V N SET_NETDEV_DEV(ndev, &pdev->dev); 2403df828598SMugunthan V N ret = register_netdev(ndev); 2404df828598SMugunthan V N if (ret) { 2405df828598SMugunthan V N dev_err(priv->dev, "error registering net device\n"); 2406df828598SMugunthan V N ret = -ENODEV; 2407aa1a15e2SDaniel Mack goto clean_ale_ret; 2408df828598SMugunthan V N } 2409df828598SMugunthan V N 24101a3b5056SOlof Johansson cpsw_notice(priv, probe, "initialized device (regs %pa, irq %d)\n", 24111a3b5056SOlof Johansson &ss_res->start, ndev->irq); 2412df828598SMugunthan V N 2413d9ba8f9eSMugunthan V N if (priv->data.dual_emac) { 2414d9ba8f9eSMugunthan V N ret = cpsw_probe_dual_emac(pdev, priv); 2415d9ba8f9eSMugunthan V N if (ret) { 2416d9ba8f9eSMugunthan V N cpsw_err(priv, probe, "error probe slave 2 emac interface\n"); 2417aa1a15e2SDaniel Mack goto clean_ale_ret; 2418d9ba8f9eSMugunthan V N } 2419d9ba8f9eSMugunthan V N } 2420d9ba8f9eSMugunthan V N 2421df828598SMugunthan V N return 0; 2422df828598SMugunthan V N 2423df828598SMugunthan V N clean_ale_ret: 2424df828598SMugunthan V N cpsw_ale_destroy(priv->ale); 2425df828598SMugunthan V N clean_dma_ret: 2426df828598SMugunthan V N cpdma_chan_destroy(priv->txch); 2427df828598SMugunthan V N cpdma_chan_destroy(priv->rxch); 2428df828598SMugunthan V N cpdma_ctlr_destroy(priv->dma); 2429aa1a15e2SDaniel Mack clean_runtime_disable_ret: 2430f150bd7fSMugunthan V N pm_runtime_disable(&pdev->dev); 2431df828598SMugunthan V N clean_ndev_ret: 2432d1bd9acfSSebastian Siewior free_netdev(priv->ndev); 2433df828598SMugunthan V N return ret; 2434df828598SMugunthan V N } 2435df828598SMugunthan V N 2436030b16a0SMugunthan V N static int cpsw_remove_child_device(struct device *dev, void *c) 2437030b16a0SMugunthan V N { 2438030b16a0SMugunthan V N struct platform_device *pdev = to_platform_device(dev); 2439030b16a0SMugunthan V N 2440030b16a0SMugunthan V N of_device_unregister(pdev); 2441030b16a0SMugunthan V N 2442030b16a0SMugunthan V N return 0; 2443030b16a0SMugunthan V N } 2444030b16a0SMugunthan V N 2445663e12e6SBill Pemberton static int cpsw_remove(struct platform_device *pdev) 2446df828598SMugunthan V N { 2447df828598SMugunthan V N struct net_device *ndev = platform_get_drvdata(pdev); 2448df828598SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 2449df828598SMugunthan V N 2450d1bd9acfSSebastian Siewior if (priv->data.dual_emac) 2451d1bd9acfSSebastian Siewior unregister_netdev(cpsw_get_slave_ndev(priv, 1)); 2452d1bd9acfSSebastian Siewior unregister_netdev(ndev); 2453df828598SMugunthan V N 2454df828598SMugunthan V N cpsw_ale_destroy(priv->ale); 2455df828598SMugunthan V N cpdma_chan_destroy(priv->txch); 2456df828598SMugunthan V N cpdma_chan_destroy(priv->rxch); 2457df828598SMugunthan V N cpdma_ctlr_destroy(priv->dma); 2458f150bd7fSMugunthan V N pm_runtime_disable(&pdev->dev); 2459030b16a0SMugunthan V N device_for_each_child(&pdev->dev, NULL, cpsw_remove_child_device); 2460d1bd9acfSSebastian Siewior if (priv->data.dual_emac) 2461d1bd9acfSSebastian Siewior free_netdev(cpsw_get_slave_ndev(priv, 1)); 2462df828598SMugunthan V N free_netdev(ndev); 2463df828598SMugunthan V N return 0; 2464df828598SMugunthan V N } 2465df828598SMugunthan V N 24668963a504SGrygorii Strashko #ifdef CONFIG_PM_SLEEP 2467df828598SMugunthan V N static int cpsw_suspend(struct device *dev) 2468df828598SMugunthan V N { 2469df828598SMugunthan V N struct platform_device *pdev = to_platform_device(dev); 2470df828598SMugunthan V N struct net_device *ndev = platform_get_drvdata(pdev); 2471b90fc27aSMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 2472df828598SMugunthan V N 2473618073e3SMugunthan V N if (priv->data.dual_emac) { 2474618073e3SMugunthan V N int i; 2475618073e3SMugunthan V N 2476618073e3SMugunthan V N for (i = 0; i < priv->data.slaves; i++) { 2477618073e3SMugunthan V N if (netif_running(priv->slaves[i].ndev)) 2478618073e3SMugunthan V N cpsw_ndo_stop(priv->slaves[i].ndev); 2479618073e3SMugunthan V N soft_reset_slave(priv->slaves + i); 2480618073e3SMugunthan V N } 2481618073e3SMugunthan V N } else { 2482df828598SMugunthan V N if (netif_running(ndev)) 2483df828598SMugunthan V N cpsw_ndo_stop(ndev); 24841e7a2e21SDaniel Mack for_each_slave(priv, soft_reset_slave); 2485618073e3SMugunthan V N } 24861e7a2e21SDaniel Mack 2487f150bd7fSMugunthan V N pm_runtime_put_sync(&pdev->dev); 2488f150bd7fSMugunthan V N 2489739683b4SMugunthan V N /* Select sleep pin state */ 2490739683b4SMugunthan V N pinctrl_pm_select_sleep_state(&pdev->dev); 2491739683b4SMugunthan V N 2492df828598SMugunthan V N return 0; 2493df828598SMugunthan V N } 2494df828598SMugunthan V N 2495df828598SMugunthan V N static int cpsw_resume(struct device *dev) 2496df828598SMugunthan V N { 2497df828598SMugunthan V N struct platform_device *pdev = to_platform_device(dev); 2498df828598SMugunthan V N struct net_device *ndev = platform_get_drvdata(pdev); 2499618073e3SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 2500df828598SMugunthan V N 2501f150bd7fSMugunthan V N pm_runtime_get_sync(&pdev->dev); 2502739683b4SMugunthan V N 2503739683b4SMugunthan V N /* Select default pin state */ 2504739683b4SMugunthan V N pinctrl_pm_select_default_state(&pdev->dev); 2505739683b4SMugunthan V N 2506618073e3SMugunthan V N if (priv->data.dual_emac) { 2507618073e3SMugunthan V N int i; 2508618073e3SMugunthan V N 2509618073e3SMugunthan V N for (i = 0; i < priv->data.slaves; i++) { 2510618073e3SMugunthan V N if (netif_running(priv->slaves[i].ndev)) 2511618073e3SMugunthan V N cpsw_ndo_open(priv->slaves[i].ndev); 2512618073e3SMugunthan V N } 2513618073e3SMugunthan V N } else { 2514df828598SMugunthan V N if (netif_running(ndev)) 2515df828598SMugunthan V N cpsw_ndo_open(ndev); 2516618073e3SMugunthan V N } 2517df828598SMugunthan V N return 0; 2518df828598SMugunthan V N } 25198963a504SGrygorii Strashko #endif 2520df828598SMugunthan V N 25218963a504SGrygorii Strashko static SIMPLE_DEV_PM_OPS(cpsw_pm_ops, cpsw_suspend, cpsw_resume); 2522df828598SMugunthan V N 25232eb32b0aSMugunthan V N static const struct of_device_id cpsw_of_mtable[] = { 25242eb32b0aSMugunthan V N { .compatible = "ti,cpsw", }, 25252eb32b0aSMugunthan V N { /* sentinel */ }, 25262eb32b0aSMugunthan V N }; 25274bc21d41SSebastian Siewior MODULE_DEVICE_TABLE(of, cpsw_of_mtable); 25282eb32b0aSMugunthan V N 2529df828598SMugunthan V N static struct platform_driver cpsw_driver = { 2530df828598SMugunthan V N .driver = { 2531df828598SMugunthan V N .name = "cpsw", 2532df828598SMugunthan V N .pm = &cpsw_pm_ops, 25331e5c76d4SSachin Kamat .of_match_table = cpsw_of_mtable, 2534df828598SMugunthan V N }, 2535df828598SMugunthan V N .probe = cpsw_probe, 2536663e12e6SBill Pemberton .remove = cpsw_remove, 2537df828598SMugunthan V N }; 2538df828598SMugunthan V N 2539df828598SMugunthan V N static int __init cpsw_init(void) 2540df828598SMugunthan V N { 2541df828598SMugunthan V N return platform_driver_register(&cpsw_driver); 2542df828598SMugunthan V N } 2543df828598SMugunthan V N late_initcall(cpsw_init); 2544df828598SMugunthan V N 2545df828598SMugunthan V N static void __exit cpsw_exit(void) 2546df828598SMugunthan V N { 2547df828598SMugunthan V N platform_driver_unregister(&cpsw_driver); 2548df828598SMugunthan V N } 2549df828598SMugunthan V N module_exit(cpsw_exit); 2550df828598SMugunthan V N 2551df828598SMugunthan V N MODULE_LICENSE("GPL"); 2552df828598SMugunthan V N MODULE_AUTHOR("Cyril Chemparathy <cyril@ti.com>"); 2553df828598SMugunthan V N MODULE_AUTHOR("Mugunthan V N <mugunthanvnm@ti.com>"); 2554df828598SMugunthan V N MODULE_DESCRIPTION("TI CPSW Ethernet driver"); 2555