1df828598SMugunthan V N /* 2df828598SMugunthan V N * Texas Instruments Ethernet Switch Driver 3df828598SMugunthan V N * 4df828598SMugunthan V N * Copyright (C) 2012 Texas Instruments 5df828598SMugunthan V N * 6df828598SMugunthan V N * This program is free software; you can redistribute it and/or 7df828598SMugunthan V N * modify it under the terms of the GNU General Public License as 8df828598SMugunthan V N * published by the Free Software Foundation version 2. 9df828598SMugunthan V N * 10df828598SMugunthan V N * This program is distributed "as is" WITHOUT ANY WARRANTY of any 11df828598SMugunthan V N * kind, whether express or implied; without even the implied warranty 12df828598SMugunthan V N * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13df828598SMugunthan V N * GNU General Public License for more details. 14df828598SMugunthan V N */ 15df828598SMugunthan V N 16df828598SMugunthan V N #include <linux/kernel.h> 17df828598SMugunthan V N #include <linux/io.h> 18df828598SMugunthan V N #include <linux/clk.h> 19df828598SMugunthan V N #include <linux/timer.h> 20df828598SMugunthan V N #include <linux/module.h> 21df828598SMugunthan V N #include <linux/platform_device.h> 22df828598SMugunthan V N #include <linux/irqreturn.h> 23df828598SMugunthan V N #include <linux/interrupt.h> 24df828598SMugunthan V N #include <linux/if_ether.h> 25df828598SMugunthan V N #include <linux/etherdevice.h> 26df828598SMugunthan V N #include <linux/netdevice.h> 272e5b38abSRichard Cochran #include <linux/net_tstamp.h> 28df828598SMugunthan V N #include <linux/phy.h> 29df828598SMugunthan V N #include <linux/workqueue.h> 30df828598SMugunthan V N #include <linux/delay.h> 31f150bd7fSMugunthan V N #include <linux/pm_runtime.h> 32e2b3e493SArnd Bergmann #include <linux/gpio/consumer.h> 332eb32b0aSMugunthan V N #include <linux/of.h> 349e42f715SHeiko Schocher #include <linux/of_mdio.h> 352eb32b0aSMugunthan V N #include <linux/of_net.h> 362eb32b0aSMugunthan V N #include <linux/of_device.h> 373b72c2feSMugunthan V N #include <linux/if_vlan.h> 38514c6032SRandy Dunlap #include <linux/kmemleak.h> 399611d6d6SIvan Khoronzhuk #include <linux/sys_soc.h> 40df828598SMugunthan V N 41739683b4SMugunthan V N #include <linux/pinctrl/consumer.h> 427929a668SIvan Khoronzhuk #include <net/pkt_cls.h> 43df828598SMugunthan V N 44dbe34724SMugunthan V N #include "cpsw.h" 45df828598SMugunthan V N #include "cpsw_ale.h" 462e5b38abSRichard Cochran #include "cpts.h" 47df828598SMugunthan V N #include "davinci_cpdma.h" 48df828598SMugunthan V N 4957d90148SIvan Khoronzhuk #include <net/pkt_sched.h> 5057d90148SIvan Khoronzhuk 51df828598SMugunthan V N #define CPSW_DEBUG (NETIF_MSG_HW | NETIF_MSG_WOL | \ 52df828598SMugunthan V N NETIF_MSG_DRV | NETIF_MSG_LINK | \ 53df828598SMugunthan V N NETIF_MSG_IFUP | NETIF_MSG_INTR | \ 54df828598SMugunthan V N NETIF_MSG_PROBE | NETIF_MSG_TIMER | \ 55df828598SMugunthan V N NETIF_MSG_IFDOWN | NETIF_MSG_RX_ERR | \ 56df828598SMugunthan V N NETIF_MSG_TX_ERR | NETIF_MSG_TX_DONE | \ 57df828598SMugunthan V N NETIF_MSG_PKTDATA | NETIF_MSG_TX_QUEUED | \ 58df828598SMugunthan V N NETIF_MSG_RX_STATUS) 59df828598SMugunthan V N 60df828598SMugunthan V N #define cpsw_info(priv, type, format, ...) \ 61df828598SMugunthan V N do { \ 62df828598SMugunthan V N if (netif_msg_##type(priv) && net_ratelimit()) \ 63df828598SMugunthan V N dev_info(priv->dev, format, ## __VA_ARGS__); \ 64df828598SMugunthan V N } while (0) 65df828598SMugunthan V N 66df828598SMugunthan V N #define cpsw_err(priv, type, format, ...) \ 67df828598SMugunthan V N do { \ 68df828598SMugunthan V N if (netif_msg_##type(priv) && net_ratelimit()) \ 69df828598SMugunthan V N dev_err(priv->dev, format, ## __VA_ARGS__); \ 70df828598SMugunthan V N } while (0) 71df828598SMugunthan V N 72df828598SMugunthan V N #define cpsw_dbg(priv, type, format, ...) \ 73df828598SMugunthan V N do { \ 74df828598SMugunthan V N if (netif_msg_##type(priv) && net_ratelimit()) \ 75df828598SMugunthan V N dev_dbg(priv->dev, format, ## __VA_ARGS__); \ 76df828598SMugunthan V N } while (0) 77df828598SMugunthan V N 78df828598SMugunthan V N #define cpsw_notice(priv, type, format, ...) \ 79df828598SMugunthan V N do { \ 80df828598SMugunthan V N if (netif_msg_##type(priv) && net_ratelimit()) \ 81df828598SMugunthan V N dev_notice(priv->dev, format, ## __VA_ARGS__); \ 82df828598SMugunthan V N } while (0) 83df828598SMugunthan V N 845c50a856SMugunthan V N #define ALE_ALL_PORTS 0x7 855c50a856SMugunthan V N 86df828598SMugunthan V N #define CPSW_MAJOR_VERSION(reg) (reg >> 8 & 0x7) 87df828598SMugunthan V N #define CPSW_MINOR_VERSION(reg) (reg & 0xff) 88df828598SMugunthan V N #define CPSW_RTL_VERSION(reg) ((reg >> 11) & 0x1f) 89df828598SMugunthan V N 90e90cfac6SRichard Cochran #define CPSW_VERSION_1 0x19010a 91e90cfac6SRichard Cochran #define CPSW_VERSION_2 0x19010c 92c193f365SMugunthan V N #define CPSW_VERSION_3 0x19010f 93926489beSMugunthan V N #define CPSW_VERSION_4 0x190112 94549985eeSRichard Cochran 95549985eeSRichard Cochran #define HOST_PORT_NUM 0 96c6395f12SGrygorii Strashko #define CPSW_ALE_PORTS_NUM 3 97549985eeSRichard Cochran #define SLIVER_SIZE 0x40 98549985eeSRichard Cochran 99549985eeSRichard Cochran #define CPSW1_HOST_PORT_OFFSET 0x028 100549985eeSRichard Cochran #define CPSW1_SLAVE_OFFSET 0x050 101549985eeSRichard Cochran #define CPSW1_SLAVE_SIZE 0x040 102549985eeSRichard Cochran #define CPSW1_CPDMA_OFFSET 0x100 103549985eeSRichard Cochran #define CPSW1_STATERAM_OFFSET 0x200 104d9718546SMugunthan V N #define CPSW1_HW_STATS 0x400 105549985eeSRichard Cochran #define CPSW1_CPTS_OFFSET 0x500 106549985eeSRichard Cochran #define CPSW1_ALE_OFFSET 0x600 107549985eeSRichard Cochran #define CPSW1_SLIVER_OFFSET 0x700 108549985eeSRichard Cochran 109549985eeSRichard Cochran #define CPSW2_HOST_PORT_OFFSET 0x108 110549985eeSRichard Cochran #define CPSW2_SLAVE_OFFSET 0x200 111549985eeSRichard Cochran #define CPSW2_SLAVE_SIZE 0x100 112549985eeSRichard Cochran #define CPSW2_CPDMA_OFFSET 0x800 113d9718546SMugunthan V N #define CPSW2_HW_STATS 0x900 114549985eeSRichard Cochran #define CPSW2_STATERAM_OFFSET 0xa00 115549985eeSRichard Cochran #define CPSW2_CPTS_OFFSET 0xc00 116549985eeSRichard Cochran #define CPSW2_ALE_OFFSET 0xd00 117549985eeSRichard Cochran #define CPSW2_SLIVER_OFFSET 0xd80 118549985eeSRichard Cochran #define CPSW2_BD_OFFSET 0x2000 119549985eeSRichard Cochran 120df828598SMugunthan V N #define CPDMA_RXTHRESH 0x0c0 121df828598SMugunthan V N #define CPDMA_RXFREE 0x0e0 122df828598SMugunthan V N #define CPDMA_TXHDP 0x00 123df828598SMugunthan V N #define CPDMA_RXHDP 0x20 124df828598SMugunthan V N #define CPDMA_TXCP 0x40 125df828598SMugunthan V N #define CPDMA_RXCP 0x60 126df828598SMugunthan V N 127df828598SMugunthan V N #define CPSW_POLL_WEIGHT 64 128a3a41d2fSGrygorii Strashko #define CPSW_RX_VLAN_ENCAP_HDR_SIZE 4 1299421c901SGrygorii Strashko #define CPSW_MIN_PACKET_SIZE (VLAN_ETH_ZLEN) 130a3a41d2fSGrygorii Strashko #define CPSW_MAX_PACKET_SIZE (VLAN_ETH_FRAME_LEN +\ 131a3a41d2fSGrygorii Strashko ETH_FCS_LEN +\ 132a3a41d2fSGrygorii Strashko CPSW_RX_VLAN_ENCAP_HDR_SIZE) 133df828598SMugunthan V N 134df828598SMugunthan V N #define RX_PRIORITY_MAPPING 0x76543210 135df828598SMugunthan V N #define TX_PRIORITY_MAPPING 0x33221100 1365e391dc5SIvan Khoronzhuk #define CPDMA_TX_PRIORITY_MAP 0x76543210 137df828598SMugunthan V N 1383b72c2feSMugunthan V N #define CPSW_VLAN_AWARE BIT(1) 139a3a41d2fSGrygorii Strashko #define CPSW_RX_VLAN_ENCAP BIT(2) 1403b72c2feSMugunthan V N #define CPSW_ALE_VLAN_AWARE 1 1413b72c2feSMugunthan V N 14235717d8dSJohn Ogness #define CPSW_FIFO_NORMAL_MODE (0 << 16) 14335717d8dSJohn Ogness #define CPSW_FIFO_DUAL_MAC_MODE (1 << 16) 14435717d8dSJohn Ogness #define CPSW_FIFO_RATE_LIMIT_MODE (2 << 16) 145d9ba8f9eSMugunthan V N 146ff5b8ef2SMugunthan V N #define CPSW_INTPACEEN (0x3f << 16) 147ff5b8ef2SMugunthan V N #define CPSW_INTPRESCALE_MASK (0x7FF << 0) 148ff5b8ef2SMugunthan V N #define CPSW_CMINTMAX_CNT 63 149ff5b8ef2SMugunthan V N #define CPSW_CMINTMIN_CNT 2 150ff5b8ef2SMugunthan V N #define CPSW_CMINTMAX_INTVL (1000 / CPSW_CMINTMIN_CNT) 151ff5b8ef2SMugunthan V N #define CPSW_CMINTMIN_INTVL ((1000 / CPSW_CMINTMAX_CNT) + 1) 152ff5b8ef2SMugunthan V N 153606f3993SIvan Khoronzhuk #define cpsw_slave_index(cpsw, priv) \ 154606f3993SIvan Khoronzhuk ((cpsw->data.dual_emac) ? priv->emac_port : \ 155606f3993SIvan Khoronzhuk cpsw->data.active_slave) 156e38b5a3dSIvan Khoronzhuk #define IRQ_NUM 2 157e05107e6SIvan Khoronzhuk #define CPSW_MAX_QUEUES 8 15890225bf0SGrygorii Strashko #define CPSW_CPDMA_DESCS_POOL_SIZE_DEFAULT 256 15957d90148SIvan Khoronzhuk #define CPSW_FIFO_QUEUE_TYPE_SHIFT 16 16057d90148SIvan Khoronzhuk #define CPSW_FIFO_SHAPE_EN_SHIFT 16 16157d90148SIvan Khoronzhuk #define CPSW_FIFO_RATE_EN_SHIFT 20 1627929a668SIvan Khoronzhuk #define CPSW_TC_NUM 4 1637929a668SIvan Khoronzhuk #define CPSW_FIFO_SHAPERS_NUM (CPSW_TC_NUM - 1) 16457d90148SIvan Khoronzhuk #define CPSW_PCT_MASK 0x7f 165d3bb9c58SMugunthan V N 166a3a41d2fSGrygorii Strashko #define CPSW_RX_VLAN_ENCAP_HDR_PRIO_SHIFT 29 167a3a41d2fSGrygorii Strashko #define CPSW_RX_VLAN_ENCAP_HDR_PRIO_MSK GENMASK(2, 0) 168a3a41d2fSGrygorii Strashko #define CPSW_RX_VLAN_ENCAP_HDR_VID_SHIFT 16 169a3a41d2fSGrygorii Strashko #define CPSW_RX_VLAN_ENCAP_HDR_PKT_TYPE_SHIFT 8 170a3a41d2fSGrygorii Strashko #define CPSW_RX_VLAN_ENCAP_HDR_PKT_TYPE_MSK GENMASK(1, 0) 171a3a41d2fSGrygorii Strashko enum { 172a3a41d2fSGrygorii Strashko CPSW_RX_VLAN_ENCAP_HDR_PKT_VLAN_TAG = 0, 173a3a41d2fSGrygorii Strashko CPSW_RX_VLAN_ENCAP_HDR_PKT_RESERV, 174a3a41d2fSGrygorii Strashko CPSW_RX_VLAN_ENCAP_HDR_PKT_PRIO_TAG, 175a3a41d2fSGrygorii Strashko CPSW_RX_VLAN_ENCAP_HDR_PKT_UNTAG, 176a3a41d2fSGrygorii Strashko }; 177a3a41d2fSGrygorii Strashko 178df828598SMugunthan V N static int debug_level; 179df828598SMugunthan V N module_param(debug_level, int, 0); 180df828598SMugunthan V N MODULE_PARM_DESC(debug_level, "cpsw debug level (NETIF_MSG bits)"); 181df828598SMugunthan V N 182df828598SMugunthan V N static int ale_ageout = 10; 183df828598SMugunthan V N module_param(ale_ageout, int, 0); 184df828598SMugunthan V N MODULE_PARM_DESC(ale_ageout, "cpsw ale ageout interval (seconds)"); 185df828598SMugunthan V N 186df828598SMugunthan V N static int rx_packet_max = CPSW_MAX_PACKET_SIZE; 187df828598SMugunthan V N module_param(rx_packet_max, int, 0); 188df828598SMugunthan V N MODULE_PARM_DESC(rx_packet_max, "maximum receive packet size (bytes)"); 189df828598SMugunthan V N 19090225bf0SGrygorii Strashko static int descs_pool_size = CPSW_CPDMA_DESCS_POOL_SIZE_DEFAULT; 19190225bf0SGrygorii Strashko module_param(descs_pool_size, int, 0444); 19290225bf0SGrygorii Strashko MODULE_PARM_DESC(descs_pool_size, "Number of CPDMA CPPI descriptors in pool"); 19390225bf0SGrygorii Strashko 194996a5c27SRichard Cochran struct cpsw_wr_regs { 195df828598SMugunthan V N u32 id_ver; 196df828598SMugunthan V N u32 soft_reset; 197df828598SMugunthan V N u32 control; 198df828598SMugunthan V N u32 int_control; 199df828598SMugunthan V N u32 rx_thresh_en; 200df828598SMugunthan V N u32 rx_en; 201df828598SMugunthan V N u32 tx_en; 202df828598SMugunthan V N u32 misc_en; 203ff5b8ef2SMugunthan V N u32 mem_allign1[8]; 204ff5b8ef2SMugunthan V N u32 rx_thresh_stat; 205ff5b8ef2SMugunthan V N u32 rx_stat; 206ff5b8ef2SMugunthan V N u32 tx_stat; 207ff5b8ef2SMugunthan V N u32 misc_stat; 208ff5b8ef2SMugunthan V N u32 mem_allign2[8]; 209ff5b8ef2SMugunthan V N u32 rx_imax; 210ff5b8ef2SMugunthan V N u32 tx_imax; 211ff5b8ef2SMugunthan V N 212df828598SMugunthan V N }; 213df828598SMugunthan V N 214996a5c27SRichard Cochran struct cpsw_ss_regs { 215df828598SMugunthan V N u32 id_ver; 216df828598SMugunthan V N u32 control; 217df828598SMugunthan V N u32 soft_reset; 218df828598SMugunthan V N u32 stat_port_en; 219df828598SMugunthan V N u32 ptype; 220bd357af2SRichard Cochran u32 soft_idle; 221bd357af2SRichard Cochran u32 thru_rate; 222bd357af2SRichard Cochran u32 gap_thresh; 223bd357af2SRichard Cochran u32 tx_start_wds; 224bd357af2SRichard Cochran u32 flow_control; 225bd357af2SRichard Cochran u32 vlan_ltype; 226bd357af2SRichard Cochran u32 ts_ltype; 227bd357af2SRichard Cochran u32 dlr_ltype; 228df828598SMugunthan V N }; 229df828598SMugunthan V N 2309750a3adSRichard Cochran /* CPSW_PORT_V1 */ 2319750a3adSRichard Cochran #define CPSW1_MAX_BLKS 0x00 /* Maximum FIFO Blocks */ 2329750a3adSRichard Cochran #define CPSW1_BLK_CNT 0x04 /* FIFO Block Usage Count (Read Only) */ 2339750a3adSRichard Cochran #define CPSW1_TX_IN_CTL 0x08 /* Transmit FIFO Control */ 2349750a3adSRichard Cochran #define CPSW1_PORT_VLAN 0x0c /* VLAN Register */ 2359750a3adSRichard Cochran #define CPSW1_TX_PRI_MAP 0x10 /* Tx Header Priority to Switch Pri Mapping */ 2369750a3adSRichard Cochran #define CPSW1_TS_CTL 0x14 /* Time Sync Control */ 2379750a3adSRichard Cochran #define CPSW1_TS_SEQ_LTYPE 0x18 /* Time Sync Sequence ID Offset and Msg Type */ 2389750a3adSRichard Cochran #define CPSW1_TS_VLAN 0x1c /* Time Sync VLAN1 and VLAN2 */ 2399750a3adSRichard Cochran 2409750a3adSRichard Cochran /* CPSW_PORT_V2 */ 2419750a3adSRichard Cochran #define CPSW2_CONTROL 0x00 /* Control Register */ 2429750a3adSRichard Cochran #define CPSW2_MAX_BLKS 0x08 /* Maximum FIFO Blocks */ 2439750a3adSRichard Cochran #define CPSW2_BLK_CNT 0x0c /* FIFO Block Usage Count (Read Only) */ 2449750a3adSRichard Cochran #define CPSW2_TX_IN_CTL 0x10 /* Transmit FIFO Control */ 2459750a3adSRichard Cochran #define CPSW2_PORT_VLAN 0x14 /* VLAN Register */ 2469750a3adSRichard Cochran #define CPSW2_TX_PRI_MAP 0x18 /* Tx Header Priority to Switch Pri Mapping */ 2479750a3adSRichard Cochran #define CPSW2_TS_SEQ_MTYPE 0x1c /* Time Sync Sequence ID Offset and Msg Type */ 2489750a3adSRichard Cochran 2499750a3adSRichard Cochran /* CPSW_PORT_V1 and V2 */ 2509750a3adSRichard Cochran #define SA_LO 0x20 /* CPGMAC_SL Source Address Low */ 2519750a3adSRichard Cochran #define SA_HI 0x24 /* CPGMAC_SL Source Address High */ 2529750a3adSRichard Cochran #define SEND_PERCENT 0x28 /* Transmit Queue Send Percentages */ 2539750a3adSRichard Cochran 2549750a3adSRichard Cochran /* CPSW_PORT_V2 only */ 2559750a3adSRichard Cochran #define RX_DSCP_PRI_MAP0 0x30 /* Rx DSCP Priority to Rx Packet Mapping */ 2569750a3adSRichard Cochran #define RX_DSCP_PRI_MAP1 0x34 /* Rx DSCP Priority to Rx Packet Mapping */ 2579750a3adSRichard Cochran #define RX_DSCP_PRI_MAP2 0x38 /* Rx DSCP Priority to Rx Packet Mapping */ 2589750a3adSRichard Cochran #define RX_DSCP_PRI_MAP3 0x3c /* Rx DSCP Priority to Rx Packet Mapping */ 2599750a3adSRichard Cochran #define RX_DSCP_PRI_MAP4 0x40 /* Rx DSCP Priority to Rx Packet Mapping */ 2609750a3adSRichard Cochran #define RX_DSCP_PRI_MAP5 0x44 /* Rx DSCP Priority to Rx Packet Mapping */ 2619750a3adSRichard Cochran #define RX_DSCP_PRI_MAP6 0x48 /* Rx DSCP Priority to Rx Packet Mapping */ 2629750a3adSRichard Cochran #define RX_DSCP_PRI_MAP7 0x4c /* Rx DSCP Priority to Rx Packet Mapping */ 2639750a3adSRichard Cochran 2649750a3adSRichard Cochran /* Bit definitions for the CPSW2_CONTROL register */ 2651239a96aSIvan Khoronzhuk #define PASS_PRI_TAGGED BIT(24) /* Pass Priority Tagged */ 2661239a96aSIvan Khoronzhuk #define VLAN_LTYPE2_EN BIT(21) /* VLAN LTYPE 2 enable */ 2671239a96aSIvan Khoronzhuk #define VLAN_LTYPE1_EN BIT(20) /* VLAN LTYPE 1 enable */ 2681239a96aSIvan Khoronzhuk #define DSCP_PRI_EN BIT(16) /* DSCP Priority Enable */ 2691c0e8123SIvan Khoronzhuk #define TS_107 BIT(15) /* Tyme Sync Dest IP Address 107 */ 2701239a96aSIvan Khoronzhuk #define TS_320 BIT(14) /* Time Sync Dest Port 320 enable */ 2711239a96aSIvan Khoronzhuk #define TS_319 BIT(13) /* Time Sync Dest Port 319 enable */ 2721239a96aSIvan Khoronzhuk #define TS_132 BIT(12) /* Time Sync Dest IP Addr 132 enable */ 2731239a96aSIvan Khoronzhuk #define TS_131 BIT(11) /* Time Sync Dest IP Addr 131 enable */ 2741239a96aSIvan Khoronzhuk #define TS_130 BIT(10) /* Time Sync Dest IP Addr 130 enable */ 2751239a96aSIvan Khoronzhuk #define TS_129 BIT(9) /* Time Sync Dest IP Addr 129 enable */ 2761239a96aSIvan Khoronzhuk #define TS_TTL_NONZERO BIT(8) /* Time Sync Time To Live Non-zero enable */ 2771239a96aSIvan Khoronzhuk #define TS_ANNEX_F_EN BIT(6) /* Time Sync Annex F enable */ 2781239a96aSIvan Khoronzhuk #define TS_ANNEX_D_EN BIT(4) /* Time Sync Annex D enable */ 2791239a96aSIvan Khoronzhuk #define TS_LTYPE2_EN BIT(3) /* Time Sync LTYPE 2 enable */ 2801239a96aSIvan Khoronzhuk #define TS_LTYPE1_EN BIT(2) /* Time Sync LTYPE 1 enable */ 2811239a96aSIvan Khoronzhuk #define TS_TX_EN BIT(1) /* Time Sync Transmit Enable */ 2821239a96aSIvan Khoronzhuk #define TS_RX_EN BIT(0) /* Time Sync Receive Enable */ 2839750a3adSRichard Cochran 28409c55372SGeorge Cherian #define CTRL_V2_TS_BITS \ 28509c55372SGeorge Cherian (TS_320 | TS_319 | TS_132 | TS_131 | TS_130 | TS_129 |\ 28609c55372SGeorge Cherian TS_TTL_NONZERO | TS_ANNEX_D_EN | TS_LTYPE1_EN) 2879750a3adSRichard Cochran 28809c55372SGeorge Cherian #define CTRL_V2_ALL_TS_MASK (CTRL_V2_TS_BITS | TS_TX_EN | TS_RX_EN) 28909c55372SGeorge Cherian #define CTRL_V2_TX_TS_BITS (CTRL_V2_TS_BITS | TS_TX_EN) 29009c55372SGeorge Cherian #define CTRL_V2_RX_TS_BITS (CTRL_V2_TS_BITS | TS_RX_EN) 29109c55372SGeorge Cherian 29209c55372SGeorge Cherian 29309c55372SGeorge Cherian #define CTRL_V3_TS_BITS \ 2941c0e8123SIvan Khoronzhuk (TS_107 | TS_320 | TS_319 | TS_132 | TS_131 | TS_130 | TS_129 |\ 29509c55372SGeorge Cherian TS_TTL_NONZERO | TS_ANNEX_F_EN | TS_ANNEX_D_EN |\ 29609c55372SGeorge Cherian TS_LTYPE1_EN) 29709c55372SGeorge Cherian 29809c55372SGeorge Cherian #define CTRL_V3_ALL_TS_MASK (CTRL_V3_TS_BITS | TS_TX_EN | TS_RX_EN) 29909c55372SGeorge Cherian #define CTRL_V3_TX_TS_BITS (CTRL_V3_TS_BITS | TS_TX_EN) 30009c55372SGeorge Cherian #define CTRL_V3_RX_TS_BITS (CTRL_V3_TS_BITS | TS_RX_EN) 3019750a3adSRichard Cochran 3029750a3adSRichard Cochran /* Bit definitions for the CPSW2_TS_SEQ_MTYPE register */ 3039750a3adSRichard Cochran #define TS_SEQ_ID_OFFSET_SHIFT (16) /* Time Sync Sequence ID Offset */ 3049750a3adSRichard Cochran #define TS_SEQ_ID_OFFSET_MASK (0x3f) 3059750a3adSRichard Cochran #define TS_MSG_TYPE_EN_SHIFT (0) /* Time Sync Message Type Enable */ 3069750a3adSRichard Cochran #define TS_MSG_TYPE_EN_MASK (0xffff) 3079750a3adSRichard Cochran 3089750a3adSRichard Cochran /* The PTP event messages - Sync, Delay_Req, Pdelay_Req, and Pdelay_Resp. */ 3099750a3adSRichard Cochran #define EVENT_MSG_BITS ((1<<0) | (1<<1) | (1<<2) | (1<<3)) 310df828598SMugunthan V N 3112e5b38abSRichard Cochran /* Bit definitions for the CPSW1_TS_CTL register */ 3122e5b38abSRichard Cochran #define CPSW_V1_TS_RX_EN BIT(0) 3132e5b38abSRichard Cochran #define CPSW_V1_TS_TX_EN BIT(4) 3142e5b38abSRichard Cochran #define CPSW_V1_MSG_TYPE_OFS 16 3152e5b38abSRichard Cochran 3162e5b38abSRichard Cochran /* Bit definitions for the CPSW1_TS_SEQ_LTYPE register */ 3172e5b38abSRichard Cochran #define CPSW_V1_SEQ_ID_OFS_SHIFT 16 3182e5b38abSRichard Cochran 31948f5bcccSGrygorii Strashko #define CPSW_MAX_BLKS_TX 15 32048f5bcccSGrygorii Strashko #define CPSW_MAX_BLKS_TX_SHIFT 4 32148f5bcccSGrygorii Strashko #define CPSW_MAX_BLKS_RX 5 32248f5bcccSGrygorii Strashko 323df828598SMugunthan V N struct cpsw_host_regs { 324df828598SMugunthan V N u32 max_blks; 325df828598SMugunthan V N u32 blk_cnt; 326d9ba8f9eSMugunthan V N u32 tx_in_ctl; 327df828598SMugunthan V N u32 port_vlan; 328df828598SMugunthan V N u32 tx_pri_map; 329df828598SMugunthan V N u32 cpdma_tx_pri_map; 330df828598SMugunthan V N u32 cpdma_rx_chan_map; 331df828598SMugunthan V N }; 332df828598SMugunthan V N 333df828598SMugunthan V N struct cpsw_sliver_regs { 334df828598SMugunthan V N u32 id_ver; 335df828598SMugunthan V N u32 mac_control; 336df828598SMugunthan V N u32 mac_status; 337df828598SMugunthan V N u32 soft_reset; 338df828598SMugunthan V N u32 rx_maxlen; 339df828598SMugunthan V N u32 __reserved_0; 340df828598SMugunthan V N u32 rx_pause; 341df828598SMugunthan V N u32 tx_pause; 342df828598SMugunthan V N u32 __reserved_1; 343df828598SMugunthan V N u32 rx_pri_map; 344df828598SMugunthan V N }; 345df828598SMugunthan V N 346d9718546SMugunthan V N struct cpsw_hw_stats { 347d9718546SMugunthan V N u32 rxgoodframes; 348d9718546SMugunthan V N u32 rxbroadcastframes; 349d9718546SMugunthan V N u32 rxmulticastframes; 350d9718546SMugunthan V N u32 rxpauseframes; 351d9718546SMugunthan V N u32 rxcrcerrors; 352d9718546SMugunthan V N u32 rxaligncodeerrors; 353d9718546SMugunthan V N u32 rxoversizedframes; 354d9718546SMugunthan V N u32 rxjabberframes; 355d9718546SMugunthan V N u32 rxundersizedframes; 356d9718546SMugunthan V N u32 rxfragments; 357d9718546SMugunthan V N u32 __pad_0[2]; 358d9718546SMugunthan V N u32 rxoctets; 359d9718546SMugunthan V N u32 txgoodframes; 360d9718546SMugunthan V N u32 txbroadcastframes; 361d9718546SMugunthan V N u32 txmulticastframes; 362d9718546SMugunthan V N u32 txpauseframes; 363d9718546SMugunthan V N u32 txdeferredframes; 364d9718546SMugunthan V N u32 txcollisionframes; 365d9718546SMugunthan V N u32 txsinglecollframes; 366d9718546SMugunthan V N u32 txmultcollframes; 367d9718546SMugunthan V N u32 txexcessivecollisions; 368d9718546SMugunthan V N u32 txlatecollisions; 369d9718546SMugunthan V N u32 txunderrun; 370d9718546SMugunthan V N u32 txcarriersenseerrors; 371d9718546SMugunthan V N u32 txoctets; 372d9718546SMugunthan V N u32 octetframes64; 373d9718546SMugunthan V N u32 octetframes65t127; 374d9718546SMugunthan V N u32 octetframes128t255; 375d9718546SMugunthan V N u32 octetframes256t511; 376d9718546SMugunthan V N u32 octetframes512t1023; 377d9718546SMugunthan V N u32 octetframes1024tup; 378d9718546SMugunthan V N u32 netoctets; 379d9718546SMugunthan V N u32 rxsofoverruns; 380d9718546SMugunthan V N u32 rxmofoverruns; 381d9718546SMugunthan V N u32 rxdmaoverruns; 382d9718546SMugunthan V N }; 383d9718546SMugunthan V N 3842c8a14d6SGrygorii Strashko struct cpsw_slave_data { 3852c8a14d6SGrygorii Strashko struct device_node *phy_node; 3862c8a14d6SGrygorii Strashko char phy_id[MII_BUS_ID_SIZE]; 3872c8a14d6SGrygorii Strashko int phy_if; 3882c8a14d6SGrygorii Strashko u8 mac_addr[ETH_ALEN]; 3892c8a14d6SGrygorii Strashko u16 dual_emac_res_vlan; /* Reserved VLAN for DualEMAC */ 3902c8a14d6SGrygorii Strashko }; 3912c8a14d6SGrygorii Strashko 3922c8a14d6SGrygorii Strashko struct cpsw_platform_data { 3932c8a14d6SGrygorii Strashko struct cpsw_slave_data *slave_data; 3942c8a14d6SGrygorii Strashko u32 ss_reg_ofs; /* Subsystem control register offset */ 3952c8a14d6SGrygorii Strashko u32 channels; /* number of cpdma channels (symmetric) */ 3962c8a14d6SGrygorii Strashko u32 slaves; /* number of slave cpgmac ports */ 3972c8a14d6SGrygorii Strashko u32 active_slave; /* time stamping, ethtool and SIOCGMIIPHY slave */ 3982c8a14d6SGrygorii Strashko u32 ale_entries; /* ale table size */ 3992c8a14d6SGrygorii Strashko u32 bd_ram_size; /*buffer descriptor ram size */ 4002c8a14d6SGrygorii Strashko u32 mac_control; /* Mac control register */ 4012c8a14d6SGrygorii Strashko u16 default_vlan; /* Def VLAN for ALE lookup in VLAN aware mode*/ 4022c8a14d6SGrygorii Strashko bool dual_emac; /* Enable Dual EMAC mode */ 4032c8a14d6SGrygorii Strashko }; 4042c8a14d6SGrygorii Strashko 405df828598SMugunthan V N struct cpsw_slave { 4069750a3adSRichard Cochran void __iomem *regs; 407df828598SMugunthan V N struct cpsw_sliver_regs __iomem *sliver; 408df828598SMugunthan V N int slave_num; 409df828598SMugunthan V N u32 mac_control; 410df828598SMugunthan V N struct cpsw_slave_data *data; 411df828598SMugunthan V N struct phy_device *phy; 412d9ba8f9eSMugunthan V N struct net_device *ndev; 413d9ba8f9eSMugunthan V N u32 port_vlan; 414df828598SMugunthan V N }; 415df828598SMugunthan V N 4169750a3adSRichard Cochran static inline u32 slave_read(struct cpsw_slave *slave, u32 offset) 4179750a3adSRichard Cochran { 418dda5f5feSGrygorii Strashko return readl_relaxed(slave->regs + offset); 4199750a3adSRichard Cochran } 4209750a3adSRichard Cochran 4219750a3adSRichard Cochran static inline void slave_write(struct cpsw_slave *slave, u32 val, u32 offset) 4229750a3adSRichard Cochran { 423dda5f5feSGrygorii Strashko writel_relaxed(val, slave->regs + offset); 4249750a3adSRichard Cochran } 4259750a3adSRichard Cochran 4268feb0a19SIvan Khoronzhuk struct cpsw_vector { 4278feb0a19SIvan Khoronzhuk struct cpdma_chan *ch; 4288feb0a19SIvan Khoronzhuk int budget; 4298feb0a19SIvan Khoronzhuk }; 4308feb0a19SIvan Khoronzhuk 431649a1688SIvan Khoronzhuk struct cpsw_common { 43256e31bd8SIvan Khoronzhuk struct device *dev; 433606f3993SIvan Khoronzhuk struct cpsw_platform_data data; 434dbc4ec52SIvan Khoronzhuk struct napi_struct napi_rx; 435dbc4ec52SIvan Khoronzhuk struct napi_struct napi_tx; 4365d8d0d4dSIvan Khoronzhuk struct cpsw_ss_regs __iomem *regs; 4375d8d0d4dSIvan Khoronzhuk struct cpsw_wr_regs __iomem *wr_regs; 4385d8d0d4dSIvan Khoronzhuk u8 __iomem *hw_stats; 4395d8d0d4dSIvan Khoronzhuk struct cpsw_host_regs __iomem *host_port_regs; 4402a05a622SIvan Khoronzhuk u32 version; 4412a05a622SIvan Khoronzhuk u32 coal_intvl; 4422a05a622SIvan Khoronzhuk u32 bus_freq_mhz; 4432a05a622SIvan Khoronzhuk int rx_packet_max; 444606f3993SIvan Khoronzhuk struct cpsw_slave *slaves; 4452c836bd9SIvan Khoronzhuk struct cpdma_ctlr *dma; 4468feb0a19SIvan Khoronzhuk struct cpsw_vector txv[CPSW_MAX_QUEUES]; 4478feb0a19SIvan Khoronzhuk struct cpsw_vector rxv[CPSW_MAX_QUEUES]; 4482a05a622SIvan Khoronzhuk struct cpsw_ale *ale; 449e38b5a3dSIvan Khoronzhuk bool quirk_irq; 450e38b5a3dSIvan Khoronzhuk bool rx_irq_disabled; 451e38b5a3dSIvan Khoronzhuk bool tx_irq_disabled; 452e38b5a3dSIvan Khoronzhuk u32 irqs_table[IRQ_NUM]; 4532a05a622SIvan Khoronzhuk struct cpts *cpts; 454e05107e6SIvan Khoronzhuk int rx_ch_num, tx_ch_num; 4550be01b8eSIvan Khoronzhuk int speed; 456d5bc1613SIvan Khoronzhuk int usage_count; 457649a1688SIvan Khoronzhuk }; 458649a1688SIvan Khoronzhuk 459649a1688SIvan Khoronzhuk struct cpsw_priv { 460df828598SMugunthan V N struct net_device *ndev; 461df828598SMugunthan V N struct device *dev; 462df828598SMugunthan V N u32 msg_enable; 463df828598SMugunthan V N u8 mac_addr[ETH_ALEN]; 4641923d6e4SMugunthan V N bool rx_pause; 4651923d6e4SMugunthan V N bool tx_pause; 4667929a668SIvan Khoronzhuk bool mqprio_hw; 46757d90148SIvan Khoronzhuk int fifo_bw[CPSW_TC_NUM]; 46857d90148SIvan Khoronzhuk int shp_cfg_speed; 469d9ba8f9eSMugunthan V N u32 emac_port; 470649a1688SIvan Khoronzhuk struct cpsw_common *cpsw; 471df828598SMugunthan V N }; 472df828598SMugunthan V N 473d9718546SMugunthan V N struct cpsw_stats { 474d9718546SMugunthan V N char stat_string[ETH_GSTRING_LEN]; 475d9718546SMugunthan V N int type; 476d9718546SMugunthan V N int sizeof_stat; 477d9718546SMugunthan V N int stat_offset; 478d9718546SMugunthan V N }; 479d9718546SMugunthan V N 480d9718546SMugunthan V N enum { 481d9718546SMugunthan V N CPSW_STATS, 482d9718546SMugunthan V N CPDMA_RX_STATS, 483d9718546SMugunthan V N CPDMA_TX_STATS, 484d9718546SMugunthan V N }; 485d9718546SMugunthan V N 486d9718546SMugunthan V N #define CPSW_STAT(m) CPSW_STATS, \ 487d9718546SMugunthan V N sizeof(((struct cpsw_hw_stats *)0)->m), \ 488d9718546SMugunthan V N offsetof(struct cpsw_hw_stats, m) 489d9718546SMugunthan V N #define CPDMA_RX_STAT(m) CPDMA_RX_STATS, \ 490d9718546SMugunthan V N sizeof(((struct cpdma_chan_stats *)0)->m), \ 491d9718546SMugunthan V N offsetof(struct cpdma_chan_stats, m) 492d9718546SMugunthan V N #define CPDMA_TX_STAT(m) CPDMA_TX_STATS, \ 493d9718546SMugunthan V N sizeof(((struct cpdma_chan_stats *)0)->m), \ 494d9718546SMugunthan V N offsetof(struct cpdma_chan_stats, m) 495d9718546SMugunthan V N 496d9718546SMugunthan V N static const struct cpsw_stats cpsw_gstrings_stats[] = { 497d9718546SMugunthan V N { "Good Rx Frames", CPSW_STAT(rxgoodframes) }, 498d9718546SMugunthan V N { "Broadcast Rx Frames", CPSW_STAT(rxbroadcastframes) }, 499d9718546SMugunthan V N { "Multicast Rx Frames", CPSW_STAT(rxmulticastframes) }, 500d9718546SMugunthan V N { "Pause Rx Frames", CPSW_STAT(rxpauseframes) }, 501d9718546SMugunthan V N { "Rx CRC Errors", CPSW_STAT(rxcrcerrors) }, 502d9718546SMugunthan V N { "Rx Align/Code Errors", CPSW_STAT(rxaligncodeerrors) }, 503d9718546SMugunthan V N { "Oversize Rx Frames", CPSW_STAT(rxoversizedframes) }, 504d9718546SMugunthan V N { "Rx Jabbers", CPSW_STAT(rxjabberframes) }, 505d9718546SMugunthan V N { "Undersize (Short) Rx Frames", CPSW_STAT(rxundersizedframes) }, 506d9718546SMugunthan V N { "Rx Fragments", CPSW_STAT(rxfragments) }, 507d9718546SMugunthan V N { "Rx Octets", CPSW_STAT(rxoctets) }, 508d9718546SMugunthan V N { "Good Tx Frames", CPSW_STAT(txgoodframes) }, 509d9718546SMugunthan V N { "Broadcast Tx Frames", CPSW_STAT(txbroadcastframes) }, 510d9718546SMugunthan V N { "Multicast Tx Frames", CPSW_STAT(txmulticastframes) }, 511d9718546SMugunthan V N { "Pause Tx Frames", CPSW_STAT(txpauseframes) }, 512d9718546SMugunthan V N { "Deferred Tx Frames", CPSW_STAT(txdeferredframes) }, 513d9718546SMugunthan V N { "Collisions", CPSW_STAT(txcollisionframes) }, 514d9718546SMugunthan V N { "Single Collision Tx Frames", CPSW_STAT(txsinglecollframes) }, 515d9718546SMugunthan V N { "Multiple Collision Tx Frames", CPSW_STAT(txmultcollframes) }, 516d9718546SMugunthan V N { "Excessive Collisions", CPSW_STAT(txexcessivecollisions) }, 517d9718546SMugunthan V N { "Late Collisions", CPSW_STAT(txlatecollisions) }, 518d9718546SMugunthan V N { "Tx Underrun", CPSW_STAT(txunderrun) }, 519d9718546SMugunthan V N { "Carrier Sense Errors", CPSW_STAT(txcarriersenseerrors) }, 520d9718546SMugunthan V N { "Tx Octets", CPSW_STAT(txoctets) }, 521d9718546SMugunthan V N { "Rx + Tx 64 Octet Frames", CPSW_STAT(octetframes64) }, 522d9718546SMugunthan V N { "Rx + Tx 65-127 Octet Frames", CPSW_STAT(octetframes65t127) }, 523d9718546SMugunthan V N { "Rx + Tx 128-255 Octet Frames", CPSW_STAT(octetframes128t255) }, 524d9718546SMugunthan V N { "Rx + Tx 256-511 Octet Frames", CPSW_STAT(octetframes256t511) }, 525d9718546SMugunthan V N { "Rx + Tx 512-1023 Octet Frames", CPSW_STAT(octetframes512t1023) }, 526d9718546SMugunthan V N { "Rx + Tx 1024-Up Octet Frames", CPSW_STAT(octetframes1024tup) }, 527d9718546SMugunthan V N { "Net Octets", CPSW_STAT(netoctets) }, 528d9718546SMugunthan V N { "Rx Start of Frame Overruns", CPSW_STAT(rxsofoverruns) }, 529d9718546SMugunthan V N { "Rx Middle of Frame Overruns", CPSW_STAT(rxmofoverruns) }, 530d9718546SMugunthan V N { "Rx DMA Overruns", CPSW_STAT(rxdmaoverruns) }, 531d9718546SMugunthan V N }; 532d9718546SMugunthan V N 533e05107e6SIvan Khoronzhuk static const struct cpsw_stats cpsw_gstrings_ch_stats[] = { 534e05107e6SIvan Khoronzhuk { "head_enqueue", CPDMA_RX_STAT(head_enqueue) }, 535e05107e6SIvan Khoronzhuk { "tail_enqueue", CPDMA_RX_STAT(tail_enqueue) }, 536e05107e6SIvan Khoronzhuk { "pad_enqueue", CPDMA_RX_STAT(pad_enqueue) }, 537e05107e6SIvan Khoronzhuk { "misqueued", CPDMA_RX_STAT(misqueued) }, 538e05107e6SIvan Khoronzhuk { "desc_alloc_fail", CPDMA_RX_STAT(desc_alloc_fail) }, 539e05107e6SIvan Khoronzhuk { "pad_alloc_fail", CPDMA_RX_STAT(pad_alloc_fail) }, 540e05107e6SIvan Khoronzhuk { "runt_receive_buf", CPDMA_RX_STAT(runt_receive_buff) }, 541e05107e6SIvan Khoronzhuk { "runt_transmit_buf", CPDMA_RX_STAT(runt_transmit_buff) }, 542e05107e6SIvan Khoronzhuk { "empty_dequeue", CPDMA_RX_STAT(empty_dequeue) }, 543e05107e6SIvan Khoronzhuk { "busy_dequeue", CPDMA_RX_STAT(busy_dequeue) }, 544e05107e6SIvan Khoronzhuk { "good_dequeue", CPDMA_RX_STAT(good_dequeue) }, 545e05107e6SIvan Khoronzhuk { "requeue", CPDMA_RX_STAT(requeue) }, 546e05107e6SIvan Khoronzhuk { "teardown_dequeue", CPDMA_RX_STAT(teardown_dequeue) }, 547e05107e6SIvan Khoronzhuk }; 548e05107e6SIvan Khoronzhuk 549e05107e6SIvan Khoronzhuk #define CPSW_STATS_COMMON_LEN ARRAY_SIZE(cpsw_gstrings_stats) 550e05107e6SIvan Khoronzhuk #define CPSW_STATS_CH_LEN ARRAY_SIZE(cpsw_gstrings_ch_stats) 551d9718546SMugunthan V N 552649a1688SIvan Khoronzhuk #define ndev_to_cpsw(ndev) (((struct cpsw_priv *)netdev_priv(ndev))->cpsw) 553dbc4ec52SIvan Khoronzhuk #define napi_to_cpsw(napi) container_of(napi, struct cpsw_common, napi) 554df828598SMugunthan V N #define for_each_slave(priv, func, arg...) \ 555df828598SMugunthan V N do { \ 5566e6ceaedSSebastian Siewior struct cpsw_slave *slave; \ 557606f3993SIvan Khoronzhuk struct cpsw_common *cpsw = (priv)->cpsw; \ 5586e6ceaedSSebastian Siewior int n; \ 559606f3993SIvan Khoronzhuk if (cpsw->data.dual_emac) \ 560606f3993SIvan Khoronzhuk (func)((cpsw)->slaves + priv->emac_port, ##arg);\ 561d9ba8f9eSMugunthan V N else \ 562606f3993SIvan Khoronzhuk for (n = cpsw->data.slaves, \ 563606f3993SIvan Khoronzhuk slave = cpsw->slaves; \ 5646e6ceaedSSebastian Siewior n; n--) \ 5656e6ceaedSSebastian Siewior (func)(slave++, ##arg); \ 566df828598SMugunthan V N } while (0) 567d9ba8f9eSMugunthan V N 5682a05a622SIvan Khoronzhuk #define cpsw_dual_emac_src_port_detect(cpsw, status, ndev, skb) \ 569d9ba8f9eSMugunthan V N do { \ 570606f3993SIvan Khoronzhuk if (!cpsw->data.dual_emac) \ 571d9ba8f9eSMugunthan V N break; \ 572d9ba8f9eSMugunthan V N if (CPDMA_RX_SOURCE_PORT(status) == 1) { \ 573606f3993SIvan Khoronzhuk ndev = cpsw->slaves[0].ndev; \ 574d9ba8f9eSMugunthan V N skb->dev = ndev; \ 575d9ba8f9eSMugunthan V N } else if (CPDMA_RX_SOURCE_PORT(status) == 2) { \ 576606f3993SIvan Khoronzhuk ndev = cpsw->slaves[1].ndev; \ 577d9ba8f9eSMugunthan V N skb->dev = ndev; \ 578d9ba8f9eSMugunthan V N } \ 579d9ba8f9eSMugunthan V N } while (0) 580606f3993SIvan Khoronzhuk #define cpsw_add_mcast(cpsw, priv, addr) \ 581d9ba8f9eSMugunthan V N do { \ 582606f3993SIvan Khoronzhuk if (cpsw->data.dual_emac) { \ 583606f3993SIvan Khoronzhuk struct cpsw_slave *slave = cpsw->slaves + \ 584d9ba8f9eSMugunthan V N priv->emac_port; \ 5856f1f5836SIvan Khoronzhuk int slave_port = cpsw_get_slave_port( \ 586d9ba8f9eSMugunthan V N slave->slave_num); \ 5872a05a622SIvan Khoronzhuk cpsw_ale_add_mcast(cpsw->ale, addr, \ 58871a2cbb7SGrygorii Strashko 1 << slave_port | ALE_PORT_HOST, \ 589d9ba8f9eSMugunthan V N ALE_VLAN, slave->port_vlan, 0); \ 590d9ba8f9eSMugunthan V N } else { \ 5912a05a622SIvan Khoronzhuk cpsw_ale_add_mcast(cpsw->ale, addr, \ 59261f1cef9SGrygorii Strashko ALE_ALL_PORTS, \ 593d9ba8f9eSMugunthan V N 0, 0, 0); \ 594d9ba8f9eSMugunthan V N } \ 595d9ba8f9eSMugunthan V N } while (0) 596d9ba8f9eSMugunthan V N 5976f1f5836SIvan Khoronzhuk static inline int cpsw_get_slave_port(u32 slave_num) 598d9ba8f9eSMugunthan V N { 599d9ba8f9eSMugunthan V N return slave_num + 1; 600d9ba8f9eSMugunthan V N } 601df828598SMugunthan V N 6020cd8f9ccSMugunthan V N static void cpsw_set_promiscious(struct net_device *ndev, bool enable) 6030cd8f9ccSMugunthan V N { 6042a05a622SIvan Khoronzhuk struct cpsw_common *cpsw = ndev_to_cpsw(ndev); 6052a05a622SIvan Khoronzhuk struct cpsw_ale *ale = cpsw->ale; 6060cd8f9ccSMugunthan V N int i; 6070cd8f9ccSMugunthan V N 608606f3993SIvan Khoronzhuk if (cpsw->data.dual_emac) { 6090cd8f9ccSMugunthan V N bool flag = false; 6100cd8f9ccSMugunthan V N 6110cd8f9ccSMugunthan V N /* Enabling promiscuous mode for one interface will be 6120cd8f9ccSMugunthan V N * common for both the interface as the interface shares 6130cd8f9ccSMugunthan V N * the same hardware resource. 6140cd8f9ccSMugunthan V N */ 615606f3993SIvan Khoronzhuk for (i = 0; i < cpsw->data.slaves; i++) 616606f3993SIvan Khoronzhuk if (cpsw->slaves[i].ndev->flags & IFF_PROMISC) 6170cd8f9ccSMugunthan V N flag = true; 6180cd8f9ccSMugunthan V N 6190cd8f9ccSMugunthan V N if (!enable && flag) { 6200cd8f9ccSMugunthan V N enable = true; 6210cd8f9ccSMugunthan V N dev_err(&ndev->dev, "promiscuity not disabled as the other interface is still in promiscuity mode\n"); 6220cd8f9ccSMugunthan V N } 6230cd8f9ccSMugunthan V N 6240cd8f9ccSMugunthan V N if (enable) { 6250cd8f9ccSMugunthan V N /* Enable Bypass */ 6260cd8f9ccSMugunthan V N cpsw_ale_control_set(ale, 0, ALE_BYPASS, 1); 6270cd8f9ccSMugunthan V N 6280cd8f9ccSMugunthan V N dev_dbg(&ndev->dev, "promiscuity enabled\n"); 6290cd8f9ccSMugunthan V N } else { 6300cd8f9ccSMugunthan V N /* Disable Bypass */ 6310cd8f9ccSMugunthan V N cpsw_ale_control_set(ale, 0, ALE_BYPASS, 0); 6320cd8f9ccSMugunthan V N dev_dbg(&ndev->dev, "promiscuity disabled\n"); 6330cd8f9ccSMugunthan V N } 6340cd8f9ccSMugunthan V N } else { 6350cd8f9ccSMugunthan V N if (enable) { 6360cd8f9ccSMugunthan V N unsigned long timeout = jiffies + HZ; 6370cd8f9ccSMugunthan V N 6386f979eb3SLennart Sorensen /* Disable Learn for all ports (host is port 0 and slaves are port 1 and up */ 639606f3993SIvan Khoronzhuk for (i = 0; i <= cpsw->data.slaves; i++) { 6400cd8f9ccSMugunthan V N cpsw_ale_control_set(ale, i, 6410cd8f9ccSMugunthan V N ALE_PORT_NOLEARN, 1); 6420cd8f9ccSMugunthan V N cpsw_ale_control_set(ale, i, 6430cd8f9ccSMugunthan V N ALE_PORT_NO_SA_UPDATE, 1); 6440cd8f9ccSMugunthan V N } 6450cd8f9ccSMugunthan V N 6460cd8f9ccSMugunthan V N /* Clear All Untouched entries */ 6470cd8f9ccSMugunthan V N cpsw_ale_control_set(ale, 0, ALE_AGEOUT, 1); 6480cd8f9ccSMugunthan V N do { 6490cd8f9ccSMugunthan V N cpu_relax(); 6500cd8f9ccSMugunthan V N if (cpsw_ale_control_get(ale, 0, ALE_AGEOUT)) 6510cd8f9ccSMugunthan V N break; 6520cd8f9ccSMugunthan V N } while (time_after(timeout, jiffies)); 6530cd8f9ccSMugunthan V N cpsw_ale_control_set(ale, 0, ALE_AGEOUT, 1); 6540cd8f9ccSMugunthan V N 6550cd8f9ccSMugunthan V N /* Clear all mcast from ALE */ 65661f1cef9SGrygorii Strashko cpsw_ale_flush_multicast(ale, ALE_ALL_PORTS, -1); 6570cd8f9ccSMugunthan V N 6580cd8f9ccSMugunthan V N /* Flood All Unicast Packets to Host port */ 6590cd8f9ccSMugunthan V N cpsw_ale_control_set(ale, 0, ALE_P0_UNI_FLOOD, 1); 6600cd8f9ccSMugunthan V N dev_dbg(&ndev->dev, "promiscuity enabled\n"); 6610cd8f9ccSMugunthan V N } else { 6626f979eb3SLennart Sorensen /* Don't Flood All Unicast Packets to Host port */ 6630cd8f9ccSMugunthan V N cpsw_ale_control_set(ale, 0, ALE_P0_UNI_FLOOD, 0); 6640cd8f9ccSMugunthan V N 6656f979eb3SLennart Sorensen /* Enable Learn for all ports (host is port 0 and slaves are port 1 and up */ 666606f3993SIvan Khoronzhuk for (i = 0; i <= cpsw->data.slaves; i++) { 6670cd8f9ccSMugunthan V N cpsw_ale_control_set(ale, i, 6680cd8f9ccSMugunthan V N ALE_PORT_NOLEARN, 0); 6690cd8f9ccSMugunthan V N cpsw_ale_control_set(ale, i, 6700cd8f9ccSMugunthan V N ALE_PORT_NO_SA_UPDATE, 0); 6710cd8f9ccSMugunthan V N } 6720cd8f9ccSMugunthan V N dev_dbg(&ndev->dev, "promiscuity disabled\n"); 6730cd8f9ccSMugunthan V N } 6740cd8f9ccSMugunthan V N } 6750cd8f9ccSMugunthan V N } 6760cd8f9ccSMugunthan V N 6775c50a856SMugunthan V N static void cpsw_ndo_set_rx_mode(struct net_device *ndev) 6785c50a856SMugunthan V N { 6795c50a856SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 680606f3993SIvan Khoronzhuk struct cpsw_common *cpsw = priv->cpsw; 68125906052SMugunthan V N int vid; 68225906052SMugunthan V N 683606f3993SIvan Khoronzhuk if (cpsw->data.dual_emac) 684606f3993SIvan Khoronzhuk vid = cpsw->slaves[priv->emac_port].port_vlan; 68525906052SMugunthan V N else 686606f3993SIvan Khoronzhuk vid = cpsw->data.default_vlan; 6875c50a856SMugunthan V N 6885c50a856SMugunthan V N if (ndev->flags & IFF_PROMISC) { 6895c50a856SMugunthan V N /* Enable promiscuous mode */ 6900cd8f9ccSMugunthan V N cpsw_set_promiscious(ndev, true); 6912a05a622SIvan Khoronzhuk cpsw_ale_set_allmulti(cpsw->ale, IFF_ALLMULTI); 6925c50a856SMugunthan V N return; 6930cd8f9ccSMugunthan V N } else { 6940cd8f9ccSMugunthan V N /* Disable promiscuous mode */ 6950cd8f9ccSMugunthan V N cpsw_set_promiscious(ndev, false); 6965c50a856SMugunthan V N } 6975c50a856SMugunthan V N 6981e5c4bc4SLennart Sorensen /* Restore allmulti on vlans if necessary */ 6992a05a622SIvan Khoronzhuk cpsw_ale_set_allmulti(cpsw->ale, priv->ndev->flags & IFF_ALLMULTI); 7001e5c4bc4SLennart Sorensen 7015c50a856SMugunthan V N /* Clear all mcast from ALE */ 7022a05a622SIvan Khoronzhuk cpsw_ale_flush_multicast(cpsw->ale, ALE_ALL_PORTS, vid); 7035c50a856SMugunthan V N 7045c50a856SMugunthan V N if (!netdev_mc_empty(ndev)) { 7055c50a856SMugunthan V N struct netdev_hw_addr *ha; 7065c50a856SMugunthan V N 7075c50a856SMugunthan V N /* program multicast address list into ALE register */ 7085c50a856SMugunthan V N netdev_for_each_mc_addr(ha, ndev) { 709606f3993SIvan Khoronzhuk cpsw_add_mcast(cpsw, priv, (u8 *)ha->addr); 7105c50a856SMugunthan V N } 7115c50a856SMugunthan V N } 7125c50a856SMugunthan V N } 7135c50a856SMugunthan V N 7142c836bd9SIvan Khoronzhuk static void cpsw_intr_enable(struct cpsw_common *cpsw) 715df828598SMugunthan V N { 716dda5f5feSGrygorii Strashko writel_relaxed(0xFF, &cpsw->wr_regs->tx_en); 717dda5f5feSGrygorii Strashko writel_relaxed(0xFF, &cpsw->wr_regs->rx_en); 718df828598SMugunthan V N 7192c836bd9SIvan Khoronzhuk cpdma_ctlr_int_ctrl(cpsw->dma, true); 720df828598SMugunthan V N return; 721df828598SMugunthan V N } 722df828598SMugunthan V N 7232c836bd9SIvan Khoronzhuk static void cpsw_intr_disable(struct cpsw_common *cpsw) 724df828598SMugunthan V N { 725dda5f5feSGrygorii Strashko writel_relaxed(0, &cpsw->wr_regs->tx_en); 726dda5f5feSGrygorii Strashko writel_relaxed(0, &cpsw->wr_regs->rx_en); 727df828598SMugunthan V N 7282c836bd9SIvan Khoronzhuk cpdma_ctlr_int_ctrl(cpsw->dma, false); 729df828598SMugunthan V N return; 730df828598SMugunthan V N } 731df828598SMugunthan V N 7321a3b5056SOlof Johansson static void cpsw_tx_handler(void *token, int len, int status) 733df828598SMugunthan V N { 734e05107e6SIvan Khoronzhuk struct netdev_queue *txq; 735df828598SMugunthan V N struct sk_buff *skb = token; 736df828598SMugunthan V N struct net_device *ndev = skb->dev; 7372a05a622SIvan Khoronzhuk struct cpsw_common *cpsw = ndev_to_cpsw(ndev); 738df828598SMugunthan V N 739fae50823SMugunthan V N /* Check whether the queue is stopped due to stalled tx dma, if the 740fae50823SMugunthan V N * queue is stopped then start the queue as we have free desc for tx 741fae50823SMugunthan V N */ 742e05107e6SIvan Khoronzhuk txq = netdev_get_tx_queue(ndev, skb_get_queue_mapping(skb)); 743e05107e6SIvan Khoronzhuk if (unlikely(netif_tx_queue_stopped(txq))) 744e05107e6SIvan Khoronzhuk netif_tx_wake_queue(txq); 745e05107e6SIvan Khoronzhuk 7462a05a622SIvan Khoronzhuk cpts_tx_timestamp(cpsw->cpts, skb); 7478dc43ddcSTobias Klauser ndev->stats.tx_packets++; 7488dc43ddcSTobias Klauser ndev->stats.tx_bytes += len; 749df828598SMugunthan V N dev_kfree_skb_any(skb); 750df828598SMugunthan V N } 751df828598SMugunthan V N 752a3a41d2fSGrygorii Strashko static void cpsw_rx_vlan_encap(struct sk_buff *skb) 753a3a41d2fSGrygorii Strashko { 754a3a41d2fSGrygorii Strashko struct cpsw_priv *priv = netdev_priv(skb->dev); 755a3a41d2fSGrygorii Strashko struct cpsw_common *cpsw = priv->cpsw; 756a3a41d2fSGrygorii Strashko u32 rx_vlan_encap_hdr = *((u32 *)skb->data); 757a3a41d2fSGrygorii Strashko u16 vtag, vid, prio, pkt_type; 758a3a41d2fSGrygorii Strashko 759a3a41d2fSGrygorii Strashko /* Remove VLAN header encapsulation word */ 760a3a41d2fSGrygorii Strashko skb_pull(skb, CPSW_RX_VLAN_ENCAP_HDR_SIZE); 761a3a41d2fSGrygorii Strashko 762a3a41d2fSGrygorii Strashko pkt_type = (rx_vlan_encap_hdr >> 763a3a41d2fSGrygorii Strashko CPSW_RX_VLAN_ENCAP_HDR_PKT_TYPE_SHIFT) & 764a3a41d2fSGrygorii Strashko CPSW_RX_VLAN_ENCAP_HDR_PKT_TYPE_MSK; 765a3a41d2fSGrygorii Strashko /* Ignore unknown & Priority-tagged packets*/ 766a3a41d2fSGrygorii Strashko if (pkt_type == CPSW_RX_VLAN_ENCAP_HDR_PKT_RESERV || 767a3a41d2fSGrygorii Strashko pkt_type == CPSW_RX_VLAN_ENCAP_HDR_PKT_PRIO_TAG) 768a3a41d2fSGrygorii Strashko return; 769a3a41d2fSGrygorii Strashko 770a3a41d2fSGrygorii Strashko vid = (rx_vlan_encap_hdr >> 771a3a41d2fSGrygorii Strashko CPSW_RX_VLAN_ENCAP_HDR_VID_SHIFT) & 772a3a41d2fSGrygorii Strashko VLAN_VID_MASK; 773a3a41d2fSGrygorii Strashko /* Ignore vid 0 and pass packet as is */ 774a3a41d2fSGrygorii Strashko if (!vid) 775a3a41d2fSGrygorii Strashko return; 776a3a41d2fSGrygorii Strashko /* Ignore default vlans in dual mac mode */ 777a3a41d2fSGrygorii Strashko if (cpsw->data.dual_emac && 778a3a41d2fSGrygorii Strashko vid == cpsw->slaves[priv->emac_port].port_vlan) 779a3a41d2fSGrygorii Strashko return; 780a3a41d2fSGrygorii Strashko 781a3a41d2fSGrygorii Strashko prio = (rx_vlan_encap_hdr >> 782a3a41d2fSGrygorii Strashko CPSW_RX_VLAN_ENCAP_HDR_PRIO_SHIFT) & 783a3a41d2fSGrygorii Strashko CPSW_RX_VLAN_ENCAP_HDR_PRIO_MSK; 784a3a41d2fSGrygorii Strashko 785a3a41d2fSGrygorii Strashko vtag = (prio << VLAN_PRIO_SHIFT) | vid; 786a3a41d2fSGrygorii Strashko __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vtag); 787a3a41d2fSGrygorii Strashko 788a3a41d2fSGrygorii Strashko /* strip vlan tag for VLAN-tagged packet */ 789a3a41d2fSGrygorii Strashko if (pkt_type == CPSW_RX_VLAN_ENCAP_HDR_PKT_VLAN_TAG) { 790a3a41d2fSGrygorii Strashko memmove(skb->data + VLAN_HLEN, skb->data, 2 * ETH_ALEN); 791a3a41d2fSGrygorii Strashko skb_pull(skb, VLAN_HLEN); 792a3a41d2fSGrygorii Strashko } 793a3a41d2fSGrygorii Strashko } 794a3a41d2fSGrygorii Strashko 7951a3b5056SOlof Johansson static void cpsw_rx_handler(void *token, int len, int status) 796df828598SMugunthan V N { 797e05107e6SIvan Khoronzhuk struct cpdma_chan *ch; 798df828598SMugunthan V N struct sk_buff *skb = token; 799b4727e69SSebastian Siewior struct sk_buff *new_skb; 800df828598SMugunthan V N struct net_device *ndev = skb->dev; 801df828598SMugunthan V N int ret = 0; 8022a05a622SIvan Khoronzhuk struct cpsw_common *cpsw = ndev_to_cpsw(ndev); 803df828598SMugunthan V N 8042a05a622SIvan Khoronzhuk cpsw_dual_emac_src_port_detect(cpsw, status, ndev, skb); 805d9ba8f9eSMugunthan V N 80616e5c57dSMugunthan V N if (unlikely(status < 0) || unlikely(!netif_running(ndev))) { 807a0e2c822SMugunthan V N /* In dual emac mode check for all interfaces */ 808d5bc1613SIvan Khoronzhuk if (cpsw->data.dual_emac && cpsw->usage_count && 809fe734d0aSIvan Khoronzhuk (status >= 0)) { 810a0e2c822SMugunthan V N /* The packet received is for the interface which 811a0e2c822SMugunthan V N * is already down and the other interface is up 812dbedd44eSJoe Perches * and running, instead of freeing which results 813a0e2c822SMugunthan V N * in reducing of the number of rx descriptor in 814a0e2c822SMugunthan V N * DMA engine, requeue skb back to cpdma. 815a0e2c822SMugunthan V N */ 816a0e2c822SMugunthan V N new_skb = skb; 817a0e2c822SMugunthan V N goto requeue; 818a0e2c822SMugunthan V N } 819a0e2c822SMugunthan V N 820b4727e69SSebastian Siewior /* the interface is going down, skbs are purged */ 821df828598SMugunthan V N dev_kfree_skb_any(skb); 822df828598SMugunthan V N return; 823df828598SMugunthan V N } 824b4727e69SSebastian Siewior 8252a05a622SIvan Khoronzhuk new_skb = netdev_alloc_skb_ip_align(ndev, cpsw->rx_packet_max); 826b4727e69SSebastian Siewior if (new_skb) { 827e05107e6SIvan Khoronzhuk skb_copy_queue_mapping(new_skb, skb); 828df828598SMugunthan V N skb_put(skb, len); 829a3a41d2fSGrygorii Strashko if (status & CPDMA_RX_VLAN_ENCAP) 830a3a41d2fSGrygorii Strashko cpsw_rx_vlan_encap(skb); 8312a05a622SIvan Khoronzhuk cpts_rx_timestamp(cpsw->cpts, skb); 832df828598SMugunthan V N skb->protocol = eth_type_trans(skb, ndev); 833df828598SMugunthan V N netif_receive_skb(skb); 8348dc43ddcSTobias Klauser ndev->stats.rx_bytes += len; 8358dc43ddcSTobias Klauser ndev->stats.rx_packets++; 836254a49d5SGrygorii Strashko kmemleak_not_leak(new_skb); 837b4727e69SSebastian Siewior } else { 8388dc43ddcSTobias Klauser ndev->stats.rx_dropped++; 839b4727e69SSebastian Siewior new_skb = skb; 840df828598SMugunthan V N } 841df828598SMugunthan V N 842a0e2c822SMugunthan V N requeue: 843ce52c744SIvan Khoronzhuk if (netif_dormant(ndev)) { 844ce52c744SIvan Khoronzhuk dev_kfree_skb_any(new_skb); 845ce52c744SIvan Khoronzhuk return; 846ce52c744SIvan Khoronzhuk } 847ce52c744SIvan Khoronzhuk 8488feb0a19SIvan Khoronzhuk ch = cpsw->rxv[skb_get_queue_mapping(new_skb)].ch; 849e05107e6SIvan Khoronzhuk ret = cpdma_chan_submit(ch, new_skb, new_skb->data, 850b4727e69SSebastian Siewior skb_tailroom(new_skb), 0); 851b4727e69SSebastian Siewior if (WARN_ON(ret < 0)) 852b4727e69SSebastian Siewior dev_kfree_skb_any(new_skb); 853df828598SMugunthan V N } 854df828598SMugunthan V N 85532b78d85SIvan Khoronzhuk static void cpsw_split_res(struct net_device *ndev) 85648e0a83eSIvan Khoronzhuk { 85748e0a83eSIvan Khoronzhuk struct cpsw_priv *priv = netdev_priv(ndev); 85832b78d85SIvan Khoronzhuk u32 consumed_rate = 0, bigest_rate = 0; 85948e0a83eSIvan Khoronzhuk struct cpsw_common *cpsw = priv->cpsw; 86048e0a83eSIvan Khoronzhuk struct cpsw_vector *txv = cpsw->txv; 86132b78d85SIvan Khoronzhuk int i, ch_weight, rlim_ch_num = 0; 86248e0a83eSIvan Khoronzhuk int budget, bigest_rate_ch = 0; 86348e0a83eSIvan Khoronzhuk u32 ch_rate, max_rate; 86448e0a83eSIvan Khoronzhuk int ch_budget = 0; 86548e0a83eSIvan Khoronzhuk 86648e0a83eSIvan Khoronzhuk for (i = 0; i < cpsw->tx_ch_num; i++) { 86748e0a83eSIvan Khoronzhuk ch_rate = cpdma_chan_get_rate(txv[i].ch); 86848e0a83eSIvan Khoronzhuk if (!ch_rate) 86948e0a83eSIvan Khoronzhuk continue; 87048e0a83eSIvan Khoronzhuk 87148e0a83eSIvan Khoronzhuk rlim_ch_num++; 87248e0a83eSIvan Khoronzhuk consumed_rate += ch_rate; 87348e0a83eSIvan Khoronzhuk } 87448e0a83eSIvan Khoronzhuk 87548e0a83eSIvan Khoronzhuk if (cpsw->tx_ch_num == rlim_ch_num) { 87648e0a83eSIvan Khoronzhuk max_rate = consumed_rate; 87732b78d85SIvan Khoronzhuk } else if (!rlim_ch_num) { 87832b78d85SIvan Khoronzhuk ch_budget = CPSW_POLL_WEIGHT / cpsw->tx_ch_num; 87932b78d85SIvan Khoronzhuk bigest_rate = 0; 88032b78d85SIvan Khoronzhuk max_rate = consumed_rate; 88148e0a83eSIvan Khoronzhuk } else { 8820be01b8eSIvan Khoronzhuk max_rate = cpsw->speed * 1000; 8830be01b8eSIvan Khoronzhuk 8840be01b8eSIvan Khoronzhuk /* if max_rate is less then expected due to reduced link speed, 8850be01b8eSIvan Khoronzhuk * split proportionally according next potential max speed 8860be01b8eSIvan Khoronzhuk */ 8870be01b8eSIvan Khoronzhuk if (max_rate < consumed_rate) 8880be01b8eSIvan Khoronzhuk max_rate *= 10; 8890be01b8eSIvan Khoronzhuk 8900be01b8eSIvan Khoronzhuk if (max_rate < consumed_rate) 8910be01b8eSIvan Khoronzhuk max_rate *= 10; 89232b78d85SIvan Khoronzhuk 89348e0a83eSIvan Khoronzhuk ch_budget = (consumed_rate * CPSW_POLL_WEIGHT) / max_rate; 89448e0a83eSIvan Khoronzhuk ch_budget = (CPSW_POLL_WEIGHT - ch_budget) / 89548e0a83eSIvan Khoronzhuk (cpsw->tx_ch_num - rlim_ch_num); 89648e0a83eSIvan Khoronzhuk bigest_rate = (max_rate - consumed_rate) / 89748e0a83eSIvan Khoronzhuk (cpsw->tx_ch_num - rlim_ch_num); 89848e0a83eSIvan Khoronzhuk } 89948e0a83eSIvan Khoronzhuk 90032b78d85SIvan Khoronzhuk /* split tx weight/budget */ 90148e0a83eSIvan Khoronzhuk budget = CPSW_POLL_WEIGHT; 90248e0a83eSIvan Khoronzhuk for (i = 0; i < cpsw->tx_ch_num; i++) { 90348e0a83eSIvan Khoronzhuk ch_rate = cpdma_chan_get_rate(txv[i].ch); 90448e0a83eSIvan Khoronzhuk if (ch_rate) { 90548e0a83eSIvan Khoronzhuk txv[i].budget = (ch_rate * CPSW_POLL_WEIGHT) / max_rate; 90648e0a83eSIvan Khoronzhuk if (!txv[i].budget) 90732b78d85SIvan Khoronzhuk txv[i].budget++; 90848e0a83eSIvan Khoronzhuk if (ch_rate > bigest_rate) { 90948e0a83eSIvan Khoronzhuk bigest_rate_ch = i; 91048e0a83eSIvan Khoronzhuk bigest_rate = ch_rate; 91148e0a83eSIvan Khoronzhuk } 91232b78d85SIvan Khoronzhuk 91332b78d85SIvan Khoronzhuk ch_weight = (ch_rate * 100) / max_rate; 91432b78d85SIvan Khoronzhuk if (!ch_weight) 91532b78d85SIvan Khoronzhuk ch_weight++; 91632b78d85SIvan Khoronzhuk cpdma_chan_set_weight(cpsw->txv[i].ch, ch_weight); 91748e0a83eSIvan Khoronzhuk } else { 91848e0a83eSIvan Khoronzhuk txv[i].budget = ch_budget; 91948e0a83eSIvan Khoronzhuk if (!bigest_rate_ch) 92048e0a83eSIvan Khoronzhuk bigest_rate_ch = i; 92132b78d85SIvan Khoronzhuk cpdma_chan_set_weight(cpsw->txv[i].ch, 0); 92248e0a83eSIvan Khoronzhuk } 92348e0a83eSIvan Khoronzhuk 92448e0a83eSIvan Khoronzhuk budget -= txv[i].budget; 92548e0a83eSIvan Khoronzhuk } 92648e0a83eSIvan Khoronzhuk 92748e0a83eSIvan Khoronzhuk if (budget) 92848e0a83eSIvan Khoronzhuk txv[bigest_rate_ch].budget += budget; 92948e0a83eSIvan Khoronzhuk 93048e0a83eSIvan Khoronzhuk /* split rx budget */ 93148e0a83eSIvan Khoronzhuk budget = CPSW_POLL_WEIGHT; 93248e0a83eSIvan Khoronzhuk ch_budget = budget / cpsw->rx_ch_num; 93348e0a83eSIvan Khoronzhuk for (i = 0; i < cpsw->rx_ch_num; i++) { 93448e0a83eSIvan Khoronzhuk cpsw->rxv[i].budget = ch_budget; 93548e0a83eSIvan Khoronzhuk budget -= ch_budget; 93648e0a83eSIvan Khoronzhuk } 93748e0a83eSIvan Khoronzhuk 93848e0a83eSIvan Khoronzhuk if (budget) 93948e0a83eSIvan Khoronzhuk cpsw->rxv[0].budget += budget; 94048e0a83eSIvan Khoronzhuk } 94148e0a83eSIvan Khoronzhuk 942c03abd84SFelipe Balbi static irqreturn_t cpsw_tx_interrupt(int irq, void *dev_id) 943df828598SMugunthan V N { 944dbc4ec52SIvan Khoronzhuk struct cpsw_common *cpsw = dev_id; 9457ce67a38SFelipe Balbi 9465d8d0d4dSIvan Khoronzhuk writel(0, &cpsw->wr_regs->tx_en); 9472c836bd9SIvan Khoronzhuk cpdma_ctlr_eoi(cpsw->dma, CPDMA_EOI_TX); 948c03abd84SFelipe Balbi 949e38b5a3dSIvan Khoronzhuk if (cpsw->quirk_irq) { 950e38b5a3dSIvan Khoronzhuk disable_irq_nosync(cpsw->irqs_table[1]); 951e38b5a3dSIvan Khoronzhuk cpsw->tx_irq_disabled = true; 9527da11600SMugunthan V N } 9537da11600SMugunthan V N 954dbc4ec52SIvan Khoronzhuk napi_schedule(&cpsw->napi_tx); 955c03abd84SFelipe Balbi return IRQ_HANDLED; 956c03abd84SFelipe Balbi } 957c03abd84SFelipe Balbi 958c03abd84SFelipe Balbi static irqreturn_t cpsw_rx_interrupt(int irq, void *dev_id) 959c03abd84SFelipe Balbi { 960dbc4ec52SIvan Khoronzhuk struct cpsw_common *cpsw = dev_id; 961c03abd84SFelipe Balbi 9622c836bd9SIvan Khoronzhuk cpdma_ctlr_eoi(cpsw->dma, CPDMA_EOI_RX); 9635d8d0d4dSIvan Khoronzhuk writel(0, &cpsw->wr_regs->rx_en); 964fd51cf19SSebastian Siewior 965e38b5a3dSIvan Khoronzhuk if (cpsw->quirk_irq) { 966e38b5a3dSIvan Khoronzhuk disable_irq_nosync(cpsw->irqs_table[0]); 967e38b5a3dSIvan Khoronzhuk cpsw->rx_irq_disabled = true; 9687da11600SMugunthan V N } 9697da11600SMugunthan V N 970dbc4ec52SIvan Khoronzhuk napi_schedule(&cpsw->napi_rx); 971df828598SMugunthan V N return IRQ_HANDLED; 972df828598SMugunthan V N } 973df828598SMugunthan V N 9749611d6d6SIvan Khoronzhuk static int cpsw_tx_mq_poll(struct napi_struct *napi_tx, int budget) 975df828598SMugunthan V N { 976e05107e6SIvan Khoronzhuk u32 ch_map; 9778feb0a19SIvan Khoronzhuk int num_tx, cur_budget, ch; 978dbc4ec52SIvan Khoronzhuk struct cpsw_common *cpsw = napi_to_cpsw(napi_tx); 9798feb0a19SIvan Khoronzhuk struct cpsw_vector *txv; 98032a7432cSMugunthan V N 981e05107e6SIvan Khoronzhuk /* process every unprocessed channel */ 982e05107e6SIvan Khoronzhuk ch_map = cpdma_ctrl_txchs_state(cpsw->dma); 98379b3325dSIvan Khoronzhuk for (ch = 0, num_tx = 0; ch_map & 0xff; ch_map <<= 1, ch++) { 98479b3325dSIvan Khoronzhuk if (!(ch_map & 0x80)) 985e05107e6SIvan Khoronzhuk continue; 986e05107e6SIvan Khoronzhuk 9878feb0a19SIvan Khoronzhuk txv = &cpsw->txv[ch]; 9888feb0a19SIvan Khoronzhuk if (unlikely(txv->budget > budget - num_tx)) 9898feb0a19SIvan Khoronzhuk cur_budget = budget - num_tx; 9908feb0a19SIvan Khoronzhuk else 9918feb0a19SIvan Khoronzhuk cur_budget = txv->budget; 9928feb0a19SIvan Khoronzhuk 9938feb0a19SIvan Khoronzhuk num_tx += cpdma_chan_process(txv->ch, cur_budget); 994342934a5SIvan Khoronzhuk if (num_tx >= budget) 995342934a5SIvan Khoronzhuk break; 996e05107e6SIvan Khoronzhuk } 997e05107e6SIvan Khoronzhuk 99832a7432cSMugunthan V N if (num_tx < budget) { 99932a7432cSMugunthan V N napi_complete(napi_tx); 10005d8d0d4dSIvan Khoronzhuk writel(0xff, &cpsw->wr_regs->tx_en); 10019611d6d6SIvan Khoronzhuk } 10029611d6d6SIvan Khoronzhuk 10039611d6d6SIvan Khoronzhuk return num_tx; 10049611d6d6SIvan Khoronzhuk } 10059611d6d6SIvan Khoronzhuk 10069611d6d6SIvan Khoronzhuk static int cpsw_tx_poll(struct napi_struct *napi_tx, int budget) 10079611d6d6SIvan Khoronzhuk { 10089611d6d6SIvan Khoronzhuk struct cpsw_common *cpsw = napi_to_cpsw(napi_tx); 10099611d6d6SIvan Khoronzhuk int num_tx; 10109611d6d6SIvan Khoronzhuk 10119611d6d6SIvan Khoronzhuk num_tx = cpdma_chan_process(cpsw->txv[0].ch, budget); 10129611d6d6SIvan Khoronzhuk if (num_tx < budget) { 10139611d6d6SIvan Khoronzhuk napi_complete(napi_tx); 10149611d6d6SIvan Khoronzhuk writel(0xff, &cpsw->wr_regs->tx_en); 10159611d6d6SIvan Khoronzhuk if (cpsw->tx_irq_disabled) { 1016e38b5a3dSIvan Khoronzhuk cpsw->tx_irq_disabled = false; 1017e38b5a3dSIvan Khoronzhuk enable_irq(cpsw->irqs_table[1]); 10187da11600SMugunthan V N } 101932a7432cSMugunthan V N } 102032a7432cSMugunthan V N 102132a7432cSMugunthan V N return num_tx; 102232a7432cSMugunthan V N } 102332a7432cSMugunthan V N 10249611d6d6SIvan Khoronzhuk static int cpsw_rx_mq_poll(struct napi_struct *napi_rx, int budget) 102532a7432cSMugunthan V N { 1026e05107e6SIvan Khoronzhuk u32 ch_map; 10278feb0a19SIvan Khoronzhuk int num_rx, cur_budget, ch; 1028dbc4ec52SIvan Khoronzhuk struct cpsw_common *cpsw = napi_to_cpsw(napi_rx); 10298feb0a19SIvan Khoronzhuk struct cpsw_vector *rxv; 1030510a1e72SMugunthan V N 1031e05107e6SIvan Khoronzhuk /* process every unprocessed channel */ 1032e05107e6SIvan Khoronzhuk ch_map = cpdma_ctrl_rxchs_state(cpsw->dma); 1033342934a5SIvan Khoronzhuk for (ch = 0, num_rx = 0; ch_map; ch_map >>= 1, ch++) { 1034e05107e6SIvan Khoronzhuk if (!(ch_map & 0x01)) 1035e05107e6SIvan Khoronzhuk continue; 1036e05107e6SIvan Khoronzhuk 10378feb0a19SIvan Khoronzhuk rxv = &cpsw->rxv[ch]; 10388feb0a19SIvan Khoronzhuk if (unlikely(rxv->budget > budget - num_rx)) 10398feb0a19SIvan Khoronzhuk cur_budget = budget - num_rx; 10408feb0a19SIvan Khoronzhuk else 10418feb0a19SIvan Khoronzhuk cur_budget = rxv->budget; 10428feb0a19SIvan Khoronzhuk 10438feb0a19SIvan Khoronzhuk num_rx += cpdma_chan_process(rxv->ch, cur_budget); 1044342934a5SIvan Khoronzhuk if (num_rx >= budget) 1045342934a5SIvan Khoronzhuk break; 1046e05107e6SIvan Khoronzhuk } 1047e05107e6SIvan Khoronzhuk 1048510a1e72SMugunthan V N if (num_rx < budget) { 10496ad20165SEric Dumazet napi_complete_done(napi_rx, num_rx); 10505d8d0d4dSIvan Khoronzhuk writel(0xff, &cpsw->wr_regs->rx_en); 10519611d6d6SIvan Khoronzhuk } 10529611d6d6SIvan Khoronzhuk 10539611d6d6SIvan Khoronzhuk return num_rx; 10549611d6d6SIvan Khoronzhuk } 10559611d6d6SIvan Khoronzhuk 10569611d6d6SIvan Khoronzhuk static int cpsw_rx_poll(struct napi_struct *napi_rx, int budget) 10579611d6d6SIvan Khoronzhuk { 10589611d6d6SIvan Khoronzhuk struct cpsw_common *cpsw = napi_to_cpsw(napi_rx); 10599611d6d6SIvan Khoronzhuk int num_rx; 10609611d6d6SIvan Khoronzhuk 10619611d6d6SIvan Khoronzhuk num_rx = cpdma_chan_process(cpsw->rxv[0].ch, budget); 10629611d6d6SIvan Khoronzhuk if (num_rx < budget) { 10639611d6d6SIvan Khoronzhuk napi_complete_done(napi_rx, num_rx); 10649611d6d6SIvan Khoronzhuk writel(0xff, &cpsw->wr_regs->rx_en); 10659611d6d6SIvan Khoronzhuk if (cpsw->rx_irq_disabled) { 1066e38b5a3dSIvan Khoronzhuk cpsw->rx_irq_disabled = false; 1067e38b5a3dSIvan Khoronzhuk enable_irq(cpsw->irqs_table[0]); 10687da11600SMugunthan V N } 1069510a1e72SMugunthan V N } 1070df828598SMugunthan V N 1071df828598SMugunthan V N return num_rx; 1072df828598SMugunthan V N } 1073df828598SMugunthan V N 1074df828598SMugunthan V N static inline void soft_reset(const char *module, void __iomem *reg) 1075df828598SMugunthan V N { 1076df828598SMugunthan V N unsigned long timeout = jiffies + HZ; 1077df828598SMugunthan V N 1078dda5f5feSGrygorii Strashko writel_relaxed(1, reg); 1079df828598SMugunthan V N do { 1080df828598SMugunthan V N cpu_relax(); 1081dda5f5feSGrygorii Strashko } while ((readl_relaxed(reg) & 1) && time_after(timeout, jiffies)); 1082df828598SMugunthan V N 1083dda5f5feSGrygorii Strashko WARN(readl_relaxed(reg) & 1, "failed to soft-reset %s\n", module); 1084df828598SMugunthan V N } 1085df828598SMugunthan V N 1086df828598SMugunthan V N static void cpsw_set_slave_mac(struct cpsw_slave *slave, 1087df828598SMugunthan V N struct cpsw_priv *priv) 1088df828598SMugunthan V N { 10899750a3adSRichard Cochran slave_write(slave, mac_hi(priv->mac_addr), SA_HI); 10909750a3adSRichard Cochran slave_write(slave, mac_lo(priv->mac_addr), SA_LO); 1091df828598SMugunthan V N } 1092df828598SMugunthan V N 109357d90148SIvan Khoronzhuk static bool cpsw_shp_is_off(struct cpsw_priv *priv) 109457d90148SIvan Khoronzhuk { 109557d90148SIvan Khoronzhuk struct cpsw_common *cpsw = priv->cpsw; 109657d90148SIvan Khoronzhuk struct cpsw_slave *slave; 109757d90148SIvan Khoronzhuk u32 shift, mask, val; 109857d90148SIvan Khoronzhuk 109957d90148SIvan Khoronzhuk val = readl_relaxed(&cpsw->regs->ptype); 110057d90148SIvan Khoronzhuk 110157d90148SIvan Khoronzhuk slave = &cpsw->slaves[cpsw_slave_index(cpsw, priv)]; 110257d90148SIvan Khoronzhuk shift = CPSW_FIFO_SHAPE_EN_SHIFT + 3 * slave->slave_num; 110357d90148SIvan Khoronzhuk mask = 7 << shift; 110457d90148SIvan Khoronzhuk val = val & mask; 110557d90148SIvan Khoronzhuk 110657d90148SIvan Khoronzhuk return !val; 110757d90148SIvan Khoronzhuk } 110857d90148SIvan Khoronzhuk 110957d90148SIvan Khoronzhuk static void cpsw_fifo_shp_on(struct cpsw_priv *priv, int fifo, int on) 111057d90148SIvan Khoronzhuk { 111157d90148SIvan Khoronzhuk struct cpsw_common *cpsw = priv->cpsw; 111257d90148SIvan Khoronzhuk struct cpsw_slave *slave; 111357d90148SIvan Khoronzhuk u32 shift, mask, val; 111457d90148SIvan Khoronzhuk 111557d90148SIvan Khoronzhuk val = readl_relaxed(&cpsw->regs->ptype); 111657d90148SIvan Khoronzhuk 111757d90148SIvan Khoronzhuk slave = &cpsw->slaves[cpsw_slave_index(cpsw, priv)]; 111857d90148SIvan Khoronzhuk shift = CPSW_FIFO_SHAPE_EN_SHIFT + 3 * slave->slave_num; 111957d90148SIvan Khoronzhuk mask = (1 << --fifo) << shift; 112057d90148SIvan Khoronzhuk val = on ? val | mask : val & ~mask; 112157d90148SIvan Khoronzhuk 112257d90148SIvan Khoronzhuk writel_relaxed(val, &cpsw->regs->ptype); 112357d90148SIvan Khoronzhuk } 112457d90148SIvan Khoronzhuk 1125df828598SMugunthan V N static void _cpsw_adjust_link(struct cpsw_slave *slave, 1126df828598SMugunthan V N struct cpsw_priv *priv, bool *link) 1127df828598SMugunthan V N { 1128df828598SMugunthan V N struct phy_device *phy = slave->phy; 1129df828598SMugunthan V N u32 mac_control = 0; 1130df828598SMugunthan V N u32 slave_port; 1131606f3993SIvan Khoronzhuk struct cpsw_common *cpsw = priv->cpsw; 1132df828598SMugunthan V N 1133df828598SMugunthan V N if (!phy) 1134df828598SMugunthan V N return; 1135df828598SMugunthan V N 11366f1f5836SIvan Khoronzhuk slave_port = cpsw_get_slave_port(slave->slave_num); 1137df828598SMugunthan V N 1138df828598SMugunthan V N if (phy->link) { 1139606f3993SIvan Khoronzhuk mac_control = cpsw->data.mac_control; 1140df828598SMugunthan V N 1141df828598SMugunthan V N /* enable forwarding */ 11422a05a622SIvan Khoronzhuk cpsw_ale_control_set(cpsw->ale, slave_port, 1143df828598SMugunthan V N ALE_PORT_STATE, ALE_PORT_STATE_FORWARD); 1144df828598SMugunthan V N 1145df828598SMugunthan V N if (phy->speed == 1000) 1146df828598SMugunthan V N mac_control |= BIT(7); /* GIGABITEN */ 1147df828598SMugunthan V N if (phy->duplex) 1148df828598SMugunthan V N mac_control |= BIT(0); /* FULLDUPLEXEN */ 1149342b7b74SDaniel Mack 1150342b7b74SDaniel Mack /* set speed_in input in case RMII mode is used in 100Mbps */ 1151342b7b74SDaniel Mack if (phy->speed == 100) 1152342b7b74SDaniel Mack mac_control |= BIT(15); 1153f9db5069SSZ Lin (林上智) /* in band mode only works in 10Mbps RGMII mode */ 1154f9db5069SSZ Lin (林上智) else if ((phy->speed == 10) && phy_interface_is_rgmii(phy)) 1155a81d8762SMugunthan V N mac_control |= BIT(18); /* In Band mode */ 1156342b7b74SDaniel Mack 11571923d6e4SMugunthan V N if (priv->rx_pause) 11581923d6e4SMugunthan V N mac_control |= BIT(3); 11591923d6e4SMugunthan V N 11601923d6e4SMugunthan V N if (priv->tx_pause) 11611923d6e4SMugunthan V N mac_control |= BIT(4); 11621923d6e4SMugunthan V N 1163df828598SMugunthan V N *link = true; 116457d90148SIvan Khoronzhuk 116557d90148SIvan Khoronzhuk if (priv->shp_cfg_speed && 116657d90148SIvan Khoronzhuk priv->shp_cfg_speed != slave->phy->speed && 116757d90148SIvan Khoronzhuk !cpsw_shp_is_off(priv)) 116857d90148SIvan Khoronzhuk dev_warn(priv->dev, 116957d90148SIvan Khoronzhuk "Speed was changed, CBS shaper speeds are changed!"); 1170df828598SMugunthan V N } else { 1171df828598SMugunthan V N mac_control = 0; 1172df828598SMugunthan V N /* disable forwarding */ 11732a05a622SIvan Khoronzhuk cpsw_ale_control_set(cpsw->ale, slave_port, 1174df828598SMugunthan V N ALE_PORT_STATE, ALE_PORT_STATE_DISABLE); 1175df828598SMugunthan V N } 1176df828598SMugunthan V N 1177df828598SMugunthan V N if (mac_control != slave->mac_control) { 1178df828598SMugunthan V N phy_print_status(phy); 1179dda5f5feSGrygorii Strashko writel_relaxed(mac_control, &slave->sliver->mac_control); 1180df828598SMugunthan V N } 1181df828598SMugunthan V N 1182df828598SMugunthan V N slave->mac_control = mac_control; 1183df828598SMugunthan V N } 1184df828598SMugunthan V N 11850be01b8eSIvan Khoronzhuk static int cpsw_get_common_speed(struct cpsw_common *cpsw) 11860be01b8eSIvan Khoronzhuk { 11870be01b8eSIvan Khoronzhuk int i, speed; 11880be01b8eSIvan Khoronzhuk 11890be01b8eSIvan Khoronzhuk for (i = 0, speed = 0; i < cpsw->data.slaves; i++) 11900be01b8eSIvan Khoronzhuk if (cpsw->slaves[i].phy && cpsw->slaves[i].phy->link) 11910be01b8eSIvan Khoronzhuk speed += cpsw->slaves[i].phy->speed; 11920be01b8eSIvan Khoronzhuk 11930be01b8eSIvan Khoronzhuk return speed; 11940be01b8eSIvan Khoronzhuk } 11950be01b8eSIvan Khoronzhuk 11960be01b8eSIvan Khoronzhuk static int cpsw_need_resplit(struct cpsw_common *cpsw) 11970be01b8eSIvan Khoronzhuk { 11980be01b8eSIvan Khoronzhuk int i, rlim_ch_num; 11990be01b8eSIvan Khoronzhuk int speed, ch_rate; 12000be01b8eSIvan Khoronzhuk 12010be01b8eSIvan Khoronzhuk /* re-split resources only in case speed was changed */ 12020be01b8eSIvan Khoronzhuk speed = cpsw_get_common_speed(cpsw); 12030be01b8eSIvan Khoronzhuk if (speed == cpsw->speed || !speed) 12040be01b8eSIvan Khoronzhuk return 0; 12050be01b8eSIvan Khoronzhuk 12060be01b8eSIvan Khoronzhuk cpsw->speed = speed; 12070be01b8eSIvan Khoronzhuk 12080be01b8eSIvan Khoronzhuk for (i = 0, rlim_ch_num = 0; i < cpsw->tx_ch_num; i++) { 12090be01b8eSIvan Khoronzhuk ch_rate = cpdma_chan_get_rate(cpsw->txv[i].ch); 12100be01b8eSIvan Khoronzhuk if (!ch_rate) 12110be01b8eSIvan Khoronzhuk break; 12120be01b8eSIvan Khoronzhuk 12130be01b8eSIvan Khoronzhuk rlim_ch_num++; 12140be01b8eSIvan Khoronzhuk } 12150be01b8eSIvan Khoronzhuk 12160be01b8eSIvan Khoronzhuk /* cases not dependent on speed */ 12170be01b8eSIvan Khoronzhuk if (!rlim_ch_num || rlim_ch_num == cpsw->tx_ch_num) 12180be01b8eSIvan Khoronzhuk return 0; 12190be01b8eSIvan Khoronzhuk 12200be01b8eSIvan Khoronzhuk return 1; 12210be01b8eSIvan Khoronzhuk } 12220be01b8eSIvan Khoronzhuk 1223df828598SMugunthan V N static void cpsw_adjust_link(struct net_device *ndev) 1224df828598SMugunthan V N { 1225df828598SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 12260be01b8eSIvan Khoronzhuk struct cpsw_common *cpsw = priv->cpsw; 1227df828598SMugunthan V N bool link = false; 1228df828598SMugunthan V N 1229df828598SMugunthan V N for_each_slave(priv, _cpsw_adjust_link, priv, &link); 1230df828598SMugunthan V N 1231df828598SMugunthan V N if (link) { 12320be01b8eSIvan Khoronzhuk if (cpsw_need_resplit(cpsw)) 12330be01b8eSIvan Khoronzhuk cpsw_split_res(ndev); 12340be01b8eSIvan Khoronzhuk 1235df828598SMugunthan V N netif_carrier_on(ndev); 1236df828598SMugunthan V N if (netif_running(ndev)) 1237e05107e6SIvan Khoronzhuk netif_tx_wake_all_queues(ndev); 1238df828598SMugunthan V N } else { 1239df828598SMugunthan V N netif_carrier_off(ndev); 1240e05107e6SIvan Khoronzhuk netif_tx_stop_all_queues(ndev); 1241df828598SMugunthan V N } 1242df828598SMugunthan V N } 1243df828598SMugunthan V N 1244ff5b8ef2SMugunthan V N static int cpsw_get_coalesce(struct net_device *ndev, 1245ff5b8ef2SMugunthan V N struct ethtool_coalesce *coal) 1246ff5b8ef2SMugunthan V N { 12472a05a622SIvan Khoronzhuk struct cpsw_common *cpsw = ndev_to_cpsw(ndev); 1248ff5b8ef2SMugunthan V N 12492a05a622SIvan Khoronzhuk coal->rx_coalesce_usecs = cpsw->coal_intvl; 1250ff5b8ef2SMugunthan V N return 0; 1251ff5b8ef2SMugunthan V N } 1252ff5b8ef2SMugunthan V N 1253ff5b8ef2SMugunthan V N static int cpsw_set_coalesce(struct net_device *ndev, 1254ff5b8ef2SMugunthan V N struct ethtool_coalesce *coal) 1255ff5b8ef2SMugunthan V N { 1256ff5b8ef2SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 1257ff5b8ef2SMugunthan V N u32 int_ctrl; 1258ff5b8ef2SMugunthan V N u32 num_interrupts = 0; 1259ff5b8ef2SMugunthan V N u32 prescale = 0; 1260ff5b8ef2SMugunthan V N u32 addnl_dvdr = 1; 1261ff5b8ef2SMugunthan V N u32 coal_intvl = 0; 12625d8d0d4dSIvan Khoronzhuk struct cpsw_common *cpsw = priv->cpsw; 1263ff5b8ef2SMugunthan V N 1264ff5b8ef2SMugunthan V N coal_intvl = coal->rx_coalesce_usecs; 1265ff5b8ef2SMugunthan V N 12665d8d0d4dSIvan Khoronzhuk int_ctrl = readl(&cpsw->wr_regs->int_control); 12672a05a622SIvan Khoronzhuk prescale = cpsw->bus_freq_mhz * 4; 1268ff5b8ef2SMugunthan V N 1269a84bc2a9SMugunthan V N if (!coal->rx_coalesce_usecs) { 1270a84bc2a9SMugunthan V N int_ctrl &= ~(CPSW_INTPRESCALE_MASK | CPSW_INTPACEEN); 1271a84bc2a9SMugunthan V N goto update_return; 1272a84bc2a9SMugunthan V N } 1273a84bc2a9SMugunthan V N 1274ff5b8ef2SMugunthan V N if (coal_intvl < CPSW_CMINTMIN_INTVL) 1275ff5b8ef2SMugunthan V N coal_intvl = CPSW_CMINTMIN_INTVL; 1276ff5b8ef2SMugunthan V N 1277ff5b8ef2SMugunthan V N if (coal_intvl > CPSW_CMINTMAX_INTVL) { 1278ff5b8ef2SMugunthan V N /* Interrupt pacer works with 4us Pulse, we can 1279ff5b8ef2SMugunthan V N * throttle further by dilating the 4us pulse. 1280ff5b8ef2SMugunthan V N */ 1281ff5b8ef2SMugunthan V N addnl_dvdr = CPSW_INTPRESCALE_MASK / prescale; 1282ff5b8ef2SMugunthan V N 1283ff5b8ef2SMugunthan V N if (addnl_dvdr > 1) { 1284ff5b8ef2SMugunthan V N prescale *= addnl_dvdr; 1285ff5b8ef2SMugunthan V N if (coal_intvl > (CPSW_CMINTMAX_INTVL * addnl_dvdr)) 1286ff5b8ef2SMugunthan V N coal_intvl = (CPSW_CMINTMAX_INTVL 1287ff5b8ef2SMugunthan V N * addnl_dvdr); 1288ff5b8ef2SMugunthan V N } else { 1289ff5b8ef2SMugunthan V N addnl_dvdr = 1; 1290ff5b8ef2SMugunthan V N coal_intvl = CPSW_CMINTMAX_INTVL; 1291ff5b8ef2SMugunthan V N } 1292ff5b8ef2SMugunthan V N } 1293ff5b8ef2SMugunthan V N 1294ff5b8ef2SMugunthan V N num_interrupts = (1000 * addnl_dvdr) / coal_intvl; 12955d8d0d4dSIvan Khoronzhuk writel(num_interrupts, &cpsw->wr_regs->rx_imax); 12965d8d0d4dSIvan Khoronzhuk writel(num_interrupts, &cpsw->wr_regs->tx_imax); 1297ff5b8ef2SMugunthan V N 1298ff5b8ef2SMugunthan V N int_ctrl |= CPSW_INTPACEEN; 1299ff5b8ef2SMugunthan V N int_ctrl &= (~CPSW_INTPRESCALE_MASK); 1300ff5b8ef2SMugunthan V N int_ctrl |= (prescale & CPSW_INTPRESCALE_MASK); 1301a84bc2a9SMugunthan V N 1302a84bc2a9SMugunthan V N update_return: 13035d8d0d4dSIvan Khoronzhuk writel(int_ctrl, &cpsw->wr_regs->int_control); 1304ff5b8ef2SMugunthan V N 1305ff5b8ef2SMugunthan V N cpsw_notice(priv, timer, "Set coalesce to %d usecs.\n", coal_intvl); 13062a05a622SIvan Khoronzhuk cpsw->coal_intvl = coal_intvl; 1307ff5b8ef2SMugunthan V N 1308ff5b8ef2SMugunthan V N return 0; 1309ff5b8ef2SMugunthan V N } 1310ff5b8ef2SMugunthan V N 1311d9718546SMugunthan V N static int cpsw_get_sset_count(struct net_device *ndev, int sset) 1312d9718546SMugunthan V N { 1313e05107e6SIvan Khoronzhuk struct cpsw_common *cpsw = ndev_to_cpsw(ndev); 1314e05107e6SIvan Khoronzhuk 1315d9718546SMugunthan V N switch (sset) { 1316d9718546SMugunthan V N case ETH_SS_STATS: 1317e05107e6SIvan Khoronzhuk return (CPSW_STATS_COMMON_LEN + 1318e05107e6SIvan Khoronzhuk (cpsw->rx_ch_num + cpsw->tx_ch_num) * 1319e05107e6SIvan Khoronzhuk CPSW_STATS_CH_LEN); 1320d9718546SMugunthan V N default: 1321d9718546SMugunthan V N return -EOPNOTSUPP; 1322d9718546SMugunthan V N } 1323d9718546SMugunthan V N } 1324d9718546SMugunthan V N 1325e05107e6SIvan Khoronzhuk static void cpsw_add_ch_strings(u8 **p, int ch_num, int rx_dir) 1326e05107e6SIvan Khoronzhuk { 1327e05107e6SIvan Khoronzhuk int ch_stats_len; 1328e05107e6SIvan Khoronzhuk int line; 1329e05107e6SIvan Khoronzhuk int i; 1330e05107e6SIvan Khoronzhuk 1331e05107e6SIvan Khoronzhuk ch_stats_len = CPSW_STATS_CH_LEN * ch_num; 1332e05107e6SIvan Khoronzhuk for (i = 0; i < ch_stats_len; i++) { 1333e05107e6SIvan Khoronzhuk line = i % CPSW_STATS_CH_LEN; 1334e05107e6SIvan Khoronzhuk snprintf(*p, ETH_GSTRING_LEN, 1335bf2ce3fdSFlorian Fainelli "%s DMA chan %ld: %s", rx_dir ? "Rx" : "Tx", 1336bf2ce3fdSFlorian Fainelli (long)(i / CPSW_STATS_CH_LEN), 1337e05107e6SIvan Khoronzhuk cpsw_gstrings_ch_stats[line].stat_string); 1338e05107e6SIvan Khoronzhuk *p += ETH_GSTRING_LEN; 1339e05107e6SIvan Khoronzhuk } 1340e05107e6SIvan Khoronzhuk } 1341e05107e6SIvan Khoronzhuk 1342d9718546SMugunthan V N static void cpsw_get_strings(struct net_device *ndev, u32 stringset, u8 *data) 1343d9718546SMugunthan V N { 1344e05107e6SIvan Khoronzhuk struct cpsw_common *cpsw = ndev_to_cpsw(ndev); 1345d9718546SMugunthan V N u8 *p = data; 1346d9718546SMugunthan V N int i; 1347d9718546SMugunthan V N 1348d9718546SMugunthan V N switch (stringset) { 1349d9718546SMugunthan V N case ETH_SS_STATS: 1350e05107e6SIvan Khoronzhuk for (i = 0; i < CPSW_STATS_COMMON_LEN; i++) { 1351d9718546SMugunthan V N memcpy(p, cpsw_gstrings_stats[i].stat_string, 1352d9718546SMugunthan V N ETH_GSTRING_LEN); 1353d9718546SMugunthan V N p += ETH_GSTRING_LEN; 1354d9718546SMugunthan V N } 1355e05107e6SIvan Khoronzhuk 1356e05107e6SIvan Khoronzhuk cpsw_add_ch_strings(&p, cpsw->rx_ch_num, 1); 1357e05107e6SIvan Khoronzhuk cpsw_add_ch_strings(&p, cpsw->tx_ch_num, 0); 1358d9718546SMugunthan V N break; 1359d9718546SMugunthan V N } 1360d9718546SMugunthan V N } 1361d9718546SMugunthan V N 1362d9718546SMugunthan V N static void cpsw_get_ethtool_stats(struct net_device *ndev, 1363d9718546SMugunthan V N struct ethtool_stats *stats, u64 *data) 1364d9718546SMugunthan V N { 1365d9718546SMugunthan V N u8 *p; 13662c836bd9SIvan Khoronzhuk struct cpsw_common *cpsw = ndev_to_cpsw(ndev); 1367e05107e6SIvan Khoronzhuk struct cpdma_chan_stats ch_stats; 1368e05107e6SIvan Khoronzhuk int i, l, ch; 1369d9718546SMugunthan V N 1370d9718546SMugunthan V N /* Collect Davinci CPDMA stats for Rx and Tx Channel */ 1371e05107e6SIvan Khoronzhuk for (l = 0; l < CPSW_STATS_COMMON_LEN; l++) 1372e05107e6SIvan Khoronzhuk data[l] = readl(cpsw->hw_stats + 1373e05107e6SIvan Khoronzhuk cpsw_gstrings_stats[l].stat_offset); 1374d9718546SMugunthan V N 1375e05107e6SIvan Khoronzhuk for (ch = 0; ch < cpsw->rx_ch_num; ch++) { 13768feb0a19SIvan Khoronzhuk cpdma_chan_get_stats(cpsw->rxv[ch].ch, &ch_stats); 1377e05107e6SIvan Khoronzhuk for (i = 0; i < CPSW_STATS_CH_LEN; i++, l++) { 1378e05107e6SIvan Khoronzhuk p = (u8 *)&ch_stats + 1379e05107e6SIvan Khoronzhuk cpsw_gstrings_ch_stats[i].stat_offset; 1380e05107e6SIvan Khoronzhuk data[l] = *(u32 *)p; 1381e05107e6SIvan Khoronzhuk } 1382e05107e6SIvan Khoronzhuk } 1383d9718546SMugunthan V N 1384e05107e6SIvan Khoronzhuk for (ch = 0; ch < cpsw->tx_ch_num; ch++) { 13858feb0a19SIvan Khoronzhuk cpdma_chan_get_stats(cpsw->txv[ch].ch, &ch_stats); 1386e05107e6SIvan Khoronzhuk for (i = 0; i < CPSW_STATS_CH_LEN; i++, l++) { 1387e05107e6SIvan Khoronzhuk p = (u8 *)&ch_stats + 1388e05107e6SIvan Khoronzhuk cpsw_gstrings_ch_stats[i].stat_offset; 1389e05107e6SIvan Khoronzhuk data[l] = *(u32 *)p; 1390d9718546SMugunthan V N } 1391d9718546SMugunthan V N } 1392d9718546SMugunthan V N } 1393d9718546SMugunthan V N 139427e9e103SIvan Khoronzhuk static inline int cpsw_tx_packet_submit(struct cpsw_priv *priv, 1395e05107e6SIvan Khoronzhuk struct sk_buff *skb, 1396e05107e6SIvan Khoronzhuk struct cpdma_chan *txch) 1397d9ba8f9eSMugunthan V N { 13982c836bd9SIvan Khoronzhuk struct cpsw_common *cpsw = priv->cpsw; 13992c836bd9SIvan Khoronzhuk 140098fdd857SIvan Khoronzhuk skb_tx_timestamp(skb); 1401e05107e6SIvan Khoronzhuk return cpdma_chan_submit(txch, skb, skb->data, skb->len, 1402606f3993SIvan Khoronzhuk priv->emac_port + cpsw->data.dual_emac); 1403d9ba8f9eSMugunthan V N } 1404d9ba8f9eSMugunthan V N 1405d9ba8f9eSMugunthan V N static inline void cpsw_add_dual_emac_def_ale_entries( 1406d9ba8f9eSMugunthan V N struct cpsw_priv *priv, struct cpsw_slave *slave, 1407d9ba8f9eSMugunthan V N u32 slave_port) 1408d9ba8f9eSMugunthan V N { 14092a05a622SIvan Khoronzhuk struct cpsw_common *cpsw = priv->cpsw; 141071a2cbb7SGrygorii Strashko u32 port_mask = 1 << slave_port | ALE_PORT_HOST; 1411d9ba8f9eSMugunthan V N 14122a05a622SIvan Khoronzhuk if (cpsw->version == CPSW_VERSION_1) 1413d9ba8f9eSMugunthan V N slave_write(slave, slave->port_vlan, CPSW1_PORT_VLAN); 1414d9ba8f9eSMugunthan V N else 1415d9ba8f9eSMugunthan V N slave_write(slave, slave->port_vlan, CPSW2_PORT_VLAN); 14162a05a622SIvan Khoronzhuk cpsw_ale_add_vlan(cpsw->ale, slave->port_vlan, port_mask, 1417d9ba8f9eSMugunthan V N port_mask, port_mask, 0); 14182a05a622SIvan Khoronzhuk cpsw_ale_add_mcast(cpsw->ale, priv->ndev->broadcast, 1419d9ba8f9eSMugunthan V N port_mask, ALE_VLAN, slave->port_vlan, 0); 14202a05a622SIvan Khoronzhuk cpsw_ale_add_ucast(cpsw->ale, priv->mac_addr, 14212a05a622SIvan Khoronzhuk HOST_PORT_NUM, ALE_VLAN | 14222a05a622SIvan Khoronzhuk ALE_SECURE, slave->port_vlan); 14235e5add17SGrygorii Strashko cpsw_ale_control_set(cpsw->ale, slave_port, 14245e5add17SGrygorii Strashko ALE_PORT_DROP_UNKNOWN_VLAN, 1); 1425d9ba8f9eSMugunthan V N } 1426d9ba8f9eSMugunthan V N 14271e7a2e21SDaniel Mack static void soft_reset_slave(struct cpsw_slave *slave) 1428df828598SMugunthan V N { 1429df828598SMugunthan V N char name[32]; 14301e7a2e21SDaniel Mack 14311e7a2e21SDaniel Mack snprintf(name, sizeof(name), "slave-%d", slave->slave_num); 14321e7a2e21SDaniel Mack soft_reset(name, &slave->sliver->soft_reset); 14331e7a2e21SDaniel Mack } 14341e7a2e21SDaniel Mack 14351e7a2e21SDaniel Mack static void cpsw_slave_open(struct cpsw_slave *slave, struct cpsw_priv *priv) 14361e7a2e21SDaniel Mack { 1437df828598SMugunthan V N u32 slave_port; 143830c57f07SSekhar Nori struct phy_device *phy; 1439649a1688SIvan Khoronzhuk struct cpsw_common *cpsw = priv->cpsw; 1440df828598SMugunthan V N 14411e7a2e21SDaniel Mack soft_reset_slave(slave); 1442df828598SMugunthan V N 1443df828598SMugunthan V N /* setup priority mapping */ 1444dda5f5feSGrygorii Strashko writel_relaxed(RX_PRIORITY_MAPPING, &slave->sliver->rx_pri_map); 14459750a3adSRichard Cochran 14462a05a622SIvan Khoronzhuk switch (cpsw->version) { 14479750a3adSRichard Cochran case CPSW_VERSION_1: 14489750a3adSRichard Cochran slave_write(slave, TX_PRIORITY_MAPPING, CPSW1_TX_PRI_MAP); 144948f5bcccSGrygorii Strashko /* Increase RX FIFO size to 5 for supporting fullduplex 145048f5bcccSGrygorii Strashko * flow control mode 145148f5bcccSGrygorii Strashko */ 145248f5bcccSGrygorii Strashko slave_write(slave, 145348f5bcccSGrygorii Strashko (CPSW_MAX_BLKS_TX << CPSW_MAX_BLKS_TX_SHIFT) | 145448f5bcccSGrygorii Strashko CPSW_MAX_BLKS_RX, CPSW1_MAX_BLKS); 14559750a3adSRichard Cochran break; 14569750a3adSRichard Cochran case CPSW_VERSION_2: 1457c193f365SMugunthan V N case CPSW_VERSION_3: 1458926489beSMugunthan V N case CPSW_VERSION_4: 14599750a3adSRichard Cochran slave_write(slave, TX_PRIORITY_MAPPING, CPSW2_TX_PRI_MAP); 146048f5bcccSGrygorii Strashko /* Increase RX FIFO size to 5 for supporting fullduplex 146148f5bcccSGrygorii Strashko * flow control mode 146248f5bcccSGrygorii Strashko */ 146348f5bcccSGrygorii Strashko slave_write(slave, 146448f5bcccSGrygorii Strashko (CPSW_MAX_BLKS_TX << CPSW_MAX_BLKS_TX_SHIFT) | 146548f5bcccSGrygorii Strashko CPSW_MAX_BLKS_RX, CPSW2_MAX_BLKS); 14669750a3adSRichard Cochran break; 14679750a3adSRichard Cochran } 1468df828598SMugunthan V N 1469df828598SMugunthan V N /* setup max packet size, and mac address */ 1470dda5f5feSGrygorii Strashko writel_relaxed(cpsw->rx_packet_max, &slave->sliver->rx_maxlen); 1471df828598SMugunthan V N cpsw_set_slave_mac(slave, priv); 1472df828598SMugunthan V N 1473df828598SMugunthan V N slave->mac_control = 0; /* no link yet */ 1474df828598SMugunthan V N 14756f1f5836SIvan Khoronzhuk slave_port = cpsw_get_slave_port(slave->slave_num); 1476df828598SMugunthan V N 1477606f3993SIvan Khoronzhuk if (cpsw->data.dual_emac) 1478d9ba8f9eSMugunthan V N cpsw_add_dual_emac_def_ale_entries(priv, slave, slave_port); 1479d9ba8f9eSMugunthan V N else 14802a05a622SIvan Khoronzhuk cpsw_ale_add_mcast(cpsw->ale, priv->ndev->broadcast, 1481e11b220fSMugunthan V N 1 << slave_port, 0, 0, ALE_MCAST_FWD_2); 1482df828598SMugunthan V N 1483d733f754SDavid Rivshin if (slave->data->phy_node) { 148430c57f07SSekhar Nori phy = of_phy_connect(priv->ndev, slave->data->phy_node, 14859e42f715SHeiko Schocher &cpsw_adjust_link, 0, slave->data->phy_if); 148630c57f07SSekhar Nori if (!phy) { 1487f7ce9103SRob Herring dev_err(priv->dev, "phy \"%pOF\" not found on slave %d\n", 1488f7ce9103SRob Herring slave->data->phy_node, 1489d733f754SDavid Rivshin slave->slave_num); 1490d733f754SDavid Rivshin return; 1491d733f754SDavid Rivshin } 1492d733f754SDavid Rivshin } else { 149330c57f07SSekhar Nori phy = phy_connect(priv->ndev, slave->data->phy_id, 1494f9a8f83bSFlorian Fainelli &cpsw_adjust_link, slave->data->phy_if); 149530c57f07SSekhar Nori if (IS_ERR(phy)) { 1496d733f754SDavid Rivshin dev_err(priv->dev, 1497d733f754SDavid Rivshin "phy \"%s\" not found on slave %d, err %ld\n", 1498d733f754SDavid Rivshin slave->data->phy_id, slave->slave_num, 149930c57f07SSekhar Nori PTR_ERR(phy)); 1500d733f754SDavid Rivshin return; 1501d733f754SDavid Rivshin } 1502d733f754SDavid Rivshin } 1503d733f754SDavid Rivshin 150430c57f07SSekhar Nori slave->phy = phy; 150530c57f07SSekhar Nori 15062220943aSAndrew Lunn phy_attached_info(slave->phy); 15072220943aSAndrew Lunn 1508df828598SMugunthan V N phy_start(slave->phy); 1509388367a5SMugunthan V N 1510388367a5SMugunthan V N /* Configure GMII_SEL register */ 151156e31bd8SIvan Khoronzhuk cpsw_phy_sel(cpsw->dev, slave->phy->interface, slave->slave_num); 1512df828598SMugunthan V N } 1513df828598SMugunthan V N 15143b72c2feSMugunthan V N static inline void cpsw_add_default_vlan(struct cpsw_priv *priv) 15153b72c2feSMugunthan V N { 1516606f3993SIvan Khoronzhuk struct cpsw_common *cpsw = priv->cpsw; 1517606f3993SIvan Khoronzhuk const int vlan = cpsw->data.default_vlan; 15183b72c2feSMugunthan V N u32 reg; 15193b72c2feSMugunthan V N int i; 15201e5c4bc4SLennart Sorensen int unreg_mcast_mask; 15213b72c2feSMugunthan V N 15222a05a622SIvan Khoronzhuk reg = (cpsw->version == CPSW_VERSION_1) ? CPSW1_PORT_VLAN : 15233b72c2feSMugunthan V N CPSW2_PORT_VLAN; 15243b72c2feSMugunthan V N 15255d8d0d4dSIvan Khoronzhuk writel(vlan, &cpsw->host_port_regs->port_vlan); 15263b72c2feSMugunthan V N 1527606f3993SIvan Khoronzhuk for (i = 0; i < cpsw->data.slaves; i++) 1528606f3993SIvan Khoronzhuk slave_write(cpsw->slaves + i, vlan, reg); 15293b72c2feSMugunthan V N 15301e5c4bc4SLennart Sorensen if (priv->ndev->flags & IFF_ALLMULTI) 15311e5c4bc4SLennart Sorensen unreg_mcast_mask = ALE_ALL_PORTS; 15321e5c4bc4SLennart Sorensen else 15331e5c4bc4SLennart Sorensen unreg_mcast_mask = ALE_PORT_1 | ALE_PORT_2; 15341e5c4bc4SLennart Sorensen 15352a05a622SIvan Khoronzhuk cpsw_ale_add_vlan(cpsw->ale, vlan, ALE_ALL_PORTS, 153661f1cef9SGrygorii Strashko ALE_ALL_PORTS, ALE_ALL_PORTS, 153761f1cef9SGrygorii Strashko unreg_mcast_mask); 15383b72c2feSMugunthan V N } 15393b72c2feSMugunthan V N 1540df828598SMugunthan V N static void cpsw_init_host_port(struct cpsw_priv *priv) 1541df828598SMugunthan V N { 1542d9ba8f9eSMugunthan V N u32 fifo_mode; 15435d8d0d4dSIvan Khoronzhuk u32 control_reg; 15445d8d0d4dSIvan Khoronzhuk struct cpsw_common *cpsw = priv->cpsw; 15453b72c2feSMugunthan V N 1546df828598SMugunthan V N /* soft reset the controller and initialize ale */ 15475d8d0d4dSIvan Khoronzhuk soft_reset("cpsw", &cpsw->regs->soft_reset); 15482a05a622SIvan Khoronzhuk cpsw_ale_start(cpsw->ale); 1549df828598SMugunthan V N 1550df828598SMugunthan V N /* switch to vlan unaware mode */ 15512a05a622SIvan Khoronzhuk cpsw_ale_control_set(cpsw->ale, HOST_PORT_NUM, ALE_VLAN_AWARE, 15523b72c2feSMugunthan V N CPSW_ALE_VLAN_AWARE); 15535d8d0d4dSIvan Khoronzhuk control_reg = readl(&cpsw->regs->control); 1554a3a41d2fSGrygorii Strashko control_reg |= CPSW_VLAN_AWARE | CPSW_RX_VLAN_ENCAP; 15555d8d0d4dSIvan Khoronzhuk writel(control_reg, &cpsw->regs->control); 1556606f3993SIvan Khoronzhuk fifo_mode = (cpsw->data.dual_emac) ? CPSW_FIFO_DUAL_MAC_MODE : 1557d9ba8f9eSMugunthan V N CPSW_FIFO_NORMAL_MODE; 15585d8d0d4dSIvan Khoronzhuk writel(fifo_mode, &cpsw->host_port_regs->tx_in_ctl); 1559df828598SMugunthan V N 1560df828598SMugunthan V N /* setup host port priority mapping */ 1561dda5f5feSGrygorii Strashko writel_relaxed(CPDMA_TX_PRIORITY_MAP, 15625d8d0d4dSIvan Khoronzhuk &cpsw->host_port_regs->cpdma_tx_pri_map); 1563dda5f5feSGrygorii Strashko writel_relaxed(0, &cpsw->host_port_regs->cpdma_rx_chan_map); 1564df828598SMugunthan V N 15652a05a622SIvan Khoronzhuk cpsw_ale_control_set(cpsw->ale, HOST_PORT_NUM, 1566df828598SMugunthan V N ALE_PORT_STATE, ALE_PORT_STATE_FORWARD); 1567df828598SMugunthan V N 1568606f3993SIvan Khoronzhuk if (!cpsw->data.dual_emac) { 15692a05a622SIvan Khoronzhuk cpsw_ale_add_ucast(cpsw->ale, priv->mac_addr, HOST_PORT_NUM, 1570d9ba8f9eSMugunthan V N 0, 0); 15712a05a622SIvan Khoronzhuk cpsw_ale_add_mcast(cpsw->ale, priv->ndev->broadcast, 157271a2cbb7SGrygorii Strashko ALE_PORT_HOST, 0, 0, ALE_MCAST_FWD_2); 1573df828598SMugunthan V N } 1574d9ba8f9eSMugunthan V N } 1575df828598SMugunthan V N 15763802dce1SIvan Khoronzhuk static int cpsw_fill_rx_channels(struct cpsw_priv *priv) 15773802dce1SIvan Khoronzhuk { 15783802dce1SIvan Khoronzhuk struct cpsw_common *cpsw = priv->cpsw; 15793802dce1SIvan Khoronzhuk struct sk_buff *skb; 15803802dce1SIvan Khoronzhuk int ch_buf_num; 1581e05107e6SIvan Khoronzhuk int ch, i, ret; 15823802dce1SIvan Khoronzhuk 1583e05107e6SIvan Khoronzhuk for (ch = 0; ch < cpsw->rx_ch_num; ch++) { 15848feb0a19SIvan Khoronzhuk ch_buf_num = cpdma_chan_get_rx_buf_num(cpsw->rxv[ch].ch); 15853802dce1SIvan Khoronzhuk for (i = 0; i < ch_buf_num; i++) { 15863802dce1SIvan Khoronzhuk skb = __netdev_alloc_skb_ip_align(priv->ndev, 15873802dce1SIvan Khoronzhuk cpsw->rx_packet_max, 15883802dce1SIvan Khoronzhuk GFP_KERNEL); 15893802dce1SIvan Khoronzhuk if (!skb) { 15903802dce1SIvan Khoronzhuk cpsw_err(priv, ifup, "cannot allocate skb\n"); 15913802dce1SIvan Khoronzhuk return -ENOMEM; 15923802dce1SIvan Khoronzhuk } 15933802dce1SIvan Khoronzhuk 1594e05107e6SIvan Khoronzhuk skb_set_queue_mapping(skb, ch); 15958feb0a19SIvan Khoronzhuk ret = cpdma_chan_submit(cpsw->rxv[ch].ch, skb, 15968feb0a19SIvan Khoronzhuk skb->data, skb_tailroom(skb), 15978feb0a19SIvan Khoronzhuk 0); 15983802dce1SIvan Khoronzhuk if (ret < 0) { 15993802dce1SIvan Khoronzhuk cpsw_err(priv, ifup, 1600e05107e6SIvan Khoronzhuk "cannot submit skb to channel %d rx, error %d\n", 1601e05107e6SIvan Khoronzhuk ch, ret); 16023802dce1SIvan Khoronzhuk kfree_skb(skb); 16033802dce1SIvan Khoronzhuk return ret; 16043802dce1SIvan Khoronzhuk } 16053802dce1SIvan Khoronzhuk kmemleak_not_leak(skb); 16063802dce1SIvan Khoronzhuk } 16073802dce1SIvan Khoronzhuk 1608e05107e6SIvan Khoronzhuk cpsw_info(priv, ifup, "ch %d rx, submitted %d descriptors\n", 1609e05107e6SIvan Khoronzhuk ch, ch_buf_num); 1610e05107e6SIvan Khoronzhuk } 16113802dce1SIvan Khoronzhuk 1612e05107e6SIvan Khoronzhuk return 0; 16133802dce1SIvan Khoronzhuk } 16143802dce1SIvan Khoronzhuk 16152a05a622SIvan Khoronzhuk static void cpsw_slave_stop(struct cpsw_slave *slave, struct cpsw_common *cpsw) 1616aacebbf8SSebastian Siewior { 16173995d265SSchuyler Patton u32 slave_port; 16183995d265SSchuyler Patton 16196f1f5836SIvan Khoronzhuk slave_port = cpsw_get_slave_port(slave->slave_num); 16203995d265SSchuyler Patton 1621aacebbf8SSebastian Siewior if (!slave->phy) 1622aacebbf8SSebastian Siewior return; 1623aacebbf8SSebastian Siewior phy_stop(slave->phy); 1624aacebbf8SSebastian Siewior phy_disconnect(slave->phy); 1625aacebbf8SSebastian Siewior slave->phy = NULL; 16262a05a622SIvan Khoronzhuk cpsw_ale_control_set(cpsw->ale, slave_port, 16273995d265SSchuyler Patton ALE_PORT_STATE, ALE_PORT_STATE_DISABLE); 16281f95ba00SGrygorii Strashko soft_reset_slave(slave); 1629aacebbf8SSebastian Siewior } 1630aacebbf8SSebastian Siewior 16317929a668SIvan Khoronzhuk static int cpsw_tc_to_fifo(int tc, int num_tc) 16327929a668SIvan Khoronzhuk { 16337929a668SIvan Khoronzhuk if (tc == num_tc - 1) 16347929a668SIvan Khoronzhuk return 0; 16357929a668SIvan Khoronzhuk 16367929a668SIvan Khoronzhuk return CPSW_FIFO_SHAPERS_NUM - tc; 16377929a668SIvan Khoronzhuk } 16387929a668SIvan Khoronzhuk 163957d90148SIvan Khoronzhuk static int cpsw_set_fifo_bw(struct cpsw_priv *priv, int fifo, int bw) 164057d90148SIvan Khoronzhuk { 164157d90148SIvan Khoronzhuk struct cpsw_common *cpsw = priv->cpsw; 164257d90148SIvan Khoronzhuk u32 val = 0, send_pct, shift; 164357d90148SIvan Khoronzhuk struct cpsw_slave *slave; 164457d90148SIvan Khoronzhuk int pct = 0, i; 164557d90148SIvan Khoronzhuk 164657d90148SIvan Khoronzhuk if (bw > priv->shp_cfg_speed * 1000) 164757d90148SIvan Khoronzhuk goto err; 164857d90148SIvan Khoronzhuk 164957d90148SIvan Khoronzhuk /* shaping has to stay enabled for highest fifos linearly 165057d90148SIvan Khoronzhuk * and fifo bw no more then interface can allow 165157d90148SIvan Khoronzhuk */ 165257d90148SIvan Khoronzhuk slave = &cpsw->slaves[cpsw_slave_index(cpsw, priv)]; 165357d90148SIvan Khoronzhuk send_pct = slave_read(slave, SEND_PERCENT); 165457d90148SIvan Khoronzhuk for (i = CPSW_FIFO_SHAPERS_NUM; i > 0; i--) { 165557d90148SIvan Khoronzhuk if (!bw) { 165657d90148SIvan Khoronzhuk if (i >= fifo || !priv->fifo_bw[i]) 165757d90148SIvan Khoronzhuk continue; 165857d90148SIvan Khoronzhuk 165957d90148SIvan Khoronzhuk dev_warn(priv->dev, "Prev FIFO%d is shaped", i); 166057d90148SIvan Khoronzhuk continue; 166157d90148SIvan Khoronzhuk } 166257d90148SIvan Khoronzhuk 166357d90148SIvan Khoronzhuk if (!priv->fifo_bw[i] && i > fifo) { 166457d90148SIvan Khoronzhuk dev_err(priv->dev, "Upper FIFO%d is not shaped", i); 166557d90148SIvan Khoronzhuk return -EINVAL; 166657d90148SIvan Khoronzhuk } 166757d90148SIvan Khoronzhuk 166857d90148SIvan Khoronzhuk shift = (i - 1) * 8; 166957d90148SIvan Khoronzhuk if (i == fifo) { 167057d90148SIvan Khoronzhuk send_pct &= ~(CPSW_PCT_MASK << shift); 167157d90148SIvan Khoronzhuk val = DIV_ROUND_UP(bw, priv->shp_cfg_speed * 10); 167257d90148SIvan Khoronzhuk if (!val) 167357d90148SIvan Khoronzhuk val = 1; 167457d90148SIvan Khoronzhuk 167557d90148SIvan Khoronzhuk send_pct |= val << shift; 167657d90148SIvan Khoronzhuk pct += val; 167757d90148SIvan Khoronzhuk continue; 167857d90148SIvan Khoronzhuk } 167957d90148SIvan Khoronzhuk 168057d90148SIvan Khoronzhuk if (priv->fifo_bw[i]) 168157d90148SIvan Khoronzhuk pct += (send_pct >> shift) & CPSW_PCT_MASK; 168257d90148SIvan Khoronzhuk } 168357d90148SIvan Khoronzhuk 168457d90148SIvan Khoronzhuk if (pct >= 100) 168557d90148SIvan Khoronzhuk goto err; 168657d90148SIvan Khoronzhuk 168757d90148SIvan Khoronzhuk slave_write(slave, send_pct, SEND_PERCENT); 168857d90148SIvan Khoronzhuk priv->fifo_bw[fifo] = bw; 168957d90148SIvan Khoronzhuk 169057d90148SIvan Khoronzhuk dev_warn(priv->dev, "set FIFO%d bw = %d\n", fifo, 169157d90148SIvan Khoronzhuk DIV_ROUND_CLOSEST(val * priv->shp_cfg_speed, 100)); 169257d90148SIvan Khoronzhuk 169357d90148SIvan Khoronzhuk return 0; 169457d90148SIvan Khoronzhuk err: 169557d90148SIvan Khoronzhuk dev_err(priv->dev, "Bandwidth doesn't fit in tc configuration"); 169657d90148SIvan Khoronzhuk return -EINVAL; 169757d90148SIvan Khoronzhuk } 169857d90148SIvan Khoronzhuk 169957d90148SIvan Khoronzhuk static int cpsw_set_fifo_rlimit(struct cpsw_priv *priv, int fifo, int bw) 170057d90148SIvan Khoronzhuk { 170157d90148SIvan Khoronzhuk struct cpsw_common *cpsw = priv->cpsw; 170257d90148SIvan Khoronzhuk struct cpsw_slave *slave; 170357d90148SIvan Khoronzhuk u32 tx_in_ctl_rg, val; 170457d90148SIvan Khoronzhuk int ret; 170557d90148SIvan Khoronzhuk 170657d90148SIvan Khoronzhuk ret = cpsw_set_fifo_bw(priv, fifo, bw); 170757d90148SIvan Khoronzhuk if (ret) 170857d90148SIvan Khoronzhuk return ret; 170957d90148SIvan Khoronzhuk 171057d90148SIvan Khoronzhuk slave = &cpsw->slaves[cpsw_slave_index(cpsw, priv)]; 171157d90148SIvan Khoronzhuk tx_in_ctl_rg = cpsw->version == CPSW_VERSION_1 ? 171257d90148SIvan Khoronzhuk CPSW1_TX_IN_CTL : CPSW2_TX_IN_CTL; 171357d90148SIvan Khoronzhuk 171457d90148SIvan Khoronzhuk if (!bw) 171557d90148SIvan Khoronzhuk cpsw_fifo_shp_on(priv, fifo, bw); 171657d90148SIvan Khoronzhuk 171757d90148SIvan Khoronzhuk val = slave_read(slave, tx_in_ctl_rg); 171857d90148SIvan Khoronzhuk if (cpsw_shp_is_off(priv)) { 171957d90148SIvan Khoronzhuk /* disable FIFOs rate limited queues */ 172057d90148SIvan Khoronzhuk val &= ~(0xf << CPSW_FIFO_RATE_EN_SHIFT); 172157d90148SIvan Khoronzhuk 172257d90148SIvan Khoronzhuk /* set type of FIFO queues to normal priority mode */ 172357d90148SIvan Khoronzhuk val &= ~(3 << CPSW_FIFO_QUEUE_TYPE_SHIFT); 172457d90148SIvan Khoronzhuk 172557d90148SIvan Khoronzhuk /* set type of FIFO queues to be rate limited */ 172657d90148SIvan Khoronzhuk if (bw) 172757d90148SIvan Khoronzhuk val |= 2 << CPSW_FIFO_QUEUE_TYPE_SHIFT; 172857d90148SIvan Khoronzhuk else 172957d90148SIvan Khoronzhuk priv->shp_cfg_speed = 0; 173057d90148SIvan Khoronzhuk } 173157d90148SIvan Khoronzhuk 173257d90148SIvan Khoronzhuk /* toggle a FIFO rate limited queue */ 173357d90148SIvan Khoronzhuk if (bw) 173457d90148SIvan Khoronzhuk val |= BIT(fifo + CPSW_FIFO_RATE_EN_SHIFT); 173557d90148SIvan Khoronzhuk else 173657d90148SIvan Khoronzhuk val &= ~BIT(fifo + CPSW_FIFO_RATE_EN_SHIFT); 173757d90148SIvan Khoronzhuk slave_write(slave, val, tx_in_ctl_rg); 173857d90148SIvan Khoronzhuk 173957d90148SIvan Khoronzhuk /* FIFO transmit shape enable */ 174057d90148SIvan Khoronzhuk cpsw_fifo_shp_on(priv, fifo, bw); 174157d90148SIvan Khoronzhuk return 0; 174257d90148SIvan Khoronzhuk } 174357d90148SIvan Khoronzhuk 174457d90148SIvan Khoronzhuk /* Defaults: 174557d90148SIvan Khoronzhuk * class A - prio 3 174657d90148SIvan Khoronzhuk * class B - prio 2 174757d90148SIvan Khoronzhuk * shaping for class A should be set first 174857d90148SIvan Khoronzhuk */ 174957d90148SIvan Khoronzhuk static int cpsw_set_cbs(struct net_device *ndev, 175057d90148SIvan Khoronzhuk struct tc_cbs_qopt_offload *qopt) 175157d90148SIvan Khoronzhuk { 175257d90148SIvan Khoronzhuk struct cpsw_priv *priv = netdev_priv(ndev); 175357d90148SIvan Khoronzhuk struct cpsw_common *cpsw = priv->cpsw; 175457d90148SIvan Khoronzhuk struct cpsw_slave *slave; 175557d90148SIvan Khoronzhuk int prev_speed = 0; 175657d90148SIvan Khoronzhuk int tc, ret, fifo; 175757d90148SIvan Khoronzhuk u32 bw = 0; 175857d90148SIvan Khoronzhuk 175957d90148SIvan Khoronzhuk tc = netdev_txq_to_tc(priv->ndev, qopt->queue); 176057d90148SIvan Khoronzhuk 176157d90148SIvan Khoronzhuk /* enable channels in backward order, as highest FIFOs must be rate 176257d90148SIvan Khoronzhuk * limited first and for compliance with CPDMA rate limited channels 176357d90148SIvan Khoronzhuk * that also used in bacward order. FIFO0 cannot be rate limited. 176457d90148SIvan Khoronzhuk */ 176557d90148SIvan Khoronzhuk fifo = cpsw_tc_to_fifo(tc, ndev->num_tc); 176657d90148SIvan Khoronzhuk if (!fifo) { 176757d90148SIvan Khoronzhuk dev_err(priv->dev, "Last tc%d can't be rate limited", tc); 176857d90148SIvan Khoronzhuk return -EINVAL; 176957d90148SIvan Khoronzhuk } 177057d90148SIvan Khoronzhuk 177157d90148SIvan Khoronzhuk /* do nothing, it's disabled anyway */ 177257d90148SIvan Khoronzhuk if (!qopt->enable && !priv->fifo_bw[fifo]) 177357d90148SIvan Khoronzhuk return 0; 177457d90148SIvan Khoronzhuk 177557d90148SIvan Khoronzhuk /* shapers can be set if link speed is known */ 177657d90148SIvan Khoronzhuk slave = &cpsw->slaves[cpsw_slave_index(cpsw, priv)]; 177757d90148SIvan Khoronzhuk if (slave->phy && slave->phy->link) { 177857d90148SIvan Khoronzhuk if (priv->shp_cfg_speed && 177957d90148SIvan Khoronzhuk priv->shp_cfg_speed != slave->phy->speed) 178057d90148SIvan Khoronzhuk prev_speed = priv->shp_cfg_speed; 178157d90148SIvan Khoronzhuk 178257d90148SIvan Khoronzhuk priv->shp_cfg_speed = slave->phy->speed; 178357d90148SIvan Khoronzhuk } 178457d90148SIvan Khoronzhuk 178557d90148SIvan Khoronzhuk if (!priv->shp_cfg_speed) { 178657d90148SIvan Khoronzhuk dev_err(priv->dev, "Link speed is not known"); 178757d90148SIvan Khoronzhuk return -1; 178857d90148SIvan Khoronzhuk } 178957d90148SIvan Khoronzhuk 179057d90148SIvan Khoronzhuk ret = pm_runtime_get_sync(cpsw->dev); 179157d90148SIvan Khoronzhuk if (ret < 0) { 179257d90148SIvan Khoronzhuk pm_runtime_put_noidle(cpsw->dev); 179357d90148SIvan Khoronzhuk return ret; 179457d90148SIvan Khoronzhuk } 179557d90148SIvan Khoronzhuk 179657d90148SIvan Khoronzhuk bw = qopt->enable ? qopt->idleslope : 0; 179757d90148SIvan Khoronzhuk ret = cpsw_set_fifo_rlimit(priv, fifo, bw); 179857d90148SIvan Khoronzhuk if (ret) { 179957d90148SIvan Khoronzhuk priv->shp_cfg_speed = prev_speed; 180057d90148SIvan Khoronzhuk prev_speed = 0; 180157d90148SIvan Khoronzhuk } 180257d90148SIvan Khoronzhuk 180357d90148SIvan Khoronzhuk if (bw && prev_speed) 180457d90148SIvan Khoronzhuk dev_warn(priv->dev, 180557d90148SIvan Khoronzhuk "Speed was changed, CBS shaper speeds are changed!"); 180657d90148SIvan Khoronzhuk 180757d90148SIvan Khoronzhuk pm_runtime_put_sync(cpsw->dev); 180857d90148SIvan Khoronzhuk return ret; 180957d90148SIvan Khoronzhuk } 181057d90148SIvan Khoronzhuk 18114b4255edSIvan Khoronzhuk static void cpsw_cbs_resume(struct cpsw_slave *slave, struct cpsw_priv *priv) 18124b4255edSIvan Khoronzhuk { 18134b4255edSIvan Khoronzhuk int fifo, bw; 18144b4255edSIvan Khoronzhuk 18154b4255edSIvan Khoronzhuk for (fifo = CPSW_FIFO_SHAPERS_NUM; fifo > 0; fifo--) { 18164b4255edSIvan Khoronzhuk bw = priv->fifo_bw[fifo]; 18174b4255edSIvan Khoronzhuk if (!bw) 18184b4255edSIvan Khoronzhuk continue; 18194b4255edSIvan Khoronzhuk 18204b4255edSIvan Khoronzhuk cpsw_set_fifo_rlimit(priv, fifo, bw); 18214b4255edSIvan Khoronzhuk } 18224b4255edSIvan Khoronzhuk } 18234b4255edSIvan Khoronzhuk 18244b4255edSIvan Khoronzhuk static void cpsw_mqprio_resume(struct cpsw_slave *slave, struct cpsw_priv *priv) 18254b4255edSIvan Khoronzhuk { 18264b4255edSIvan Khoronzhuk struct cpsw_common *cpsw = priv->cpsw; 18274b4255edSIvan Khoronzhuk u32 tx_prio_map = 0; 18284b4255edSIvan Khoronzhuk int i, tc, fifo; 18294b4255edSIvan Khoronzhuk u32 tx_prio_rg; 18304b4255edSIvan Khoronzhuk 18314b4255edSIvan Khoronzhuk if (!priv->mqprio_hw) 18324b4255edSIvan Khoronzhuk return; 18334b4255edSIvan Khoronzhuk 18344b4255edSIvan Khoronzhuk for (i = 0; i < 8; i++) { 18354b4255edSIvan Khoronzhuk tc = netdev_get_prio_tc_map(priv->ndev, i); 18364b4255edSIvan Khoronzhuk fifo = CPSW_FIFO_SHAPERS_NUM - tc; 18374b4255edSIvan Khoronzhuk tx_prio_map |= fifo << (4 * i); 18384b4255edSIvan Khoronzhuk } 18394b4255edSIvan Khoronzhuk 18404b4255edSIvan Khoronzhuk tx_prio_rg = cpsw->version == CPSW_VERSION_1 ? 18414b4255edSIvan Khoronzhuk CPSW1_TX_PRI_MAP : CPSW2_TX_PRI_MAP; 18424b4255edSIvan Khoronzhuk 18434b4255edSIvan Khoronzhuk slave_write(slave, tx_prio_map, tx_prio_rg); 18444b4255edSIvan Khoronzhuk } 18454b4255edSIvan Khoronzhuk 18464b4255edSIvan Khoronzhuk /* restore resources after port reset */ 18474b4255edSIvan Khoronzhuk static void cpsw_restore(struct cpsw_priv *priv) 18484b4255edSIvan Khoronzhuk { 18494b4255edSIvan Khoronzhuk /* restore MQPRIO offload */ 18504b4255edSIvan Khoronzhuk for_each_slave(priv, cpsw_mqprio_resume, priv); 18514b4255edSIvan Khoronzhuk 18524b4255edSIvan Khoronzhuk /* restore CBS offload */ 18534b4255edSIvan Khoronzhuk for_each_slave(priv, cpsw_cbs_resume, priv); 18544b4255edSIvan Khoronzhuk } 18554b4255edSIvan Khoronzhuk 1856df828598SMugunthan V N static int cpsw_ndo_open(struct net_device *ndev) 1857df828598SMugunthan V N { 1858df828598SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 1859649a1688SIvan Khoronzhuk struct cpsw_common *cpsw = priv->cpsw; 18603802dce1SIvan Khoronzhuk int ret; 1861df828598SMugunthan V N u32 reg; 1862df828598SMugunthan V N 186356e31bd8SIvan Khoronzhuk ret = pm_runtime_get_sync(cpsw->dev); 1864108a6537SGrygorii Strashko if (ret < 0) { 186556e31bd8SIvan Khoronzhuk pm_runtime_put_noidle(cpsw->dev); 1866108a6537SGrygorii Strashko return ret; 1867108a6537SGrygorii Strashko } 18683fa88c51SGrygorii Strashko 1869df828598SMugunthan V N netif_carrier_off(ndev); 1870df828598SMugunthan V N 1871e05107e6SIvan Khoronzhuk /* Notify the stack of the actual queue counts. */ 1872e05107e6SIvan Khoronzhuk ret = netif_set_real_num_tx_queues(ndev, cpsw->tx_ch_num); 1873e05107e6SIvan Khoronzhuk if (ret) { 1874e05107e6SIvan Khoronzhuk dev_err(priv->dev, "cannot set real number of tx queues\n"); 1875e05107e6SIvan Khoronzhuk goto err_cleanup; 1876e05107e6SIvan Khoronzhuk } 1877e05107e6SIvan Khoronzhuk 1878e05107e6SIvan Khoronzhuk ret = netif_set_real_num_rx_queues(ndev, cpsw->rx_ch_num); 1879e05107e6SIvan Khoronzhuk if (ret) { 1880e05107e6SIvan Khoronzhuk dev_err(priv->dev, "cannot set real number of rx queues\n"); 1881e05107e6SIvan Khoronzhuk goto err_cleanup; 1882e05107e6SIvan Khoronzhuk } 1883e05107e6SIvan Khoronzhuk 18842a05a622SIvan Khoronzhuk reg = cpsw->version; 1885df828598SMugunthan V N 1886df828598SMugunthan V N dev_info(priv->dev, "initializing cpsw version %d.%d (%d)\n", 1887df828598SMugunthan V N CPSW_MAJOR_VERSION(reg), CPSW_MINOR_VERSION(reg), 1888df828598SMugunthan V N CPSW_RTL_VERSION(reg)); 1889df828598SMugunthan V N 1890d5bc1613SIvan Khoronzhuk /* Initialize host and slave ports */ 1891d5bc1613SIvan Khoronzhuk if (!cpsw->usage_count) 1892df828598SMugunthan V N cpsw_init_host_port(priv); 1893df828598SMugunthan V N for_each_slave(priv, cpsw_slave_open, priv); 1894df828598SMugunthan V N 18953b72c2feSMugunthan V N /* Add default VLAN */ 1896606f3993SIvan Khoronzhuk if (!cpsw->data.dual_emac) 18973b72c2feSMugunthan V N cpsw_add_default_vlan(priv); 1898e6afea0bSMugunthan V N else 18992a05a622SIvan Khoronzhuk cpsw_ale_add_vlan(cpsw->ale, cpsw->data.default_vlan, 190061f1cef9SGrygorii Strashko ALE_ALL_PORTS, ALE_ALL_PORTS, 0, 0); 19013b72c2feSMugunthan V N 1902d5bc1613SIvan Khoronzhuk /* initialize shared resources for every ndev */ 1903d5bc1613SIvan Khoronzhuk if (!cpsw->usage_count) { 1904d9ba8f9eSMugunthan V N /* disable priority elevation */ 1905dda5f5feSGrygorii Strashko writel_relaxed(0, &cpsw->regs->ptype); 1906df828598SMugunthan V N 1907d9ba8f9eSMugunthan V N /* enable statistics collection only on all ports */ 1908dda5f5feSGrygorii Strashko writel_relaxed(0x7, &cpsw->regs->stat_port_en); 1909df828598SMugunthan V N 19101923d6e4SMugunthan V N /* Enable internal fifo flow control */ 19115d8d0d4dSIvan Khoronzhuk writel(0x7, &cpsw->regs->flow_control); 19121923d6e4SMugunthan V N 1913dbc4ec52SIvan Khoronzhuk napi_enable(&cpsw->napi_rx); 1914dbc4ec52SIvan Khoronzhuk napi_enable(&cpsw->napi_tx); 1915d354eb85SMugunthan V N 1916e38b5a3dSIvan Khoronzhuk if (cpsw->tx_irq_disabled) { 1917e38b5a3dSIvan Khoronzhuk cpsw->tx_irq_disabled = false; 1918e38b5a3dSIvan Khoronzhuk enable_irq(cpsw->irqs_table[1]); 19197da11600SMugunthan V N } 19207da11600SMugunthan V N 1921e38b5a3dSIvan Khoronzhuk if (cpsw->rx_irq_disabled) { 1922e38b5a3dSIvan Khoronzhuk cpsw->rx_irq_disabled = false; 1923e38b5a3dSIvan Khoronzhuk enable_irq(cpsw->irqs_table[0]); 19247da11600SMugunthan V N } 19257da11600SMugunthan V N 19263802dce1SIvan Khoronzhuk ret = cpsw_fill_rx_channels(priv); 19273802dce1SIvan Khoronzhuk if (ret < 0) 1928aacebbf8SSebastian Siewior goto err_cleanup; 1929f280e89aSMugunthan V N 19308a2c9a5aSGrygorii Strashko if (cpts_register(cpsw->cpts)) 1931f280e89aSMugunthan V N dev_err(priv->dev, "error registering cpts device\n"); 1932f280e89aSMugunthan V N 1933d9ba8f9eSMugunthan V N } 1934df828598SMugunthan V N 19354b4255edSIvan Khoronzhuk cpsw_restore(priv); 19364b4255edSIvan Khoronzhuk 1937ff5b8ef2SMugunthan V N /* Enable Interrupt pacing if configured */ 19382a05a622SIvan Khoronzhuk if (cpsw->coal_intvl != 0) { 1939ff5b8ef2SMugunthan V N struct ethtool_coalesce coal; 1940ff5b8ef2SMugunthan V N 19412a05a622SIvan Khoronzhuk coal.rx_coalesce_usecs = cpsw->coal_intvl; 1942ff5b8ef2SMugunthan V N cpsw_set_coalesce(ndev, &coal); 1943ff5b8ef2SMugunthan V N } 1944ff5b8ef2SMugunthan V N 19452c836bd9SIvan Khoronzhuk cpdma_ctlr_start(cpsw->dma); 19462c836bd9SIvan Khoronzhuk cpsw_intr_enable(cpsw); 1947d5bc1613SIvan Khoronzhuk cpsw->usage_count++; 1948f63a975eSMugunthan V N 1949df828598SMugunthan V N return 0; 1950df828598SMugunthan V N 1951aacebbf8SSebastian Siewior err_cleanup: 19522c836bd9SIvan Khoronzhuk cpdma_ctlr_stop(cpsw->dma); 19532a05a622SIvan Khoronzhuk for_each_slave(priv, cpsw_slave_stop, cpsw); 195456e31bd8SIvan Khoronzhuk pm_runtime_put_sync(cpsw->dev); 1955aacebbf8SSebastian Siewior netif_carrier_off(priv->ndev); 1956aacebbf8SSebastian Siewior return ret; 1957df828598SMugunthan V N } 1958df828598SMugunthan V N 1959df828598SMugunthan V N static int cpsw_ndo_stop(struct net_device *ndev) 1960df828598SMugunthan V N { 1961df828598SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 1962649a1688SIvan Khoronzhuk struct cpsw_common *cpsw = priv->cpsw; 1963df828598SMugunthan V N 1964df828598SMugunthan V N cpsw_info(priv, ifdown, "shutting down cpsw device\n"); 1965e05107e6SIvan Khoronzhuk netif_tx_stop_all_queues(priv->ndev); 1966df828598SMugunthan V N netif_carrier_off(priv->ndev); 1967d9ba8f9eSMugunthan V N 1968d5bc1613SIvan Khoronzhuk if (cpsw->usage_count <= 1) { 1969dbc4ec52SIvan Khoronzhuk napi_disable(&cpsw->napi_rx); 1970dbc4ec52SIvan Khoronzhuk napi_disable(&cpsw->napi_tx); 19712a05a622SIvan Khoronzhuk cpts_unregister(cpsw->cpts); 19722c836bd9SIvan Khoronzhuk cpsw_intr_disable(cpsw); 19732c836bd9SIvan Khoronzhuk cpdma_ctlr_stop(cpsw->dma); 19742a05a622SIvan Khoronzhuk cpsw_ale_stop(cpsw->ale); 1975d9ba8f9eSMugunthan V N } 19762a05a622SIvan Khoronzhuk for_each_slave(priv, cpsw_slave_stop, cpsw); 19770be01b8eSIvan Khoronzhuk 19780be01b8eSIvan Khoronzhuk if (cpsw_need_resplit(cpsw)) 19790be01b8eSIvan Khoronzhuk cpsw_split_res(ndev); 19800be01b8eSIvan Khoronzhuk 1981d5bc1613SIvan Khoronzhuk cpsw->usage_count--; 198256e31bd8SIvan Khoronzhuk pm_runtime_put_sync(cpsw->dev); 1983df828598SMugunthan V N return 0; 1984df828598SMugunthan V N } 1985df828598SMugunthan V N 1986df828598SMugunthan V N static netdev_tx_t cpsw_ndo_start_xmit(struct sk_buff *skb, 1987df828598SMugunthan V N struct net_device *ndev) 1988df828598SMugunthan V N { 1989df828598SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 19902c836bd9SIvan Khoronzhuk struct cpsw_common *cpsw = priv->cpsw; 1991f44f8417SIvan Khoronzhuk struct cpts *cpts = cpsw->cpts; 1992e05107e6SIvan Khoronzhuk struct netdev_queue *txq; 1993e05107e6SIvan Khoronzhuk struct cpdma_chan *txch; 1994e05107e6SIvan Khoronzhuk int ret, q_idx; 1995df828598SMugunthan V N 1996df828598SMugunthan V N if (skb_padto(skb, CPSW_MIN_PACKET_SIZE)) { 1997df828598SMugunthan V N cpsw_err(priv, tx_err, "packet pad failed\n"); 19988dc43ddcSTobias Klauser ndev->stats.tx_dropped++; 19991bf96050SIvan Khoronzhuk return NET_XMIT_DROP; 2000df828598SMugunthan V N } 2001df828598SMugunthan V N 20029232b16dSMugunthan V N if (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP && 2003f44f8417SIvan Khoronzhuk cpts_is_tx_enabled(cpts) && cpts_can_timestamp(cpts, skb)) 20042e5b38abSRichard Cochran skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 20052e5b38abSRichard Cochran 2006e05107e6SIvan Khoronzhuk q_idx = skb_get_queue_mapping(skb); 2007e05107e6SIvan Khoronzhuk if (q_idx >= cpsw->tx_ch_num) 2008e05107e6SIvan Khoronzhuk q_idx = q_idx % cpsw->tx_ch_num; 2009e05107e6SIvan Khoronzhuk 20108feb0a19SIvan Khoronzhuk txch = cpsw->txv[q_idx].ch; 201162f94c21SGrygorii Strashko txq = netdev_get_tx_queue(ndev, q_idx); 2012e05107e6SIvan Khoronzhuk ret = cpsw_tx_packet_submit(priv, skb, txch); 2013df828598SMugunthan V N if (unlikely(ret != 0)) { 2014df828598SMugunthan V N cpsw_err(priv, tx_err, "desc submit failed\n"); 2015df828598SMugunthan V N goto fail; 2016df828598SMugunthan V N } 2017df828598SMugunthan V N 2018fae50823SMugunthan V N /* If there is no more tx desc left free then we need to 2019fae50823SMugunthan V N * tell the kernel to stop sending us tx frames. 2020fae50823SMugunthan V N */ 2021e05107e6SIvan Khoronzhuk if (unlikely(!cpdma_check_free_tx_desc(txch))) { 2022e05107e6SIvan Khoronzhuk netif_tx_stop_queue(txq); 202362f94c21SGrygorii Strashko 202462f94c21SGrygorii Strashko /* Barrier, so that stop_queue visible to other cpus */ 202562f94c21SGrygorii Strashko smp_mb__after_atomic(); 202662f94c21SGrygorii Strashko 202762f94c21SGrygorii Strashko if (cpdma_check_free_tx_desc(txch)) 202862f94c21SGrygorii Strashko netif_tx_wake_queue(txq); 2029e05107e6SIvan Khoronzhuk } 2030fae50823SMugunthan V N 2031df828598SMugunthan V N return NETDEV_TX_OK; 2032df828598SMugunthan V N fail: 20338dc43ddcSTobias Klauser ndev->stats.tx_dropped++; 2034e05107e6SIvan Khoronzhuk netif_tx_stop_queue(txq); 203562f94c21SGrygorii Strashko 203662f94c21SGrygorii Strashko /* Barrier, so that stop_queue visible to other cpus */ 203762f94c21SGrygorii Strashko smp_mb__after_atomic(); 203862f94c21SGrygorii Strashko 203962f94c21SGrygorii Strashko if (cpdma_check_free_tx_desc(txch)) 204062f94c21SGrygorii Strashko netif_tx_wake_queue(txq); 204162f94c21SGrygorii Strashko 2042df828598SMugunthan V N return NETDEV_TX_BUSY; 2043df828598SMugunthan V N } 2044df828598SMugunthan V N 2045c8395d4eSGrygorii Strashko #if IS_ENABLED(CONFIG_TI_CPTS) 20462e5b38abSRichard Cochran 20472a05a622SIvan Khoronzhuk static void cpsw_hwtstamp_v1(struct cpsw_common *cpsw) 20482e5b38abSRichard Cochran { 2049606f3993SIvan Khoronzhuk struct cpsw_slave *slave = &cpsw->slaves[cpsw->data.active_slave]; 20502e5b38abSRichard Cochran u32 ts_en, seq_id; 20512e5b38abSRichard Cochran 2052b63ba58eSGrygorii Strashko if (!cpts_is_tx_enabled(cpsw->cpts) && 2053b63ba58eSGrygorii Strashko !cpts_is_rx_enabled(cpsw->cpts)) { 20542e5b38abSRichard Cochran slave_write(slave, 0, CPSW1_TS_CTL); 20552e5b38abSRichard Cochran return; 20562e5b38abSRichard Cochran } 20572e5b38abSRichard Cochran 20582e5b38abSRichard Cochran seq_id = (30 << CPSW_V1_SEQ_ID_OFS_SHIFT) | ETH_P_1588; 20592e5b38abSRichard Cochran ts_en = EVENT_MSG_BITS << CPSW_V1_MSG_TYPE_OFS; 20602e5b38abSRichard Cochran 2061b63ba58eSGrygorii Strashko if (cpts_is_tx_enabled(cpsw->cpts)) 20622e5b38abSRichard Cochran ts_en |= CPSW_V1_TS_TX_EN; 20632e5b38abSRichard Cochran 2064b63ba58eSGrygorii Strashko if (cpts_is_rx_enabled(cpsw->cpts)) 20652e5b38abSRichard Cochran ts_en |= CPSW_V1_TS_RX_EN; 20662e5b38abSRichard Cochran 20672e5b38abSRichard Cochran slave_write(slave, ts_en, CPSW1_TS_CTL); 20682e5b38abSRichard Cochran slave_write(slave, seq_id, CPSW1_TS_SEQ_LTYPE); 20692e5b38abSRichard Cochran } 20702e5b38abSRichard Cochran 20712e5b38abSRichard Cochran static void cpsw_hwtstamp_v2(struct cpsw_priv *priv) 20722e5b38abSRichard Cochran { 2073d9ba8f9eSMugunthan V N struct cpsw_slave *slave; 20745d8d0d4dSIvan Khoronzhuk struct cpsw_common *cpsw = priv->cpsw; 20752e5b38abSRichard Cochran u32 ctrl, mtype; 20762e5b38abSRichard Cochran 2077cb7d78d0SIvan Khoronzhuk slave = &cpsw->slaves[cpsw_slave_index(cpsw, priv)]; 2078d9ba8f9eSMugunthan V N 20792e5b38abSRichard Cochran ctrl = slave_read(slave, CPSW2_CONTROL); 20802a05a622SIvan Khoronzhuk switch (cpsw->version) { 208109c55372SGeorge Cherian case CPSW_VERSION_2: 208209c55372SGeorge Cherian ctrl &= ~CTRL_V2_ALL_TS_MASK; 20832e5b38abSRichard Cochran 2084b63ba58eSGrygorii Strashko if (cpts_is_tx_enabled(cpsw->cpts)) 208509c55372SGeorge Cherian ctrl |= CTRL_V2_TX_TS_BITS; 20862e5b38abSRichard Cochran 2087b63ba58eSGrygorii Strashko if (cpts_is_rx_enabled(cpsw->cpts)) 208809c55372SGeorge Cherian ctrl |= CTRL_V2_RX_TS_BITS; 208909c55372SGeorge Cherian break; 209009c55372SGeorge Cherian case CPSW_VERSION_3: 209109c55372SGeorge Cherian default: 209209c55372SGeorge Cherian ctrl &= ~CTRL_V3_ALL_TS_MASK; 209309c55372SGeorge Cherian 2094b63ba58eSGrygorii Strashko if (cpts_is_tx_enabled(cpsw->cpts)) 209509c55372SGeorge Cherian ctrl |= CTRL_V3_TX_TS_BITS; 209609c55372SGeorge Cherian 2097b63ba58eSGrygorii Strashko if (cpts_is_rx_enabled(cpsw->cpts)) 209809c55372SGeorge Cherian ctrl |= CTRL_V3_RX_TS_BITS; 209909c55372SGeorge Cherian break; 210009c55372SGeorge Cherian } 21012e5b38abSRichard Cochran 21022e5b38abSRichard Cochran mtype = (30 << TS_SEQ_ID_OFFSET_SHIFT) | EVENT_MSG_BITS; 21032e5b38abSRichard Cochran 21042e5b38abSRichard Cochran slave_write(slave, mtype, CPSW2_TS_SEQ_MTYPE); 21052e5b38abSRichard Cochran slave_write(slave, ctrl, CPSW2_CONTROL); 2106dda5f5feSGrygorii Strashko writel_relaxed(ETH_P_1588, &cpsw->regs->ts_ltype); 21072e5b38abSRichard Cochran } 21082e5b38abSRichard Cochran 2109a5b4145bSBen Hutchings static int cpsw_hwtstamp_set(struct net_device *dev, struct ifreq *ifr) 21102e5b38abSRichard Cochran { 21113177bf6fSMugunthan V N struct cpsw_priv *priv = netdev_priv(dev); 21122e5b38abSRichard Cochran struct hwtstamp_config cfg; 21132a05a622SIvan Khoronzhuk struct cpsw_common *cpsw = priv->cpsw; 21142a05a622SIvan Khoronzhuk struct cpts *cpts = cpsw->cpts; 21152e5b38abSRichard Cochran 21162a05a622SIvan Khoronzhuk if (cpsw->version != CPSW_VERSION_1 && 21172a05a622SIvan Khoronzhuk cpsw->version != CPSW_VERSION_2 && 21182a05a622SIvan Khoronzhuk cpsw->version != CPSW_VERSION_3) 21192ee91e54SBen Hutchings return -EOPNOTSUPP; 21202ee91e54SBen Hutchings 21212e5b38abSRichard Cochran if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg))) 21222e5b38abSRichard Cochran return -EFAULT; 21232e5b38abSRichard Cochran 21242e5b38abSRichard Cochran /* reserved for future extensions */ 21252e5b38abSRichard Cochran if (cfg.flags) 21262e5b38abSRichard Cochran return -EINVAL; 21272e5b38abSRichard Cochran 21282ee91e54SBen Hutchings if (cfg.tx_type != HWTSTAMP_TX_OFF && cfg.tx_type != HWTSTAMP_TX_ON) 21292e5b38abSRichard Cochran return -ERANGE; 21302e5b38abSRichard Cochran 21312e5b38abSRichard Cochran switch (cfg.rx_filter) { 21322e5b38abSRichard Cochran case HWTSTAMP_FILTER_NONE: 2133b63ba58eSGrygorii Strashko cpts_rx_enable(cpts, 0); 21342e5b38abSRichard Cochran break; 21352e5b38abSRichard Cochran case HWTSTAMP_FILTER_ALL: 2136e9523a5aSGrygorii Strashko case HWTSTAMP_FILTER_NTP_ALL: 2137e9523a5aSGrygorii Strashko return -ERANGE; 21382e5b38abSRichard Cochran case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: 21392e5b38abSRichard Cochran case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: 21402e5b38abSRichard Cochran case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: 2141e9523a5aSGrygorii Strashko cpts_rx_enable(cpts, HWTSTAMP_FILTER_PTP_V1_L4_EVENT); 2142e9523a5aSGrygorii Strashko cfg.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT; 2143e9523a5aSGrygorii Strashko break; 21442e5b38abSRichard Cochran case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: 21452e5b38abSRichard Cochran case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 21462e5b38abSRichard Cochran case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 21472e5b38abSRichard Cochran case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: 21482e5b38abSRichard Cochran case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: 21492e5b38abSRichard Cochran case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: 21502e5b38abSRichard Cochran case HWTSTAMP_FILTER_PTP_V2_EVENT: 21512e5b38abSRichard Cochran case HWTSTAMP_FILTER_PTP_V2_SYNC: 21522e5b38abSRichard Cochran case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 2153e9523a5aSGrygorii Strashko cpts_rx_enable(cpts, HWTSTAMP_FILTER_PTP_V2_EVENT); 21542e5b38abSRichard Cochran cfg.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT; 21552e5b38abSRichard Cochran break; 21562e5b38abSRichard Cochran default: 21572e5b38abSRichard Cochran return -ERANGE; 21582e5b38abSRichard Cochran } 21592e5b38abSRichard Cochran 2160b63ba58eSGrygorii Strashko cpts_tx_enable(cpts, cfg.tx_type == HWTSTAMP_TX_ON); 21612ee91e54SBen Hutchings 21622a05a622SIvan Khoronzhuk switch (cpsw->version) { 21632e5b38abSRichard Cochran case CPSW_VERSION_1: 21642a05a622SIvan Khoronzhuk cpsw_hwtstamp_v1(cpsw); 21652e5b38abSRichard Cochran break; 21662e5b38abSRichard Cochran case CPSW_VERSION_2: 2167f7d403cbSGeorge Cherian case CPSW_VERSION_3: 21682e5b38abSRichard Cochran cpsw_hwtstamp_v2(priv); 21692e5b38abSRichard Cochran break; 21702e5b38abSRichard Cochran default: 21712ee91e54SBen Hutchings WARN_ON(1); 21722e5b38abSRichard Cochran } 21732e5b38abSRichard Cochran 21742e5b38abSRichard Cochran return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0; 21752e5b38abSRichard Cochran } 21762e5b38abSRichard Cochran 2177a5b4145bSBen Hutchings static int cpsw_hwtstamp_get(struct net_device *dev, struct ifreq *ifr) 2178a5b4145bSBen Hutchings { 21792a05a622SIvan Khoronzhuk struct cpsw_common *cpsw = ndev_to_cpsw(dev); 21802a05a622SIvan Khoronzhuk struct cpts *cpts = cpsw->cpts; 2181a5b4145bSBen Hutchings struct hwtstamp_config cfg; 2182a5b4145bSBen Hutchings 21832a05a622SIvan Khoronzhuk if (cpsw->version != CPSW_VERSION_1 && 21842a05a622SIvan Khoronzhuk cpsw->version != CPSW_VERSION_2 && 21852a05a622SIvan Khoronzhuk cpsw->version != CPSW_VERSION_3) 2186a5b4145bSBen Hutchings return -EOPNOTSUPP; 2187a5b4145bSBen Hutchings 2188a5b4145bSBen Hutchings cfg.flags = 0; 2189b63ba58eSGrygorii Strashko cfg.tx_type = cpts_is_tx_enabled(cpts) ? 2190b63ba58eSGrygorii Strashko HWTSTAMP_TX_ON : HWTSTAMP_TX_OFF; 2191b63ba58eSGrygorii Strashko cfg.rx_filter = (cpts_is_rx_enabled(cpts) ? 2192e9523a5aSGrygorii Strashko cpts->rx_enable : HWTSTAMP_FILTER_NONE); 2193a5b4145bSBen Hutchings 2194a5b4145bSBen Hutchings return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0; 2195a5b4145bSBen Hutchings } 2196c8395d4eSGrygorii Strashko #else 2197c8395d4eSGrygorii Strashko static int cpsw_hwtstamp_get(struct net_device *dev, struct ifreq *ifr) 2198c8395d4eSGrygorii Strashko { 2199c8395d4eSGrygorii Strashko return -EOPNOTSUPP; 2200c8395d4eSGrygorii Strashko } 2201a5b4145bSBen Hutchings 2202c8395d4eSGrygorii Strashko static int cpsw_hwtstamp_set(struct net_device *dev, struct ifreq *ifr) 2203c8395d4eSGrygorii Strashko { 2204c8395d4eSGrygorii Strashko return -EOPNOTSUPP; 2205c8395d4eSGrygorii Strashko } 22062e5b38abSRichard Cochran #endif /*CONFIG_TI_CPTS*/ 22072e5b38abSRichard Cochran 22082e5b38abSRichard Cochran static int cpsw_ndo_ioctl(struct net_device *dev, struct ifreq *req, int cmd) 22092e5b38abSRichard Cochran { 221011f2c988SMugunthan V N struct cpsw_priv *priv = netdev_priv(dev); 2211606f3993SIvan Khoronzhuk struct cpsw_common *cpsw = priv->cpsw; 2212606f3993SIvan Khoronzhuk int slave_no = cpsw_slave_index(cpsw, priv); 221311f2c988SMugunthan V N 22142e5b38abSRichard Cochran if (!netif_running(dev)) 22152e5b38abSRichard Cochran return -EINVAL; 22162e5b38abSRichard Cochran 221711f2c988SMugunthan V N switch (cmd) { 221811f2c988SMugunthan V N case SIOCSHWTSTAMP: 2219a5b4145bSBen Hutchings return cpsw_hwtstamp_set(dev, req); 2220a5b4145bSBen Hutchings case SIOCGHWTSTAMP: 2221a5b4145bSBen Hutchings return cpsw_hwtstamp_get(dev, req); 22222e5b38abSRichard Cochran } 22232e5b38abSRichard Cochran 2224606f3993SIvan Khoronzhuk if (!cpsw->slaves[slave_no].phy) 2225c1b59947SStefan Sørensen return -EOPNOTSUPP; 2226606f3993SIvan Khoronzhuk return phy_mii_ioctl(cpsw->slaves[slave_no].phy, req, cmd); 222711f2c988SMugunthan V N } 222811f2c988SMugunthan V N 2229df828598SMugunthan V N static void cpsw_ndo_tx_timeout(struct net_device *ndev) 2230df828598SMugunthan V N { 2231df828598SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 22322c836bd9SIvan Khoronzhuk struct cpsw_common *cpsw = priv->cpsw; 2233e05107e6SIvan Khoronzhuk int ch; 2234df828598SMugunthan V N 2235df828598SMugunthan V N cpsw_err(priv, tx_err, "transmit timeout, restarting dma\n"); 22368dc43ddcSTobias Klauser ndev->stats.tx_errors++; 22372c836bd9SIvan Khoronzhuk cpsw_intr_disable(cpsw); 2238e05107e6SIvan Khoronzhuk for (ch = 0; ch < cpsw->tx_ch_num; ch++) { 22398feb0a19SIvan Khoronzhuk cpdma_chan_stop(cpsw->txv[ch].ch); 22408feb0a19SIvan Khoronzhuk cpdma_chan_start(cpsw->txv[ch].ch); 2241e05107e6SIvan Khoronzhuk } 2242e05107e6SIvan Khoronzhuk 22432c836bd9SIvan Khoronzhuk cpsw_intr_enable(cpsw); 224475514b66SGrygorii Strashko netif_trans_update(ndev); 224575514b66SGrygorii Strashko netif_tx_wake_all_queues(ndev); 2246df828598SMugunthan V N } 2247df828598SMugunthan V N 2248dcfd8d58SMugunthan V N static int cpsw_ndo_set_mac_address(struct net_device *ndev, void *p) 2249dcfd8d58SMugunthan V N { 2250dcfd8d58SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 2251dcfd8d58SMugunthan V N struct sockaddr *addr = (struct sockaddr *)p; 2252649a1688SIvan Khoronzhuk struct cpsw_common *cpsw = priv->cpsw; 2253dcfd8d58SMugunthan V N int flags = 0; 2254dcfd8d58SMugunthan V N u16 vid = 0; 2255a6c5d14fSGrygorii Strashko int ret; 2256dcfd8d58SMugunthan V N 2257dcfd8d58SMugunthan V N if (!is_valid_ether_addr(addr->sa_data)) 2258dcfd8d58SMugunthan V N return -EADDRNOTAVAIL; 2259dcfd8d58SMugunthan V N 226056e31bd8SIvan Khoronzhuk ret = pm_runtime_get_sync(cpsw->dev); 2261a6c5d14fSGrygorii Strashko if (ret < 0) { 226256e31bd8SIvan Khoronzhuk pm_runtime_put_noidle(cpsw->dev); 2263a6c5d14fSGrygorii Strashko return ret; 2264a6c5d14fSGrygorii Strashko } 2265a6c5d14fSGrygorii Strashko 2266606f3993SIvan Khoronzhuk if (cpsw->data.dual_emac) { 2267606f3993SIvan Khoronzhuk vid = cpsw->slaves[priv->emac_port].port_vlan; 2268dcfd8d58SMugunthan V N flags = ALE_VLAN; 2269dcfd8d58SMugunthan V N } 2270dcfd8d58SMugunthan V N 22712a05a622SIvan Khoronzhuk cpsw_ale_del_ucast(cpsw->ale, priv->mac_addr, HOST_PORT_NUM, 2272dcfd8d58SMugunthan V N flags, vid); 22732a05a622SIvan Khoronzhuk cpsw_ale_add_ucast(cpsw->ale, addr->sa_data, HOST_PORT_NUM, 2274dcfd8d58SMugunthan V N flags, vid); 2275dcfd8d58SMugunthan V N 2276dcfd8d58SMugunthan V N memcpy(priv->mac_addr, addr->sa_data, ETH_ALEN); 2277dcfd8d58SMugunthan V N memcpy(ndev->dev_addr, priv->mac_addr, ETH_ALEN); 2278dcfd8d58SMugunthan V N for_each_slave(priv, cpsw_set_slave_mac, priv); 2279dcfd8d58SMugunthan V N 228056e31bd8SIvan Khoronzhuk pm_runtime_put(cpsw->dev); 2281a6c5d14fSGrygorii Strashko 2282dcfd8d58SMugunthan V N return 0; 2283dcfd8d58SMugunthan V N } 2284dcfd8d58SMugunthan V N 2285df828598SMugunthan V N #ifdef CONFIG_NET_POLL_CONTROLLER 2286df828598SMugunthan V N static void cpsw_ndo_poll_controller(struct net_device *ndev) 2287df828598SMugunthan V N { 2288dbc4ec52SIvan Khoronzhuk struct cpsw_common *cpsw = ndev_to_cpsw(ndev); 2289df828598SMugunthan V N 2290dbc4ec52SIvan Khoronzhuk cpsw_intr_disable(cpsw); 2291dbc4ec52SIvan Khoronzhuk cpsw_rx_interrupt(cpsw->irqs_table[0], cpsw); 2292dbc4ec52SIvan Khoronzhuk cpsw_tx_interrupt(cpsw->irqs_table[1], cpsw); 2293dbc4ec52SIvan Khoronzhuk cpsw_intr_enable(cpsw); 2294df828598SMugunthan V N } 2295df828598SMugunthan V N #endif 2296df828598SMugunthan V N 22973b72c2feSMugunthan V N static inline int cpsw_add_vlan_ale_entry(struct cpsw_priv *priv, 22983b72c2feSMugunthan V N unsigned short vid) 22993b72c2feSMugunthan V N { 23003b72c2feSMugunthan V N int ret; 23019f6bd8faSMugunthan V N int unreg_mcast_mask = 0; 23029f6bd8faSMugunthan V N u32 port_mask; 2303606f3993SIvan Khoronzhuk struct cpsw_common *cpsw = priv->cpsw; 23049f6bd8faSMugunthan V N 2305606f3993SIvan Khoronzhuk if (cpsw->data.dual_emac) { 23069f6bd8faSMugunthan V N port_mask = (1 << (priv->emac_port + 1)) | ALE_PORT_HOST; 23079f6bd8faSMugunthan V N 23089f6bd8faSMugunthan V N if (priv->ndev->flags & IFF_ALLMULTI) 23099f6bd8faSMugunthan V N unreg_mcast_mask = port_mask; 23109f6bd8faSMugunthan V N } else { 23119f6bd8faSMugunthan V N port_mask = ALE_ALL_PORTS; 23121e5c4bc4SLennart Sorensen 23131e5c4bc4SLennart Sorensen if (priv->ndev->flags & IFF_ALLMULTI) 23141e5c4bc4SLennart Sorensen unreg_mcast_mask = ALE_ALL_PORTS; 23151e5c4bc4SLennart Sorensen else 23161e5c4bc4SLennart Sorensen unreg_mcast_mask = ALE_PORT_1 | ALE_PORT_2; 23179f6bd8faSMugunthan V N } 23183b72c2feSMugunthan V N 23192a05a622SIvan Khoronzhuk ret = cpsw_ale_add_vlan(cpsw->ale, vid, port_mask, 0, port_mask, 232061f1cef9SGrygorii Strashko unreg_mcast_mask); 23213b72c2feSMugunthan V N if (ret != 0) 23223b72c2feSMugunthan V N return ret; 23233b72c2feSMugunthan V N 23242a05a622SIvan Khoronzhuk ret = cpsw_ale_add_ucast(cpsw->ale, priv->mac_addr, 232571a2cbb7SGrygorii Strashko HOST_PORT_NUM, ALE_VLAN, vid); 23263b72c2feSMugunthan V N if (ret != 0) 23273b72c2feSMugunthan V N goto clean_vid; 23283b72c2feSMugunthan V N 23292a05a622SIvan Khoronzhuk ret = cpsw_ale_add_mcast(cpsw->ale, priv->ndev->broadcast, 23309f6bd8faSMugunthan V N port_mask, ALE_VLAN, vid, 0); 23313b72c2feSMugunthan V N if (ret != 0) 23323b72c2feSMugunthan V N goto clean_vlan_ucast; 23333b72c2feSMugunthan V N return 0; 23343b72c2feSMugunthan V N 23353b72c2feSMugunthan V N clean_vlan_ucast: 23362a05a622SIvan Khoronzhuk cpsw_ale_del_ucast(cpsw->ale, priv->mac_addr, 233771a2cbb7SGrygorii Strashko HOST_PORT_NUM, ALE_VLAN, vid); 23383b72c2feSMugunthan V N clean_vid: 23392a05a622SIvan Khoronzhuk cpsw_ale_del_vlan(cpsw->ale, vid, 0); 23403b72c2feSMugunthan V N return ret; 23413b72c2feSMugunthan V N } 23423b72c2feSMugunthan V N 23433b72c2feSMugunthan V N static int cpsw_ndo_vlan_rx_add_vid(struct net_device *ndev, 234480d5c368SPatrick McHardy __be16 proto, u16 vid) 23453b72c2feSMugunthan V N { 23463b72c2feSMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 2347649a1688SIvan Khoronzhuk struct cpsw_common *cpsw = priv->cpsw; 2348a6c5d14fSGrygorii Strashko int ret; 23493b72c2feSMugunthan V N 2350606f3993SIvan Khoronzhuk if (vid == cpsw->data.default_vlan) 23513b72c2feSMugunthan V N return 0; 23523b72c2feSMugunthan V N 235356e31bd8SIvan Khoronzhuk ret = pm_runtime_get_sync(cpsw->dev); 2354a6c5d14fSGrygorii Strashko if (ret < 0) { 235556e31bd8SIvan Khoronzhuk pm_runtime_put_noidle(cpsw->dev); 2356a6c5d14fSGrygorii Strashko return ret; 2357a6c5d14fSGrygorii Strashko } 2358a6c5d14fSGrygorii Strashko 2359606f3993SIvan Khoronzhuk if (cpsw->data.dual_emac) { 236002a54164SMugunthan V N /* In dual EMAC, reserved VLAN id should not be used for 236102a54164SMugunthan V N * creating VLAN interfaces as this can break the dual 236202a54164SMugunthan V N * EMAC port separation 236302a54164SMugunthan V N */ 236402a54164SMugunthan V N int i; 236502a54164SMugunthan V N 2366606f3993SIvan Khoronzhuk for (i = 0; i < cpsw->data.slaves; i++) { 2367606f3993SIvan Khoronzhuk if (vid == cpsw->slaves[i].port_vlan) 236802a54164SMugunthan V N return -EINVAL; 236902a54164SMugunthan V N } 237002a54164SMugunthan V N } 237102a54164SMugunthan V N 23723b72c2feSMugunthan V N dev_info(priv->dev, "Adding vlanid %d to vlan filter\n", vid); 2373a6c5d14fSGrygorii Strashko ret = cpsw_add_vlan_ale_entry(priv, vid); 2374a6c5d14fSGrygorii Strashko 237556e31bd8SIvan Khoronzhuk pm_runtime_put(cpsw->dev); 2376a6c5d14fSGrygorii Strashko return ret; 23773b72c2feSMugunthan V N } 23783b72c2feSMugunthan V N 23793b72c2feSMugunthan V N static int cpsw_ndo_vlan_rx_kill_vid(struct net_device *ndev, 238080d5c368SPatrick McHardy __be16 proto, u16 vid) 23813b72c2feSMugunthan V N { 23823b72c2feSMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 2383649a1688SIvan Khoronzhuk struct cpsw_common *cpsw = priv->cpsw; 23843b72c2feSMugunthan V N int ret; 23853b72c2feSMugunthan V N 2386606f3993SIvan Khoronzhuk if (vid == cpsw->data.default_vlan) 23873b72c2feSMugunthan V N return 0; 23883b72c2feSMugunthan V N 238956e31bd8SIvan Khoronzhuk ret = pm_runtime_get_sync(cpsw->dev); 2390a6c5d14fSGrygorii Strashko if (ret < 0) { 239156e31bd8SIvan Khoronzhuk pm_runtime_put_noidle(cpsw->dev); 2392a6c5d14fSGrygorii Strashko return ret; 2393a6c5d14fSGrygorii Strashko } 2394a6c5d14fSGrygorii Strashko 2395606f3993SIvan Khoronzhuk if (cpsw->data.dual_emac) { 239602a54164SMugunthan V N int i; 239702a54164SMugunthan V N 2398606f3993SIvan Khoronzhuk for (i = 0; i < cpsw->data.slaves; i++) { 2399606f3993SIvan Khoronzhuk if (vid == cpsw->slaves[i].port_vlan) 240002a54164SMugunthan V N return -EINVAL; 240102a54164SMugunthan V N } 240202a54164SMugunthan V N } 240302a54164SMugunthan V N 24043b72c2feSMugunthan V N dev_info(priv->dev, "removing vlanid %d from vlan filter\n", vid); 24052a05a622SIvan Khoronzhuk ret = cpsw_ale_del_vlan(cpsw->ale, vid, 0); 24063b72c2feSMugunthan V N if (ret != 0) 24073b72c2feSMugunthan V N return ret; 24083b72c2feSMugunthan V N 24092a05a622SIvan Khoronzhuk ret = cpsw_ale_del_ucast(cpsw->ale, priv->mac_addr, 241061f1cef9SGrygorii Strashko HOST_PORT_NUM, ALE_VLAN, vid); 24113b72c2feSMugunthan V N if (ret != 0) 24123b72c2feSMugunthan V N return ret; 24133b72c2feSMugunthan V N 24142a05a622SIvan Khoronzhuk ret = cpsw_ale_del_mcast(cpsw->ale, priv->ndev->broadcast, 24153b72c2feSMugunthan V N 0, ALE_VLAN, vid); 241656e31bd8SIvan Khoronzhuk pm_runtime_put(cpsw->dev); 2417a6c5d14fSGrygorii Strashko return ret; 24183b72c2feSMugunthan V N } 24193b72c2feSMugunthan V N 242083fcad0cSIvan Khoronzhuk static int cpsw_ndo_set_tx_maxrate(struct net_device *ndev, int queue, u32 rate) 242183fcad0cSIvan Khoronzhuk { 242283fcad0cSIvan Khoronzhuk struct cpsw_priv *priv = netdev_priv(ndev); 242383fcad0cSIvan Khoronzhuk struct cpsw_common *cpsw = priv->cpsw; 242452986a2fSIvan Khoronzhuk struct cpsw_slave *slave; 242532b78d85SIvan Khoronzhuk u32 min_rate; 242683fcad0cSIvan Khoronzhuk u32 ch_rate; 242752986a2fSIvan Khoronzhuk int i, ret; 242883fcad0cSIvan Khoronzhuk 242983fcad0cSIvan Khoronzhuk ch_rate = netdev_get_tx_queue(ndev, queue)->tx_maxrate; 243083fcad0cSIvan Khoronzhuk if (ch_rate == rate) 243183fcad0cSIvan Khoronzhuk return 0; 243283fcad0cSIvan Khoronzhuk 243332b78d85SIvan Khoronzhuk ch_rate = rate * 1000; 243483fcad0cSIvan Khoronzhuk min_rate = cpdma_chan_get_min_rate(cpsw->dma); 243532b78d85SIvan Khoronzhuk if ((ch_rate < min_rate && ch_rate)) { 243632b78d85SIvan Khoronzhuk dev_err(priv->dev, "The channel rate cannot be less than %dMbps", 243783fcad0cSIvan Khoronzhuk min_rate); 243883fcad0cSIvan Khoronzhuk return -EINVAL; 243983fcad0cSIvan Khoronzhuk } 244083fcad0cSIvan Khoronzhuk 24410be01b8eSIvan Khoronzhuk if (rate > cpsw->speed) { 244232b78d85SIvan Khoronzhuk dev_err(priv->dev, "The channel rate cannot be more than 2Gbps"); 244332b78d85SIvan Khoronzhuk return -EINVAL; 244432b78d85SIvan Khoronzhuk } 244532b78d85SIvan Khoronzhuk 244683fcad0cSIvan Khoronzhuk ret = pm_runtime_get_sync(cpsw->dev); 244783fcad0cSIvan Khoronzhuk if (ret < 0) { 244883fcad0cSIvan Khoronzhuk pm_runtime_put_noidle(cpsw->dev); 244983fcad0cSIvan Khoronzhuk return ret; 245083fcad0cSIvan Khoronzhuk } 245183fcad0cSIvan Khoronzhuk 245232b78d85SIvan Khoronzhuk ret = cpdma_chan_set_rate(cpsw->txv[queue].ch, ch_rate); 245383fcad0cSIvan Khoronzhuk pm_runtime_put(cpsw->dev); 245432b78d85SIvan Khoronzhuk 245532b78d85SIvan Khoronzhuk if (ret) 245632b78d85SIvan Khoronzhuk return ret; 245732b78d85SIvan Khoronzhuk 245852986a2fSIvan Khoronzhuk /* update rates for slaves tx queues */ 245952986a2fSIvan Khoronzhuk for (i = 0; i < cpsw->data.slaves; i++) { 246052986a2fSIvan Khoronzhuk slave = &cpsw->slaves[i]; 246152986a2fSIvan Khoronzhuk if (!slave->ndev) 246252986a2fSIvan Khoronzhuk continue; 246352986a2fSIvan Khoronzhuk 246452986a2fSIvan Khoronzhuk netdev_get_tx_queue(slave->ndev, queue)->tx_maxrate = rate; 246552986a2fSIvan Khoronzhuk } 246652986a2fSIvan Khoronzhuk 246732b78d85SIvan Khoronzhuk cpsw_split_res(ndev); 246883fcad0cSIvan Khoronzhuk return ret; 246983fcad0cSIvan Khoronzhuk } 247083fcad0cSIvan Khoronzhuk 24717929a668SIvan Khoronzhuk static int cpsw_set_mqprio(struct net_device *ndev, void *type_data) 24727929a668SIvan Khoronzhuk { 24737929a668SIvan Khoronzhuk struct tc_mqprio_qopt_offload *mqprio = type_data; 24747929a668SIvan Khoronzhuk struct cpsw_priv *priv = netdev_priv(ndev); 24757929a668SIvan Khoronzhuk struct cpsw_common *cpsw = priv->cpsw; 24767929a668SIvan Khoronzhuk int fifo, num_tc, count, offset; 24777929a668SIvan Khoronzhuk struct cpsw_slave *slave; 24787929a668SIvan Khoronzhuk u32 tx_prio_map = 0; 24797929a668SIvan Khoronzhuk int i, tc, ret; 24807929a668SIvan Khoronzhuk 24817929a668SIvan Khoronzhuk num_tc = mqprio->qopt.num_tc; 24827929a668SIvan Khoronzhuk if (num_tc > CPSW_TC_NUM) 24837929a668SIvan Khoronzhuk return -EINVAL; 24847929a668SIvan Khoronzhuk 24857929a668SIvan Khoronzhuk if (mqprio->mode != TC_MQPRIO_MODE_DCB) 24867929a668SIvan Khoronzhuk return -EINVAL; 24877929a668SIvan Khoronzhuk 24887929a668SIvan Khoronzhuk ret = pm_runtime_get_sync(cpsw->dev); 24897929a668SIvan Khoronzhuk if (ret < 0) { 24907929a668SIvan Khoronzhuk pm_runtime_put_noidle(cpsw->dev); 24917929a668SIvan Khoronzhuk return ret; 24927929a668SIvan Khoronzhuk } 24937929a668SIvan Khoronzhuk 24947929a668SIvan Khoronzhuk if (num_tc) { 24957929a668SIvan Khoronzhuk for (i = 0; i < 8; i++) { 24967929a668SIvan Khoronzhuk tc = mqprio->qopt.prio_tc_map[i]; 24977929a668SIvan Khoronzhuk fifo = cpsw_tc_to_fifo(tc, num_tc); 24987929a668SIvan Khoronzhuk tx_prio_map |= fifo << (4 * i); 24997929a668SIvan Khoronzhuk } 25007929a668SIvan Khoronzhuk 25017929a668SIvan Khoronzhuk netdev_set_num_tc(ndev, num_tc); 25027929a668SIvan Khoronzhuk for (i = 0; i < num_tc; i++) { 25037929a668SIvan Khoronzhuk count = mqprio->qopt.count[i]; 25047929a668SIvan Khoronzhuk offset = mqprio->qopt.offset[i]; 25057929a668SIvan Khoronzhuk netdev_set_tc_queue(ndev, i, count, offset); 25067929a668SIvan Khoronzhuk } 25077929a668SIvan Khoronzhuk } 25087929a668SIvan Khoronzhuk 25097929a668SIvan Khoronzhuk if (!mqprio->qopt.hw) { 25107929a668SIvan Khoronzhuk /* restore default configuration */ 25117929a668SIvan Khoronzhuk netdev_reset_tc(ndev); 25127929a668SIvan Khoronzhuk tx_prio_map = TX_PRIORITY_MAPPING; 25137929a668SIvan Khoronzhuk } 25147929a668SIvan Khoronzhuk 25157929a668SIvan Khoronzhuk priv->mqprio_hw = mqprio->qopt.hw; 25167929a668SIvan Khoronzhuk 25177929a668SIvan Khoronzhuk offset = cpsw->version == CPSW_VERSION_1 ? 25187929a668SIvan Khoronzhuk CPSW1_TX_PRI_MAP : CPSW2_TX_PRI_MAP; 25197929a668SIvan Khoronzhuk 25207929a668SIvan Khoronzhuk slave = &cpsw->slaves[cpsw_slave_index(cpsw, priv)]; 25217929a668SIvan Khoronzhuk slave_write(slave, tx_prio_map, offset); 25227929a668SIvan Khoronzhuk 25237929a668SIvan Khoronzhuk pm_runtime_put_sync(cpsw->dev); 25247929a668SIvan Khoronzhuk 25257929a668SIvan Khoronzhuk return 0; 25267929a668SIvan Khoronzhuk } 25277929a668SIvan Khoronzhuk 25287929a668SIvan Khoronzhuk static int cpsw_ndo_setup_tc(struct net_device *ndev, enum tc_setup_type type, 25297929a668SIvan Khoronzhuk void *type_data) 25307929a668SIvan Khoronzhuk { 25317929a668SIvan Khoronzhuk switch (type) { 253257d90148SIvan Khoronzhuk case TC_SETUP_QDISC_CBS: 253357d90148SIvan Khoronzhuk return cpsw_set_cbs(ndev, type_data); 253457d90148SIvan Khoronzhuk 25357929a668SIvan Khoronzhuk case TC_SETUP_QDISC_MQPRIO: 25367929a668SIvan Khoronzhuk return cpsw_set_mqprio(ndev, type_data); 25377929a668SIvan Khoronzhuk 25387929a668SIvan Khoronzhuk default: 25397929a668SIvan Khoronzhuk return -EOPNOTSUPP; 25407929a668SIvan Khoronzhuk } 25417929a668SIvan Khoronzhuk } 25427929a668SIvan Khoronzhuk 2543df828598SMugunthan V N static const struct net_device_ops cpsw_netdev_ops = { 2544df828598SMugunthan V N .ndo_open = cpsw_ndo_open, 2545df828598SMugunthan V N .ndo_stop = cpsw_ndo_stop, 2546df828598SMugunthan V N .ndo_start_xmit = cpsw_ndo_start_xmit, 2547dcfd8d58SMugunthan V N .ndo_set_mac_address = cpsw_ndo_set_mac_address, 25482e5b38abSRichard Cochran .ndo_do_ioctl = cpsw_ndo_ioctl, 2549df828598SMugunthan V N .ndo_validate_addr = eth_validate_addr, 2550df828598SMugunthan V N .ndo_tx_timeout = cpsw_ndo_tx_timeout, 25515c50a856SMugunthan V N .ndo_set_rx_mode = cpsw_ndo_set_rx_mode, 255283fcad0cSIvan Khoronzhuk .ndo_set_tx_maxrate = cpsw_ndo_set_tx_maxrate, 2553df828598SMugunthan V N #ifdef CONFIG_NET_POLL_CONTROLLER 2554df828598SMugunthan V N .ndo_poll_controller = cpsw_ndo_poll_controller, 2555df828598SMugunthan V N #endif 25563b72c2feSMugunthan V N .ndo_vlan_rx_add_vid = cpsw_ndo_vlan_rx_add_vid, 25573b72c2feSMugunthan V N .ndo_vlan_rx_kill_vid = cpsw_ndo_vlan_rx_kill_vid, 25587929a668SIvan Khoronzhuk .ndo_setup_tc = cpsw_ndo_setup_tc, 2559df828598SMugunthan V N }; 2560df828598SMugunthan V N 256152c4f0ecSMugunthan V N static int cpsw_get_regs_len(struct net_device *ndev) 256252c4f0ecSMugunthan V N { 2563606f3993SIvan Khoronzhuk struct cpsw_common *cpsw = ndev_to_cpsw(ndev); 256452c4f0ecSMugunthan V N 2565606f3993SIvan Khoronzhuk return cpsw->data.ale_entries * ALE_ENTRY_WORDS * sizeof(u32); 256652c4f0ecSMugunthan V N } 256752c4f0ecSMugunthan V N 256852c4f0ecSMugunthan V N static void cpsw_get_regs(struct net_device *ndev, 256952c4f0ecSMugunthan V N struct ethtool_regs *regs, void *p) 257052c4f0ecSMugunthan V N { 257152c4f0ecSMugunthan V N u32 *reg = p; 25722a05a622SIvan Khoronzhuk struct cpsw_common *cpsw = ndev_to_cpsw(ndev); 257352c4f0ecSMugunthan V N 257452c4f0ecSMugunthan V N /* update CPSW IP version */ 25752a05a622SIvan Khoronzhuk regs->version = cpsw->version; 257652c4f0ecSMugunthan V N 25772a05a622SIvan Khoronzhuk cpsw_ale_dump(cpsw->ale, reg); 257852c4f0ecSMugunthan V N } 257952c4f0ecSMugunthan V N 2580df828598SMugunthan V N static void cpsw_get_drvinfo(struct net_device *ndev, 2581df828598SMugunthan V N struct ethtool_drvinfo *info) 2582df828598SMugunthan V N { 2583649a1688SIvan Khoronzhuk struct cpsw_common *cpsw = ndev_to_cpsw(ndev); 258456e31bd8SIvan Khoronzhuk struct platform_device *pdev = to_platform_device(cpsw->dev); 25857826d43fSJiri Pirko 258652c4f0ecSMugunthan V N strlcpy(info->driver, "cpsw", sizeof(info->driver)); 25877826d43fSJiri Pirko strlcpy(info->version, "1.0", sizeof(info->version)); 258856e31bd8SIvan Khoronzhuk strlcpy(info->bus_info, pdev->name, sizeof(info->bus_info)); 2589df828598SMugunthan V N } 2590df828598SMugunthan V N 2591df828598SMugunthan V N static u32 cpsw_get_msglevel(struct net_device *ndev) 2592df828598SMugunthan V N { 2593df828598SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 2594df828598SMugunthan V N return priv->msg_enable; 2595df828598SMugunthan V N } 2596df828598SMugunthan V N 2597df828598SMugunthan V N static void cpsw_set_msglevel(struct net_device *ndev, u32 value) 2598df828598SMugunthan V N { 2599df828598SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 2600df828598SMugunthan V N priv->msg_enable = value; 2601df828598SMugunthan V N } 2602df828598SMugunthan V N 2603c8395d4eSGrygorii Strashko #if IS_ENABLED(CONFIG_TI_CPTS) 26042e5b38abSRichard Cochran static int cpsw_get_ts_info(struct net_device *ndev, 26052e5b38abSRichard Cochran struct ethtool_ts_info *info) 26062e5b38abSRichard Cochran { 26072a05a622SIvan Khoronzhuk struct cpsw_common *cpsw = ndev_to_cpsw(ndev); 26082e5b38abSRichard Cochran 26092e5b38abSRichard Cochran info->so_timestamping = 26102e5b38abSRichard Cochran SOF_TIMESTAMPING_TX_HARDWARE | 26112e5b38abSRichard Cochran SOF_TIMESTAMPING_TX_SOFTWARE | 26122e5b38abSRichard Cochran SOF_TIMESTAMPING_RX_HARDWARE | 26132e5b38abSRichard Cochran SOF_TIMESTAMPING_RX_SOFTWARE | 26142e5b38abSRichard Cochran SOF_TIMESTAMPING_SOFTWARE | 26152e5b38abSRichard Cochran SOF_TIMESTAMPING_RAW_HARDWARE; 26162a05a622SIvan Khoronzhuk info->phc_index = cpsw->cpts->phc_index; 26172e5b38abSRichard Cochran info->tx_types = 26182e5b38abSRichard Cochran (1 << HWTSTAMP_TX_OFF) | 26192e5b38abSRichard Cochran (1 << HWTSTAMP_TX_ON); 26202e5b38abSRichard Cochran info->rx_filters = 26212e5b38abSRichard Cochran (1 << HWTSTAMP_FILTER_NONE) | 2622e9523a5aSGrygorii Strashko (1 << HWTSTAMP_FILTER_PTP_V1_L4_EVENT) | 26232e5b38abSRichard Cochran (1 << HWTSTAMP_FILTER_PTP_V2_EVENT); 2624c8395d4eSGrygorii Strashko return 0; 2625c8395d4eSGrygorii Strashko } 26262e5b38abSRichard Cochran #else 2627c8395d4eSGrygorii Strashko static int cpsw_get_ts_info(struct net_device *ndev, 2628c8395d4eSGrygorii Strashko struct ethtool_ts_info *info) 2629c8395d4eSGrygorii Strashko { 26302e5b38abSRichard Cochran info->so_timestamping = 26312e5b38abSRichard Cochran SOF_TIMESTAMPING_TX_SOFTWARE | 26322e5b38abSRichard Cochran SOF_TIMESTAMPING_RX_SOFTWARE | 26332e5b38abSRichard Cochran SOF_TIMESTAMPING_SOFTWARE; 26342e5b38abSRichard Cochran info->phc_index = -1; 26352e5b38abSRichard Cochran info->tx_types = 0; 26362e5b38abSRichard Cochran info->rx_filters = 0; 26372e5b38abSRichard Cochran return 0; 26382e5b38abSRichard Cochran } 2639c8395d4eSGrygorii Strashko #endif 26402e5b38abSRichard Cochran 26412479876dSPhilippe Reynes static int cpsw_get_link_ksettings(struct net_device *ndev, 26422479876dSPhilippe Reynes struct ethtool_link_ksettings *ecmd) 2643d3bb9c58SMugunthan V N { 2644d3bb9c58SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 2645606f3993SIvan Khoronzhuk struct cpsw_common *cpsw = priv->cpsw; 2646606f3993SIvan Khoronzhuk int slave_no = cpsw_slave_index(cpsw, priv); 2647d3bb9c58SMugunthan V N 26485514174fSyuval.shaia@oracle.com if (!cpsw->slaves[slave_no].phy) 2649d3bb9c58SMugunthan V N return -EOPNOTSUPP; 26505514174fSyuval.shaia@oracle.com 26515514174fSyuval.shaia@oracle.com phy_ethtool_ksettings_get(cpsw->slaves[slave_no].phy, ecmd); 26525514174fSyuval.shaia@oracle.com return 0; 2653d3bb9c58SMugunthan V N } 2654d3bb9c58SMugunthan V N 26552479876dSPhilippe Reynes static int cpsw_set_link_ksettings(struct net_device *ndev, 26562479876dSPhilippe Reynes const struct ethtool_link_ksettings *ecmd) 2657d3bb9c58SMugunthan V N { 2658d3bb9c58SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 2659606f3993SIvan Khoronzhuk struct cpsw_common *cpsw = priv->cpsw; 2660606f3993SIvan Khoronzhuk int slave_no = cpsw_slave_index(cpsw, priv); 2661d3bb9c58SMugunthan V N 2662606f3993SIvan Khoronzhuk if (cpsw->slaves[slave_no].phy) 26632479876dSPhilippe Reynes return phy_ethtool_ksettings_set(cpsw->slaves[slave_no].phy, 26642479876dSPhilippe Reynes ecmd); 2665d3bb9c58SMugunthan V N else 2666d3bb9c58SMugunthan V N return -EOPNOTSUPP; 2667d3bb9c58SMugunthan V N } 2668d3bb9c58SMugunthan V N 2669d8a64420SMatus Ujhelyi static void cpsw_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol) 2670d8a64420SMatus Ujhelyi { 2671d8a64420SMatus Ujhelyi struct cpsw_priv *priv = netdev_priv(ndev); 2672606f3993SIvan Khoronzhuk struct cpsw_common *cpsw = priv->cpsw; 2673606f3993SIvan Khoronzhuk int slave_no = cpsw_slave_index(cpsw, priv); 2674d8a64420SMatus Ujhelyi 2675d8a64420SMatus Ujhelyi wol->supported = 0; 2676d8a64420SMatus Ujhelyi wol->wolopts = 0; 2677d8a64420SMatus Ujhelyi 2678606f3993SIvan Khoronzhuk if (cpsw->slaves[slave_no].phy) 2679606f3993SIvan Khoronzhuk phy_ethtool_get_wol(cpsw->slaves[slave_no].phy, wol); 2680d8a64420SMatus Ujhelyi } 2681d8a64420SMatus Ujhelyi 2682d8a64420SMatus Ujhelyi static int cpsw_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol) 2683d8a64420SMatus Ujhelyi { 2684d8a64420SMatus Ujhelyi struct cpsw_priv *priv = netdev_priv(ndev); 2685606f3993SIvan Khoronzhuk struct cpsw_common *cpsw = priv->cpsw; 2686606f3993SIvan Khoronzhuk int slave_no = cpsw_slave_index(cpsw, priv); 2687d8a64420SMatus Ujhelyi 2688606f3993SIvan Khoronzhuk if (cpsw->slaves[slave_no].phy) 2689606f3993SIvan Khoronzhuk return phy_ethtool_set_wol(cpsw->slaves[slave_no].phy, wol); 2690d8a64420SMatus Ujhelyi else 2691d8a64420SMatus Ujhelyi return -EOPNOTSUPP; 2692d8a64420SMatus Ujhelyi } 2693d8a64420SMatus Ujhelyi 26941923d6e4SMugunthan V N static void cpsw_get_pauseparam(struct net_device *ndev, 26951923d6e4SMugunthan V N struct ethtool_pauseparam *pause) 26961923d6e4SMugunthan V N { 26971923d6e4SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 26981923d6e4SMugunthan V N 26991923d6e4SMugunthan V N pause->autoneg = AUTONEG_DISABLE; 27001923d6e4SMugunthan V N pause->rx_pause = priv->rx_pause ? true : false; 27011923d6e4SMugunthan V N pause->tx_pause = priv->tx_pause ? true : false; 27021923d6e4SMugunthan V N } 27031923d6e4SMugunthan V N 27041923d6e4SMugunthan V N static int cpsw_set_pauseparam(struct net_device *ndev, 27051923d6e4SMugunthan V N struct ethtool_pauseparam *pause) 27061923d6e4SMugunthan V N { 27071923d6e4SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 27081923d6e4SMugunthan V N bool link; 27091923d6e4SMugunthan V N 27101923d6e4SMugunthan V N priv->rx_pause = pause->rx_pause ? true : false; 27111923d6e4SMugunthan V N priv->tx_pause = pause->tx_pause ? true : false; 27121923d6e4SMugunthan V N 27131923d6e4SMugunthan V N for_each_slave(priv, _cpsw_adjust_link, priv, &link); 27141923d6e4SMugunthan V N return 0; 27151923d6e4SMugunthan V N } 27161923d6e4SMugunthan V N 27177898b1daSGrygorii Strashko static int cpsw_ethtool_op_begin(struct net_device *ndev) 27187898b1daSGrygorii Strashko { 27197898b1daSGrygorii Strashko struct cpsw_priv *priv = netdev_priv(ndev); 2720649a1688SIvan Khoronzhuk struct cpsw_common *cpsw = priv->cpsw; 27217898b1daSGrygorii Strashko int ret; 27227898b1daSGrygorii Strashko 272356e31bd8SIvan Khoronzhuk ret = pm_runtime_get_sync(cpsw->dev); 27247898b1daSGrygorii Strashko if (ret < 0) { 27257898b1daSGrygorii Strashko cpsw_err(priv, drv, "ethtool begin failed %d\n", ret); 272656e31bd8SIvan Khoronzhuk pm_runtime_put_noidle(cpsw->dev); 27277898b1daSGrygorii Strashko } 27287898b1daSGrygorii Strashko 27297898b1daSGrygorii Strashko return ret; 27307898b1daSGrygorii Strashko } 27317898b1daSGrygorii Strashko 27327898b1daSGrygorii Strashko static void cpsw_ethtool_op_complete(struct net_device *ndev) 27337898b1daSGrygorii Strashko { 27347898b1daSGrygorii Strashko struct cpsw_priv *priv = netdev_priv(ndev); 27357898b1daSGrygorii Strashko int ret; 27367898b1daSGrygorii Strashko 273756e31bd8SIvan Khoronzhuk ret = pm_runtime_put(priv->cpsw->dev); 27387898b1daSGrygorii Strashko if (ret < 0) 27397898b1daSGrygorii Strashko cpsw_err(priv, drv, "ethtool complete failed %d\n", ret); 27407898b1daSGrygorii Strashko } 27417898b1daSGrygorii Strashko 2742ce52c744SIvan Khoronzhuk static void cpsw_get_channels(struct net_device *ndev, 2743ce52c744SIvan Khoronzhuk struct ethtool_channels *ch) 2744ce52c744SIvan Khoronzhuk { 2745ce52c744SIvan Khoronzhuk struct cpsw_common *cpsw = ndev_to_cpsw(ndev); 2746ce52c744SIvan Khoronzhuk 27479611d6d6SIvan Khoronzhuk ch->max_rx = cpsw->quirk_irq ? 1 : CPSW_MAX_QUEUES; 27489611d6d6SIvan Khoronzhuk ch->max_tx = cpsw->quirk_irq ? 1 : CPSW_MAX_QUEUES; 2749ce52c744SIvan Khoronzhuk ch->max_combined = 0; 2750ce52c744SIvan Khoronzhuk ch->max_other = 0; 2751ce52c744SIvan Khoronzhuk ch->other_count = 0; 2752ce52c744SIvan Khoronzhuk ch->rx_count = cpsw->rx_ch_num; 2753ce52c744SIvan Khoronzhuk ch->tx_count = cpsw->tx_ch_num; 2754ce52c744SIvan Khoronzhuk ch->combined_count = 0; 2755ce52c744SIvan Khoronzhuk } 2756ce52c744SIvan Khoronzhuk 2757ce52c744SIvan Khoronzhuk static int cpsw_check_ch_settings(struct cpsw_common *cpsw, 2758ce52c744SIvan Khoronzhuk struct ethtool_channels *ch) 2759ce52c744SIvan Khoronzhuk { 27609611d6d6SIvan Khoronzhuk if (cpsw->quirk_irq) { 27619611d6d6SIvan Khoronzhuk dev_err(cpsw->dev, "Maximum one tx/rx queue is allowed"); 27629611d6d6SIvan Khoronzhuk return -EOPNOTSUPP; 27639611d6d6SIvan Khoronzhuk } 27649611d6d6SIvan Khoronzhuk 2765ce52c744SIvan Khoronzhuk if (ch->combined_count) 2766ce52c744SIvan Khoronzhuk return -EINVAL; 2767ce52c744SIvan Khoronzhuk 2768ce52c744SIvan Khoronzhuk /* verify we have at least one channel in each direction */ 2769ce52c744SIvan Khoronzhuk if (!ch->rx_count || !ch->tx_count) 2770ce52c744SIvan Khoronzhuk return -EINVAL; 2771ce52c744SIvan Khoronzhuk 2772ce52c744SIvan Khoronzhuk if (ch->rx_count > cpsw->data.channels || 2773ce52c744SIvan Khoronzhuk ch->tx_count > cpsw->data.channels) 2774ce52c744SIvan Khoronzhuk return -EINVAL; 2775ce52c744SIvan Khoronzhuk 2776ce52c744SIvan Khoronzhuk return 0; 2777ce52c744SIvan Khoronzhuk } 2778ce52c744SIvan Khoronzhuk 2779ce52c744SIvan Khoronzhuk static int cpsw_update_channels_res(struct cpsw_priv *priv, int ch_num, int rx) 2780ce52c744SIvan Khoronzhuk { 2781ce52c744SIvan Khoronzhuk struct cpsw_common *cpsw = priv->cpsw; 2782ce52c744SIvan Khoronzhuk void (*handler)(void *, int, int); 278383fcad0cSIvan Khoronzhuk struct netdev_queue *queue; 27848feb0a19SIvan Khoronzhuk struct cpsw_vector *vec; 278579b3325dSIvan Khoronzhuk int ret, *ch, vch; 2786ce52c744SIvan Khoronzhuk 2787ce52c744SIvan Khoronzhuk if (rx) { 2788ce52c744SIvan Khoronzhuk ch = &cpsw->rx_ch_num; 27898feb0a19SIvan Khoronzhuk vec = cpsw->rxv; 2790ce52c744SIvan Khoronzhuk handler = cpsw_rx_handler; 2791ce52c744SIvan Khoronzhuk } else { 2792ce52c744SIvan Khoronzhuk ch = &cpsw->tx_ch_num; 27938feb0a19SIvan Khoronzhuk vec = cpsw->txv; 2794ce52c744SIvan Khoronzhuk handler = cpsw_tx_handler; 2795ce52c744SIvan Khoronzhuk } 2796ce52c744SIvan Khoronzhuk 2797ce52c744SIvan Khoronzhuk while (*ch < ch_num) { 279879b3325dSIvan Khoronzhuk vch = rx ? *ch : 7 - *ch; 279979b3325dSIvan Khoronzhuk vec[*ch].ch = cpdma_chan_create(cpsw->dma, vch, handler, rx); 280083fcad0cSIvan Khoronzhuk queue = netdev_get_tx_queue(priv->ndev, *ch); 280183fcad0cSIvan Khoronzhuk queue->tx_maxrate = 0; 2802ce52c744SIvan Khoronzhuk 28038feb0a19SIvan Khoronzhuk if (IS_ERR(vec[*ch].ch)) 28048feb0a19SIvan Khoronzhuk return PTR_ERR(vec[*ch].ch); 2805ce52c744SIvan Khoronzhuk 28068feb0a19SIvan Khoronzhuk if (!vec[*ch].ch) 2807ce52c744SIvan Khoronzhuk return -EINVAL; 2808ce52c744SIvan Khoronzhuk 2809ce52c744SIvan Khoronzhuk cpsw_info(priv, ifup, "created new %d %s channel\n", *ch, 2810ce52c744SIvan Khoronzhuk (rx ? "rx" : "tx")); 2811ce52c744SIvan Khoronzhuk (*ch)++; 2812ce52c744SIvan Khoronzhuk } 2813ce52c744SIvan Khoronzhuk 2814ce52c744SIvan Khoronzhuk while (*ch > ch_num) { 2815ce52c744SIvan Khoronzhuk (*ch)--; 2816ce52c744SIvan Khoronzhuk 28178feb0a19SIvan Khoronzhuk ret = cpdma_chan_destroy(vec[*ch].ch); 2818ce52c744SIvan Khoronzhuk if (ret) 2819ce52c744SIvan Khoronzhuk return ret; 2820ce52c744SIvan Khoronzhuk 2821ce52c744SIvan Khoronzhuk cpsw_info(priv, ifup, "destroyed %d %s channel\n", *ch, 2822ce52c744SIvan Khoronzhuk (rx ? "rx" : "tx")); 2823ce52c744SIvan Khoronzhuk } 2824ce52c744SIvan Khoronzhuk 2825ce52c744SIvan Khoronzhuk return 0; 2826ce52c744SIvan Khoronzhuk } 2827ce52c744SIvan Khoronzhuk 2828ce52c744SIvan Khoronzhuk static int cpsw_update_channels(struct cpsw_priv *priv, 2829ce52c744SIvan Khoronzhuk struct ethtool_channels *ch) 2830ce52c744SIvan Khoronzhuk { 2831ce52c744SIvan Khoronzhuk int ret; 2832ce52c744SIvan Khoronzhuk 2833ce52c744SIvan Khoronzhuk ret = cpsw_update_channels_res(priv, ch->rx_count, 1); 2834ce52c744SIvan Khoronzhuk if (ret) 2835ce52c744SIvan Khoronzhuk return ret; 2836ce52c744SIvan Khoronzhuk 2837ce52c744SIvan Khoronzhuk ret = cpsw_update_channels_res(priv, ch->tx_count, 0); 2838ce52c744SIvan Khoronzhuk if (ret) 2839ce52c744SIvan Khoronzhuk return ret; 2840ce52c744SIvan Khoronzhuk 2841ce52c744SIvan Khoronzhuk return 0; 2842ce52c744SIvan Khoronzhuk } 2843ce52c744SIvan Khoronzhuk 2844022d7ad7SIvan Khoronzhuk static void cpsw_suspend_data_pass(struct net_device *ndev) 2845ce52c744SIvan Khoronzhuk { 2846022d7ad7SIvan Khoronzhuk struct cpsw_common *cpsw = ndev_to_cpsw(ndev); 2847ce52c744SIvan Khoronzhuk struct cpsw_slave *slave; 2848022d7ad7SIvan Khoronzhuk int i; 2849ce52c744SIvan Khoronzhuk 2850ce52c744SIvan Khoronzhuk /* Disable NAPI scheduling */ 2851ce52c744SIvan Khoronzhuk cpsw_intr_disable(cpsw); 2852ce52c744SIvan Khoronzhuk 2853ce52c744SIvan Khoronzhuk /* Stop all transmit queues for every network device. 2854ce52c744SIvan Khoronzhuk * Disable re-using rx descriptors with dormant_on. 2855ce52c744SIvan Khoronzhuk */ 2856ce52c744SIvan Khoronzhuk for (i = cpsw->data.slaves, slave = cpsw->slaves; i; i--, slave++) { 2857ce52c744SIvan Khoronzhuk if (!(slave->ndev && netif_running(slave->ndev))) 2858ce52c744SIvan Khoronzhuk continue; 2859ce52c744SIvan Khoronzhuk 2860ce52c744SIvan Khoronzhuk netif_tx_stop_all_queues(slave->ndev); 2861ce52c744SIvan Khoronzhuk netif_dormant_on(slave->ndev); 2862ce52c744SIvan Khoronzhuk } 2863ce52c744SIvan Khoronzhuk 2864ce52c744SIvan Khoronzhuk /* Handle rest of tx packets and stop cpdma channels */ 2865ce52c744SIvan Khoronzhuk cpdma_ctlr_stop(cpsw->dma); 2866022d7ad7SIvan Khoronzhuk } 2867022d7ad7SIvan Khoronzhuk 2868022d7ad7SIvan Khoronzhuk static int cpsw_resume_data_pass(struct net_device *ndev) 2869022d7ad7SIvan Khoronzhuk { 2870022d7ad7SIvan Khoronzhuk struct cpsw_priv *priv = netdev_priv(ndev); 2871022d7ad7SIvan Khoronzhuk struct cpsw_common *cpsw = priv->cpsw; 2872022d7ad7SIvan Khoronzhuk struct cpsw_slave *slave; 2873022d7ad7SIvan Khoronzhuk int i, ret; 2874022d7ad7SIvan Khoronzhuk 2875022d7ad7SIvan Khoronzhuk /* Allow rx packets handling */ 2876022d7ad7SIvan Khoronzhuk for (i = cpsw->data.slaves, slave = cpsw->slaves; i; i--, slave++) 2877022d7ad7SIvan Khoronzhuk if (slave->ndev && netif_running(slave->ndev)) 2878022d7ad7SIvan Khoronzhuk netif_dormant_off(slave->ndev); 2879022d7ad7SIvan Khoronzhuk 2880022d7ad7SIvan Khoronzhuk /* After this receive is started */ 2881d5bc1613SIvan Khoronzhuk if (cpsw->usage_count) { 2882022d7ad7SIvan Khoronzhuk ret = cpsw_fill_rx_channels(priv); 2883022d7ad7SIvan Khoronzhuk if (ret) 2884022d7ad7SIvan Khoronzhuk return ret; 2885022d7ad7SIvan Khoronzhuk 2886022d7ad7SIvan Khoronzhuk cpdma_ctlr_start(cpsw->dma); 2887022d7ad7SIvan Khoronzhuk cpsw_intr_enable(cpsw); 2888022d7ad7SIvan Khoronzhuk } 2889022d7ad7SIvan Khoronzhuk 2890022d7ad7SIvan Khoronzhuk /* Resume transmit for every affected interface */ 2891022d7ad7SIvan Khoronzhuk for (i = cpsw->data.slaves, slave = cpsw->slaves; i; i--, slave++) 2892022d7ad7SIvan Khoronzhuk if (slave->ndev && netif_running(slave->ndev)) 2893022d7ad7SIvan Khoronzhuk netif_tx_start_all_queues(slave->ndev); 2894022d7ad7SIvan Khoronzhuk 2895022d7ad7SIvan Khoronzhuk return 0; 2896022d7ad7SIvan Khoronzhuk } 2897022d7ad7SIvan Khoronzhuk 2898022d7ad7SIvan Khoronzhuk static int cpsw_set_channels(struct net_device *ndev, 2899022d7ad7SIvan Khoronzhuk struct ethtool_channels *chs) 2900022d7ad7SIvan Khoronzhuk { 2901022d7ad7SIvan Khoronzhuk struct cpsw_priv *priv = netdev_priv(ndev); 2902022d7ad7SIvan Khoronzhuk struct cpsw_common *cpsw = priv->cpsw; 2903022d7ad7SIvan Khoronzhuk struct cpsw_slave *slave; 2904022d7ad7SIvan Khoronzhuk int i, ret; 2905022d7ad7SIvan Khoronzhuk 2906022d7ad7SIvan Khoronzhuk ret = cpsw_check_ch_settings(cpsw, chs); 2907022d7ad7SIvan Khoronzhuk if (ret < 0) 2908022d7ad7SIvan Khoronzhuk return ret; 2909022d7ad7SIvan Khoronzhuk 2910022d7ad7SIvan Khoronzhuk cpsw_suspend_data_pass(ndev); 2911ce52c744SIvan Khoronzhuk ret = cpsw_update_channels(priv, chs); 2912ce52c744SIvan Khoronzhuk if (ret) 2913ce52c744SIvan Khoronzhuk goto err; 2914ce52c744SIvan Khoronzhuk 2915ce52c744SIvan Khoronzhuk for (i = cpsw->data.slaves, slave = cpsw->slaves; i; i--, slave++) { 2916ce52c744SIvan Khoronzhuk if (!(slave->ndev && netif_running(slave->ndev))) 2917ce52c744SIvan Khoronzhuk continue; 2918ce52c744SIvan Khoronzhuk 2919ce52c744SIvan Khoronzhuk /* Inform stack about new count of queues */ 2920ce52c744SIvan Khoronzhuk ret = netif_set_real_num_tx_queues(slave->ndev, 2921ce52c744SIvan Khoronzhuk cpsw->tx_ch_num); 2922ce52c744SIvan Khoronzhuk if (ret) { 2923ce52c744SIvan Khoronzhuk dev_err(priv->dev, "cannot set real number of tx queues\n"); 2924ce52c744SIvan Khoronzhuk goto err; 2925ce52c744SIvan Khoronzhuk } 2926ce52c744SIvan Khoronzhuk 2927ce52c744SIvan Khoronzhuk ret = netif_set_real_num_rx_queues(slave->ndev, 2928ce52c744SIvan Khoronzhuk cpsw->rx_ch_num); 2929ce52c744SIvan Khoronzhuk if (ret) { 2930ce52c744SIvan Khoronzhuk dev_err(priv->dev, "cannot set real number of rx queues\n"); 2931ce52c744SIvan Khoronzhuk goto err; 2932ce52c744SIvan Khoronzhuk } 2933ce52c744SIvan Khoronzhuk } 2934ce52c744SIvan Khoronzhuk 2935d5bc1613SIvan Khoronzhuk if (cpsw->usage_count) 293632b78d85SIvan Khoronzhuk cpsw_split_res(ndev); 29378feb0a19SIvan Khoronzhuk 2938022d7ad7SIvan Khoronzhuk ret = cpsw_resume_data_pass(ndev); 2939022d7ad7SIvan Khoronzhuk if (!ret) 2940ce52c744SIvan Khoronzhuk return 0; 2941ce52c744SIvan Khoronzhuk err: 2942ce52c744SIvan Khoronzhuk dev_err(priv->dev, "cannot update channels number, closing device\n"); 2943ce52c744SIvan Khoronzhuk dev_close(ndev); 2944ce52c744SIvan Khoronzhuk return ret; 2945ce52c744SIvan Khoronzhuk } 2946ce52c744SIvan Khoronzhuk 2947a0909949SYegor Yefremov static int cpsw_get_eee(struct net_device *ndev, struct ethtool_eee *edata) 2948a0909949SYegor Yefremov { 2949a0909949SYegor Yefremov struct cpsw_priv *priv = netdev_priv(ndev); 2950a0909949SYegor Yefremov struct cpsw_common *cpsw = priv->cpsw; 2951a0909949SYegor Yefremov int slave_no = cpsw_slave_index(cpsw, priv); 2952a0909949SYegor Yefremov 2953a0909949SYegor Yefremov if (cpsw->slaves[slave_no].phy) 2954a0909949SYegor Yefremov return phy_ethtool_get_eee(cpsw->slaves[slave_no].phy, edata); 2955a0909949SYegor Yefremov else 2956a0909949SYegor Yefremov return -EOPNOTSUPP; 2957a0909949SYegor Yefremov } 2958a0909949SYegor Yefremov 2959a0909949SYegor Yefremov static int cpsw_set_eee(struct net_device *ndev, struct ethtool_eee *edata) 2960a0909949SYegor Yefremov { 2961a0909949SYegor Yefremov struct cpsw_priv *priv = netdev_priv(ndev); 2962a0909949SYegor Yefremov struct cpsw_common *cpsw = priv->cpsw; 2963a0909949SYegor Yefremov int slave_no = cpsw_slave_index(cpsw, priv); 2964a0909949SYegor Yefremov 2965a0909949SYegor Yefremov if (cpsw->slaves[slave_no].phy) 2966a0909949SYegor Yefremov return phy_ethtool_set_eee(cpsw->slaves[slave_no].phy, edata); 2967a0909949SYegor Yefremov else 2968a0909949SYegor Yefremov return -EOPNOTSUPP; 2969a0909949SYegor Yefremov } 2970a0909949SYegor Yefremov 29716bb10c2bSYegor Yefremov static int cpsw_nway_reset(struct net_device *ndev) 29726bb10c2bSYegor Yefremov { 29736bb10c2bSYegor Yefremov struct cpsw_priv *priv = netdev_priv(ndev); 29746bb10c2bSYegor Yefremov struct cpsw_common *cpsw = priv->cpsw; 29756bb10c2bSYegor Yefremov int slave_no = cpsw_slave_index(cpsw, priv); 29766bb10c2bSYegor Yefremov 29776bb10c2bSYegor Yefremov if (cpsw->slaves[slave_no].phy) 29786bb10c2bSYegor Yefremov return genphy_restart_aneg(cpsw->slaves[slave_no].phy); 29796bb10c2bSYegor Yefremov else 29806bb10c2bSYegor Yefremov return -EOPNOTSUPP; 29816bb10c2bSYegor Yefremov } 29826bb10c2bSYegor Yefremov 2983be034fc1SGrygorii Strashko static void cpsw_get_ringparam(struct net_device *ndev, 2984be034fc1SGrygorii Strashko struct ethtool_ringparam *ering) 2985be034fc1SGrygorii Strashko { 2986be034fc1SGrygorii Strashko struct cpsw_priv *priv = netdev_priv(ndev); 2987be034fc1SGrygorii Strashko struct cpsw_common *cpsw = priv->cpsw; 2988be034fc1SGrygorii Strashko 2989be034fc1SGrygorii Strashko /* not supported */ 2990be034fc1SGrygorii Strashko ering->tx_max_pending = 0; 2991be034fc1SGrygorii Strashko ering->tx_pending = cpdma_get_num_tx_descs(cpsw->dma); 2992f89d21b9SIvan Khoronzhuk ering->rx_max_pending = descs_pool_size - CPSW_MAX_QUEUES; 2993be034fc1SGrygorii Strashko ering->rx_pending = cpdma_get_num_rx_descs(cpsw->dma); 2994be034fc1SGrygorii Strashko } 2995be034fc1SGrygorii Strashko 2996be034fc1SGrygorii Strashko static int cpsw_set_ringparam(struct net_device *ndev, 2997be034fc1SGrygorii Strashko struct ethtool_ringparam *ering) 2998be034fc1SGrygorii Strashko { 2999be034fc1SGrygorii Strashko struct cpsw_priv *priv = netdev_priv(ndev); 3000be034fc1SGrygorii Strashko struct cpsw_common *cpsw = priv->cpsw; 3001022d7ad7SIvan Khoronzhuk int ret; 3002be034fc1SGrygorii Strashko 3003be034fc1SGrygorii Strashko /* ignore ering->tx_pending - only rx_pending adjustment is supported */ 3004be034fc1SGrygorii Strashko 3005be034fc1SGrygorii Strashko if (ering->rx_mini_pending || ering->rx_jumbo_pending || 3006f89d21b9SIvan Khoronzhuk ering->rx_pending < CPSW_MAX_QUEUES || 3007f89d21b9SIvan Khoronzhuk ering->rx_pending > (descs_pool_size - CPSW_MAX_QUEUES)) 3008be034fc1SGrygorii Strashko return -EINVAL; 3009be034fc1SGrygorii Strashko 3010be034fc1SGrygorii Strashko if (ering->rx_pending == cpdma_get_num_rx_descs(cpsw->dma)) 3011be034fc1SGrygorii Strashko return 0; 3012be034fc1SGrygorii Strashko 3013022d7ad7SIvan Khoronzhuk cpsw_suspend_data_pass(ndev); 3014be034fc1SGrygorii Strashko 3015be034fc1SGrygorii Strashko cpdma_set_num_rx_descs(cpsw->dma, ering->rx_pending); 3016be034fc1SGrygorii Strashko 3017d5bc1613SIvan Khoronzhuk if (cpsw->usage_count) 3018be034fc1SGrygorii Strashko cpdma_chan_split_pool(cpsw->dma); 3019be034fc1SGrygorii Strashko 3020022d7ad7SIvan Khoronzhuk ret = cpsw_resume_data_pass(ndev); 3021022d7ad7SIvan Khoronzhuk if (!ret) 3022be034fc1SGrygorii Strashko return 0; 3023022d7ad7SIvan Khoronzhuk 3024022d7ad7SIvan Khoronzhuk dev_err(&ndev->dev, "cannot set ring params, closing device\n"); 3025be034fc1SGrygorii Strashko dev_close(ndev); 3026be034fc1SGrygorii Strashko return ret; 3027be034fc1SGrygorii Strashko } 3028be034fc1SGrygorii Strashko 3029df828598SMugunthan V N static const struct ethtool_ops cpsw_ethtool_ops = { 3030df828598SMugunthan V N .get_drvinfo = cpsw_get_drvinfo, 3031df828598SMugunthan V N .get_msglevel = cpsw_get_msglevel, 3032df828598SMugunthan V N .set_msglevel = cpsw_set_msglevel, 3033df828598SMugunthan V N .get_link = ethtool_op_get_link, 30342e5b38abSRichard Cochran .get_ts_info = cpsw_get_ts_info, 3035ff5b8ef2SMugunthan V N .get_coalesce = cpsw_get_coalesce, 3036ff5b8ef2SMugunthan V N .set_coalesce = cpsw_set_coalesce, 3037d9718546SMugunthan V N .get_sset_count = cpsw_get_sset_count, 3038d9718546SMugunthan V N .get_strings = cpsw_get_strings, 3039d9718546SMugunthan V N .get_ethtool_stats = cpsw_get_ethtool_stats, 30401923d6e4SMugunthan V N .get_pauseparam = cpsw_get_pauseparam, 30411923d6e4SMugunthan V N .set_pauseparam = cpsw_set_pauseparam, 3042d8a64420SMatus Ujhelyi .get_wol = cpsw_get_wol, 3043d8a64420SMatus Ujhelyi .set_wol = cpsw_set_wol, 304452c4f0ecSMugunthan V N .get_regs_len = cpsw_get_regs_len, 304552c4f0ecSMugunthan V N .get_regs = cpsw_get_regs, 30467898b1daSGrygorii Strashko .begin = cpsw_ethtool_op_begin, 30477898b1daSGrygorii Strashko .complete = cpsw_ethtool_op_complete, 3048ce52c744SIvan Khoronzhuk .get_channels = cpsw_get_channels, 3049ce52c744SIvan Khoronzhuk .set_channels = cpsw_set_channels, 30502479876dSPhilippe Reynes .get_link_ksettings = cpsw_get_link_ksettings, 30512479876dSPhilippe Reynes .set_link_ksettings = cpsw_set_link_ksettings, 3052a0909949SYegor Yefremov .get_eee = cpsw_get_eee, 3053a0909949SYegor Yefremov .set_eee = cpsw_set_eee, 30546bb10c2bSYegor Yefremov .nway_reset = cpsw_nway_reset, 3055be034fc1SGrygorii Strashko .get_ringparam = cpsw_get_ringparam, 3056be034fc1SGrygorii Strashko .set_ringparam = cpsw_set_ringparam, 3057df828598SMugunthan V N }; 3058df828598SMugunthan V N 3059606f3993SIvan Khoronzhuk static void cpsw_slave_init(struct cpsw_slave *slave, struct cpsw_common *cpsw, 3060549985eeSRichard Cochran u32 slave_reg_ofs, u32 sliver_reg_ofs) 3061df828598SMugunthan V N { 30625d8d0d4dSIvan Khoronzhuk void __iomem *regs = cpsw->regs; 3063df828598SMugunthan V N int slave_num = slave->slave_num; 3064606f3993SIvan Khoronzhuk struct cpsw_slave_data *data = cpsw->data.slave_data + slave_num; 3065df828598SMugunthan V N 3066df828598SMugunthan V N slave->data = data; 3067549985eeSRichard Cochran slave->regs = regs + slave_reg_ofs; 3068549985eeSRichard Cochran slave->sliver = regs + sliver_reg_ofs; 3069d9ba8f9eSMugunthan V N slave->port_vlan = data->dual_emac_res_vlan; 3070df828598SMugunthan V N } 3071df828598SMugunthan V N 3072552165bcSDavid Rivshin static int cpsw_probe_dt(struct cpsw_platform_data *data, 30732eb32b0aSMugunthan V N struct platform_device *pdev) 30742eb32b0aSMugunthan V N { 30752eb32b0aSMugunthan V N struct device_node *node = pdev->dev.of_node; 30762eb32b0aSMugunthan V N struct device_node *slave_node; 30772eb32b0aSMugunthan V N int i = 0, ret; 30782eb32b0aSMugunthan V N u32 prop; 30792eb32b0aSMugunthan V N 30802eb32b0aSMugunthan V N if (!node) 30812eb32b0aSMugunthan V N return -EINVAL; 30822eb32b0aSMugunthan V N 30832eb32b0aSMugunthan V N if (of_property_read_u32(node, "slaves", &prop)) { 308488c99ff6SGeorge Cherian dev_err(&pdev->dev, "Missing slaves property in the DT.\n"); 30852eb32b0aSMugunthan V N return -EINVAL; 30862eb32b0aSMugunthan V N } 30872eb32b0aSMugunthan V N data->slaves = prop; 30882eb32b0aSMugunthan V N 3089e86ac13bSMugunthan V N if (of_property_read_u32(node, "active_slave", &prop)) { 309088c99ff6SGeorge Cherian dev_err(&pdev->dev, "Missing active_slave property in the DT.\n"); 3091aa1a15e2SDaniel Mack return -EINVAL; 309278ca0b28SRichard Cochran } 3093e86ac13bSMugunthan V N data->active_slave = prop; 309478ca0b28SRichard Cochran 3095a86854d0SKees Cook data->slave_data = devm_kcalloc(&pdev->dev, 3096a86854d0SKees Cook data->slaves, 3097a86854d0SKees Cook sizeof(struct cpsw_slave_data), 3098b2adaca9SJoe Perches GFP_KERNEL); 3099b2adaca9SJoe Perches if (!data->slave_data) 3100aa1a15e2SDaniel Mack return -ENOMEM; 31012eb32b0aSMugunthan V N 31022eb32b0aSMugunthan V N if (of_property_read_u32(node, "cpdma_channels", &prop)) { 310388c99ff6SGeorge Cherian dev_err(&pdev->dev, "Missing cpdma_channels property in the DT.\n"); 3104aa1a15e2SDaniel Mack return -EINVAL; 31052eb32b0aSMugunthan V N } 31062eb32b0aSMugunthan V N data->channels = prop; 31072eb32b0aSMugunthan V N 31082eb32b0aSMugunthan V N if (of_property_read_u32(node, "ale_entries", &prop)) { 310988c99ff6SGeorge Cherian dev_err(&pdev->dev, "Missing ale_entries property in the DT.\n"); 3110aa1a15e2SDaniel Mack return -EINVAL; 31112eb32b0aSMugunthan V N } 31122eb32b0aSMugunthan V N data->ale_entries = prop; 31132eb32b0aSMugunthan V N 31142eb32b0aSMugunthan V N if (of_property_read_u32(node, "bd_ram_size", &prop)) { 311588c99ff6SGeorge Cherian dev_err(&pdev->dev, "Missing bd_ram_size property in the DT.\n"); 3116aa1a15e2SDaniel Mack return -EINVAL; 31172eb32b0aSMugunthan V N } 31182eb32b0aSMugunthan V N data->bd_ram_size = prop; 31192eb32b0aSMugunthan V N 31202eb32b0aSMugunthan V N if (of_property_read_u32(node, "mac_control", &prop)) { 312188c99ff6SGeorge Cherian dev_err(&pdev->dev, "Missing mac_control property in the DT.\n"); 3122aa1a15e2SDaniel Mack return -EINVAL; 31232eb32b0aSMugunthan V N } 31242eb32b0aSMugunthan V N data->mac_control = prop; 31252eb32b0aSMugunthan V N 3126281abd96SMarkus Pargmann if (of_property_read_bool(node, "dual_emac")) 3127281abd96SMarkus Pargmann data->dual_emac = 1; 3128d9ba8f9eSMugunthan V N 31291fb19aa7SVaibhav Hiremath /* 31301fb19aa7SVaibhav Hiremath * Populate all the child nodes here... 31311fb19aa7SVaibhav Hiremath */ 31321fb19aa7SVaibhav Hiremath ret = of_platform_populate(node, NULL, NULL, &pdev->dev); 31331fb19aa7SVaibhav Hiremath /* We do not want to force this, as in some cases may not have child */ 31341fb19aa7SVaibhav Hiremath if (ret) 313588c99ff6SGeorge Cherian dev_warn(&pdev->dev, "Doesn't have any child node\n"); 31361fb19aa7SVaibhav Hiremath 31378658aaf2SBen Hutchings for_each_available_child_of_node(node, slave_node) { 3138549985eeSRichard Cochran struct cpsw_slave_data *slave_data = data->slave_data + i; 3139549985eeSRichard Cochran const void *mac_addr = NULL; 3140549985eeSRichard Cochran int lenp; 3141549985eeSRichard Cochran const __be32 *parp; 3142549985eeSRichard Cochran 3143f468b10eSMarkus Pargmann /* This is no slave child node, continue */ 3144f468b10eSMarkus Pargmann if (strcmp(slave_node->name, "slave")) 3145f468b10eSMarkus Pargmann continue; 3146f468b10eSMarkus Pargmann 3147552165bcSDavid Rivshin slave_data->phy_node = of_parse_phandle(slave_node, 3148552165bcSDavid Rivshin "phy-handle", 0); 3149f1eea5c1SDavid Rivshin parp = of_get_property(slave_node, "phy_id", &lenp); 3150ae092b5bSDavid Rivshin if (slave_data->phy_node) { 3151ae092b5bSDavid Rivshin dev_dbg(&pdev->dev, 3152f7ce9103SRob Herring "slave[%d] using phy-handle=\"%pOF\"\n", 3153f7ce9103SRob Herring i, slave_data->phy_node); 3154ae092b5bSDavid Rivshin } else if (of_phy_is_fixed_link(slave_node)) { 3155dfc0a6d3SDavid Rivshin /* In the case of a fixed PHY, the DT node associated 3156dfc0a6d3SDavid Rivshin * to the PHY is the Ethernet MAC DT node. 3157dfc0a6d3SDavid Rivshin */ 31581f71e8c9SMarkus Brunner ret = of_phy_register_fixed_link(slave_node); 315923a09873SJohan Hovold if (ret) { 316023a09873SJohan Hovold if (ret != -EPROBE_DEFER) 316123a09873SJohan Hovold dev_err(&pdev->dev, "failed to register fixed-link phy: %d\n", ret); 31621f71e8c9SMarkus Brunner return ret; 316323a09873SJohan Hovold } 316406cd6d6eSDavid Rivshin slave_data->phy_node = of_node_get(slave_node); 3165f1eea5c1SDavid Rivshin } else if (parp) { 3166f1eea5c1SDavid Rivshin u32 phyid; 3167f1eea5c1SDavid Rivshin struct device_node *mdio_node; 3168f1eea5c1SDavid Rivshin struct platform_device *mdio; 3169f1eea5c1SDavid Rivshin 3170f1eea5c1SDavid Rivshin if (lenp != (sizeof(__be32) * 2)) { 3171f1eea5c1SDavid Rivshin dev_err(&pdev->dev, "Invalid slave[%d] phy_id property\n", i); 317247276fccSMugunthan V N goto no_phy_slave; 3173549985eeSRichard Cochran } 3174549985eeSRichard Cochran mdio_node = of_find_node_by_phandle(be32_to_cpup(parp)); 3175549985eeSRichard Cochran phyid = be32_to_cpup(parp+1); 3176549985eeSRichard Cochran mdio = of_find_device_by_node(mdio_node); 317760e71ab5SJohan Hovold of_node_put(mdio_node); 31786954cc1fSJohan Hovold if (!mdio) { 317956fdb2e0SMarkus Pargmann dev_err(&pdev->dev, "Missing mdio platform device\n"); 31806954cc1fSJohan Hovold return -EINVAL; 31816954cc1fSJohan Hovold } 3182549985eeSRichard Cochran snprintf(slave_data->phy_id, sizeof(slave_data->phy_id), 3183549985eeSRichard Cochran PHY_ID_FMT, mdio->name, phyid); 318486e1d5adSJohan Hovold put_device(&mdio->dev); 3185f1eea5c1SDavid Rivshin } else { 3186ae092b5bSDavid Rivshin dev_err(&pdev->dev, 3187ae092b5bSDavid Rivshin "No slave[%d] phy_id, phy-handle, or fixed-link property\n", 3188ae092b5bSDavid Rivshin i); 3189f1eea5c1SDavid Rivshin goto no_phy_slave; 3190f1eea5c1SDavid Rivshin } 319147276fccSMugunthan V N slave_data->phy_if = of_get_phy_mode(slave_node); 319247276fccSMugunthan V N if (slave_data->phy_if < 0) { 319347276fccSMugunthan V N dev_err(&pdev->dev, "Missing or malformed slave[%d] phy-mode property\n", 319447276fccSMugunthan V N i); 319547276fccSMugunthan V N return slave_data->phy_if; 319647276fccSMugunthan V N } 319747276fccSMugunthan V N 319847276fccSMugunthan V N no_phy_slave: 3199549985eeSRichard Cochran mac_addr = of_get_mac_address(slave_node); 32000ba517b1SMarkus Pargmann if (mac_addr) { 3201549985eeSRichard Cochran memcpy(slave_data->mac_addr, mac_addr, ETH_ALEN); 32020ba517b1SMarkus Pargmann } else { 3203b6745f6eSMugunthan V N ret = ti_cm_get_macid(&pdev->dev, i, 32040ba517b1SMarkus Pargmann slave_data->mac_addr); 32050ba517b1SMarkus Pargmann if (ret) 32060ba517b1SMarkus Pargmann return ret; 32070ba517b1SMarkus Pargmann } 3208d9ba8f9eSMugunthan V N if (data->dual_emac) { 320991c4166cSMugunthan V N if (of_property_read_u32(slave_node, "dual_emac_res_vlan", 3210d9ba8f9eSMugunthan V N &prop)) { 321188c99ff6SGeorge Cherian dev_err(&pdev->dev, "Missing dual_emac_res_vlan in DT.\n"); 3212d9ba8f9eSMugunthan V N slave_data->dual_emac_res_vlan = i+1; 321388c99ff6SGeorge Cherian dev_err(&pdev->dev, "Using %d as Reserved VLAN for %d slave\n", 3214d9ba8f9eSMugunthan V N slave_data->dual_emac_res_vlan, i); 3215d9ba8f9eSMugunthan V N } else { 3216d9ba8f9eSMugunthan V N slave_data->dual_emac_res_vlan = prop; 3217d9ba8f9eSMugunthan V N } 3218d9ba8f9eSMugunthan V N } 3219d9ba8f9eSMugunthan V N 3220549985eeSRichard Cochran i++; 32213a27bfacSMugunthan V N if (i == data->slaves) 32223a27bfacSMugunthan V N break; 3223549985eeSRichard Cochran } 3224549985eeSRichard Cochran 32252eb32b0aSMugunthan V N return 0; 32262eb32b0aSMugunthan V N } 32272eb32b0aSMugunthan V N 3228a4e32b0dSJohan Hovold static void cpsw_remove_dt(struct platform_device *pdev) 3229a4e32b0dSJohan Hovold { 32308cbcc466SJohan Hovold struct net_device *ndev = platform_get_drvdata(pdev); 32318cbcc466SJohan Hovold struct cpsw_common *cpsw = ndev_to_cpsw(ndev); 32328cbcc466SJohan Hovold struct cpsw_platform_data *data = &cpsw->data; 32338cbcc466SJohan Hovold struct device_node *node = pdev->dev.of_node; 32348cbcc466SJohan Hovold struct device_node *slave_node; 32358cbcc466SJohan Hovold int i = 0; 32368cbcc466SJohan Hovold 32378cbcc466SJohan Hovold for_each_available_child_of_node(node, slave_node) { 32388cbcc466SJohan Hovold struct cpsw_slave_data *slave_data = &data->slave_data[i]; 32398cbcc466SJohan Hovold 32408cbcc466SJohan Hovold if (strcmp(slave_node->name, "slave")) 32418cbcc466SJohan Hovold continue; 32428cbcc466SJohan Hovold 32433f65047cSJohan Hovold if (of_phy_is_fixed_link(slave_node)) 32443f65047cSJohan Hovold of_phy_deregister_fixed_link(slave_node); 32458cbcc466SJohan Hovold 32468cbcc466SJohan Hovold of_node_put(slave_data->phy_node); 32478cbcc466SJohan Hovold 32488cbcc466SJohan Hovold i++; 32498cbcc466SJohan Hovold if (i == data->slaves) 32508cbcc466SJohan Hovold break; 32518cbcc466SJohan Hovold } 32528cbcc466SJohan Hovold 3253a4e32b0dSJohan Hovold of_platform_depopulate(&pdev->dev); 3254a4e32b0dSJohan Hovold } 3255a4e32b0dSJohan Hovold 325656e31bd8SIvan Khoronzhuk static int cpsw_probe_dual_emac(struct cpsw_priv *priv) 3257d9ba8f9eSMugunthan V N { 3258606f3993SIvan Khoronzhuk struct cpsw_common *cpsw = priv->cpsw; 3259606f3993SIvan Khoronzhuk struct cpsw_platform_data *data = &cpsw->data; 3260d9ba8f9eSMugunthan V N struct net_device *ndev; 3261d9ba8f9eSMugunthan V N struct cpsw_priv *priv_sl2; 3262e38b5a3dSIvan Khoronzhuk int ret = 0; 3263d9ba8f9eSMugunthan V N 3264e05107e6SIvan Khoronzhuk ndev = alloc_etherdev_mq(sizeof(struct cpsw_priv), CPSW_MAX_QUEUES); 3265d9ba8f9eSMugunthan V N if (!ndev) { 326656e31bd8SIvan Khoronzhuk dev_err(cpsw->dev, "cpsw: error allocating net_device\n"); 3267d9ba8f9eSMugunthan V N return -ENOMEM; 3268d9ba8f9eSMugunthan V N } 3269d9ba8f9eSMugunthan V N 3270d9ba8f9eSMugunthan V N priv_sl2 = netdev_priv(ndev); 3271606f3993SIvan Khoronzhuk priv_sl2->cpsw = cpsw; 3272d9ba8f9eSMugunthan V N priv_sl2->ndev = ndev; 3273d9ba8f9eSMugunthan V N priv_sl2->dev = &ndev->dev; 3274d9ba8f9eSMugunthan V N priv_sl2->msg_enable = netif_msg_init(debug_level, CPSW_DEBUG); 3275d9ba8f9eSMugunthan V N 3276d9ba8f9eSMugunthan V N if (is_valid_ether_addr(data->slave_data[1].mac_addr)) { 3277d9ba8f9eSMugunthan V N memcpy(priv_sl2->mac_addr, data->slave_data[1].mac_addr, 3278d9ba8f9eSMugunthan V N ETH_ALEN); 327956e31bd8SIvan Khoronzhuk dev_info(cpsw->dev, "cpsw: Detected MACID = %pM\n", 328056e31bd8SIvan Khoronzhuk priv_sl2->mac_addr); 3281d9ba8f9eSMugunthan V N } else { 32826c1f0a1fSJoe Perches eth_random_addr(priv_sl2->mac_addr); 328356e31bd8SIvan Khoronzhuk dev_info(cpsw->dev, "cpsw: Random MACID = %pM\n", 328456e31bd8SIvan Khoronzhuk priv_sl2->mac_addr); 3285d9ba8f9eSMugunthan V N } 3286d9ba8f9eSMugunthan V N memcpy(ndev->dev_addr, priv_sl2->mac_addr, ETH_ALEN); 3287d9ba8f9eSMugunthan V N 3288d9ba8f9eSMugunthan V N priv_sl2->emac_port = 1; 3289606f3993SIvan Khoronzhuk cpsw->slaves[1].ndev = ndev; 3290193736c8SIvan Khoronzhuk ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER | NETIF_F_HW_VLAN_CTAG_RX; 3291d9ba8f9eSMugunthan V N 3292d9ba8f9eSMugunthan V N ndev->netdev_ops = &cpsw_netdev_ops; 32937ad24ea4SWilfried Klaebe ndev->ethtool_ops = &cpsw_ethtool_ops; 3294d9ba8f9eSMugunthan V N 3295d9ba8f9eSMugunthan V N /* register the network device */ 329656e31bd8SIvan Khoronzhuk SET_NETDEV_DEV(ndev, cpsw->dev); 3297d9ba8f9eSMugunthan V N ret = register_netdev(ndev); 3298d9ba8f9eSMugunthan V N if (ret) { 329956e31bd8SIvan Khoronzhuk dev_err(cpsw->dev, "cpsw: error registering net device\n"); 3300d9ba8f9eSMugunthan V N free_netdev(ndev); 3301d9ba8f9eSMugunthan V N ret = -ENODEV; 3302d9ba8f9eSMugunthan V N } 3303d9ba8f9eSMugunthan V N 3304d9ba8f9eSMugunthan V N return ret; 3305d9ba8f9eSMugunthan V N } 3306d9ba8f9eSMugunthan V N 33077da11600SMugunthan V N static const struct of_device_id cpsw_of_mtable[] = { 33089611d6d6SIvan Khoronzhuk { .compatible = "ti,cpsw"}, 33099611d6d6SIvan Khoronzhuk { .compatible = "ti,am335x-cpsw"}, 33109611d6d6SIvan Khoronzhuk { .compatible = "ti,am4372-cpsw"}, 33119611d6d6SIvan Khoronzhuk { .compatible = "ti,dra7-cpsw"}, 33127da11600SMugunthan V N { /* sentinel */ }, 33137da11600SMugunthan V N }; 33147da11600SMugunthan V N MODULE_DEVICE_TABLE(of, cpsw_of_mtable); 33157da11600SMugunthan V N 33169611d6d6SIvan Khoronzhuk static const struct soc_device_attribute cpsw_soc_devices[] = { 33179611d6d6SIvan Khoronzhuk { .family = "AM33xx", .revision = "ES1.0"}, 33189611d6d6SIvan Khoronzhuk { /* sentinel */ } 33199611d6d6SIvan Khoronzhuk }; 33209611d6d6SIvan Khoronzhuk 3321663e12e6SBill Pemberton static int cpsw_probe(struct platform_device *pdev) 3322df828598SMugunthan V N { 3323ef4183a1SIvan Khoronzhuk struct clk *clk; 3324d1bd9acfSSebastian Siewior struct cpsw_platform_data *data; 3325df828598SMugunthan V N struct net_device *ndev; 3326df828598SMugunthan V N struct cpsw_priv *priv; 3327df828598SMugunthan V N struct cpdma_params dma_params; 3328df828598SMugunthan V N struct cpsw_ale_params ale_params; 3329aa1a15e2SDaniel Mack void __iomem *ss_regs; 33308a2c9a5aSGrygorii Strashko void __iomem *cpts_regs; 3331aa1a15e2SDaniel Mack struct resource *res, *ss_res; 33321d147ccbSMugunthan V N struct gpio_descs *mode; 3333549985eeSRichard Cochran u32 slave_offset, sliver_offset, slave_size; 33349611d6d6SIvan Khoronzhuk const struct soc_device_attribute *soc; 3335649a1688SIvan Khoronzhuk struct cpsw_common *cpsw; 333679b3325dSIvan Khoronzhuk int ret = 0, i, ch; 33375087b915SFelipe Balbi int irq; 3338df828598SMugunthan V N 3339649a1688SIvan Khoronzhuk cpsw = devm_kzalloc(&pdev->dev, sizeof(struct cpsw_common), GFP_KERNEL); 33403420ea88SJohan Hovold if (!cpsw) 33413420ea88SJohan Hovold return -ENOMEM; 33423420ea88SJohan Hovold 334356e31bd8SIvan Khoronzhuk cpsw->dev = &pdev->dev; 3344649a1688SIvan Khoronzhuk 3345e05107e6SIvan Khoronzhuk ndev = alloc_etherdev_mq(sizeof(struct cpsw_priv), CPSW_MAX_QUEUES); 3346df828598SMugunthan V N if (!ndev) { 334788c99ff6SGeorge Cherian dev_err(&pdev->dev, "error allocating net_device\n"); 3348df828598SMugunthan V N return -ENOMEM; 3349df828598SMugunthan V N } 3350df828598SMugunthan V N 3351df828598SMugunthan V N platform_set_drvdata(pdev, ndev); 3352df828598SMugunthan V N priv = netdev_priv(ndev); 3353649a1688SIvan Khoronzhuk priv->cpsw = cpsw; 3354df828598SMugunthan V N priv->ndev = ndev; 3355df828598SMugunthan V N priv->dev = &ndev->dev; 3356df828598SMugunthan V N priv->msg_enable = netif_msg_init(debug_level, CPSW_DEBUG); 33572a05a622SIvan Khoronzhuk cpsw->rx_packet_max = max(rx_packet_max, 128); 3358df828598SMugunthan V N 33591d147ccbSMugunthan V N mode = devm_gpiod_get_array_optional(&pdev->dev, "mode", GPIOD_OUT_LOW); 33601d147ccbSMugunthan V N if (IS_ERR(mode)) { 33611d147ccbSMugunthan V N ret = PTR_ERR(mode); 33621d147ccbSMugunthan V N dev_err(&pdev->dev, "gpio request failed, ret %d\n", ret); 33631d147ccbSMugunthan V N goto clean_ndev_ret; 33641d147ccbSMugunthan V N } 33651d147ccbSMugunthan V N 33661fb19aa7SVaibhav Hiremath /* 33671fb19aa7SVaibhav Hiremath * This may be required here for child devices. 33681fb19aa7SVaibhav Hiremath */ 33691fb19aa7SVaibhav Hiremath pm_runtime_enable(&pdev->dev); 33701fb19aa7SVaibhav Hiremath 3371739683b4SMugunthan V N /* Select default pin state */ 3372739683b4SMugunthan V N pinctrl_pm_select_default_state(&pdev->dev); 3373739683b4SMugunthan V N 3374a4e32b0dSJohan Hovold /* Need to enable clocks with runtime PM api to access module 3375a4e32b0dSJohan Hovold * registers 3376a4e32b0dSJohan Hovold */ 3377a4e32b0dSJohan Hovold ret = pm_runtime_get_sync(&pdev->dev); 3378a4e32b0dSJohan Hovold if (ret < 0) { 3379a4e32b0dSJohan Hovold pm_runtime_put_noidle(&pdev->dev); 3380aa1a15e2SDaniel Mack goto clean_runtime_disable_ret; 33812eb32b0aSMugunthan V N } 3382a4e32b0dSJohan Hovold 338323a09873SJohan Hovold ret = cpsw_probe_dt(&cpsw->data, pdev); 338423a09873SJohan Hovold if (ret) 3385a4e32b0dSJohan Hovold goto clean_dt_ret; 338623a09873SJohan Hovold 3387606f3993SIvan Khoronzhuk data = &cpsw->data; 3388e05107e6SIvan Khoronzhuk cpsw->rx_ch_num = 1; 3389e05107e6SIvan Khoronzhuk cpsw->tx_ch_num = 1; 33902eb32b0aSMugunthan V N 3391df828598SMugunthan V N if (is_valid_ether_addr(data->slave_data[0].mac_addr)) { 3392df828598SMugunthan V N memcpy(priv->mac_addr, data->slave_data[0].mac_addr, ETH_ALEN); 339388c99ff6SGeorge Cherian dev_info(&pdev->dev, "Detected MACID = %pM\n", priv->mac_addr); 3394df828598SMugunthan V N } else { 33957efd26d0SJoe Perches eth_random_addr(priv->mac_addr); 339688c99ff6SGeorge Cherian dev_info(&pdev->dev, "Random MACID = %pM\n", priv->mac_addr); 3397df828598SMugunthan V N } 3398df828598SMugunthan V N 3399df828598SMugunthan V N memcpy(ndev->dev_addr, priv->mac_addr, ETH_ALEN); 3400df828598SMugunthan V N 3401a86854d0SKees Cook cpsw->slaves = devm_kcalloc(&pdev->dev, 3402a86854d0SKees Cook data->slaves, sizeof(struct cpsw_slave), 3403df828598SMugunthan V N GFP_KERNEL); 3404606f3993SIvan Khoronzhuk if (!cpsw->slaves) { 3405aa1a15e2SDaniel Mack ret = -ENOMEM; 3406a4e32b0dSJohan Hovold goto clean_dt_ret; 3407df828598SMugunthan V N } 3408df828598SMugunthan V N for (i = 0; i < data->slaves; i++) 3409606f3993SIvan Khoronzhuk cpsw->slaves[i].slave_num = i; 3410df828598SMugunthan V N 3411606f3993SIvan Khoronzhuk cpsw->slaves[0].ndev = ndev; 3412d9ba8f9eSMugunthan V N priv->emac_port = 0; 3413d9ba8f9eSMugunthan V N 3414ef4183a1SIvan Khoronzhuk clk = devm_clk_get(&pdev->dev, "fck"); 3415ef4183a1SIvan Khoronzhuk if (IS_ERR(clk)) { 3416aa1a15e2SDaniel Mack dev_err(priv->dev, "fck is not found\n"); 3417f150bd7fSMugunthan V N ret = -ENODEV; 3418a4e32b0dSJohan Hovold goto clean_dt_ret; 3419df828598SMugunthan V N } 34202a05a622SIvan Khoronzhuk cpsw->bus_freq_mhz = clk_get_rate(clk) / 1000000; 3421df828598SMugunthan V N 3422aa1a15e2SDaniel Mack ss_res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 3423aa1a15e2SDaniel Mack ss_regs = devm_ioremap_resource(&pdev->dev, ss_res); 3424aa1a15e2SDaniel Mack if (IS_ERR(ss_regs)) { 3425aa1a15e2SDaniel Mack ret = PTR_ERR(ss_regs); 3426a4e32b0dSJohan Hovold goto clean_dt_ret; 3427df828598SMugunthan V N } 34285d8d0d4dSIvan Khoronzhuk cpsw->regs = ss_regs; 3429df828598SMugunthan V N 34302a05a622SIvan Khoronzhuk cpsw->version = readl(&cpsw->regs->id_ver); 3431f280e89aSMugunthan V N 3432aa1a15e2SDaniel Mack res = platform_get_resource(pdev, IORESOURCE_MEM, 1); 34335d8d0d4dSIvan Khoronzhuk cpsw->wr_regs = devm_ioremap_resource(&pdev->dev, res); 34345d8d0d4dSIvan Khoronzhuk if (IS_ERR(cpsw->wr_regs)) { 34355d8d0d4dSIvan Khoronzhuk ret = PTR_ERR(cpsw->wr_regs); 3436a4e32b0dSJohan Hovold goto clean_dt_ret; 3437df828598SMugunthan V N } 3438df828598SMugunthan V N 3439df828598SMugunthan V N memset(&dma_params, 0, sizeof(dma_params)); 3440549985eeSRichard Cochran memset(&ale_params, 0, sizeof(ale_params)); 3441549985eeSRichard Cochran 34422a05a622SIvan Khoronzhuk switch (cpsw->version) { 3443549985eeSRichard Cochran case CPSW_VERSION_1: 34445d8d0d4dSIvan Khoronzhuk cpsw->host_port_regs = ss_regs + CPSW1_HOST_PORT_OFFSET; 34458a2c9a5aSGrygorii Strashko cpts_regs = ss_regs + CPSW1_CPTS_OFFSET; 34465d8d0d4dSIvan Khoronzhuk cpsw->hw_stats = ss_regs + CPSW1_HW_STATS; 3447549985eeSRichard Cochran dma_params.dmaregs = ss_regs + CPSW1_CPDMA_OFFSET; 3448549985eeSRichard Cochran dma_params.txhdp = ss_regs + CPSW1_STATERAM_OFFSET; 3449549985eeSRichard Cochran ale_params.ale_regs = ss_regs + CPSW1_ALE_OFFSET; 3450549985eeSRichard Cochran slave_offset = CPSW1_SLAVE_OFFSET; 3451549985eeSRichard Cochran slave_size = CPSW1_SLAVE_SIZE; 3452549985eeSRichard Cochran sliver_offset = CPSW1_SLIVER_OFFSET; 3453549985eeSRichard Cochran dma_params.desc_mem_phys = 0; 3454549985eeSRichard Cochran break; 3455549985eeSRichard Cochran case CPSW_VERSION_2: 3456c193f365SMugunthan V N case CPSW_VERSION_3: 3457926489beSMugunthan V N case CPSW_VERSION_4: 34585d8d0d4dSIvan Khoronzhuk cpsw->host_port_regs = ss_regs + CPSW2_HOST_PORT_OFFSET; 34598a2c9a5aSGrygorii Strashko cpts_regs = ss_regs + CPSW2_CPTS_OFFSET; 34605d8d0d4dSIvan Khoronzhuk cpsw->hw_stats = ss_regs + CPSW2_HW_STATS; 3461549985eeSRichard Cochran dma_params.dmaregs = ss_regs + CPSW2_CPDMA_OFFSET; 3462549985eeSRichard Cochran dma_params.txhdp = ss_regs + CPSW2_STATERAM_OFFSET; 3463549985eeSRichard Cochran ale_params.ale_regs = ss_regs + CPSW2_ALE_OFFSET; 3464549985eeSRichard Cochran slave_offset = CPSW2_SLAVE_OFFSET; 3465549985eeSRichard Cochran slave_size = CPSW2_SLAVE_SIZE; 3466549985eeSRichard Cochran sliver_offset = CPSW2_SLIVER_OFFSET; 3467549985eeSRichard Cochran dma_params.desc_mem_phys = 3468aa1a15e2SDaniel Mack (u32 __force) ss_res->start + CPSW2_BD_OFFSET; 3469549985eeSRichard Cochran break; 3470549985eeSRichard Cochran default: 34712a05a622SIvan Khoronzhuk dev_err(priv->dev, "unknown version 0x%08x\n", cpsw->version); 3472549985eeSRichard Cochran ret = -ENODEV; 3473a4e32b0dSJohan Hovold goto clean_dt_ret; 3474549985eeSRichard Cochran } 3475606f3993SIvan Khoronzhuk for (i = 0; i < cpsw->data.slaves; i++) { 3476606f3993SIvan Khoronzhuk struct cpsw_slave *slave = &cpsw->slaves[i]; 3477606f3993SIvan Khoronzhuk 3478606f3993SIvan Khoronzhuk cpsw_slave_init(slave, cpsw, slave_offset, sliver_offset); 3479549985eeSRichard Cochran slave_offset += slave_size; 3480549985eeSRichard Cochran sliver_offset += SLIVER_SIZE; 3481549985eeSRichard Cochran } 3482549985eeSRichard Cochran 3483df828598SMugunthan V N dma_params.dev = &pdev->dev; 3484549985eeSRichard Cochran dma_params.rxthresh = dma_params.dmaregs + CPDMA_RXTHRESH; 3485549985eeSRichard Cochran dma_params.rxfree = dma_params.dmaregs + CPDMA_RXFREE; 3486549985eeSRichard Cochran dma_params.rxhdp = dma_params.txhdp + CPDMA_RXHDP; 3487549985eeSRichard Cochran dma_params.txcp = dma_params.txhdp + CPDMA_TXCP; 3488549985eeSRichard Cochran dma_params.rxcp = dma_params.txhdp + CPDMA_RXCP; 3489df828598SMugunthan V N 3490df828598SMugunthan V N dma_params.num_chan = data->channels; 3491df828598SMugunthan V N dma_params.has_soft_reset = true; 3492df828598SMugunthan V N dma_params.min_packet_size = CPSW_MIN_PACKET_SIZE; 3493df828598SMugunthan V N dma_params.desc_mem_size = data->bd_ram_size; 3494df828598SMugunthan V N dma_params.desc_align = 16; 3495df828598SMugunthan V N dma_params.has_ext_regs = true; 3496549985eeSRichard Cochran dma_params.desc_hw_addr = dma_params.desc_mem_phys; 349783fcad0cSIvan Khoronzhuk dma_params.bus_freq_mhz = cpsw->bus_freq_mhz; 349890225bf0SGrygorii Strashko dma_params.descs_pool_size = descs_pool_size; 3499df828598SMugunthan V N 35002c836bd9SIvan Khoronzhuk cpsw->dma = cpdma_ctlr_create(&dma_params); 35012c836bd9SIvan Khoronzhuk if (!cpsw->dma) { 3502df828598SMugunthan V N dev_err(priv->dev, "error initializing dma\n"); 3503df828598SMugunthan V N ret = -ENOMEM; 3504a4e32b0dSJohan Hovold goto clean_dt_ret; 3505df828598SMugunthan V N } 3506df828598SMugunthan V N 35079611d6d6SIvan Khoronzhuk soc = soc_device_match(cpsw_soc_devices); 35089611d6d6SIvan Khoronzhuk if (soc) 35099611d6d6SIvan Khoronzhuk cpsw->quirk_irq = 1; 35109611d6d6SIvan Khoronzhuk 351179b3325dSIvan Khoronzhuk ch = cpsw->quirk_irq ? 0 : 7; 351279b3325dSIvan Khoronzhuk cpsw->txv[0].ch = cpdma_chan_create(cpsw->dma, ch, cpsw_tx_handler, 0); 35138a83c5d7SIvan Khoronzhuk if (IS_ERR(cpsw->txv[0].ch)) { 35148a83c5d7SIvan Khoronzhuk dev_err(priv->dev, "error initializing tx dma channel\n"); 35158a83c5d7SIvan Khoronzhuk ret = PTR_ERR(cpsw->txv[0].ch); 35168a83c5d7SIvan Khoronzhuk goto clean_dma_ret; 35178a83c5d7SIvan Khoronzhuk } 35188a83c5d7SIvan Khoronzhuk 35198feb0a19SIvan Khoronzhuk cpsw->rxv[0].ch = cpdma_chan_create(cpsw->dma, 0, cpsw_rx_handler, 1); 35208a83c5d7SIvan Khoronzhuk if (IS_ERR(cpsw->rxv[0].ch)) { 35218a83c5d7SIvan Khoronzhuk dev_err(priv->dev, "error initializing rx dma channel\n"); 35228a83c5d7SIvan Khoronzhuk ret = PTR_ERR(cpsw->rxv[0].ch); 3523df828598SMugunthan V N goto clean_dma_ret; 3524df828598SMugunthan V N } 3525df828598SMugunthan V N 35269fe9aa0bSIvan Khoronzhuk ale_params.dev = &pdev->dev; 3527df828598SMugunthan V N ale_params.ale_ageout = ale_ageout; 3528df828598SMugunthan V N ale_params.ale_entries = data->ale_entries; 3529c6395f12SGrygorii Strashko ale_params.ale_ports = CPSW_ALE_PORTS_NUM; 3530df828598SMugunthan V N 35312a05a622SIvan Khoronzhuk cpsw->ale = cpsw_ale_create(&ale_params); 35322a05a622SIvan Khoronzhuk if (!cpsw->ale) { 3533df828598SMugunthan V N dev_err(priv->dev, "error initializing ale engine\n"); 3534df828598SMugunthan V N ret = -ENODEV; 3535df828598SMugunthan V N goto clean_dma_ret; 3536df828598SMugunthan V N } 3537df828598SMugunthan V N 35384a88fb95SGrygorii Strashko cpsw->cpts = cpts_create(cpsw->dev, cpts_regs, cpsw->dev->of_node); 35398a2c9a5aSGrygorii Strashko if (IS_ERR(cpsw->cpts)) { 35408a2c9a5aSGrygorii Strashko ret = PTR_ERR(cpsw->cpts); 35411971ab58SGrygorii Strashko goto clean_dma_ret; 35428a2c9a5aSGrygorii Strashko } 35438a2c9a5aSGrygorii Strashko 3544c03abd84SFelipe Balbi ndev->irq = platform_get_irq(pdev, 1); 3545df828598SMugunthan V N if (ndev->irq < 0) { 3546df828598SMugunthan V N dev_err(priv->dev, "error getting irq resource\n"); 3547c1e3334fSJulia Lawall ret = ndev->irq; 35481971ab58SGrygorii Strashko goto clean_dma_ret; 3549df828598SMugunthan V N } 3550df828598SMugunthan V N 3551a3a41d2fSGrygorii Strashko ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER | NETIF_F_HW_VLAN_CTAG_RX; 3552070f9c65SKeerthy 3553070f9c65SKeerthy ndev->netdev_ops = &cpsw_netdev_ops; 3554070f9c65SKeerthy ndev->ethtool_ops = &cpsw_ethtool_ops; 35559611d6d6SIvan Khoronzhuk netif_napi_add(ndev, &cpsw->napi_rx, 35569611d6d6SIvan Khoronzhuk cpsw->quirk_irq ? cpsw_rx_poll : cpsw_rx_mq_poll, 35579611d6d6SIvan Khoronzhuk CPSW_POLL_WEIGHT); 35589611d6d6SIvan Khoronzhuk netif_tx_napi_add(ndev, &cpsw->napi_tx, 35599611d6d6SIvan Khoronzhuk cpsw->quirk_irq ? cpsw_tx_poll : cpsw_tx_mq_poll, 35609611d6d6SIvan Khoronzhuk CPSW_POLL_WEIGHT); 3561070f9c65SKeerthy cpsw_split_res(ndev); 3562070f9c65SKeerthy 3563070f9c65SKeerthy /* register the network device */ 3564070f9c65SKeerthy SET_NETDEV_DEV(ndev, &pdev->dev); 3565070f9c65SKeerthy ret = register_netdev(ndev); 3566070f9c65SKeerthy if (ret) { 3567070f9c65SKeerthy dev_err(priv->dev, "error registering net device\n"); 3568070f9c65SKeerthy ret = -ENODEV; 35691971ab58SGrygorii Strashko goto clean_dma_ret; 3570070f9c65SKeerthy } 3571070f9c65SKeerthy 3572070f9c65SKeerthy if (cpsw->data.dual_emac) { 3573070f9c65SKeerthy ret = cpsw_probe_dual_emac(priv); 3574070f9c65SKeerthy if (ret) { 3575070f9c65SKeerthy cpsw_err(priv, probe, "error probe slave 2 emac interface\n"); 3576070f9c65SKeerthy goto clean_unregister_netdev_ret; 3577070f9c65SKeerthy } 3578070f9c65SKeerthy } 3579070f9c65SKeerthy 3580c03abd84SFelipe Balbi /* Grab RX and TX IRQs. Note that we also have RX_THRESHOLD and 3581c03abd84SFelipe Balbi * MISC IRQs which are always kept disabled with this driver so 3582c03abd84SFelipe Balbi * we will not request them. 3583c03abd84SFelipe Balbi * 3584c03abd84SFelipe Balbi * If anyone wants to implement support for those, make sure to 3585c03abd84SFelipe Balbi * first request and append them to irqs_table array. 3586c03abd84SFelipe Balbi */ 3587c2b32e58SDaniel Mack 3588c03abd84SFelipe Balbi /* RX IRQ */ 35895087b915SFelipe Balbi irq = platform_get_irq(pdev, 1); 3590c1e3334fSJulia Lawall if (irq < 0) { 3591c1e3334fSJulia Lawall ret = irq; 35921971ab58SGrygorii Strashko goto clean_dma_ret; 3593c1e3334fSJulia Lawall } 35945087b915SFelipe Balbi 3595e38b5a3dSIvan Khoronzhuk cpsw->irqs_table[0] = irq; 3596c03abd84SFelipe Balbi ret = devm_request_irq(&pdev->dev, irq, cpsw_rx_interrupt, 3597dbc4ec52SIvan Khoronzhuk 0, dev_name(&pdev->dev), cpsw); 35985087b915SFelipe Balbi if (ret < 0) { 35995087b915SFelipe Balbi dev_err(priv->dev, "error attaching irq (%d)\n", ret); 36001971ab58SGrygorii Strashko goto clean_dma_ret; 3601df828598SMugunthan V N } 3602df828598SMugunthan V N 3603c03abd84SFelipe Balbi /* TX IRQ */ 36045087b915SFelipe Balbi irq = platform_get_irq(pdev, 2); 3605c1e3334fSJulia Lawall if (irq < 0) { 3606c1e3334fSJulia Lawall ret = irq; 36071971ab58SGrygorii Strashko goto clean_dma_ret; 3608c1e3334fSJulia Lawall } 36095087b915SFelipe Balbi 3610e38b5a3dSIvan Khoronzhuk cpsw->irqs_table[1] = irq; 3611c03abd84SFelipe Balbi ret = devm_request_irq(&pdev->dev, irq, cpsw_tx_interrupt, 3612dbc4ec52SIvan Khoronzhuk 0, dev_name(&pdev->dev), cpsw); 36135087b915SFelipe Balbi if (ret < 0) { 36145087b915SFelipe Balbi dev_err(priv->dev, "error attaching irq (%d)\n", ret); 36151971ab58SGrygorii Strashko goto clean_dma_ret; 36165087b915SFelipe Balbi } 3617c2b32e58SDaniel Mack 361890225bf0SGrygorii Strashko cpsw_notice(priv, probe, 361990225bf0SGrygorii Strashko "initialized device (regs %pa, irq %d, pool size %d)\n", 362090225bf0SGrygorii Strashko &ss_res->start, ndev->irq, dma_params.descs_pool_size); 3621d9ba8f9eSMugunthan V N 3622c46ab7e0SJohan Hovold pm_runtime_put(&pdev->dev); 3623c46ab7e0SJohan Hovold 3624df828598SMugunthan V N return 0; 3625df828598SMugunthan V N 3626a7fe9d46SJohan Hovold clean_unregister_netdev_ret: 3627a7fe9d46SJohan Hovold unregister_netdev(ndev); 3628df828598SMugunthan V N clean_dma_ret: 36292c836bd9SIvan Khoronzhuk cpdma_ctlr_destroy(cpsw->dma); 3630a4e32b0dSJohan Hovold clean_dt_ret: 3631a4e32b0dSJohan Hovold cpsw_remove_dt(pdev); 3632c46ab7e0SJohan Hovold pm_runtime_put_sync(&pdev->dev); 3633aa1a15e2SDaniel Mack clean_runtime_disable_ret: 3634f150bd7fSMugunthan V N pm_runtime_disable(&pdev->dev); 3635df828598SMugunthan V N clean_ndev_ret: 3636d1bd9acfSSebastian Siewior free_netdev(priv->ndev); 3637df828598SMugunthan V N return ret; 3638df828598SMugunthan V N } 3639df828598SMugunthan V N 3640663e12e6SBill Pemberton static int cpsw_remove(struct platform_device *pdev) 3641df828598SMugunthan V N { 3642df828598SMugunthan V N struct net_device *ndev = platform_get_drvdata(pdev); 36432a05a622SIvan Khoronzhuk struct cpsw_common *cpsw = ndev_to_cpsw(ndev); 36448a0b6dc9SGrygorii Strashko int ret; 36458a0b6dc9SGrygorii Strashko 36468a0b6dc9SGrygorii Strashko ret = pm_runtime_get_sync(&pdev->dev); 36478a0b6dc9SGrygorii Strashko if (ret < 0) { 36488a0b6dc9SGrygorii Strashko pm_runtime_put_noidle(&pdev->dev); 36498a0b6dc9SGrygorii Strashko return ret; 36508a0b6dc9SGrygorii Strashko } 3651df828598SMugunthan V N 3652606f3993SIvan Khoronzhuk if (cpsw->data.dual_emac) 3653606f3993SIvan Khoronzhuk unregister_netdev(cpsw->slaves[1].ndev); 3654d1bd9acfSSebastian Siewior unregister_netdev(ndev); 3655df828598SMugunthan V N 36568a2c9a5aSGrygorii Strashko cpts_release(cpsw->cpts); 36572c836bd9SIvan Khoronzhuk cpdma_ctlr_destroy(cpsw->dma); 3658a4e32b0dSJohan Hovold cpsw_remove_dt(pdev); 36598a0b6dc9SGrygorii Strashko pm_runtime_put_sync(&pdev->dev); 36608a0b6dc9SGrygorii Strashko pm_runtime_disable(&pdev->dev); 3661606f3993SIvan Khoronzhuk if (cpsw->data.dual_emac) 3662606f3993SIvan Khoronzhuk free_netdev(cpsw->slaves[1].ndev); 3663df828598SMugunthan V N free_netdev(ndev); 3664df828598SMugunthan V N return 0; 3665df828598SMugunthan V N } 3666df828598SMugunthan V N 36678963a504SGrygorii Strashko #ifdef CONFIG_PM_SLEEP 3668df828598SMugunthan V N static int cpsw_suspend(struct device *dev) 3669df828598SMugunthan V N { 3670df828598SMugunthan V N struct platform_device *pdev = to_platform_device(dev); 3671df828598SMugunthan V N struct net_device *ndev = platform_get_drvdata(pdev); 3672606f3993SIvan Khoronzhuk struct cpsw_common *cpsw = ndev_to_cpsw(ndev); 3673df828598SMugunthan V N 3674606f3993SIvan Khoronzhuk if (cpsw->data.dual_emac) { 3675618073e3SMugunthan V N int i; 3676618073e3SMugunthan V N 3677606f3993SIvan Khoronzhuk for (i = 0; i < cpsw->data.slaves; i++) { 3678606f3993SIvan Khoronzhuk if (netif_running(cpsw->slaves[i].ndev)) 3679606f3993SIvan Khoronzhuk cpsw_ndo_stop(cpsw->slaves[i].ndev); 3680618073e3SMugunthan V N } 3681618073e3SMugunthan V N } else { 3682df828598SMugunthan V N if (netif_running(ndev)) 3683df828598SMugunthan V N cpsw_ndo_stop(ndev); 3684618073e3SMugunthan V N } 36851e7a2e21SDaniel Mack 3686739683b4SMugunthan V N /* Select sleep pin state */ 368756e31bd8SIvan Khoronzhuk pinctrl_pm_select_sleep_state(dev); 3688739683b4SMugunthan V N 3689df828598SMugunthan V N return 0; 3690df828598SMugunthan V N } 3691df828598SMugunthan V N 3692df828598SMugunthan V N static int cpsw_resume(struct device *dev) 3693df828598SMugunthan V N { 3694df828598SMugunthan V N struct platform_device *pdev = to_platform_device(dev); 3695df828598SMugunthan V N struct net_device *ndev = platform_get_drvdata(pdev); 3696a60ced99SIvan Khoronzhuk struct cpsw_common *cpsw = ndev_to_cpsw(ndev); 3697df828598SMugunthan V N 3698739683b4SMugunthan V N /* Select default pin state */ 369956e31bd8SIvan Khoronzhuk pinctrl_pm_select_default_state(dev); 3700739683b4SMugunthan V N 37014ccfd638SGrygorii Strashko /* shut up ASSERT_RTNL() warning in netif_set_real_num_tx/rx_queues */ 37024ccfd638SGrygorii Strashko rtnl_lock(); 3703606f3993SIvan Khoronzhuk if (cpsw->data.dual_emac) { 3704618073e3SMugunthan V N int i; 3705618073e3SMugunthan V N 3706606f3993SIvan Khoronzhuk for (i = 0; i < cpsw->data.slaves; i++) { 3707606f3993SIvan Khoronzhuk if (netif_running(cpsw->slaves[i].ndev)) 3708606f3993SIvan Khoronzhuk cpsw_ndo_open(cpsw->slaves[i].ndev); 3709618073e3SMugunthan V N } 3710618073e3SMugunthan V N } else { 3711df828598SMugunthan V N if (netif_running(ndev)) 3712df828598SMugunthan V N cpsw_ndo_open(ndev); 3713618073e3SMugunthan V N } 37144ccfd638SGrygorii Strashko rtnl_unlock(); 37154ccfd638SGrygorii Strashko 3716df828598SMugunthan V N return 0; 3717df828598SMugunthan V N } 37188963a504SGrygorii Strashko #endif 3719df828598SMugunthan V N 37208963a504SGrygorii Strashko static SIMPLE_DEV_PM_OPS(cpsw_pm_ops, cpsw_suspend, cpsw_resume); 3721df828598SMugunthan V N 3722df828598SMugunthan V N static struct platform_driver cpsw_driver = { 3723df828598SMugunthan V N .driver = { 3724df828598SMugunthan V N .name = "cpsw", 3725df828598SMugunthan V N .pm = &cpsw_pm_ops, 37261e5c76d4SSachin Kamat .of_match_table = cpsw_of_mtable, 3727df828598SMugunthan V N }, 3728df828598SMugunthan V N .probe = cpsw_probe, 3729663e12e6SBill Pemberton .remove = cpsw_remove, 3730df828598SMugunthan V N }; 3731df828598SMugunthan V N 37326fb3b6b5SGrygorii Strashko module_platform_driver(cpsw_driver); 3733df828598SMugunthan V N 3734df828598SMugunthan V N MODULE_LICENSE("GPL"); 3735df828598SMugunthan V N MODULE_AUTHOR("Cyril Chemparathy <cyril@ti.com>"); 3736df828598SMugunthan V N MODULE_AUTHOR("Mugunthan V N <mugunthanvnm@ti.com>"); 3737df828598SMugunthan V N MODULE_DESCRIPTION("TI CPSW Ethernet driver"); 3738