1df828598SMugunthan V N /* 2df828598SMugunthan V N * Texas Instruments Ethernet Switch Driver 3df828598SMugunthan V N * 4df828598SMugunthan V N * Copyright (C) 2012 Texas Instruments 5df828598SMugunthan V N * 6df828598SMugunthan V N * This program is free software; you can redistribute it and/or 7df828598SMugunthan V N * modify it under the terms of the GNU General Public License as 8df828598SMugunthan V N * published by the Free Software Foundation version 2. 9df828598SMugunthan V N * 10df828598SMugunthan V N * This program is distributed "as is" WITHOUT ANY WARRANTY of any 11df828598SMugunthan V N * kind, whether express or implied; without even the implied warranty 12df828598SMugunthan V N * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13df828598SMugunthan V N * GNU General Public License for more details. 14df828598SMugunthan V N */ 15df828598SMugunthan V N 16df828598SMugunthan V N #include <linux/kernel.h> 17df828598SMugunthan V N #include <linux/io.h> 18df828598SMugunthan V N #include <linux/clk.h> 19df828598SMugunthan V N #include <linux/timer.h> 20df828598SMugunthan V N #include <linux/module.h> 21df828598SMugunthan V N #include <linux/platform_device.h> 22df828598SMugunthan V N #include <linux/irqreturn.h> 23df828598SMugunthan V N #include <linux/interrupt.h> 24df828598SMugunthan V N #include <linux/if_ether.h> 25df828598SMugunthan V N #include <linux/etherdevice.h> 26df828598SMugunthan V N #include <linux/netdevice.h> 272e5b38abSRichard Cochran #include <linux/net_tstamp.h> 28df828598SMugunthan V N #include <linux/phy.h> 29df828598SMugunthan V N #include <linux/workqueue.h> 30df828598SMugunthan V N #include <linux/delay.h> 31f150bd7fSMugunthan V N #include <linux/pm_runtime.h> 322eb32b0aSMugunthan V N #include <linux/of.h> 332eb32b0aSMugunthan V N #include <linux/of_net.h> 342eb32b0aSMugunthan V N #include <linux/of_device.h> 353b72c2feSMugunthan V N #include <linux/if_vlan.h> 36df828598SMugunthan V N 37739683b4SMugunthan V N #include <linux/pinctrl/consumer.h> 38df828598SMugunthan V N 39dbe34724SMugunthan V N #include "cpsw.h" 40df828598SMugunthan V N #include "cpsw_ale.h" 412e5b38abSRichard Cochran #include "cpts.h" 42df828598SMugunthan V N #include "davinci_cpdma.h" 43df828598SMugunthan V N 44df828598SMugunthan V N #define CPSW_DEBUG (NETIF_MSG_HW | NETIF_MSG_WOL | \ 45df828598SMugunthan V N NETIF_MSG_DRV | NETIF_MSG_LINK | \ 46df828598SMugunthan V N NETIF_MSG_IFUP | NETIF_MSG_INTR | \ 47df828598SMugunthan V N NETIF_MSG_PROBE | NETIF_MSG_TIMER | \ 48df828598SMugunthan V N NETIF_MSG_IFDOWN | NETIF_MSG_RX_ERR | \ 49df828598SMugunthan V N NETIF_MSG_TX_ERR | NETIF_MSG_TX_DONE | \ 50df828598SMugunthan V N NETIF_MSG_PKTDATA | NETIF_MSG_TX_QUEUED | \ 51df828598SMugunthan V N NETIF_MSG_RX_STATUS) 52df828598SMugunthan V N 53df828598SMugunthan V N #define cpsw_info(priv, type, format, ...) \ 54df828598SMugunthan V N do { \ 55df828598SMugunthan V N if (netif_msg_##type(priv) && net_ratelimit()) \ 56df828598SMugunthan V N dev_info(priv->dev, format, ## __VA_ARGS__); \ 57df828598SMugunthan V N } while (0) 58df828598SMugunthan V N 59df828598SMugunthan V N #define cpsw_err(priv, type, format, ...) \ 60df828598SMugunthan V N do { \ 61df828598SMugunthan V N if (netif_msg_##type(priv) && net_ratelimit()) \ 62df828598SMugunthan V N dev_err(priv->dev, format, ## __VA_ARGS__); \ 63df828598SMugunthan V N } while (0) 64df828598SMugunthan V N 65df828598SMugunthan V N #define cpsw_dbg(priv, type, format, ...) \ 66df828598SMugunthan V N do { \ 67df828598SMugunthan V N if (netif_msg_##type(priv) && net_ratelimit()) \ 68df828598SMugunthan V N dev_dbg(priv->dev, format, ## __VA_ARGS__); \ 69df828598SMugunthan V N } while (0) 70df828598SMugunthan V N 71df828598SMugunthan V N #define cpsw_notice(priv, type, format, ...) \ 72df828598SMugunthan V N do { \ 73df828598SMugunthan V N if (netif_msg_##type(priv) && net_ratelimit()) \ 74df828598SMugunthan V N dev_notice(priv->dev, format, ## __VA_ARGS__); \ 75df828598SMugunthan V N } while (0) 76df828598SMugunthan V N 775c50a856SMugunthan V N #define ALE_ALL_PORTS 0x7 785c50a856SMugunthan V N 79df828598SMugunthan V N #define CPSW_MAJOR_VERSION(reg) (reg >> 8 & 0x7) 80df828598SMugunthan V N #define CPSW_MINOR_VERSION(reg) (reg & 0xff) 81df828598SMugunthan V N #define CPSW_RTL_VERSION(reg) ((reg >> 11) & 0x1f) 82df828598SMugunthan V N 83e90cfac6SRichard Cochran #define CPSW_VERSION_1 0x19010a 84e90cfac6SRichard Cochran #define CPSW_VERSION_2 0x19010c 85c193f365SMugunthan V N #define CPSW_VERSION_3 0x19010f 86926489beSMugunthan V N #define CPSW_VERSION_4 0x190112 87549985eeSRichard Cochran 88549985eeSRichard Cochran #define HOST_PORT_NUM 0 89549985eeSRichard Cochran #define SLIVER_SIZE 0x40 90549985eeSRichard Cochran 91549985eeSRichard Cochran #define CPSW1_HOST_PORT_OFFSET 0x028 92549985eeSRichard Cochran #define CPSW1_SLAVE_OFFSET 0x050 93549985eeSRichard Cochran #define CPSW1_SLAVE_SIZE 0x040 94549985eeSRichard Cochran #define CPSW1_CPDMA_OFFSET 0x100 95549985eeSRichard Cochran #define CPSW1_STATERAM_OFFSET 0x200 96d9718546SMugunthan V N #define CPSW1_HW_STATS 0x400 97549985eeSRichard Cochran #define CPSW1_CPTS_OFFSET 0x500 98549985eeSRichard Cochran #define CPSW1_ALE_OFFSET 0x600 99549985eeSRichard Cochran #define CPSW1_SLIVER_OFFSET 0x700 100549985eeSRichard Cochran 101549985eeSRichard Cochran #define CPSW2_HOST_PORT_OFFSET 0x108 102549985eeSRichard Cochran #define CPSW2_SLAVE_OFFSET 0x200 103549985eeSRichard Cochran #define CPSW2_SLAVE_SIZE 0x100 104549985eeSRichard Cochran #define CPSW2_CPDMA_OFFSET 0x800 105d9718546SMugunthan V N #define CPSW2_HW_STATS 0x900 106549985eeSRichard Cochran #define CPSW2_STATERAM_OFFSET 0xa00 107549985eeSRichard Cochran #define CPSW2_CPTS_OFFSET 0xc00 108549985eeSRichard Cochran #define CPSW2_ALE_OFFSET 0xd00 109549985eeSRichard Cochran #define CPSW2_SLIVER_OFFSET 0xd80 110549985eeSRichard Cochran #define CPSW2_BD_OFFSET 0x2000 111549985eeSRichard Cochran 112df828598SMugunthan V N #define CPDMA_RXTHRESH 0x0c0 113df828598SMugunthan V N #define CPDMA_RXFREE 0x0e0 114df828598SMugunthan V N #define CPDMA_TXHDP 0x00 115df828598SMugunthan V N #define CPDMA_RXHDP 0x20 116df828598SMugunthan V N #define CPDMA_TXCP 0x40 117df828598SMugunthan V N #define CPDMA_RXCP 0x60 118df828598SMugunthan V N 119df828598SMugunthan V N #define CPSW_POLL_WEIGHT 64 120df828598SMugunthan V N #define CPSW_MIN_PACKET_SIZE 60 121df828598SMugunthan V N #define CPSW_MAX_PACKET_SIZE (1500 + 14 + 4 + 4) 122df828598SMugunthan V N 123df828598SMugunthan V N #define RX_PRIORITY_MAPPING 0x76543210 124df828598SMugunthan V N #define TX_PRIORITY_MAPPING 0x33221100 125df828598SMugunthan V N #define CPDMA_TX_PRIORITY_MAP 0x76543210 126df828598SMugunthan V N 1273b72c2feSMugunthan V N #define CPSW_VLAN_AWARE BIT(1) 1283b72c2feSMugunthan V N #define CPSW_ALE_VLAN_AWARE 1 1293b72c2feSMugunthan V N 130d9ba8f9eSMugunthan V N #define CPSW_FIFO_NORMAL_MODE (0 << 15) 131d9ba8f9eSMugunthan V N #define CPSW_FIFO_DUAL_MAC_MODE (1 << 15) 132d9ba8f9eSMugunthan V N #define CPSW_FIFO_RATE_LIMIT_MODE (2 << 15) 133d9ba8f9eSMugunthan V N 134ff5b8ef2SMugunthan V N #define CPSW_INTPACEEN (0x3f << 16) 135ff5b8ef2SMugunthan V N #define CPSW_INTPRESCALE_MASK (0x7FF << 0) 136ff5b8ef2SMugunthan V N #define CPSW_CMINTMAX_CNT 63 137ff5b8ef2SMugunthan V N #define CPSW_CMINTMIN_CNT 2 138ff5b8ef2SMugunthan V N #define CPSW_CMINTMAX_INTVL (1000 / CPSW_CMINTMIN_CNT) 139ff5b8ef2SMugunthan V N #define CPSW_CMINTMIN_INTVL ((1000 / CPSW_CMINTMAX_CNT) + 1) 140ff5b8ef2SMugunthan V N 141df828598SMugunthan V N #define cpsw_enable_irq(priv) \ 142df828598SMugunthan V N do { \ 143df828598SMugunthan V N u32 i; \ 144df828598SMugunthan V N for (i = 0; i < priv->num_irqs; i++) \ 145df828598SMugunthan V N enable_irq(priv->irqs_table[i]); \ 146df828598SMugunthan V N } while (0); 147df828598SMugunthan V N #define cpsw_disable_irq(priv) \ 148df828598SMugunthan V N do { \ 149df828598SMugunthan V N u32 i; \ 150df828598SMugunthan V N for (i = 0; i < priv->num_irqs; i++) \ 151df828598SMugunthan V N disable_irq_nosync(priv->irqs_table[i]); \ 152df828598SMugunthan V N } while (0); 153df828598SMugunthan V N 154d3bb9c58SMugunthan V N #define cpsw_slave_index(priv) \ 155d3bb9c58SMugunthan V N ((priv->data.dual_emac) ? priv->emac_port : \ 156d3bb9c58SMugunthan V N priv->data.active_slave) 157d3bb9c58SMugunthan V N 158df828598SMugunthan V N static int debug_level; 159df828598SMugunthan V N module_param(debug_level, int, 0); 160df828598SMugunthan V N MODULE_PARM_DESC(debug_level, "cpsw debug level (NETIF_MSG bits)"); 161df828598SMugunthan V N 162df828598SMugunthan V N static int ale_ageout = 10; 163df828598SMugunthan V N module_param(ale_ageout, int, 0); 164df828598SMugunthan V N MODULE_PARM_DESC(ale_ageout, "cpsw ale ageout interval (seconds)"); 165df828598SMugunthan V N 166df828598SMugunthan V N static int rx_packet_max = CPSW_MAX_PACKET_SIZE; 167df828598SMugunthan V N module_param(rx_packet_max, int, 0); 168df828598SMugunthan V N MODULE_PARM_DESC(rx_packet_max, "maximum receive packet size (bytes)"); 169df828598SMugunthan V N 170996a5c27SRichard Cochran struct cpsw_wr_regs { 171df828598SMugunthan V N u32 id_ver; 172df828598SMugunthan V N u32 soft_reset; 173df828598SMugunthan V N u32 control; 174df828598SMugunthan V N u32 int_control; 175df828598SMugunthan V N u32 rx_thresh_en; 176df828598SMugunthan V N u32 rx_en; 177df828598SMugunthan V N u32 tx_en; 178df828598SMugunthan V N u32 misc_en; 179ff5b8ef2SMugunthan V N u32 mem_allign1[8]; 180ff5b8ef2SMugunthan V N u32 rx_thresh_stat; 181ff5b8ef2SMugunthan V N u32 rx_stat; 182ff5b8ef2SMugunthan V N u32 tx_stat; 183ff5b8ef2SMugunthan V N u32 misc_stat; 184ff5b8ef2SMugunthan V N u32 mem_allign2[8]; 185ff5b8ef2SMugunthan V N u32 rx_imax; 186ff5b8ef2SMugunthan V N u32 tx_imax; 187ff5b8ef2SMugunthan V N 188df828598SMugunthan V N }; 189df828598SMugunthan V N 190996a5c27SRichard Cochran struct cpsw_ss_regs { 191df828598SMugunthan V N u32 id_ver; 192df828598SMugunthan V N u32 control; 193df828598SMugunthan V N u32 soft_reset; 194df828598SMugunthan V N u32 stat_port_en; 195df828598SMugunthan V N u32 ptype; 196bd357af2SRichard Cochran u32 soft_idle; 197bd357af2SRichard Cochran u32 thru_rate; 198bd357af2SRichard Cochran u32 gap_thresh; 199bd357af2SRichard Cochran u32 tx_start_wds; 200bd357af2SRichard Cochran u32 flow_control; 201bd357af2SRichard Cochran u32 vlan_ltype; 202bd357af2SRichard Cochran u32 ts_ltype; 203bd357af2SRichard Cochran u32 dlr_ltype; 204df828598SMugunthan V N }; 205df828598SMugunthan V N 2069750a3adSRichard Cochran /* CPSW_PORT_V1 */ 2079750a3adSRichard Cochran #define CPSW1_MAX_BLKS 0x00 /* Maximum FIFO Blocks */ 2089750a3adSRichard Cochran #define CPSW1_BLK_CNT 0x04 /* FIFO Block Usage Count (Read Only) */ 2099750a3adSRichard Cochran #define CPSW1_TX_IN_CTL 0x08 /* Transmit FIFO Control */ 2109750a3adSRichard Cochran #define CPSW1_PORT_VLAN 0x0c /* VLAN Register */ 2119750a3adSRichard Cochran #define CPSW1_TX_PRI_MAP 0x10 /* Tx Header Priority to Switch Pri Mapping */ 2129750a3adSRichard Cochran #define CPSW1_TS_CTL 0x14 /* Time Sync Control */ 2139750a3adSRichard Cochran #define CPSW1_TS_SEQ_LTYPE 0x18 /* Time Sync Sequence ID Offset and Msg Type */ 2149750a3adSRichard Cochran #define CPSW1_TS_VLAN 0x1c /* Time Sync VLAN1 and VLAN2 */ 2159750a3adSRichard Cochran 2169750a3adSRichard Cochran /* CPSW_PORT_V2 */ 2179750a3adSRichard Cochran #define CPSW2_CONTROL 0x00 /* Control Register */ 2189750a3adSRichard Cochran #define CPSW2_MAX_BLKS 0x08 /* Maximum FIFO Blocks */ 2199750a3adSRichard Cochran #define CPSW2_BLK_CNT 0x0c /* FIFO Block Usage Count (Read Only) */ 2209750a3adSRichard Cochran #define CPSW2_TX_IN_CTL 0x10 /* Transmit FIFO Control */ 2219750a3adSRichard Cochran #define CPSW2_PORT_VLAN 0x14 /* VLAN Register */ 2229750a3adSRichard Cochran #define CPSW2_TX_PRI_MAP 0x18 /* Tx Header Priority to Switch Pri Mapping */ 2239750a3adSRichard Cochran #define CPSW2_TS_SEQ_MTYPE 0x1c /* Time Sync Sequence ID Offset and Msg Type */ 2249750a3adSRichard Cochran 2259750a3adSRichard Cochran /* CPSW_PORT_V1 and V2 */ 2269750a3adSRichard Cochran #define SA_LO 0x20 /* CPGMAC_SL Source Address Low */ 2279750a3adSRichard Cochran #define SA_HI 0x24 /* CPGMAC_SL Source Address High */ 2289750a3adSRichard Cochran #define SEND_PERCENT 0x28 /* Transmit Queue Send Percentages */ 2299750a3adSRichard Cochran 2309750a3adSRichard Cochran /* CPSW_PORT_V2 only */ 2319750a3adSRichard Cochran #define RX_DSCP_PRI_MAP0 0x30 /* Rx DSCP Priority to Rx Packet Mapping */ 2329750a3adSRichard Cochran #define RX_DSCP_PRI_MAP1 0x34 /* Rx DSCP Priority to Rx Packet Mapping */ 2339750a3adSRichard Cochran #define RX_DSCP_PRI_MAP2 0x38 /* Rx DSCP Priority to Rx Packet Mapping */ 2349750a3adSRichard Cochran #define RX_DSCP_PRI_MAP3 0x3c /* Rx DSCP Priority to Rx Packet Mapping */ 2359750a3adSRichard Cochran #define RX_DSCP_PRI_MAP4 0x40 /* Rx DSCP Priority to Rx Packet Mapping */ 2369750a3adSRichard Cochran #define RX_DSCP_PRI_MAP5 0x44 /* Rx DSCP Priority to Rx Packet Mapping */ 2379750a3adSRichard Cochran #define RX_DSCP_PRI_MAP6 0x48 /* Rx DSCP Priority to Rx Packet Mapping */ 2389750a3adSRichard Cochran #define RX_DSCP_PRI_MAP7 0x4c /* Rx DSCP Priority to Rx Packet Mapping */ 2399750a3adSRichard Cochran 2409750a3adSRichard Cochran /* Bit definitions for the CPSW2_CONTROL register */ 2419750a3adSRichard Cochran #define PASS_PRI_TAGGED (1<<24) /* Pass Priority Tagged */ 2429750a3adSRichard Cochran #define VLAN_LTYPE2_EN (1<<21) /* VLAN LTYPE 2 enable */ 2439750a3adSRichard Cochran #define VLAN_LTYPE1_EN (1<<20) /* VLAN LTYPE 1 enable */ 2449750a3adSRichard Cochran #define DSCP_PRI_EN (1<<16) /* DSCP Priority Enable */ 2459750a3adSRichard Cochran #define TS_320 (1<<14) /* Time Sync Dest Port 320 enable */ 2469750a3adSRichard Cochran #define TS_319 (1<<13) /* Time Sync Dest Port 319 enable */ 2479750a3adSRichard Cochran #define TS_132 (1<<12) /* Time Sync Dest IP Addr 132 enable */ 2489750a3adSRichard Cochran #define TS_131 (1<<11) /* Time Sync Dest IP Addr 131 enable */ 2499750a3adSRichard Cochran #define TS_130 (1<<10) /* Time Sync Dest IP Addr 130 enable */ 2509750a3adSRichard Cochran #define TS_129 (1<<9) /* Time Sync Dest IP Addr 129 enable */ 2519750a3adSRichard Cochran #define TS_BIT8 (1<<8) /* ts_ttl_nonzero? */ 2529750a3adSRichard Cochran #define TS_ANNEX_D_EN (1<<4) /* Time Sync Annex D enable */ 2539750a3adSRichard Cochran #define TS_LTYPE2_EN (1<<3) /* Time Sync LTYPE 2 enable */ 2549750a3adSRichard Cochran #define TS_LTYPE1_EN (1<<2) /* Time Sync LTYPE 1 enable */ 2559750a3adSRichard Cochran #define TS_TX_EN (1<<1) /* Time Sync Transmit Enable */ 2569750a3adSRichard Cochran #define TS_RX_EN (1<<0) /* Time Sync Receive Enable */ 2579750a3adSRichard Cochran 2589750a3adSRichard Cochran #define CTRL_TS_BITS \ 2599750a3adSRichard Cochran (TS_320 | TS_319 | TS_132 | TS_131 | TS_130 | TS_129 | TS_BIT8 | \ 2609750a3adSRichard Cochran TS_ANNEX_D_EN | TS_LTYPE1_EN) 2619750a3adSRichard Cochran 2629750a3adSRichard Cochran #define CTRL_ALL_TS_MASK (CTRL_TS_BITS | TS_TX_EN | TS_RX_EN) 2639750a3adSRichard Cochran #define CTRL_TX_TS_BITS (CTRL_TS_BITS | TS_TX_EN) 2649750a3adSRichard Cochran #define CTRL_RX_TS_BITS (CTRL_TS_BITS | TS_RX_EN) 2659750a3adSRichard Cochran 2669750a3adSRichard Cochran /* Bit definitions for the CPSW2_TS_SEQ_MTYPE register */ 2679750a3adSRichard Cochran #define TS_SEQ_ID_OFFSET_SHIFT (16) /* Time Sync Sequence ID Offset */ 2689750a3adSRichard Cochran #define TS_SEQ_ID_OFFSET_MASK (0x3f) 2699750a3adSRichard Cochran #define TS_MSG_TYPE_EN_SHIFT (0) /* Time Sync Message Type Enable */ 2709750a3adSRichard Cochran #define TS_MSG_TYPE_EN_MASK (0xffff) 2719750a3adSRichard Cochran 2729750a3adSRichard Cochran /* The PTP event messages - Sync, Delay_Req, Pdelay_Req, and Pdelay_Resp. */ 2739750a3adSRichard Cochran #define EVENT_MSG_BITS ((1<<0) | (1<<1) | (1<<2) | (1<<3)) 274df828598SMugunthan V N 2752e5b38abSRichard Cochran /* Bit definitions for the CPSW1_TS_CTL register */ 2762e5b38abSRichard Cochran #define CPSW_V1_TS_RX_EN BIT(0) 2772e5b38abSRichard Cochran #define CPSW_V1_TS_TX_EN BIT(4) 2782e5b38abSRichard Cochran #define CPSW_V1_MSG_TYPE_OFS 16 2792e5b38abSRichard Cochran 2802e5b38abSRichard Cochran /* Bit definitions for the CPSW1_TS_SEQ_LTYPE register */ 2812e5b38abSRichard Cochran #define CPSW_V1_SEQ_ID_OFS_SHIFT 16 2822e5b38abSRichard Cochran 283df828598SMugunthan V N struct cpsw_host_regs { 284df828598SMugunthan V N u32 max_blks; 285df828598SMugunthan V N u32 blk_cnt; 286d9ba8f9eSMugunthan V N u32 tx_in_ctl; 287df828598SMugunthan V N u32 port_vlan; 288df828598SMugunthan V N u32 tx_pri_map; 289df828598SMugunthan V N u32 cpdma_tx_pri_map; 290df828598SMugunthan V N u32 cpdma_rx_chan_map; 291df828598SMugunthan V N }; 292df828598SMugunthan V N 293df828598SMugunthan V N struct cpsw_sliver_regs { 294df828598SMugunthan V N u32 id_ver; 295df828598SMugunthan V N u32 mac_control; 296df828598SMugunthan V N u32 mac_status; 297df828598SMugunthan V N u32 soft_reset; 298df828598SMugunthan V N u32 rx_maxlen; 299df828598SMugunthan V N u32 __reserved_0; 300df828598SMugunthan V N u32 rx_pause; 301df828598SMugunthan V N u32 tx_pause; 302df828598SMugunthan V N u32 __reserved_1; 303df828598SMugunthan V N u32 rx_pri_map; 304df828598SMugunthan V N }; 305df828598SMugunthan V N 306d9718546SMugunthan V N struct cpsw_hw_stats { 307d9718546SMugunthan V N u32 rxgoodframes; 308d9718546SMugunthan V N u32 rxbroadcastframes; 309d9718546SMugunthan V N u32 rxmulticastframes; 310d9718546SMugunthan V N u32 rxpauseframes; 311d9718546SMugunthan V N u32 rxcrcerrors; 312d9718546SMugunthan V N u32 rxaligncodeerrors; 313d9718546SMugunthan V N u32 rxoversizedframes; 314d9718546SMugunthan V N u32 rxjabberframes; 315d9718546SMugunthan V N u32 rxundersizedframes; 316d9718546SMugunthan V N u32 rxfragments; 317d9718546SMugunthan V N u32 __pad_0[2]; 318d9718546SMugunthan V N u32 rxoctets; 319d9718546SMugunthan V N u32 txgoodframes; 320d9718546SMugunthan V N u32 txbroadcastframes; 321d9718546SMugunthan V N u32 txmulticastframes; 322d9718546SMugunthan V N u32 txpauseframes; 323d9718546SMugunthan V N u32 txdeferredframes; 324d9718546SMugunthan V N u32 txcollisionframes; 325d9718546SMugunthan V N u32 txsinglecollframes; 326d9718546SMugunthan V N u32 txmultcollframes; 327d9718546SMugunthan V N u32 txexcessivecollisions; 328d9718546SMugunthan V N u32 txlatecollisions; 329d9718546SMugunthan V N u32 txunderrun; 330d9718546SMugunthan V N u32 txcarriersenseerrors; 331d9718546SMugunthan V N u32 txoctets; 332d9718546SMugunthan V N u32 octetframes64; 333d9718546SMugunthan V N u32 octetframes65t127; 334d9718546SMugunthan V N u32 octetframes128t255; 335d9718546SMugunthan V N u32 octetframes256t511; 336d9718546SMugunthan V N u32 octetframes512t1023; 337d9718546SMugunthan V N u32 octetframes1024tup; 338d9718546SMugunthan V N u32 netoctets; 339d9718546SMugunthan V N u32 rxsofoverruns; 340d9718546SMugunthan V N u32 rxmofoverruns; 341d9718546SMugunthan V N u32 rxdmaoverruns; 342d9718546SMugunthan V N }; 343d9718546SMugunthan V N 344df828598SMugunthan V N struct cpsw_slave { 3459750a3adSRichard Cochran void __iomem *regs; 346df828598SMugunthan V N struct cpsw_sliver_regs __iomem *sliver; 347df828598SMugunthan V N int slave_num; 348df828598SMugunthan V N u32 mac_control; 349df828598SMugunthan V N struct cpsw_slave_data *data; 350df828598SMugunthan V N struct phy_device *phy; 351d9ba8f9eSMugunthan V N struct net_device *ndev; 352d9ba8f9eSMugunthan V N u32 port_vlan; 353d9ba8f9eSMugunthan V N u32 open_stat; 354df828598SMugunthan V N }; 355df828598SMugunthan V N 3569750a3adSRichard Cochran static inline u32 slave_read(struct cpsw_slave *slave, u32 offset) 3579750a3adSRichard Cochran { 3589750a3adSRichard Cochran return __raw_readl(slave->regs + offset); 3599750a3adSRichard Cochran } 3609750a3adSRichard Cochran 3619750a3adSRichard Cochran static inline void slave_write(struct cpsw_slave *slave, u32 val, u32 offset) 3629750a3adSRichard Cochran { 3639750a3adSRichard Cochran __raw_writel(val, slave->regs + offset); 3649750a3adSRichard Cochran } 3659750a3adSRichard Cochran 366df828598SMugunthan V N struct cpsw_priv { 367df828598SMugunthan V N spinlock_t lock; 368df828598SMugunthan V N struct platform_device *pdev; 369df828598SMugunthan V N struct net_device *ndev; 370df828598SMugunthan V N struct napi_struct napi; 371df828598SMugunthan V N struct device *dev; 372df828598SMugunthan V N struct cpsw_platform_data data; 373996a5c27SRichard Cochran struct cpsw_ss_regs __iomem *regs; 374996a5c27SRichard Cochran struct cpsw_wr_regs __iomem *wr_regs; 375d9718546SMugunthan V N u8 __iomem *hw_stats; 376df828598SMugunthan V N struct cpsw_host_regs __iomem *host_port_regs; 377df828598SMugunthan V N u32 msg_enable; 378e90cfac6SRichard Cochran u32 version; 379ff5b8ef2SMugunthan V N u32 coal_intvl; 380ff5b8ef2SMugunthan V N u32 bus_freq_mhz; 381df828598SMugunthan V N int rx_packet_max; 382df828598SMugunthan V N int host_port; 383df828598SMugunthan V N struct clk *clk; 384df828598SMugunthan V N u8 mac_addr[ETH_ALEN]; 385df828598SMugunthan V N struct cpsw_slave *slaves; 386df828598SMugunthan V N struct cpdma_ctlr *dma; 387df828598SMugunthan V N struct cpdma_chan *txch, *rxch; 388df828598SMugunthan V N struct cpsw_ale *ale; 389df828598SMugunthan V N /* snapshot of IRQ numbers */ 390df828598SMugunthan V N u32 irqs_table[4]; 391df828598SMugunthan V N u32 num_irqs; 392a11fbba9SSebastian Siewior bool irq_enabled; 3939232b16dSMugunthan V N struct cpts *cpts; 394d9ba8f9eSMugunthan V N u32 emac_port; 395df828598SMugunthan V N }; 396df828598SMugunthan V N 397d9718546SMugunthan V N struct cpsw_stats { 398d9718546SMugunthan V N char stat_string[ETH_GSTRING_LEN]; 399d9718546SMugunthan V N int type; 400d9718546SMugunthan V N int sizeof_stat; 401d9718546SMugunthan V N int stat_offset; 402d9718546SMugunthan V N }; 403d9718546SMugunthan V N 404d9718546SMugunthan V N enum { 405d9718546SMugunthan V N CPSW_STATS, 406d9718546SMugunthan V N CPDMA_RX_STATS, 407d9718546SMugunthan V N CPDMA_TX_STATS, 408d9718546SMugunthan V N }; 409d9718546SMugunthan V N 410d9718546SMugunthan V N #define CPSW_STAT(m) CPSW_STATS, \ 411d9718546SMugunthan V N sizeof(((struct cpsw_hw_stats *)0)->m), \ 412d9718546SMugunthan V N offsetof(struct cpsw_hw_stats, m) 413d9718546SMugunthan V N #define CPDMA_RX_STAT(m) CPDMA_RX_STATS, \ 414d9718546SMugunthan V N sizeof(((struct cpdma_chan_stats *)0)->m), \ 415d9718546SMugunthan V N offsetof(struct cpdma_chan_stats, m) 416d9718546SMugunthan V N #define CPDMA_TX_STAT(m) CPDMA_TX_STATS, \ 417d9718546SMugunthan V N sizeof(((struct cpdma_chan_stats *)0)->m), \ 418d9718546SMugunthan V N offsetof(struct cpdma_chan_stats, m) 419d9718546SMugunthan V N 420d9718546SMugunthan V N static const struct cpsw_stats cpsw_gstrings_stats[] = { 421d9718546SMugunthan V N { "Good Rx Frames", CPSW_STAT(rxgoodframes) }, 422d9718546SMugunthan V N { "Broadcast Rx Frames", CPSW_STAT(rxbroadcastframes) }, 423d9718546SMugunthan V N { "Multicast Rx Frames", CPSW_STAT(rxmulticastframes) }, 424d9718546SMugunthan V N { "Pause Rx Frames", CPSW_STAT(rxpauseframes) }, 425d9718546SMugunthan V N { "Rx CRC Errors", CPSW_STAT(rxcrcerrors) }, 426d9718546SMugunthan V N { "Rx Align/Code Errors", CPSW_STAT(rxaligncodeerrors) }, 427d9718546SMugunthan V N { "Oversize Rx Frames", CPSW_STAT(rxoversizedframes) }, 428d9718546SMugunthan V N { "Rx Jabbers", CPSW_STAT(rxjabberframes) }, 429d9718546SMugunthan V N { "Undersize (Short) Rx Frames", CPSW_STAT(rxundersizedframes) }, 430d9718546SMugunthan V N { "Rx Fragments", CPSW_STAT(rxfragments) }, 431d9718546SMugunthan V N { "Rx Octets", CPSW_STAT(rxoctets) }, 432d9718546SMugunthan V N { "Good Tx Frames", CPSW_STAT(txgoodframes) }, 433d9718546SMugunthan V N { "Broadcast Tx Frames", CPSW_STAT(txbroadcastframes) }, 434d9718546SMugunthan V N { "Multicast Tx Frames", CPSW_STAT(txmulticastframes) }, 435d9718546SMugunthan V N { "Pause Tx Frames", CPSW_STAT(txpauseframes) }, 436d9718546SMugunthan V N { "Deferred Tx Frames", CPSW_STAT(txdeferredframes) }, 437d9718546SMugunthan V N { "Collisions", CPSW_STAT(txcollisionframes) }, 438d9718546SMugunthan V N { "Single Collision Tx Frames", CPSW_STAT(txsinglecollframes) }, 439d9718546SMugunthan V N { "Multiple Collision Tx Frames", CPSW_STAT(txmultcollframes) }, 440d9718546SMugunthan V N { "Excessive Collisions", CPSW_STAT(txexcessivecollisions) }, 441d9718546SMugunthan V N { "Late Collisions", CPSW_STAT(txlatecollisions) }, 442d9718546SMugunthan V N { "Tx Underrun", CPSW_STAT(txunderrun) }, 443d9718546SMugunthan V N { "Carrier Sense Errors", CPSW_STAT(txcarriersenseerrors) }, 444d9718546SMugunthan V N { "Tx Octets", CPSW_STAT(txoctets) }, 445d9718546SMugunthan V N { "Rx + Tx 64 Octet Frames", CPSW_STAT(octetframes64) }, 446d9718546SMugunthan V N { "Rx + Tx 65-127 Octet Frames", CPSW_STAT(octetframes65t127) }, 447d9718546SMugunthan V N { "Rx + Tx 128-255 Octet Frames", CPSW_STAT(octetframes128t255) }, 448d9718546SMugunthan V N { "Rx + Tx 256-511 Octet Frames", CPSW_STAT(octetframes256t511) }, 449d9718546SMugunthan V N { "Rx + Tx 512-1023 Octet Frames", CPSW_STAT(octetframes512t1023) }, 450d9718546SMugunthan V N { "Rx + Tx 1024-Up Octet Frames", CPSW_STAT(octetframes1024tup) }, 451d9718546SMugunthan V N { "Net Octets", CPSW_STAT(netoctets) }, 452d9718546SMugunthan V N { "Rx Start of Frame Overruns", CPSW_STAT(rxsofoverruns) }, 453d9718546SMugunthan V N { "Rx Middle of Frame Overruns", CPSW_STAT(rxmofoverruns) }, 454d9718546SMugunthan V N { "Rx DMA Overruns", CPSW_STAT(rxdmaoverruns) }, 455d9718546SMugunthan V N { "Rx DMA chan: head_enqueue", CPDMA_RX_STAT(head_enqueue) }, 456d9718546SMugunthan V N { "Rx DMA chan: tail_enqueue", CPDMA_RX_STAT(tail_enqueue) }, 457d9718546SMugunthan V N { "Rx DMA chan: pad_enqueue", CPDMA_RX_STAT(pad_enqueue) }, 458d9718546SMugunthan V N { "Rx DMA chan: misqueued", CPDMA_RX_STAT(misqueued) }, 459d9718546SMugunthan V N { "Rx DMA chan: desc_alloc_fail", CPDMA_RX_STAT(desc_alloc_fail) }, 460d9718546SMugunthan V N { "Rx DMA chan: pad_alloc_fail", CPDMA_RX_STAT(pad_alloc_fail) }, 461d9718546SMugunthan V N { "Rx DMA chan: runt_receive_buf", CPDMA_RX_STAT(runt_receive_buff) }, 462d9718546SMugunthan V N { "Rx DMA chan: runt_transmit_buf", CPDMA_RX_STAT(runt_transmit_buff) }, 463d9718546SMugunthan V N { "Rx DMA chan: empty_dequeue", CPDMA_RX_STAT(empty_dequeue) }, 464d9718546SMugunthan V N { "Rx DMA chan: busy_dequeue", CPDMA_RX_STAT(busy_dequeue) }, 465d9718546SMugunthan V N { "Rx DMA chan: good_dequeue", CPDMA_RX_STAT(good_dequeue) }, 466d9718546SMugunthan V N { "Rx DMA chan: requeue", CPDMA_RX_STAT(requeue) }, 467d9718546SMugunthan V N { "Rx DMA chan: teardown_dequeue", CPDMA_RX_STAT(teardown_dequeue) }, 468d9718546SMugunthan V N { "Tx DMA chan: head_enqueue", CPDMA_TX_STAT(head_enqueue) }, 469d9718546SMugunthan V N { "Tx DMA chan: tail_enqueue", CPDMA_TX_STAT(tail_enqueue) }, 470d9718546SMugunthan V N { "Tx DMA chan: pad_enqueue", CPDMA_TX_STAT(pad_enqueue) }, 471d9718546SMugunthan V N { "Tx DMA chan: misqueued", CPDMA_TX_STAT(misqueued) }, 472d9718546SMugunthan V N { "Tx DMA chan: desc_alloc_fail", CPDMA_TX_STAT(desc_alloc_fail) }, 473d9718546SMugunthan V N { "Tx DMA chan: pad_alloc_fail", CPDMA_TX_STAT(pad_alloc_fail) }, 474d9718546SMugunthan V N { "Tx DMA chan: runt_receive_buf", CPDMA_TX_STAT(runt_receive_buff) }, 475d9718546SMugunthan V N { "Tx DMA chan: runt_transmit_buf", CPDMA_TX_STAT(runt_transmit_buff) }, 476d9718546SMugunthan V N { "Tx DMA chan: empty_dequeue", CPDMA_TX_STAT(empty_dequeue) }, 477d9718546SMugunthan V N { "Tx DMA chan: busy_dequeue", CPDMA_TX_STAT(busy_dequeue) }, 478d9718546SMugunthan V N { "Tx DMA chan: good_dequeue", CPDMA_TX_STAT(good_dequeue) }, 479d9718546SMugunthan V N { "Tx DMA chan: requeue", CPDMA_TX_STAT(requeue) }, 480d9718546SMugunthan V N { "Tx DMA chan: teardown_dequeue", CPDMA_TX_STAT(teardown_dequeue) }, 481d9718546SMugunthan V N }; 482d9718546SMugunthan V N 483d9718546SMugunthan V N #define CPSW_STATS_LEN ARRAY_SIZE(cpsw_gstrings_stats) 484d9718546SMugunthan V N 485df828598SMugunthan V N #define napi_to_priv(napi) container_of(napi, struct cpsw_priv, napi) 486df828598SMugunthan V N #define for_each_slave(priv, func, arg...) \ 487df828598SMugunthan V N do { \ 4886e6ceaedSSebastian Siewior struct cpsw_slave *slave; \ 4896e6ceaedSSebastian Siewior int n; \ 490d9ba8f9eSMugunthan V N if (priv->data.dual_emac) \ 491d9ba8f9eSMugunthan V N (func)((priv)->slaves + priv->emac_port, ##arg);\ 492d9ba8f9eSMugunthan V N else \ 4936e6ceaedSSebastian Siewior for (n = (priv)->data.slaves, \ 4946e6ceaedSSebastian Siewior slave = (priv)->slaves; \ 4956e6ceaedSSebastian Siewior n; n--) \ 4966e6ceaedSSebastian Siewior (func)(slave++, ##arg); \ 497df828598SMugunthan V N } while (0) 498d9ba8f9eSMugunthan V N #define cpsw_get_slave_ndev(priv, __slave_no__) \ 499d9ba8f9eSMugunthan V N (priv->slaves[__slave_no__].ndev) 500d9ba8f9eSMugunthan V N #define cpsw_get_slave_priv(priv, __slave_no__) \ 501d9ba8f9eSMugunthan V N ((priv->slaves[__slave_no__].ndev) ? \ 502d9ba8f9eSMugunthan V N netdev_priv(priv->slaves[__slave_no__].ndev) : NULL) \ 503d9ba8f9eSMugunthan V N 504d9ba8f9eSMugunthan V N #define cpsw_dual_emac_src_port_detect(status, priv, ndev, skb) \ 505d9ba8f9eSMugunthan V N do { \ 506d9ba8f9eSMugunthan V N if (!priv->data.dual_emac) \ 507d9ba8f9eSMugunthan V N break; \ 508d9ba8f9eSMugunthan V N if (CPDMA_RX_SOURCE_PORT(status) == 1) { \ 509d9ba8f9eSMugunthan V N ndev = cpsw_get_slave_ndev(priv, 0); \ 510d9ba8f9eSMugunthan V N priv = netdev_priv(ndev); \ 511d9ba8f9eSMugunthan V N skb->dev = ndev; \ 512d9ba8f9eSMugunthan V N } else if (CPDMA_RX_SOURCE_PORT(status) == 2) { \ 513d9ba8f9eSMugunthan V N ndev = cpsw_get_slave_ndev(priv, 1); \ 514d9ba8f9eSMugunthan V N priv = netdev_priv(ndev); \ 515d9ba8f9eSMugunthan V N skb->dev = ndev; \ 516d9ba8f9eSMugunthan V N } \ 517d9ba8f9eSMugunthan V N } while (0) 518d9ba8f9eSMugunthan V N #define cpsw_add_mcast(priv, addr) \ 519d9ba8f9eSMugunthan V N do { \ 520d9ba8f9eSMugunthan V N if (priv->data.dual_emac) { \ 521d9ba8f9eSMugunthan V N struct cpsw_slave *slave = priv->slaves + \ 522d9ba8f9eSMugunthan V N priv->emac_port; \ 523d9ba8f9eSMugunthan V N int slave_port = cpsw_get_slave_port(priv, \ 524d9ba8f9eSMugunthan V N slave->slave_num); \ 525d9ba8f9eSMugunthan V N cpsw_ale_add_mcast(priv->ale, addr, \ 526d9ba8f9eSMugunthan V N 1 << slave_port | 1 << priv->host_port, \ 527d9ba8f9eSMugunthan V N ALE_VLAN, slave->port_vlan, 0); \ 528d9ba8f9eSMugunthan V N } else { \ 529d9ba8f9eSMugunthan V N cpsw_ale_add_mcast(priv->ale, addr, \ 530d9ba8f9eSMugunthan V N ALE_ALL_PORTS << priv->host_port, \ 531d9ba8f9eSMugunthan V N 0, 0, 0); \ 532d9ba8f9eSMugunthan V N } \ 533d9ba8f9eSMugunthan V N } while (0) 534d9ba8f9eSMugunthan V N 535d9ba8f9eSMugunthan V N static inline int cpsw_get_slave_port(struct cpsw_priv *priv, u32 slave_num) 536d9ba8f9eSMugunthan V N { 537d9ba8f9eSMugunthan V N if (priv->host_port == 0) 538d9ba8f9eSMugunthan V N return slave_num + 1; 539d9ba8f9eSMugunthan V N else 540d9ba8f9eSMugunthan V N return slave_num; 541d9ba8f9eSMugunthan V N } 542df828598SMugunthan V N 5430cd8f9ccSMugunthan V N static void cpsw_set_promiscious(struct net_device *ndev, bool enable) 5440cd8f9ccSMugunthan V N { 5450cd8f9ccSMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 5460cd8f9ccSMugunthan V N struct cpsw_ale *ale = priv->ale; 5470cd8f9ccSMugunthan V N int i; 5480cd8f9ccSMugunthan V N 5490cd8f9ccSMugunthan V N if (priv->data.dual_emac) { 5500cd8f9ccSMugunthan V N bool flag = false; 5510cd8f9ccSMugunthan V N 5520cd8f9ccSMugunthan V N /* Enabling promiscuous mode for one interface will be 5530cd8f9ccSMugunthan V N * common for both the interface as the interface shares 5540cd8f9ccSMugunthan V N * the same hardware resource. 5550cd8f9ccSMugunthan V N */ 5560d961b3bSHeiko Schocher for (i = 0; i < priv->data.slaves; i++) 5570cd8f9ccSMugunthan V N if (priv->slaves[i].ndev->flags & IFF_PROMISC) 5580cd8f9ccSMugunthan V N flag = true; 5590cd8f9ccSMugunthan V N 5600cd8f9ccSMugunthan V N if (!enable && flag) { 5610cd8f9ccSMugunthan V N enable = true; 5620cd8f9ccSMugunthan V N dev_err(&ndev->dev, "promiscuity not disabled as the other interface is still in promiscuity mode\n"); 5630cd8f9ccSMugunthan V N } 5640cd8f9ccSMugunthan V N 5650cd8f9ccSMugunthan V N if (enable) { 5660cd8f9ccSMugunthan V N /* Enable Bypass */ 5670cd8f9ccSMugunthan V N cpsw_ale_control_set(ale, 0, ALE_BYPASS, 1); 5680cd8f9ccSMugunthan V N 5690cd8f9ccSMugunthan V N dev_dbg(&ndev->dev, "promiscuity enabled\n"); 5700cd8f9ccSMugunthan V N } else { 5710cd8f9ccSMugunthan V N /* Disable Bypass */ 5720cd8f9ccSMugunthan V N cpsw_ale_control_set(ale, 0, ALE_BYPASS, 0); 5730cd8f9ccSMugunthan V N dev_dbg(&ndev->dev, "promiscuity disabled\n"); 5740cd8f9ccSMugunthan V N } 5750cd8f9ccSMugunthan V N } else { 5760cd8f9ccSMugunthan V N if (enable) { 5770cd8f9ccSMugunthan V N unsigned long timeout = jiffies + HZ; 5780cd8f9ccSMugunthan V N 5790cd8f9ccSMugunthan V N /* Disable Learn for all ports */ 5800d961b3bSHeiko Schocher for (i = 0; i < priv->data.slaves; i++) { 5810cd8f9ccSMugunthan V N cpsw_ale_control_set(ale, i, 5820cd8f9ccSMugunthan V N ALE_PORT_NOLEARN, 1); 5830cd8f9ccSMugunthan V N cpsw_ale_control_set(ale, i, 5840cd8f9ccSMugunthan V N ALE_PORT_NO_SA_UPDATE, 1); 5850cd8f9ccSMugunthan V N } 5860cd8f9ccSMugunthan V N 5870cd8f9ccSMugunthan V N /* Clear All Untouched entries */ 5880cd8f9ccSMugunthan V N cpsw_ale_control_set(ale, 0, ALE_AGEOUT, 1); 5890cd8f9ccSMugunthan V N do { 5900cd8f9ccSMugunthan V N cpu_relax(); 5910cd8f9ccSMugunthan V N if (cpsw_ale_control_get(ale, 0, ALE_AGEOUT)) 5920cd8f9ccSMugunthan V N break; 5930cd8f9ccSMugunthan V N } while (time_after(timeout, jiffies)); 5940cd8f9ccSMugunthan V N cpsw_ale_control_set(ale, 0, ALE_AGEOUT, 1); 5950cd8f9ccSMugunthan V N 5960cd8f9ccSMugunthan V N /* Clear all mcast from ALE */ 5970cd8f9ccSMugunthan V N cpsw_ale_flush_multicast(ale, ALE_ALL_PORTS << 5980cd8f9ccSMugunthan V N priv->host_port); 5990cd8f9ccSMugunthan V N 6000cd8f9ccSMugunthan V N /* Flood All Unicast Packets to Host port */ 6010cd8f9ccSMugunthan V N cpsw_ale_control_set(ale, 0, ALE_P0_UNI_FLOOD, 1); 6020cd8f9ccSMugunthan V N dev_dbg(&ndev->dev, "promiscuity enabled\n"); 6030cd8f9ccSMugunthan V N } else { 6040cd8f9ccSMugunthan V N /* Flood All Unicast Packets to Host port */ 6050cd8f9ccSMugunthan V N cpsw_ale_control_set(ale, 0, ALE_P0_UNI_FLOOD, 0); 6060cd8f9ccSMugunthan V N 6070cd8f9ccSMugunthan V N /* Enable Learn for all ports */ 6080d961b3bSHeiko Schocher for (i = 0; i < priv->data.slaves; i++) { 6090cd8f9ccSMugunthan V N cpsw_ale_control_set(ale, i, 6100cd8f9ccSMugunthan V N ALE_PORT_NOLEARN, 0); 6110cd8f9ccSMugunthan V N cpsw_ale_control_set(ale, i, 6120cd8f9ccSMugunthan V N ALE_PORT_NO_SA_UPDATE, 0); 6130cd8f9ccSMugunthan V N } 6140cd8f9ccSMugunthan V N dev_dbg(&ndev->dev, "promiscuity disabled\n"); 6150cd8f9ccSMugunthan V N } 6160cd8f9ccSMugunthan V N } 6170cd8f9ccSMugunthan V N } 6180cd8f9ccSMugunthan V N 6195c50a856SMugunthan V N static void cpsw_ndo_set_rx_mode(struct net_device *ndev) 6205c50a856SMugunthan V N { 6215c50a856SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 6225c50a856SMugunthan V N 6235c50a856SMugunthan V N if (ndev->flags & IFF_PROMISC) { 6245c50a856SMugunthan V N /* Enable promiscuous mode */ 6250cd8f9ccSMugunthan V N cpsw_set_promiscious(ndev, true); 6265c50a856SMugunthan V N return; 6270cd8f9ccSMugunthan V N } else { 6280cd8f9ccSMugunthan V N /* Disable promiscuous mode */ 6290cd8f9ccSMugunthan V N cpsw_set_promiscious(ndev, false); 6305c50a856SMugunthan V N } 6315c50a856SMugunthan V N 6325c50a856SMugunthan V N /* Clear all mcast from ALE */ 6335c50a856SMugunthan V N cpsw_ale_flush_multicast(priv->ale, ALE_ALL_PORTS << priv->host_port); 6345c50a856SMugunthan V N 6355c50a856SMugunthan V N if (!netdev_mc_empty(ndev)) { 6365c50a856SMugunthan V N struct netdev_hw_addr *ha; 6375c50a856SMugunthan V N 6385c50a856SMugunthan V N /* program multicast address list into ALE register */ 6395c50a856SMugunthan V N netdev_for_each_mc_addr(ha, ndev) { 640d9ba8f9eSMugunthan V N cpsw_add_mcast(priv, (u8 *)ha->addr); 6415c50a856SMugunthan V N } 6425c50a856SMugunthan V N } 6435c50a856SMugunthan V N } 6445c50a856SMugunthan V N 645df828598SMugunthan V N static void cpsw_intr_enable(struct cpsw_priv *priv) 646df828598SMugunthan V N { 647996a5c27SRichard Cochran __raw_writel(0xFF, &priv->wr_regs->tx_en); 648996a5c27SRichard Cochran __raw_writel(0xFF, &priv->wr_regs->rx_en); 649df828598SMugunthan V N 650df828598SMugunthan V N cpdma_ctlr_int_ctrl(priv->dma, true); 651df828598SMugunthan V N return; 652df828598SMugunthan V N } 653df828598SMugunthan V N 654df828598SMugunthan V N static void cpsw_intr_disable(struct cpsw_priv *priv) 655df828598SMugunthan V N { 656996a5c27SRichard Cochran __raw_writel(0, &priv->wr_regs->tx_en); 657996a5c27SRichard Cochran __raw_writel(0, &priv->wr_regs->rx_en); 658df828598SMugunthan V N 659df828598SMugunthan V N cpdma_ctlr_int_ctrl(priv->dma, false); 660df828598SMugunthan V N return; 661df828598SMugunthan V N } 662df828598SMugunthan V N 6631a3b5056SOlof Johansson static void cpsw_tx_handler(void *token, int len, int status) 664df828598SMugunthan V N { 665df828598SMugunthan V N struct sk_buff *skb = token; 666df828598SMugunthan V N struct net_device *ndev = skb->dev; 667df828598SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 668df828598SMugunthan V N 669fae50823SMugunthan V N /* Check whether the queue is stopped due to stalled tx dma, if the 670fae50823SMugunthan V N * queue is stopped then start the queue as we have free desc for tx 671fae50823SMugunthan V N */ 672df828598SMugunthan V N if (unlikely(netif_queue_stopped(ndev))) 673b56d6b3fSMugunthan V N netif_wake_queue(ndev); 6749232b16dSMugunthan V N cpts_tx_timestamp(priv->cpts, skb); 6758dc43ddcSTobias Klauser ndev->stats.tx_packets++; 6768dc43ddcSTobias Klauser ndev->stats.tx_bytes += len; 677df828598SMugunthan V N dev_kfree_skb_any(skb); 678df828598SMugunthan V N } 679df828598SMugunthan V N 6801a3b5056SOlof Johansson static void cpsw_rx_handler(void *token, int len, int status) 681df828598SMugunthan V N { 682df828598SMugunthan V N struct sk_buff *skb = token; 683b4727e69SSebastian Siewior struct sk_buff *new_skb; 684df828598SMugunthan V N struct net_device *ndev = skb->dev; 685df828598SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 686df828598SMugunthan V N int ret = 0; 687df828598SMugunthan V N 688d9ba8f9eSMugunthan V N cpsw_dual_emac_src_port_detect(status, priv, ndev, skb); 689d9ba8f9eSMugunthan V N 69016e5c57dSMugunthan V N if (unlikely(status < 0) || unlikely(!netif_running(ndev))) { 691b4727e69SSebastian Siewior /* the interface is going down, skbs are purged */ 692df828598SMugunthan V N dev_kfree_skb_any(skb); 693df828598SMugunthan V N return; 694df828598SMugunthan V N } 695b4727e69SSebastian Siewior 696b4727e69SSebastian Siewior new_skb = netdev_alloc_skb_ip_align(ndev, priv->rx_packet_max); 697b4727e69SSebastian Siewior if (new_skb) { 698df828598SMugunthan V N skb_put(skb, len); 6999232b16dSMugunthan V N cpts_rx_timestamp(priv->cpts, skb); 700df828598SMugunthan V N skb->protocol = eth_type_trans(skb, ndev); 701df828598SMugunthan V N netif_receive_skb(skb); 7028dc43ddcSTobias Klauser ndev->stats.rx_bytes += len; 7038dc43ddcSTobias Klauser ndev->stats.rx_packets++; 704b4727e69SSebastian Siewior } else { 7058dc43ddcSTobias Klauser ndev->stats.rx_dropped++; 706b4727e69SSebastian Siewior new_skb = skb; 707df828598SMugunthan V N } 708df828598SMugunthan V N 709b4727e69SSebastian Siewior ret = cpdma_chan_submit(priv->rxch, new_skb, new_skb->data, 710b4727e69SSebastian Siewior skb_tailroom(new_skb), 0); 711b4727e69SSebastian Siewior if (WARN_ON(ret < 0)) 712b4727e69SSebastian Siewior dev_kfree_skb_any(new_skb); 713df828598SMugunthan V N } 714df828598SMugunthan V N 715df828598SMugunthan V N static irqreturn_t cpsw_interrupt(int irq, void *dev_id) 716df828598SMugunthan V N { 717df828598SMugunthan V N struct cpsw_priv *priv = dev_id; 718fd51cf19SSebastian Siewior 719df828598SMugunthan V N cpsw_intr_disable(priv); 720a11fbba9SSebastian Siewior if (priv->irq_enabled == true) { 721df828598SMugunthan V N cpsw_disable_irq(priv); 722a11fbba9SSebastian Siewior priv->irq_enabled = false; 723a11fbba9SSebastian Siewior } 724fd51cf19SSebastian Siewior 725fd51cf19SSebastian Siewior if (netif_running(priv->ndev)) { 726df828598SMugunthan V N napi_schedule(&priv->napi); 727df828598SMugunthan V N return IRQ_HANDLED; 728df828598SMugunthan V N } 729df828598SMugunthan V N 730fd51cf19SSebastian Siewior priv = cpsw_get_slave_priv(priv, 1); 731fd51cf19SSebastian Siewior if (!priv) 732fd51cf19SSebastian Siewior return IRQ_NONE; 733fd51cf19SSebastian Siewior 734fd51cf19SSebastian Siewior if (netif_running(priv->ndev)) { 735fd51cf19SSebastian Siewior napi_schedule(&priv->napi); 736fd51cf19SSebastian Siewior return IRQ_HANDLED; 737fd51cf19SSebastian Siewior } 738fd51cf19SSebastian Siewior return IRQ_NONE; 739fd51cf19SSebastian Siewior } 740fd51cf19SSebastian Siewior 741df828598SMugunthan V N static int cpsw_poll(struct napi_struct *napi, int budget) 742df828598SMugunthan V N { 743df828598SMugunthan V N struct cpsw_priv *priv = napi_to_priv(napi); 744df828598SMugunthan V N int num_tx, num_rx; 745df828598SMugunthan V N 746df828598SMugunthan V N num_tx = cpdma_chan_process(priv->txch, 128); 747510a1e72SMugunthan V N if (num_tx) 748510a1e72SMugunthan V N cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_TX); 749510a1e72SMugunthan V N 750df828598SMugunthan V N num_rx = cpdma_chan_process(priv->rxch, budget); 751510a1e72SMugunthan V N if (num_rx < budget) { 752a11fbba9SSebastian Siewior struct cpsw_priv *prim_cpsw; 753a11fbba9SSebastian Siewior 754510a1e72SMugunthan V N napi_complete(napi); 755510a1e72SMugunthan V N cpsw_intr_enable(priv); 756510a1e72SMugunthan V N cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_RX); 757a11fbba9SSebastian Siewior prim_cpsw = cpsw_get_slave_priv(priv, 0); 758a11fbba9SSebastian Siewior if (prim_cpsw->irq_enabled == false) { 759a11fbba9SSebastian Siewior prim_cpsw->irq_enabled = true; 760af5c6df7SMugunthan V N cpsw_enable_irq(priv); 761a11fbba9SSebastian Siewior } 762510a1e72SMugunthan V N } 763df828598SMugunthan V N 764df828598SMugunthan V N if (num_rx || num_tx) 765df828598SMugunthan V N cpsw_dbg(priv, intr, "poll %d rx, %d tx pkts\n", 766df828598SMugunthan V N num_rx, num_tx); 767df828598SMugunthan V N 768df828598SMugunthan V N return num_rx; 769df828598SMugunthan V N } 770df828598SMugunthan V N 771df828598SMugunthan V N static inline void soft_reset(const char *module, void __iomem *reg) 772df828598SMugunthan V N { 773df828598SMugunthan V N unsigned long timeout = jiffies + HZ; 774df828598SMugunthan V N 775df828598SMugunthan V N __raw_writel(1, reg); 776df828598SMugunthan V N do { 777df828598SMugunthan V N cpu_relax(); 778df828598SMugunthan V N } while ((__raw_readl(reg) & 1) && time_after(timeout, jiffies)); 779df828598SMugunthan V N 780df828598SMugunthan V N WARN(__raw_readl(reg) & 1, "failed to soft-reset %s\n", module); 781df828598SMugunthan V N } 782df828598SMugunthan V N 783df828598SMugunthan V N #define mac_hi(mac) (((mac)[0] << 0) | ((mac)[1] << 8) | \ 784df828598SMugunthan V N ((mac)[2] << 16) | ((mac)[3] << 24)) 785df828598SMugunthan V N #define mac_lo(mac) (((mac)[4] << 0) | ((mac)[5] << 8)) 786df828598SMugunthan V N 787df828598SMugunthan V N static void cpsw_set_slave_mac(struct cpsw_slave *slave, 788df828598SMugunthan V N struct cpsw_priv *priv) 789df828598SMugunthan V N { 7909750a3adSRichard Cochran slave_write(slave, mac_hi(priv->mac_addr), SA_HI); 7919750a3adSRichard Cochran slave_write(slave, mac_lo(priv->mac_addr), SA_LO); 792df828598SMugunthan V N } 793df828598SMugunthan V N 794df828598SMugunthan V N static void _cpsw_adjust_link(struct cpsw_slave *slave, 795df828598SMugunthan V N struct cpsw_priv *priv, bool *link) 796df828598SMugunthan V N { 797df828598SMugunthan V N struct phy_device *phy = slave->phy; 798df828598SMugunthan V N u32 mac_control = 0; 799df828598SMugunthan V N u32 slave_port; 800df828598SMugunthan V N 801df828598SMugunthan V N if (!phy) 802df828598SMugunthan V N return; 803df828598SMugunthan V N 804df828598SMugunthan V N slave_port = cpsw_get_slave_port(priv, slave->slave_num); 805df828598SMugunthan V N 806df828598SMugunthan V N if (phy->link) { 807df828598SMugunthan V N mac_control = priv->data.mac_control; 808df828598SMugunthan V N 809df828598SMugunthan V N /* enable forwarding */ 810df828598SMugunthan V N cpsw_ale_control_set(priv->ale, slave_port, 811df828598SMugunthan V N ALE_PORT_STATE, ALE_PORT_STATE_FORWARD); 812df828598SMugunthan V N 813df828598SMugunthan V N if (phy->speed == 1000) 814df828598SMugunthan V N mac_control |= BIT(7); /* GIGABITEN */ 815df828598SMugunthan V N if (phy->duplex) 816df828598SMugunthan V N mac_control |= BIT(0); /* FULLDUPLEXEN */ 817342b7b74SDaniel Mack 818342b7b74SDaniel Mack /* set speed_in input in case RMII mode is used in 100Mbps */ 819342b7b74SDaniel Mack if (phy->speed == 100) 820342b7b74SDaniel Mack mac_control |= BIT(15); 821a81d8762SMugunthan V N else if (phy->speed == 10) 822a81d8762SMugunthan V N mac_control |= BIT(18); /* In Band mode */ 823342b7b74SDaniel Mack 824df828598SMugunthan V N *link = true; 825df828598SMugunthan V N } else { 826df828598SMugunthan V N mac_control = 0; 827df828598SMugunthan V N /* disable forwarding */ 828df828598SMugunthan V N cpsw_ale_control_set(priv->ale, slave_port, 829df828598SMugunthan V N ALE_PORT_STATE, ALE_PORT_STATE_DISABLE); 830df828598SMugunthan V N } 831df828598SMugunthan V N 832df828598SMugunthan V N if (mac_control != slave->mac_control) { 833df828598SMugunthan V N phy_print_status(phy); 834df828598SMugunthan V N __raw_writel(mac_control, &slave->sliver->mac_control); 835df828598SMugunthan V N } 836df828598SMugunthan V N 837df828598SMugunthan V N slave->mac_control = mac_control; 838df828598SMugunthan V N } 839df828598SMugunthan V N 840df828598SMugunthan V N static void cpsw_adjust_link(struct net_device *ndev) 841df828598SMugunthan V N { 842df828598SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 843df828598SMugunthan V N bool link = false; 844df828598SMugunthan V N 845df828598SMugunthan V N for_each_slave(priv, _cpsw_adjust_link, priv, &link); 846df828598SMugunthan V N 847df828598SMugunthan V N if (link) { 848df828598SMugunthan V N netif_carrier_on(ndev); 849df828598SMugunthan V N if (netif_running(ndev)) 850df828598SMugunthan V N netif_wake_queue(ndev); 851df828598SMugunthan V N } else { 852df828598SMugunthan V N netif_carrier_off(ndev); 853df828598SMugunthan V N netif_stop_queue(ndev); 854df828598SMugunthan V N } 855df828598SMugunthan V N } 856df828598SMugunthan V N 857ff5b8ef2SMugunthan V N static int cpsw_get_coalesce(struct net_device *ndev, 858ff5b8ef2SMugunthan V N struct ethtool_coalesce *coal) 859ff5b8ef2SMugunthan V N { 860ff5b8ef2SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 861ff5b8ef2SMugunthan V N 862ff5b8ef2SMugunthan V N coal->rx_coalesce_usecs = priv->coal_intvl; 863ff5b8ef2SMugunthan V N return 0; 864ff5b8ef2SMugunthan V N } 865ff5b8ef2SMugunthan V N 866ff5b8ef2SMugunthan V N static int cpsw_set_coalesce(struct net_device *ndev, 867ff5b8ef2SMugunthan V N struct ethtool_coalesce *coal) 868ff5b8ef2SMugunthan V N { 869ff5b8ef2SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 870ff5b8ef2SMugunthan V N u32 int_ctrl; 871ff5b8ef2SMugunthan V N u32 num_interrupts = 0; 872ff5b8ef2SMugunthan V N u32 prescale = 0; 873ff5b8ef2SMugunthan V N u32 addnl_dvdr = 1; 874ff5b8ef2SMugunthan V N u32 coal_intvl = 0; 875ff5b8ef2SMugunthan V N 876ff5b8ef2SMugunthan V N if (!coal->rx_coalesce_usecs) 877ff5b8ef2SMugunthan V N return -EINVAL; 878ff5b8ef2SMugunthan V N 879ff5b8ef2SMugunthan V N coal_intvl = coal->rx_coalesce_usecs; 880ff5b8ef2SMugunthan V N 881ff5b8ef2SMugunthan V N int_ctrl = readl(&priv->wr_regs->int_control); 882ff5b8ef2SMugunthan V N prescale = priv->bus_freq_mhz * 4; 883ff5b8ef2SMugunthan V N 884ff5b8ef2SMugunthan V N if (coal_intvl < CPSW_CMINTMIN_INTVL) 885ff5b8ef2SMugunthan V N coal_intvl = CPSW_CMINTMIN_INTVL; 886ff5b8ef2SMugunthan V N 887ff5b8ef2SMugunthan V N if (coal_intvl > CPSW_CMINTMAX_INTVL) { 888ff5b8ef2SMugunthan V N /* Interrupt pacer works with 4us Pulse, we can 889ff5b8ef2SMugunthan V N * throttle further by dilating the 4us pulse. 890ff5b8ef2SMugunthan V N */ 891ff5b8ef2SMugunthan V N addnl_dvdr = CPSW_INTPRESCALE_MASK / prescale; 892ff5b8ef2SMugunthan V N 893ff5b8ef2SMugunthan V N if (addnl_dvdr > 1) { 894ff5b8ef2SMugunthan V N prescale *= addnl_dvdr; 895ff5b8ef2SMugunthan V N if (coal_intvl > (CPSW_CMINTMAX_INTVL * addnl_dvdr)) 896ff5b8ef2SMugunthan V N coal_intvl = (CPSW_CMINTMAX_INTVL 897ff5b8ef2SMugunthan V N * addnl_dvdr); 898ff5b8ef2SMugunthan V N } else { 899ff5b8ef2SMugunthan V N addnl_dvdr = 1; 900ff5b8ef2SMugunthan V N coal_intvl = CPSW_CMINTMAX_INTVL; 901ff5b8ef2SMugunthan V N } 902ff5b8ef2SMugunthan V N } 903ff5b8ef2SMugunthan V N 904ff5b8ef2SMugunthan V N num_interrupts = (1000 * addnl_dvdr) / coal_intvl; 905ff5b8ef2SMugunthan V N writel(num_interrupts, &priv->wr_regs->rx_imax); 906ff5b8ef2SMugunthan V N writel(num_interrupts, &priv->wr_regs->tx_imax); 907ff5b8ef2SMugunthan V N 908ff5b8ef2SMugunthan V N int_ctrl |= CPSW_INTPACEEN; 909ff5b8ef2SMugunthan V N int_ctrl &= (~CPSW_INTPRESCALE_MASK); 910ff5b8ef2SMugunthan V N int_ctrl |= (prescale & CPSW_INTPRESCALE_MASK); 911ff5b8ef2SMugunthan V N writel(int_ctrl, &priv->wr_regs->int_control); 912ff5b8ef2SMugunthan V N 913ff5b8ef2SMugunthan V N cpsw_notice(priv, timer, "Set coalesce to %d usecs.\n", coal_intvl); 914ff5b8ef2SMugunthan V N if (priv->data.dual_emac) { 915ff5b8ef2SMugunthan V N int i; 916ff5b8ef2SMugunthan V N 917ff5b8ef2SMugunthan V N for (i = 0; i < priv->data.slaves; i++) { 918ff5b8ef2SMugunthan V N priv = netdev_priv(priv->slaves[i].ndev); 919ff5b8ef2SMugunthan V N priv->coal_intvl = coal_intvl; 920ff5b8ef2SMugunthan V N } 921ff5b8ef2SMugunthan V N } else { 922ff5b8ef2SMugunthan V N priv->coal_intvl = coal_intvl; 923ff5b8ef2SMugunthan V N } 924ff5b8ef2SMugunthan V N 925ff5b8ef2SMugunthan V N return 0; 926ff5b8ef2SMugunthan V N } 927ff5b8ef2SMugunthan V N 928d9718546SMugunthan V N static int cpsw_get_sset_count(struct net_device *ndev, int sset) 929d9718546SMugunthan V N { 930d9718546SMugunthan V N switch (sset) { 931d9718546SMugunthan V N case ETH_SS_STATS: 932d9718546SMugunthan V N return CPSW_STATS_LEN; 933d9718546SMugunthan V N default: 934d9718546SMugunthan V N return -EOPNOTSUPP; 935d9718546SMugunthan V N } 936d9718546SMugunthan V N } 937d9718546SMugunthan V N 938d9718546SMugunthan V N static void cpsw_get_strings(struct net_device *ndev, u32 stringset, u8 *data) 939d9718546SMugunthan V N { 940d9718546SMugunthan V N u8 *p = data; 941d9718546SMugunthan V N int i; 942d9718546SMugunthan V N 943d9718546SMugunthan V N switch (stringset) { 944d9718546SMugunthan V N case ETH_SS_STATS: 945d9718546SMugunthan V N for (i = 0; i < CPSW_STATS_LEN; i++) { 946d9718546SMugunthan V N memcpy(p, cpsw_gstrings_stats[i].stat_string, 947d9718546SMugunthan V N ETH_GSTRING_LEN); 948d9718546SMugunthan V N p += ETH_GSTRING_LEN; 949d9718546SMugunthan V N } 950d9718546SMugunthan V N break; 951d9718546SMugunthan V N } 952d9718546SMugunthan V N } 953d9718546SMugunthan V N 954d9718546SMugunthan V N static void cpsw_get_ethtool_stats(struct net_device *ndev, 955d9718546SMugunthan V N struct ethtool_stats *stats, u64 *data) 956d9718546SMugunthan V N { 957d9718546SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 958d9718546SMugunthan V N struct cpdma_chan_stats rx_stats; 959d9718546SMugunthan V N struct cpdma_chan_stats tx_stats; 960d9718546SMugunthan V N u32 val; 961d9718546SMugunthan V N u8 *p; 962d9718546SMugunthan V N int i; 963d9718546SMugunthan V N 964d9718546SMugunthan V N /* Collect Davinci CPDMA stats for Rx and Tx Channel */ 965d9718546SMugunthan V N cpdma_chan_get_stats(priv->rxch, &rx_stats); 966d9718546SMugunthan V N cpdma_chan_get_stats(priv->txch, &tx_stats); 967d9718546SMugunthan V N 968d9718546SMugunthan V N for (i = 0; i < CPSW_STATS_LEN; i++) { 969d9718546SMugunthan V N switch (cpsw_gstrings_stats[i].type) { 970d9718546SMugunthan V N case CPSW_STATS: 971d9718546SMugunthan V N val = readl(priv->hw_stats + 972d9718546SMugunthan V N cpsw_gstrings_stats[i].stat_offset); 973d9718546SMugunthan V N data[i] = val; 974d9718546SMugunthan V N break; 975d9718546SMugunthan V N 976d9718546SMugunthan V N case CPDMA_RX_STATS: 977d9718546SMugunthan V N p = (u8 *)&rx_stats + 978d9718546SMugunthan V N cpsw_gstrings_stats[i].stat_offset; 979d9718546SMugunthan V N data[i] = *(u32 *)p; 980d9718546SMugunthan V N break; 981d9718546SMugunthan V N 982d9718546SMugunthan V N case CPDMA_TX_STATS: 983d9718546SMugunthan V N p = (u8 *)&tx_stats + 984d9718546SMugunthan V N cpsw_gstrings_stats[i].stat_offset; 985d9718546SMugunthan V N data[i] = *(u32 *)p; 986d9718546SMugunthan V N break; 987d9718546SMugunthan V N } 988d9718546SMugunthan V N } 989d9718546SMugunthan V N } 990d9718546SMugunthan V N 991df828598SMugunthan V N static inline int __show_stat(char *buf, int maxlen, const char *name, u32 val) 992df828598SMugunthan V N { 993df828598SMugunthan V N static char *leader = "........................................"; 994df828598SMugunthan V N 995df828598SMugunthan V N if (!val) 996df828598SMugunthan V N return 0; 997df828598SMugunthan V N else 998df828598SMugunthan V N return snprintf(buf, maxlen, "%s %s %10d\n", name, 999df828598SMugunthan V N leader + strlen(name), val); 1000df828598SMugunthan V N } 1001df828598SMugunthan V N 1002d9ba8f9eSMugunthan V N static int cpsw_common_res_usage_state(struct cpsw_priv *priv) 1003d9ba8f9eSMugunthan V N { 1004d9ba8f9eSMugunthan V N u32 i; 1005d9ba8f9eSMugunthan V N u32 usage_count = 0; 1006d9ba8f9eSMugunthan V N 1007d9ba8f9eSMugunthan V N if (!priv->data.dual_emac) 1008d9ba8f9eSMugunthan V N return 0; 1009d9ba8f9eSMugunthan V N 1010d9ba8f9eSMugunthan V N for (i = 0; i < priv->data.slaves; i++) 1011d9ba8f9eSMugunthan V N if (priv->slaves[i].open_stat) 1012d9ba8f9eSMugunthan V N usage_count++; 1013d9ba8f9eSMugunthan V N 1014d9ba8f9eSMugunthan V N return usage_count; 1015d9ba8f9eSMugunthan V N } 1016d9ba8f9eSMugunthan V N 1017d9ba8f9eSMugunthan V N static inline int cpsw_tx_packet_submit(struct net_device *ndev, 1018d9ba8f9eSMugunthan V N struct cpsw_priv *priv, struct sk_buff *skb) 1019d9ba8f9eSMugunthan V N { 1020d9ba8f9eSMugunthan V N if (!priv->data.dual_emac) 1021d9ba8f9eSMugunthan V N return cpdma_chan_submit(priv->txch, skb, skb->data, 1022aef614e1SSebastian Siewior skb->len, 0); 1023d9ba8f9eSMugunthan V N 1024d9ba8f9eSMugunthan V N if (ndev == cpsw_get_slave_ndev(priv, 0)) 1025d9ba8f9eSMugunthan V N return cpdma_chan_submit(priv->txch, skb, skb->data, 1026aef614e1SSebastian Siewior skb->len, 1); 1027d9ba8f9eSMugunthan V N else 1028d9ba8f9eSMugunthan V N return cpdma_chan_submit(priv->txch, skb, skb->data, 1029aef614e1SSebastian Siewior skb->len, 2); 1030d9ba8f9eSMugunthan V N } 1031d9ba8f9eSMugunthan V N 1032d9ba8f9eSMugunthan V N static inline void cpsw_add_dual_emac_def_ale_entries( 1033d9ba8f9eSMugunthan V N struct cpsw_priv *priv, struct cpsw_slave *slave, 1034d9ba8f9eSMugunthan V N u32 slave_port) 1035d9ba8f9eSMugunthan V N { 1036d9ba8f9eSMugunthan V N u32 port_mask = 1 << slave_port | 1 << priv->host_port; 1037d9ba8f9eSMugunthan V N 1038d9ba8f9eSMugunthan V N if (priv->version == CPSW_VERSION_1) 1039d9ba8f9eSMugunthan V N slave_write(slave, slave->port_vlan, CPSW1_PORT_VLAN); 1040d9ba8f9eSMugunthan V N else 1041d9ba8f9eSMugunthan V N slave_write(slave, slave->port_vlan, CPSW2_PORT_VLAN); 1042d9ba8f9eSMugunthan V N cpsw_ale_add_vlan(priv->ale, slave->port_vlan, port_mask, 1043d9ba8f9eSMugunthan V N port_mask, port_mask, 0); 1044d9ba8f9eSMugunthan V N cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast, 1045d9ba8f9eSMugunthan V N port_mask, ALE_VLAN, slave->port_vlan, 0); 1046d9ba8f9eSMugunthan V N cpsw_ale_add_ucast(priv->ale, priv->mac_addr, 1047d9ba8f9eSMugunthan V N priv->host_port, ALE_VLAN, slave->port_vlan); 1048d9ba8f9eSMugunthan V N } 1049d9ba8f9eSMugunthan V N 10501e7a2e21SDaniel Mack static void soft_reset_slave(struct cpsw_slave *slave) 1051df828598SMugunthan V N { 1052df828598SMugunthan V N char name[32]; 10531e7a2e21SDaniel Mack 10541e7a2e21SDaniel Mack snprintf(name, sizeof(name), "slave-%d", slave->slave_num); 10551e7a2e21SDaniel Mack soft_reset(name, &slave->sliver->soft_reset); 10561e7a2e21SDaniel Mack } 10571e7a2e21SDaniel Mack 10581e7a2e21SDaniel Mack static void cpsw_slave_open(struct cpsw_slave *slave, struct cpsw_priv *priv) 10591e7a2e21SDaniel Mack { 1060df828598SMugunthan V N u32 slave_port; 1061df828598SMugunthan V N 10621e7a2e21SDaniel Mack soft_reset_slave(slave); 1063df828598SMugunthan V N 1064df828598SMugunthan V N /* setup priority mapping */ 1065df828598SMugunthan V N __raw_writel(RX_PRIORITY_MAPPING, &slave->sliver->rx_pri_map); 10669750a3adSRichard Cochran 10679750a3adSRichard Cochran switch (priv->version) { 10689750a3adSRichard Cochran case CPSW_VERSION_1: 10699750a3adSRichard Cochran slave_write(slave, TX_PRIORITY_MAPPING, CPSW1_TX_PRI_MAP); 10709750a3adSRichard Cochran break; 10719750a3adSRichard Cochran case CPSW_VERSION_2: 1072c193f365SMugunthan V N case CPSW_VERSION_3: 1073926489beSMugunthan V N case CPSW_VERSION_4: 10749750a3adSRichard Cochran slave_write(slave, TX_PRIORITY_MAPPING, CPSW2_TX_PRI_MAP); 10759750a3adSRichard Cochran break; 10769750a3adSRichard Cochran } 1077df828598SMugunthan V N 1078df828598SMugunthan V N /* setup max packet size, and mac address */ 1079df828598SMugunthan V N __raw_writel(priv->rx_packet_max, &slave->sliver->rx_maxlen); 1080df828598SMugunthan V N cpsw_set_slave_mac(slave, priv); 1081df828598SMugunthan V N 1082df828598SMugunthan V N slave->mac_control = 0; /* no link yet */ 1083df828598SMugunthan V N 1084df828598SMugunthan V N slave_port = cpsw_get_slave_port(priv, slave->slave_num); 1085df828598SMugunthan V N 1086d9ba8f9eSMugunthan V N if (priv->data.dual_emac) 1087d9ba8f9eSMugunthan V N cpsw_add_dual_emac_def_ale_entries(priv, slave, slave_port); 1088d9ba8f9eSMugunthan V N else 1089df828598SMugunthan V N cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast, 1090e11b220fSMugunthan V N 1 << slave_port, 0, 0, ALE_MCAST_FWD_2); 1091df828598SMugunthan V N 1092df828598SMugunthan V N slave->phy = phy_connect(priv->ndev, slave->data->phy_id, 1093f9a8f83bSFlorian Fainelli &cpsw_adjust_link, slave->data->phy_if); 1094df828598SMugunthan V N if (IS_ERR(slave->phy)) { 1095df828598SMugunthan V N dev_err(priv->dev, "phy %s not found on slave %d\n", 1096df828598SMugunthan V N slave->data->phy_id, slave->slave_num); 1097df828598SMugunthan V N slave->phy = NULL; 1098df828598SMugunthan V N } else { 1099df828598SMugunthan V N dev_info(priv->dev, "phy found : id is : 0x%x\n", 1100df828598SMugunthan V N slave->phy->phy_id); 1101df828598SMugunthan V N phy_start(slave->phy); 1102388367a5SMugunthan V N 1103388367a5SMugunthan V N /* Configure GMII_SEL register */ 1104388367a5SMugunthan V N cpsw_phy_sel(&priv->pdev->dev, slave->phy->interface, 1105388367a5SMugunthan V N slave->slave_num); 1106df828598SMugunthan V N } 1107df828598SMugunthan V N } 1108df828598SMugunthan V N 11093b72c2feSMugunthan V N static inline void cpsw_add_default_vlan(struct cpsw_priv *priv) 11103b72c2feSMugunthan V N { 11113b72c2feSMugunthan V N const int vlan = priv->data.default_vlan; 11123b72c2feSMugunthan V N const int port = priv->host_port; 11133b72c2feSMugunthan V N u32 reg; 11143b72c2feSMugunthan V N int i; 11153b72c2feSMugunthan V N 11163b72c2feSMugunthan V N reg = (priv->version == CPSW_VERSION_1) ? CPSW1_PORT_VLAN : 11173b72c2feSMugunthan V N CPSW2_PORT_VLAN; 11183b72c2feSMugunthan V N 11193b72c2feSMugunthan V N writel(vlan, &priv->host_port_regs->port_vlan); 11203b72c2feSMugunthan V N 11210237c110SDaniel Mack for (i = 0; i < priv->data.slaves; i++) 11223b72c2feSMugunthan V N slave_write(priv->slaves + i, vlan, reg); 11233b72c2feSMugunthan V N 11243b72c2feSMugunthan V N cpsw_ale_add_vlan(priv->ale, vlan, ALE_ALL_PORTS << port, 11253b72c2feSMugunthan V N ALE_ALL_PORTS << port, ALE_ALL_PORTS << port, 11263b72c2feSMugunthan V N (ALE_PORT_1 | ALE_PORT_2) << port); 11273b72c2feSMugunthan V N } 11283b72c2feSMugunthan V N 1129df828598SMugunthan V N static void cpsw_init_host_port(struct cpsw_priv *priv) 1130df828598SMugunthan V N { 11313b72c2feSMugunthan V N u32 control_reg; 1132d9ba8f9eSMugunthan V N u32 fifo_mode; 11333b72c2feSMugunthan V N 1134df828598SMugunthan V N /* soft reset the controller and initialize ale */ 1135df828598SMugunthan V N soft_reset("cpsw", &priv->regs->soft_reset); 1136df828598SMugunthan V N cpsw_ale_start(priv->ale); 1137df828598SMugunthan V N 1138df828598SMugunthan V N /* switch to vlan unaware mode */ 11393b72c2feSMugunthan V N cpsw_ale_control_set(priv->ale, priv->host_port, ALE_VLAN_AWARE, 11403b72c2feSMugunthan V N CPSW_ALE_VLAN_AWARE); 11413b72c2feSMugunthan V N control_reg = readl(&priv->regs->control); 11423b72c2feSMugunthan V N control_reg |= CPSW_VLAN_AWARE; 11433b72c2feSMugunthan V N writel(control_reg, &priv->regs->control); 1144d9ba8f9eSMugunthan V N fifo_mode = (priv->data.dual_emac) ? CPSW_FIFO_DUAL_MAC_MODE : 1145d9ba8f9eSMugunthan V N CPSW_FIFO_NORMAL_MODE; 1146d9ba8f9eSMugunthan V N writel(fifo_mode, &priv->host_port_regs->tx_in_ctl); 1147df828598SMugunthan V N 1148df828598SMugunthan V N /* setup host port priority mapping */ 1149df828598SMugunthan V N __raw_writel(CPDMA_TX_PRIORITY_MAP, 1150df828598SMugunthan V N &priv->host_port_regs->cpdma_tx_pri_map); 1151df828598SMugunthan V N __raw_writel(0, &priv->host_port_regs->cpdma_rx_chan_map); 1152df828598SMugunthan V N 1153df828598SMugunthan V N cpsw_ale_control_set(priv->ale, priv->host_port, 1154df828598SMugunthan V N ALE_PORT_STATE, ALE_PORT_STATE_FORWARD); 1155df828598SMugunthan V N 1156d9ba8f9eSMugunthan V N if (!priv->data.dual_emac) { 1157d9ba8f9eSMugunthan V N cpsw_ale_add_ucast(priv->ale, priv->mac_addr, priv->host_port, 1158d9ba8f9eSMugunthan V N 0, 0); 1159df828598SMugunthan V N cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast, 1160e11b220fSMugunthan V N 1 << priv->host_port, 0, 0, ALE_MCAST_FWD_2); 1161df828598SMugunthan V N } 1162d9ba8f9eSMugunthan V N } 1163df828598SMugunthan V N 1164aacebbf8SSebastian Siewior static void cpsw_slave_stop(struct cpsw_slave *slave, struct cpsw_priv *priv) 1165aacebbf8SSebastian Siewior { 11663995d265SSchuyler Patton u32 slave_port; 11673995d265SSchuyler Patton 11683995d265SSchuyler Patton slave_port = cpsw_get_slave_port(priv, slave->slave_num); 11693995d265SSchuyler Patton 1170aacebbf8SSebastian Siewior if (!slave->phy) 1171aacebbf8SSebastian Siewior return; 1172aacebbf8SSebastian Siewior phy_stop(slave->phy); 1173aacebbf8SSebastian Siewior phy_disconnect(slave->phy); 1174aacebbf8SSebastian Siewior slave->phy = NULL; 11753995d265SSchuyler Patton cpsw_ale_control_set(priv->ale, slave_port, 11763995d265SSchuyler Patton ALE_PORT_STATE, ALE_PORT_STATE_DISABLE); 1177aacebbf8SSebastian Siewior } 1178aacebbf8SSebastian Siewior 1179df828598SMugunthan V N static int cpsw_ndo_open(struct net_device *ndev) 1180df828598SMugunthan V N { 1181df828598SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 1182a11fbba9SSebastian Siewior struct cpsw_priv *prim_cpsw; 1183df828598SMugunthan V N int i, ret; 1184df828598SMugunthan V N u32 reg; 1185df828598SMugunthan V N 1186d9ba8f9eSMugunthan V N if (!cpsw_common_res_usage_state(priv)) 1187df828598SMugunthan V N cpsw_intr_disable(priv); 1188df828598SMugunthan V N netif_carrier_off(ndev); 1189df828598SMugunthan V N 1190f150bd7fSMugunthan V N pm_runtime_get_sync(&priv->pdev->dev); 1191df828598SMugunthan V N 1192549985eeSRichard Cochran reg = priv->version; 1193df828598SMugunthan V N 1194df828598SMugunthan V N dev_info(priv->dev, "initializing cpsw version %d.%d (%d)\n", 1195df828598SMugunthan V N CPSW_MAJOR_VERSION(reg), CPSW_MINOR_VERSION(reg), 1196df828598SMugunthan V N CPSW_RTL_VERSION(reg)); 1197df828598SMugunthan V N 1198df828598SMugunthan V N /* initialize host and slave ports */ 1199d9ba8f9eSMugunthan V N if (!cpsw_common_res_usage_state(priv)) 1200df828598SMugunthan V N cpsw_init_host_port(priv); 1201df828598SMugunthan V N for_each_slave(priv, cpsw_slave_open, priv); 1202df828598SMugunthan V N 12033b72c2feSMugunthan V N /* Add default VLAN */ 12043b72c2feSMugunthan V N cpsw_add_default_vlan(priv); 12053b72c2feSMugunthan V N 1206d9ba8f9eSMugunthan V N if (!cpsw_common_res_usage_state(priv)) { 1207df828598SMugunthan V N /* setup tx dma to fixed prio and zero offset */ 1208df828598SMugunthan V N cpdma_control_set(priv->dma, CPDMA_TX_PRIO_FIXED, 1); 1209df828598SMugunthan V N cpdma_control_set(priv->dma, CPDMA_RX_BUFFER_OFFSET, 0); 1210df828598SMugunthan V N 1211d9ba8f9eSMugunthan V N /* disable priority elevation */ 1212df828598SMugunthan V N __raw_writel(0, &priv->regs->ptype); 1213df828598SMugunthan V N 1214d9ba8f9eSMugunthan V N /* enable statistics collection only on all ports */ 1215df828598SMugunthan V N __raw_writel(0x7, &priv->regs->stat_port_en); 1216df828598SMugunthan V N 1217df828598SMugunthan V N if (WARN_ON(!priv->data.rx_descs)) 1218df828598SMugunthan V N priv->data.rx_descs = 128; 1219df828598SMugunthan V N 1220df828598SMugunthan V N for (i = 0; i < priv->data.rx_descs; i++) { 1221df828598SMugunthan V N struct sk_buff *skb; 1222df828598SMugunthan V N 1223df828598SMugunthan V N ret = -ENOMEM; 1224aacebbf8SSebastian Siewior skb = __netdev_alloc_skb_ip_align(priv->ndev, 1225aacebbf8SSebastian Siewior priv->rx_packet_max, GFP_KERNEL); 1226df828598SMugunthan V N if (!skb) 1227aacebbf8SSebastian Siewior goto err_cleanup; 1228df828598SMugunthan V N ret = cpdma_chan_submit(priv->rxch, skb, skb->data, 1229aef614e1SSebastian Siewior skb_tailroom(skb), 0); 1230aacebbf8SSebastian Siewior if (ret < 0) { 1231aacebbf8SSebastian Siewior kfree_skb(skb); 1232aacebbf8SSebastian Siewior goto err_cleanup; 1233aacebbf8SSebastian Siewior } 1234df828598SMugunthan V N } 1235d9ba8f9eSMugunthan V N /* continue even if we didn't manage to submit all 1236d9ba8f9eSMugunthan V N * receive descs 1237d9ba8f9eSMugunthan V N */ 1238df828598SMugunthan V N cpsw_info(priv, ifup, "submitted %d rx descriptors\n", i); 1239f280e89aSMugunthan V N 1240f280e89aSMugunthan V N if (cpts_register(&priv->pdev->dev, priv->cpts, 1241f280e89aSMugunthan V N priv->data.cpts_clock_mult, 1242f280e89aSMugunthan V N priv->data.cpts_clock_shift)) 1243f280e89aSMugunthan V N dev_err(priv->dev, "error registering cpts device\n"); 1244f280e89aSMugunthan V N 1245d9ba8f9eSMugunthan V N } 1246df828598SMugunthan V N 1247ff5b8ef2SMugunthan V N /* Enable Interrupt pacing if configured */ 1248ff5b8ef2SMugunthan V N if (priv->coal_intvl != 0) { 1249ff5b8ef2SMugunthan V N struct ethtool_coalesce coal; 1250ff5b8ef2SMugunthan V N 1251ff5b8ef2SMugunthan V N coal.rx_coalesce_usecs = (priv->coal_intvl << 4); 1252ff5b8ef2SMugunthan V N cpsw_set_coalesce(ndev, &coal); 1253ff5b8ef2SMugunthan V N } 1254ff5b8ef2SMugunthan V N 1255a11fbba9SSebastian Siewior prim_cpsw = cpsw_get_slave_priv(priv, 0); 1256a11fbba9SSebastian Siewior if (prim_cpsw->irq_enabled == false) { 1257a11fbba9SSebastian Siewior if ((priv == prim_cpsw) || !netif_running(prim_cpsw->ndev)) { 1258a11fbba9SSebastian Siewior prim_cpsw->irq_enabled = true; 1259a11fbba9SSebastian Siewior cpsw_enable_irq(prim_cpsw); 1260a11fbba9SSebastian Siewior } 1261a11fbba9SSebastian Siewior } 1262a11fbba9SSebastian Siewior 1263dbbd2ad8SMarkus Pargmann napi_enable(&priv->napi); 1264df828598SMugunthan V N cpdma_ctlr_start(priv->dma); 1265df828598SMugunthan V N cpsw_intr_enable(priv); 1266510a1e72SMugunthan V N cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_RX); 1267510a1e72SMugunthan V N cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_TX); 1268df828598SMugunthan V N 1269d9ba8f9eSMugunthan V N if (priv->data.dual_emac) 1270d9ba8f9eSMugunthan V N priv->slaves[priv->emac_port].open_stat = true; 1271df828598SMugunthan V N return 0; 1272df828598SMugunthan V N 1273aacebbf8SSebastian Siewior err_cleanup: 1274aacebbf8SSebastian Siewior cpdma_ctlr_stop(priv->dma); 1275aacebbf8SSebastian Siewior for_each_slave(priv, cpsw_slave_stop, priv); 1276aacebbf8SSebastian Siewior pm_runtime_put_sync(&priv->pdev->dev); 1277aacebbf8SSebastian Siewior netif_carrier_off(priv->ndev); 1278aacebbf8SSebastian Siewior return ret; 1279df828598SMugunthan V N } 1280df828598SMugunthan V N 1281df828598SMugunthan V N static int cpsw_ndo_stop(struct net_device *ndev) 1282df828598SMugunthan V N { 1283df828598SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 1284df828598SMugunthan V N 1285df828598SMugunthan V N cpsw_info(priv, ifdown, "shutting down cpsw device\n"); 1286df828598SMugunthan V N netif_stop_queue(priv->ndev); 1287df828598SMugunthan V N napi_disable(&priv->napi); 1288df828598SMugunthan V N netif_carrier_off(priv->ndev); 1289d9ba8f9eSMugunthan V N 1290d9ba8f9eSMugunthan V N if (cpsw_common_res_usage_state(priv) <= 1) { 1291f280e89aSMugunthan V N cpts_unregister(priv->cpts); 129271380f9bSMugunthan V N cpsw_intr_disable(priv); 129371380f9bSMugunthan V N cpdma_ctlr_int_ctrl(priv->dma, false); 129471380f9bSMugunthan V N cpdma_ctlr_stop(priv->dma); 1295df828598SMugunthan V N cpsw_ale_stop(priv->ale); 1296d9ba8f9eSMugunthan V N } 1297df828598SMugunthan V N for_each_slave(priv, cpsw_slave_stop, priv); 1298f150bd7fSMugunthan V N pm_runtime_put_sync(&priv->pdev->dev); 1299d9ba8f9eSMugunthan V N if (priv->data.dual_emac) 1300d9ba8f9eSMugunthan V N priv->slaves[priv->emac_port].open_stat = false; 1301df828598SMugunthan V N return 0; 1302df828598SMugunthan V N } 1303df828598SMugunthan V N 1304df828598SMugunthan V N static netdev_tx_t cpsw_ndo_start_xmit(struct sk_buff *skb, 1305df828598SMugunthan V N struct net_device *ndev) 1306df828598SMugunthan V N { 1307df828598SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 1308df828598SMugunthan V N int ret; 1309df828598SMugunthan V N 1310df828598SMugunthan V N ndev->trans_start = jiffies; 1311df828598SMugunthan V N 1312df828598SMugunthan V N if (skb_padto(skb, CPSW_MIN_PACKET_SIZE)) { 1313df828598SMugunthan V N cpsw_err(priv, tx_err, "packet pad failed\n"); 13148dc43ddcSTobias Klauser ndev->stats.tx_dropped++; 1315df828598SMugunthan V N return NETDEV_TX_OK; 1316df828598SMugunthan V N } 1317df828598SMugunthan V N 13189232b16dSMugunthan V N if (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP && 13199232b16dSMugunthan V N priv->cpts->tx_enable) 13202e5b38abSRichard Cochran skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 13212e5b38abSRichard Cochran 13222e5b38abSRichard Cochran skb_tx_timestamp(skb); 13232e5b38abSRichard Cochran 1324d9ba8f9eSMugunthan V N ret = cpsw_tx_packet_submit(ndev, priv, skb); 1325df828598SMugunthan V N if (unlikely(ret != 0)) { 1326df828598SMugunthan V N cpsw_err(priv, tx_err, "desc submit failed\n"); 1327df828598SMugunthan V N goto fail; 1328df828598SMugunthan V N } 1329df828598SMugunthan V N 1330fae50823SMugunthan V N /* If there is no more tx desc left free then we need to 1331fae50823SMugunthan V N * tell the kernel to stop sending us tx frames. 1332fae50823SMugunthan V N */ 1333d35162f8SDaniel Mack if (unlikely(!cpdma_check_free_tx_desc(priv->txch))) 1334fae50823SMugunthan V N netif_stop_queue(ndev); 1335fae50823SMugunthan V N 1336df828598SMugunthan V N return NETDEV_TX_OK; 1337df828598SMugunthan V N fail: 13388dc43ddcSTobias Klauser ndev->stats.tx_dropped++; 1339df828598SMugunthan V N netif_stop_queue(ndev); 1340df828598SMugunthan V N return NETDEV_TX_BUSY; 1341df828598SMugunthan V N } 1342df828598SMugunthan V N 13432e5b38abSRichard Cochran #ifdef CONFIG_TI_CPTS 13442e5b38abSRichard Cochran 13452e5b38abSRichard Cochran static void cpsw_hwtstamp_v1(struct cpsw_priv *priv) 13462e5b38abSRichard Cochran { 1347e86ac13bSMugunthan V N struct cpsw_slave *slave = &priv->slaves[priv->data.active_slave]; 13482e5b38abSRichard Cochran u32 ts_en, seq_id; 13492e5b38abSRichard Cochran 13509232b16dSMugunthan V N if (!priv->cpts->tx_enable && !priv->cpts->rx_enable) { 13512e5b38abSRichard Cochran slave_write(slave, 0, CPSW1_TS_CTL); 13522e5b38abSRichard Cochran return; 13532e5b38abSRichard Cochran } 13542e5b38abSRichard Cochran 13552e5b38abSRichard Cochran seq_id = (30 << CPSW_V1_SEQ_ID_OFS_SHIFT) | ETH_P_1588; 13562e5b38abSRichard Cochran ts_en = EVENT_MSG_BITS << CPSW_V1_MSG_TYPE_OFS; 13572e5b38abSRichard Cochran 13589232b16dSMugunthan V N if (priv->cpts->tx_enable) 13592e5b38abSRichard Cochran ts_en |= CPSW_V1_TS_TX_EN; 13602e5b38abSRichard Cochran 13619232b16dSMugunthan V N if (priv->cpts->rx_enable) 13622e5b38abSRichard Cochran ts_en |= CPSW_V1_TS_RX_EN; 13632e5b38abSRichard Cochran 13642e5b38abSRichard Cochran slave_write(slave, ts_en, CPSW1_TS_CTL); 13652e5b38abSRichard Cochran slave_write(slave, seq_id, CPSW1_TS_SEQ_LTYPE); 13662e5b38abSRichard Cochran } 13672e5b38abSRichard Cochran 13682e5b38abSRichard Cochran static void cpsw_hwtstamp_v2(struct cpsw_priv *priv) 13692e5b38abSRichard Cochran { 1370d9ba8f9eSMugunthan V N struct cpsw_slave *slave; 13712e5b38abSRichard Cochran u32 ctrl, mtype; 13722e5b38abSRichard Cochran 1373d9ba8f9eSMugunthan V N if (priv->data.dual_emac) 1374d9ba8f9eSMugunthan V N slave = &priv->slaves[priv->emac_port]; 1375d9ba8f9eSMugunthan V N else 1376e86ac13bSMugunthan V N slave = &priv->slaves[priv->data.active_slave]; 1377d9ba8f9eSMugunthan V N 13782e5b38abSRichard Cochran ctrl = slave_read(slave, CPSW2_CONTROL); 13792e5b38abSRichard Cochran ctrl &= ~CTRL_ALL_TS_MASK; 13802e5b38abSRichard Cochran 13819232b16dSMugunthan V N if (priv->cpts->tx_enable) 13822e5b38abSRichard Cochran ctrl |= CTRL_TX_TS_BITS; 13832e5b38abSRichard Cochran 13849232b16dSMugunthan V N if (priv->cpts->rx_enable) 13852e5b38abSRichard Cochran ctrl |= CTRL_RX_TS_BITS; 13862e5b38abSRichard Cochran 13872e5b38abSRichard Cochran mtype = (30 << TS_SEQ_ID_OFFSET_SHIFT) | EVENT_MSG_BITS; 13882e5b38abSRichard Cochran 13892e5b38abSRichard Cochran slave_write(slave, mtype, CPSW2_TS_SEQ_MTYPE); 13902e5b38abSRichard Cochran slave_write(slave, ctrl, CPSW2_CONTROL); 13912e5b38abSRichard Cochran __raw_writel(ETH_P_1588, &priv->regs->ts_ltype); 13922e5b38abSRichard Cochran } 13932e5b38abSRichard Cochran 1394a5b4145bSBen Hutchings static int cpsw_hwtstamp_set(struct net_device *dev, struct ifreq *ifr) 13952e5b38abSRichard Cochran { 13963177bf6fSMugunthan V N struct cpsw_priv *priv = netdev_priv(dev); 13979232b16dSMugunthan V N struct cpts *cpts = priv->cpts; 13982e5b38abSRichard Cochran struct hwtstamp_config cfg; 13992e5b38abSRichard Cochran 14002ee91e54SBen Hutchings if (priv->version != CPSW_VERSION_1 && 14012ee91e54SBen Hutchings priv->version != CPSW_VERSION_2) 14022ee91e54SBen Hutchings return -EOPNOTSUPP; 14032ee91e54SBen Hutchings 14042e5b38abSRichard Cochran if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg))) 14052e5b38abSRichard Cochran return -EFAULT; 14062e5b38abSRichard Cochran 14072e5b38abSRichard Cochran /* reserved for future extensions */ 14082e5b38abSRichard Cochran if (cfg.flags) 14092e5b38abSRichard Cochran return -EINVAL; 14102e5b38abSRichard Cochran 14112ee91e54SBen Hutchings if (cfg.tx_type != HWTSTAMP_TX_OFF && cfg.tx_type != HWTSTAMP_TX_ON) 14122e5b38abSRichard Cochran return -ERANGE; 14132e5b38abSRichard Cochran 14142e5b38abSRichard Cochran switch (cfg.rx_filter) { 14152e5b38abSRichard Cochran case HWTSTAMP_FILTER_NONE: 14162e5b38abSRichard Cochran cpts->rx_enable = 0; 14172e5b38abSRichard Cochran break; 14182e5b38abSRichard Cochran case HWTSTAMP_FILTER_ALL: 14192e5b38abSRichard Cochran case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: 14202e5b38abSRichard Cochran case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: 14212e5b38abSRichard Cochran case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: 14222e5b38abSRichard Cochran return -ERANGE; 14232e5b38abSRichard Cochran case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: 14242e5b38abSRichard Cochran case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 14252e5b38abSRichard Cochran case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 14262e5b38abSRichard Cochran case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: 14272e5b38abSRichard Cochran case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: 14282e5b38abSRichard Cochran case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: 14292e5b38abSRichard Cochran case HWTSTAMP_FILTER_PTP_V2_EVENT: 14302e5b38abSRichard Cochran case HWTSTAMP_FILTER_PTP_V2_SYNC: 14312e5b38abSRichard Cochran case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 14322e5b38abSRichard Cochran cpts->rx_enable = 1; 14332e5b38abSRichard Cochran cfg.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT; 14342e5b38abSRichard Cochran break; 14352e5b38abSRichard Cochran default: 14362e5b38abSRichard Cochran return -ERANGE; 14372e5b38abSRichard Cochran } 14382e5b38abSRichard Cochran 14392ee91e54SBen Hutchings cpts->tx_enable = cfg.tx_type == HWTSTAMP_TX_ON; 14402ee91e54SBen Hutchings 14412e5b38abSRichard Cochran switch (priv->version) { 14422e5b38abSRichard Cochran case CPSW_VERSION_1: 14432e5b38abSRichard Cochran cpsw_hwtstamp_v1(priv); 14442e5b38abSRichard Cochran break; 14452e5b38abSRichard Cochran case CPSW_VERSION_2: 14462e5b38abSRichard Cochran cpsw_hwtstamp_v2(priv); 14472e5b38abSRichard Cochran break; 14482e5b38abSRichard Cochran default: 14492ee91e54SBen Hutchings WARN_ON(1); 14502e5b38abSRichard Cochran } 14512e5b38abSRichard Cochran 14522e5b38abSRichard Cochran return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0; 14532e5b38abSRichard Cochran } 14542e5b38abSRichard Cochran 1455a5b4145bSBen Hutchings static int cpsw_hwtstamp_get(struct net_device *dev, struct ifreq *ifr) 1456a5b4145bSBen Hutchings { 1457a5b4145bSBen Hutchings struct cpsw_priv *priv = netdev_priv(dev); 1458a5b4145bSBen Hutchings struct cpts *cpts = priv->cpts; 1459a5b4145bSBen Hutchings struct hwtstamp_config cfg; 1460a5b4145bSBen Hutchings 1461a5b4145bSBen Hutchings if (priv->version != CPSW_VERSION_1 && 1462a5b4145bSBen Hutchings priv->version != CPSW_VERSION_2) 1463a5b4145bSBen Hutchings return -EOPNOTSUPP; 1464a5b4145bSBen Hutchings 1465a5b4145bSBen Hutchings cfg.flags = 0; 1466a5b4145bSBen Hutchings cfg.tx_type = cpts->tx_enable ? HWTSTAMP_TX_ON : HWTSTAMP_TX_OFF; 1467a5b4145bSBen Hutchings cfg.rx_filter = (cpts->rx_enable ? 1468a5b4145bSBen Hutchings HWTSTAMP_FILTER_PTP_V2_EVENT : HWTSTAMP_FILTER_NONE); 1469a5b4145bSBen Hutchings 1470a5b4145bSBen Hutchings return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0; 1471a5b4145bSBen Hutchings } 1472a5b4145bSBen Hutchings 14732e5b38abSRichard Cochran #endif /*CONFIG_TI_CPTS*/ 14742e5b38abSRichard Cochran 14752e5b38abSRichard Cochran static int cpsw_ndo_ioctl(struct net_device *dev, struct ifreq *req, int cmd) 14762e5b38abSRichard Cochran { 147711f2c988SMugunthan V N struct cpsw_priv *priv = netdev_priv(dev); 147811f2c988SMugunthan V N int slave_no = cpsw_slave_index(priv); 147911f2c988SMugunthan V N 14802e5b38abSRichard Cochran if (!netif_running(dev)) 14812e5b38abSRichard Cochran return -EINVAL; 14822e5b38abSRichard Cochran 148311f2c988SMugunthan V N switch (cmd) { 14842e5b38abSRichard Cochran #ifdef CONFIG_TI_CPTS 148511f2c988SMugunthan V N case SIOCSHWTSTAMP: 1486a5b4145bSBen Hutchings return cpsw_hwtstamp_set(dev, req); 1487a5b4145bSBen Hutchings case SIOCGHWTSTAMP: 1488a5b4145bSBen Hutchings return cpsw_hwtstamp_get(dev, req); 14892e5b38abSRichard Cochran #endif 14902e5b38abSRichard Cochran } 14912e5b38abSRichard Cochran 1492c1b59947SStefan Sørensen if (!priv->slaves[slave_no].phy) 1493c1b59947SStefan Sørensen return -EOPNOTSUPP; 1494c1b59947SStefan Sørensen return phy_mii_ioctl(priv->slaves[slave_no].phy, req, cmd); 149511f2c988SMugunthan V N } 149611f2c988SMugunthan V N 1497df828598SMugunthan V N static void cpsw_ndo_tx_timeout(struct net_device *ndev) 1498df828598SMugunthan V N { 1499df828598SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 1500df828598SMugunthan V N 1501df828598SMugunthan V N cpsw_err(priv, tx_err, "transmit timeout, restarting dma\n"); 15028dc43ddcSTobias Klauser ndev->stats.tx_errors++; 1503df828598SMugunthan V N cpsw_intr_disable(priv); 1504df828598SMugunthan V N cpdma_ctlr_int_ctrl(priv->dma, false); 1505df828598SMugunthan V N cpdma_chan_stop(priv->txch); 1506df828598SMugunthan V N cpdma_chan_start(priv->txch); 1507df828598SMugunthan V N cpdma_ctlr_int_ctrl(priv->dma, true); 1508df828598SMugunthan V N cpsw_intr_enable(priv); 1509510a1e72SMugunthan V N cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_RX); 1510510a1e72SMugunthan V N cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_TX); 1511510a1e72SMugunthan V N 1512df828598SMugunthan V N } 1513df828598SMugunthan V N 1514dcfd8d58SMugunthan V N static int cpsw_ndo_set_mac_address(struct net_device *ndev, void *p) 1515dcfd8d58SMugunthan V N { 1516dcfd8d58SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 1517dcfd8d58SMugunthan V N struct sockaddr *addr = (struct sockaddr *)p; 1518dcfd8d58SMugunthan V N int flags = 0; 1519dcfd8d58SMugunthan V N u16 vid = 0; 1520dcfd8d58SMugunthan V N 1521dcfd8d58SMugunthan V N if (!is_valid_ether_addr(addr->sa_data)) 1522dcfd8d58SMugunthan V N return -EADDRNOTAVAIL; 1523dcfd8d58SMugunthan V N 1524dcfd8d58SMugunthan V N if (priv->data.dual_emac) { 1525dcfd8d58SMugunthan V N vid = priv->slaves[priv->emac_port].port_vlan; 1526dcfd8d58SMugunthan V N flags = ALE_VLAN; 1527dcfd8d58SMugunthan V N } 1528dcfd8d58SMugunthan V N 1529dcfd8d58SMugunthan V N cpsw_ale_del_ucast(priv->ale, priv->mac_addr, priv->host_port, 1530dcfd8d58SMugunthan V N flags, vid); 1531dcfd8d58SMugunthan V N cpsw_ale_add_ucast(priv->ale, addr->sa_data, priv->host_port, 1532dcfd8d58SMugunthan V N flags, vid); 1533dcfd8d58SMugunthan V N 1534dcfd8d58SMugunthan V N memcpy(priv->mac_addr, addr->sa_data, ETH_ALEN); 1535dcfd8d58SMugunthan V N memcpy(ndev->dev_addr, priv->mac_addr, ETH_ALEN); 1536dcfd8d58SMugunthan V N for_each_slave(priv, cpsw_set_slave_mac, priv); 1537dcfd8d58SMugunthan V N 1538dcfd8d58SMugunthan V N return 0; 1539dcfd8d58SMugunthan V N } 1540dcfd8d58SMugunthan V N 1541df828598SMugunthan V N #ifdef CONFIG_NET_POLL_CONTROLLER 1542df828598SMugunthan V N static void cpsw_ndo_poll_controller(struct net_device *ndev) 1543df828598SMugunthan V N { 1544df828598SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 1545df828598SMugunthan V N 1546df828598SMugunthan V N cpsw_intr_disable(priv); 1547df828598SMugunthan V N cpdma_ctlr_int_ctrl(priv->dma, false); 1548df828598SMugunthan V N cpsw_interrupt(ndev->irq, priv); 1549df828598SMugunthan V N cpdma_ctlr_int_ctrl(priv->dma, true); 1550df828598SMugunthan V N cpsw_intr_enable(priv); 1551510a1e72SMugunthan V N cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_RX); 1552510a1e72SMugunthan V N cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_TX); 1553510a1e72SMugunthan V N 1554df828598SMugunthan V N } 1555df828598SMugunthan V N #endif 1556df828598SMugunthan V N 15573b72c2feSMugunthan V N static inline int cpsw_add_vlan_ale_entry(struct cpsw_priv *priv, 15583b72c2feSMugunthan V N unsigned short vid) 15593b72c2feSMugunthan V N { 15603b72c2feSMugunthan V N int ret; 15613b72c2feSMugunthan V N 15623b72c2feSMugunthan V N ret = cpsw_ale_add_vlan(priv->ale, vid, 15633b72c2feSMugunthan V N ALE_ALL_PORTS << priv->host_port, 15643b72c2feSMugunthan V N 0, ALE_ALL_PORTS << priv->host_port, 15653b72c2feSMugunthan V N (ALE_PORT_1 | ALE_PORT_2) << priv->host_port); 15663b72c2feSMugunthan V N if (ret != 0) 15673b72c2feSMugunthan V N return ret; 15683b72c2feSMugunthan V N 15693b72c2feSMugunthan V N ret = cpsw_ale_add_ucast(priv->ale, priv->mac_addr, 15703b72c2feSMugunthan V N priv->host_port, ALE_VLAN, vid); 15713b72c2feSMugunthan V N if (ret != 0) 15723b72c2feSMugunthan V N goto clean_vid; 15733b72c2feSMugunthan V N 15743b72c2feSMugunthan V N ret = cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast, 15753b72c2feSMugunthan V N ALE_ALL_PORTS << priv->host_port, 15763b72c2feSMugunthan V N ALE_VLAN, vid, 0); 15773b72c2feSMugunthan V N if (ret != 0) 15783b72c2feSMugunthan V N goto clean_vlan_ucast; 15793b72c2feSMugunthan V N return 0; 15803b72c2feSMugunthan V N 15813b72c2feSMugunthan V N clean_vlan_ucast: 15823b72c2feSMugunthan V N cpsw_ale_del_ucast(priv->ale, priv->mac_addr, 15833b72c2feSMugunthan V N priv->host_port, ALE_VLAN, vid); 15843b72c2feSMugunthan V N clean_vid: 15853b72c2feSMugunthan V N cpsw_ale_del_vlan(priv->ale, vid, 0); 15863b72c2feSMugunthan V N return ret; 15873b72c2feSMugunthan V N } 15883b72c2feSMugunthan V N 15893b72c2feSMugunthan V N static int cpsw_ndo_vlan_rx_add_vid(struct net_device *ndev, 159080d5c368SPatrick McHardy __be16 proto, u16 vid) 15913b72c2feSMugunthan V N { 15923b72c2feSMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 15933b72c2feSMugunthan V N 15943b72c2feSMugunthan V N if (vid == priv->data.default_vlan) 15953b72c2feSMugunthan V N return 0; 15963b72c2feSMugunthan V N 15973b72c2feSMugunthan V N dev_info(priv->dev, "Adding vlanid %d to vlan filter\n", vid); 15983b72c2feSMugunthan V N return cpsw_add_vlan_ale_entry(priv, vid); 15993b72c2feSMugunthan V N } 16003b72c2feSMugunthan V N 16013b72c2feSMugunthan V N static int cpsw_ndo_vlan_rx_kill_vid(struct net_device *ndev, 160280d5c368SPatrick McHardy __be16 proto, u16 vid) 16033b72c2feSMugunthan V N { 16043b72c2feSMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 16053b72c2feSMugunthan V N int ret; 16063b72c2feSMugunthan V N 16073b72c2feSMugunthan V N if (vid == priv->data.default_vlan) 16083b72c2feSMugunthan V N return 0; 16093b72c2feSMugunthan V N 16103b72c2feSMugunthan V N dev_info(priv->dev, "removing vlanid %d from vlan filter\n", vid); 16113b72c2feSMugunthan V N ret = cpsw_ale_del_vlan(priv->ale, vid, 0); 16123b72c2feSMugunthan V N if (ret != 0) 16133b72c2feSMugunthan V N return ret; 16143b72c2feSMugunthan V N 16153b72c2feSMugunthan V N ret = cpsw_ale_del_ucast(priv->ale, priv->mac_addr, 16163b72c2feSMugunthan V N priv->host_port, ALE_VLAN, vid); 16173b72c2feSMugunthan V N if (ret != 0) 16183b72c2feSMugunthan V N return ret; 16193b72c2feSMugunthan V N 16203b72c2feSMugunthan V N return cpsw_ale_del_mcast(priv->ale, priv->ndev->broadcast, 16213b72c2feSMugunthan V N 0, ALE_VLAN, vid); 16223b72c2feSMugunthan V N } 16233b72c2feSMugunthan V N 1624df828598SMugunthan V N static const struct net_device_ops cpsw_netdev_ops = { 1625df828598SMugunthan V N .ndo_open = cpsw_ndo_open, 1626df828598SMugunthan V N .ndo_stop = cpsw_ndo_stop, 1627df828598SMugunthan V N .ndo_start_xmit = cpsw_ndo_start_xmit, 1628dcfd8d58SMugunthan V N .ndo_set_mac_address = cpsw_ndo_set_mac_address, 16292e5b38abSRichard Cochran .ndo_do_ioctl = cpsw_ndo_ioctl, 1630df828598SMugunthan V N .ndo_validate_addr = eth_validate_addr, 16315c473ed2SDavid S. Miller .ndo_change_mtu = eth_change_mtu, 1632df828598SMugunthan V N .ndo_tx_timeout = cpsw_ndo_tx_timeout, 16335c50a856SMugunthan V N .ndo_set_rx_mode = cpsw_ndo_set_rx_mode, 1634df828598SMugunthan V N #ifdef CONFIG_NET_POLL_CONTROLLER 1635df828598SMugunthan V N .ndo_poll_controller = cpsw_ndo_poll_controller, 1636df828598SMugunthan V N #endif 16373b72c2feSMugunthan V N .ndo_vlan_rx_add_vid = cpsw_ndo_vlan_rx_add_vid, 16383b72c2feSMugunthan V N .ndo_vlan_rx_kill_vid = cpsw_ndo_vlan_rx_kill_vid, 1639df828598SMugunthan V N }; 1640df828598SMugunthan V N 1641df828598SMugunthan V N static void cpsw_get_drvinfo(struct net_device *ndev, 1642df828598SMugunthan V N struct ethtool_drvinfo *info) 1643df828598SMugunthan V N { 1644df828598SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 16457826d43fSJiri Pirko 16467826d43fSJiri Pirko strlcpy(info->driver, "TI CPSW Driver v1.0", sizeof(info->driver)); 16477826d43fSJiri Pirko strlcpy(info->version, "1.0", sizeof(info->version)); 16487826d43fSJiri Pirko strlcpy(info->bus_info, priv->pdev->name, sizeof(info->bus_info)); 1649df828598SMugunthan V N } 1650df828598SMugunthan V N 1651df828598SMugunthan V N static u32 cpsw_get_msglevel(struct net_device *ndev) 1652df828598SMugunthan V N { 1653df828598SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 1654df828598SMugunthan V N return priv->msg_enable; 1655df828598SMugunthan V N } 1656df828598SMugunthan V N 1657df828598SMugunthan V N static void cpsw_set_msglevel(struct net_device *ndev, u32 value) 1658df828598SMugunthan V N { 1659df828598SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 1660df828598SMugunthan V N priv->msg_enable = value; 1661df828598SMugunthan V N } 1662df828598SMugunthan V N 16632e5b38abSRichard Cochran static int cpsw_get_ts_info(struct net_device *ndev, 16642e5b38abSRichard Cochran struct ethtool_ts_info *info) 16652e5b38abSRichard Cochran { 16662e5b38abSRichard Cochran #ifdef CONFIG_TI_CPTS 16672e5b38abSRichard Cochran struct cpsw_priv *priv = netdev_priv(ndev); 16682e5b38abSRichard Cochran 16692e5b38abSRichard Cochran info->so_timestamping = 16702e5b38abSRichard Cochran SOF_TIMESTAMPING_TX_HARDWARE | 16712e5b38abSRichard Cochran SOF_TIMESTAMPING_TX_SOFTWARE | 16722e5b38abSRichard Cochran SOF_TIMESTAMPING_RX_HARDWARE | 16732e5b38abSRichard Cochran SOF_TIMESTAMPING_RX_SOFTWARE | 16742e5b38abSRichard Cochran SOF_TIMESTAMPING_SOFTWARE | 16752e5b38abSRichard Cochran SOF_TIMESTAMPING_RAW_HARDWARE; 16769232b16dSMugunthan V N info->phc_index = priv->cpts->phc_index; 16772e5b38abSRichard Cochran info->tx_types = 16782e5b38abSRichard Cochran (1 << HWTSTAMP_TX_OFF) | 16792e5b38abSRichard Cochran (1 << HWTSTAMP_TX_ON); 16802e5b38abSRichard Cochran info->rx_filters = 16812e5b38abSRichard Cochran (1 << HWTSTAMP_FILTER_NONE) | 16822e5b38abSRichard Cochran (1 << HWTSTAMP_FILTER_PTP_V2_EVENT); 16832e5b38abSRichard Cochran #else 16842e5b38abSRichard Cochran info->so_timestamping = 16852e5b38abSRichard Cochran SOF_TIMESTAMPING_TX_SOFTWARE | 16862e5b38abSRichard Cochran SOF_TIMESTAMPING_RX_SOFTWARE | 16872e5b38abSRichard Cochran SOF_TIMESTAMPING_SOFTWARE; 16882e5b38abSRichard Cochran info->phc_index = -1; 16892e5b38abSRichard Cochran info->tx_types = 0; 16902e5b38abSRichard Cochran info->rx_filters = 0; 16912e5b38abSRichard Cochran #endif 16922e5b38abSRichard Cochran return 0; 16932e5b38abSRichard Cochran } 16942e5b38abSRichard Cochran 1695d3bb9c58SMugunthan V N static int cpsw_get_settings(struct net_device *ndev, 1696d3bb9c58SMugunthan V N struct ethtool_cmd *ecmd) 1697d3bb9c58SMugunthan V N { 1698d3bb9c58SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 1699d3bb9c58SMugunthan V N int slave_no = cpsw_slave_index(priv); 1700d3bb9c58SMugunthan V N 1701d3bb9c58SMugunthan V N if (priv->slaves[slave_no].phy) 1702d3bb9c58SMugunthan V N return phy_ethtool_gset(priv->slaves[slave_no].phy, ecmd); 1703d3bb9c58SMugunthan V N else 1704d3bb9c58SMugunthan V N return -EOPNOTSUPP; 1705d3bb9c58SMugunthan V N } 1706d3bb9c58SMugunthan V N 1707d3bb9c58SMugunthan V N static int cpsw_set_settings(struct net_device *ndev, struct ethtool_cmd *ecmd) 1708d3bb9c58SMugunthan V N { 1709d3bb9c58SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 1710d3bb9c58SMugunthan V N int slave_no = cpsw_slave_index(priv); 1711d3bb9c58SMugunthan V N 1712d3bb9c58SMugunthan V N if (priv->slaves[slave_no].phy) 1713d3bb9c58SMugunthan V N return phy_ethtool_sset(priv->slaves[slave_no].phy, ecmd); 1714d3bb9c58SMugunthan V N else 1715d3bb9c58SMugunthan V N return -EOPNOTSUPP; 1716d3bb9c58SMugunthan V N } 1717d3bb9c58SMugunthan V N 1718d8a64420SMatus Ujhelyi static void cpsw_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol) 1719d8a64420SMatus Ujhelyi { 1720d8a64420SMatus Ujhelyi struct cpsw_priv *priv = netdev_priv(ndev); 1721d8a64420SMatus Ujhelyi int slave_no = cpsw_slave_index(priv); 1722d8a64420SMatus Ujhelyi 1723d8a64420SMatus Ujhelyi wol->supported = 0; 1724d8a64420SMatus Ujhelyi wol->wolopts = 0; 1725d8a64420SMatus Ujhelyi 1726d8a64420SMatus Ujhelyi if (priv->slaves[slave_no].phy) 1727d8a64420SMatus Ujhelyi phy_ethtool_get_wol(priv->slaves[slave_no].phy, wol); 1728d8a64420SMatus Ujhelyi } 1729d8a64420SMatus Ujhelyi 1730d8a64420SMatus Ujhelyi static int cpsw_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol) 1731d8a64420SMatus Ujhelyi { 1732d8a64420SMatus Ujhelyi struct cpsw_priv *priv = netdev_priv(ndev); 1733d8a64420SMatus Ujhelyi int slave_no = cpsw_slave_index(priv); 1734d8a64420SMatus Ujhelyi 1735d8a64420SMatus Ujhelyi if (priv->slaves[slave_no].phy) 1736d8a64420SMatus Ujhelyi return phy_ethtool_set_wol(priv->slaves[slave_no].phy, wol); 1737d8a64420SMatus Ujhelyi else 1738d8a64420SMatus Ujhelyi return -EOPNOTSUPP; 1739d8a64420SMatus Ujhelyi } 1740d8a64420SMatus Ujhelyi 1741df828598SMugunthan V N static const struct ethtool_ops cpsw_ethtool_ops = { 1742df828598SMugunthan V N .get_drvinfo = cpsw_get_drvinfo, 1743df828598SMugunthan V N .get_msglevel = cpsw_get_msglevel, 1744df828598SMugunthan V N .set_msglevel = cpsw_set_msglevel, 1745df828598SMugunthan V N .get_link = ethtool_op_get_link, 17462e5b38abSRichard Cochran .get_ts_info = cpsw_get_ts_info, 1747d3bb9c58SMugunthan V N .get_settings = cpsw_get_settings, 1748d3bb9c58SMugunthan V N .set_settings = cpsw_set_settings, 1749ff5b8ef2SMugunthan V N .get_coalesce = cpsw_get_coalesce, 1750ff5b8ef2SMugunthan V N .set_coalesce = cpsw_set_coalesce, 1751d9718546SMugunthan V N .get_sset_count = cpsw_get_sset_count, 1752d9718546SMugunthan V N .get_strings = cpsw_get_strings, 1753d9718546SMugunthan V N .get_ethtool_stats = cpsw_get_ethtool_stats, 1754d8a64420SMatus Ujhelyi .get_wol = cpsw_get_wol, 1755d8a64420SMatus Ujhelyi .set_wol = cpsw_set_wol, 1756df828598SMugunthan V N }; 1757df828598SMugunthan V N 1758549985eeSRichard Cochran static void cpsw_slave_init(struct cpsw_slave *slave, struct cpsw_priv *priv, 1759549985eeSRichard Cochran u32 slave_reg_ofs, u32 sliver_reg_ofs) 1760df828598SMugunthan V N { 1761df828598SMugunthan V N void __iomem *regs = priv->regs; 1762df828598SMugunthan V N int slave_num = slave->slave_num; 1763df828598SMugunthan V N struct cpsw_slave_data *data = priv->data.slave_data + slave_num; 1764df828598SMugunthan V N 1765df828598SMugunthan V N slave->data = data; 1766549985eeSRichard Cochran slave->regs = regs + slave_reg_ofs; 1767549985eeSRichard Cochran slave->sliver = regs + sliver_reg_ofs; 1768d9ba8f9eSMugunthan V N slave->port_vlan = data->dual_emac_res_vlan; 1769df828598SMugunthan V N } 1770df828598SMugunthan V N 17712eb32b0aSMugunthan V N static int cpsw_probe_dt(struct cpsw_platform_data *data, 17722eb32b0aSMugunthan V N struct platform_device *pdev) 17732eb32b0aSMugunthan V N { 17742eb32b0aSMugunthan V N struct device_node *node = pdev->dev.of_node; 17752eb32b0aSMugunthan V N struct device_node *slave_node; 17762eb32b0aSMugunthan V N int i = 0, ret; 17772eb32b0aSMugunthan V N u32 prop; 17782eb32b0aSMugunthan V N 17792eb32b0aSMugunthan V N if (!node) 17802eb32b0aSMugunthan V N return -EINVAL; 17812eb32b0aSMugunthan V N 17822eb32b0aSMugunthan V N if (of_property_read_u32(node, "slaves", &prop)) { 17832eb32b0aSMugunthan V N pr_err("Missing slaves property in the DT.\n"); 17842eb32b0aSMugunthan V N return -EINVAL; 17852eb32b0aSMugunthan V N } 17862eb32b0aSMugunthan V N data->slaves = prop; 17872eb32b0aSMugunthan V N 1788e86ac13bSMugunthan V N if (of_property_read_u32(node, "active_slave", &prop)) { 1789e86ac13bSMugunthan V N pr_err("Missing active_slave property in the DT.\n"); 1790aa1a15e2SDaniel Mack return -EINVAL; 179178ca0b28SRichard Cochran } 1792e86ac13bSMugunthan V N data->active_slave = prop; 179378ca0b28SRichard Cochran 179400ab94eeSRichard Cochran if (of_property_read_u32(node, "cpts_clock_mult", &prop)) { 179500ab94eeSRichard Cochran pr_err("Missing cpts_clock_mult property in the DT.\n"); 1796aa1a15e2SDaniel Mack return -EINVAL; 179700ab94eeSRichard Cochran } 179800ab94eeSRichard Cochran data->cpts_clock_mult = prop; 179900ab94eeSRichard Cochran 180000ab94eeSRichard Cochran if (of_property_read_u32(node, "cpts_clock_shift", &prop)) { 180100ab94eeSRichard Cochran pr_err("Missing cpts_clock_shift property in the DT.\n"); 1802aa1a15e2SDaniel Mack return -EINVAL; 180300ab94eeSRichard Cochran } 180400ab94eeSRichard Cochran data->cpts_clock_shift = prop; 180500ab94eeSRichard Cochran 1806aa1a15e2SDaniel Mack data->slave_data = devm_kzalloc(&pdev->dev, data->slaves 1807aa1a15e2SDaniel Mack * sizeof(struct cpsw_slave_data), 1808b2adaca9SJoe Perches GFP_KERNEL); 1809b2adaca9SJoe Perches if (!data->slave_data) 1810aa1a15e2SDaniel Mack return -ENOMEM; 18112eb32b0aSMugunthan V N 18122eb32b0aSMugunthan V N if (of_property_read_u32(node, "cpdma_channels", &prop)) { 18132eb32b0aSMugunthan V N pr_err("Missing cpdma_channels property in the DT.\n"); 1814aa1a15e2SDaniel Mack return -EINVAL; 18152eb32b0aSMugunthan V N } 18162eb32b0aSMugunthan V N data->channels = prop; 18172eb32b0aSMugunthan V N 18182eb32b0aSMugunthan V N if (of_property_read_u32(node, "ale_entries", &prop)) { 18192eb32b0aSMugunthan V N pr_err("Missing ale_entries property in the DT.\n"); 1820aa1a15e2SDaniel Mack return -EINVAL; 18212eb32b0aSMugunthan V N } 18222eb32b0aSMugunthan V N data->ale_entries = prop; 18232eb32b0aSMugunthan V N 18242eb32b0aSMugunthan V N if (of_property_read_u32(node, "bd_ram_size", &prop)) { 18252eb32b0aSMugunthan V N pr_err("Missing bd_ram_size property in the DT.\n"); 1826aa1a15e2SDaniel Mack return -EINVAL; 18272eb32b0aSMugunthan V N } 18282eb32b0aSMugunthan V N data->bd_ram_size = prop; 18292eb32b0aSMugunthan V N 18302eb32b0aSMugunthan V N if (of_property_read_u32(node, "rx_descs", &prop)) { 18312eb32b0aSMugunthan V N pr_err("Missing rx_descs property in the DT.\n"); 1832aa1a15e2SDaniel Mack return -EINVAL; 18332eb32b0aSMugunthan V N } 18342eb32b0aSMugunthan V N data->rx_descs = prop; 18352eb32b0aSMugunthan V N 18362eb32b0aSMugunthan V N if (of_property_read_u32(node, "mac_control", &prop)) { 18372eb32b0aSMugunthan V N pr_err("Missing mac_control property in the DT.\n"); 1838aa1a15e2SDaniel Mack return -EINVAL; 18392eb32b0aSMugunthan V N } 18402eb32b0aSMugunthan V N data->mac_control = prop; 18412eb32b0aSMugunthan V N 1842281abd96SMarkus Pargmann if (of_property_read_bool(node, "dual_emac")) 1843281abd96SMarkus Pargmann data->dual_emac = 1; 1844d9ba8f9eSMugunthan V N 18451fb19aa7SVaibhav Hiremath /* 18461fb19aa7SVaibhav Hiremath * Populate all the child nodes here... 18471fb19aa7SVaibhav Hiremath */ 18481fb19aa7SVaibhav Hiremath ret = of_platform_populate(node, NULL, NULL, &pdev->dev); 18491fb19aa7SVaibhav Hiremath /* We do not want to force this, as in some cases may not have child */ 18501fb19aa7SVaibhav Hiremath if (ret) 18511fb19aa7SVaibhav Hiremath pr_warn("Doesn't have any child node\n"); 18521fb19aa7SVaibhav Hiremath 1853f468b10eSMarkus Pargmann for_each_child_of_node(node, slave_node) { 1854549985eeSRichard Cochran struct cpsw_slave_data *slave_data = data->slave_data + i; 1855549985eeSRichard Cochran const void *mac_addr = NULL; 1856549985eeSRichard Cochran u32 phyid; 1857549985eeSRichard Cochran int lenp; 1858549985eeSRichard Cochran const __be32 *parp; 1859549985eeSRichard Cochran struct device_node *mdio_node; 1860549985eeSRichard Cochran struct platform_device *mdio; 1861549985eeSRichard Cochran 1862f468b10eSMarkus Pargmann /* This is no slave child node, continue */ 1863f468b10eSMarkus Pargmann if (strcmp(slave_node->name, "slave")) 1864f468b10eSMarkus Pargmann continue; 1865f468b10eSMarkus Pargmann 1866549985eeSRichard Cochran parp = of_get_property(slave_node, "phy_id", &lenp); 1867ce16294fSLothar Waßmann if ((parp == NULL) || (lenp != (sizeof(void *) * 2))) { 1868549985eeSRichard Cochran pr_err("Missing slave[%d] phy_id property\n", i); 1869aa1a15e2SDaniel Mack return -EINVAL; 1870549985eeSRichard Cochran } 1871549985eeSRichard Cochran mdio_node = of_find_node_by_phandle(be32_to_cpup(parp)); 1872549985eeSRichard Cochran phyid = be32_to_cpup(parp+1); 1873549985eeSRichard Cochran mdio = of_find_device_by_node(mdio_node); 1874f8d56d8fSStefan Roese 1875f8d56d8fSStefan Roese if (strncmp(mdio->name, "gpio", 4) == 0) { 1876f8d56d8fSStefan Roese /* GPIO bitbang MDIO driver attached */ 1877f8d56d8fSStefan Roese struct mii_bus *bus = dev_get_drvdata(&mdio->dev); 1878f8d56d8fSStefan Roese 1879f8d56d8fSStefan Roese snprintf(slave_data->phy_id, sizeof(slave_data->phy_id), 1880f8d56d8fSStefan Roese PHY_ID_FMT, bus->id, phyid); 1881f8d56d8fSStefan Roese } else { 1882f8d56d8fSStefan Roese /* davinci MDIO driver attached */ 1883549985eeSRichard Cochran snprintf(slave_data->phy_id, sizeof(slave_data->phy_id), 1884549985eeSRichard Cochran PHY_ID_FMT, mdio->name, phyid); 1885f8d56d8fSStefan Roese } 1886549985eeSRichard Cochran 1887549985eeSRichard Cochran mac_addr = of_get_mac_address(slave_node); 1888549985eeSRichard Cochran if (mac_addr) 1889549985eeSRichard Cochran memcpy(slave_data->mac_addr, mac_addr, ETH_ALEN); 1890549985eeSRichard Cochran 1891c5ceea7aSMugunthan V N slave_data->phy_if = of_get_phy_mode(slave_node); 189289e10172SUwe Kleine-König if (slave_data->phy_if < 0) { 189389e10172SUwe Kleine-König pr_err("Missing or malformed slave[%d] phy-mode property\n", 189489e10172SUwe Kleine-König i); 189589e10172SUwe Kleine-König return slave_data->phy_if; 189689e10172SUwe Kleine-König } 1897c5ceea7aSMugunthan V N 1898d9ba8f9eSMugunthan V N if (data->dual_emac) { 189991c4166cSMugunthan V N if (of_property_read_u32(slave_node, "dual_emac_res_vlan", 1900d9ba8f9eSMugunthan V N &prop)) { 1901d9ba8f9eSMugunthan V N pr_err("Missing dual_emac_res_vlan in DT.\n"); 1902d9ba8f9eSMugunthan V N slave_data->dual_emac_res_vlan = i+1; 1903d9ba8f9eSMugunthan V N pr_err("Using %d as Reserved VLAN for %d slave\n", 1904d9ba8f9eSMugunthan V N slave_data->dual_emac_res_vlan, i); 1905d9ba8f9eSMugunthan V N } else { 1906d9ba8f9eSMugunthan V N slave_data->dual_emac_res_vlan = prop; 1907d9ba8f9eSMugunthan V N } 1908d9ba8f9eSMugunthan V N } 1909d9ba8f9eSMugunthan V N 1910549985eeSRichard Cochran i++; 19113a27bfacSMugunthan V N if (i == data->slaves) 19123a27bfacSMugunthan V N break; 1913549985eeSRichard Cochran } 1914549985eeSRichard Cochran 19152eb32b0aSMugunthan V N return 0; 19162eb32b0aSMugunthan V N } 19172eb32b0aSMugunthan V N 1918d9ba8f9eSMugunthan V N static int cpsw_probe_dual_emac(struct platform_device *pdev, 1919d9ba8f9eSMugunthan V N struct cpsw_priv *priv) 1920d9ba8f9eSMugunthan V N { 1921d9ba8f9eSMugunthan V N struct cpsw_platform_data *data = &priv->data; 1922d9ba8f9eSMugunthan V N struct net_device *ndev; 1923d9ba8f9eSMugunthan V N struct cpsw_priv *priv_sl2; 1924d9ba8f9eSMugunthan V N int ret = 0, i; 1925d9ba8f9eSMugunthan V N 1926d9ba8f9eSMugunthan V N ndev = alloc_etherdev(sizeof(struct cpsw_priv)); 1927d9ba8f9eSMugunthan V N if (!ndev) { 1928d9ba8f9eSMugunthan V N pr_err("cpsw: error allocating net_device\n"); 1929d9ba8f9eSMugunthan V N return -ENOMEM; 1930d9ba8f9eSMugunthan V N } 1931d9ba8f9eSMugunthan V N 1932d9ba8f9eSMugunthan V N priv_sl2 = netdev_priv(ndev); 1933d9ba8f9eSMugunthan V N spin_lock_init(&priv_sl2->lock); 1934d9ba8f9eSMugunthan V N priv_sl2->data = *data; 1935d9ba8f9eSMugunthan V N priv_sl2->pdev = pdev; 1936d9ba8f9eSMugunthan V N priv_sl2->ndev = ndev; 1937d9ba8f9eSMugunthan V N priv_sl2->dev = &ndev->dev; 1938d9ba8f9eSMugunthan V N priv_sl2->msg_enable = netif_msg_init(debug_level, CPSW_DEBUG); 1939d9ba8f9eSMugunthan V N priv_sl2->rx_packet_max = max(rx_packet_max, 128); 1940d9ba8f9eSMugunthan V N 1941d9ba8f9eSMugunthan V N if (is_valid_ether_addr(data->slave_data[1].mac_addr)) { 1942d9ba8f9eSMugunthan V N memcpy(priv_sl2->mac_addr, data->slave_data[1].mac_addr, 1943d9ba8f9eSMugunthan V N ETH_ALEN); 1944d9ba8f9eSMugunthan V N pr_info("cpsw: Detected MACID = %pM\n", priv_sl2->mac_addr); 1945d9ba8f9eSMugunthan V N } else { 1946d9ba8f9eSMugunthan V N random_ether_addr(priv_sl2->mac_addr); 1947d9ba8f9eSMugunthan V N pr_info("cpsw: Random MACID = %pM\n", priv_sl2->mac_addr); 1948d9ba8f9eSMugunthan V N } 1949d9ba8f9eSMugunthan V N memcpy(ndev->dev_addr, priv_sl2->mac_addr, ETH_ALEN); 1950d9ba8f9eSMugunthan V N 1951d9ba8f9eSMugunthan V N priv_sl2->slaves = priv->slaves; 1952d9ba8f9eSMugunthan V N priv_sl2->clk = priv->clk; 1953d9ba8f9eSMugunthan V N 1954ff5b8ef2SMugunthan V N priv_sl2->coal_intvl = 0; 1955ff5b8ef2SMugunthan V N priv_sl2->bus_freq_mhz = priv->bus_freq_mhz; 1956ff5b8ef2SMugunthan V N 1957d9ba8f9eSMugunthan V N priv_sl2->regs = priv->regs; 1958d9ba8f9eSMugunthan V N priv_sl2->host_port = priv->host_port; 1959d9ba8f9eSMugunthan V N priv_sl2->host_port_regs = priv->host_port_regs; 1960d9ba8f9eSMugunthan V N priv_sl2->wr_regs = priv->wr_regs; 1961d9718546SMugunthan V N priv_sl2->hw_stats = priv->hw_stats; 1962d9ba8f9eSMugunthan V N priv_sl2->dma = priv->dma; 1963d9ba8f9eSMugunthan V N priv_sl2->txch = priv->txch; 1964d9ba8f9eSMugunthan V N priv_sl2->rxch = priv->rxch; 1965d9ba8f9eSMugunthan V N priv_sl2->ale = priv->ale; 1966d9ba8f9eSMugunthan V N priv_sl2->emac_port = 1; 1967d9ba8f9eSMugunthan V N priv->slaves[1].ndev = ndev; 1968d9ba8f9eSMugunthan V N priv_sl2->cpts = priv->cpts; 1969d9ba8f9eSMugunthan V N priv_sl2->version = priv->version; 1970d9ba8f9eSMugunthan V N 1971d9ba8f9eSMugunthan V N for (i = 0; i < priv->num_irqs; i++) { 1972d9ba8f9eSMugunthan V N priv_sl2->irqs_table[i] = priv->irqs_table[i]; 1973d9ba8f9eSMugunthan V N priv_sl2->num_irqs = priv->num_irqs; 1974d9ba8f9eSMugunthan V N } 1975f646968fSPatrick McHardy ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER; 1976d9ba8f9eSMugunthan V N 1977d9ba8f9eSMugunthan V N ndev->netdev_ops = &cpsw_netdev_ops; 1978d9ba8f9eSMugunthan V N SET_ETHTOOL_OPS(ndev, &cpsw_ethtool_ops); 1979d9ba8f9eSMugunthan V N netif_napi_add(ndev, &priv_sl2->napi, cpsw_poll, CPSW_POLL_WEIGHT); 1980d9ba8f9eSMugunthan V N 1981d9ba8f9eSMugunthan V N /* register the network device */ 1982d9ba8f9eSMugunthan V N SET_NETDEV_DEV(ndev, &pdev->dev); 1983d9ba8f9eSMugunthan V N ret = register_netdev(ndev); 1984d9ba8f9eSMugunthan V N if (ret) { 1985d9ba8f9eSMugunthan V N pr_err("cpsw: error registering net device\n"); 1986d9ba8f9eSMugunthan V N free_netdev(ndev); 1987d9ba8f9eSMugunthan V N ret = -ENODEV; 1988d9ba8f9eSMugunthan V N } 1989d9ba8f9eSMugunthan V N 1990d9ba8f9eSMugunthan V N return ret; 1991d9ba8f9eSMugunthan V N } 1992d9ba8f9eSMugunthan V N 1993663e12e6SBill Pemberton static int cpsw_probe(struct platform_device *pdev) 1994df828598SMugunthan V N { 1995d1bd9acfSSebastian Siewior struct cpsw_platform_data *data; 1996df828598SMugunthan V N struct net_device *ndev; 1997df828598SMugunthan V N struct cpsw_priv *priv; 1998df828598SMugunthan V N struct cpdma_params dma_params; 1999df828598SMugunthan V N struct cpsw_ale_params ale_params; 2000aa1a15e2SDaniel Mack void __iomem *ss_regs; 2001aa1a15e2SDaniel Mack struct resource *res, *ss_res; 2002549985eeSRichard Cochran u32 slave_offset, sliver_offset, slave_size; 2003df828598SMugunthan V N int ret = 0, i, k = 0; 2004df828598SMugunthan V N 2005df828598SMugunthan V N ndev = alloc_etherdev(sizeof(struct cpsw_priv)); 2006df828598SMugunthan V N if (!ndev) { 2007df828598SMugunthan V N pr_err("error allocating net_device\n"); 2008df828598SMugunthan V N return -ENOMEM; 2009df828598SMugunthan V N } 2010df828598SMugunthan V N 2011df828598SMugunthan V N platform_set_drvdata(pdev, ndev); 2012df828598SMugunthan V N priv = netdev_priv(ndev); 2013df828598SMugunthan V N spin_lock_init(&priv->lock); 2014df828598SMugunthan V N priv->pdev = pdev; 2015df828598SMugunthan V N priv->ndev = ndev; 2016df828598SMugunthan V N priv->dev = &ndev->dev; 2017df828598SMugunthan V N priv->msg_enable = netif_msg_init(debug_level, CPSW_DEBUG); 2018df828598SMugunthan V N priv->rx_packet_max = max(rx_packet_max, 128); 20199232b16dSMugunthan V N priv->cpts = devm_kzalloc(&pdev->dev, sizeof(struct cpts), GFP_KERNEL); 20207dcf313aSMugunthan V N priv->irq_enabled = true; 2021ab8e99d2SSebastian Siewior if (!priv->cpts) { 20229232b16dSMugunthan V N pr_err("error allocating cpts\n"); 20239232b16dSMugunthan V N goto clean_ndev_ret; 20249232b16dSMugunthan V N } 2025df828598SMugunthan V N 20261fb19aa7SVaibhav Hiremath /* 20271fb19aa7SVaibhav Hiremath * This may be required here for child devices. 20281fb19aa7SVaibhav Hiremath */ 20291fb19aa7SVaibhav Hiremath pm_runtime_enable(&pdev->dev); 20301fb19aa7SVaibhav Hiremath 2031739683b4SMugunthan V N /* Select default pin state */ 2032739683b4SMugunthan V N pinctrl_pm_select_default_state(&pdev->dev); 2033739683b4SMugunthan V N 20342eb32b0aSMugunthan V N if (cpsw_probe_dt(&priv->data, pdev)) { 20352eb32b0aSMugunthan V N pr_err("cpsw: platform data missing\n"); 20362eb32b0aSMugunthan V N ret = -ENODEV; 2037aa1a15e2SDaniel Mack goto clean_runtime_disable_ret; 20382eb32b0aSMugunthan V N } 20392eb32b0aSMugunthan V N data = &priv->data; 20402eb32b0aSMugunthan V N 2041df828598SMugunthan V N if (is_valid_ether_addr(data->slave_data[0].mac_addr)) { 2042df828598SMugunthan V N memcpy(priv->mac_addr, data->slave_data[0].mac_addr, ETH_ALEN); 2043cf6122beSDaniel Mack pr_info("Detected MACID = %pM\n", priv->mac_addr); 2044df828598SMugunthan V N } else { 20457efd26d0SJoe Perches eth_random_addr(priv->mac_addr); 2046cf6122beSDaniel Mack pr_info("Random MACID = %pM\n", priv->mac_addr); 2047df828598SMugunthan V N } 2048df828598SMugunthan V N 2049df828598SMugunthan V N memcpy(ndev->dev_addr, priv->mac_addr, ETH_ALEN); 2050df828598SMugunthan V N 2051aa1a15e2SDaniel Mack priv->slaves = devm_kzalloc(&pdev->dev, 2052aa1a15e2SDaniel Mack sizeof(struct cpsw_slave) * data->slaves, 2053df828598SMugunthan V N GFP_KERNEL); 2054df828598SMugunthan V N if (!priv->slaves) { 2055aa1a15e2SDaniel Mack ret = -ENOMEM; 2056aa1a15e2SDaniel Mack goto clean_runtime_disable_ret; 2057df828598SMugunthan V N } 2058df828598SMugunthan V N for (i = 0; i < data->slaves; i++) 2059df828598SMugunthan V N priv->slaves[i].slave_num = i; 2060df828598SMugunthan V N 2061d9ba8f9eSMugunthan V N priv->slaves[0].ndev = ndev; 2062d9ba8f9eSMugunthan V N priv->emac_port = 0; 2063d9ba8f9eSMugunthan V N 2064aa1a15e2SDaniel Mack priv->clk = devm_clk_get(&pdev->dev, "fck"); 2065df828598SMugunthan V N if (IS_ERR(priv->clk)) { 2066aa1a15e2SDaniel Mack dev_err(priv->dev, "fck is not found\n"); 2067f150bd7fSMugunthan V N ret = -ENODEV; 2068aa1a15e2SDaniel Mack goto clean_runtime_disable_ret; 2069df828598SMugunthan V N } 2070ff5b8ef2SMugunthan V N priv->coal_intvl = 0; 2071ff5b8ef2SMugunthan V N priv->bus_freq_mhz = clk_get_rate(priv->clk) / 1000000; 2072df828598SMugunthan V N 2073aa1a15e2SDaniel Mack ss_res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2074aa1a15e2SDaniel Mack ss_regs = devm_ioremap_resource(&pdev->dev, ss_res); 2075aa1a15e2SDaniel Mack if (IS_ERR(ss_regs)) { 2076aa1a15e2SDaniel Mack ret = PTR_ERR(ss_regs); 2077aa1a15e2SDaniel Mack goto clean_runtime_disable_ret; 2078df828598SMugunthan V N } 2079549985eeSRichard Cochran priv->regs = ss_regs; 2080549985eeSRichard Cochran priv->host_port = HOST_PORT_NUM; 2081df828598SMugunthan V N 2082f280e89aSMugunthan V N /* Need to enable clocks with runtime PM api to access module 2083f280e89aSMugunthan V N * registers 2084f280e89aSMugunthan V N */ 2085f280e89aSMugunthan V N pm_runtime_get_sync(&pdev->dev); 2086f280e89aSMugunthan V N priv->version = readl(&priv->regs->id_ver); 2087f280e89aSMugunthan V N pm_runtime_put_sync(&pdev->dev); 2088f280e89aSMugunthan V N 2089aa1a15e2SDaniel Mack res = platform_get_resource(pdev, IORESOURCE_MEM, 1); 2090aa1a15e2SDaniel Mack priv->wr_regs = devm_ioremap_resource(&pdev->dev, res); 2091aa1a15e2SDaniel Mack if (IS_ERR(priv->wr_regs)) { 2092aa1a15e2SDaniel Mack ret = PTR_ERR(priv->wr_regs); 2093aa1a15e2SDaniel Mack goto clean_runtime_disable_ret; 2094df828598SMugunthan V N } 2095df828598SMugunthan V N 2096df828598SMugunthan V N memset(&dma_params, 0, sizeof(dma_params)); 2097549985eeSRichard Cochran memset(&ale_params, 0, sizeof(ale_params)); 2098549985eeSRichard Cochran 2099549985eeSRichard Cochran switch (priv->version) { 2100549985eeSRichard Cochran case CPSW_VERSION_1: 2101549985eeSRichard Cochran priv->host_port_regs = ss_regs + CPSW1_HOST_PORT_OFFSET; 21029232b16dSMugunthan V N priv->cpts->reg = ss_regs + CPSW1_CPTS_OFFSET; 2103d9718546SMugunthan V N priv->hw_stats = ss_regs + CPSW1_HW_STATS; 2104549985eeSRichard Cochran dma_params.dmaregs = ss_regs + CPSW1_CPDMA_OFFSET; 2105549985eeSRichard Cochran dma_params.txhdp = ss_regs + CPSW1_STATERAM_OFFSET; 2106549985eeSRichard Cochran ale_params.ale_regs = ss_regs + CPSW1_ALE_OFFSET; 2107549985eeSRichard Cochran slave_offset = CPSW1_SLAVE_OFFSET; 2108549985eeSRichard Cochran slave_size = CPSW1_SLAVE_SIZE; 2109549985eeSRichard Cochran sliver_offset = CPSW1_SLIVER_OFFSET; 2110549985eeSRichard Cochran dma_params.desc_mem_phys = 0; 2111549985eeSRichard Cochran break; 2112549985eeSRichard Cochran case CPSW_VERSION_2: 2113c193f365SMugunthan V N case CPSW_VERSION_3: 2114926489beSMugunthan V N case CPSW_VERSION_4: 2115549985eeSRichard Cochran priv->host_port_regs = ss_regs + CPSW2_HOST_PORT_OFFSET; 21169232b16dSMugunthan V N priv->cpts->reg = ss_regs + CPSW2_CPTS_OFFSET; 2117d9718546SMugunthan V N priv->hw_stats = ss_regs + CPSW2_HW_STATS; 2118549985eeSRichard Cochran dma_params.dmaregs = ss_regs + CPSW2_CPDMA_OFFSET; 2119549985eeSRichard Cochran dma_params.txhdp = ss_regs + CPSW2_STATERAM_OFFSET; 2120549985eeSRichard Cochran ale_params.ale_regs = ss_regs + CPSW2_ALE_OFFSET; 2121549985eeSRichard Cochran slave_offset = CPSW2_SLAVE_OFFSET; 2122549985eeSRichard Cochran slave_size = CPSW2_SLAVE_SIZE; 2123549985eeSRichard Cochran sliver_offset = CPSW2_SLIVER_OFFSET; 2124549985eeSRichard Cochran dma_params.desc_mem_phys = 2125aa1a15e2SDaniel Mack (u32 __force) ss_res->start + CPSW2_BD_OFFSET; 2126549985eeSRichard Cochran break; 2127549985eeSRichard Cochran default: 2128549985eeSRichard Cochran dev_err(priv->dev, "unknown version 0x%08x\n", priv->version); 2129549985eeSRichard Cochran ret = -ENODEV; 2130aa1a15e2SDaniel Mack goto clean_runtime_disable_ret; 2131549985eeSRichard Cochran } 2132549985eeSRichard Cochran for (i = 0; i < priv->data.slaves; i++) { 2133549985eeSRichard Cochran struct cpsw_slave *slave = &priv->slaves[i]; 2134549985eeSRichard Cochran cpsw_slave_init(slave, priv, slave_offset, sliver_offset); 2135549985eeSRichard Cochran slave_offset += slave_size; 2136549985eeSRichard Cochran sliver_offset += SLIVER_SIZE; 2137549985eeSRichard Cochran } 2138549985eeSRichard Cochran 2139df828598SMugunthan V N dma_params.dev = &pdev->dev; 2140549985eeSRichard Cochran dma_params.rxthresh = dma_params.dmaregs + CPDMA_RXTHRESH; 2141549985eeSRichard Cochran dma_params.rxfree = dma_params.dmaregs + CPDMA_RXFREE; 2142549985eeSRichard Cochran dma_params.rxhdp = dma_params.txhdp + CPDMA_RXHDP; 2143549985eeSRichard Cochran dma_params.txcp = dma_params.txhdp + CPDMA_TXCP; 2144549985eeSRichard Cochran dma_params.rxcp = dma_params.txhdp + CPDMA_RXCP; 2145df828598SMugunthan V N 2146df828598SMugunthan V N dma_params.num_chan = data->channels; 2147df828598SMugunthan V N dma_params.has_soft_reset = true; 2148df828598SMugunthan V N dma_params.min_packet_size = CPSW_MIN_PACKET_SIZE; 2149df828598SMugunthan V N dma_params.desc_mem_size = data->bd_ram_size; 2150df828598SMugunthan V N dma_params.desc_align = 16; 2151df828598SMugunthan V N dma_params.has_ext_regs = true; 2152549985eeSRichard Cochran dma_params.desc_hw_addr = dma_params.desc_mem_phys; 2153df828598SMugunthan V N 2154df828598SMugunthan V N priv->dma = cpdma_ctlr_create(&dma_params); 2155df828598SMugunthan V N if (!priv->dma) { 2156df828598SMugunthan V N dev_err(priv->dev, "error initializing dma\n"); 2157df828598SMugunthan V N ret = -ENOMEM; 2158aa1a15e2SDaniel Mack goto clean_runtime_disable_ret; 2159df828598SMugunthan V N } 2160df828598SMugunthan V N 2161df828598SMugunthan V N priv->txch = cpdma_chan_create(priv->dma, tx_chan_num(0), 2162df828598SMugunthan V N cpsw_tx_handler); 2163df828598SMugunthan V N priv->rxch = cpdma_chan_create(priv->dma, rx_chan_num(0), 2164df828598SMugunthan V N cpsw_rx_handler); 2165df828598SMugunthan V N 2166df828598SMugunthan V N if (WARN_ON(!priv->txch || !priv->rxch)) { 2167df828598SMugunthan V N dev_err(priv->dev, "error initializing dma channels\n"); 2168df828598SMugunthan V N ret = -ENOMEM; 2169df828598SMugunthan V N goto clean_dma_ret; 2170df828598SMugunthan V N } 2171df828598SMugunthan V N 2172df828598SMugunthan V N ale_params.dev = &ndev->dev; 2173df828598SMugunthan V N ale_params.ale_ageout = ale_ageout; 2174df828598SMugunthan V N ale_params.ale_entries = data->ale_entries; 2175df828598SMugunthan V N ale_params.ale_ports = data->slaves; 2176df828598SMugunthan V N 2177df828598SMugunthan V N priv->ale = cpsw_ale_create(&ale_params); 2178df828598SMugunthan V N if (!priv->ale) { 2179df828598SMugunthan V N dev_err(priv->dev, "error initializing ale engine\n"); 2180df828598SMugunthan V N ret = -ENODEV; 2181df828598SMugunthan V N goto clean_dma_ret; 2182df828598SMugunthan V N } 2183df828598SMugunthan V N 2184df828598SMugunthan V N ndev->irq = platform_get_irq(pdev, 0); 2185df828598SMugunthan V N if (ndev->irq < 0) { 2186df828598SMugunthan V N dev_err(priv->dev, "error getting irq resource\n"); 2187df828598SMugunthan V N ret = -ENOENT; 2188df828598SMugunthan V N goto clean_ale_ret; 2189df828598SMugunthan V N } 2190df828598SMugunthan V N 2191df828598SMugunthan V N while ((res = platform_get_resource(priv->pdev, IORESOURCE_IRQ, k))) { 2192df828598SMugunthan V N for (i = res->start; i <= res->end; i++) { 2193aa1a15e2SDaniel Mack if (devm_request_irq(&pdev->dev, i, cpsw_interrupt, 0, 2194db850559SMugunthan V N dev_name(&pdev->dev), priv)) { 2195df828598SMugunthan V N dev_err(priv->dev, "error attaching irq\n"); 2196df828598SMugunthan V N goto clean_ale_ret; 2197df828598SMugunthan V N } 2198df828598SMugunthan V N priv->irqs_table[k] = i; 2199d1bd9acfSSebastian Siewior priv->num_irqs = k + 1; 2200df828598SMugunthan V N } 2201df828598SMugunthan V N k++; 2202df828598SMugunthan V N } 2203df828598SMugunthan V N 2204f646968fSPatrick McHardy ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER; 2205df828598SMugunthan V N 2206df828598SMugunthan V N ndev->netdev_ops = &cpsw_netdev_ops; 2207df828598SMugunthan V N SET_ETHTOOL_OPS(ndev, &cpsw_ethtool_ops); 2208df828598SMugunthan V N netif_napi_add(ndev, &priv->napi, cpsw_poll, CPSW_POLL_WEIGHT); 2209df828598SMugunthan V N 2210df828598SMugunthan V N /* register the network device */ 2211df828598SMugunthan V N SET_NETDEV_DEV(ndev, &pdev->dev); 2212df828598SMugunthan V N ret = register_netdev(ndev); 2213df828598SMugunthan V N if (ret) { 2214df828598SMugunthan V N dev_err(priv->dev, "error registering net device\n"); 2215df828598SMugunthan V N ret = -ENODEV; 2216aa1a15e2SDaniel Mack goto clean_ale_ret; 2217df828598SMugunthan V N } 2218df828598SMugunthan V N 22191a3b5056SOlof Johansson cpsw_notice(priv, probe, "initialized device (regs %pa, irq %d)\n", 22201a3b5056SOlof Johansson &ss_res->start, ndev->irq); 2221df828598SMugunthan V N 2222d9ba8f9eSMugunthan V N if (priv->data.dual_emac) { 2223d9ba8f9eSMugunthan V N ret = cpsw_probe_dual_emac(pdev, priv); 2224d9ba8f9eSMugunthan V N if (ret) { 2225d9ba8f9eSMugunthan V N cpsw_err(priv, probe, "error probe slave 2 emac interface\n"); 2226aa1a15e2SDaniel Mack goto clean_ale_ret; 2227d9ba8f9eSMugunthan V N } 2228d9ba8f9eSMugunthan V N } 2229d9ba8f9eSMugunthan V N 2230df828598SMugunthan V N return 0; 2231df828598SMugunthan V N 2232df828598SMugunthan V N clean_ale_ret: 2233df828598SMugunthan V N cpsw_ale_destroy(priv->ale); 2234df828598SMugunthan V N clean_dma_ret: 2235df828598SMugunthan V N cpdma_chan_destroy(priv->txch); 2236df828598SMugunthan V N cpdma_chan_destroy(priv->rxch); 2237df828598SMugunthan V N cpdma_ctlr_destroy(priv->dma); 2238aa1a15e2SDaniel Mack clean_runtime_disable_ret: 2239f150bd7fSMugunthan V N pm_runtime_disable(&pdev->dev); 2240df828598SMugunthan V N clean_ndev_ret: 2241d1bd9acfSSebastian Siewior free_netdev(priv->ndev); 2242df828598SMugunthan V N return ret; 2243df828598SMugunthan V N } 2244df828598SMugunthan V N 2245663e12e6SBill Pemberton static int cpsw_remove(struct platform_device *pdev) 2246df828598SMugunthan V N { 2247df828598SMugunthan V N struct net_device *ndev = platform_get_drvdata(pdev); 2248df828598SMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 2249df828598SMugunthan V N 2250d1bd9acfSSebastian Siewior if (priv->data.dual_emac) 2251d1bd9acfSSebastian Siewior unregister_netdev(cpsw_get_slave_ndev(priv, 1)); 2252d1bd9acfSSebastian Siewior unregister_netdev(ndev); 2253df828598SMugunthan V N 2254df828598SMugunthan V N cpsw_ale_destroy(priv->ale); 2255df828598SMugunthan V N cpdma_chan_destroy(priv->txch); 2256df828598SMugunthan V N cpdma_chan_destroy(priv->rxch); 2257df828598SMugunthan V N cpdma_ctlr_destroy(priv->dma); 2258f150bd7fSMugunthan V N pm_runtime_disable(&pdev->dev); 2259d1bd9acfSSebastian Siewior if (priv->data.dual_emac) 2260d1bd9acfSSebastian Siewior free_netdev(cpsw_get_slave_ndev(priv, 1)); 2261df828598SMugunthan V N free_netdev(ndev); 2262df828598SMugunthan V N return 0; 2263df828598SMugunthan V N } 2264df828598SMugunthan V N 2265df828598SMugunthan V N static int cpsw_suspend(struct device *dev) 2266df828598SMugunthan V N { 2267df828598SMugunthan V N struct platform_device *pdev = to_platform_device(dev); 2268df828598SMugunthan V N struct net_device *ndev = platform_get_drvdata(pdev); 2269b90fc27aSMugunthan V N struct cpsw_priv *priv = netdev_priv(ndev); 2270df828598SMugunthan V N 2271df828598SMugunthan V N if (netif_running(ndev)) 2272df828598SMugunthan V N cpsw_ndo_stop(ndev); 22731e7a2e21SDaniel Mack 22741e7a2e21SDaniel Mack for_each_slave(priv, soft_reset_slave); 22751e7a2e21SDaniel Mack 2276f150bd7fSMugunthan V N pm_runtime_put_sync(&pdev->dev); 2277f150bd7fSMugunthan V N 2278739683b4SMugunthan V N /* Select sleep pin state */ 2279739683b4SMugunthan V N pinctrl_pm_select_sleep_state(&pdev->dev); 2280739683b4SMugunthan V N 2281df828598SMugunthan V N return 0; 2282df828598SMugunthan V N } 2283df828598SMugunthan V N 2284df828598SMugunthan V N static int cpsw_resume(struct device *dev) 2285df828598SMugunthan V N { 2286df828598SMugunthan V N struct platform_device *pdev = to_platform_device(dev); 2287df828598SMugunthan V N struct net_device *ndev = platform_get_drvdata(pdev); 2288df828598SMugunthan V N 2289f150bd7fSMugunthan V N pm_runtime_get_sync(&pdev->dev); 2290739683b4SMugunthan V N 2291739683b4SMugunthan V N /* Select default pin state */ 2292739683b4SMugunthan V N pinctrl_pm_select_default_state(&pdev->dev); 2293739683b4SMugunthan V N 2294df828598SMugunthan V N if (netif_running(ndev)) 2295df828598SMugunthan V N cpsw_ndo_open(ndev); 2296df828598SMugunthan V N return 0; 2297df828598SMugunthan V N } 2298df828598SMugunthan V N 2299df828598SMugunthan V N static const struct dev_pm_ops cpsw_pm_ops = { 2300df828598SMugunthan V N .suspend = cpsw_suspend, 2301df828598SMugunthan V N .resume = cpsw_resume, 2302df828598SMugunthan V N }; 2303df828598SMugunthan V N 23042eb32b0aSMugunthan V N static const struct of_device_id cpsw_of_mtable[] = { 23052eb32b0aSMugunthan V N { .compatible = "ti,cpsw", }, 23062eb32b0aSMugunthan V N { /* sentinel */ }, 23072eb32b0aSMugunthan V N }; 23084bc21d41SSebastian Siewior MODULE_DEVICE_TABLE(of, cpsw_of_mtable); 23092eb32b0aSMugunthan V N 2310df828598SMugunthan V N static struct platform_driver cpsw_driver = { 2311df828598SMugunthan V N .driver = { 2312df828598SMugunthan V N .name = "cpsw", 2313df828598SMugunthan V N .owner = THIS_MODULE, 2314df828598SMugunthan V N .pm = &cpsw_pm_ops, 23151e5c76d4SSachin Kamat .of_match_table = cpsw_of_mtable, 2316df828598SMugunthan V N }, 2317df828598SMugunthan V N .probe = cpsw_probe, 2318663e12e6SBill Pemberton .remove = cpsw_remove, 2319df828598SMugunthan V N }; 2320df828598SMugunthan V N 2321df828598SMugunthan V N static int __init cpsw_init(void) 2322df828598SMugunthan V N { 2323df828598SMugunthan V N return platform_driver_register(&cpsw_driver); 2324df828598SMugunthan V N } 2325df828598SMugunthan V N late_initcall(cpsw_init); 2326df828598SMugunthan V N 2327df828598SMugunthan V N static void __exit cpsw_exit(void) 2328df828598SMugunthan V N { 2329df828598SMugunthan V N platform_driver_unregister(&cpsw_driver); 2330df828598SMugunthan V N } 2331df828598SMugunthan V N module_exit(cpsw_exit); 2332df828598SMugunthan V N 2333df828598SMugunthan V N MODULE_LICENSE("GPL"); 2334df828598SMugunthan V N MODULE_AUTHOR("Cyril Chemparathy <cyril@ti.com>"); 2335df828598SMugunthan V N MODULE_AUTHOR("Mugunthan V N <mugunthanvnm@ti.com>"); 2336df828598SMugunthan V N MODULE_DESCRIPTION("TI CPSW Ethernet driver"); 2337