1 /* 2 * Copyright (C) 2006, 2007 Eugene Konev 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License as published by 6 * the Free Software Foundation; either version 2 of the License, or 7 * (at your option) any later version. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program; if not, write to the Free Software 16 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA 17 */ 18 19 #include <linux/module.h> 20 #include <linux/interrupt.h> 21 #include <linux/moduleparam.h> 22 23 #include <linux/sched.h> 24 #include <linux/kernel.h> 25 #include <linux/slab.h> 26 #include <linux/errno.h> 27 #include <linux/types.h> 28 #include <linux/delay.h> 29 30 #include <linux/netdevice.h> 31 #include <linux/if_vlan.h> 32 #include <linux/etherdevice.h> 33 #include <linux/ethtool.h> 34 #include <linux/skbuff.h> 35 #include <linux/mii.h> 36 #include <linux/phy.h> 37 #include <linux/phy_fixed.h> 38 #include <linux/platform_device.h> 39 #include <linux/dma-mapping.h> 40 #include <linux/clk.h> 41 #include <linux/gpio.h> 42 #include <linux/atomic.h> 43 44 #include <asm/mach-ar7/ar7.h> 45 46 MODULE_AUTHOR("Eugene Konev <ejka@imfi.kspu.ru>"); 47 MODULE_DESCRIPTION("TI AR7 ethernet driver (CPMAC)"); 48 MODULE_LICENSE("GPL"); 49 MODULE_ALIAS("platform:cpmac"); 50 51 static int debug_level = 8; 52 static int dumb_switch; 53 54 /* Next 2 are only used in cpmac_probe, so it's pointless to change them */ 55 module_param(debug_level, int, 0444); 56 module_param(dumb_switch, int, 0444); 57 58 MODULE_PARM_DESC(debug_level, "Number of NETIF_MSG bits to enable"); 59 MODULE_PARM_DESC(dumb_switch, "Assume switch is not connected to MDIO bus"); 60 61 #define CPMAC_VERSION "0.5.2" 62 /* frame size + 802.1q tag + FCS size */ 63 #define CPMAC_SKB_SIZE (ETH_FRAME_LEN + ETH_FCS_LEN + VLAN_HLEN) 64 #define CPMAC_QUEUES 8 65 66 /* Ethernet registers */ 67 #define CPMAC_TX_CONTROL 0x0004 68 #define CPMAC_TX_TEARDOWN 0x0008 69 #define CPMAC_RX_CONTROL 0x0014 70 #define CPMAC_RX_TEARDOWN 0x0018 71 #define CPMAC_MBP 0x0100 72 #define MBP_RXPASSCRC 0x40000000 73 #define MBP_RXQOS 0x20000000 74 #define MBP_RXNOCHAIN 0x10000000 75 #define MBP_RXCMF 0x01000000 76 #define MBP_RXSHORT 0x00800000 77 #define MBP_RXCEF 0x00400000 78 #define MBP_RXPROMISC 0x00200000 79 #define MBP_PROMISCCHAN(channel) (((channel) & 0x7) << 16) 80 #define MBP_RXBCAST 0x00002000 81 #define MBP_BCASTCHAN(channel) (((channel) & 0x7) << 8) 82 #define MBP_RXMCAST 0x00000020 83 #define MBP_MCASTCHAN(channel) ((channel) & 0x7) 84 #define CPMAC_UNICAST_ENABLE 0x0104 85 #define CPMAC_UNICAST_CLEAR 0x0108 86 #define CPMAC_MAX_LENGTH 0x010c 87 #define CPMAC_BUFFER_OFFSET 0x0110 88 #define CPMAC_MAC_CONTROL 0x0160 89 #define MAC_TXPTYPE 0x00000200 90 #define MAC_TXPACE 0x00000040 91 #define MAC_MII 0x00000020 92 #define MAC_TXFLOW 0x00000010 93 #define MAC_RXFLOW 0x00000008 94 #define MAC_MTEST 0x00000004 95 #define MAC_LOOPBACK 0x00000002 96 #define MAC_FDX 0x00000001 97 #define CPMAC_MAC_STATUS 0x0164 98 #define MAC_STATUS_QOS 0x00000004 99 #define MAC_STATUS_RXFLOW 0x00000002 100 #define MAC_STATUS_TXFLOW 0x00000001 101 #define CPMAC_TX_INT_ENABLE 0x0178 102 #define CPMAC_TX_INT_CLEAR 0x017c 103 #define CPMAC_MAC_INT_VECTOR 0x0180 104 #define MAC_INT_STATUS 0x00080000 105 #define MAC_INT_HOST 0x00040000 106 #define MAC_INT_RX 0x00020000 107 #define MAC_INT_TX 0x00010000 108 #define CPMAC_MAC_EOI_VECTOR 0x0184 109 #define CPMAC_RX_INT_ENABLE 0x0198 110 #define CPMAC_RX_INT_CLEAR 0x019c 111 #define CPMAC_MAC_INT_ENABLE 0x01a8 112 #define CPMAC_MAC_INT_CLEAR 0x01ac 113 #define CPMAC_MAC_ADDR_LO(channel) (0x01b0 + (channel) * 4) 114 #define CPMAC_MAC_ADDR_MID 0x01d0 115 #define CPMAC_MAC_ADDR_HI 0x01d4 116 #define CPMAC_MAC_HASH_LO 0x01d8 117 #define CPMAC_MAC_HASH_HI 0x01dc 118 #define CPMAC_TX_PTR(channel) (0x0600 + (channel) * 4) 119 #define CPMAC_RX_PTR(channel) (0x0620 + (channel) * 4) 120 #define CPMAC_TX_ACK(channel) (0x0640 + (channel) * 4) 121 #define CPMAC_RX_ACK(channel) (0x0660 + (channel) * 4) 122 #define CPMAC_REG_END 0x0680 123 124 /* Rx/Tx statistics 125 * TODO: use some of them to fill stats in cpmac_stats() 126 */ 127 #define CPMAC_STATS_RX_GOOD 0x0200 128 #define CPMAC_STATS_RX_BCAST 0x0204 129 #define CPMAC_STATS_RX_MCAST 0x0208 130 #define CPMAC_STATS_RX_PAUSE 0x020c 131 #define CPMAC_STATS_RX_CRC 0x0210 132 #define CPMAC_STATS_RX_ALIGN 0x0214 133 #define CPMAC_STATS_RX_OVER 0x0218 134 #define CPMAC_STATS_RX_JABBER 0x021c 135 #define CPMAC_STATS_RX_UNDER 0x0220 136 #define CPMAC_STATS_RX_FRAG 0x0224 137 #define CPMAC_STATS_RX_FILTER 0x0228 138 #define CPMAC_STATS_RX_QOSFILTER 0x022c 139 #define CPMAC_STATS_RX_OCTETS 0x0230 140 141 #define CPMAC_STATS_TX_GOOD 0x0234 142 #define CPMAC_STATS_TX_BCAST 0x0238 143 #define CPMAC_STATS_TX_MCAST 0x023c 144 #define CPMAC_STATS_TX_PAUSE 0x0240 145 #define CPMAC_STATS_TX_DEFER 0x0244 146 #define CPMAC_STATS_TX_COLLISION 0x0248 147 #define CPMAC_STATS_TX_SINGLECOLL 0x024c 148 #define CPMAC_STATS_TX_MULTICOLL 0x0250 149 #define CPMAC_STATS_TX_EXCESSCOLL 0x0254 150 #define CPMAC_STATS_TX_LATECOLL 0x0258 151 #define CPMAC_STATS_TX_UNDERRUN 0x025c 152 #define CPMAC_STATS_TX_CARRIERSENSE 0x0260 153 #define CPMAC_STATS_TX_OCTETS 0x0264 154 155 #define cpmac_read(base, reg) (readl((void __iomem *)(base) + (reg))) 156 #define cpmac_write(base, reg, val) (writel(val, (void __iomem *)(base) + \ 157 (reg))) 158 159 /* MDIO bus */ 160 #define CPMAC_MDIO_VERSION 0x0000 161 #define CPMAC_MDIO_CONTROL 0x0004 162 #define MDIOC_IDLE 0x80000000 163 #define MDIOC_ENABLE 0x40000000 164 #define MDIOC_PREAMBLE 0x00100000 165 #define MDIOC_FAULT 0x00080000 166 #define MDIOC_FAULTDETECT 0x00040000 167 #define MDIOC_INTTEST 0x00020000 168 #define MDIOC_CLKDIV(div) ((div) & 0xff) 169 #define CPMAC_MDIO_ALIVE 0x0008 170 #define CPMAC_MDIO_LINK 0x000c 171 #define CPMAC_MDIO_ACCESS(channel) (0x0080 + (channel) * 8) 172 #define MDIO_BUSY 0x80000000 173 #define MDIO_WRITE 0x40000000 174 #define MDIO_REG(reg) (((reg) & 0x1f) << 21) 175 #define MDIO_PHY(phy) (((phy) & 0x1f) << 16) 176 #define MDIO_DATA(data) ((data) & 0xffff) 177 #define CPMAC_MDIO_PHYSEL(channel) (0x0084 + (channel) * 8) 178 #define PHYSEL_LINKSEL 0x00000040 179 #define PHYSEL_LINKINT 0x00000020 180 181 struct cpmac_desc { 182 u32 hw_next; 183 u32 hw_data; 184 u16 buflen; 185 u16 bufflags; 186 u16 datalen; 187 u16 dataflags; 188 #define CPMAC_SOP 0x8000 189 #define CPMAC_EOP 0x4000 190 #define CPMAC_OWN 0x2000 191 #define CPMAC_EOQ 0x1000 192 struct sk_buff *skb; 193 struct cpmac_desc *next; 194 struct cpmac_desc *prev; 195 dma_addr_t mapping; 196 dma_addr_t data_mapping; 197 }; 198 199 struct cpmac_priv { 200 spinlock_t lock; 201 spinlock_t rx_lock; 202 struct cpmac_desc *rx_head; 203 int ring_size; 204 struct cpmac_desc *desc_ring; 205 dma_addr_t dma_ring; 206 void __iomem *regs; 207 struct mii_bus *mii_bus; 208 struct phy_device *phy; 209 char phy_name[MII_BUS_ID_SIZE + 3]; 210 int oldlink, oldspeed, oldduplex; 211 u32 msg_enable; 212 struct net_device *dev; 213 struct work_struct reset_work; 214 struct platform_device *pdev; 215 struct napi_struct napi; 216 atomic_t reset_pending; 217 }; 218 219 static irqreturn_t cpmac_irq(int, void *); 220 static void cpmac_hw_start(struct net_device *dev); 221 static void cpmac_hw_stop(struct net_device *dev); 222 static int cpmac_stop(struct net_device *dev); 223 static int cpmac_open(struct net_device *dev); 224 225 static void cpmac_dump_regs(struct net_device *dev) 226 { 227 int i; 228 struct cpmac_priv *priv = netdev_priv(dev); 229 230 for (i = 0; i < CPMAC_REG_END; i += 4) { 231 if (i % 16 == 0) { 232 if (i) 233 printk("\n"); 234 printk("%s: reg[%p]:", dev->name, priv->regs + i); 235 } 236 printk(" %08x", cpmac_read(priv->regs, i)); 237 } 238 printk("\n"); 239 } 240 241 static void cpmac_dump_desc(struct net_device *dev, struct cpmac_desc *desc) 242 { 243 int i; 244 245 printk("%s: desc[%p]:", dev->name, desc); 246 for (i = 0; i < sizeof(*desc) / 4; i++) 247 printk(" %08x", ((u32 *)desc)[i]); 248 printk("\n"); 249 } 250 251 static void cpmac_dump_all_desc(struct net_device *dev) 252 { 253 struct cpmac_priv *priv = netdev_priv(dev); 254 struct cpmac_desc *dump = priv->rx_head; 255 256 do { 257 cpmac_dump_desc(dev, dump); 258 dump = dump->next; 259 } while (dump != priv->rx_head); 260 } 261 262 static void cpmac_dump_skb(struct net_device *dev, struct sk_buff *skb) 263 { 264 int i; 265 266 printk("%s: skb 0x%p, len=%d\n", dev->name, skb, skb->len); 267 for (i = 0; i < skb->len; i++) { 268 if (i % 16 == 0) { 269 if (i) 270 printk("\n"); 271 printk("%s: data[%p]:", dev->name, skb->data + i); 272 } 273 printk(" %02x", ((u8 *)skb->data)[i]); 274 } 275 printk("\n"); 276 } 277 278 static int cpmac_mdio_read(struct mii_bus *bus, int phy_id, int reg) 279 { 280 u32 val; 281 282 while (cpmac_read(bus->priv, CPMAC_MDIO_ACCESS(0)) & MDIO_BUSY) 283 cpu_relax(); 284 cpmac_write(bus->priv, CPMAC_MDIO_ACCESS(0), MDIO_BUSY | MDIO_REG(reg) | 285 MDIO_PHY(phy_id)); 286 while ((val = cpmac_read(bus->priv, CPMAC_MDIO_ACCESS(0))) & MDIO_BUSY) 287 cpu_relax(); 288 289 return MDIO_DATA(val); 290 } 291 292 static int cpmac_mdio_write(struct mii_bus *bus, int phy_id, 293 int reg, u16 val) 294 { 295 while (cpmac_read(bus->priv, CPMAC_MDIO_ACCESS(0)) & MDIO_BUSY) 296 cpu_relax(); 297 cpmac_write(bus->priv, CPMAC_MDIO_ACCESS(0), MDIO_BUSY | MDIO_WRITE | 298 MDIO_REG(reg) | MDIO_PHY(phy_id) | MDIO_DATA(val)); 299 300 return 0; 301 } 302 303 static int cpmac_mdio_reset(struct mii_bus *bus) 304 { 305 struct clk *cpmac_clk; 306 307 cpmac_clk = clk_get(&bus->dev, "cpmac"); 308 if (IS_ERR(cpmac_clk)) { 309 pr_err("unable to get cpmac clock\n"); 310 return -1; 311 } 312 ar7_device_reset(AR7_RESET_BIT_MDIO); 313 cpmac_write(bus->priv, CPMAC_MDIO_CONTROL, MDIOC_ENABLE | 314 MDIOC_CLKDIV(clk_get_rate(cpmac_clk) / 2200000 - 1)); 315 316 return 0; 317 } 318 319 static struct mii_bus *cpmac_mii; 320 321 static void cpmac_set_multicast_list(struct net_device *dev) 322 { 323 struct netdev_hw_addr *ha; 324 u8 tmp; 325 u32 mbp, bit, hash[2] = { 0, }; 326 struct cpmac_priv *priv = netdev_priv(dev); 327 328 mbp = cpmac_read(priv->regs, CPMAC_MBP); 329 if (dev->flags & IFF_PROMISC) { 330 cpmac_write(priv->regs, CPMAC_MBP, (mbp & ~MBP_PROMISCCHAN(0)) | 331 MBP_RXPROMISC); 332 } else { 333 cpmac_write(priv->regs, CPMAC_MBP, mbp & ~MBP_RXPROMISC); 334 if (dev->flags & IFF_ALLMULTI) { 335 /* enable all multicast mode */ 336 cpmac_write(priv->regs, CPMAC_MAC_HASH_LO, 0xffffffff); 337 cpmac_write(priv->regs, CPMAC_MAC_HASH_HI, 0xffffffff); 338 } else { 339 /* cpmac uses some strange mac address hashing 340 * (not crc32) 341 */ 342 netdev_for_each_mc_addr(ha, dev) { 343 bit = 0; 344 tmp = ha->addr[0]; 345 bit ^= (tmp >> 2) ^ (tmp << 4); 346 tmp = ha->addr[1]; 347 bit ^= (tmp >> 4) ^ (tmp << 2); 348 tmp = ha->addr[2]; 349 bit ^= (tmp >> 6) ^ tmp; 350 tmp = ha->addr[3]; 351 bit ^= (tmp >> 2) ^ (tmp << 4); 352 tmp = ha->addr[4]; 353 bit ^= (tmp >> 4) ^ (tmp << 2); 354 tmp = ha->addr[5]; 355 bit ^= (tmp >> 6) ^ tmp; 356 bit &= 0x3f; 357 hash[bit / 32] |= 1 << (bit % 32); 358 } 359 360 cpmac_write(priv->regs, CPMAC_MAC_HASH_LO, hash[0]); 361 cpmac_write(priv->regs, CPMAC_MAC_HASH_HI, hash[1]); 362 } 363 } 364 } 365 366 static struct sk_buff *cpmac_rx_one(struct cpmac_priv *priv, 367 struct cpmac_desc *desc) 368 { 369 struct sk_buff *skb, *result = NULL; 370 371 if (unlikely(netif_msg_hw(priv))) 372 cpmac_dump_desc(priv->dev, desc); 373 cpmac_write(priv->regs, CPMAC_RX_ACK(0), (u32)desc->mapping); 374 if (unlikely(!desc->datalen)) { 375 if (netif_msg_rx_err(priv) && net_ratelimit()) 376 netdev_warn(priv->dev, "rx: spurious interrupt\n"); 377 378 return NULL; 379 } 380 381 skb = netdev_alloc_skb_ip_align(priv->dev, CPMAC_SKB_SIZE); 382 if (likely(skb)) { 383 skb_put(desc->skb, desc->datalen); 384 desc->skb->protocol = eth_type_trans(desc->skb, priv->dev); 385 skb_checksum_none_assert(desc->skb); 386 priv->dev->stats.rx_packets++; 387 priv->dev->stats.rx_bytes += desc->datalen; 388 result = desc->skb; 389 dma_unmap_single(&priv->dev->dev, desc->data_mapping, 390 CPMAC_SKB_SIZE, DMA_FROM_DEVICE); 391 desc->skb = skb; 392 desc->data_mapping = dma_map_single(&priv->dev->dev, skb->data, 393 CPMAC_SKB_SIZE, 394 DMA_FROM_DEVICE); 395 desc->hw_data = (u32)desc->data_mapping; 396 if (unlikely(netif_msg_pktdata(priv))) { 397 netdev_dbg(priv->dev, "received packet:\n"); 398 cpmac_dump_skb(priv->dev, result); 399 } 400 } else { 401 if (netif_msg_rx_err(priv) && net_ratelimit()) 402 netdev_warn(priv->dev, 403 "low on skbs, dropping packet\n"); 404 405 priv->dev->stats.rx_dropped++; 406 } 407 408 desc->buflen = CPMAC_SKB_SIZE; 409 desc->dataflags = CPMAC_OWN; 410 411 return result; 412 } 413 414 static int cpmac_poll(struct napi_struct *napi, int budget) 415 { 416 struct sk_buff *skb; 417 struct cpmac_desc *desc, *restart; 418 struct cpmac_priv *priv = container_of(napi, struct cpmac_priv, napi); 419 int received = 0, processed = 0; 420 421 spin_lock(&priv->rx_lock); 422 if (unlikely(!priv->rx_head)) { 423 if (netif_msg_rx_err(priv) && net_ratelimit()) 424 netdev_warn(priv->dev, "rx: polling, but no queue\n"); 425 426 spin_unlock(&priv->rx_lock); 427 napi_complete(napi); 428 return 0; 429 } 430 431 desc = priv->rx_head; 432 restart = NULL; 433 while (((desc->dataflags & CPMAC_OWN) == 0) && (received < budget)) { 434 processed++; 435 436 if ((desc->dataflags & CPMAC_EOQ) != 0) { 437 /* The last update to eoq->hw_next didn't happen 438 * soon enough, and the receiver stopped here. 439 * Remember this descriptor so we can restart 440 * the receiver after freeing some space. 441 */ 442 if (unlikely(restart)) { 443 if (netif_msg_rx_err(priv)) 444 netdev_err(priv->dev, "poll found a" 445 " duplicate EOQ: %p and %p\n", 446 restart, desc); 447 goto fatal_error; 448 } 449 450 restart = desc->next; 451 } 452 453 skb = cpmac_rx_one(priv, desc); 454 if (likely(skb)) { 455 netif_receive_skb(skb); 456 received++; 457 } 458 desc = desc->next; 459 } 460 461 if (desc != priv->rx_head) { 462 /* We freed some buffers, but not the whole ring, 463 * add what we did free to the rx list 464 */ 465 desc->prev->hw_next = (u32)0; 466 priv->rx_head->prev->hw_next = priv->rx_head->mapping; 467 } 468 469 /* Optimization: If we did not actually process an EOQ (perhaps because 470 * of quota limits), check to see if the tail of the queue has EOQ set. 471 * We should immediately restart in that case so that the receiver can 472 * restart and run in parallel with more packet processing. 473 * This lets us handle slightly larger bursts before running 474 * out of ring space (assuming dev->weight < ring_size) 475 */ 476 477 if (!restart && 478 (priv->rx_head->prev->dataflags & (CPMAC_OWN|CPMAC_EOQ)) 479 == CPMAC_EOQ && 480 (priv->rx_head->dataflags & CPMAC_OWN) != 0) { 481 /* reset EOQ so the poll loop (above) doesn't try to 482 * restart this when it eventually gets to this descriptor. 483 */ 484 priv->rx_head->prev->dataflags &= ~CPMAC_EOQ; 485 restart = priv->rx_head; 486 } 487 488 if (restart) { 489 priv->dev->stats.rx_errors++; 490 priv->dev->stats.rx_fifo_errors++; 491 if (netif_msg_rx_err(priv) && net_ratelimit()) 492 netdev_warn(priv->dev, "rx dma ring overrun\n"); 493 494 if (unlikely((restart->dataflags & CPMAC_OWN) == 0)) { 495 if (netif_msg_drv(priv)) 496 netdev_err(priv->dev, "cpmac_poll is trying " 497 "to restart rx from a descriptor " 498 "that's not free: %p\n", restart); 499 goto fatal_error; 500 } 501 502 cpmac_write(priv->regs, CPMAC_RX_PTR(0), restart->mapping); 503 } 504 505 priv->rx_head = desc; 506 spin_unlock(&priv->rx_lock); 507 if (unlikely(netif_msg_rx_status(priv))) 508 netdev_dbg(priv->dev, "poll processed %d packets\n", received); 509 510 if (processed == 0) { 511 /* we ran out of packets to read, 512 * revert to interrupt-driven mode 513 */ 514 napi_complete(napi); 515 cpmac_write(priv->regs, CPMAC_RX_INT_ENABLE, 1); 516 return 0; 517 } 518 519 return 1; 520 521 fatal_error: 522 /* Something went horribly wrong. 523 * Reset hardware to try to recover rather than wedging. 524 */ 525 if (netif_msg_drv(priv)) { 526 netdev_err(priv->dev, "cpmac_poll is confused. " 527 "Resetting hardware\n"); 528 cpmac_dump_all_desc(priv->dev); 529 netdev_dbg(priv->dev, "RX_PTR(0)=0x%08x RX_ACK(0)=0x%08x\n", 530 cpmac_read(priv->regs, CPMAC_RX_PTR(0)), 531 cpmac_read(priv->regs, CPMAC_RX_ACK(0))); 532 } 533 534 spin_unlock(&priv->rx_lock); 535 napi_complete(napi); 536 netif_tx_stop_all_queues(priv->dev); 537 napi_disable(&priv->napi); 538 539 atomic_inc(&priv->reset_pending); 540 cpmac_hw_stop(priv->dev); 541 if (!schedule_work(&priv->reset_work)) 542 atomic_dec(&priv->reset_pending); 543 544 return 0; 545 546 } 547 548 static int cpmac_start_xmit(struct sk_buff *skb, struct net_device *dev) 549 { 550 int queue, len; 551 struct cpmac_desc *desc; 552 struct cpmac_priv *priv = netdev_priv(dev); 553 554 if (unlikely(atomic_read(&priv->reset_pending))) 555 return NETDEV_TX_BUSY; 556 557 if (unlikely(skb_padto(skb, ETH_ZLEN))) 558 return NETDEV_TX_OK; 559 560 len = max(skb->len, ETH_ZLEN); 561 queue = skb_get_queue_mapping(skb); 562 netif_stop_subqueue(dev, queue); 563 564 desc = &priv->desc_ring[queue]; 565 if (unlikely(desc->dataflags & CPMAC_OWN)) { 566 if (netif_msg_tx_err(priv) && net_ratelimit()) 567 netdev_warn(dev, "tx dma ring full\n"); 568 569 return NETDEV_TX_BUSY; 570 } 571 572 spin_lock(&priv->lock); 573 spin_unlock(&priv->lock); 574 desc->dataflags = CPMAC_SOP | CPMAC_EOP | CPMAC_OWN; 575 desc->skb = skb; 576 desc->data_mapping = dma_map_single(&dev->dev, skb->data, len, 577 DMA_TO_DEVICE); 578 desc->hw_data = (u32)desc->data_mapping; 579 desc->datalen = len; 580 desc->buflen = len; 581 if (unlikely(netif_msg_tx_queued(priv))) 582 netdev_dbg(dev, "sending 0x%p, len=%d\n", skb, skb->len); 583 if (unlikely(netif_msg_hw(priv))) 584 cpmac_dump_desc(dev, desc); 585 if (unlikely(netif_msg_pktdata(priv))) 586 cpmac_dump_skb(dev, skb); 587 cpmac_write(priv->regs, CPMAC_TX_PTR(queue), (u32)desc->mapping); 588 589 return NETDEV_TX_OK; 590 } 591 592 static void cpmac_end_xmit(struct net_device *dev, int queue) 593 { 594 struct cpmac_desc *desc; 595 struct cpmac_priv *priv = netdev_priv(dev); 596 597 desc = &priv->desc_ring[queue]; 598 cpmac_write(priv->regs, CPMAC_TX_ACK(queue), (u32)desc->mapping); 599 if (likely(desc->skb)) { 600 spin_lock(&priv->lock); 601 dev->stats.tx_packets++; 602 dev->stats.tx_bytes += desc->skb->len; 603 spin_unlock(&priv->lock); 604 dma_unmap_single(&dev->dev, desc->data_mapping, desc->skb->len, 605 DMA_TO_DEVICE); 606 607 if (unlikely(netif_msg_tx_done(priv))) 608 netdev_dbg(dev, "sent 0x%p, len=%d\n", 609 desc->skb, desc->skb->len); 610 611 dev_kfree_skb_irq(desc->skb); 612 desc->skb = NULL; 613 if (__netif_subqueue_stopped(dev, queue)) 614 netif_wake_subqueue(dev, queue); 615 } else { 616 if (netif_msg_tx_err(priv) && net_ratelimit()) 617 netdev_warn(dev, "end_xmit: spurious interrupt\n"); 618 if (__netif_subqueue_stopped(dev, queue)) 619 netif_wake_subqueue(dev, queue); 620 } 621 } 622 623 static void cpmac_hw_stop(struct net_device *dev) 624 { 625 int i; 626 struct cpmac_priv *priv = netdev_priv(dev); 627 struct plat_cpmac_data *pdata = dev_get_platdata(&priv->pdev->dev); 628 629 ar7_device_reset(pdata->reset_bit); 630 cpmac_write(priv->regs, CPMAC_RX_CONTROL, 631 cpmac_read(priv->regs, CPMAC_RX_CONTROL) & ~1); 632 cpmac_write(priv->regs, CPMAC_TX_CONTROL, 633 cpmac_read(priv->regs, CPMAC_TX_CONTROL) & ~1); 634 for (i = 0; i < 8; i++) { 635 cpmac_write(priv->regs, CPMAC_TX_PTR(i), 0); 636 cpmac_write(priv->regs, CPMAC_RX_PTR(i), 0); 637 } 638 cpmac_write(priv->regs, CPMAC_UNICAST_CLEAR, 0xff); 639 cpmac_write(priv->regs, CPMAC_RX_INT_CLEAR, 0xff); 640 cpmac_write(priv->regs, CPMAC_TX_INT_CLEAR, 0xff); 641 cpmac_write(priv->regs, CPMAC_MAC_INT_CLEAR, 0xff); 642 cpmac_write(priv->regs, CPMAC_MAC_CONTROL, 643 cpmac_read(priv->regs, CPMAC_MAC_CONTROL) & ~MAC_MII); 644 } 645 646 static void cpmac_hw_start(struct net_device *dev) 647 { 648 int i; 649 struct cpmac_priv *priv = netdev_priv(dev); 650 struct plat_cpmac_data *pdata = dev_get_platdata(&priv->pdev->dev); 651 652 ar7_device_reset(pdata->reset_bit); 653 for (i = 0; i < 8; i++) { 654 cpmac_write(priv->regs, CPMAC_TX_PTR(i), 0); 655 cpmac_write(priv->regs, CPMAC_RX_PTR(i), 0); 656 } 657 cpmac_write(priv->regs, CPMAC_RX_PTR(0), priv->rx_head->mapping); 658 659 cpmac_write(priv->regs, CPMAC_MBP, MBP_RXSHORT | MBP_RXBCAST | 660 MBP_RXMCAST); 661 cpmac_write(priv->regs, CPMAC_BUFFER_OFFSET, 0); 662 for (i = 0; i < 8; i++) 663 cpmac_write(priv->regs, CPMAC_MAC_ADDR_LO(i), dev->dev_addr[5]); 664 cpmac_write(priv->regs, CPMAC_MAC_ADDR_MID, dev->dev_addr[4]); 665 cpmac_write(priv->regs, CPMAC_MAC_ADDR_HI, dev->dev_addr[0] | 666 (dev->dev_addr[1] << 8) | (dev->dev_addr[2] << 16) | 667 (dev->dev_addr[3] << 24)); 668 cpmac_write(priv->regs, CPMAC_MAX_LENGTH, CPMAC_SKB_SIZE); 669 cpmac_write(priv->regs, CPMAC_UNICAST_CLEAR, 0xff); 670 cpmac_write(priv->regs, CPMAC_RX_INT_CLEAR, 0xff); 671 cpmac_write(priv->regs, CPMAC_TX_INT_CLEAR, 0xff); 672 cpmac_write(priv->regs, CPMAC_MAC_INT_CLEAR, 0xff); 673 cpmac_write(priv->regs, CPMAC_UNICAST_ENABLE, 1); 674 cpmac_write(priv->regs, CPMAC_RX_INT_ENABLE, 1); 675 cpmac_write(priv->regs, CPMAC_TX_INT_ENABLE, 0xff); 676 cpmac_write(priv->regs, CPMAC_MAC_INT_ENABLE, 3); 677 678 cpmac_write(priv->regs, CPMAC_RX_CONTROL, 679 cpmac_read(priv->regs, CPMAC_RX_CONTROL) | 1); 680 cpmac_write(priv->regs, CPMAC_TX_CONTROL, 681 cpmac_read(priv->regs, CPMAC_TX_CONTROL) | 1); 682 cpmac_write(priv->regs, CPMAC_MAC_CONTROL, 683 cpmac_read(priv->regs, CPMAC_MAC_CONTROL) | MAC_MII | 684 MAC_FDX); 685 } 686 687 static void cpmac_clear_rx(struct net_device *dev) 688 { 689 struct cpmac_priv *priv = netdev_priv(dev); 690 struct cpmac_desc *desc; 691 int i; 692 693 if (unlikely(!priv->rx_head)) 694 return; 695 desc = priv->rx_head; 696 for (i = 0; i < priv->ring_size; i++) { 697 if ((desc->dataflags & CPMAC_OWN) == 0) { 698 if (netif_msg_rx_err(priv) && net_ratelimit()) 699 netdev_warn(dev, "packet dropped\n"); 700 if (unlikely(netif_msg_hw(priv))) 701 cpmac_dump_desc(dev, desc); 702 desc->dataflags = CPMAC_OWN; 703 dev->stats.rx_dropped++; 704 } 705 desc->hw_next = desc->next->mapping; 706 desc = desc->next; 707 } 708 priv->rx_head->prev->hw_next = 0; 709 } 710 711 static void cpmac_clear_tx(struct net_device *dev) 712 { 713 struct cpmac_priv *priv = netdev_priv(dev); 714 int i; 715 716 if (unlikely(!priv->desc_ring)) 717 return; 718 for (i = 0; i < CPMAC_QUEUES; i++) { 719 priv->desc_ring[i].dataflags = 0; 720 if (priv->desc_ring[i].skb) { 721 dev_kfree_skb_any(priv->desc_ring[i].skb); 722 priv->desc_ring[i].skb = NULL; 723 } 724 } 725 } 726 727 static void cpmac_hw_error(struct work_struct *work) 728 { 729 struct cpmac_priv *priv = 730 container_of(work, struct cpmac_priv, reset_work); 731 732 spin_lock(&priv->rx_lock); 733 cpmac_clear_rx(priv->dev); 734 spin_unlock(&priv->rx_lock); 735 cpmac_clear_tx(priv->dev); 736 cpmac_hw_start(priv->dev); 737 barrier(); 738 atomic_dec(&priv->reset_pending); 739 740 netif_tx_wake_all_queues(priv->dev); 741 cpmac_write(priv->regs, CPMAC_MAC_INT_ENABLE, 3); 742 } 743 744 static void cpmac_check_status(struct net_device *dev) 745 { 746 struct cpmac_priv *priv = netdev_priv(dev); 747 748 u32 macstatus = cpmac_read(priv->regs, CPMAC_MAC_STATUS); 749 int rx_channel = (macstatus >> 8) & 7; 750 int rx_code = (macstatus >> 12) & 15; 751 int tx_channel = (macstatus >> 16) & 7; 752 int tx_code = (macstatus >> 20) & 15; 753 754 if (rx_code || tx_code) { 755 if (netif_msg_drv(priv) && net_ratelimit()) { 756 /* Can't find any documentation on what these 757 * error codes actually are. So just log them and hope.. 758 */ 759 if (rx_code) 760 netdev_warn(dev, "host error %d on rx " 761 "channel %d (macstatus %08x), resetting\n", 762 rx_code, rx_channel, macstatus); 763 if (tx_code) 764 netdev_warn(dev, "host error %d on tx " 765 "channel %d (macstatus %08x), resetting\n", 766 tx_code, tx_channel, macstatus); 767 } 768 769 netif_tx_stop_all_queues(dev); 770 cpmac_hw_stop(dev); 771 if (schedule_work(&priv->reset_work)) 772 atomic_inc(&priv->reset_pending); 773 if (unlikely(netif_msg_hw(priv))) 774 cpmac_dump_regs(dev); 775 } 776 cpmac_write(priv->regs, CPMAC_MAC_INT_CLEAR, 0xff); 777 } 778 779 static irqreturn_t cpmac_irq(int irq, void *dev_id) 780 { 781 struct net_device *dev = dev_id; 782 struct cpmac_priv *priv; 783 int queue; 784 u32 status; 785 786 priv = netdev_priv(dev); 787 788 status = cpmac_read(priv->regs, CPMAC_MAC_INT_VECTOR); 789 790 if (unlikely(netif_msg_intr(priv))) 791 netdev_dbg(dev, "interrupt status: 0x%08x\n", status); 792 793 if (status & MAC_INT_TX) 794 cpmac_end_xmit(dev, (status & 7)); 795 796 if (status & MAC_INT_RX) { 797 queue = (status >> 8) & 7; 798 if (napi_schedule_prep(&priv->napi)) { 799 cpmac_write(priv->regs, CPMAC_RX_INT_CLEAR, 1 << queue); 800 __napi_schedule(&priv->napi); 801 } 802 } 803 804 cpmac_write(priv->regs, CPMAC_MAC_EOI_VECTOR, 0); 805 806 if (unlikely(status & (MAC_INT_HOST | MAC_INT_STATUS))) 807 cpmac_check_status(dev); 808 809 return IRQ_HANDLED; 810 } 811 812 static void cpmac_tx_timeout(struct net_device *dev) 813 { 814 struct cpmac_priv *priv = netdev_priv(dev); 815 816 spin_lock(&priv->lock); 817 dev->stats.tx_errors++; 818 spin_unlock(&priv->lock); 819 if (netif_msg_tx_err(priv) && net_ratelimit()) 820 netdev_warn(dev, "transmit timeout\n"); 821 822 atomic_inc(&priv->reset_pending); 823 barrier(); 824 cpmac_clear_tx(dev); 825 barrier(); 826 atomic_dec(&priv->reset_pending); 827 828 netif_tx_wake_all_queues(priv->dev); 829 } 830 831 static int cpmac_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) 832 { 833 struct cpmac_priv *priv = netdev_priv(dev); 834 835 if (!(netif_running(dev))) 836 return -EINVAL; 837 if (!priv->phy) 838 return -EINVAL; 839 840 return phy_mii_ioctl(priv->phy, ifr, cmd); 841 } 842 843 static int cpmac_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) 844 { 845 struct cpmac_priv *priv = netdev_priv(dev); 846 847 if (priv->phy) 848 return phy_ethtool_gset(priv->phy, cmd); 849 850 return -EINVAL; 851 } 852 853 static int cpmac_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) 854 { 855 struct cpmac_priv *priv = netdev_priv(dev); 856 857 if (!capable(CAP_NET_ADMIN)) 858 return -EPERM; 859 860 if (priv->phy) 861 return phy_ethtool_sset(priv->phy, cmd); 862 863 return -EINVAL; 864 } 865 866 static void cpmac_get_ringparam(struct net_device *dev, 867 struct ethtool_ringparam *ring) 868 { 869 struct cpmac_priv *priv = netdev_priv(dev); 870 871 ring->rx_max_pending = 1024; 872 ring->rx_mini_max_pending = 1; 873 ring->rx_jumbo_max_pending = 1; 874 ring->tx_max_pending = 1; 875 876 ring->rx_pending = priv->ring_size; 877 ring->rx_mini_pending = 1; 878 ring->rx_jumbo_pending = 1; 879 ring->tx_pending = 1; 880 } 881 882 static int cpmac_set_ringparam(struct net_device *dev, 883 struct ethtool_ringparam *ring) 884 { 885 struct cpmac_priv *priv = netdev_priv(dev); 886 887 if (netif_running(dev)) 888 return -EBUSY; 889 priv->ring_size = ring->rx_pending; 890 891 return 0; 892 } 893 894 static void cpmac_get_drvinfo(struct net_device *dev, 895 struct ethtool_drvinfo *info) 896 { 897 strlcpy(info->driver, "cpmac", sizeof(info->driver)); 898 strlcpy(info->version, CPMAC_VERSION, sizeof(info->version)); 899 snprintf(info->bus_info, sizeof(info->bus_info), "%s", "cpmac"); 900 } 901 902 static const struct ethtool_ops cpmac_ethtool_ops = { 903 .get_settings = cpmac_get_settings, 904 .set_settings = cpmac_set_settings, 905 .get_drvinfo = cpmac_get_drvinfo, 906 .get_link = ethtool_op_get_link, 907 .get_ringparam = cpmac_get_ringparam, 908 .set_ringparam = cpmac_set_ringparam, 909 }; 910 911 static void cpmac_adjust_link(struct net_device *dev) 912 { 913 struct cpmac_priv *priv = netdev_priv(dev); 914 int new_state = 0; 915 916 spin_lock(&priv->lock); 917 if (priv->phy->link) { 918 netif_tx_start_all_queues(dev); 919 if (priv->phy->duplex != priv->oldduplex) { 920 new_state = 1; 921 priv->oldduplex = priv->phy->duplex; 922 } 923 924 if (priv->phy->speed != priv->oldspeed) { 925 new_state = 1; 926 priv->oldspeed = priv->phy->speed; 927 } 928 929 if (!priv->oldlink) { 930 new_state = 1; 931 priv->oldlink = 1; 932 } 933 } else if (priv->oldlink) { 934 new_state = 1; 935 priv->oldlink = 0; 936 priv->oldspeed = 0; 937 priv->oldduplex = -1; 938 } 939 940 if (new_state && netif_msg_link(priv) && net_ratelimit()) 941 phy_print_status(priv->phy); 942 943 spin_unlock(&priv->lock); 944 } 945 946 static int cpmac_open(struct net_device *dev) 947 { 948 int i, size, res; 949 struct cpmac_priv *priv = netdev_priv(dev); 950 struct resource *mem; 951 struct cpmac_desc *desc; 952 struct sk_buff *skb; 953 954 mem = platform_get_resource_byname(priv->pdev, IORESOURCE_MEM, "regs"); 955 if (!request_mem_region(mem->start, resource_size(mem), dev->name)) { 956 if (netif_msg_drv(priv)) 957 netdev_err(dev, "failed to request registers\n"); 958 959 res = -ENXIO; 960 goto fail_reserve; 961 } 962 963 priv->regs = ioremap(mem->start, resource_size(mem)); 964 if (!priv->regs) { 965 if (netif_msg_drv(priv)) 966 netdev_err(dev, "failed to remap registers\n"); 967 968 res = -ENXIO; 969 goto fail_remap; 970 } 971 972 size = priv->ring_size + CPMAC_QUEUES; 973 priv->desc_ring = dma_alloc_coherent(&dev->dev, 974 sizeof(struct cpmac_desc) * size, 975 &priv->dma_ring, 976 GFP_KERNEL); 977 if (!priv->desc_ring) { 978 res = -ENOMEM; 979 goto fail_alloc; 980 } 981 982 for (i = 0; i < size; i++) 983 priv->desc_ring[i].mapping = priv->dma_ring + sizeof(*desc) * i; 984 985 priv->rx_head = &priv->desc_ring[CPMAC_QUEUES]; 986 for (i = 0, desc = priv->rx_head; i < priv->ring_size; i++, desc++) { 987 skb = netdev_alloc_skb_ip_align(dev, CPMAC_SKB_SIZE); 988 if (unlikely(!skb)) { 989 res = -ENOMEM; 990 goto fail_desc; 991 } 992 desc->skb = skb; 993 desc->data_mapping = dma_map_single(&dev->dev, skb->data, 994 CPMAC_SKB_SIZE, 995 DMA_FROM_DEVICE); 996 desc->hw_data = (u32)desc->data_mapping; 997 desc->buflen = CPMAC_SKB_SIZE; 998 desc->dataflags = CPMAC_OWN; 999 desc->next = &priv->rx_head[(i + 1) % priv->ring_size]; 1000 desc->next->prev = desc; 1001 desc->hw_next = (u32)desc->next->mapping; 1002 } 1003 1004 priv->rx_head->prev->hw_next = (u32)0; 1005 1006 res = request_irq(dev->irq, cpmac_irq, IRQF_SHARED, dev->name, dev); 1007 if (res) { 1008 if (netif_msg_drv(priv)) 1009 netdev_err(dev, "failed to obtain irq\n"); 1010 1011 goto fail_irq; 1012 } 1013 1014 atomic_set(&priv->reset_pending, 0); 1015 INIT_WORK(&priv->reset_work, cpmac_hw_error); 1016 cpmac_hw_start(dev); 1017 1018 napi_enable(&priv->napi); 1019 priv->phy->state = PHY_CHANGELINK; 1020 phy_start(priv->phy); 1021 1022 return 0; 1023 1024 fail_irq: 1025 fail_desc: 1026 for (i = 0; i < priv->ring_size; i++) { 1027 if (priv->rx_head[i].skb) { 1028 dma_unmap_single(&dev->dev, 1029 priv->rx_head[i].data_mapping, 1030 CPMAC_SKB_SIZE, 1031 DMA_FROM_DEVICE); 1032 kfree_skb(priv->rx_head[i].skb); 1033 } 1034 } 1035 fail_alloc: 1036 kfree(priv->desc_ring); 1037 iounmap(priv->regs); 1038 1039 fail_remap: 1040 release_mem_region(mem->start, resource_size(mem)); 1041 1042 fail_reserve: 1043 return res; 1044 } 1045 1046 static int cpmac_stop(struct net_device *dev) 1047 { 1048 int i; 1049 struct cpmac_priv *priv = netdev_priv(dev); 1050 struct resource *mem; 1051 1052 netif_tx_stop_all_queues(dev); 1053 1054 cancel_work_sync(&priv->reset_work); 1055 napi_disable(&priv->napi); 1056 phy_stop(priv->phy); 1057 1058 cpmac_hw_stop(dev); 1059 1060 for (i = 0; i < 8; i++) 1061 cpmac_write(priv->regs, CPMAC_TX_PTR(i), 0); 1062 cpmac_write(priv->regs, CPMAC_RX_PTR(0), 0); 1063 cpmac_write(priv->regs, CPMAC_MBP, 0); 1064 1065 free_irq(dev->irq, dev); 1066 iounmap(priv->regs); 1067 mem = platform_get_resource_byname(priv->pdev, IORESOURCE_MEM, "regs"); 1068 release_mem_region(mem->start, resource_size(mem)); 1069 priv->rx_head = &priv->desc_ring[CPMAC_QUEUES]; 1070 for (i = 0; i < priv->ring_size; i++) { 1071 if (priv->rx_head[i].skb) { 1072 dma_unmap_single(&dev->dev, 1073 priv->rx_head[i].data_mapping, 1074 CPMAC_SKB_SIZE, 1075 DMA_FROM_DEVICE); 1076 kfree_skb(priv->rx_head[i].skb); 1077 } 1078 } 1079 1080 dma_free_coherent(&dev->dev, sizeof(struct cpmac_desc) * 1081 (CPMAC_QUEUES + priv->ring_size), 1082 priv->desc_ring, priv->dma_ring); 1083 1084 return 0; 1085 } 1086 1087 static const struct net_device_ops cpmac_netdev_ops = { 1088 .ndo_open = cpmac_open, 1089 .ndo_stop = cpmac_stop, 1090 .ndo_start_xmit = cpmac_start_xmit, 1091 .ndo_tx_timeout = cpmac_tx_timeout, 1092 .ndo_set_rx_mode = cpmac_set_multicast_list, 1093 .ndo_do_ioctl = cpmac_ioctl, 1094 .ndo_change_mtu = eth_change_mtu, 1095 .ndo_validate_addr = eth_validate_addr, 1096 .ndo_set_mac_address = eth_mac_addr, 1097 }; 1098 1099 static int external_switch; 1100 1101 static int cpmac_probe(struct platform_device *pdev) 1102 { 1103 int rc, phy_id; 1104 char mdio_bus_id[MII_BUS_ID_SIZE]; 1105 struct resource *mem; 1106 struct cpmac_priv *priv; 1107 struct net_device *dev; 1108 struct plat_cpmac_data *pdata; 1109 1110 pdata = dev_get_platdata(&pdev->dev); 1111 1112 if (external_switch || dumb_switch) { 1113 strncpy(mdio_bus_id, "fixed-0", MII_BUS_ID_SIZE); /* fixed phys bus */ 1114 phy_id = pdev->id; 1115 } else { 1116 for (phy_id = 0; phy_id < PHY_MAX_ADDR; phy_id++) { 1117 if (!(pdata->phy_mask & (1 << phy_id))) 1118 continue; 1119 if (!mdiobus_get_phy(cpmac_mii, phy_id)) 1120 continue; 1121 strncpy(mdio_bus_id, cpmac_mii->id, MII_BUS_ID_SIZE); 1122 break; 1123 } 1124 } 1125 1126 if (phy_id == PHY_MAX_ADDR) { 1127 dev_err(&pdev->dev, "no PHY present, falling back " 1128 "to switch on MDIO bus 0\n"); 1129 strncpy(mdio_bus_id, "fixed-0", MII_BUS_ID_SIZE); /* fixed phys bus */ 1130 phy_id = pdev->id; 1131 } 1132 mdio_bus_id[sizeof(mdio_bus_id) - 1] = '\0'; 1133 1134 dev = alloc_etherdev_mq(sizeof(*priv), CPMAC_QUEUES); 1135 if (!dev) 1136 return -ENOMEM; 1137 1138 platform_set_drvdata(pdev, dev); 1139 priv = netdev_priv(dev); 1140 1141 priv->pdev = pdev; 1142 mem = platform_get_resource_byname(pdev, IORESOURCE_MEM, "regs"); 1143 if (!mem) { 1144 rc = -ENODEV; 1145 goto out; 1146 } 1147 1148 dev->irq = platform_get_irq_byname(pdev, "irq"); 1149 1150 dev->netdev_ops = &cpmac_netdev_ops; 1151 dev->ethtool_ops = &cpmac_ethtool_ops; 1152 1153 netif_napi_add(dev, &priv->napi, cpmac_poll, 64); 1154 1155 spin_lock_init(&priv->lock); 1156 spin_lock_init(&priv->rx_lock); 1157 priv->dev = dev; 1158 priv->ring_size = 64; 1159 priv->msg_enable = netif_msg_init(debug_level, 0xff); 1160 memcpy(dev->dev_addr, pdata->dev_addr, sizeof(pdata->dev_addr)); 1161 1162 snprintf(priv->phy_name, MII_BUS_ID_SIZE, PHY_ID_FMT, 1163 mdio_bus_id, phy_id); 1164 1165 priv->phy = phy_connect(dev, priv->phy_name, cpmac_adjust_link, 1166 PHY_INTERFACE_MODE_MII); 1167 1168 if (IS_ERR(priv->phy)) { 1169 if (netif_msg_drv(priv)) 1170 dev_err(&pdev->dev, "Could not attach to PHY\n"); 1171 1172 rc = PTR_ERR(priv->phy); 1173 goto out; 1174 } 1175 1176 rc = register_netdev(dev); 1177 if (rc) { 1178 dev_err(&pdev->dev, "Could not register net device\n"); 1179 goto fail; 1180 } 1181 1182 if (netif_msg_probe(priv)) { 1183 dev_info(&pdev->dev, "regs: %p, irq: %d, phy: %s, " 1184 "mac: %pM\n", (void *)mem->start, dev->irq, 1185 priv->phy_name, dev->dev_addr); 1186 } 1187 1188 return 0; 1189 1190 fail: 1191 free_netdev(dev); 1192 out: 1193 return rc; 1194 } 1195 1196 static int cpmac_remove(struct platform_device *pdev) 1197 { 1198 struct net_device *dev = platform_get_drvdata(pdev); 1199 1200 unregister_netdev(dev); 1201 free_netdev(dev); 1202 1203 return 0; 1204 } 1205 1206 static struct platform_driver cpmac_driver = { 1207 .driver = { 1208 .name = "cpmac", 1209 }, 1210 .probe = cpmac_probe, 1211 .remove = cpmac_remove, 1212 }; 1213 1214 int cpmac_init(void) 1215 { 1216 u32 mask; 1217 int i, res; 1218 1219 cpmac_mii = mdiobus_alloc(); 1220 if (cpmac_mii == NULL) 1221 return -ENOMEM; 1222 1223 cpmac_mii->name = "cpmac-mii"; 1224 cpmac_mii->read = cpmac_mdio_read; 1225 cpmac_mii->write = cpmac_mdio_write; 1226 cpmac_mii->reset = cpmac_mdio_reset; 1227 1228 cpmac_mii->priv = ioremap(AR7_REGS_MDIO, 256); 1229 1230 if (!cpmac_mii->priv) { 1231 pr_err("Can't ioremap mdio registers\n"); 1232 res = -ENXIO; 1233 goto fail_alloc; 1234 } 1235 1236 #warning FIXME: unhardcode gpio&reset bits 1237 ar7_gpio_disable(26); 1238 ar7_gpio_disable(27); 1239 ar7_device_reset(AR7_RESET_BIT_CPMAC_LO); 1240 ar7_device_reset(AR7_RESET_BIT_CPMAC_HI); 1241 ar7_device_reset(AR7_RESET_BIT_EPHY); 1242 1243 cpmac_mii->reset(cpmac_mii); 1244 1245 for (i = 0; i < 300; i++) { 1246 mask = cpmac_read(cpmac_mii->priv, CPMAC_MDIO_ALIVE); 1247 if (mask) 1248 break; 1249 else 1250 msleep(10); 1251 } 1252 1253 mask &= 0x7fffffff; 1254 if (mask & (mask - 1)) { 1255 external_switch = 1; 1256 mask = 0; 1257 } 1258 1259 cpmac_mii->phy_mask = ~(mask | 0x80000000); 1260 snprintf(cpmac_mii->id, MII_BUS_ID_SIZE, "cpmac-1"); 1261 1262 res = mdiobus_register(cpmac_mii); 1263 if (res) 1264 goto fail_mii; 1265 1266 res = platform_driver_register(&cpmac_driver); 1267 if (res) 1268 goto fail_cpmac; 1269 1270 return 0; 1271 1272 fail_cpmac: 1273 mdiobus_unregister(cpmac_mii); 1274 1275 fail_mii: 1276 iounmap(cpmac_mii->priv); 1277 1278 fail_alloc: 1279 mdiobus_free(cpmac_mii); 1280 1281 return res; 1282 } 1283 1284 void cpmac_exit(void) 1285 { 1286 platform_driver_unregister(&cpmac_driver); 1287 mdiobus_unregister(cpmac_mii); 1288 iounmap(cpmac_mii->priv); 1289 mdiobus_free(cpmac_mii); 1290 } 1291 1292 module_init(cpmac_init); 1293 module_exit(cpmac_exit); 1294