1 // SPDX-License-Identifier: GPL-2.0 2 /* TI K3 AM65x Common Platform Time Sync 3 * 4 * Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com 5 * 6 */ 7 8 #include <linux/clk.h> 9 #include <linux/clk-provider.h> 10 #include <linux/err.h> 11 #include <linux/if_vlan.h> 12 #include <linux/interrupt.h> 13 #include <linux/module.h> 14 #include <linux/netdevice.h> 15 #include <linux/net_tstamp.h> 16 #include <linux/of.h> 17 #include <linux/of_irq.h> 18 #include <linux/platform_device.h> 19 #include <linux/pm_runtime.h> 20 #include <linux/ptp_classify.h> 21 #include <linux/ptp_clock_kernel.h> 22 23 #include "am65-cpts.h" 24 25 struct am65_genf_regs { 26 u32 comp_lo; /* Comparison Low Value 0:31 */ 27 u32 comp_hi; /* Comparison High Value 32:63 */ 28 u32 control; /* control */ 29 u32 length; /* Length */ 30 u32 ppm_low; /* PPM Load Low Value 0:31 */ 31 u32 ppm_hi; /* PPM Load High Value 32:63 */ 32 u32 ts_nudge; /* Nudge value */ 33 } __aligned(32) __packed; 34 35 #define AM65_CPTS_GENF_MAX_NUM 9 36 #define AM65_CPTS_ESTF_MAX_NUM 8 37 38 struct am65_cpts_regs { 39 u32 idver; /* Identification and version */ 40 u32 control; /* Time sync control */ 41 u32 rftclk_sel; /* Reference Clock Select Register */ 42 u32 ts_push; /* Time stamp event push */ 43 u32 ts_load_val_lo; /* Time Stamp Load Low Value 0:31 */ 44 u32 ts_load_en; /* Time stamp load enable */ 45 u32 ts_comp_lo; /* Time Stamp Comparison Low Value 0:31 */ 46 u32 ts_comp_length; /* Time Stamp Comparison Length */ 47 u32 intstat_raw; /* Time sync interrupt status raw */ 48 u32 intstat_masked; /* Time sync interrupt status masked */ 49 u32 int_enable; /* Time sync interrupt enable */ 50 u32 ts_comp_nudge; /* Time Stamp Comparison Nudge Value */ 51 u32 event_pop; /* Event interrupt pop */ 52 u32 event_0; /* Event Time Stamp lo 0:31 */ 53 u32 event_1; /* Event Type Fields */ 54 u32 event_2; /* Event Type Fields domain */ 55 u32 event_3; /* Event Time Stamp hi 32:63 */ 56 u32 ts_load_val_hi; /* Time Stamp Load High Value 32:63 */ 57 u32 ts_comp_hi; /* Time Stamp Comparison High Value 32:63 */ 58 u32 ts_add_val; /* Time Stamp Add value */ 59 u32 ts_ppm_low; /* Time Stamp PPM Load Low Value 0:31 */ 60 u32 ts_ppm_hi; /* Time Stamp PPM Load High Value 32:63 */ 61 u32 ts_nudge; /* Time Stamp Nudge value */ 62 u32 reserv[33]; 63 struct am65_genf_regs genf[AM65_CPTS_GENF_MAX_NUM]; 64 struct am65_genf_regs estf[AM65_CPTS_ESTF_MAX_NUM]; 65 }; 66 67 /* CONTROL_REG */ 68 #define AM65_CPTS_CONTROL_EN BIT(0) 69 #define AM65_CPTS_CONTROL_INT_TEST BIT(1) 70 #define AM65_CPTS_CONTROL_TS_COMP_POLARITY BIT(2) 71 #define AM65_CPTS_CONTROL_TSTAMP_EN BIT(3) 72 #define AM65_CPTS_CONTROL_SEQUENCE_EN BIT(4) 73 #define AM65_CPTS_CONTROL_64MODE BIT(5) 74 #define AM65_CPTS_CONTROL_TS_COMP_TOG BIT(6) 75 #define AM65_CPTS_CONTROL_TS_PPM_DIR BIT(7) 76 #define AM65_CPTS_CONTROL_HW1_TS_PUSH_EN BIT(8) 77 #define AM65_CPTS_CONTROL_HW2_TS_PUSH_EN BIT(9) 78 #define AM65_CPTS_CONTROL_HW3_TS_PUSH_EN BIT(10) 79 #define AM65_CPTS_CONTROL_HW4_TS_PUSH_EN BIT(11) 80 #define AM65_CPTS_CONTROL_HW5_TS_PUSH_EN BIT(12) 81 #define AM65_CPTS_CONTROL_HW6_TS_PUSH_EN BIT(13) 82 #define AM65_CPTS_CONTROL_HW7_TS_PUSH_EN BIT(14) 83 #define AM65_CPTS_CONTROL_HW8_TS_PUSH_EN BIT(15) 84 #define AM65_CPTS_CONTROL_HW1_TS_PUSH_OFFSET (8) 85 86 #define AM65_CPTS_CONTROL_TX_GENF_CLR_EN BIT(17) 87 88 #define AM65_CPTS_CONTROL_TS_SYNC_SEL_MASK (0xF) 89 #define AM65_CPTS_CONTROL_TS_SYNC_SEL_SHIFT (28) 90 91 /* RFTCLK_SEL_REG */ 92 #define AM65_CPTS_RFTCLK_SEL_MASK (0x1F) 93 94 /* TS_PUSH_REG */ 95 #define AM65_CPTS_TS_PUSH BIT(0) 96 97 /* TS_LOAD_EN_REG */ 98 #define AM65_CPTS_TS_LOAD_EN BIT(0) 99 100 /* INTSTAT_RAW_REG */ 101 #define AM65_CPTS_INTSTAT_RAW_TS_PEND BIT(0) 102 103 /* INTSTAT_MASKED_REG */ 104 #define AM65_CPTS_INTSTAT_MASKED_TS_PEND BIT(0) 105 106 /* INT_ENABLE_REG */ 107 #define AM65_CPTS_INT_ENABLE_TS_PEND_EN BIT(0) 108 109 /* TS_COMP_NUDGE_REG */ 110 #define AM65_CPTS_TS_COMP_NUDGE_MASK (0xFF) 111 112 /* EVENT_POP_REG */ 113 #define AM65_CPTS_EVENT_POP BIT(0) 114 115 /* EVENT_1_REG */ 116 #define AM65_CPTS_EVENT_1_SEQUENCE_ID_MASK GENMASK(15, 0) 117 118 #define AM65_CPTS_EVENT_1_MESSAGE_TYPE_MASK GENMASK(19, 16) 119 #define AM65_CPTS_EVENT_1_MESSAGE_TYPE_SHIFT (16) 120 121 #define AM65_CPTS_EVENT_1_EVENT_TYPE_MASK GENMASK(23, 20) 122 #define AM65_CPTS_EVENT_1_EVENT_TYPE_SHIFT (20) 123 124 #define AM65_CPTS_EVENT_1_PORT_NUMBER_MASK GENMASK(28, 24) 125 #define AM65_CPTS_EVENT_1_PORT_NUMBER_SHIFT (24) 126 127 /* EVENT_2_REG */ 128 #define AM65_CPTS_EVENT_2_REG_DOMAIN_MASK (0xFF) 129 #define AM65_CPTS_EVENT_2_REG_DOMAIN_SHIFT (0) 130 131 enum { 132 AM65_CPTS_EV_PUSH, /* Time Stamp Push Event */ 133 AM65_CPTS_EV_ROLL, /* Time Stamp Rollover Event */ 134 AM65_CPTS_EV_HALF, /* Time Stamp Half Rollover Event */ 135 AM65_CPTS_EV_HW, /* Hardware Time Stamp Push Event */ 136 AM65_CPTS_EV_RX, /* Ethernet Receive Event */ 137 AM65_CPTS_EV_TX, /* Ethernet Transmit Event */ 138 AM65_CPTS_EV_TS_COMP, /* Time Stamp Compare Event */ 139 AM65_CPTS_EV_HOST, /* Host Transmit Event */ 140 }; 141 142 struct am65_cpts_event { 143 struct list_head list; 144 unsigned long tmo; 145 u32 event1; 146 u32 event2; 147 u64 timestamp; 148 }; 149 150 #define AM65_CPTS_FIFO_DEPTH (16) 151 #define AM65_CPTS_MAX_EVENTS (32) 152 #define AM65_CPTS_EVENT_RX_TX_TIMEOUT (20) /* ms */ 153 #define AM65_CPTS_SKB_TX_WORK_TIMEOUT 1 /* jiffies */ 154 #define AM65_CPTS_MIN_PPM 0x400 155 156 struct am65_cpts { 157 struct device *dev; 158 struct am65_cpts_regs __iomem *reg; 159 struct ptp_clock_info ptp_info; 160 struct ptp_clock *ptp_clock; 161 int phc_index; 162 struct clk_hw *clk_mux_hw; 163 struct device_node *clk_mux_np; 164 struct clk *refclk; 165 u32 refclk_freq; 166 struct list_head events; 167 struct list_head pool; 168 struct am65_cpts_event pool_data[AM65_CPTS_MAX_EVENTS]; 169 spinlock_t lock; /* protects events lists*/ 170 u32 ext_ts_inputs; 171 u32 genf_num; 172 u32 ts_add_val; 173 int irq; 174 struct mutex ptp_clk_lock; /* PHC access sync */ 175 u64 timestamp; 176 u32 genf_enable; 177 u32 hw_ts_enable; 178 struct sk_buff_head txq; 179 /* context save/restore */ 180 u64 sr_cpts_ns; 181 u64 sr_ktime_ns; 182 u32 sr_control; 183 u32 sr_int_enable; 184 u32 sr_rftclk_sel; 185 u32 sr_ts_ppm_hi; 186 u32 sr_ts_ppm_low; 187 struct am65_genf_regs sr_genf[AM65_CPTS_GENF_MAX_NUM]; 188 struct am65_genf_regs sr_estf[AM65_CPTS_ESTF_MAX_NUM]; 189 }; 190 191 struct am65_cpts_skb_cb_data { 192 unsigned long tmo; 193 u32 skb_mtype_seqid; 194 }; 195 196 #define am65_cpts_write32(c, v, r) writel(v, &(c)->reg->r) 197 #define am65_cpts_read32(c, r) readl(&(c)->reg->r) 198 199 static void am65_cpts_settime(struct am65_cpts *cpts, u64 start_tstamp) 200 { 201 u32 val; 202 203 val = upper_32_bits(start_tstamp); 204 am65_cpts_write32(cpts, val, ts_load_val_hi); 205 val = lower_32_bits(start_tstamp); 206 am65_cpts_write32(cpts, val, ts_load_val_lo); 207 208 am65_cpts_write32(cpts, AM65_CPTS_TS_LOAD_EN, ts_load_en); 209 } 210 211 static void am65_cpts_set_add_val(struct am65_cpts *cpts) 212 { 213 /* select coefficient according to the rate */ 214 cpts->ts_add_val = (NSEC_PER_SEC / cpts->refclk_freq - 1) & 0x7; 215 216 am65_cpts_write32(cpts, cpts->ts_add_val, ts_add_val); 217 } 218 219 static void am65_cpts_disable(struct am65_cpts *cpts) 220 { 221 am65_cpts_write32(cpts, 0, control); 222 am65_cpts_write32(cpts, 0, int_enable); 223 } 224 225 static int am65_cpts_event_get_port(struct am65_cpts_event *event) 226 { 227 return (event->event1 & AM65_CPTS_EVENT_1_PORT_NUMBER_MASK) >> 228 AM65_CPTS_EVENT_1_PORT_NUMBER_SHIFT; 229 } 230 231 static int am65_cpts_event_get_type(struct am65_cpts_event *event) 232 { 233 return (event->event1 & AM65_CPTS_EVENT_1_EVENT_TYPE_MASK) >> 234 AM65_CPTS_EVENT_1_EVENT_TYPE_SHIFT; 235 } 236 237 static int am65_cpts_cpts_purge_events(struct am65_cpts *cpts) 238 { 239 struct list_head *this, *next; 240 struct am65_cpts_event *event; 241 int removed = 0; 242 243 list_for_each_safe(this, next, &cpts->events) { 244 event = list_entry(this, struct am65_cpts_event, list); 245 if (time_after(jiffies, event->tmo)) { 246 list_del_init(&event->list); 247 list_add(&event->list, &cpts->pool); 248 ++removed; 249 } 250 } 251 252 if (removed) 253 dev_dbg(cpts->dev, "event pool cleaned up %d\n", removed); 254 return removed ? 0 : -1; 255 } 256 257 static bool am65_cpts_fifo_pop_event(struct am65_cpts *cpts, 258 struct am65_cpts_event *event) 259 { 260 u32 r = am65_cpts_read32(cpts, intstat_raw); 261 262 if (r & AM65_CPTS_INTSTAT_RAW_TS_PEND) { 263 event->timestamp = am65_cpts_read32(cpts, event_0); 264 event->event1 = am65_cpts_read32(cpts, event_1); 265 event->event2 = am65_cpts_read32(cpts, event_2); 266 event->timestamp |= (u64)am65_cpts_read32(cpts, event_3) << 32; 267 am65_cpts_write32(cpts, AM65_CPTS_EVENT_POP, event_pop); 268 return false; 269 } 270 return true; 271 } 272 273 static int am65_cpts_fifo_read(struct am65_cpts *cpts) 274 { 275 struct ptp_clock_event pevent; 276 struct am65_cpts_event *event; 277 bool schedule = false; 278 int i, type, ret = 0; 279 unsigned long flags; 280 281 spin_lock_irqsave(&cpts->lock, flags); 282 for (i = 0; i < AM65_CPTS_FIFO_DEPTH; i++) { 283 event = list_first_entry_or_null(&cpts->pool, 284 struct am65_cpts_event, list); 285 286 if (!event) { 287 if (am65_cpts_cpts_purge_events(cpts)) { 288 dev_err(cpts->dev, "cpts: event pool empty\n"); 289 ret = -1; 290 goto out; 291 } 292 continue; 293 } 294 295 if (am65_cpts_fifo_pop_event(cpts, event)) 296 break; 297 298 type = am65_cpts_event_get_type(event); 299 switch (type) { 300 case AM65_CPTS_EV_PUSH: 301 cpts->timestamp = event->timestamp; 302 dev_dbg(cpts->dev, "AM65_CPTS_EV_PUSH t:%llu\n", 303 cpts->timestamp); 304 break; 305 case AM65_CPTS_EV_RX: 306 case AM65_CPTS_EV_TX: 307 event->tmo = jiffies + 308 msecs_to_jiffies(AM65_CPTS_EVENT_RX_TX_TIMEOUT); 309 310 list_del_init(&event->list); 311 list_add_tail(&event->list, &cpts->events); 312 313 dev_dbg(cpts->dev, 314 "AM65_CPTS_EV_TX e1:%08x e2:%08x t:%lld\n", 315 event->event1, event->event2, 316 event->timestamp); 317 schedule = true; 318 break; 319 case AM65_CPTS_EV_HW: 320 pevent.index = am65_cpts_event_get_port(event) - 1; 321 pevent.timestamp = event->timestamp; 322 pevent.type = PTP_CLOCK_EXTTS; 323 dev_dbg(cpts->dev, "AM65_CPTS_EV_HW p:%d t:%llu\n", 324 pevent.index, event->timestamp); 325 326 ptp_clock_event(cpts->ptp_clock, &pevent); 327 break; 328 case AM65_CPTS_EV_HOST: 329 break; 330 case AM65_CPTS_EV_ROLL: 331 case AM65_CPTS_EV_HALF: 332 case AM65_CPTS_EV_TS_COMP: 333 dev_dbg(cpts->dev, 334 "AM65_CPTS_EVT: %d e1:%08x e2:%08x t:%lld\n", 335 type, 336 event->event1, event->event2, 337 event->timestamp); 338 break; 339 default: 340 dev_err(cpts->dev, "cpts: unknown event type\n"); 341 ret = -1; 342 goto out; 343 } 344 } 345 346 out: 347 spin_unlock_irqrestore(&cpts->lock, flags); 348 349 if (schedule) 350 ptp_schedule_worker(cpts->ptp_clock, 0); 351 352 return ret; 353 } 354 355 static u64 am65_cpts_gettime(struct am65_cpts *cpts, 356 struct ptp_system_timestamp *sts) 357 { 358 unsigned long flags; 359 u64 val = 0; 360 361 /* temporarily disable cpts interrupt to avoid intentional 362 * doubled read. Interrupt can be in-flight - it's Ok. 363 */ 364 am65_cpts_write32(cpts, 0, int_enable); 365 366 /* use spin_lock_irqsave() here as it has to run very fast */ 367 spin_lock_irqsave(&cpts->lock, flags); 368 ptp_read_system_prets(sts); 369 am65_cpts_write32(cpts, AM65_CPTS_TS_PUSH, ts_push); 370 am65_cpts_read32(cpts, ts_push); 371 ptp_read_system_postts(sts); 372 spin_unlock_irqrestore(&cpts->lock, flags); 373 374 am65_cpts_fifo_read(cpts); 375 376 am65_cpts_write32(cpts, AM65_CPTS_INT_ENABLE_TS_PEND_EN, int_enable); 377 378 val = cpts->timestamp; 379 380 return val; 381 } 382 383 static irqreturn_t am65_cpts_interrupt(int irq, void *dev_id) 384 { 385 struct am65_cpts *cpts = dev_id; 386 387 if (am65_cpts_fifo_read(cpts)) 388 dev_dbg(cpts->dev, "cpts: unable to obtain a time stamp\n"); 389 390 return IRQ_HANDLED; 391 } 392 393 /* PTP clock operations */ 394 static int am65_cpts_ptp_adjfreq(struct ptp_clock_info *ptp, s32 ppb) 395 { 396 struct am65_cpts *cpts = container_of(ptp, struct am65_cpts, ptp_info); 397 int neg_adj = 0; 398 u64 adj_period; 399 u32 val; 400 401 if (ppb < 0) { 402 neg_adj = 1; 403 ppb = -ppb; 404 } 405 406 /* base freq = 1GHz = 1 000 000 000 407 * ppb_norm = ppb * base_freq / clock_freq; 408 * ppm_norm = ppb_norm / 1000 409 * adj_period = 1 000 000 / ppm_norm 410 * adj_period = 1 000 000 000 / ppb_norm 411 * adj_period = 1 000 000 000 / (ppb * base_freq / clock_freq) 412 * adj_period = (1 000 000 000 * clock_freq) / (ppb * base_freq) 413 * adj_period = clock_freq / ppb 414 */ 415 adj_period = div_u64(cpts->refclk_freq, ppb); 416 417 mutex_lock(&cpts->ptp_clk_lock); 418 419 val = am65_cpts_read32(cpts, control); 420 if (neg_adj) 421 val |= AM65_CPTS_CONTROL_TS_PPM_DIR; 422 else 423 val &= ~AM65_CPTS_CONTROL_TS_PPM_DIR; 424 am65_cpts_write32(cpts, val, control); 425 426 val = upper_32_bits(adj_period) & 0x3FF; 427 am65_cpts_write32(cpts, val, ts_ppm_hi); 428 val = lower_32_bits(adj_period); 429 am65_cpts_write32(cpts, val, ts_ppm_low); 430 431 mutex_unlock(&cpts->ptp_clk_lock); 432 433 return 0; 434 } 435 436 static int am65_cpts_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta) 437 { 438 struct am65_cpts *cpts = container_of(ptp, struct am65_cpts, ptp_info); 439 s64 ns; 440 441 mutex_lock(&cpts->ptp_clk_lock); 442 ns = am65_cpts_gettime(cpts, NULL); 443 ns += delta; 444 am65_cpts_settime(cpts, ns); 445 mutex_unlock(&cpts->ptp_clk_lock); 446 447 return 0; 448 } 449 450 static int am65_cpts_ptp_gettimex(struct ptp_clock_info *ptp, 451 struct timespec64 *ts, 452 struct ptp_system_timestamp *sts) 453 { 454 struct am65_cpts *cpts = container_of(ptp, struct am65_cpts, ptp_info); 455 u64 ns; 456 457 mutex_lock(&cpts->ptp_clk_lock); 458 ns = am65_cpts_gettime(cpts, sts); 459 mutex_unlock(&cpts->ptp_clk_lock); 460 *ts = ns_to_timespec64(ns); 461 462 return 0; 463 } 464 465 u64 am65_cpts_ns_gettime(struct am65_cpts *cpts) 466 { 467 u64 ns; 468 469 /* reuse ptp_clk_lock as it serialize ts push */ 470 mutex_lock(&cpts->ptp_clk_lock); 471 ns = am65_cpts_gettime(cpts, NULL); 472 mutex_unlock(&cpts->ptp_clk_lock); 473 474 return ns; 475 } 476 EXPORT_SYMBOL_GPL(am65_cpts_ns_gettime); 477 478 static int am65_cpts_ptp_settime(struct ptp_clock_info *ptp, 479 const struct timespec64 *ts) 480 { 481 struct am65_cpts *cpts = container_of(ptp, struct am65_cpts, ptp_info); 482 u64 ns; 483 484 ns = timespec64_to_ns(ts); 485 mutex_lock(&cpts->ptp_clk_lock); 486 am65_cpts_settime(cpts, ns); 487 mutex_unlock(&cpts->ptp_clk_lock); 488 489 return 0; 490 } 491 492 static void am65_cpts_extts_enable_hw(struct am65_cpts *cpts, u32 index, int on) 493 { 494 u32 v; 495 496 v = am65_cpts_read32(cpts, control); 497 if (on) { 498 v |= BIT(AM65_CPTS_CONTROL_HW1_TS_PUSH_OFFSET + index); 499 cpts->hw_ts_enable |= BIT(index); 500 } else { 501 v &= ~BIT(AM65_CPTS_CONTROL_HW1_TS_PUSH_OFFSET + index); 502 cpts->hw_ts_enable &= ~BIT(index); 503 } 504 am65_cpts_write32(cpts, v, control); 505 } 506 507 static int am65_cpts_extts_enable(struct am65_cpts *cpts, u32 index, int on) 508 { 509 if (!!(cpts->hw_ts_enable & BIT(index)) == !!on) 510 return 0; 511 512 mutex_lock(&cpts->ptp_clk_lock); 513 am65_cpts_extts_enable_hw(cpts, index, on); 514 mutex_unlock(&cpts->ptp_clk_lock); 515 516 dev_dbg(cpts->dev, "%s: ExtTS:%u %s\n", 517 __func__, index, on ? "enabled" : "disabled"); 518 519 return 0; 520 } 521 522 int am65_cpts_estf_enable(struct am65_cpts *cpts, int idx, 523 struct am65_cpts_estf_cfg *cfg) 524 { 525 u64 cycles; 526 u32 val; 527 528 cycles = cfg->ns_period * cpts->refclk_freq; 529 cycles = DIV_ROUND_UP(cycles, NSEC_PER_SEC); 530 if (cycles > U32_MAX) 531 return -EINVAL; 532 533 /* according to TRM should be zeroed */ 534 am65_cpts_write32(cpts, 0, estf[idx].length); 535 536 val = upper_32_bits(cfg->ns_start); 537 am65_cpts_write32(cpts, val, estf[idx].comp_hi); 538 val = lower_32_bits(cfg->ns_start); 539 am65_cpts_write32(cpts, val, estf[idx].comp_lo); 540 val = lower_32_bits(cycles); 541 am65_cpts_write32(cpts, val, estf[idx].length); 542 543 dev_dbg(cpts->dev, "%s: ESTF:%u enabled\n", __func__, idx); 544 545 return 0; 546 } 547 EXPORT_SYMBOL_GPL(am65_cpts_estf_enable); 548 549 void am65_cpts_estf_disable(struct am65_cpts *cpts, int idx) 550 { 551 am65_cpts_write32(cpts, 0, estf[idx].length); 552 553 dev_dbg(cpts->dev, "%s: ESTF:%u disabled\n", __func__, idx); 554 } 555 EXPORT_SYMBOL_GPL(am65_cpts_estf_disable); 556 557 static void am65_cpts_perout_enable_hw(struct am65_cpts *cpts, 558 struct ptp_perout_request *req, int on) 559 { 560 u64 ns_period, ns_start, cycles; 561 struct timespec64 ts; 562 u32 val; 563 564 if (on) { 565 ts.tv_sec = req->period.sec; 566 ts.tv_nsec = req->period.nsec; 567 ns_period = timespec64_to_ns(&ts); 568 569 cycles = (ns_period * cpts->refclk_freq) / NSEC_PER_SEC; 570 571 ts.tv_sec = req->start.sec; 572 ts.tv_nsec = req->start.nsec; 573 ns_start = timespec64_to_ns(&ts); 574 575 val = upper_32_bits(ns_start); 576 am65_cpts_write32(cpts, val, genf[req->index].comp_hi); 577 val = lower_32_bits(ns_start); 578 am65_cpts_write32(cpts, val, genf[req->index].comp_lo); 579 val = lower_32_bits(cycles); 580 am65_cpts_write32(cpts, val, genf[req->index].length); 581 582 cpts->genf_enable |= BIT(req->index); 583 } else { 584 am65_cpts_write32(cpts, 0, genf[req->index].length); 585 586 cpts->genf_enable &= ~BIT(req->index); 587 } 588 } 589 590 static int am65_cpts_perout_enable(struct am65_cpts *cpts, 591 struct ptp_perout_request *req, int on) 592 { 593 if (!!(cpts->genf_enable & BIT(req->index)) == !!on) 594 return 0; 595 596 mutex_lock(&cpts->ptp_clk_lock); 597 am65_cpts_perout_enable_hw(cpts, req, on); 598 mutex_unlock(&cpts->ptp_clk_lock); 599 600 dev_dbg(cpts->dev, "%s: GenF:%u %s\n", 601 __func__, req->index, on ? "enabled" : "disabled"); 602 603 return 0; 604 } 605 606 static int am65_cpts_ptp_enable(struct ptp_clock_info *ptp, 607 struct ptp_clock_request *rq, int on) 608 { 609 struct am65_cpts *cpts = container_of(ptp, struct am65_cpts, ptp_info); 610 611 switch (rq->type) { 612 case PTP_CLK_REQ_EXTTS: 613 return am65_cpts_extts_enable(cpts, rq->extts.index, on); 614 case PTP_CLK_REQ_PEROUT: 615 return am65_cpts_perout_enable(cpts, &rq->perout, on); 616 default: 617 break; 618 } 619 620 return -EOPNOTSUPP; 621 } 622 623 static long am65_cpts_ts_work(struct ptp_clock_info *ptp); 624 625 static struct ptp_clock_info am65_ptp_info = { 626 .owner = THIS_MODULE, 627 .name = "CTPS timer", 628 .adjfreq = am65_cpts_ptp_adjfreq, 629 .adjtime = am65_cpts_ptp_adjtime, 630 .gettimex64 = am65_cpts_ptp_gettimex, 631 .settime64 = am65_cpts_ptp_settime, 632 .enable = am65_cpts_ptp_enable, 633 .do_aux_work = am65_cpts_ts_work, 634 }; 635 636 static bool am65_cpts_match_tx_ts(struct am65_cpts *cpts, 637 struct am65_cpts_event *event) 638 { 639 struct sk_buff_head txq_list; 640 struct sk_buff *skb, *tmp; 641 unsigned long flags; 642 bool found = false; 643 u32 mtype_seqid; 644 645 mtype_seqid = event->event1 & 646 (AM65_CPTS_EVENT_1_MESSAGE_TYPE_MASK | 647 AM65_CPTS_EVENT_1_EVENT_TYPE_MASK | 648 AM65_CPTS_EVENT_1_SEQUENCE_ID_MASK); 649 650 __skb_queue_head_init(&txq_list); 651 652 spin_lock_irqsave(&cpts->txq.lock, flags); 653 skb_queue_splice_init(&cpts->txq, &txq_list); 654 spin_unlock_irqrestore(&cpts->txq.lock, flags); 655 656 /* no need to grab txq.lock as access is always done under cpts->lock */ 657 skb_queue_walk_safe(&txq_list, skb, tmp) { 658 struct skb_shared_hwtstamps ssh; 659 struct am65_cpts_skb_cb_data *skb_cb = 660 (struct am65_cpts_skb_cb_data *)skb->cb; 661 662 if (mtype_seqid == skb_cb->skb_mtype_seqid) { 663 u64 ns = event->timestamp; 664 665 memset(&ssh, 0, sizeof(ssh)); 666 ssh.hwtstamp = ns_to_ktime(ns); 667 skb_tstamp_tx(skb, &ssh); 668 found = true; 669 __skb_unlink(skb, &txq_list); 670 dev_consume_skb_any(skb); 671 dev_dbg(cpts->dev, 672 "match tx timestamp mtype_seqid %08x\n", 673 mtype_seqid); 674 break; 675 } 676 677 if (time_after(jiffies, skb_cb->tmo)) { 678 /* timeout any expired skbs over 100 ms */ 679 dev_dbg(cpts->dev, 680 "expiring tx timestamp mtype_seqid %08x\n", 681 mtype_seqid); 682 __skb_unlink(skb, &txq_list); 683 dev_consume_skb_any(skb); 684 } 685 } 686 687 spin_lock_irqsave(&cpts->txq.lock, flags); 688 skb_queue_splice(&txq_list, &cpts->txq); 689 spin_unlock_irqrestore(&cpts->txq.lock, flags); 690 691 return found; 692 } 693 694 static void am65_cpts_find_ts(struct am65_cpts *cpts) 695 { 696 struct am65_cpts_event *event; 697 struct list_head *this, *next; 698 LIST_HEAD(events_free); 699 unsigned long flags; 700 LIST_HEAD(events); 701 702 spin_lock_irqsave(&cpts->lock, flags); 703 list_splice_init(&cpts->events, &events); 704 spin_unlock_irqrestore(&cpts->lock, flags); 705 706 list_for_each_safe(this, next, &events) { 707 event = list_entry(this, struct am65_cpts_event, list); 708 if (am65_cpts_match_tx_ts(cpts, event) || 709 time_after(jiffies, event->tmo)) { 710 list_del_init(&event->list); 711 list_add(&event->list, &events_free); 712 } 713 } 714 715 spin_lock_irqsave(&cpts->lock, flags); 716 list_splice_tail(&events, &cpts->events); 717 list_splice_tail(&events_free, &cpts->pool); 718 spin_unlock_irqrestore(&cpts->lock, flags); 719 } 720 721 static long am65_cpts_ts_work(struct ptp_clock_info *ptp) 722 { 723 struct am65_cpts *cpts = container_of(ptp, struct am65_cpts, ptp_info); 724 unsigned long flags; 725 long delay = -1; 726 727 am65_cpts_find_ts(cpts); 728 729 spin_lock_irqsave(&cpts->txq.lock, flags); 730 if (!skb_queue_empty(&cpts->txq)) 731 delay = AM65_CPTS_SKB_TX_WORK_TIMEOUT; 732 spin_unlock_irqrestore(&cpts->txq.lock, flags); 733 734 return delay; 735 } 736 737 /** 738 * am65_cpts_rx_enable - enable rx timestamping 739 * @cpts: cpts handle 740 * @en: enable 741 * 742 * This functions enables rx packets timestamping. The CPTS can timestamp all 743 * rx packets. 744 */ 745 void am65_cpts_rx_enable(struct am65_cpts *cpts, bool en) 746 { 747 u32 val; 748 749 mutex_lock(&cpts->ptp_clk_lock); 750 val = am65_cpts_read32(cpts, control); 751 if (en) 752 val |= AM65_CPTS_CONTROL_TSTAMP_EN; 753 else 754 val &= ~AM65_CPTS_CONTROL_TSTAMP_EN; 755 am65_cpts_write32(cpts, val, control); 756 mutex_unlock(&cpts->ptp_clk_lock); 757 } 758 EXPORT_SYMBOL_GPL(am65_cpts_rx_enable); 759 760 static int am65_skb_get_mtype_seqid(struct sk_buff *skb, u32 *mtype_seqid) 761 { 762 unsigned int ptp_class = ptp_classify_raw(skb); 763 struct ptp_header *hdr; 764 u8 msgtype; 765 u16 seqid; 766 767 if (ptp_class == PTP_CLASS_NONE) 768 return 0; 769 770 hdr = ptp_parse_header(skb, ptp_class); 771 if (!hdr) 772 return 0; 773 774 msgtype = ptp_get_msgtype(hdr, ptp_class); 775 seqid = ntohs(hdr->sequence_id); 776 777 *mtype_seqid = (msgtype << AM65_CPTS_EVENT_1_MESSAGE_TYPE_SHIFT) & 778 AM65_CPTS_EVENT_1_MESSAGE_TYPE_MASK; 779 *mtype_seqid |= (seqid & AM65_CPTS_EVENT_1_SEQUENCE_ID_MASK); 780 781 return 1; 782 } 783 784 /** 785 * am65_cpts_tx_timestamp - save tx packet for timestamping 786 * @cpts: cpts handle 787 * @skb: packet 788 * 789 * This functions saves tx packet for timestamping if packet can be timestamped. 790 * The future processing is done in from PTP auxiliary worker. 791 */ 792 void am65_cpts_tx_timestamp(struct am65_cpts *cpts, struct sk_buff *skb) 793 { 794 struct am65_cpts_skb_cb_data *skb_cb = (void *)skb->cb; 795 796 if (!(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)) 797 return; 798 799 /* add frame to queue for processing later. 800 * The periodic FIFO check will handle this. 801 */ 802 skb_get(skb); 803 /* get the timestamp for timeouts */ 804 skb_cb->tmo = jiffies + msecs_to_jiffies(100); 805 skb_queue_tail(&cpts->txq, skb); 806 ptp_schedule_worker(cpts->ptp_clock, 0); 807 } 808 EXPORT_SYMBOL_GPL(am65_cpts_tx_timestamp); 809 810 /** 811 * am65_cpts_prep_tx_timestamp - check and prepare tx packet for timestamping 812 * @cpts: cpts handle 813 * @skb: packet 814 * 815 * This functions should be called from .xmit(). 816 * It checks if packet can be timestamped, fills internal cpts data 817 * in skb-cb and marks packet as SKBTX_IN_PROGRESS. 818 */ 819 void am65_cpts_prep_tx_timestamp(struct am65_cpts *cpts, struct sk_buff *skb) 820 { 821 struct am65_cpts_skb_cb_data *skb_cb = (void *)skb->cb; 822 int ret; 823 824 if (!(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) 825 return; 826 827 ret = am65_skb_get_mtype_seqid(skb, &skb_cb->skb_mtype_seqid); 828 if (!ret) 829 return; 830 skb_cb->skb_mtype_seqid |= (AM65_CPTS_EV_TX << 831 AM65_CPTS_EVENT_1_EVENT_TYPE_SHIFT); 832 833 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 834 } 835 EXPORT_SYMBOL_GPL(am65_cpts_prep_tx_timestamp); 836 837 int am65_cpts_phc_index(struct am65_cpts *cpts) 838 { 839 return cpts->phc_index; 840 } 841 EXPORT_SYMBOL_GPL(am65_cpts_phc_index); 842 843 static void cpts_free_clk_mux(void *data) 844 { 845 struct am65_cpts *cpts = data; 846 847 of_clk_del_provider(cpts->clk_mux_np); 848 clk_hw_unregister_mux(cpts->clk_mux_hw); 849 of_node_put(cpts->clk_mux_np); 850 } 851 852 static int cpts_of_mux_clk_setup(struct am65_cpts *cpts, 853 struct device_node *node) 854 { 855 unsigned int num_parents; 856 const char **parent_names; 857 char *clk_mux_name; 858 void __iomem *reg; 859 int ret = -EINVAL; 860 861 cpts->clk_mux_np = of_get_child_by_name(node, "refclk-mux"); 862 if (!cpts->clk_mux_np) 863 return 0; 864 865 num_parents = of_clk_get_parent_count(cpts->clk_mux_np); 866 if (num_parents < 1) { 867 dev_err(cpts->dev, "mux-clock %pOF must have parents\n", 868 cpts->clk_mux_np); 869 goto mux_fail; 870 } 871 872 parent_names = devm_kcalloc(cpts->dev, sizeof(char *), num_parents, 873 GFP_KERNEL); 874 if (!parent_names) { 875 ret = -ENOMEM; 876 goto mux_fail; 877 } 878 879 of_clk_parent_fill(cpts->clk_mux_np, parent_names, num_parents); 880 881 clk_mux_name = devm_kasprintf(cpts->dev, GFP_KERNEL, "%s.%pOFn", 882 dev_name(cpts->dev), cpts->clk_mux_np); 883 if (!clk_mux_name) { 884 ret = -ENOMEM; 885 goto mux_fail; 886 } 887 888 reg = &cpts->reg->rftclk_sel; 889 /* dev must be NULL to avoid recursive incrementing 890 * of module refcnt 891 */ 892 cpts->clk_mux_hw = clk_hw_register_mux(NULL, clk_mux_name, 893 parent_names, num_parents, 894 0, reg, 0, 5, 0, NULL); 895 if (IS_ERR(cpts->clk_mux_hw)) { 896 ret = PTR_ERR(cpts->clk_mux_hw); 897 goto mux_fail; 898 } 899 900 ret = of_clk_add_hw_provider(cpts->clk_mux_np, of_clk_hw_simple_get, 901 cpts->clk_mux_hw); 902 if (ret) 903 goto clk_hw_register; 904 905 ret = devm_add_action_or_reset(cpts->dev, cpts_free_clk_mux, cpts); 906 if (ret) 907 dev_err(cpts->dev, "failed to add clkmux reset action %d", ret); 908 909 return ret; 910 911 clk_hw_register: 912 clk_hw_unregister_mux(cpts->clk_mux_hw); 913 mux_fail: 914 of_node_put(cpts->clk_mux_np); 915 return ret; 916 } 917 918 static int am65_cpts_of_parse(struct am65_cpts *cpts, struct device_node *node) 919 { 920 u32 prop[2]; 921 922 if (!of_property_read_u32(node, "ti,cpts-ext-ts-inputs", &prop[0])) 923 cpts->ext_ts_inputs = prop[0]; 924 925 if (!of_property_read_u32(node, "ti,cpts-periodic-outputs", &prop[0])) 926 cpts->genf_num = prop[0]; 927 928 return cpts_of_mux_clk_setup(cpts, node); 929 } 930 931 static void am65_cpts_release(void *data) 932 { 933 struct am65_cpts *cpts = data; 934 935 ptp_clock_unregister(cpts->ptp_clock); 936 am65_cpts_disable(cpts); 937 clk_disable_unprepare(cpts->refclk); 938 } 939 940 struct am65_cpts *am65_cpts_create(struct device *dev, void __iomem *regs, 941 struct device_node *node) 942 { 943 struct am65_cpts *cpts; 944 int ret, i; 945 946 cpts = devm_kzalloc(dev, sizeof(*cpts), GFP_KERNEL); 947 if (!cpts) 948 return ERR_PTR(-ENOMEM); 949 950 cpts->dev = dev; 951 cpts->reg = (struct am65_cpts_regs __iomem *)regs; 952 953 cpts->irq = of_irq_get_byname(node, "cpts"); 954 if (cpts->irq <= 0) { 955 ret = cpts->irq ?: -ENXIO; 956 dev_err_probe(dev, ret, "Failed to get IRQ number\n"); 957 return ERR_PTR(ret); 958 } 959 960 ret = am65_cpts_of_parse(cpts, node); 961 if (ret) 962 return ERR_PTR(ret); 963 964 mutex_init(&cpts->ptp_clk_lock); 965 INIT_LIST_HEAD(&cpts->events); 966 INIT_LIST_HEAD(&cpts->pool); 967 spin_lock_init(&cpts->lock); 968 skb_queue_head_init(&cpts->txq); 969 970 for (i = 0; i < AM65_CPTS_MAX_EVENTS; i++) 971 list_add(&cpts->pool_data[i].list, &cpts->pool); 972 973 cpts->refclk = devm_get_clk_from_child(dev, node, "cpts"); 974 if (IS_ERR(cpts->refclk)) { 975 ret = PTR_ERR(cpts->refclk); 976 dev_err_probe(dev, ret, "Failed to get refclk\n"); 977 return ERR_PTR(ret); 978 } 979 980 ret = clk_prepare_enable(cpts->refclk); 981 if (ret) { 982 dev_err(dev, "Failed to enable refclk %d\n", ret); 983 return ERR_PTR(ret); 984 } 985 986 cpts->refclk_freq = clk_get_rate(cpts->refclk); 987 988 am65_ptp_info.max_adj = cpts->refclk_freq / AM65_CPTS_MIN_PPM; 989 cpts->ptp_info = am65_ptp_info; 990 991 if (cpts->ext_ts_inputs) 992 cpts->ptp_info.n_ext_ts = cpts->ext_ts_inputs; 993 if (cpts->genf_num) 994 cpts->ptp_info.n_per_out = cpts->genf_num; 995 996 am65_cpts_set_add_val(cpts); 997 998 am65_cpts_write32(cpts, AM65_CPTS_CONTROL_EN | 999 AM65_CPTS_CONTROL_64MODE | 1000 AM65_CPTS_CONTROL_TX_GENF_CLR_EN, 1001 control); 1002 am65_cpts_write32(cpts, AM65_CPTS_INT_ENABLE_TS_PEND_EN, int_enable); 1003 1004 /* set time to the current system time */ 1005 am65_cpts_settime(cpts, ktime_to_ns(ktime_get_real())); 1006 1007 cpts->ptp_clock = ptp_clock_register(&cpts->ptp_info, cpts->dev); 1008 if (IS_ERR_OR_NULL(cpts->ptp_clock)) { 1009 dev_err(dev, "Failed to register ptp clk %ld\n", 1010 PTR_ERR(cpts->ptp_clock)); 1011 ret = cpts->ptp_clock ? PTR_ERR(cpts->ptp_clock) : -ENODEV; 1012 goto refclk_disable; 1013 } 1014 cpts->phc_index = ptp_clock_index(cpts->ptp_clock); 1015 1016 ret = devm_add_action_or_reset(dev, am65_cpts_release, cpts); 1017 if (ret) { 1018 dev_err(dev, "failed to add ptpclk reset action %d", ret); 1019 return ERR_PTR(ret); 1020 } 1021 1022 ret = devm_request_threaded_irq(dev, cpts->irq, NULL, 1023 am65_cpts_interrupt, 1024 IRQF_ONESHOT, dev_name(dev), cpts); 1025 if (ret < 0) { 1026 dev_err(cpts->dev, "error attaching irq %d\n", ret); 1027 return ERR_PTR(ret); 1028 } 1029 1030 dev_info(dev, "CPTS ver 0x%08x, freq:%u, add_val:%u\n", 1031 am65_cpts_read32(cpts, idver), 1032 cpts->refclk_freq, cpts->ts_add_val); 1033 1034 return cpts; 1035 1036 refclk_disable: 1037 clk_disable_unprepare(cpts->refclk); 1038 return ERR_PTR(ret); 1039 } 1040 EXPORT_SYMBOL_GPL(am65_cpts_create); 1041 1042 void am65_cpts_suspend(struct am65_cpts *cpts) 1043 { 1044 /* save state and disable CPTS */ 1045 cpts->sr_control = am65_cpts_read32(cpts, control); 1046 cpts->sr_int_enable = am65_cpts_read32(cpts, int_enable); 1047 cpts->sr_rftclk_sel = am65_cpts_read32(cpts, rftclk_sel); 1048 cpts->sr_ts_ppm_hi = am65_cpts_read32(cpts, ts_ppm_hi); 1049 cpts->sr_ts_ppm_low = am65_cpts_read32(cpts, ts_ppm_low); 1050 cpts->sr_cpts_ns = am65_cpts_gettime(cpts, NULL); 1051 cpts->sr_ktime_ns = ktime_to_ns(ktime_get_real()); 1052 am65_cpts_disable(cpts); 1053 clk_disable(cpts->refclk); 1054 1055 /* Save GENF state */ 1056 memcpy_fromio(&cpts->sr_genf, &cpts->reg->genf, sizeof(cpts->sr_genf)); 1057 1058 /* Save ESTF state */ 1059 memcpy_fromio(&cpts->sr_estf, &cpts->reg->estf, sizeof(cpts->sr_estf)); 1060 } 1061 EXPORT_SYMBOL_GPL(am65_cpts_suspend); 1062 1063 void am65_cpts_resume(struct am65_cpts *cpts) 1064 { 1065 int i; 1066 s64 ktime_ns; 1067 1068 /* restore state and enable CPTS */ 1069 clk_enable(cpts->refclk); 1070 am65_cpts_write32(cpts, cpts->sr_rftclk_sel, rftclk_sel); 1071 am65_cpts_set_add_val(cpts); 1072 am65_cpts_write32(cpts, cpts->sr_control, control); 1073 am65_cpts_write32(cpts, cpts->sr_int_enable, int_enable); 1074 1075 /* Restore time to saved CPTS time + time in suspend/resume */ 1076 ktime_ns = ktime_to_ns(ktime_get_real()); 1077 ktime_ns -= cpts->sr_ktime_ns; 1078 am65_cpts_settime(cpts, cpts->sr_cpts_ns + ktime_ns); 1079 1080 /* Restore compensation (PPM) */ 1081 am65_cpts_write32(cpts, cpts->sr_ts_ppm_hi, ts_ppm_hi); 1082 am65_cpts_write32(cpts, cpts->sr_ts_ppm_low, ts_ppm_low); 1083 1084 /* Restore GENF state */ 1085 for (i = 0; i < AM65_CPTS_GENF_MAX_NUM; i++) { 1086 am65_cpts_write32(cpts, 0, genf[i].length); /* TRM sequence */ 1087 am65_cpts_write32(cpts, cpts->sr_genf[i].comp_hi, genf[i].comp_hi); 1088 am65_cpts_write32(cpts, cpts->sr_genf[i].comp_lo, genf[i].comp_lo); 1089 am65_cpts_write32(cpts, cpts->sr_genf[i].length, genf[i].length); 1090 am65_cpts_write32(cpts, cpts->sr_genf[i].control, genf[i].control); 1091 am65_cpts_write32(cpts, cpts->sr_genf[i].ppm_hi, genf[i].ppm_hi); 1092 am65_cpts_write32(cpts, cpts->sr_genf[i].ppm_low, genf[i].ppm_low); 1093 } 1094 1095 /* Restore ESTTF state */ 1096 for (i = 0; i < AM65_CPTS_ESTF_MAX_NUM; i++) { 1097 am65_cpts_write32(cpts, 0, estf[i].length); /* TRM sequence */ 1098 am65_cpts_write32(cpts, cpts->sr_estf[i].comp_hi, estf[i].comp_hi); 1099 am65_cpts_write32(cpts, cpts->sr_estf[i].comp_lo, estf[i].comp_lo); 1100 am65_cpts_write32(cpts, cpts->sr_estf[i].length, estf[i].length); 1101 am65_cpts_write32(cpts, cpts->sr_estf[i].control, estf[i].control); 1102 am65_cpts_write32(cpts, cpts->sr_estf[i].ppm_hi, estf[i].ppm_hi); 1103 am65_cpts_write32(cpts, cpts->sr_estf[i].ppm_low, estf[i].ppm_low); 1104 } 1105 } 1106 EXPORT_SYMBOL_GPL(am65_cpts_resume); 1107 1108 static int am65_cpts_probe(struct platform_device *pdev) 1109 { 1110 struct device_node *node = pdev->dev.of_node; 1111 struct device *dev = &pdev->dev; 1112 struct am65_cpts *cpts; 1113 void __iomem *base; 1114 1115 base = devm_platform_ioremap_resource_byname(pdev, "cpts"); 1116 if (IS_ERR(base)) 1117 return PTR_ERR(base); 1118 1119 cpts = am65_cpts_create(dev, base, node); 1120 return PTR_ERR_OR_ZERO(cpts); 1121 } 1122 1123 static const struct of_device_id am65_cpts_of_match[] = { 1124 { .compatible = "ti,am65-cpts", }, 1125 { .compatible = "ti,j721e-cpts", }, 1126 {}, 1127 }; 1128 MODULE_DEVICE_TABLE(of, am65_cpts_of_match); 1129 1130 static struct platform_driver am65_cpts_driver = { 1131 .probe = am65_cpts_probe, 1132 .driver = { 1133 .name = "am65-cpts", 1134 .of_match_table = am65_cpts_of_match, 1135 }, 1136 }; 1137 module_platform_driver(am65_cpts_driver); 1138 1139 MODULE_LICENSE("GPL v2"); 1140 MODULE_AUTHOR("Grygorii Strashko <grygorii.strashko@ti.com>"); 1141 MODULE_DESCRIPTION("TI K3 AM65 CPTS driver"); 1142