1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/ 3 * 4 */ 5 6 #ifndef AM65_CPSW_NUSS_H_ 7 #define AM65_CPSW_NUSS_H_ 8 9 #include <linux/kernel.h> 10 #include <linux/module.h> 11 #include <linux/netdevice.h> 12 #include <linux/phy.h> 13 #include <linux/platform_device.h> 14 #include <linux/soc/ti/k3-ringacc.h> 15 #include "am65-cpsw-qos.h" 16 17 struct am65_cpts; 18 19 #define HOST_PORT_NUM 0 20 21 #define AM65_CPSW_MAX_TX_QUEUES 8 22 #define AM65_CPSW_MAX_RX_QUEUES 1 23 #define AM65_CPSW_MAX_RX_FLOWS 1 24 25 struct am65_cpsw_slave_data { 26 bool mac_only; 27 struct cpsw_sl *mac_sl; 28 struct device_node *phy_node; 29 struct phy_device *phy; 30 phy_interface_t phy_if; 31 struct phy *ifphy; 32 bool rx_pause; 33 bool tx_pause; 34 u8 mac_addr[ETH_ALEN]; 35 }; 36 37 struct am65_cpsw_port { 38 struct am65_cpsw_common *common; 39 struct net_device *ndev; 40 const char *name; 41 u32 port_id; 42 void __iomem *port_base; 43 void __iomem *stat_base; 44 void __iomem *fetch_ram_base; 45 bool disabled; 46 struct am65_cpsw_slave_data slave; 47 bool tx_ts_enabled; 48 bool rx_ts_enabled; 49 struct am65_cpsw_qos qos; 50 }; 51 52 struct am65_cpsw_host { 53 struct am65_cpsw_common *common; 54 void __iomem *port_base; 55 void __iomem *stat_base; 56 }; 57 58 struct am65_cpsw_tx_chn { 59 struct napi_struct napi_tx; 60 struct am65_cpsw_common *common; 61 struct k3_cppi_desc_pool *desc_pool; 62 struct k3_udma_glue_tx_channel *tx_chn; 63 spinlock_t lock; /* protect TX rings in multi-port mode */ 64 int irq; 65 u32 id; 66 u32 descs_num; 67 char tx_chn_name[128]; 68 }; 69 70 struct am65_cpsw_rx_chn { 71 struct device *dev; 72 struct k3_cppi_desc_pool *desc_pool; 73 struct k3_udma_glue_rx_channel *rx_chn; 74 u32 descs_num; 75 int irq; 76 }; 77 78 #define AM65_CPSW_QUIRK_I2027_NO_TX_CSUM BIT(0) 79 80 struct am65_cpsw_pdata { 81 u32 quirks; 82 enum k3_ring_mode fdqring_mode; 83 const char *ale_dev_id; 84 }; 85 86 struct am65_cpsw_common { 87 struct device *dev; 88 struct device *mdio_dev; 89 struct am65_cpsw_pdata pdata; 90 91 void __iomem *ss_base; 92 void __iomem *cpsw_base; 93 94 u32 port_num; 95 struct am65_cpsw_host host; 96 struct am65_cpsw_port *ports; 97 u32 disabled_ports_mask; 98 struct net_device *dma_ndev; 99 100 int usage_count; /* number of opened ports */ 101 struct cpsw_ale *ale; 102 int tx_ch_num; 103 u32 rx_flow_id_base; 104 105 struct am65_cpsw_tx_chn tx_chns[AM65_CPSW_MAX_TX_QUEUES]; 106 struct completion tdown_complete; 107 atomic_t tdown_cnt; 108 109 struct am65_cpsw_rx_chn rx_chns; 110 struct napi_struct napi_rx; 111 112 u32 nuss_ver; 113 u32 cpsw_ver; 114 unsigned long bus_freq; 115 bool pf_p0_rx_ptype_rrobin; 116 struct am65_cpts *cpts; 117 int est_enabled; 118 }; 119 120 struct am65_cpsw_ndev_stats { 121 u64 tx_packets; 122 u64 tx_bytes; 123 u64 rx_packets; 124 u64 rx_bytes; 125 struct u64_stats_sync syncp; 126 }; 127 128 struct am65_cpsw_ndev_priv { 129 u32 msg_enable; 130 struct am65_cpsw_port *port; 131 struct am65_cpsw_ndev_stats __percpu *stats; 132 }; 133 134 #define am65_ndev_to_priv(ndev) \ 135 ((struct am65_cpsw_ndev_priv *)netdev_priv(ndev)) 136 #define am65_ndev_to_port(ndev) (am65_ndev_to_priv(ndev)->port) 137 #define am65_ndev_to_common(ndev) (am65_ndev_to_port(ndev)->common) 138 #define am65_ndev_to_slave(ndev) (&am65_ndev_to_port(ndev)->slave) 139 140 #define am65_common_get_host(common) (&(common)->host) 141 #define am65_common_get_port(common, id) (&(common)->ports[(id) - 1]) 142 143 #define am65_cpsw_napi_to_common(pnapi) \ 144 container_of(pnapi, struct am65_cpsw_common, napi_rx) 145 #define am65_cpsw_napi_to_tx_chn(pnapi) \ 146 container_of(pnapi, struct am65_cpsw_tx_chn, napi_tx) 147 148 #define AM65_CPSW_DRV_NAME "am65-cpsw-nuss" 149 150 #define AM65_CPSW_IS_CPSW2G(common) ((common)->port_num == 1) 151 152 extern const struct ethtool_ops am65_cpsw_ethtool_ops_slave; 153 154 void am65_cpsw_nuss_adjust_link(struct net_device *ndev); 155 void am65_cpsw_nuss_set_p0_ptype(struct am65_cpsw_common *common); 156 void am65_cpsw_nuss_remove_tx_chns(struct am65_cpsw_common *common); 157 int am65_cpsw_nuss_update_tx_chns(struct am65_cpsw_common *common, int num_tx); 158 159 #endif /* AM65_CPSW_NUSS_H_ */ 160