1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
3  *
4  */
5 
6 #ifndef AM65_CPSW_NUSS_H_
7 #define AM65_CPSW_NUSS_H_
8 
9 #include <linux/if_ether.h>
10 #include <linux/kernel.h>
11 #include <linux/module.h>
12 #include <linux/netdevice.h>
13 #include <linux/phylink.h>
14 #include <linux/platform_device.h>
15 #include <linux/soc/ti/k3-ringacc.h>
16 #include <net/devlink.h>
17 #include "am65-cpsw-qos.h"
18 
19 struct am65_cpts;
20 
21 #define HOST_PORT_NUM		0
22 
23 #define AM65_CPSW_MAX_TX_QUEUES	8
24 #define AM65_CPSW_MAX_RX_QUEUES	1
25 #define AM65_CPSW_MAX_RX_FLOWS	1
26 
27 #define AM65_CPSW_PORT_VLAN_REG_OFFSET	0x014
28 
29 struct am65_cpsw_slave_data {
30 	bool				mac_only;
31 	struct cpsw_sl			*mac_sl;
32 	struct device_node		*phy_node;
33 	phy_interface_t			phy_if;
34 	struct phy			*ifphy;
35 	bool				rx_pause;
36 	bool				tx_pause;
37 	u8				mac_addr[ETH_ALEN];
38 	int				port_vlan;
39 	struct phylink			*phylink;
40 	struct phylink_config		phylink_config;
41 };
42 
43 struct am65_cpsw_port {
44 	struct am65_cpsw_common		*common;
45 	struct net_device		*ndev;
46 	const char			*name;
47 	u32				port_id;
48 	void __iomem			*port_base;
49 	void __iomem			*sgmii_base;
50 	void __iomem			*stat_base;
51 	void __iomem			*fetch_ram_base;
52 	bool				disabled;
53 	struct am65_cpsw_slave_data	slave;
54 	bool				tx_ts_enabled;
55 	bool				rx_ts_enabled;
56 	struct am65_cpsw_qos		qos;
57 	struct devlink_port		devlink_port;
58 };
59 
60 struct am65_cpsw_host {
61 	struct am65_cpsw_common		*common;
62 	void __iomem			*port_base;
63 	void __iomem			*stat_base;
64 };
65 
66 struct am65_cpsw_tx_chn {
67 	struct device *dma_dev;
68 	struct napi_struct napi_tx;
69 	struct am65_cpsw_common	*common;
70 	struct k3_cppi_desc_pool *desc_pool;
71 	struct k3_udma_glue_tx_channel *tx_chn;
72 	spinlock_t lock; /* protect TX rings in multi-port mode */
73 	int irq;
74 	u32 id;
75 	u32 descs_num;
76 	char tx_chn_name[128];
77 };
78 
79 struct am65_cpsw_rx_chn {
80 	struct device *dev;
81 	struct device *dma_dev;
82 	struct k3_cppi_desc_pool *desc_pool;
83 	struct k3_udma_glue_rx_channel *rx_chn;
84 	u32 descs_num;
85 	int irq;
86 };
87 
88 #define AM65_CPSW_QUIRK_I2027_NO_TX_CSUM BIT(0)
89 
90 struct am65_cpsw_pdata {
91 	u32	quirks;
92 	u64	extra_modes;
93 	enum k3_ring_mode fdqring_mode;
94 	const char	*ale_dev_id;
95 };
96 
97 enum cpsw_devlink_param_id {
98 	AM65_CPSW_DEVLINK_PARAM_ID_BASE = DEVLINK_PARAM_GENERIC_ID_MAX,
99 	AM65_CPSW_DL_PARAM_SWITCH_MODE,
100 };
101 
102 struct am65_cpsw_devlink {
103 	struct am65_cpsw_common *common;
104 };
105 
106 struct am65_cpsw_common {
107 	struct device		*dev;
108 	struct device		*mdio_dev;
109 	struct am65_cpsw_pdata	pdata;
110 
111 	void __iomem		*ss_base;
112 	void __iomem		*cpsw_base;
113 
114 	u32			port_num;
115 	struct am65_cpsw_host   host;
116 	struct am65_cpsw_port	*ports;
117 	u32			disabled_ports_mask;
118 	struct net_device	*dma_ndev;
119 
120 	int			usage_count; /* number of opened ports */
121 	struct cpsw_ale		*ale;
122 	int			tx_ch_num;
123 	u32			rx_flow_id_base;
124 
125 	struct am65_cpsw_tx_chn	tx_chns[AM65_CPSW_MAX_TX_QUEUES];
126 	struct completion	tdown_complete;
127 	atomic_t		tdown_cnt;
128 
129 	struct am65_cpsw_rx_chn	rx_chns;
130 	struct napi_struct	napi_rx;
131 
132 	bool			rx_irq_disabled;
133 
134 	u32			nuss_ver;
135 	u32			cpsw_ver;
136 	unsigned long		bus_freq;
137 	bool			pf_p0_rx_ptype_rrobin;
138 	struct am65_cpts	*cpts;
139 	int			est_enabled;
140 
141 	bool		is_emac_mode;
142 	u16			br_members;
143 	int			default_vlan;
144 	struct devlink *devlink;
145 	struct net_device *hw_bridge_dev;
146 	struct notifier_block am65_cpsw_netdevice_nb;
147 	unsigned char switch_id[MAX_PHYS_ITEM_ID_LEN];
148 };
149 
150 struct am65_cpsw_ndev_stats {
151 	u64 tx_packets;
152 	u64 tx_bytes;
153 	u64 rx_packets;
154 	u64 rx_bytes;
155 	struct u64_stats_sync syncp;
156 };
157 
158 struct am65_cpsw_ndev_priv {
159 	u32			msg_enable;
160 	struct am65_cpsw_port	*port;
161 	struct am65_cpsw_ndev_stats __percpu *stats;
162 	bool offload_fwd_mark;
163 };
164 
165 #define am65_ndev_to_priv(ndev) \
166 	((struct am65_cpsw_ndev_priv *)netdev_priv(ndev))
167 #define am65_ndev_to_port(ndev) (am65_ndev_to_priv(ndev)->port)
168 #define am65_ndev_to_common(ndev) (am65_ndev_to_port(ndev)->common)
169 #define am65_ndev_to_slave(ndev) (&am65_ndev_to_port(ndev)->slave)
170 
171 #define am65_common_get_host(common) (&(common)->host)
172 #define am65_common_get_port(common, id) (&(common)->ports[(id) - 1])
173 
174 #define am65_cpsw_napi_to_common(pnapi) \
175 	container_of(pnapi, struct am65_cpsw_common, napi_rx)
176 #define am65_cpsw_napi_to_tx_chn(pnapi) \
177 	container_of(pnapi, struct am65_cpsw_tx_chn, napi_tx)
178 
179 #define AM65_CPSW_DRV_NAME "am65-cpsw-nuss"
180 
181 #define AM65_CPSW_IS_CPSW2G(common) ((common)->port_num == 1)
182 
183 extern const struct ethtool_ops am65_cpsw_ethtool_ops_slave;
184 
185 void am65_cpsw_nuss_adjust_link(struct net_device *ndev);
186 void am65_cpsw_nuss_set_p0_ptype(struct am65_cpsw_common *common);
187 void am65_cpsw_nuss_remove_tx_chns(struct am65_cpsw_common *common);
188 int am65_cpsw_nuss_update_tx_chns(struct am65_cpsw_common *common, int num_tx);
189 
190 bool am65_cpsw_port_dev_check(const struct net_device *dev);
191 
192 #endif /* AM65_CPSW_NUSS_H_ */
193