1 // SPDX-License-Identifier: GPL-2.0 2 /* Texas Instruments K3 AM65 Ethernet Switch SubSystem Driver 3 * 4 * Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/ 5 * 6 */ 7 8 #include <linux/etherdevice.h> 9 #include <linux/if_vlan.h> 10 #include <linux/interrupt.h> 11 #include <linux/kernel.h> 12 #include <linux/kmemleak.h> 13 #include <linux/module.h> 14 #include <linux/netdevice.h> 15 #include <linux/net_tstamp.h> 16 #include <linux/of.h> 17 #include <linux/of_mdio.h> 18 #include <linux/of_net.h> 19 #include <linux/of_device.h> 20 #include <linux/phy.h> 21 #include <linux/phy/phy.h> 22 #include <linux/platform_device.h> 23 #include <linux/pm_runtime.h> 24 #include <linux/regmap.h> 25 #include <linux/mfd/syscon.h> 26 #include <linux/sys_soc.h> 27 #include <linux/dma/ti-cppi5.h> 28 #include <linux/dma/k3-udma-glue.h> 29 30 #include "cpsw_ale.h" 31 #include "cpsw_sl.h" 32 #include "am65-cpsw-nuss.h" 33 #include "k3-cppi-desc-pool.h" 34 #include "am65-cpts.h" 35 36 #define AM65_CPSW_SS_BASE 0x0 37 #define AM65_CPSW_SGMII_BASE 0x100 38 #define AM65_CPSW_XGMII_BASE 0x2100 39 #define AM65_CPSW_CPSW_NU_BASE 0x20000 40 #define AM65_CPSW_NU_PORTS_BASE 0x1000 41 #define AM65_CPSW_NU_FRAM_BASE 0x12000 42 #define AM65_CPSW_NU_STATS_BASE 0x1a000 43 #define AM65_CPSW_NU_ALE_BASE 0x1e000 44 #define AM65_CPSW_NU_CPTS_BASE 0x1d000 45 46 #define AM65_CPSW_NU_PORTS_OFFSET 0x1000 47 #define AM65_CPSW_NU_STATS_PORT_OFFSET 0x200 48 #define AM65_CPSW_NU_FRAM_PORT_OFFSET 0x200 49 50 #define AM65_CPSW_MAX_PORTS 8 51 52 #define AM65_CPSW_MIN_PACKET_SIZE VLAN_ETH_ZLEN 53 #define AM65_CPSW_MAX_PACKET_SIZE (VLAN_ETH_FRAME_LEN + ETH_FCS_LEN) 54 55 #define AM65_CPSW_REG_CTL 0x004 56 #define AM65_CPSW_REG_STAT_PORT_EN 0x014 57 #define AM65_CPSW_REG_PTYPE 0x018 58 59 #define AM65_CPSW_P0_REG_CTL 0x004 60 #define AM65_CPSW_PORT0_REG_FLOW_ID_OFFSET 0x008 61 62 #define AM65_CPSW_PORT_REG_PRI_CTL 0x01c 63 #define AM65_CPSW_PORT_REG_RX_PRI_MAP 0x020 64 #define AM65_CPSW_PORT_REG_RX_MAXLEN 0x024 65 66 #define AM65_CPSW_PORTN_REG_SA_L 0x308 67 #define AM65_CPSW_PORTN_REG_SA_H 0x30c 68 #define AM65_CPSW_PORTN_REG_TS_CTL 0x310 69 #define AM65_CPSW_PORTN_REG_TS_SEQ_LTYPE_REG 0x314 70 #define AM65_CPSW_PORTN_REG_TS_VLAN_LTYPE_REG 0x318 71 #define AM65_CPSW_PORTN_REG_TS_CTL_LTYPE2 0x31C 72 73 #define AM65_CPSW_CTL_VLAN_AWARE BIT(1) 74 #define AM65_CPSW_CTL_P0_ENABLE BIT(2) 75 #define AM65_CPSW_CTL_P0_TX_CRC_REMOVE BIT(13) 76 #define AM65_CPSW_CTL_P0_RX_PAD BIT(14) 77 78 /* AM65_CPSW_P0_REG_CTL */ 79 #define AM65_CPSW_P0_REG_CTL_RX_CHECKSUM_EN BIT(0) 80 81 /* AM65_CPSW_PORT_REG_PRI_CTL */ 82 #define AM65_CPSW_PORT_REG_PRI_CTL_RX_PTYPE_RROBIN BIT(8) 83 84 /* AM65_CPSW_PN_TS_CTL register fields */ 85 #define AM65_CPSW_PN_TS_CTL_TX_ANX_F_EN BIT(4) 86 #define AM65_CPSW_PN_TS_CTL_TX_VLAN_LT1_EN BIT(5) 87 #define AM65_CPSW_PN_TS_CTL_TX_VLAN_LT2_EN BIT(6) 88 #define AM65_CPSW_PN_TS_CTL_TX_ANX_D_EN BIT(7) 89 #define AM65_CPSW_PN_TS_CTL_TX_ANX_E_EN BIT(10) 90 #define AM65_CPSW_PN_TS_CTL_TX_HOST_TS_EN BIT(11) 91 #define AM65_CPSW_PN_TS_CTL_MSG_TYPE_EN_SHIFT 16 92 93 /* AM65_CPSW_PORTN_REG_TS_SEQ_LTYPE_REG register fields */ 94 #define AM65_CPSW_PN_TS_SEQ_ID_OFFSET_SHIFT 16 95 96 /* AM65_CPSW_PORTN_REG_TS_CTL_LTYPE2 */ 97 #define AM65_CPSW_PN_TS_CTL_LTYPE2_TS_107 BIT(16) 98 #define AM65_CPSW_PN_TS_CTL_LTYPE2_TS_129 BIT(17) 99 #define AM65_CPSW_PN_TS_CTL_LTYPE2_TS_130 BIT(18) 100 #define AM65_CPSW_PN_TS_CTL_LTYPE2_TS_131 BIT(19) 101 #define AM65_CPSW_PN_TS_CTL_LTYPE2_TS_132 BIT(20) 102 #define AM65_CPSW_PN_TS_CTL_LTYPE2_TS_319 BIT(21) 103 #define AM65_CPSW_PN_TS_CTL_LTYPE2_TS_320 BIT(22) 104 #define AM65_CPSW_PN_TS_CTL_LTYPE2_TS_TTL_NONZERO BIT(23) 105 106 /* The PTP event messages - Sync, Delay_Req, Pdelay_Req, and Pdelay_Resp. */ 107 #define AM65_CPSW_TS_EVENT_MSG_TYPE_BITS (BIT(0) | BIT(1) | BIT(2) | BIT(3)) 108 109 #define AM65_CPSW_TS_SEQ_ID_OFFSET (0x1e) 110 111 #define AM65_CPSW_TS_TX_ANX_ALL_EN \ 112 (AM65_CPSW_PN_TS_CTL_TX_ANX_D_EN | \ 113 AM65_CPSW_PN_TS_CTL_TX_ANX_E_EN | \ 114 AM65_CPSW_PN_TS_CTL_TX_ANX_F_EN) 115 116 #define AM65_CPSW_ALE_AGEOUT_DEFAULT 30 117 /* Number of TX/RX descriptors */ 118 #define AM65_CPSW_MAX_TX_DESC 500 119 #define AM65_CPSW_MAX_RX_DESC 500 120 121 #define AM65_CPSW_NAV_PS_DATA_SIZE 16 122 #define AM65_CPSW_NAV_SW_DATA_SIZE 16 123 124 #define AM65_CPSW_DEBUG (NETIF_MSG_HW | NETIF_MSG_DRV | NETIF_MSG_LINK | \ 125 NETIF_MSG_IFUP | NETIF_MSG_PROBE | NETIF_MSG_IFDOWN | \ 126 NETIF_MSG_RX_ERR | NETIF_MSG_TX_ERR) 127 128 static void am65_cpsw_port_set_sl_mac(struct am65_cpsw_port *slave, 129 const u8 *dev_addr) 130 { 131 u32 mac_hi = (dev_addr[0] << 0) | (dev_addr[1] << 8) | 132 (dev_addr[2] << 16) | (dev_addr[3] << 24); 133 u32 mac_lo = (dev_addr[4] << 0) | (dev_addr[5] << 8); 134 135 writel(mac_hi, slave->port_base + AM65_CPSW_PORTN_REG_SA_H); 136 writel(mac_lo, slave->port_base + AM65_CPSW_PORTN_REG_SA_L); 137 } 138 139 static void am65_cpsw_sl_ctl_reset(struct am65_cpsw_port *port) 140 { 141 cpsw_sl_reset(port->slave.mac_sl, 100); 142 /* Max length register has to be restored after MAC SL reset */ 143 writel(AM65_CPSW_MAX_PACKET_SIZE, 144 port->port_base + AM65_CPSW_PORT_REG_RX_MAXLEN); 145 } 146 147 static void am65_cpsw_nuss_get_ver(struct am65_cpsw_common *common) 148 { 149 common->nuss_ver = readl(common->ss_base); 150 common->cpsw_ver = readl(common->cpsw_base); 151 dev_info(common->dev, 152 "initializing am65 cpsw nuss version 0x%08X, cpsw version 0x%08X Ports: %u quirks:%08x\n", 153 common->nuss_ver, 154 common->cpsw_ver, 155 common->port_num + 1, 156 common->pdata.quirks); 157 } 158 159 void am65_cpsw_nuss_adjust_link(struct net_device *ndev) 160 { 161 struct am65_cpsw_common *common = am65_ndev_to_common(ndev); 162 struct am65_cpsw_port *port = am65_ndev_to_port(ndev); 163 struct phy_device *phy = port->slave.phy; 164 u32 mac_control = 0; 165 166 if (!phy) 167 return; 168 169 if (phy->link) { 170 mac_control = CPSW_SL_CTL_GMII_EN; 171 172 if (phy->speed == 1000) 173 mac_control |= CPSW_SL_CTL_GIG; 174 if (phy->speed == 10 && phy_interface_is_rgmii(phy)) 175 /* Can be used with in band mode only */ 176 mac_control |= CPSW_SL_CTL_EXT_EN; 177 if (phy->speed == 100 && phy->interface == PHY_INTERFACE_MODE_RMII) 178 mac_control |= CPSW_SL_CTL_IFCTL_A; 179 if (phy->duplex) 180 mac_control |= CPSW_SL_CTL_FULLDUPLEX; 181 182 /* RGMII speed is 100M if !CPSW_SL_CTL_GIG*/ 183 184 /* rx_pause/tx_pause */ 185 if (port->slave.rx_pause) 186 mac_control |= CPSW_SL_CTL_RX_FLOW_EN; 187 188 if (port->slave.tx_pause) 189 mac_control |= CPSW_SL_CTL_TX_FLOW_EN; 190 191 cpsw_sl_ctl_set(port->slave.mac_sl, mac_control); 192 193 /* enable forwarding */ 194 cpsw_ale_control_set(common->ale, port->port_id, 195 ALE_PORT_STATE, ALE_PORT_STATE_FORWARD); 196 197 am65_cpsw_qos_link_up(ndev, phy->speed); 198 netif_tx_wake_all_queues(ndev); 199 } else { 200 int tmo; 201 202 /* disable forwarding */ 203 cpsw_ale_control_set(common->ale, port->port_id, 204 ALE_PORT_STATE, ALE_PORT_STATE_DISABLE); 205 206 cpsw_sl_ctl_set(port->slave.mac_sl, CPSW_SL_CTL_CMD_IDLE); 207 208 tmo = cpsw_sl_wait_for_idle(port->slave.mac_sl, 100); 209 dev_dbg(common->dev, "donw msc_sl %08x tmo %d\n", 210 cpsw_sl_reg_read(port->slave.mac_sl, CPSW_SL_MACSTATUS), 211 tmo); 212 213 cpsw_sl_ctl_reset(port->slave.mac_sl); 214 215 am65_cpsw_qos_link_down(ndev); 216 netif_tx_stop_all_queues(ndev); 217 } 218 219 phy_print_status(phy); 220 } 221 222 static int am65_cpsw_nuss_ndo_slave_add_vid(struct net_device *ndev, 223 __be16 proto, u16 vid) 224 { 225 struct am65_cpsw_common *common = am65_ndev_to_common(ndev); 226 struct am65_cpsw_port *port = am65_ndev_to_port(ndev); 227 u32 port_mask, unreg_mcast = 0; 228 int ret; 229 230 if (!netif_running(ndev) || !vid) 231 return 0; 232 233 ret = pm_runtime_get_sync(common->dev); 234 if (ret < 0) { 235 pm_runtime_put_noidle(common->dev); 236 return ret; 237 } 238 239 port_mask = BIT(port->port_id) | ALE_PORT_HOST; 240 if (!vid) 241 unreg_mcast = port_mask; 242 dev_info(common->dev, "Adding vlan %d to vlan filter\n", vid); 243 ret = cpsw_ale_add_vlan(common->ale, vid, port_mask, 244 unreg_mcast, port_mask, 0); 245 246 pm_runtime_put(common->dev); 247 return ret; 248 } 249 250 static int am65_cpsw_nuss_ndo_slave_kill_vid(struct net_device *ndev, 251 __be16 proto, u16 vid) 252 { 253 struct am65_cpsw_common *common = am65_ndev_to_common(ndev); 254 int ret; 255 256 if (!netif_running(ndev) || !vid) 257 return 0; 258 259 ret = pm_runtime_get_sync(common->dev); 260 if (ret < 0) { 261 pm_runtime_put_noidle(common->dev); 262 return ret; 263 } 264 265 dev_info(common->dev, "Removing vlan %d from vlan filter\n", vid); 266 ret = cpsw_ale_del_vlan(common->ale, vid, 0); 267 268 pm_runtime_put(common->dev); 269 return ret; 270 } 271 272 static void am65_cpsw_slave_set_promisc_2g(struct am65_cpsw_port *port, 273 bool promisc) 274 { 275 struct am65_cpsw_common *common = port->common; 276 277 if (promisc) { 278 /* Enable promiscuous mode */ 279 cpsw_ale_control_set(common->ale, port->port_id, 280 ALE_PORT_MACONLY_CAF, 1); 281 dev_dbg(common->dev, "promisc enabled\n"); 282 } else { 283 /* Disable promiscuous mode */ 284 cpsw_ale_control_set(common->ale, port->port_id, 285 ALE_PORT_MACONLY_CAF, 0); 286 dev_dbg(common->dev, "promisc disabled\n"); 287 } 288 } 289 290 static void am65_cpsw_nuss_ndo_slave_set_rx_mode(struct net_device *ndev) 291 { 292 struct am65_cpsw_common *common = am65_ndev_to_common(ndev); 293 struct am65_cpsw_port *port = am65_ndev_to_port(ndev); 294 u32 port_mask; 295 bool promisc; 296 297 promisc = !!(ndev->flags & IFF_PROMISC); 298 am65_cpsw_slave_set_promisc_2g(port, promisc); 299 300 if (promisc) 301 return; 302 303 /* Restore allmulti on vlans if necessary */ 304 cpsw_ale_set_allmulti(common->ale, 305 ndev->flags & IFF_ALLMULTI, port->port_id); 306 307 port_mask = ALE_PORT_HOST; 308 /* Clear all mcast from ALE */ 309 cpsw_ale_flush_multicast(common->ale, port_mask, -1); 310 311 if (!netdev_mc_empty(ndev)) { 312 struct netdev_hw_addr *ha; 313 314 /* program multicast address list into ALE register */ 315 netdev_for_each_mc_addr(ha, ndev) { 316 cpsw_ale_add_mcast(common->ale, ha->addr, 317 port_mask, 0, 0, 0); 318 } 319 } 320 } 321 322 static void am65_cpsw_nuss_ndo_host_tx_timeout(struct net_device *ndev, 323 unsigned int txqueue) 324 { 325 struct am65_cpsw_common *common = am65_ndev_to_common(ndev); 326 struct am65_cpsw_tx_chn *tx_chn; 327 struct netdev_queue *netif_txq; 328 unsigned long trans_start; 329 330 netif_txq = netdev_get_tx_queue(ndev, txqueue); 331 tx_chn = &common->tx_chns[txqueue]; 332 trans_start = netif_txq->trans_start; 333 334 netdev_err(ndev, "txq:%d DRV_XOFF:%d tmo:%u dql_avail:%d free_desc:%zu\n", 335 txqueue, 336 netif_tx_queue_stopped(netif_txq), 337 jiffies_to_msecs(jiffies - trans_start), 338 dql_avail(&netif_txq->dql), 339 k3_cppi_desc_pool_avail(tx_chn->desc_pool)); 340 341 if (netif_tx_queue_stopped(netif_txq)) { 342 /* try recover if stopped by us */ 343 txq_trans_update(netif_txq); 344 netif_tx_wake_queue(netif_txq); 345 } 346 } 347 348 static int am65_cpsw_nuss_rx_push(struct am65_cpsw_common *common, 349 struct sk_buff *skb) 350 { 351 struct am65_cpsw_rx_chn *rx_chn = &common->rx_chns; 352 struct cppi5_host_desc_t *desc_rx; 353 struct device *dev = common->dev; 354 u32 pkt_len = skb_tailroom(skb); 355 dma_addr_t desc_dma; 356 dma_addr_t buf_dma; 357 void *swdata; 358 359 desc_rx = k3_cppi_desc_pool_alloc(rx_chn->desc_pool); 360 if (!desc_rx) { 361 dev_err(dev, "Failed to allocate RXFDQ descriptor\n"); 362 return -ENOMEM; 363 } 364 desc_dma = k3_cppi_desc_pool_virt2dma(rx_chn->desc_pool, desc_rx); 365 366 buf_dma = dma_map_single(dev, skb->data, pkt_len, DMA_FROM_DEVICE); 367 if (unlikely(dma_mapping_error(dev, buf_dma))) { 368 k3_cppi_desc_pool_free(rx_chn->desc_pool, desc_rx); 369 dev_err(dev, "Failed to map rx skb buffer\n"); 370 return -EINVAL; 371 } 372 373 cppi5_hdesc_init(desc_rx, CPPI5_INFO0_HDESC_EPIB_PRESENT, 374 AM65_CPSW_NAV_PS_DATA_SIZE); 375 cppi5_hdesc_attach_buf(desc_rx, 0, 0, buf_dma, skb_tailroom(skb)); 376 swdata = cppi5_hdesc_get_swdata(desc_rx); 377 *((void **)swdata) = skb; 378 379 return k3_udma_glue_push_rx_chn(rx_chn->rx_chn, 0, desc_rx, desc_dma); 380 } 381 382 void am65_cpsw_nuss_set_p0_ptype(struct am65_cpsw_common *common) 383 { 384 struct am65_cpsw_host *host_p = am65_common_get_host(common); 385 u32 val, pri_map; 386 387 /* P0 set Receive Priority Type */ 388 val = readl(host_p->port_base + AM65_CPSW_PORT_REG_PRI_CTL); 389 390 if (common->pf_p0_rx_ptype_rrobin) { 391 val |= AM65_CPSW_PORT_REG_PRI_CTL_RX_PTYPE_RROBIN; 392 /* Enet Ports fifos works in fixed priority mode only, so 393 * reset P0_Rx_Pri_Map so all packet will go in Enet fifo 0 394 */ 395 pri_map = 0x0; 396 } else { 397 val &= ~AM65_CPSW_PORT_REG_PRI_CTL_RX_PTYPE_RROBIN; 398 /* restore P0_Rx_Pri_Map */ 399 pri_map = 0x76543210; 400 } 401 402 writel(pri_map, host_p->port_base + AM65_CPSW_PORT_REG_RX_PRI_MAP); 403 writel(val, host_p->port_base + AM65_CPSW_PORT_REG_PRI_CTL); 404 } 405 406 static int am65_cpsw_nuss_common_open(struct am65_cpsw_common *common, 407 netdev_features_t features) 408 { 409 struct am65_cpsw_host *host_p = am65_common_get_host(common); 410 int port_idx, i, ret; 411 struct sk_buff *skb; 412 u32 val, port_mask; 413 414 if (common->usage_count) 415 return 0; 416 417 /* Control register */ 418 writel(AM65_CPSW_CTL_P0_ENABLE | AM65_CPSW_CTL_P0_TX_CRC_REMOVE | 419 AM65_CPSW_CTL_VLAN_AWARE | AM65_CPSW_CTL_P0_RX_PAD, 420 common->cpsw_base + AM65_CPSW_REG_CTL); 421 /* Max length register */ 422 writel(AM65_CPSW_MAX_PACKET_SIZE, 423 host_p->port_base + AM65_CPSW_PORT_REG_RX_MAXLEN); 424 /* set base flow_id */ 425 writel(common->rx_flow_id_base, 426 host_p->port_base + AM65_CPSW_PORT0_REG_FLOW_ID_OFFSET); 427 /* en tx crc offload */ 428 if (features & NETIF_F_HW_CSUM) 429 writel(AM65_CPSW_P0_REG_CTL_RX_CHECKSUM_EN, 430 host_p->port_base + AM65_CPSW_P0_REG_CTL); 431 432 am65_cpsw_nuss_set_p0_ptype(common); 433 434 /* enable statistic */ 435 val = BIT(HOST_PORT_NUM); 436 for (port_idx = 0; port_idx < common->port_num; port_idx++) { 437 struct am65_cpsw_port *port = &common->ports[port_idx]; 438 439 if (!port->disabled) 440 val |= BIT(port->port_id); 441 } 442 writel(val, common->cpsw_base + AM65_CPSW_REG_STAT_PORT_EN); 443 444 /* disable priority elevation */ 445 writel(0, common->cpsw_base + AM65_CPSW_REG_PTYPE); 446 447 cpsw_ale_start(common->ale); 448 449 /* limit to one RX flow only */ 450 cpsw_ale_control_set(common->ale, HOST_PORT_NUM, 451 ALE_DEFAULT_THREAD_ID, 0); 452 cpsw_ale_control_set(common->ale, HOST_PORT_NUM, 453 ALE_DEFAULT_THREAD_ENABLE, 1); 454 if (AM65_CPSW_IS_CPSW2G(common)) 455 cpsw_ale_control_set(common->ale, HOST_PORT_NUM, 456 ALE_PORT_NOLEARN, 1); 457 /* switch to vlan unaware mode */ 458 cpsw_ale_control_set(common->ale, HOST_PORT_NUM, ALE_VLAN_AWARE, 1); 459 cpsw_ale_control_set(common->ale, HOST_PORT_NUM, 460 ALE_PORT_STATE, ALE_PORT_STATE_FORWARD); 461 462 /* default vlan cfg: create mask based on enabled ports */ 463 port_mask = GENMASK(common->port_num, 0) & 464 ~common->disabled_ports_mask; 465 466 cpsw_ale_add_vlan(common->ale, 0, port_mask, 467 port_mask, port_mask, 468 port_mask & ~ALE_PORT_HOST); 469 470 for (i = 0; i < common->rx_chns.descs_num; i++) { 471 skb = __netdev_alloc_skb_ip_align(NULL, 472 AM65_CPSW_MAX_PACKET_SIZE, 473 GFP_KERNEL); 474 if (!skb) { 475 dev_err(common->dev, "cannot allocate skb\n"); 476 return -ENOMEM; 477 } 478 479 ret = am65_cpsw_nuss_rx_push(common, skb); 480 if (ret < 0) { 481 dev_err(common->dev, 482 "cannot submit skb to channel rx, error %d\n", 483 ret); 484 kfree_skb(skb); 485 return ret; 486 } 487 kmemleak_not_leak(skb); 488 } 489 k3_udma_glue_enable_rx_chn(common->rx_chns.rx_chn); 490 491 for (i = 0; i < common->tx_ch_num; i++) { 492 ret = k3_udma_glue_enable_tx_chn(common->tx_chns[i].tx_chn); 493 if (ret) 494 return ret; 495 napi_enable(&common->tx_chns[i].napi_tx); 496 } 497 498 napi_enable(&common->napi_rx); 499 500 dev_dbg(common->dev, "cpsw_nuss started\n"); 501 return 0; 502 } 503 504 static void am65_cpsw_nuss_tx_cleanup(void *data, dma_addr_t desc_dma); 505 static void am65_cpsw_nuss_rx_cleanup(void *data, dma_addr_t desc_dma); 506 507 static int am65_cpsw_nuss_common_stop(struct am65_cpsw_common *common) 508 { 509 int i; 510 511 if (common->usage_count != 1) 512 return 0; 513 514 cpsw_ale_control_set(common->ale, HOST_PORT_NUM, 515 ALE_PORT_STATE, ALE_PORT_STATE_DISABLE); 516 517 /* shutdown tx channels */ 518 atomic_set(&common->tdown_cnt, common->tx_ch_num); 519 /* ensure new tdown_cnt value is visible */ 520 smp_mb__after_atomic(); 521 reinit_completion(&common->tdown_complete); 522 523 for (i = 0; i < common->tx_ch_num; i++) 524 k3_udma_glue_tdown_tx_chn(common->tx_chns[i].tx_chn, false); 525 526 i = wait_for_completion_timeout(&common->tdown_complete, 527 msecs_to_jiffies(1000)); 528 if (!i) 529 dev_err(common->dev, "tx timeout\n"); 530 for (i = 0; i < common->tx_ch_num; i++) 531 napi_disable(&common->tx_chns[i].napi_tx); 532 533 for (i = 0; i < common->tx_ch_num; i++) { 534 k3_udma_glue_reset_tx_chn(common->tx_chns[i].tx_chn, 535 &common->tx_chns[i], 536 am65_cpsw_nuss_tx_cleanup); 537 k3_udma_glue_disable_tx_chn(common->tx_chns[i].tx_chn); 538 } 539 540 k3_udma_glue_tdown_rx_chn(common->rx_chns.rx_chn, true); 541 napi_disable(&common->napi_rx); 542 543 for (i = 0; i < AM65_CPSW_MAX_RX_FLOWS; i++) 544 k3_udma_glue_reset_rx_chn(common->rx_chns.rx_chn, i, 545 &common->rx_chns, 546 am65_cpsw_nuss_rx_cleanup, !!i); 547 548 k3_udma_glue_disable_rx_chn(common->rx_chns.rx_chn); 549 550 cpsw_ale_stop(common->ale); 551 552 writel(0, common->cpsw_base + AM65_CPSW_REG_CTL); 553 writel(0, common->cpsw_base + AM65_CPSW_REG_STAT_PORT_EN); 554 555 dev_dbg(common->dev, "cpsw_nuss stopped\n"); 556 return 0; 557 } 558 559 static int am65_cpsw_nuss_ndo_slave_stop(struct net_device *ndev) 560 { 561 struct am65_cpsw_common *common = am65_ndev_to_common(ndev); 562 struct am65_cpsw_port *port = am65_ndev_to_port(ndev); 563 int ret; 564 565 if (port->slave.phy) 566 phy_stop(port->slave.phy); 567 568 netif_tx_stop_all_queues(ndev); 569 570 if (port->slave.phy) { 571 phy_disconnect(port->slave.phy); 572 port->slave.phy = NULL; 573 } 574 575 ret = am65_cpsw_nuss_common_stop(common); 576 if (ret) 577 return ret; 578 579 common->usage_count--; 580 pm_runtime_put(common->dev); 581 return 0; 582 } 583 584 static int cpsw_restore_vlans(struct net_device *vdev, int vid, void *arg) 585 { 586 struct am65_cpsw_port *port = arg; 587 588 if (!vdev) 589 return 0; 590 591 return am65_cpsw_nuss_ndo_slave_add_vid(port->ndev, 0, vid); 592 } 593 594 static int am65_cpsw_nuss_ndo_slave_open(struct net_device *ndev) 595 { 596 struct am65_cpsw_common *common = am65_ndev_to_common(ndev); 597 struct am65_cpsw_port *port = am65_ndev_to_port(ndev); 598 u32 port_mask; 599 int ret, i; 600 601 ret = pm_runtime_get_sync(common->dev); 602 if (ret < 0) { 603 pm_runtime_put_noidle(common->dev); 604 return ret; 605 } 606 607 /* Notify the stack of the actual queue counts. */ 608 ret = netif_set_real_num_tx_queues(ndev, common->tx_ch_num); 609 if (ret) { 610 dev_err(common->dev, "cannot set real number of tx queues\n"); 611 return ret; 612 } 613 614 ret = netif_set_real_num_rx_queues(ndev, AM65_CPSW_MAX_RX_QUEUES); 615 if (ret) { 616 dev_err(common->dev, "cannot set real number of rx queues\n"); 617 return ret; 618 } 619 620 for (i = 0; i < common->tx_ch_num; i++) 621 netdev_tx_reset_queue(netdev_get_tx_queue(ndev, i)); 622 623 ret = am65_cpsw_nuss_common_open(common, ndev->features); 624 if (ret) 625 return ret; 626 627 common->usage_count++; 628 629 am65_cpsw_port_set_sl_mac(port, ndev->dev_addr); 630 631 if (port->slave.mac_only) 632 /* enable mac-only mode on port */ 633 cpsw_ale_control_set(common->ale, port->port_id, 634 ALE_PORT_MACONLY, 1); 635 if (AM65_CPSW_IS_CPSW2G(common)) 636 cpsw_ale_control_set(common->ale, port->port_id, 637 ALE_PORT_NOLEARN, 1); 638 639 port_mask = BIT(port->port_id) | ALE_PORT_HOST; 640 cpsw_ale_add_ucast(common->ale, ndev->dev_addr, 641 HOST_PORT_NUM, ALE_SECURE, 0); 642 cpsw_ale_add_mcast(common->ale, ndev->broadcast, 643 port_mask, 0, 0, ALE_MCAST_FWD_2); 644 645 /* mac_sl should be configured via phy-link interface */ 646 am65_cpsw_sl_ctl_reset(port); 647 648 ret = phy_set_mode_ext(port->slave.ifphy, PHY_MODE_ETHERNET, 649 port->slave.phy_if); 650 if (ret) 651 goto error_cleanup; 652 653 if (port->slave.phy_node) { 654 port->slave.phy = of_phy_connect(ndev, 655 port->slave.phy_node, 656 &am65_cpsw_nuss_adjust_link, 657 0, port->slave.phy_if); 658 if (!port->slave.phy) { 659 dev_err(common->dev, "phy %pOF not found on slave %d\n", 660 port->slave.phy_node, 661 port->port_id); 662 ret = -ENODEV; 663 goto error_cleanup; 664 } 665 } 666 667 /* restore vlan configurations */ 668 vlan_for_each(ndev, cpsw_restore_vlans, port); 669 670 phy_attached_info(port->slave.phy); 671 phy_start(port->slave.phy); 672 673 return 0; 674 675 error_cleanup: 676 am65_cpsw_nuss_ndo_slave_stop(ndev); 677 return ret; 678 } 679 680 static void am65_cpsw_nuss_rx_cleanup(void *data, dma_addr_t desc_dma) 681 { 682 struct am65_cpsw_rx_chn *rx_chn = data; 683 struct cppi5_host_desc_t *desc_rx; 684 struct sk_buff *skb; 685 dma_addr_t buf_dma; 686 u32 buf_dma_len; 687 void **swdata; 688 689 desc_rx = k3_cppi_desc_pool_dma2virt(rx_chn->desc_pool, desc_dma); 690 swdata = cppi5_hdesc_get_swdata(desc_rx); 691 skb = *swdata; 692 cppi5_hdesc_get_obuf(desc_rx, &buf_dma, &buf_dma_len); 693 694 dma_unmap_single(rx_chn->dev, buf_dma, buf_dma_len, DMA_FROM_DEVICE); 695 k3_cppi_desc_pool_free(rx_chn->desc_pool, desc_rx); 696 697 dev_kfree_skb_any(skb); 698 } 699 700 static void am65_cpsw_nuss_rx_ts(struct sk_buff *skb, u32 *psdata) 701 { 702 struct skb_shared_hwtstamps *ssh; 703 u64 ns; 704 705 ns = ((u64)psdata[1] << 32) | psdata[0]; 706 707 ssh = skb_hwtstamps(skb); 708 memset(ssh, 0, sizeof(*ssh)); 709 ssh->hwtstamp = ns_to_ktime(ns); 710 } 711 712 /* RX psdata[2] word format - checksum information */ 713 #define AM65_CPSW_RX_PSD_CSUM_ADD GENMASK(15, 0) 714 #define AM65_CPSW_RX_PSD_CSUM_ERR BIT(16) 715 #define AM65_CPSW_RX_PSD_IS_FRAGMENT BIT(17) 716 #define AM65_CPSW_RX_PSD_IS_TCP BIT(18) 717 #define AM65_CPSW_RX_PSD_IPV6_VALID BIT(19) 718 #define AM65_CPSW_RX_PSD_IPV4_VALID BIT(20) 719 720 static void am65_cpsw_nuss_rx_csum(struct sk_buff *skb, u32 csum_info) 721 { 722 /* HW can verify IPv4/IPv6 TCP/UDP packets checksum 723 * csum information provides in psdata[2] word: 724 * AM65_CPSW_RX_PSD_CSUM_ERR bit - indicates csum error 725 * AM65_CPSW_RX_PSD_IPV6_VALID and AM65_CPSW_RX_PSD_IPV4_VALID 726 * bits - indicates IPv4/IPv6 packet 727 * AM65_CPSW_RX_PSD_IS_FRAGMENT bit - indicates fragmented packet 728 * AM65_CPSW_RX_PSD_CSUM_ADD has value 0xFFFF for non fragmented packets 729 * or csum value for fragmented packets if !AM65_CPSW_RX_PSD_CSUM_ERR 730 */ 731 skb_checksum_none_assert(skb); 732 733 if (unlikely(!(skb->dev->features & NETIF_F_RXCSUM))) 734 return; 735 736 if ((csum_info & (AM65_CPSW_RX_PSD_IPV6_VALID | 737 AM65_CPSW_RX_PSD_IPV4_VALID)) && 738 !(csum_info & AM65_CPSW_RX_PSD_CSUM_ERR)) { 739 /* csum for fragmented packets is unsupported */ 740 if (!(csum_info & AM65_CPSW_RX_PSD_IS_FRAGMENT)) 741 skb->ip_summed = CHECKSUM_UNNECESSARY; 742 } 743 } 744 745 static int am65_cpsw_nuss_rx_packets(struct am65_cpsw_common *common, 746 u32 flow_idx) 747 { 748 struct am65_cpsw_rx_chn *rx_chn = &common->rx_chns; 749 u32 buf_dma_len, pkt_len, port_id = 0, csum_info; 750 struct am65_cpsw_ndev_priv *ndev_priv; 751 struct am65_cpsw_ndev_stats *stats; 752 struct cppi5_host_desc_t *desc_rx; 753 struct device *dev = common->dev; 754 struct sk_buff *skb, *new_skb; 755 dma_addr_t desc_dma, buf_dma; 756 struct am65_cpsw_port *port; 757 struct net_device *ndev; 758 void **swdata; 759 u32 *psdata; 760 int ret = 0; 761 762 ret = k3_udma_glue_pop_rx_chn(rx_chn->rx_chn, flow_idx, &desc_dma); 763 if (ret) { 764 if (ret != -ENODATA) 765 dev_err(dev, "RX: pop chn fail %d\n", ret); 766 return ret; 767 } 768 769 if (desc_dma & 0x1) { 770 dev_dbg(dev, "%s RX tdown flow: %u\n", __func__, flow_idx); 771 return 0; 772 } 773 774 desc_rx = k3_cppi_desc_pool_dma2virt(rx_chn->desc_pool, desc_dma); 775 dev_dbg(dev, "%s flow_idx: %u desc %pad\n", 776 __func__, flow_idx, &desc_dma); 777 778 swdata = cppi5_hdesc_get_swdata(desc_rx); 779 skb = *swdata; 780 cppi5_hdesc_get_obuf(desc_rx, &buf_dma, &buf_dma_len); 781 pkt_len = cppi5_hdesc_get_pktlen(desc_rx); 782 cppi5_desc_get_tags_ids(&desc_rx->hdr, &port_id, NULL); 783 dev_dbg(dev, "%s rx port_id:%d\n", __func__, port_id); 784 port = am65_common_get_port(common, port_id); 785 ndev = port->ndev; 786 skb->dev = ndev; 787 788 psdata = cppi5_hdesc_get_psdata(desc_rx); 789 /* add RX timestamp */ 790 if (port->rx_ts_enabled) 791 am65_cpsw_nuss_rx_ts(skb, psdata); 792 csum_info = psdata[2]; 793 dev_dbg(dev, "%s rx csum_info:%#x\n", __func__, csum_info); 794 795 dma_unmap_single(dev, buf_dma, buf_dma_len, DMA_FROM_DEVICE); 796 797 k3_cppi_desc_pool_free(rx_chn->desc_pool, desc_rx); 798 799 new_skb = netdev_alloc_skb_ip_align(ndev, AM65_CPSW_MAX_PACKET_SIZE); 800 if (new_skb) { 801 skb_put(skb, pkt_len); 802 skb->protocol = eth_type_trans(skb, ndev); 803 am65_cpsw_nuss_rx_csum(skb, csum_info); 804 napi_gro_receive(&common->napi_rx, skb); 805 806 ndev_priv = netdev_priv(ndev); 807 stats = this_cpu_ptr(ndev_priv->stats); 808 809 u64_stats_update_begin(&stats->syncp); 810 stats->rx_packets++; 811 stats->rx_bytes += pkt_len; 812 u64_stats_update_end(&stats->syncp); 813 kmemleak_not_leak(new_skb); 814 } else { 815 ndev->stats.rx_dropped++; 816 new_skb = skb; 817 } 818 819 if (netif_dormant(ndev)) { 820 dev_kfree_skb_any(new_skb); 821 ndev->stats.rx_dropped++; 822 return 0; 823 } 824 825 ret = am65_cpsw_nuss_rx_push(common, new_skb); 826 if (WARN_ON(ret < 0)) { 827 dev_kfree_skb_any(new_skb); 828 ndev->stats.rx_errors++; 829 ndev->stats.rx_dropped++; 830 } 831 832 return ret; 833 } 834 835 static int am65_cpsw_nuss_rx_poll(struct napi_struct *napi_rx, int budget) 836 { 837 struct am65_cpsw_common *common = am65_cpsw_napi_to_common(napi_rx); 838 int flow = AM65_CPSW_MAX_RX_FLOWS; 839 int cur_budget, ret; 840 int num_rx = 0; 841 842 /* process every flow */ 843 while (flow--) { 844 cur_budget = budget - num_rx; 845 846 while (cur_budget--) { 847 ret = am65_cpsw_nuss_rx_packets(common, flow); 848 if (ret) 849 break; 850 num_rx++; 851 } 852 853 if (num_rx >= budget) 854 break; 855 } 856 857 dev_dbg(common->dev, "%s num_rx:%d %d\n", __func__, num_rx, budget); 858 859 if (num_rx < budget && napi_complete_done(napi_rx, num_rx)) 860 enable_irq(common->rx_chns.irq); 861 862 return num_rx; 863 } 864 865 static void am65_cpsw_nuss_xmit_free(struct am65_cpsw_tx_chn *tx_chn, 866 struct device *dev, 867 struct cppi5_host_desc_t *desc) 868 { 869 struct cppi5_host_desc_t *first_desc, *next_desc; 870 dma_addr_t buf_dma, next_desc_dma; 871 u32 buf_dma_len; 872 873 first_desc = desc; 874 next_desc = first_desc; 875 876 cppi5_hdesc_get_obuf(first_desc, &buf_dma, &buf_dma_len); 877 878 dma_unmap_single(dev, buf_dma, buf_dma_len, 879 DMA_TO_DEVICE); 880 881 next_desc_dma = cppi5_hdesc_get_next_hbdesc(first_desc); 882 while (next_desc_dma) { 883 next_desc = k3_cppi_desc_pool_dma2virt(tx_chn->desc_pool, 884 next_desc_dma); 885 cppi5_hdesc_get_obuf(next_desc, &buf_dma, &buf_dma_len); 886 887 dma_unmap_page(dev, buf_dma, buf_dma_len, 888 DMA_TO_DEVICE); 889 890 next_desc_dma = cppi5_hdesc_get_next_hbdesc(next_desc); 891 892 k3_cppi_desc_pool_free(tx_chn->desc_pool, next_desc); 893 } 894 895 k3_cppi_desc_pool_free(tx_chn->desc_pool, first_desc); 896 } 897 898 static void am65_cpsw_nuss_tx_cleanup(void *data, dma_addr_t desc_dma) 899 { 900 struct am65_cpsw_tx_chn *tx_chn = data; 901 struct cppi5_host_desc_t *desc_tx; 902 struct sk_buff *skb; 903 void **swdata; 904 905 desc_tx = k3_cppi_desc_pool_dma2virt(tx_chn->desc_pool, desc_dma); 906 swdata = cppi5_hdesc_get_swdata(desc_tx); 907 skb = *(swdata); 908 am65_cpsw_nuss_xmit_free(tx_chn, tx_chn->common->dev, desc_tx); 909 910 dev_kfree_skb_any(skb); 911 } 912 913 static int am65_cpsw_nuss_tx_compl_packets(struct am65_cpsw_common *common, 914 int chn, unsigned int budget) 915 { 916 struct cppi5_host_desc_t *desc_tx; 917 struct device *dev = common->dev; 918 struct am65_cpsw_tx_chn *tx_chn; 919 struct netdev_queue *netif_txq; 920 unsigned int total_bytes = 0; 921 struct net_device *ndev; 922 struct sk_buff *skb; 923 dma_addr_t desc_dma; 924 int res, num_tx = 0; 925 void **swdata; 926 927 tx_chn = &common->tx_chns[chn]; 928 929 while (true) { 930 struct am65_cpsw_ndev_priv *ndev_priv; 931 struct am65_cpsw_ndev_stats *stats; 932 933 res = k3_udma_glue_pop_tx_chn(tx_chn->tx_chn, &desc_dma); 934 if (res == -ENODATA) 935 break; 936 937 if (desc_dma & 0x1) { 938 if (atomic_dec_and_test(&common->tdown_cnt)) 939 complete(&common->tdown_complete); 940 break; 941 } 942 943 desc_tx = k3_cppi_desc_pool_dma2virt(tx_chn->desc_pool, 944 desc_dma); 945 swdata = cppi5_hdesc_get_swdata(desc_tx); 946 skb = *(swdata); 947 am65_cpsw_nuss_xmit_free(tx_chn, dev, desc_tx); 948 949 ndev = skb->dev; 950 951 am65_cpts_tx_timestamp(common->cpts, skb); 952 953 ndev_priv = netdev_priv(ndev); 954 stats = this_cpu_ptr(ndev_priv->stats); 955 u64_stats_update_begin(&stats->syncp); 956 stats->tx_packets++; 957 stats->tx_bytes += skb->len; 958 u64_stats_update_end(&stats->syncp); 959 960 total_bytes += skb->len; 961 napi_consume_skb(skb, budget); 962 num_tx++; 963 } 964 965 if (!num_tx) 966 return 0; 967 968 netif_txq = netdev_get_tx_queue(ndev, chn); 969 970 netdev_tx_completed_queue(netif_txq, num_tx, total_bytes); 971 972 if (netif_tx_queue_stopped(netif_txq)) { 973 /* Check whether the queue is stopped due to stalled tx dma, 974 * if the queue is stopped then wake the queue as 975 * we have free desc for tx 976 */ 977 __netif_tx_lock(netif_txq, smp_processor_id()); 978 if (netif_running(ndev) && 979 (k3_cppi_desc_pool_avail(tx_chn->desc_pool) >= 980 MAX_SKB_FRAGS)) 981 netif_tx_wake_queue(netif_txq); 982 983 __netif_tx_unlock(netif_txq); 984 } 985 dev_dbg(dev, "%s:%u pkt:%d\n", __func__, chn, num_tx); 986 987 return num_tx; 988 } 989 990 static int am65_cpsw_nuss_tx_poll(struct napi_struct *napi_tx, int budget) 991 { 992 struct am65_cpsw_tx_chn *tx_chn = am65_cpsw_napi_to_tx_chn(napi_tx); 993 int num_tx; 994 995 num_tx = am65_cpsw_nuss_tx_compl_packets(tx_chn->common, tx_chn->id, 996 budget); 997 num_tx = min(num_tx, budget); 998 if (num_tx < budget) { 999 napi_complete(napi_tx); 1000 enable_irq(tx_chn->irq); 1001 } 1002 1003 return num_tx; 1004 } 1005 1006 static irqreturn_t am65_cpsw_nuss_rx_irq(int irq, void *dev_id) 1007 { 1008 struct am65_cpsw_common *common = dev_id; 1009 1010 disable_irq_nosync(irq); 1011 napi_schedule(&common->napi_rx); 1012 1013 return IRQ_HANDLED; 1014 } 1015 1016 static irqreturn_t am65_cpsw_nuss_tx_irq(int irq, void *dev_id) 1017 { 1018 struct am65_cpsw_tx_chn *tx_chn = dev_id; 1019 1020 disable_irq_nosync(irq); 1021 napi_schedule(&tx_chn->napi_tx); 1022 1023 return IRQ_HANDLED; 1024 } 1025 1026 static netdev_tx_t am65_cpsw_nuss_ndo_slave_xmit(struct sk_buff *skb, 1027 struct net_device *ndev) 1028 { 1029 struct am65_cpsw_common *common = am65_ndev_to_common(ndev); 1030 struct cppi5_host_desc_t *first_desc, *next_desc, *cur_desc; 1031 struct am65_cpsw_port *port = am65_ndev_to_port(ndev); 1032 struct device *dev = common->dev; 1033 struct am65_cpsw_tx_chn *tx_chn; 1034 struct netdev_queue *netif_txq; 1035 dma_addr_t desc_dma, buf_dma; 1036 int ret, q_idx, i; 1037 void **swdata; 1038 u32 *psdata; 1039 u32 pkt_len; 1040 1041 /* padding enabled in hw */ 1042 pkt_len = skb_headlen(skb); 1043 1044 /* SKB TX timestamp */ 1045 if (port->tx_ts_enabled) 1046 am65_cpts_prep_tx_timestamp(common->cpts, skb); 1047 1048 q_idx = skb_get_queue_mapping(skb); 1049 dev_dbg(dev, "%s skb_queue:%d\n", __func__, q_idx); 1050 1051 tx_chn = &common->tx_chns[q_idx]; 1052 netif_txq = netdev_get_tx_queue(ndev, q_idx); 1053 1054 /* Map the linear buffer */ 1055 buf_dma = dma_map_single(dev, skb->data, pkt_len, 1056 DMA_TO_DEVICE); 1057 if (unlikely(dma_mapping_error(dev, buf_dma))) { 1058 dev_err(dev, "Failed to map tx skb buffer\n"); 1059 ndev->stats.tx_errors++; 1060 goto err_free_skb; 1061 } 1062 1063 first_desc = k3_cppi_desc_pool_alloc(tx_chn->desc_pool); 1064 if (!first_desc) { 1065 dev_dbg(dev, "Failed to allocate descriptor\n"); 1066 dma_unmap_single(dev, buf_dma, pkt_len, DMA_TO_DEVICE); 1067 goto busy_stop_q; 1068 } 1069 1070 cppi5_hdesc_init(first_desc, CPPI5_INFO0_HDESC_EPIB_PRESENT, 1071 AM65_CPSW_NAV_PS_DATA_SIZE); 1072 cppi5_desc_set_pktids(&first_desc->hdr, 0, 0x3FFF); 1073 cppi5_hdesc_set_pkttype(first_desc, 0x7); 1074 cppi5_desc_set_tags_ids(&first_desc->hdr, 0, port->port_id); 1075 1076 cppi5_hdesc_attach_buf(first_desc, buf_dma, pkt_len, buf_dma, pkt_len); 1077 swdata = cppi5_hdesc_get_swdata(first_desc); 1078 *(swdata) = skb; 1079 psdata = cppi5_hdesc_get_psdata(first_desc); 1080 1081 /* HW csum offload if enabled */ 1082 psdata[2] = 0; 1083 if (likely(skb->ip_summed == CHECKSUM_PARTIAL)) { 1084 unsigned int cs_start, cs_offset; 1085 1086 cs_start = skb_transport_offset(skb); 1087 cs_offset = cs_start + skb->csum_offset; 1088 /* HW numerates bytes starting from 1 */ 1089 psdata[2] = ((cs_offset + 1) << 24) | 1090 ((cs_start + 1) << 16) | (skb->len - cs_start); 1091 dev_dbg(dev, "%s tx psdata:%#x\n", __func__, psdata[2]); 1092 } 1093 1094 if (!skb_is_nonlinear(skb)) 1095 goto done_tx; 1096 1097 dev_dbg(dev, "fragmented SKB\n"); 1098 1099 /* Handle the case where skb is fragmented in pages */ 1100 cur_desc = first_desc; 1101 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { 1102 skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 1103 u32 frag_size = skb_frag_size(frag); 1104 1105 next_desc = k3_cppi_desc_pool_alloc(tx_chn->desc_pool); 1106 if (!next_desc) { 1107 dev_err(dev, "Failed to allocate descriptor\n"); 1108 goto busy_free_descs; 1109 } 1110 1111 buf_dma = skb_frag_dma_map(dev, frag, 0, frag_size, 1112 DMA_TO_DEVICE); 1113 if (unlikely(dma_mapping_error(dev, buf_dma))) { 1114 dev_err(dev, "Failed to map tx skb page\n"); 1115 k3_cppi_desc_pool_free(tx_chn->desc_pool, next_desc); 1116 ndev->stats.tx_errors++; 1117 goto err_free_descs; 1118 } 1119 1120 cppi5_hdesc_reset_hbdesc(next_desc); 1121 cppi5_hdesc_attach_buf(next_desc, 1122 buf_dma, frag_size, buf_dma, frag_size); 1123 1124 desc_dma = k3_cppi_desc_pool_virt2dma(tx_chn->desc_pool, 1125 next_desc); 1126 cppi5_hdesc_link_hbdesc(cur_desc, desc_dma); 1127 1128 pkt_len += frag_size; 1129 cur_desc = next_desc; 1130 } 1131 WARN_ON(pkt_len != skb->len); 1132 1133 done_tx: 1134 skb_tx_timestamp(skb); 1135 1136 /* report bql before sending packet */ 1137 netdev_tx_sent_queue(netif_txq, pkt_len); 1138 1139 cppi5_hdesc_set_pktlen(first_desc, pkt_len); 1140 desc_dma = k3_cppi_desc_pool_virt2dma(tx_chn->desc_pool, first_desc); 1141 ret = k3_udma_glue_push_tx_chn(tx_chn->tx_chn, first_desc, desc_dma); 1142 if (ret) { 1143 dev_err(dev, "can't push desc %d\n", ret); 1144 /* inform bql */ 1145 netdev_tx_completed_queue(netif_txq, 1, pkt_len); 1146 ndev->stats.tx_errors++; 1147 goto err_free_descs; 1148 } 1149 1150 if (k3_cppi_desc_pool_avail(tx_chn->desc_pool) < MAX_SKB_FRAGS) { 1151 netif_tx_stop_queue(netif_txq); 1152 /* Barrier, so that stop_queue visible to other cpus */ 1153 smp_mb__after_atomic(); 1154 dev_dbg(dev, "netif_tx_stop_queue %d\n", q_idx); 1155 1156 /* re-check for smp */ 1157 if (k3_cppi_desc_pool_avail(tx_chn->desc_pool) >= 1158 MAX_SKB_FRAGS) { 1159 netif_tx_wake_queue(netif_txq); 1160 dev_dbg(dev, "netif_tx_wake_queue %d\n", q_idx); 1161 } 1162 } 1163 1164 return NETDEV_TX_OK; 1165 1166 err_free_descs: 1167 am65_cpsw_nuss_xmit_free(tx_chn, dev, first_desc); 1168 err_free_skb: 1169 ndev->stats.tx_dropped++; 1170 dev_kfree_skb_any(skb); 1171 return NETDEV_TX_OK; 1172 1173 busy_free_descs: 1174 am65_cpsw_nuss_xmit_free(tx_chn, dev, first_desc); 1175 busy_stop_q: 1176 netif_tx_stop_queue(netif_txq); 1177 return NETDEV_TX_BUSY; 1178 } 1179 1180 static int am65_cpsw_nuss_ndo_slave_set_mac_address(struct net_device *ndev, 1181 void *addr) 1182 { 1183 struct am65_cpsw_common *common = am65_ndev_to_common(ndev); 1184 struct am65_cpsw_port *port = am65_ndev_to_port(ndev); 1185 struct sockaddr *sockaddr = (struct sockaddr *)addr; 1186 int ret; 1187 1188 ret = eth_prepare_mac_addr_change(ndev, addr); 1189 if (ret < 0) 1190 return ret; 1191 1192 ret = pm_runtime_get_sync(common->dev); 1193 if (ret < 0) { 1194 pm_runtime_put_noidle(common->dev); 1195 return ret; 1196 } 1197 1198 cpsw_ale_del_ucast(common->ale, ndev->dev_addr, 1199 HOST_PORT_NUM, 0, 0); 1200 cpsw_ale_add_ucast(common->ale, sockaddr->sa_data, 1201 HOST_PORT_NUM, ALE_SECURE, 0); 1202 1203 am65_cpsw_port_set_sl_mac(port, addr); 1204 eth_commit_mac_addr_change(ndev, sockaddr); 1205 1206 pm_runtime_put(common->dev); 1207 1208 return 0; 1209 } 1210 1211 static int am65_cpsw_nuss_hwtstamp_set(struct net_device *ndev, 1212 struct ifreq *ifr) 1213 { 1214 struct am65_cpsw_common *common = am65_ndev_to_common(ndev); 1215 struct am65_cpsw_port *port = am65_ndev_to_port(ndev); 1216 u32 ts_ctrl, seq_id, ts_ctrl_ltype2, ts_vlan_ltype; 1217 struct hwtstamp_config cfg; 1218 1219 if (!IS_ENABLED(CONFIG_TI_K3_AM65_CPTS)) 1220 return -EOPNOTSUPP; 1221 1222 if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg))) 1223 return -EFAULT; 1224 1225 /* TX HW timestamp */ 1226 switch (cfg.tx_type) { 1227 case HWTSTAMP_TX_OFF: 1228 case HWTSTAMP_TX_ON: 1229 break; 1230 default: 1231 return -ERANGE; 1232 } 1233 1234 switch (cfg.rx_filter) { 1235 case HWTSTAMP_FILTER_NONE: 1236 port->rx_ts_enabled = false; 1237 break; 1238 case HWTSTAMP_FILTER_ALL: 1239 case HWTSTAMP_FILTER_SOME: 1240 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: 1241 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: 1242 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: 1243 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: 1244 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 1245 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 1246 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: 1247 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: 1248 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: 1249 case HWTSTAMP_FILTER_PTP_V2_EVENT: 1250 case HWTSTAMP_FILTER_PTP_V2_SYNC: 1251 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 1252 case HWTSTAMP_FILTER_NTP_ALL: 1253 port->rx_ts_enabled = true; 1254 cfg.rx_filter = HWTSTAMP_FILTER_ALL; 1255 break; 1256 default: 1257 return -ERANGE; 1258 } 1259 1260 port->tx_ts_enabled = (cfg.tx_type == HWTSTAMP_TX_ON); 1261 1262 /* cfg TX timestamp */ 1263 seq_id = (AM65_CPSW_TS_SEQ_ID_OFFSET << 1264 AM65_CPSW_PN_TS_SEQ_ID_OFFSET_SHIFT) | ETH_P_1588; 1265 1266 ts_vlan_ltype = ETH_P_8021Q; 1267 1268 ts_ctrl_ltype2 = ETH_P_1588 | 1269 AM65_CPSW_PN_TS_CTL_LTYPE2_TS_107 | 1270 AM65_CPSW_PN_TS_CTL_LTYPE2_TS_129 | 1271 AM65_CPSW_PN_TS_CTL_LTYPE2_TS_130 | 1272 AM65_CPSW_PN_TS_CTL_LTYPE2_TS_131 | 1273 AM65_CPSW_PN_TS_CTL_LTYPE2_TS_132 | 1274 AM65_CPSW_PN_TS_CTL_LTYPE2_TS_319 | 1275 AM65_CPSW_PN_TS_CTL_LTYPE2_TS_320 | 1276 AM65_CPSW_PN_TS_CTL_LTYPE2_TS_TTL_NONZERO; 1277 1278 ts_ctrl = AM65_CPSW_TS_EVENT_MSG_TYPE_BITS << 1279 AM65_CPSW_PN_TS_CTL_MSG_TYPE_EN_SHIFT; 1280 1281 if (port->tx_ts_enabled) 1282 ts_ctrl |= AM65_CPSW_TS_TX_ANX_ALL_EN | 1283 AM65_CPSW_PN_TS_CTL_TX_VLAN_LT1_EN; 1284 1285 writel(seq_id, port->port_base + AM65_CPSW_PORTN_REG_TS_SEQ_LTYPE_REG); 1286 writel(ts_vlan_ltype, port->port_base + 1287 AM65_CPSW_PORTN_REG_TS_VLAN_LTYPE_REG); 1288 writel(ts_ctrl_ltype2, port->port_base + 1289 AM65_CPSW_PORTN_REG_TS_CTL_LTYPE2); 1290 writel(ts_ctrl, port->port_base + AM65_CPSW_PORTN_REG_TS_CTL); 1291 1292 /* en/dis RX timestamp */ 1293 am65_cpts_rx_enable(common->cpts, port->rx_ts_enabled); 1294 1295 return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0; 1296 } 1297 1298 static int am65_cpsw_nuss_hwtstamp_get(struct net_device *ndev, 1299 struct ifreq *ifr) 1300 { 1301 struct am65_cpsw_port *port = am65_ndev_to_port(ndev); 1302 struct hwtstamp_config cfg; 1303 1304 if (!IS_ENABLED(CONFIG_TI_K3_AM65_CPTS)) 1305 return -EOPNOTSUPP; 1306 1307 cfg.flags = 0; 1308 cfg.tx_type = port->tx_ts_enabled ? 1309 HWTSTAMP_TX_ON : HWTSTAMP_TX_OFF; 1310 cfg.rx_filter = port->rx_ts_enabled ? 1311 HWTSTAMP_FILTER_ALL : HWTSTAMP_FILTER_NONE; 1312 1313 return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0; 1314 } 1315 1316 static int am65_cpsw_nuss_ndo_slave_ioctl(struct net_device *ndev, 1317 struct ifreq *req, int cmd) 1318 { 1319 struct am65_cpsw_port *port = am65_ndev_to_port(ndev); 1320 1321 if (!netif_running(ndev)) 1322 return -EINVAL; 1323 1324 switch (cmd) { 1325 case SIOCSHWTSTAMP: 1326 return am65_cpsw_nuss_hwtstamp_set(ndev, req); 1327 case SIOCGHWTSTAMP: 1328 return am65_cpsw_nuss_hwtstamp_get(ndev, req); 1329 } 1330 1331 if (!port->slave.phy) 1332 return -EOPNOTSUPP; 1333 1334 return phy_mii_ioctl(port->slave.phy, req, cmd); 1335 } 1336 1337 static void am65_cpsw_nuss_ndo_get_stats(struct net_device *dev, 1338 struct rtnl_link_stats64 *stats) 1339 { 1340 struct am65_cpsw_ndev_priv *ndev_priv = netdev_priv(dev); 1341 unsigned int start; 1342 int cpu; 1343 1344 for_each_possible_cpu(cpu) { 1345 struct am65_cpsw_ndev_stats *cpu_stats; 1346 u64 rx_packets; 1347 u64 rx_bytes; 1348 u64 tx_packets; 1349 u64 tx_bytes; 1350 1351 cpu_stats = per_cpu_ptr(ndev_priv->stats, cpu); 1352 do { 1353 start = u64_stats_fetch_begin_irq(&cpu_stats->syncp); 1354 rx_packets = cpu_stats->rx_packets; 1355 rx_bytes = cpu_stats->rx_bytes; 1356 tx_packets = cpu_stats->tx_packets; 1357 tx_bytes = cpu_stats->tx_bytes; 1358 } while (u64_stats_fetch_retry_irq(&cpu_stats->syncp, start)); 1359 1360 stats->rx_packets += rx_packets; 1361 stats->rx_bytes += rx_bytes; 1362 stats->tx_packets += tx_packets; 1363 stats->tx_bytes += tx_bytes; 1364 } 1365 1366 stats->rx_errors = dev->stats.rx_errors; 1367 stats->rx_dropped = dev->stats.rx_dropped; 1368 stats->tx_dropped = dev->stats.tx_dropped; 1369 } 1370 1371 static int am65_cpsw_nuss_ndo_slave_set_features(struct net_device *ndev, 1372 netdev_features_t features) 1373 { 1374 struct am65_cpsw_common *common = am65_ndev_to_common(ndev); 1375 netdev_features_t changes = features ^ ndev->features; 1376 struct am65_cpsw_host *host_p; 1377 1378 host_p = am65_common_get_host(common); 1379 1380 if (changes & NETIF_F_HW_CSUM) { 1381 bool enable = !!(features & NETIF_F_HW_CSUM); 1382 1383 dev_info(common->dev, "Turn %s tx-checksum-ip-generic\n", 1384 enable ? "ON" : "OFF"); 1385 if (enable) 1386 writel(AM65_CPSW_P0_REG_CTL_RX_CHECKSUM_EN, 1387 host_p->port_base + AM65_CPSW_P0_REG_CTL); 1388 else 1389 writel(0, 1390 host_p->port_base + AM65_CPSW_P0_REG_CTL); 1391 } 1392 1393 return 0; 1394 } 1395 1396 static const struct net_device_ops am65_cpsw_nuss_netdev_ops_2g = { 1397 .ndo_open = am65_cpsw_nuss_ndo_slave_open, 1398 .ndo_stop = am65_cpsw_nuss_ndo_slave_stop, 1399 .ndo_start_xmit = am65_cpsw_nuss_ndo_slave_xmit, 1400 .ndo_set_rx_mode = am65_cpsw_nuss_ndo_slave_set_rx_mode, 1401 .ndo_get_stats64 = am65_cpsw_nuss_ndo_get_stats, 1402 .ndo_validate_addr = eth_validate_addr, 1403 .ndo_set_mac_address = am65_cpsw_nuss_ndo_slave_set_mac_address, 1404 .ndo_tx_timeout = am65_cpsw_nuss_ndo_host_tx_timeout, 1405 .ndo_vlan_rx_add_vid = am65_cpsw_nuss_ndo_slave_add_vid, 1406 .ndo_vlan_rx_kill_vid = am65_cpsw_nuss_ndo_slave_kill_vid, 1407 .ndo_do_ioctl = am65_cpsw_nuss_ndo_slave_ioctl, 1408 .ndo_set_features = am65_cpsw_nuss_ndo_slave_set_features, 1409 .ndo_setup_tc = am65_cpsw_qos_ndo_setup_tc, 1410 }; 1411 1412 static void am65_cpsw_nuss_slave_disable_unused(struct am65_cpsw_port *port) 1413 { 1414 struct am65_cpsw_common *common = port->common; 1415 1416 if (!port->disabled) 1417 return; 1418 1419 common->disabled_ports_mask |= BIT(port->port_id); 1420 cpsw_ale_control_set(common->ale, port->port_id, 1421 ALE_PORT_STATE, ALE_PORT_STATE_DISABLE); 1422 1423 cpsw_sl_reset(port->slave.mac_sl, 100); 1424 cpsw_sl_ctl_reset(port->slave.mac_sl); 1425 } 1426 1427 static void am65_cpsw_nuss_free_tx_chns(void *data) 1428 { 1429 struct am65_cpsw_common *common = data; 1430 int i; 1431 1432 for (i = 0; i < common->tx_ch_num; i++) { 1433 struct am65_cpsw_tx_chn *tx_chn = &common->tx_chns[i]; 1434 1435 if (!IS_ERR_OR_NULL(tx_chn->tx_chn)) 1436 k3_udma_glue_release_tx_chn(tx_chn->tx_chn); 1437 1438 if (!IS_ERR_OR_NULL(tx_chn->desc_pool)) 1439 k3_cppi_desc_pool_destroy(tx_chn->desc_pool); 1440 1441 memset(tx_chn, 0, sizeof(*tx_chn)); 1442 } 1443 } 1444 1445 void am65_cpsw_nuss_remove_tx_chns(struct am65_cpsw_common *common) 1446 { 1447 struct device *dev = common->dev; 1448 int i; 1449 1450 devm_remove_action(dev, am65_cpsw_nuss_free_tx_chns, common); 1451 1452 for (i = 0; i < common->tx_ch_num; i++) { 1453 struct am65_cpsw_tx_chn *tx_chn = &common->tx_chns[i]; 1454 1455 if (tx_chn->irq) 1456 devm_free_irq(dev, tx_chn->irq, tx_chn); 1457 1458 netif_napi_del(&tx_chn->napi_tx); 1459 1460 if (!IS_ERR_OR_NULL(tx_chn->tx_chn)) 1461 k3_udma_glue_release_tx_chn(tx_chn->tx_chn); 1462 1463 if (!IS_ERR_OR_NULL(tx_chn->desc_pool)) 1464 k3_cppi_desc_pool_destroy(tx_chn->desc_pool); 1465 1466 memset(tx_chn, 0, sizeof(*tx_chn)); 1467 } 1468 } 1469 1470 static int am65_cpsw_nuss_init_tx_chns(struct am65_cpsw_common *common) 1471 { 1472 u32 max_desc_num = ALIGN(AM65_CPSW_MAX_TX_DESC, MAX_SKB_FRAGS); 1473 struct k3_udma_glue_tx_channel_cfg tx_cfg = { 0 }; 1474 struct device *dev = common->dev; 1475 struct k3_ring_cfg ring_cfg = { 1476 .elm_size = K3_RINGACC_RING_ELSIZE_8, 1477 .mode = K3_RINGACC_RING_MODE_RING, 1478 .flags = 0 1479 }; 1480 u32 hdesc_size; 1481 int i, ret = 0; 1482 1483 hdesc_size = cppi5_hdesc_calc_size(true, AM65_CPSW_NAV_PS_DATA_SIZE, 1484 AM65_CPSW_NAV_SW_DATA_SIZE); 1485 1486 tx_cfg.swdata_size = AM65_CPSW_NAV_SW_DATA_SIZE; 1487 tx_cfg.tx_cfg = ring_cfg; 1488 tx_cfg.txcq_cfg = ring_cfg; 1489 tx_cfg.tx_cfg.size = max_desc_num; 1490 tx_cfg.txcq_cfg.size = max_desc_num; 1491 1492 for (i = 0; i < common->tx_ch_num; i++) { 1493 struct am65_cpsw_tx_chn *tx_chn = &common->tx_chns[i]; 1494 1495 snprintf(tx_chn->tx_chn_name, 1496 sizeof(tx_chn->tx_chn_name), "tx%d", i); 1497 1498 tx_chn->common = common; 1499 tx_chn->id = i; 1500 tx_chn->descs_num = max_desc_num; 1501 tx_chn->desc_pool = 1502 k3_cppi_desc_pool_create_name(dev, 1503 tx_chn->descs_num, 1504 hdesc_size, 1505 tx_chn->tx_chn_name); 1506 if (IS_ERR(tx_chn->desc_pool)) { 1507 ret = PTR_ERR(tx_chn->desc_pool); 1508 dev_err(dev, "Failed to create poll %d\n", ret); 1509 goto err; 1510 } 1511 1512 tx_chn->tx_chn = 1513 k3_udma_glue_request_tx_chn(dev, 1514 tx_chn->tx_chn_name, 1515 &tx_cfg); 1516 if (IS_ERR(tx_chn->tx_chn)) { 1517 ret = PTR_ERR(tx_chn->tx_chn); 1518 dev_err(dev, "Failed to request tx dma channel %d\n", 1519 ret); 1520 goto err; 1521 } 1522 1523 tx_chn->irq = k3_udma_glue_tx_get_irq(tx_chn->tx_chn); 1524 if (tx_chn->irq <= 0) { 1525 dev_err(dev, "Failed to get tx dma irq %d\n", 1526 tx_chn->irq); 1527 goto err; 1528 } 1529 1530 snprintf(tx_chn->tx_chn_name, 1531 sizeof(tx_chn->tx_chn_name), "%s-tx%d", 1532 dev_name(dev), tx_chn->id); 1533 } 1534 1535 err: 1536 i = devm_add_action(dev, am65_cpsw_nuss_free_tx_chns, common); 1537 if (i) { 1538 dev_err(dev, "Failed to add free_tx_chns action %d\n", i); 1539 return i; 1540 } 1541 1542 return ret; 1543 } 1544 1545 static void am65_cpsw_nuss_free_rx_chns(void *data) 1546 { 1547 struct am65_cpsw_common *common = data; 1548 struct am65_cpsw_rx_chn *rx_chn; 1549 1550 rx_chn = &common->rx_chns; 1551 1552 if (!IS_ERR_OR_NULL(rx_chn->rx_chn)) 1553 k3_udma_glue_release_rx_chn(rx_chn->rx_chn); 1554 1555 if (!IS_ERR_OR_NULL(rx_chn->desc_pool)) 1556 k3_cppi_desc_pool_destroy(rx_chn->desc_pool); 1557 } 1558 1559 static int am65_cpsw_nuss_init_rx_chns(struct am65_cpsw_common *common) 1560 { 1561 struct am65_cpsw_rx_chn *rx_chn = &common->rx_chns; 1562 struct k3_udma_glue_rx_channel_cfg rx_cfg = { 0 }; 1563 u32 max_desc_num = AM65_CPSW_MAX_RX_DESC; 1564 struct device *dev = common->dev; 1565 u32 hdesc_size; 1566 u32 fdqring_id; 1567 int i, ret = 0; 1568 1569 hdesc_size = cppi5_hdesc_calc_size(true, AM65_CPSW_NAV_PS_DATA_SIZE, 1570 AM65_CPSW_NAV_SW_DATA_SIZE); 1571 1572 rx_cfg.swdata_size = AM65_CPSW_NAV_SW_DATA_SIZE; 1573 rx_cfg.flow_id_num = AM65_CPSW_MAX_RX_FLOWS; 1574 rx_cfg.flow_id_base = common->rx_flow_id_base; 1575 1576 /* init all flows */ 1577 rx_chn->dev = dev; 1578 rx_chn->descs_num = max_desc_num; 1579 rx_chn->desc_pool = k3_cppi_desc_pool_create_name(dev, 1580 rx_chn->descs_num, 1581 hdesc_size, "rx"); 1582 if (IS_ERR(rx_chn->desc_pool)) { 1583 ret = PTR_ERR(rx_chn->desc_pool); 1584 dev_err(dev, "Failed to create rx poll %d\n", ret); 1585 goto err; 1586 } 1587 1588 rx_chn->rx_chn = k3_udma_glue_request_rx_chn(dev, "rx", &rx_cfg); 1589 if (IS_ERR(rx_chn->rx_chn)) { 1590 ret = PTR_ERR(rx_chn->rx_chn); 1591 dev_err(dev, "Failed to request rx dma channel %d\n", ret); 1592 goto err; 1593 } 1594 1595 common->rx_flow_id_base = 1596 k3_udma_glue_rx_get_flow_id_base(rx_chn->rx_chn); 1597 dev_info(dev, "set new flow-id-base %u\n", common->rx_flow_id_base); 1598 1599 fdqring_id = K3_RINGACC_RING_ID_ANY; 1600 for (i = 0; i < rx_cfg.flow_id_num; i++) { 1601 struct k3_ring_cfg rxring_cfg = { 1602 .elm_size = K3_RINGACC_RING_ELSIZE_8, 1603 .mode = K3_RINGACC_RING_MODE_RING, 1604 .flags = 0, 1605 }; 1606 struct k3_ring_cfg fdqring_cfg = { 1607 .elm_size = K3_RINGACC_RING_ELSIZE_8, 1608 .mode = K3_RINGACC_RING_MODE_MESSAGE, 1609 .flags = K3_RINGACC_RING_SHARED, 1610 }; 1611 struct k3_udma_glue_rx_flow_cfg rx_flow_cfg = { 1612 .rx_cfg = rxring_cfg, 1613 .rxfdq_cfg = fdqring_cfg, 1614 .ring_rxq_id = K3_RINGACC_RING_ID_ANY, 1615 .src_tag_lo_sel = 1616 K3_UDMA_GLUE_SRC_TAG_LO_USE_REMOTE_SRC_TAG, 1617 }; 1618 1619 rx_flow_cfg.ring_rxfdq0_id = fdqring_id; 1620 rx_flow_cfg.rx_cfg.size = max_desc_num; 1621 rx_flow_cfg.rxfdq_cfg.size = max_desc_num; 1622 1623 ret = k3_udma_glue_rx_flow_init(rx_chn->rx_chn, 1624 i, &rx_flow_cfg); 1625 if (ret) { 1626 dev_err(dev, "Failed to init rx flow%d %d\n", i, ret); 1627 goto err; 1628 } 1629 if (!i) 1630 fdqring_id = 1631 k3_udma_glue_rx_flow_get_fdq_id(rx_chn->rx_chn, 1632 i); 1633 1634 rx_chn->irq = k3_udma_glue_rx_get_irq(rx_chn->rx_chn, i); 1635 1636 if (rx_chn->irq <= 0) { 1637 dev_err(dev, "Failed to get rx dma irq %d\n", 1638 rx_chn->irq); 1639 ret = -ENXIO; 1640 goto err; 1641 } 1642 } 1643 1644 err: 1645 i = devm_add_action(dev, am65_cpsw_nuss_free_rx_chns, common); 1646 if (i) { 1647 dev_err(dev, "Failed to add free_rx_chns action %d\n", i); 1648 return i; 1649 } 1650 1651 return ret; 1652 } 1653 1654 static int am65_cpsw_nuss_init_host_p(struct am65_cpsw_common *common) 1655 { 1656 struct am65_cpsw_host *host_p = am65_common_get_host(common); 1657 1658 host_p->common = common; 1659 host_p->port_base = common->cpsw_base + AM65_CPSW_NU_PORTS_BASE; 1660 host_p->stat_base = common->cpsw_base + AM65_CPSW_NU_STATS_BASE; 1661 1662 return 0; 1663 } 1664 1665 static int am65_cpsw_am654_get_efuse_macid(struct device_node *of_node, 1666 int slave, u8 *mac_addr) 1667 { 1668 u32 mac_lo, mac_hi, offset; 1669 struct regmap *syscon; 1670 int ret; 1671 1672 syscon = syscon_regmap_lookup_by_phandle(of_node, "ti,syscon-efuse"); 1673 if (IS_ERR(syscon)) { 1674 if (PTR_ERR(syscon) == -ENODEV) 1675 return 0; 1676 return PTR_ERR(syscon); 1677 } 1678 1679 ret = of_property_read_u32_index(of_node, "ti,syscon-efuse", 1, 1680 &offset); 1681 if (ret) 1682 return ret; 1683 1684 regmap_read(syscon, offset, &mac_lo); 1685 regmap_read(syscon, offset + 4, &mac_hi); 1686 1687 mac_addr[0] = (mac_hi >> 8) & 0xff; 1688 mac_addr[1] = mac_hi & 0xff; 1689 mac_addr[2] = (mac_lo >> 24) & 0xff; 1690 mac_addr[3] = (mac_lo >> 16) & 0xff; 1691 mac_addr[4] = (mac_lo >> 8) & 0xff; 1692 mac_addr[5] = mac_lo & 0xff; 1693 1694 return 0; 1695 } 1696 1697 static int am65_cpsw_init_cpts(struct am65_cpsw_common *common) 1698 { 1699 struct device *dev = common->dev; 1700 struct device_node *node; 1701 struct am65_cpts *cpts; 1702 void __iomem *reg_base; 1703 1704 if (!IS_ENABLED(CONFIG_TI_K3_AM65_CPTS)) 1705 return 0; 1706 1707 node = of_get_child_by_name(dev->of_node, "cpts"); 1708 if (!node) { 1709 dev_err(dev, "%s cpts not found\n", __func__); 1710 return -ENOENT; 1711 } 1712 1713 reg_base = common->cpsw_base + AM65_CPSW_NU_CPTS_BASE; 1714 cpts = am65_cpts_create(dev, reg_base, node); 1715 if (IS_ERR(cpts)) { 1716 int ret = PTR_ERR(cpts); 1717 1718 if (ret == -EOPNOTSUPP) { 1719 dev_info(dev, "cpts disabled\n"); 1720 return 0; 1721 } 1722 1723 dev_err(dev, "cpts create err %d\n", ret); 1724 return ret; 1725 } 1726 common->cpts = cpts; 1727 1728 return 0; 1729 } 1730 1731 static int am65_cpsw_nuss_init_slave_ports(struct am65_cpsw_common *common) 1732 { 1733 struct device_node *node, *port_np; 1734 struct device *dev = common->dev; 1735 int ret; 1736 1737 node = of_get_child_by_name(dev->of_node, "ethernet-ports"); 1738 if (!node) 1739 return -ENOENT; 1740 1741 for_each_child_of_node(node, port_np) { 1742 struct am65_cpsw_port *port; 1743 const void *mac_addr; 1744 u32 port_id; 1745 1746 /* it is not a slave port node, continue */ 1747 if (strcmp(port_np->name, "port")) 1748 continue; 1749 1750 ret = of_property_read_u32(port_np, "reg", &port_id); 1751 if (ret < 0) { 1752 dev_err(dev, "%pOF error reading port_id %d\n", 1753 port_np, ret); 1754 return ret; 1755 } 1756 1757 if (!port_id || port_id > common->port_num) { 1758 dev_err(dev, "%pOF has invalid port_id %u %s\n", 1759 port_np, port_id, port_np->name); 1760 return -EINVAL; 1761 } 1762 1763 port = am65_common_get_port(common, port_id); 1764 port->port_id = port_id; 1765 port->common = common; 1766 port->port_base = common->cpsw_base + AM65_CPSW_NU_PORTS_BASE + 1767 AM65_CPSW_NU_PORTS_OFFSET * (port_id); 1768 port->stat_base = common->cpsw_base + AM65_CPSW_NU_STATS_BASE + 1769 (AM65_CPSW_NU_STATS_PORT_OFFSET * port_id); 1770 port->name = of_get_property(port_np, "label", NULL); 1771 port->fetch_ram_base = 1772 common->cpsw_base + AM65_CPSW_NU_FRAM_BASE + 1773 (AM65_CPSW_NU_FRAM_PORT_OFFSET * (port_id - 1)); 1774 1775 port->slave.mac_sl = cpsw_sl_get("am65", dev, port->port_base); 1776 if (IS_ERR(port->slave.mac_sl)) 1777 return PTR_ERR(port->slave.mac_sl); 1778 1779 port->disabled = !of_device_is_available(port_np); 1780 if (port->disabled) 1781 continue; 1782 1783 port->slave.ifphy = devm_of_phy_get(dev, port_np, NULL); 1784 if (IS_ERR(port->slave.ifphy)) { 1785 ret = PTR_ERR(port->slave.ifphy); 1786 dev_err(dev, "%pOF error retrieving port phy: %d\n", 1787 port_np, ret); 1788 return ret; 1789 } 1790 1791 port->slave.mac_only = 1792 of_property_read_bool(port_np, "ti,mac-only"); 1793 1794 /* get phy/link info */ 1795 if (of_phy_is_fixed_link(port_np)) { 1796 ret = of_phy_register_fixed_link(port_np); 1797 if (ret) { 1798 if (ret != -EPROBE_DEFER) 1799 dev_err(dev, "%pOF failed to register fixed-link phy: %d\n", 1800 port_np, ret); 1801 return ret; 1802 } 1803 port->slave.phy_node = of_node_get(port_np); 1804 } else { 1805 port->slave.phy_node = 1806 of_parse_phandle(port_np, "phy-handle", 0); 1807 } 1808 1809 if (!port->slave.phy_node) { 1810 dev_err(dev, 1811 "slave[%d] no phy found\n", port_id); 1812 return -ENODEV; 1813 } 1814 1815 ret = of_get_phy_mode(port_np, &port->slave.phy_if); 1816 if (ret) { 1817 dev_err(dev, "%pOF read phy-mode err %d\n", 1818 port_np, ret); 1819 return ret; 1820 } 1821 1822 mac_addr = of_get_mac_address(port_np); 1823 if (!IS_ERR(mac_addr)) { 1824 ether_addr_copy(port->slave.mac_addr, mac_addr); 1825 } else if (am65_cpsw_am654_get_efuse_macid(port_np, 1826 port->port_id, 1827 port->slave.mac_addr) || 1828 !is_valid_ether_addr(port->slave.mac_addr)) { 1829 random_ether_addr(port->slave.mac_addr); 1830 dev_err(dev, "Use random MAC address\n"); 1831 } 1832 } 1833 of_node_put(node); 1834 1835 return 0; 1836 } 1837 1838 static void am65_cpsw_pcpu_stats_free(void *data) 1839 { 1840 struct am65_cpsw_ndev_stats __percpu *stats = data; 1841 1842 free_percpu(stats); 1843 } 1844 1845 static int am65_cpsw_nuss_init_ndev_2g(struct am65_cpsw_common *common) 1846 { 1847 struct am65_cpsw_ndev_priv *ndev_priv; 1848 struct device *dev = common->dev; 1849 struct am65_cpsw_port *port; 1850 int ret; 1851 1852 port = am65_common_get_port(common, 1); 1853 1854 /* alloc netdev */ 1855 port->ndev = devm_alloc_etherdev_mqs(common->dev, 1856 sizeof(struct am65_cpsw_ndev_priv), 1857 AM65_CPSW_MAX_TX_QUEUES, 1858 AM65_CPSW_MAX_RX_QUEUES); 1859 if (!port->ndev) { 1860 dev_err(dev, "error allocating slave net_device %u\n", 1861 port->port_id); 1862 return -ENOMEM; 1863 } 1864 1865 ndev_priv = netdev_priv(port->ndev); 1866 ndev_priv->port = port; 1867 ndev_priv->msg_enable = AM65_CPSW_DEBUG; 1868 SET_NETDEV_DEV(port->ndev, dev); 1869 1870 ether_addr_copy(port->ndev->dev_addr, port->slave.mac_addr); 1871 1872 port->ndev->min_mtu = AM65_CPSW_MIN_PACKET_SIZE; 1873 port->ndev->max_mtu = AM65_CPSW_MAX_PACKET_SIZE; 1874 port->ndev->hw_features = NETIF_F_SG | 1875 NETIF_F_RXCSUM | 1876 NETIF_F_HW_CSUM | 1877 NETIF_F_HW_TC; 1878 port->ndev->features = port->ndev->hw_features | 1879 NETIF_F_HW_VLAN_CTAG_FILTER; 1880 port->ndev->vlan_features |= NETIF_F_SG; 1881 port->ndev->netdev_ops = &am65_cpsw_nuss_netdev_ops_2g; 1882 port->ndev->ethtool_ops = &am65_cpsw_ethtool_ops_slave; 1883 1884 /* Disable TX checksum offload by default due to HW bug */ 1885 if (common->pdata.quirks & AM65_CPSW_QUIRK_I2027_NO_TX_CSUM) 1886 port->ndev->features &= ~NETIF_F_HW_CSUM; 1887 1888 ndev_priv->stats = netdev_alloc_pcpu_stats(struct am65_cpsw_ndev_stats); 1889 if (!ndev_priv->stats) 1890 return -ENOMEM; 1891 1892 ret = devm_add_action_or_reset(dev, am65_cpsw_pcpu_stats_free, 1893 ndev_priv->stats); 1894 if (ret) { 1895 dev_err(dev, "Failed to add percpu stat free action %d\n", ret); 1896 return ret; 1897 } 1898 1899 netif_napi_add(port->ndev, &common->napi_rx, 1900 am65_cpsw_nuss_rx_poll, NAPI_POLL_WEIGHT); 1901 1902 return ret; 1903 } 1904 1905 static int am65_cpsw_nuss_ndev_add_napi_2g(struct am65_cpsw_common *common) 1906 { 1907 struct device *dev = common->dev; 1908 struct am65_cpsw_port *port; 1909 int i, ret = 0; 1910 1911 port = am65_common_get_port(common, 1); 1912 1913 for (i = 0; i < common->tx_ch_num; i++) { 1914 struct am65_cpsw_tx_chn *tx_chn = &common->tx_chns[i]; 1915 1916 netif_tx_napi_add(port->ndev, &tx_chn->napi_tx, 1917 am65_cpsw_nuss_tx_poll, NAPI_POLL_WEIGHT); 1918 1919 ret = devm_request_irq(dev, tx_chn->irq, 1920 am65_cpsw_nuss_tx_irq, 1921 IRQF_TRIGGER_HIGH, 1922 tx_chn->tx_chn_name, tx_chn); 1923 if (ret) { 1924 dev_err(dev, "failure requesting tx%u irq %u, %d\n", 1925 tx_chn->id, tx_chn->irq, ret); 1926 goto err; 1927 } 1928 } 1929 1930 err: 1931 return ret; 1932 } 1933 1934 static int am65_cpsw_nuss_ndev_reg_2g(struct am65_cpsw_common *common) 1935 { 1936 struct device *dev = common->dev; 1937 struct am65_cpsw_port *port; 1938 int ret = 0; 1939 1940 port = am65_common_get_port(common, 1); 1941 ret = am65_cpsw_nuss_ndev_add_napi_2g(common); 1942 if (ret) 1943 goto err; 1944 1945 ret = devm_request_irq(dev, common->rx_chns.irq, 1946 am65_cpsw_nuss_rx_irq, 1947 IRQF_TRIGGER_HIGH, dev_name(dev), common); 1948 if (ret) { 1949 dev_err(dev, "failure requesting rx irq %u, %d\n", 1950 common->rx_chns.irq, ret); 1951 goto err; 1952 } 1953 1954 ret = register_netdev(port->ndev); 1955 if (ret) 1956 dev_err(dev, "error registering slave net device %d\n", ret); 1957 1958 /* can't auto unregister ndev using devm_add_action() due to 1959 * devres release sequence in DD core for DMA 1960 */ 1961 err: 1962 return ret; 1963 } 1964 1965 int am65_cpsw_nuss_update_tx_chns(struct am65_cpsw_common *common, int num_tx) 1966 { 1967 int ret; 1968 1969 common->tx_ch_num = num_tx; 1970 ret = am65_cpsw_nuss_init_tx_chns(common); 1971 if (ret) 1972 return ret; 1973 1974 return am65_cpsw_nuss_ndev_add_napi_2g(common); 1975 } 1976 1977 static void am65_cpsw_nuss_cleanup_ndev(struct am65_cpsw_common *common) 1978 { 1979 struct am65_cpsw_port *port; 1980 int i; 1981 1982 for (i = 0; i < common->port_num; i++) { 1983 port = &common->ports[i]; 1984 if (port->ndev) 1985 unregister_netdev(port->ndev); 1986 } 1987 } 1988 1989 struct am65_cpsw_soc_pdata { 1990 u32 quirks_dis; 1991 }; 1992 1993 static const struct am65_cpsw_soc_pdata am65x_soc_sr2_0 = { 1994 .quirks_dis = AM65_CPSW_QUIRK_I2027_NO_TX_CSUM, 1995 }; 1996 1997 static const struct soc_device_attribute am65_cpsw_socinfo[] = { 1998 { .family = "AM65X", 1999 .revision = "SR2.0", 2000 .data = &am65x_soc_sr2_0 2001 }, 2002 {/* sentinel */} 2003 }; 2004 2005 static const struct am65_cpsw_pdata am65x_sr1_0 = { 2006 .quirks = AM65_CPSW_QUIRK_I2027_NO_TX_CSUM, 2007 }; 2008 2009 static const struct am65_cpsw_pdata j721e_pdata = { 2010 .quirks = 0, 2011 }; 2012 2013 static const struct of_device_id am65_cpsw_nuss_of_mtable[] = { 2014 { .compatible = "ti,am654-cpsw-nuss", .data = &am65x_sr1_0}, 2015 { .compatible = "ti,j721e-cpsw-nuss", .data = &j721e_pdata}, 2016 { /* sentinel */ }, 2017 }; 2018 MODULE_DEVICE_TABLE(of, am65_cpsw_nuss_of_mtable); 2019 2020 static void am65_cpsw_nuss_apply_socinfo(struct am65_cpsw_common *common) 2021 { 2022 const struct soc_device_attribute *soc; 2023 2024 soc = soc_device_match(am65_cpsw_socinfo); 2025 if (soc && soc->data) { 2026 const struct am65_cpsw_soc_pdata *socdata = soc->data; 2027 2028 /* disable quirks */ 2029 common->pdata.quirks &= ~socdata->quirks_dis; 2030 } 2031 } 2032 2033 static int am65_cpsw_nuss_probe(struct platform_device *pdev) 2034 { 2035 struct cpsw_ale_params ale_params = { 0 }; 2036 const struct of_device_id *of_id; 2037 struct device *dev = &pdev->dev; 2038 struct am65_cpsw_common *common; 2039 struct device_node *node; 2040 struct resource *res; 2041 int ret, i; 2042 2043 common = devm_kzalloc(dev, sizeof(struct am65_cpsw_common), GFP_KERNEL); 2044 if (!common) 2045 return -ENOMEM; 2046 common->dev = dev; 2047 2048 of_id = of_match_device(am65_cpsw_nuss_of_mtable, dev); 2049 if (!of_id) 2050 return -EINVAL; 2051 common->pdata = *(const struct am65_cpsw_pdata *)of_id->data; 2052 2053 am65_cpsw_nuss_apply_socinfo(common); 2054 2055 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cpsw_nuss"); 2056 common->ss_base = devm_ioremap_resource(&pdev->dev, res); 2057 if (IS_ERR(common->ss_base)) 2058 return PTR_ERR(common->ss_base); 2059 common->cpsw_base = common->ss_base + AM65_CPSW_CPSW_NU_BASE; 2060 2061 node = of_get_child_by_name(dev->of_node, "ethernet-ports"); 2062 if (!node) 2063 return -ENOENT; 2064 common->port_num = of_get_child_count(node); 2065 if (common->port_num < 1 || common->port_num > AM65_CPSW_MAX_PORTS) 2066 return -ENOENT; 2067 of_node_put(node); 2068 2069 if (common->port_num != 1) 2070 return -EOPNOTSUPP; 2071 2072 common->rx_flow_id_base = -1; 2073 init_completion(&common->tdown_complete); 2074 common->tx_ch_num = 1; 2075 common->pf_p0_rx_ptype_rrobin = false; 2076 2077 ret = dma_coerce_mask_and_coherent(dev, DMA_BIT_MASK(48)); 2078 if (ret) { 2079 dev_err(dev, "error setting dma mask: %d\n", ret); 2080 return ret; 2081 } 2082 2083 common->ports = devm_kcalloc(dev, common->port_num, 2084 sizeof(*common->ports), 2085 GFP_KERNEL); 2086 if (!common->ports) 2087 return -ENOMEM; 2088 2089 pm_runtime_enable(dev); 2090 ret = pm_runtime_get_sync(dev); 2091 if (ret < 0) { 2092 pm_runtime_put_noidle(dev); 2093 pm_runtime_disable(dev); 2094 return ret; 2095 } 2096 2097 node = of_get_child_by_name(dev->of_node, "mdio"); 2098 if (!node) { 2099 dev_warn(dev, "MDIO node not found\n"); 2100 } else if (of_device_is_available(node)) { 2101 struct platform_device *mdio_pdev; 2102 2103 mdio_pdev = of_platform_device_create(node, NULL, dev); 2104 if (!mdio_pdev) { 2105 ret = -ENODEV; 2106 goto err_pm_clear; 2107 } 2108 2109 common->mdio_dev = &mdio_pdev->dev; 2110 } 2111 of_node_put(node); 2112 2113 am65_cpsw_nuss_get_ver(common); 2114 2115 /* init tx channels */ 2116 ret = am65_cpsw_nuss_init_tx_chns(common); 2117 if (ret) 2118 goto err_of_clear; 2119 ret = am65_cpsw_nuss_init_rx_chns(common); 2120 if (ret) 2121 goto err_of_clear; 2122 2123 ret = am65_cpsw_nuss_init_host_p(common); 2124 if (ret) 2125 goto err_of_clear; 2126 2127 ret = am65_cpsw_nuss_init_slave_ports(common); 2128 if (ret) 2129 goto err_of_clear; 2130 2131 /* init common data */ 2132 ale_params.dev = dev; 2133 ale_params.ale_ageout = AM65_CPSW_ALE_AGEOUT_DEFAULT; 2134 ale_params.ale_entries = 0; 2135 ale_params.ale_ports = common->port_num + 1; 2136 ale_params.ale_regs = common->cpsw_base + AM65_CPSW_NU_ALE_BASE; 2137 ale_params.nu_switch_ale = true; 2138 2139 common->ale = cpsw_ale_create(&ale_params); 2140 if (IS_ERR(common->ale)) { 2141 dev_err(dev, "error initializing ale engine\n"); 2142 ret = PTR_ERR(common->ale); 2143 goto err_of_clear; 2144 } 2145 2146 ret = am65_cpsw_init_cpts(common); 2147 if (ret) 2148 goto err_of_clear; 2149 2150 /* init ports */ 2151 for (i = 0; i < common->port_num; i++) 2152 am65_cpsw_nuss_slave_disable_unused(&common->ports[i]); 2153 2154 dev_set_drvdata(dev, common); 2155 2156 ret = am65_cpsw_nuss_init_ndev_2g(common); 2157 if (ret) 2158 goto err_of_clear; 2159 2160 ret = am65_cpsw_nuss_ndev_reg_2g(common); 2161 if (ret) 2162 goto err_of_clear; 2163 2164 pm_runtime_put(dev); 2165 return 0; 2166 2167 err_of_clear: 2168 of_platform_device_destroy(common->mdio_dev, NULL); 2169 err_pm_clear: 2170 pm_runtime_put_sync(dev); 2171 pm_runtime_disable(dev); 2172 return ret; 2173 } 2174 2175 static int am65_cpsw_nuss_remove(struct platform_device *pdev) 2176 { 2177 struct device *dev = &pdev->dev; 2178 struct am65_cpsw_common *common; 2179 int ret; 2180 2181 common = dev_get_drvdata(dev); 2182 2183 ret = pm_runtime_get_sync(&pdev->dev); 2184 if (ret < 0) { 2185 pm_runtime_put_noidle(&pdev->dev); 2186 return ret; 2187 } 2188 2189 /* must unregister ndevs here because DD release_driver routine calls 2190 * dma_deconfigure(dev) before devres_release_all(dev) 2191 */ 2192 am65_cpsw_nuss_cleanup_ndev(common); 2193 2194 of_platform_device_destroy(common->mdio_dev, NULL); 2195 2196 pm_runtime_put_sync(&pdev->dev); 2197 pm_runtime_disable(&pdev->dev); 2198 return 0; 2199 } 2200 2201 static struct platform_driver am65_cpsw_nuss_driver = { 2202 .driver = { 2203 .name = AM65_CPSW_DRV_NAME, 2204 .of_match_table = am65_cpsw_nuss_of_mtable, 2205 }, 2206 .probe = am65_cpsw_nuss_probe, 2207 .remove = am65_cpsw_nuss_remove, 2208 }; 2209 2210 module_platform_driver(am65_cpsw_nuss_driver); 2211 2212 MODULE_LICENSE("GPL v2"); 2213 MODULE_AUTHOR("Grygorii Strashko <grygorii.strashko@ti.com>"); 2214 MODULE_DESCRIPTION("TI AM65 CPSW Ethernet driver"); 2215