1 // SPDX-License-Identifier: GPL-2.0 2 /* Texas Instruments K3 AM65 Ethernet Switch SubSystem Driver 3 * 4 * Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/ 5 * 6 */ 7 8 #include <linux/clk.h> 9 #include <linux/etherdevice.h> 10 #include <linux/if_vlan.h> 11 #include <linux/interrupt.h> 12 #include <linux/irqdomain.h> 13 #include <linux/kernel.h> 14 #include <linux/kmemleak.h> 15 #include <linux/module.h> 16 #include <linux/netdevice.h> 17 #include <linux/net_tstamp.h> 18 #include <linux/of.h> 19 #include <linux/of_mdio.h> 20 #include <linux/of_net.h> 21 #include <linux/of_device.h> 22 #include <linux/phylink.h> 23 #include <linux/phy/phy.h> 24 #include <linux/platform_device.h> 25 #include <linux/pm_runtime.h> 26 #include <linux/regmap.h> 27 #include <linux/rtnetlink.h> 28 #include <linux/mfd/syscon.h> 29 #include <linux/sys_soc.h> 30 #include <linux/dma/ti-cppi5.h> 31 #include <linux/dma/k3-udma-glue.h> 32 #include <net/switchdev.h> 33 34 #include "cpsw_ale.h" 35 #include "cpsw_sl.h" 36 #include "am65-cpsw-nuss.h" 37 #include "am65-cpsw-switchdev.h" 38 #include "k3-cppi-desc-pool.h" 39 #include "am65-cpts.h" 40 41 #define AM65_CPSW_SS_BASE 0x0 42 #define AM65_CPSW_SGMII_BASE 0x100 43 #define AM65_CPSW_XGMII_BASE 0x2100 44 #define AM65_CPSW_CPSW_NU_BASE 0x20000 45 #define AM65_CPSW_NU_PORTS_BASE 0x1000 46 #define AM65_CPSW_NU_FRAM_BASE 0x12000 47 #define AM65_CPSW_NU_STATS_BASE 0x1a000 48 #define AM65_CPSW_NU_ALE_BASE 0x1e000 49 #define AM65_CPSW_NU_CPTS_BASE 0x1d000 50 51 #define AM65_CPSW_NU_PORTS_OFFSET 0x1000 52 #define AM65_CPSW_NU_STATS_PORT_OFFSET 0x200 53 #define AM65_CPSW_NU_FRAM_PORT_OFFSET 0x200 54 55 #define AM65_CPSW_MAX_PORTS 8 56 57 #define AM65_CPSW_MIN_PACKET_SIZE VLAN_ETH_ZLEN 58 #define AM65_CPSW_MAX_PACKET_SIZE (VLAN_ETH_FRAME_LEN + ETH_FCS_LEN) 59 60 #define AM65_CPSW_REG_CTL 0x004 61 #define AM65_CPSW_REG_STAT_PORT_EN 0x014 62 #define AM65_CPSW_REG_PTYPE 0x018 63 64 #define AM65_CPSW_P0_REG_CTL 0x004 65 #define AM65_CPSW_PORT0_REG_FLOW_ID_OFFSET 0x008 66 67 #define AM65_CPSW_PORT_REG_PRI_CTL 0x01c 68 #define AM65_CPSW_PORT_REG_RX_PRI_MAP 0x020 69 #define AM65_CPSW_PORT_REG_RX_MAXLEN 0x024 70 71 #define AM65_CPSW_PORTN_REG_SA_L 0x308 72 #define AM65_CPSW_PORTN_REG_SA_H 0x30c 73 #define AM65_CPSW_PORTN_REG_TS_CTL 0x310 74 #define AM65_CPSW_PORTN_REG_TS_SEQ_LTYPE_REG 0x314 75 #define AM65_CPSW_PORTN_REG_TS_VLAN_LTYPE_REG 0x318 76 #define AM65_CPSW_PORTN_REG_TS_CTL_LTYPE2 0x31C 77 78 #define AM65_CPSW_SGMII_CONTROL_REG 0x010 79 #define AM65_CPSW_SGMII_CONTROL_MR_AN_ENABLE BIT(0) 80 81 #define AM65_CPSW_CTL_VLAN_AWARE BIT(1) 82 #define AM65_CPSW_CTL_P0_ENABLE BIT(2) 83 #define AM65_CPSW_CTL_P0_TX_CRC_REMOVE BIT(13) 84 #define AM65_CPSW_CTL_P0_RX_PAD BIT(14) 85 86 /* AM65_CPSW_P0_REG_CTL */ 87 #define AM65_CPSW_P0_REG_CTL_RX_CHECKSUM_EN BIT(0) 88 89 /* AM65_CPSW_PORT_REG_PRI_CTL */ 90 #define AM65_CPSW_PORT_REG_PRI_CTL_RX_PTYPE_RROBIN BIT(8) 91 92 /* AM65_CPSW_PN_TS_CTL register fields */ 93 #define AM65_CPSW_PN_TS_CTL_TX_ANX_F_EN BIT(4) 94 #define AM65_CPSW_PN_TS_CTL_TX_VLAN_LT1_EN BIT(5) 95 #define AM65_CPSW_PN_TS_CTL_TX_VLAN_LT2_EN BIT(6) 96 #define AM65_CPSW_PN_TS_CTL_TX_ANX_D_EN BIT(7) 97 #define AM65_CPSW_PN_TS_CTL_TX_ANX_E_EN BIT(10) 98 #define AM65_CPSW_PN_TS_CTL_TX_HOST_TS_EN BIT(11) 99 #define AM65_CPSW_PN_TS_CTL_MSG_TYPE_EN_SHIFT 16 100 101 /* AM65_CPSW_PORTN_REG_TS_SEQ_LTYPE_REG register fields */ 102 #define AM65_CPSW_PN_TS_SEQ_ID_OFFSET_SHIFT 16 103 104 /* AM65_CPSW_PORTN_REG_TS_CTL_LTYPE2 */ 105 #define AM65_CPSW_PN_TS_CTL_LTYPE2_TS_107 BIT(16) 106 #define AM65_CPSW_PN_TS_CTL_LTYPE2_TS_129 BIT(17) 107 #define AM65_CPSW_PN_TS_CTL_LTYPE2_TS_130 BIT(18) 108 #define AM65_CPSW_PN_TS_CTL_LTYPE2_TS_131 BIT(19) 109 #define AM65_CPSW_PN_TS_CTL_LTYPE2_TS_132 BIT(20) 110 #define AM65_CPSW_PN_TS_CTL_LTYPE2_TS_319 BIT(21) 111 #define AM65_CPSW_PN_TS_CTL_LTYPE2_TS_320 BIT(22) 112 #define AM65_CPSW_PN_TS_CTL_LTYPE2_TS_TTL_NONZERO BIT(23) 113 114 /* The PTP event messages - Sync, Delay_Req, Pdelay_Req, and Pdelay_Resp. */ 115 #define AM65_CPSW_TS_EVENT_MSG_TYPE_BITS (BIT(0) | BIT(1) | BIT(2) | BIT(3)) 116 117 #define AM65_CPSW_TS_SEQ_ID_OFFSET (0x1e) 118 119 #define AM65_CPSW_TS_TX_ANX_ALL_EN \ 120 (AM65_CPSW_PN_TS_CTL_TX_ANX_D_EN | \ 121 AM65_CPSW_PN_TS_CTL_TX_ANX_E_EN | \ 122 AM65_CPSW_PN_TS_CTL_TX_ANX_F_EN) 123 124 #define AM65_CPSW_ALE_AGEOUT_DEFAULT 30 125 /* Number of TX/RX descriptors */ 126 #define AM65_CPSW_MAX_TX_DESC 500 127 #define AM65_CPSW_MAX_RX_DESC 500 128 129 #define AM65_CPSW_NAV_PS_DATA_SIZE 16 130 #define AM65_CPSW_NAV_SW_DATA_SIZE 16 131 132 #define AM65_CPSW_DEBUG (NETIF_MSG_HW | NETIF_MSG_DRV | NETIF_MSG_LINK | \ 133 NETIF_MSG_IFUP | NETIF_MSG_PROBE | NETIF_MSG_IFDOWN | \ 134 NETIF_MSG_RX_ERR | NETIF_MSG_TX_ERR) 135 136 static int am65_cpsw_nuss_init_tx_chns(struct am65_cpsw_common *common); 137 static int am65_cpsw_nuss_init_rx_chns(struct am65_cpsw_common *common); 138 static void am65_cpsw_nuss_free_tx_chns(struct am65_cpsw_common *common); 139 static void am65_cpsw_nuss_free_rx_chns(struct am65_cpsw_common *common); 140 141 static void am65_cpsw_port_set_sl_mac(struct am65_cpsw_port *slave, 142 const u8 *dev_addr) 143 { 144 u32 mac_hi = (dev_addr[0] << 0) | (dev_addr[1] << 8) | 145 (dev_addr[2] << 16) | (dev_addr[3] << 24); 146 u32 mac_lo = (dev_addr[4] << 0) | (dev_addr[5] << 8); 147 148 writel(mac_hi, slave->port_base + AM65_CPSW_PORTN_REG_SA_H); 149 writel(mac_lo, slave->port_base + AM65_CPSW_PORTN_REG_SA_L); 150 } 151 152 static void am65_cpsw_sl_ctl_reset(struct am65_cpsw_port *port) 153 { 154 cpsw_sl_reset(port->slave.mac_sl, 100); 155 /* Max length register has to be restored after MAC SL reset */ 156 writel(AM65_CPSW_MAX_PACKET_SIZE, 157 port->port_base + AM65_CPSW_PORT_REG_RX_MAXLEN); 158 } 159 160 static void am65_cpsw_nuss_get_ver(struct am65_cpsw_common *common) 161 { 162 common->nuss_ver = readl(common->ss_base); 163 common->cpsw_ver = readl(common->cpsw_base); 164 dev_info(common->dev, 165 "initializing am65 cpsw nuss version 0x%08X, cpsw version 0x%08X Ports: %u quirks:%08x\n", 166 common->nuss_ver, 167 common->cpsw_ver, 168 common->port_num + 1, 169 common->pdata.quirks); 170 } 171 172 static int am65_cpsw_nuss_ndo_slave_add_vid(struct net_device *ndev, 173 __be16 proto, u16 vid) 174 { 175 struct am65_cpsw_common *common = am65_ndev_to_common(ndev); 176 struct am65_cpsw_port *port = am65_ndev_to_port(ndev); 177 u32 port_mask, unreg_mcast = 0; 178 int ret; 179 180 if (!common->is_emac_mode) 181 return 0; 182 183 if (!netif_running(ndev) || !vid) 184 return 0; 185 186 ret = pm_runtime_resume_and_get(common->dev); 187 if (ret < 0) 188 return ret; 189 190 port_mask = BIT(port->port_id) | ALE_PORT_HOST; 191 if (!vid) 192 unreg_mcast = port_mask; 193 dev_info(common->dev, "Adding vlan %d to vlan filter\n", vid); 194 ret = cpsw_ale_vlan_add_modify(common->ale, vid, port_mask, 195 unreg_mcast, port_mask, 0); 196 197 pm_runtime_put(common->dev); 198 return ret; 199 } 200 201 static int am65_cpsw_nuss_ndo_slave_kill_vid(struct net_device *ndev, 202 __be16 proto, u16 vid) 203 { 204 struct am65_cpsw_common *common = am65_ndev_to_common(ndev); 205 struct am65_cpsw_port *port = am65_ndev_to_port(ndev); 206 int ret; 207 208 if (!common->is_emac_mode) 209 return 0; 210 211 if (!netif_running(ndev) || !vid) 212 return 0; 213 214 ret = pm_runtime_resume_and_get(common->dev); 215 if (ret < 0) 216 return ret; 217 218 dev_info(common->dev, "Removing vlan %d from vlan filter\n", vid); 219 ret = cpsw_ale_del_vlan(common->ale, vid, 220 BIT(port->port_id) | ALE_PORT_HOST); 221 222 pm_runtime_put(common->dev); 223 return ret; 224 } 225 226 static void am65_cpsw_slave_set_promisc(struct am65_cpsw_port *port, 227 bool promisc) 228 { 229 struct am65_cpsw_common *common = port->common; 230 231 if (promisc && !common->is_emac_mode) { 232 dev_dbg(common->dev, "promisc mode requested in switch mode"); 233 return; 234 } 235 236 if (promisc) { 237 /* Enable promiscuous mode */ 238 cpsw_ale_control_set(common->ale, port->port_id, 239 ALE_PORT_MACONLY_CAF, 1); 240 dev_dbg(common->dev, "promisc enabled\n"); 241 } else { 242 /* Disable promiscuous mode */ 243 cpsw_ale_control_set(common->ale, port->port_id, 244 ALE_PORT_MACONLY_CAF, 0); 245 dev_dbg(common->dev, "promisc disabled\n"); 246 } 247 } 248 249 static void am65_cpsw_nuss_ndo_slave_set_rx_mode(struct net_device *ndev) 250 { 251 struct am65_cpsw_common *common = am65_ndev_to_common(ndev); 252 struct am65_cpsw_port *port = am65_ndev_to_port(ndev); 253 u32 port_mask; 254 bool promisc; 255 256 promisc = !!(ndev->flags & IFF_PROMISC); 257 am65_cpsw_slave_set_promisc(port, promisc); 258 259 if (promisc) 260 return; 261 262 /* Restore allmulti on vlans if necessary */ 263 cpsw_ale_set_allmulti(common->ale, 264 ndev->flags & IFF_ALLMULTI, port->port_id); 265 266 port_mask = ALE_PORT_HOST; 267 /* Clear all mcast from ALE */ 268 cpsw_ale_flush_multicast(common->ale, port_mask, -1); 269 270 if (!netdev_mc_empty(ndev)) { 271 struct netdev_hw_addr *ha; 272 273 /* program multicast address list into ALE register */ 274 netdev_for_each_mc_addr(ha, ndev) { 275 cpsw_ale_add_mcast(common->ale, ha->addr, 276 port_mask, 0, 0, 0); 277 } 278 } 279 } 280 281 static void am65_cpsw_nuss_ndo_host_tx_timeout(struct net_device *ndev, 282 unsigned int txqueue) 283 { 284 struct am65_cpsw_common *common = am65_ndev_to_common(ndev); 285 struct am65_cpsw_tx_chn *tx_chn; 286 struct netdev_queue *netif_txq; 287 unsigned long trans_start; 288 289 netif_txq = netdev_get_tx_queue(ndev, txqueue); 290 tx_chn = &common->tx_chns[txqueue]; 291 trans_start = READ_ONCE(netif_txq->trans_start); 292 293 netdev_err(ndev, "txq:%d DRV_XOFF:%d tmo:%u dql_avail:%d free_desc:%zu\n", 294 txqueue, 295 netif_tx_queue_stopped(netif_txq), 296 jiffies_to_msecs(jiffies - trans_start), 297 dql_avail(&netif_txq->dql), 298 k3_cppi_desc_pool_avail(tx_chn->desc_pool)); 299 300 if (netif_tx_queue_stopped(netif_txq)) { 301 /* try recover if stopped by us */ 302 txq_trans_update(netif_txq); 303 netif_tx_wake_queue(netif_txq); 304 } 305 } 306 307 static int am65_cpsw_nuss_rx_push(struct am65_cpsw_common *common, 308 struct sk_buff *skb) 309 { 310 struct am65_cpsw_rx_chn *rx_chn = &common->rx_chns; 311 struct cppi5_host_desc_t *desc_rx; 312 struct device *dev = common->dev; 313 u32 pkt_len = skb_tailroom(skb); 314 dma_addr_t desc_dma; 315 dma_addr_t buf_dma; 316 void *swdata; 317 318 desc_rx = k3_cppi_desc_pool_alloc(rx_chn->desc_pool); 319 if (!desc_rx) { 320 dev_err(dev, "Failed to allocate RXFDQ descriptor\n"); 321 return -ENOMEM; 322 } 323 desc_dma = k3_cppi_desc_pool_virt2dma(rx_chn->desc_pool, desc_rx); 324 325 buf_dma = dma_map_single(rx_chn->dma_dev, skb->data, pkt_len, 326 DMA_FROM_DEVICE); 327 if (unlikely(dma_mapping_error(rx_chn->dma_dev, buf_dma))) { 328 k3_cppi_desc_pool_free(rx_chn->desc_pool, desc_rx); 329 dev_err(dev, "Failed to map rx skb buffer\n"); 330 return -EINVAL; 331 } 332 333 cppi5_hdesc_init(desc_rx, CPPI5_INFO0_HDESC_EPIB_PRESENT, 334 AM65_CPSW_NAV_PS_DATA_SIZE); 335 k3_udma_glue_rx_dma_to_cppi5_addr(rx_chn->rx_chn, &buf_dma); 336 cppi5_hdesc_attach_buf(desc_rx, buf_dma, skb_tailroom(skb), buf_dma, skb_tailroom(skb)); 337 swdata = cppi5_hdesc_get_swdata(desc_rx); 338 *((void **)swdata) = skb; 339 340 return k3_udma_glue_push_rx_chn(rx_chn->rx_chn, 0, desc_rx, desc_dma); 341 } 342 343 void am65_cpsw_nuss_set_p0_ptype(struct am65_cpsw_common *common) 344 { 345 struct am65_cpsw_host *host_p = am65_common_get_host(common); 346 u32 val, pri_map; 347 348 /* P0 set Receive Priority Type */ 349 val = readl(host_p->port_base + AM65_CPSW_PORT_REG_PRI_CTL); 350 351 if (common->pf_p0_rx_ptype_rrobin) { 352 val |= AM65_CPSW_PORT_REG_PRI_CTL_RX_PTYPE_RROBIN; 353 /* Enet Ports fifos works in fixed priority mode only, so 354 * reset P0_Rx_Pri_Map so all packet will go in Enet fifo 0 355 */ 356 pri_map = 0x0; 357 } else { 358 val &= ~AM65_CPSW_PORT_REG_PRI_CTL_RX_PTYPE_RROBIN; 359 /* restore P0_Rx_Pri_Map */ 360 pri_map = 0x76543210; 361 } 362 363 writel(pri_map, host_p->port_base + AM65_CPSW_PORT_REG_RX_PRI_MAP); 364 writel(val, host_p->port_base + AM65_CPSW_PORT_REG_PRI_CTL); 365 } 366 367 static void am65_cpsw_init_host_port_switch(struct am65_cpsw_common *common); 368 static void am65_cpsw_init_host_port_emac(struct am65_cpsw_common *common); 369 static void am65_cpsw_init_port_switch_ale(struct am65_cpsw_port *port); 370 static void am65_cpsw_init_port_emac_ale(struct am65_cpsw_port *port); 371 372 static int am65_cpsw_nuss_common_open(struct am65_cpsw_common *common) 373 { 374 struct am65_cpsw_host *host_p = am65_common_get_host(common); 375 int port_idx, i, ret; 376 struct sk_buff *skb; 377 u32 val, port_mask; 378 379 if (common->usage_count) 380 return 0; 381 382 /* init tx/rx channels */ 383 ret = am65_cpsw_nuss_init_tx_chns(common); 384 if (ret) { 385 dev_err(common->dev, "init_tx_chns failed\n"); 386 return ret; 387 } 388 389 ret = am65_cpsw_nuss_init_rx_chns(common); 390 if (ret) { 391 dev_err(common->dev, "init_rx_chns failed\n"); 392 am65_cpsw_nuss_free_tx_chns(common); 393 return ret; 394 } 395 396 /* Control register */ 397 writel(AM65_CPSW_CTL_P0_ENABLE | AM65_CPSW_CTL_P0_TX_CRC_REMOVE | 398 AM65_CPSW_CTL_VLAN_AWARE | AM65_CPSW_CTL_P0_RX_PAD, 399 common->cpsw_base + AM65_CPSW_REG_CTL); 400 /* Max length register */ 401 writel(AM65_CPSW_MAX_PACKET_SIZE, 402 host_p->port_base + AM65_CPSW_PORT_REG_RX_MAXLEN); 403 /* set base flow_id */ 404 writel(common->rx_flow_id_base, 405 host_p->port_base + AM65_CPSW_PORT0_REG_FLOW_ID_OFFSET); 406 /* en tx crc offload */ 407 writel(AM65_CPSW_P0_REG_CTL_RX_CHECKSUM_EN, host_p->port_base + AM65_CPSW_P0_REG_CTL); 408 409 am65_cpsw_nuss_set_p0_ptype(common); 410 411 /* enable statistic */ 412 val = BIT(HOST_PORT_NUM); 413 for (port_idx = 0; port_idx < common->port_num; port_idx++) { 414 struct am65_cpsw_port *port = &common->ports[port_idx]; 415 416 if (!port->disabled) 417 val |= BIT(port->port_id); 418 } 419 writel(val, common->cpsw_base + AM65_CPSW_REG_STAT_PORT_EN); 420 421 /* disable priority elevation */ 422 writel(0, common->cpsw_base + AM65_CPSW_REG_PTYPE); 423 424 cpsw_ale_control_set(common->ale, 0, ALE_CLEAR, 1); 425 cpsw_ale_start(common->ale); 426 427 /* limit to one RX flow only */ 428 cpsw_ale_control_set(common->ale, HOST_PORT_NUM, 429 ALE_DEFAULT_THREAD_ID, 0); 430 cpsw_ale_control_set(common->ale, HOST_PORT_NUM, 431 ALE_DEFAULT_THREAD_ENABLE, 1); 432 /* switch to vlan unaware mode */ 433 cpsw_ale_control_set(common->ale, HOST_PORT_NUM, ALE_VLAN_AWARE, 1); 434 cpsw_ale_control_set(common->ale, HOST_PORT_NUM, 435 ALE_PORT_STATE, ALE_PORT_STATE_FORWARD); 436 437 /* default vlan cfg: create mask based on enabled ports */ 438 port_mask = GENMASK(common->port_num, 0) & 439 ~common->disabled_ports_mask; 440 441 cpsw_ale_add_vlan(common->ale, 0, port_mask, 442 port_mask, port_mask, 443 port_mask & ~ALE_PORT_HOST); 444 445 if (common->is_emac_mode) 446 am65_cpsw_init_host_port_emac(common); 447 else 448 am65_cpsw_init_host_port_switch(common); 449 450 for (i = 0; i < common->rx_chns.descs_num; i++) { 451 skb = __netdev_alloc_skb_ip_align(NULL, 452 AM65_CPSW_MAX_PACKET_SIZE, 453 GFP_KERNEL); 454 if (!skb) { 455 dev_err(common->dev, "cannot allocate skb\n"); 456 ret = -ENOMEM; 457 goto err; 458 } 459 460 ret = am65_cpsw_nuss_rx_push(common, skb); 461 if (ret < 0) { 462 dev_err(common->dev, 463 "cannot submit skb to channel rx, error %d\n", 464 ret); 465 kfree_skb(skb); 466 goto err; 467 } 468 kmemleak_not_leak(skb); 469 } 470 k3_udma_glue_enable_rx_chn(common->rx_chns.rx_chn); 471 472 for (i = 0; i < common->tx_ch_num; i++) { 473 ret = k3_udma_glue_enable_tx_chn(common->tx_chns[i].tx_chn); 474 if (ret) 475 goto err; 476 napi_enable(&common->tx_chns[i].napi_tx); 477 } 478 479 napi_enable(&common->napi_rx); 480 if (common->rx_irq_disabled) { 481 common->rx_irq_disabled = false; 482 enable_irq(common->rx_chns.irq); 483 } 484 485 dev_dbg(common->dev, "cpsw_nuss started\n"); 486 return 0; 487 488 err: 489 am65_cpsw_nuss_free_tx_chns(common); 490 am65_cpsw_nuss_free_rx_chns(common); 491 492 return ret; 493 } 494 495 static void am65_cpsw_nuss_tx_cleanup(void *data, dma_addr_t desc_dma); 496 static void am65_cpsw_nuss_rx_cleanup(void *data, dma_addr_t desc_dma); 497 498 static int am65_cpsw_nuss_common_stop(struct am65_cpsw_common *common) 499 { 500 int i; 501 502 if (common->usage_count != 1) 503 return 0; 504 505 cpsw_ale_control_set(common->ale, HOST_PORT_NUM, 506 ALE_PORT_STATE, ALE_PORT_STATE_DISABLE); 507 508 /* shutdown tx channels */ 509 atomic_set(&common->tdown_cnt, common->tx_ch_num); 510 /* ensure new tdown_cnt value is visible */ 511 smp_mb__after_atomic(); 512 reinit_completion(&common->tdown_complete); 513 514 for (i = 0; i < common->tx_ch_num; i++) 515 k3_udma_glue_tdown_tx_chn(common->tx_chns[i].tx_chn, false); 516 517 i = wait_for_completion_timeout(&common->tdown_complete, 518 msecs_to_jiffies(1000)); 519 if (!i) 520 dev_err(common->dev, "tx timeout\n"); 521 for (i = 0; i < common->tx_ch_num; i++) 522 napi_disable(&common->tx_chns[i].napi_tx); 523 524 for (i = 0; i < common->tx_ch_num; i++) { 525 k3_udma_glue_reset_tx_chn(common->tx_chns[i].tx_chn, 526 &common->tx_chns[i], 527 am65_cpsw_nuss_tx_cleanup); 528 k3_udma_glue_disable_tx_chn(common->tx_chns[i].tx_chn); 529 } 530 531 k3_udma_glue_tdown_rx_chn(common->rx_chns.rx_chn, true); 532 napi_disable(&common->napi_rx); 533 534 for (i = 0; i < AM65_CPSW_MAX_RX_FLOWS; i++) 535 k3_udma_glue_reset_rx_chn(common->rx_chns.rx_chn, i, 536 &common->rx_chns, 537 am65_cpsw_nuss_rx_cleanup, !!i); 538 539 k3_udma_glue_disable_rx_chn(common->rx_chns.rx_chn); 540 541 cpsw_ale_stop(common->ale); 542 543 writel(0, common->cpsw_base + AM65_CPSW_REG_CTL); 544 writel(0, common->cpsw_base + AM65_CPSW_REG_STAT_PORT_EN); 545 546 am65_cpsw_nuss_free_tx_chns(common); 547 am65_cpsw_nuss_free_rx_chns(common); 548 549 dev_dbg(common->dev, "cpsw_nuss stopped\n"); 550 return 0; 551 } 552 553 static int am65_cpsw_nuss_ndo_slave_stop(struct net_device *ndev) 554 { 555 struct am65_cpsw_common *common = am65_ndev_to_common(ndev); 556 struct am65_cpsw_port *port = am65_ndev_to_port(ndev); 557 int ret; 558 559 phylink_stop(port->slave.phylink); 560 561 netif_tx_stop_all_queues(ndev); 562 563 phylink_disconnect_phy(port->slave.phylink); 564 565 ret = am65_cpsw_nuss_common_stop(common); 566 if (ret) 567 return ret; 568 569 common->usage_count--; 570 pm_runtime_put(common->dev); 571 return 0; 572 } 573 574 static int cpsw_restore_vlans(struct net_device *vdev, int vid, void *arg) 575 { 576 struct am65_cpsw_port *port = arg; 577 578 if (!vdev) 579 return 0; 580 581 return am65_cpsw_nuss_ndo_slave_add_vid(port->ndev, 0, vid); 582 } 583 584 static int am65_cpsw_nuss_ndo_slave_open(struct net_device *ndev) 585 { 586 struct am65_cpsw_common *common = am65_ndev_to_common(ndev); 587 struct am65_cpsw_port *port = am65_ndev_to_port(ndev); 588 int ret, i; 589 u32 reg; 590 int tmo; 591 592 ret = pm_runtime_resume_and_get(common->dev); 593 if (ret < 0) 594 return ret; 595 596 /* Idle MAC port */ 597 cpsw_sl_ctl_set(port->slave.mac_sl, CPSW_SL_CTL_CMD_IDLE); 598 599 tmo = cpsw_sl_wait_for_idle(port->slave.mac_sl, 100); 600 dev_info(common->dev, "down msc_sl %08x tmo %d\n", 601 cpsw_sl_reg_read(port->slave.mac_sl, CPSW_SL_MACSTATUS), tmo); 602 603 cpsw_sl_ctl_reset(port->slave.mac_sl); 604 605 /* soft reset MAC */ 606 cpsw_sl_reg_write(port->slave.mac_sl, CPSW_SL_SOFT_RESET, 1); 607 mdelay(1); 608 reg = cpsw_sl_reg_read(port->slave.mac_sl, CPSW_SL_SOFT_RESET); 609 if (reg) 610 dev_info(common->dev, "mac reset not yet done\n"); 611 612 /* Notify the stack of the actual queue counts. */ 613 ret = netif_set_real_num_tx_queues(ndev, common->tx_ch_num); 614 if (ret) { 615 dev_err(common->dev, "cannot set real number of tx queues\n"); 616 return ret; 617 } 618 619 ret = netif_set_real_num_rx_queues(ndev, AM65_CPSW_MAX_RX_QUEUES); 620 if (ret) { 621 dev_err(common->dev, "cannot set real number of rx queues\n"); 622 return ret; 623 } 624 625 for (i = 0; i < common->tx_ch_num; i++) 626 netdev_tx_reset_queue(netdev_get_tx_queue(ndev, i)); 627 628 ret = am65_cpsw_nuss_common_open(common); 629 if (ret) 630 return ret; 631 632 common->usage_count++; 633 634 am65_cpsw_port_set_sl_mac(port, ndev->dev_addr); 635 636 if (common->is_emac_mode) 637 am65_cpsw_init_port_emac_ale(port); 638 else 639 am65_cpsw_init_port_switch_ale(port); 640 641 /* mac_sl should be configured via phy-link interface */ 642 am65_cpsw_sl_ctl_reset(port); 643 644 ret = phylink_of_phy_connect(port->slave.phylink, port->slave.phy_node, 0); 645 if (ret) 646 goto error_cleanup; 647 648 /* restore vlan configurations */ 649 vlan_for_each(ndev, cpsw_restore_vlans, port); 650 651 phylink_start(port->slave.phylink); 652 653 return 0; 654 655 error_cleanup: 656 am65_cpsw_nuss_ndo_slave_stop(ndev); 657 return ret; 658 } 659 660 static void am65_cpsw_nuss_rx_cleanup(void *data, dma_addr_t desc_dma) 661 { 662 struct am65_cpsw_rx_chn *rx_chn = data; 663 struct cppi5_host_desc_t *desc_rx; 664 struct sk_buff *skb; 665 dma_addr_t buf_dma; 666 u32 buf_dma_len; 667 void **swdata; 668 669 desc_rx = k3_cppi_desc_pool_dma2virt(rx_chn->desc_pool, desc_dma); 670 swdata = cppi5_hdesc_get_swdata(desc_rx); 671 skb = *swdata; 672 cppi5_hdesc_get_obuf(desc_rx, &buf_dma, &buf_dma_len); 673 k3_udma_glue_rx_cppi5_to_dma_addr(rx_chn->rx_chn, &buf_dma); 674 675 dma_unmap_single(rx_chn->dma_dev, buf_dma, buf_dma_len, DMA_FROM_DEVICE); 676 k3_cppi_desc_pool_free(rx_chn->desc_pool, desc_rx); 677 678 dev_kfree_skb_any(skb); 679 } 680 681 static void am65_cpsw_nuss_rx_ts(struct sk_buff *skb, u32 *psdata) 682 { 683 struct skb_shared_hwtstamps *ssh; 684 u64 ns; 685 686 ns = ((u64)psdata[1] << 32) | psdata[0]; 687 688 ssh = skb_hwtstamps(skb); 689 memset(ssh, 0, sizeof(*ssh)); 690 ssh->hwtstamp = ns_to_ktime(ns); 691 } 692 693 /* RX psdata[2] word format - checksum information */ 694 #define AM65_CPSW_RX_PSD_CSUM_ADD GENMASK(15, 0) 695 #define AM65_CPSW_RX_PSD_CSUM_ERR BIT(16) 696 #define AM65_CPSW_RX_PSD_IS_FRAGMENT BIT(17) 697 #define AM65_CPSW_RX_PSD_IS_TCP BIT(18) 698 #define AM65_CPSW_RX_PSD_IPV6_VALID BIT(19) 699 #define AM65_CPSW_RX_PSD_IPV4_VALID BIT(20) 700 701 static void am65_cpsw_nuss_rx_csum(struct sk_buff *skb, u32 csum_info) 702 { 703 /* HW can verify IPv4/IPv6 TCP/UDP packets checksum 704 * csum information provides in psdata[2] word: 705 * AM65_CPSW_RX_PSD_CSUM_ERR bit - indicates csum error 706 * AM65_CPSW_RX_PSD_IPV6_VALID and AM65_CPSW_RX_PSD_IPV4_VALID 707 * bits - indicates IPv4/IPv6 packet 708 * AM65_CPSW_RX_PSD_IS_FRAGMENT bit - indicates fragmented packet 709 * AM65_CPSW_RX_PSD_CSUM_ADD has value 0xFFFF for non fragmented packets 710 * or csum value for fragmented packets if !AM65_CPSW_RX_PSD_CSUM_ERR 711 */ 712 skb_checksum_none_assert(skb); 713 714 if (unlikely(!(skb->dev->features & NETIF_F_RXCSUM))) 715 return; 716 717 if ((csum_info & (AM65_CPSW_RX_PSD_IPV6_VALID | 718 AM65_CPSW_RX_PSD_IPV4_VALID)) && 719 !(csum_info & AM65_CPSW_RX_PSD_CSUM_ERR)) { 720 /* csum for fragmented packets is unsupported */ 721 if (!(csum_info & AM65_CPSW_RX_PSD_IS_FRAGMENT)) 722 skb->ip_summed = CHECKSUM_UNNECESSARY; 723 } 724 } 725 726 static int am65_cpsw_nuss_rx_packets(struct am65_cpsw_common *common, 727 u32 flow_idx) 728 { 729 struct am65_cpsw_rx_chn *rx_chn = &common->rx_chns; 730 u32 buf_dma_len, pkt_len, port_id = 0, csum_info; 731 struct am65_cpsw_ndev_priv *ndev_priv; 732 struct am65_cpsw_ndev_stats *stats; 733 struct cppi5_host_desc_t *desc_rx; 734 struct device *dev = common->dev; 735 struct sk_buff *skb, *new_skb; 736 dma_addr_t desc_dma, buf_dma; 737 struct am65_cpsw_port *port; 738 struct net_device *ndev; 739 void **swdata; 740 u32 *psdata; 741 int ret = 0; 742 743 ret = k3_udma_glue_pop_rx_chn(rx_chn->rx_chn, flow_idx, &desc_dma); 744 if (ret) { 745 if (ret != -ENODATA) 746 dev_err(dev, "RX: pop chn fail %d\n", ret); 747 return ret; 748 } 749 750 if (cppi5_desc_is_tdcm(desc_dma)) { 751 dev_dbg(dev, "%s RX tdown flow: %u\n", __func__, flow_idx); 752 return 0; 753 } 754 755 desc_rx = k3_cppi_desc_pool_dma2virt(rx_chn->desc_pool, desc_dma); 756 dev_dbg(dev, "%s flow_idx: %u desc %pad\n", 757 __func__, flow_idx, &desc_dma); 758 759 swdata = cppi5_hdesc_get_swdata(desc_rx); 760 skb = *swdata; 761 cppi5_hdesc_get_obuf(desc_rx, &buf_dma, &buf_dma_len); 762 k3_udma_glue_rx_cppi5_to_dma_addr(rx_chn->rx_chn, &buf_dma); 763 pkt_len = cppi5_hdesc_get_pktlen(desc_rx); 764 cppi5_desc_get_tags_ids(&desc_rx->hdr, &port_id, NULL); 765 dev_dbg(dev, "%s rx port_id:%d\n", __func__, port_id); 766 port = am65_common_get_port(common, port_id); 767 ndev = port->ndev; 768 skb->dev = ndev; 769 770 psdata = cppi5_hdesc_get_psdata(desc_rx); 771 /* add RX timestamp */ 772 if (port->rx_ts_enabled) 773 am65_cpsw_nuss_rx_ts(skb, psdata); 774 csum_info = psdata[2]; 775 dev_dbg(dev, "%s rx csum_info:%#x\n", __func__, csum_info); 776 777 dma_unmap_single(rx_chn->dma_dev, buf_dma, buf_dma_len, DMA_FROM_DEVICE); 778 779 k3_cppi_desc_pool_free(rx_chn->desc_pool, desc_rx); 780 781 new_skb = netdev_alloc_skb_ip_align(ndev, AM65_CPSW_MAX_PACKET_SIZE); 782 if (new_skb) { 783 ndev_priv = netdev_priv(ndev); 784 am65_cpsw_nuss_set_offload_fwd_mark(skb, ndev_priv->offload_fwd_mark); 785 skb_put(skb, pkt_len); 786 skb->protocol = eth_type_trans(skb, ndev); 787 am65_cpsw_nuss_rx_csum(skb, csum_info); 788 napi_gro_receive(&common->napi_rx, skb); 789 790 stats = this_cpu_ptr(ndev_priv->stats); 791 792 u64_stats_update_begin(&stats->syncp); 793 stats->rx_packets++; 794 stats->rx_bytes += pkt_len; 795 u64_stats_update_end(&stats->syncp); 796 kmemleak_not_leak(new_skb); 797 } else { 798 ndev->stats.rx_dropped++; 799 new_skb = skb; 800 } 801 802 if (netif_dormant(ndev)) { 803 dev_kfree_skb_any(new_skb); 804 ndev->stats.rx_dropped++; 805 return 0; 806 } 807 808 ret = am65_cpsw_nuss_rx_push(common, new_skb); 809 if (WARN_ON(ret < 0)) { 810 dev_kfree_skb_any(new_skb); 811 ndev->stats.rx_errors++; 812 ndev->stats.rx_dropped++; 813 } 814 815 return ret; 816 } 817 818 static int am65_cpsw_nuss_rx_poll(struct napi_struct *napi_rx, int budget) 819 { 820 struct am65_cpsw_common *common = am65_cpsw_napi_to_common(napi_rx); 821 int flow = AM65_CPSW_MAX_RX_FLOWS; 822 int cur_budget, ret; 823 int num_rx = 0; 824 825 /* process every flow */ 826 while (flow--) { 827 cur_budget = budget - num_rx; 828 829 while (cur_budget--) { 830 ret = am65_cpsw_nuss_rx_packets(common, flow); 831 if (ret) 832 break; 833 num_rx++; 834 } 835 836 if (num_rx >= budget) 837 break; 838 } 839 840 dev_dbg(common->dev, "%s num_rx:%d %d\n", __func__, num_rx, budget); 841 842 if (num_rx < budget && napi_complete_done(napi_rx, num_rx)) { 843 if (common->rx_irq_disabled) { 844 common->rx_irq_disabled = false; 845 enable_irq(common->rx_chns.irq); 846 } 847 } 848 849 return num_rx; 850 } 851 852 static void am65_cpsw_nuss_xmit_free(struct am65_cpsw_tx_chn *tx_chn, 853 struct cppi5_host_desc_t *desc) 854 { 855 struct cppi5_host_desc_t *first_desc, *next_desc; 856 dma_addr_t buf_dma, next_desc_dma; 857 u32 buf_dma_len; 858 859 first_desc = desc; 860 next_desc = first_desc; 861 862 cppi5_hdesc_get_obuf(first_desc, &buf_dma, &buf_dma_len); 863 k3_udma_glue_tx_cppi5_to_dma_addr(tx_chn->tx_chn, &buf_dma); 864 865 dma_unmap_single(tx_chn->dma_dev, buf_dma, buf_dma_len, DMA_TO_DEVICE); 866 867 next_desc_dma = cppi5_hdesc_get_next_hbdesc(first_desc); 868 k3_udma_glue_tx_cppi5_to_dma_addr(tx_chn->tx_chn, &next_desc_dma); 869 while (next_desc_dma) { 870 next_desc = k3_cppi_desc_pool_dma2virt(tx_chn->desc_pool, 871 next_desc_dma); 872 cppi5_hdesc_get_obuf(next_desc, &buf_dma, &buf_dma_len); 873 k3_udma_glue_tx_cppi5_to_dma_addr(tx_chn->tx_chn, &buf_dma); 874 875 dma_unmap_page(tx_chn->dma_dev, buf_dma, buf_dma_len, 876 DMA_TO_DEVICE); 877 878 next_desc_dma = cppi5_hdesc_get_next_hbdesc(next_desc); 879 k3_udma_glue_tx_cppi5_to_dma_addr(tx_chn->tx_chn, &next_desc_dma); 880 881 k3_cppi_desc_pool_free(tx_chn->desc_pool, next_desc); 882 } 883 884 k3_cppi_desc_pool_free(tx_chn->desc_pool, first_desc); 885 } 886 887 static void am65_cpsw_nuss_tx_cleanup(void *data, dma_addr_t desc_dma) 888 { 889 struct am65_cpsw_tx_chn *tx_chn = data; 890 struct cppi5_host_desc_t *desc_tx; 891 struct sk_buff *skb; 892 void **swdata; 893 894 desc_tx = k3_cppi_desc_pool_dma2virt(tx_chn->desc_pool, desc_dma); 895 swdata = cppi5_hdesc_get_swdata(desc_tx); 896 skb = *(swdata); 897 am65_cpsw_nuss_xmit_free(tx_chn, desc_tx); 898 899 dev_kfree_skb_any(skb); 900 } 901 902 static struct sk_buff * 903 am65_cpsw_nuss_tx_compl_packet(struct am65_cpsw_tx_chn *tx_chn, 904 dma_addr_t desc_dma) 905 { 906 struct am65_cpsw_ndev_priv *ndev_priv; 907 struct am65_cpsw_ndev_stats *stats; 908 struct cppi5_host_desc_t *desc_tx; 909 struct net_device *ndev; 910 struct sk_buff *skb; 911 void **swdata; 912 913 desc_tx = k3_cppi_desc_pool_dma2virt(tx_chn->desc_pool, 914 desc_dma); 915 swdata = cppi5_hdesc_get_swdata(desc_tx); 916 skb = *(swdata); 917 am65_cpsw_nuss_xmit_free(tx_chn, desc_tx); 918 919 ndev = skb->dev; 920 921 am65_cpts_tx_timestamp(tx_chn->common->cpts, skb); 922 923 ndev_priv = netdev_priv(ndev); 924 stats = this_cpu_ptr(ndev_priv->stats); 925 u64_stats_update_begin(&stats->syncp); 926 stats->tx_packets++; 927 stats->tx_bytes += skb->len; 928 u64_stats_update_end(&stats->syncp); 929 930 return skb; 931 } 932 933 static void am65_cpsw_nuss_tx_wake(struct am65_cpsw_tx_chn *tx_chn, struct net_device *ndev, 934 struct netdev_queue *netif_txq) 935 { 936 if (netif_tx_queue_stopped(netif_txq)) { 937 /* Check whether the queue is stopped due to stalled 938 * tx dma, if the queue is stopped then wake the queue 939 * as we have free desc for tx 940 */ 941 __netif_tx_lock(netif_txq, smp_processor_id()); 942 if (netif_running(ndev) && 943 (k3_cppi_desc_pool_avail(tx_chn->desc_pool) >= MAX_SKB_FRAGS)) 944 netif_tx_wake_queue(netif_txq); 945 946 __netif_tx_unlock(netif_txq); 947 } 948 } 949 950 static int am65_cpsw_nuss_tx_compl_packets(struct am65_cpsw_common *common, 951 int chn, unsigned int budget) 952 { 953 struct device *dev = common->dev; 954 struct am65_cpsw_tx_chn *tx_chn; 955 struct netdev_queue *netif_txq; 956 unsigned int total_bytes = 0; 957 struct net_device *ndev; 958 struct sk_buff *skb; 959 dma_addr_t desc_dma; 960 int res, num_tx = 0; 961 962 tx_chn = &common->tx_chns[chn]; 963 964 while (true) { 965 spin_lock(&tx_chn->lock); 966 res = k3_udma_glue_pop_tx_chn(tx_chn->tx_chn, &desc_dma); 967 spin_unlock(&tx_chn->lock); 968 if (res == -ENODATA) 969 break; 970 971 if (cppi5_desc_is_tdcm(desc_dma)) { 972 if (atomic_dec_and_test(&common->tdown_cnt)) 973 complete(&common->tdown_complete); 974 break; 975 } 976 977 skb = am65_cpsw_nuss_tx_compl_packet(tx_chn, desc_dma); 978 total_bytes = skb->len; 979 ndev = skb->dev; 980 napi_consume_skb(skb, budget); 981 num_tx++; 982 983 netif_txq = netdev_get_tx_queue(ndev, chn); 984 985 netdev_tx_completed_queue(netif_txq, num_tx, total_bytes); 986 987 am65_cpsw_nuss_tx_wake(tx_chn, ndev, netif_txq); 988 } 989 990 dev_dbg(dev, "%s:%u pkt:%d\n", __func__, chn, num_tx); 991 992 return num_tx; 993 } 994 995 static int am65_cpsw_nuss_tx_compl_packets_2g(struct am65_cpsw_common *common, 996 int chn, unsigned int budget) 997 { 998 struct device *dev = common->dev; 999 struct am65_cpsw_tx_chn *tx_chn; 1000 struct netdev_queue *netif_txq; 1001 unsigned int total_bytes = 0; 1002 struct net_device *ndev; 1003 struct sk_buff *skb; 1004 dma_addr_t desc_dma; 1005 int res, num_tx = 0; 1006 1007 tx_chn = &common->tx_chns[chn]; 1008 1009 while (true) { 1010 res = k3_udma_glue_pop_tx_chn(tx_chn->tx_chn, &desc_dma); 1011 if (res == -ENODATA) 1012 break; 1013 1014 if (cppi5_desc_is_tdcm(desc_dma)) { 1015 if (atomic_dec_and_test(&common->tdown_cnt)) 1016 complete(&common->tdown_complete); 1017 break; 1018 } 1019 1020 skb = am65_cpsw_nuss_tx_compl_packet(tx_chn, desc_dma); 1021 1022 ndev = skb->dev; 1023 total_bytes += skb->len; 1024 napi_consume_skb(skb, budget); 1025 num_tx++; 1026 } 1027 1028 if (!num_tx) 1029 return 0; 1030 1031 netif_txq = netdev_get_tx_queue(ndev, chn); 1032 1033 netdev_tx_completed_queue(netif_txq, num_tx, total_bytes); 1034 1035 am65_cpsw_nuss_tx_wake(tx_chn, ndev, netif_txq); 1036 1037 dev_dbg(dev, "%s:%u pkt:%d\n", __func__, chn, num_tx); 1038 1039 return num_tx; 1040 } 1041 1042 static int am65_cpsw_nuss_tx_poll(struct napi_struct *napi_tx, int budget) 1043 { 1044 struct am65_cpsw_tx_chn *tx_chn = am65_cpsw_napi_to_tx_chn(napi_tx); 1045 int num_tx; 1046 1047 if (AM65_CPSW_IS_CPSW2G(tx_chn->common)) 1048 num_tx = am65_cpsw_nuss_tx_compl_packets_2g(tx_chn->common, tx_chn->id, budget); 1049 else 1050 num_tx = am65_cpsw_nuss_tx_compl_packets(tx_chn->common, tx_chn->id, budget); 1051 1052 if (num_tx >= budget) 1053 return budget; 1054 1055 if (napi_complete_done(napi_tx, num_tx)) 1056 enable_irq(tx_chn->irq); 1057 1058 return 0; 1059 } 1060 1061 static irqreturn_t am65_cpsw_nuss_rx_irq(int irq, void *dev_id) 1062 { 1063 struct am65_cpsw_common *common = dev_id; 1064 1065 common->rx_irq_disabled = true; 1066 disable_irq_nosync(irq); 1067 napi_schedule(&common->napi_rx); 1068 1069 return IRQ_HANDLED; 1070 } 1071 1072 static irqreturn_t am65_cpsw_nuss_tx_irq(int irq, void *dev_id) 1073 { 1074 struct am65_cpsw_tx_chn *tx_chn = dev_id; 1075 1076 disable_irq_nosync(irq); 1077 napi_schedule(&tx_chn->napi_tx); 1078 1079 return IRQ_HANDLED; 1080 } 1081 1082 static netdev_tx_t am65_cpsw_nuss_ndo_slave_xmit(struct sk_buff *skb, 1083 struct net_device *ndev) 1084 { 1085 struct am65_cpsw_common *common = am65_ndev_to_common(ndev); 1086 struct cppi5_host_desc_t *first_desc, *next_desc, *cur_desc; 1087 struct am65_cpsw_port *port = am65_ndev_to_port(ndev); 1088 struct device *dev = common->dev; 1089 struct am65_cpsw_tx_chn *tx_chn; 1090 struct netdev_queue *netif_txq; 1091 dma_addr_t desc_dma, buf_dma; 1092 int ret, q_idx, i; 1093 void **swdata; 1094 u32 *psdata; 1095 u32 pkt_len; 1096 1097 /* padding enabled in hw */ 1098 pkt_len = skb_headlen(skb); 1099 1100 /* SKB TX timestamp */ 1101 if (port->tx_ts_enabled) 1102 am65_cpts_prep_tx_timestamp(common->cpts, skb); 1103 1104 q_idx = skb_get_queue_mapping(skb); 1105 dev_dbg(dev, "%s skb_queue:%d\n", __func__, q_idx); 1106 1107 tx_chn = &common->tx_chns[q_idx]; 1108 netif_txq = netdev_get_tx_queue(ndev, q_idx); 1109 1110 /* Map the linear buffer */ 1111 buf_dma = dma_map_single(tx_chn->dma_dev, skb->data, pkt_len, 1112 DMA_TO_DEVICE); 1113 if (unlikely(dma_mapping_error(tx_chn->dma_dev, buf_dma))) { 1114 dev_err(dev, "Failed to map tx skb buffer\n"); 1115 ndev->stats.tx_errors++; 1116 goto err_free_skb; 1117 } 1118 1119 first_desc = k3_cppi_desc_pool_alloc(tx_chn->desc_pool); 1120 if (!first_desc) { 1121 dev_dbg(dev, "Failed to allocate descriptor\n"); 1122 dma_unmap_single(tx_chn->dma_dev, buf_dma, pkt_len, 1123 DMA_TO_DEVICE); 1124 goto busy_stop_q; 1125 } 1126 1127 cppi5_hdesc_init(first_desc, CPPI5_INFO0_HDESC_EPIB_PRESENT, 1128 AM65_CPSW_NAV_PS_DATA_SIZE); 1129 cppi5_desc_set_pktids(&first_desc->hdr, 0, 0x3FFF); 1130 cppi5_hdesc_set_pkttype(first_desc, 0x7); 1131 cppi5_desc_set_tags_ids(&first_desc->hdr, 0, port->port_id); 1132 1133 k3_udma_glue_tx_dma_to_cppi5_addr(tx_chn->tx_chn, &buf_dma); 1134 cppi5_hdesc_attach_buf(first_desc, buf_dma, pkt_len, buf_dma, pkt_len); 1135 swdata = cppi5_hdesc_get_swdata(first_desc); 1136 *(swdata) = skb; 1137 psdata = cppi5_hdesc_get_psdata(first_desc); 1138 1139 /* HW csum offload if enabled */ 1140 psdata[2] = 0; 1141 if (likely(skb->ip_summed == CHECKSUM_PARTIAL)) { 1142 unsigned int cs_start, cs_offset; 1143 1144 cs_start = skb_transport_offset(skb); 1145 cs_offset = cs_start + skb->csum_offset; 1146 /* HW numerates bytes starting from 1 */ 1147 psdata[2] = ((cs_offset + 1) << 24) | 1148 ((cs_start + 1) << 16) | (skb->len - cs_start); 1149 dev_dbg(dev, "%s tx psdata:%#x\n", __func__, psdata[2]); 1150 } 1151 1152 if (!skb_is_nonlinear(skb)) 1153 goto done_tx; 1154 1155 dev_dbg(dev, "fragmented SKB\n"); 1156 1157 /* Handle the case where skb is fragmented in pages */ 1158 cur_desc = first_desc; 1159 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { 1160 skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 1161 u32 frag_size = skb_frag_size(frag); 1162 1163 next_desc = k3_cppi_desc_pool_alloc(tx_chn->desc_pool); 1164 if (!next_desc) { 1165 dev_err(dev, "Failed to allocate descriptor\n"); 1166 goto busy_free_descs; 1167 } 1168 1169 buf_dma = skb_frag_dma_map(tx_chn->dma_dev, frag, 0, frag_size, 1170 DMA_TO_DEVICE); 1171 if (unlikely(dma_mapping_error(tx_chn->dma_dev, buf_dma))) { 1172 dev_err(dev, "Failed to map tx skb page\n"); 1173 k3_cppi_desc_pool_free(tx_chn->desc_pool, next_desc); 1174 ndev->stats.tx_errors++; 1175 goto err_free_descs; 1176 } 1177 1178 cppi5_hdesc_reset_hbdesc(next_desc); 1179 k3_udma_glue_tx_dma_to_cppi5_addr(tx_chn->tx_chn, &buf_dma); 1180 cppi5_hdesc_attach_buf(next_desc, 1181 buf_dma, frag_size, buf_dma, frag_size); 1182 1183 desc_dma = k3_cppi_desc_pool_virt2dma(tx_chn->desc_pool, 1184 next_desc); 1185 k3_udma_glue_tx_dma_to_cppi5_addr(tx_chn->tx_chn, &desc_dma); 1186 cppi5_hdesc_link_hbdesc(cur_desc, desc_dma); 1187 1188 pkt_len += frag_size; 1189 cur_desc = next_desc; 1190 } 1191 WARN_ON(pkt_len != skb->len); 1192 1193 done_tx: 1194 skb_tx_timestamp(skb); 1195 1196 /* report bql before sending packet */ 1197 netdev_tx_sent_queue(netif_txq, pkt_len); 1198 1199 cppi5_hdesc_set_pktlen(first_desc, pkt_len); 1200 desc_dma = k3_cppi_desc_pool_virt2dma(tx_chn->desc_pool, first_desc); 1201 if (AM65_CPSW_IS_CPSW2G(common)) { 1202 ret = k3_udma_glue_push_tx_chn(tx_chn->tx_chn, first_desc, desc_dma); 1203 } else { 1204 spin_lock_bh(&tx_chn->lock); 1205 ret = k3_udma_glue_push_tx_chn(tx_chn->tx_chn, first_desc, desc_dma); 1206 spin_unlock_bh(&tx_chn->lock); 1207 } 1208 if (ret) { 1209 dev_err(dev, "can't push desc %d\n", ret); 1210 /* inform bql */ 1211 netdev_tx_completed_queue(netif_txq, 1, pkt_len); 1212 ndev->stats.tx_errors++; 1213 goto err_free_descs; 1214 } 1215 1216 if (k3_cppi_desc_pool_avail(tx_chn->desc_pool) < MAX_SKB_FRAGS) { 1217 netif_tx_stop_queue(netif_txq); 1218 /* Barrier, so that stop_queue visible to other cpus */ 1219 smp_mb__after_atomic(); 1220 dev_dbg(dev, "netif_tx_stop_queue %d\n", q_idx); 1221 1222 /* re-check for smp */ 1223 if (k3_cppi_desc_pool_avail(tx_chn->desc_pool) >= 1224 MAX_SKB_FRAGS) { 1225 netif_tx_wake_queue(netif_txq); 1226 dev_dbg(dev, "netif_tx_wake_queue %d\n", q_idx); 1227 } 1228 } 1229 1230 return NETDEV_TX_OK; 1231 1232 err_free_descs: 1233 am65_cpsw_nuss_xmit_free(tx_chn, first_desc); 1234 err_free_skb: 1235 ndev->stats.tx_dropped++; 1236 dev_kfree_skb_any(skb); 1237 return NETDEV_TX_OK; 1238 1239 busy_free_descs: 1240 am65_cpsw_nuss_xmit_free(tx_chn, first_desc); 1241 busy_stop_q: 1242 netif_tx_stop_queue(netif_txq); 1243 return NETDEV_TX_BUSY; 1244 } 1245 1246 static int am65_cpsw_nuss_ndo_slave_set_mac_address(struct net_device *ndev, 1247 void *addr) 1248 { 1249 struct am65_cpsw_common *common = am65_ndev_to_common(ndev); 1250 struct am65_cpsw_port *port = am65_ndev_to_port(ndev); 1251 struct sockaddr *sockaddr = (struct sockaddr *)addr; 1252 int ret; 1253 1254 ret = eth_prepare_mac_addr_change(ndev, addr); 1255 if (ret < 0) 1256 return ret; 1257 1258 ret = pm_runtime_resume_and_get(common->dev); 1259 if (ret < 0) 1260 return ret; 1261 1262 cpsw_ale_del_ucast(common->ale, ndev->dev_addr, 1263 HOST_PORT_NUM, 0, 0); 1264 cpsw_ale_add_ucast(common->ale, sockaddr->sa_data, 1265 HOST_PORT_NUM, ALE_SECURE, 0); 1266 1267 am65_cpsw_port_set_sl_mac(port, addr); 1268 eth_commit_mac_addr_change(ndev, sockaddr); 1269 1270 pm_runtime_put(common->dev); 1271 1272 return 0; 1273 } 1274 1275 static int am65_cpsw_nuss_hwtstamp_set(struct net_device *ndev, 1276 struct ifreq *ifr) 1277 { 1278 struct am65_cpsw_common *common = am65_ndev_to_common(ndev); 1279 struct am65_cpsw_port *port = am65_ndev_to_port(ndev); 1280 u32 ts_ctrl, seq_id, ts_ctrl_ltype2, ts_vlan_ltype; 1281 struct hwtstamp_config cfg; 1282 1283 if (!IS_ENABLED(CONFIG_TI_K3_AM65_CPTS)) 1284 return -EOPNOTSUPP; 1285 1286 if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg))) 1287 return -EFAULT; 1288 1289 /* TX HW timestamp */ 1290 switch (cfg.tx_type) { 1291 case HWTSTAMP_TX_OFF: 1292 case HWTSTAMP_TX_ON: 1293 break; 1294 default: 1295 return -ERANGE; 1296 } 1297 1298 switch (cfg.rx_filter) { 1299 case HWTSTAMP_FILTER_NONE: 1300 port->rx_ts_enabled = false; 1301 break; 1302 case HWTSTAMP_FILTER_ALL: 1303 case HWTSTAMP_FILTER_SOME: 1304 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: 1305 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: 1306 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: 1307 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: 1308 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 1309 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 1310 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: 1311 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: 1312 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: 1313 case HWTSTAMP_FILTER_PTP_V2_EVENT: 1314 case HWTSTAMP_FILTER_PTP_V2_SYNC: 1315 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 1316 case HWTSTAMP_FILTER_NTP_ALL: 1317 port->rx_ts_enabled = true; 1318 cfg.rx_filter = HWTSTAMP_FILTER_ALL; 1319 break; 1320 default: 1321 return -ERANGE; 1322 } 1323 1324 port->tx_ts_enabled = (cfg.tx_type == HWTSTAMP_TX_ON); 1325 1326 /* cfg TX timestamp */ 1327 seq_id = (AM65_CPSW_TS_SEQ_ID_OFFSET << 1328 AM65_CPSW_PN_TS_SEQ_ID_OFFSET_SHIFT) | ETH_P_1588; 1329 1330 ts_vlan_ltype = ETH_P_8021Q; 1331 1332 ts_ctrl_ltype2 = ETH_P_1588 | 1333 AM65_CPSW_PN_TS_CTL_LTYPE2_TS_107 | 1334 AM65_CPSW_PN_TS_CTL_LTYPE2_TS_129 | 1335 AM65_CPSW_PN_TS_CTL_LTYPE2_TS_130 | 1336 AM65_CPSW_PN_TS_CTL_LTYPE2_TS_131 | 1337 AM65_CPSW_PN_TS_CTL_LTYPE2_TS_132 | 1338 AM65_CPSW_PN_TS_CTL_LTYPE2_TS_319 | 1339 AM65_CPSW_PN_TS_CTL_LTYPE2_TS_320 | 1340 AM65_CPSW_PN_TS_CTL_LTYPE2_TS_TTL_NONZERO; 1341 1342 ts_ctrl = AM65_CPSW_TS_EVENT_MSG_TYPE_BITS << 1343 AM65_CPSW_PN_TS_CTL_MSG_TYPE_EN_SHIFT; 1344 1345 if (port->tx_ts_enabled) 1346 ts_ctrl |= AM65_CPSW_TS_TX_ANX_ALL_EN | 1347 AM65_CPSW_PN_TS_CTL_TX_VLAN_LT1_EN; 1348 1349 writel(seq_id, port->port_base + AM65_CPSW_PORTN_REG_TS_SEQ_LTYPE_REG); 1350 writel(ts_vlan_ltype, port->port_base + 1351 AM65_CPSW_PORTN_REG_TS_VLAN_LTYPE_REG); 1352 writel(ts_ctrl_ltype2, port->port_base + 1353 AM65_CPSW_PORTN_REG_TS_CTL_LTYPE2); 1354 writel(ts_ctrl, port->port_base + AM65_CPSW_PORTN_REG_TS_CTL); 1355 1356 /* en/dis RX timestamp */ 1357 am65_cpts_rx_enable(common->cpts, port->rx_ts_enabled); 1358 1359 return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0; 1360 } 1361 1362 static int am65_cpsw_nuss_hwtstamp_get(struct net_device *ndev, 1363 struct ifreq *ifr) 1364 { 1365 struct am65_cpsw_port *port = am65_ndev_to_port(ndev); 1366 struct hwtstamp_config cfg; 1367 1368 if (!IS_ENABLED(CONFIG_TI_K3_AM65_CPTS)) 1369 return -EOPNOTSUPP; 1370 1371 cfg.flags = 0; 1372 cfg.tx_type = port->tx_ts_enabled ? 1373 HWTSTAMP_TX_ON : HWTSTAMP_TX_OFF; 1374 cfg.rx_filter = port->rx_ts_enabled ? 1375 HWTSTAMP_FILTER_ALL : HWTSTAMP_FILTER_NONE; 1376 1377 return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0; 1378 } 1379 1380 static int am65_cpsw_nuss_ndo_slave_ioctl(struct net_device *ndev, 1381 struct ifreq *req, int cmd) 1382 { 1383 struct am65_cpsw_port *port = am65_ndev_to_port(ndev); 1384 1385 if (!netif_running(ndev)) 1386 return -EINVAL; 1387 1388 switch (cmd) { 1389 case SIOCSHWTSTAMP: 1390 return am65_cpsw_nuss_hwtstamp_set(ndev, req); 1391 case SIOCGHWTSTAMP: 1392 return am65_cpsw_nuss_hwtstamp_get(ndev, req); 1393 } 1394 1395 return phylink_mii_ioctl(port->slave.phylink, req, cmd); 1396 } 1397 1398 static void am65_cpsw_nuss_ndo_get_stats(struct net_device *dev, 1399 struct rtnl_link_stats64 *stats) 1400 { 1401 struct am65_cpsw_ndev_priv *ndev_priv = netdev_priv(dev); 1402 unsigned int start; 1403 int cpu; 1404 1405 for_each_possible_cpu(cpu) { 1406 struct am65_cpsw_ndev_stats *cpu_stats; 1407 u64 rx_packets; 1408 u64 rx_bytes; 1409 u64 tx_packets; 1410 u64 tx_bytes; 1411 1412 cpu_stats = per_cpu_ptr(ndev_priv->stats, cpu); 1413 do { 1414 start = u64_stats_fetch_begin(&cpu_stats->syncp); 1415 rx_packets = cpu_stats->rx_packets; 1416 rx_bytes = cpu_stats->rx_bytes; 1417 tx_packets = cpu_stats->tx_packets; 1418 tx_bytes = cpu_stats->tx_bytes; 1419 } while (u64_stats_fetch_retry(&cpu_stats->syncp, start)); 1420 1421 stats->rx_packets += rx_packets; 1422 stats->rx_bytes += rx_bytes; 1423 stats->tx_packets += tx_packets; 1424 stats->tx_bytes += tx_bytes; 1425 } 1426 1427 stats->rx_errors = dev->stats.rx_errors; 1428 stats->rx_dropped = dev->stats.rx_dropped; 1429 stats->tx_dropped = dev->stats.tx_dropped; 1430 } 1431 1432 static const struct net_device_ops am65_cpsw_nuss_netdev_ops = { 1433 .ndo_open = am65_cpsw_nuss_ndo_slave_open, 1434 .ndo_stop = am65_cpsw_nuss_ndo_slave_stop, 1435 .ndo_start_xmit = am65_cpsw_nuss_ndo_slave_xmit, 1436 .ndo_set_rx_mode = am65_cpsw_nuss_ndo_slave_set_rx_mode, 1437 .ndo_get_stats64 = am65_cpsw_nuss_ndo_get_stats, 1438 .ndo_validate_addr = eth_validate_addr, 1439 .ndo_set_mac_address = am65_cpsw_nuss_ndo_slave_set_mac_address, 1440 .ndo_tx_timeout = am65_cpsw_nuss_ndo_host_tx_timeout, 1441 .ndo_vlan_rx_add_vid = am65_cpsw_nuss_ndo_slave_add_vid, 1442 .ndo_vlan_rx_kill_vid = am65_cpsw_nuss_ndo_slave_kill_vid, 1443 .ndo_eth_ioctl = am65_cpsw_nuss_ndo_slave_ioctl, 1444 .ndo_setup_tc = am65_cpsw_qos_ndo_setup_tc, 1445 }; 1446 1447 static void am65_cpsw_nuss_mac_config(struct phylink_config *config, unsigned int mode, 1448 const struct phylink_link_state *state) 1449 { 1450 struct am65_cpsw_slave_data *slave = container_of(config, struct am65_cpsw_slave_data, 1451 phylink_config); 1452 struct am65_cpsw_port *port = container_of(slave, struct am65_cpsw_port, slave); 1453 struct am65_cpsw_common *common = port->common; 1454 1455 if (common->pdata.extra_modes & BIT(state->interface)) 1456 writel(AM65_CPSW_SGMII_CONTROL_MR_AN_ENABLE, 1457 port->sgmii_base + AM65_CPSW_SGMII_CONTROL_REG); 1458 } 1459 1460 static void am65_cpsw_nuss_mac_link_down(struct phylink_config *config, unsigned int mode, 1461 phy_interface_t interface) 1462 { 1463 struct am65_cpsw_slave_data *slave = container_of(config, struct am65_cpsw_slave_data, 1464 phylink_config); 1465 struct am65_cpsw_port *port = container_of(slave, struct am65_cpsw_port, slave); 1466 struct am65_cpsw_common *common = port->common; 1467 struct net_device *ndev = port->ndev; 1468 int tmo; 1469 1470 /* disable forwarding */ 1471 cpsw_ale_control_set(common->ale, port->port_id, ALE_PORT_STATE, ALE_PORT_STATE_DISABLE); 1472 1473 cpsw_sl_ctl_set(port->slave.mac_sl, CPSW_SL_CTL_CMD_IDLE); 1474 1475 tmo = cpsw_sl_wait_for_idle(port->slave.mac_sl, 100); 1476 dev_dbg(common->dev, "down msc_sl %08x tmo %d\n", 1477 cpsw_sl_reg_read(port->slave.mac_sl, CPSW_SL_MACSTATUS), tmo); 1478 1479 cpsw_sl_ctl_reset(port->slave.mac_sl); 1480 1481 am65_cpsw_qos_link_down(ndev); 1482 netif_tx_stop_all_queues(ndev); 1483 } 1484 1485 static void am65_cpsw_nuss_mac_link_up(struct phylink_config *config, struct phy_device *phy, 1486 unsigned int mode, phy_interface_t interface, int speed, 1487 int duplex, bool tx_pause, bool rx_pause) 1488 { 1489 struct am65_cpsw_slave_data *slave = container_of(config, struct am65_cpsw_slave_data, 1490 phylink_config); 1491 struct am65_cpsw_port *port = container_of(slave, struct am65_cpsw_port, slave); 1492 struct am65_cpsw_common *common = port->common; 1493 u32 mac_control = CPSW_SL_CTL_GMII_EN; 1494 struct net_device *ndev = port->ndev; 1495 1496 if (speed == SPEED_1000) 1497 mac_control |= CPSW_SL_CTL_GIG; 1498 if (speed == SPEED_10 && interface == PHY_INTERFACE_MODE_RGMII) 1499 /* Can be used with in band mode only */ 1500 mac_control |= CPSW_SL_CTL_EXT_EN; 1501 if (speed == SPEED_100 && interface == PHY_INTERFACE_MODE_RMII) 1502 mac_control |= CPSW_SL_CTL_IFCTL_A; 1503 if (duplex) 1504 mac_control |= CPSW_SL_CTL_FULLDUPLEX; 1505 1506 /* rx_pause/tx_pause */ 1507 if (rx_pause) 1508 mac_control |= CPSW_SL_CTL_RX_FLOW_EN; 1509 1510 if (tx_pause) 1511 mac_control |= CPSW_SL_CTL_TX_FLOW_EN; 1512 1513 cpsw_sl_ctl_set(port->slave.mac_sl, mac_control); 1514 1515 /* enable forwarding */ 1516 cpsw_ale_control_set(common->ale, port->port_id, ALE_PORT_STATE, ALE_PORT_STATE_FORWARD); 1517 1518 am65_cpsw_qos_link_up(ndev, speed); 1519 netif_tx_wake_all_queues(ndev); 1520 } 1521 1522 static const struct phylink_mac_ops am65_cpsw_phylink_mac_ops = { 1523 .mac_config = am65_cpsw_nuss_mac_config, 1524 .mac_link_down = am65_cpsw_nuss_mac_link_down, 1525 .mac_link_up = am65_cpsw_nuss_mac_link_up, 1526 }; 1527 1528 static void am65_cpsw_nuss_slave_disable_unused(struct am65_cpsw_port *port) 1529 { 1530 struct am65_cpsw_common *common = port->common; 1531 1532 if (!port->disabled) 1533 return; 1534 1535 cpsw_ale_control_set(common->ale, port->port_id, 1536 ALE_PORT_STATE, ALE_PORT_STATE_DISABLE); 1537 1538 cpsw_sl_reset(port->slave.mac_sl, 100); 1539 cpsw_sl_ctl_reset(port->slave.mac_sl); 1540 } 1541 1542 static void am65_cpsw_nuss_free_tx_chns(struct am65_cpsw_common *common) 1543 { 1544 struct device *dev = common->dev; 1545 int i; 1546 1547 for (i = 0; i < common->tx_ch_num; i++) { 1548 struct am65_cpsw_tx_chn *tx_chn = &common->tx_chns[i]; 1549 1550 if (!IS_ERR_OR_NULL(tx_chn->desc_pool)) 1551 k3_cppi_desc_pool_destroy(tx_chn->desc_pool); 1552 1553 if (!IS_ERR_OR_NULL(tx_chn->tx_chn)) 1554 k3_udma_glue_release_tx_chn(tx_chn->tx_chn); 1555 1556 /* Don't clear tx_chn memory as we need to preserve 1557 * data between suspend/resume 1558 */ 1559 if (!(tx_chn->irq < 0)) 1560 devm_free_irq(dev, tx_chn->irq, tx_chn); 1561 } 1562 } 1563 1564 void am65_cpsw_nuss_remove_tx_chns(struct am65_cpsw_common *common) 1565 { 1566 struct device *dev = common->dev; 1567 int i; 1568 1569 for (i = 0; i < common->tx_ch_num; i++) { 1570 struct am65_cpsw_tx_chn *tx_chn = &common->tx_chns[i]; 1571 1572 if (!(tx_chn->irq < 0)) 1573 devm_free_irq(dev, tx_chn->irq, tx_chn); 1574 1575 netif_napi_del(&tx_chn->napi_tx); 1576 1577 if (!IS_ERR_OR_NULL(tx_chn->desc_pool)) 1578 k3_cppi_desc_pool_destroy(tx_chn->desc_pool); 1579 1580 if (!IS_ERR_OR_NULL(tx_chn->tx_chn)) 1581 k3_udma_glue_release_tx_chn(tx_chn->tx_chn); 1582 1583 memset(tx_chn, 0, sizeof(*tx_chn)); 1584 } 1585 } 1586 1587 static int am65_cpsw_nuss_init_tx_chns(struct am65_cpsw_common *common) 1588 { 1589 u32 max_desc_num = ALIGN(AM65_CPSW_MAX_TX_DESC, MAX_SKB_FRAGS); 1590 struct k3_udma_glue_tx_channel_cfg tx_cfg = { 0 }; 1591 struct device *dev = common->dev; 1592 struct k3_ring_cfg ring_cfg = { 1593 .elm_size = K3_RINGACC_RING_ELSIZE_8, 1594 .mode = K3_RINGACC_RING_MODE_RING, 1595 .flags = 0 1596 }; 1597 u32 hdesc_size; 1598 int i, ret = 0; 1599 1600 hdesc_size = cppi5_hdesc_calc_size(true, AM65_CPSW_NAV_PS_DATA_SIZE, 1601 AM65_CPSW_NAV_SW_DATA_SIZE); 1602 1603 tx_cfg.swdata_size = AM65_CPSW_NAV_SW_DATA_SIZE; 1604 tx_cfg.tx_cfg = ring_cfg; 1605 tx_cfg.txcq_cfg = ring_cfg; 1606 tx_cfg.tx_cfg.size = max_desc_num; 1607 tx_cfg.txcq_cfg.size = max_desc_num; 1608 1609 for (i = 0; i < common->tx_ch_num; i++) { 1610 struct am65_cpsw_tx_chn *tx_chn = &common->tx_chns[i]; 1611 1612 snprintf(tx_chn->tx_chn_name, 1613 sizeof(tx_chn->tx_chn_name), "tx%d", i); 1614 1615 spin_lock_init(&tx_chn->lock); 1616 tx_chn->common = common; 1617 tx_chn->id = i; 1618 tx_chn->descs_num = max_desc_num; 1619 1620 tx_chn->tx_chn = 1621 k3_udma_glue_request_tx_chn(dev, 1622 tx_chn->tx_chn_name, 1623 &tx_cfg); 1624 if (IS_ERR(tx_chn->tx_chn)) { 1625 ret = dev_err_probe(dev, PTR_ERR(tx_chn->tx_chn), 1626 "Failed to request tx dma channel\n"); 1627 goto err; 1628 } 1629 tx_chn->dma_dev = k3_udma_glue_tx_get_dma_device(tx_chn->tx_chn); 1630 1631 tx_chn->desc_pool = k3_cppi_desc_pool_create_name(tx_chn->dma_dev, 1632 tx_chn->descs_num, 1633 hdesc_size, 1634 tx_chn->tx_chn_name); 1635 if (IS_ERR(tx_chn->desc_pool)) { 1636 ret = PTR_ERR(tx_chn->desc_pool); 1637 dev_err(dev, "Failed to create poll %d\n", ret); 1638 goto err; 1639 } 1640 1641 tx_chn->irq = k3_udma_glue_tx_get_irq(tx_chn->tx_chn); 1642 if (tx_chn->irq < 0) { 1643 dev_err(dev, "Failed to get tx dma irq %d\n", 1644 tx_chn->irq); 1645 goto err; 1646 } 1647 1648 snprintf(tx_chn->tx_chn_name, 1649 sizeof(tx_chn->tx_chn_name), "%s-tx%d", 1650 dev_name(dev), tx_chn->id); 1651 1652 ret = devm_request_irq(dev, tx_chn->irq, 1653 am65_cpsw_nuss_tx_irq, 1654 IRQF_TRIGGER_HIGH, 1655 tx_chn->tx_chn_name, tx_chn); 1656 if (ret) { 1657 dev_err(dev, "failure requesting tx%u irq %u, %d\n", 1658 tx_chn->id, tx_chn->irq, ret); 1659 tx_chn->irq = -EINVAL; 1660 goto err; 1661 } 1662 } 1663 1664 return 0; 1665 1666 err: 1667 am65_cpsw_nuss_free_tx_chns(common); 1668 1669 return ret; 1670 } 1671 1672 static void am65_cpsw_nuss_free_rx_chns(struct am65_cpsw_common *common) 1673 { 1674 struct am65_cpsw_rx_chn *rx_chn; 1675 1676 rx_chn = &common->rx_chns; 1677 1678 if (!(rx_chn->irq < 0)) 1679 devm_free_irq(common->dev, rx_chn->irq, common); 1680 1681 if (!IS_ERR_OR_NULL(rx_chn->desc_pool)) 1682 k3_cppi_desc_pool_destroy(rx_chn->desc_pool); 1683 1684 if (!IS_ERR_OR_NULL(rx_chn->rx_chn)) 1685 k3_udma_glue_release_rx_chn(rx_chn->rx_chn); 1686 } 1687 1688 static int am65_cpsw_nuss_init_rx_chns(struct am65_cpsw_common *common) 1689 { 1690 struct am65_cpsw_rx_chn *rx_chn = &common->rx_chns; 1691 struct k3_udma_glue_rx_channel_cfg rx_cfg = { 0 }; 1692 u32 max_desc_num = AM65_CPSW_MAX_RX_DESC; 1693 struct device *dev = common->dev; 1694 u32 hdesc_size; 1695 u32 fdqring_id; 1696 int i, ret = 0; 1697 1698 hdesc_size = cppi5_hdesc_calc_size(true, AM65_CPSW_NAV_PS_DATA_SIZE, 1699 AM65_CPSW_NAV_SW_DATA_SIZE); 1700 1701 rx_cfg.swdata_size = AM65_CPSW_NAV_SW_DATA_SIZE; 1702 rx_cfg.flow_id_num = AM65_CPSW_MAX_RX_FLOWS; 1703 rx_cfg.flow_id_base = -1; 1704 1705 /* init all flows */ 1706 rx_chn->dev = dev; 1707 rx_chn->descs_num = max_desc_num; 1708 1709 rx_chn->rx_chn = k3_udma_glue_request_rx_chn(dev, "rx", &rx_cfg); 1710 if (IS_ERR(rx_chn->rx_chn)) { 1711 ret = dev_err_probe(dev, PTR_ERR(rx_chn->rx_chn), 1712 "Failed to request rx dma channel\n"); 1713 goto err; 1714 } 1715 rx_chn->dma_dev = k3_udma_glue_rx_get_dma_device(rx_chn->rx_chn); 1716 1717 rx_chn->desc_pool = k3_cppi_desc_pool_create_name(rx_chn->dma_dev, 1718 rx_chn->descs_num, 1719 hdesc_size, "rx"); 1720 if (IS_ERR(rx_chn->desc_pool)) { 1721 ret = PTR_ERR(rx_chn->desc_pool); 1722 dev_err(dev, "Failed to create rx poll %d\n", ret); 1723 goto err; 1724 } 1725 1726 common->rx_flow_id_base = 1727 k3_udma_glue_rx_get_flow_id_base(rx_chn->rx_chn); 1728 dev_info(dev, "set new flow-id-base %u\n", common->rx_flow_id_base); 1729 1730 fdqring_id = K3_RINGACC_RING_ID_ANY; 1731 for (i = 0; i < rx_cfg.flow_id_num; i++) { 1732 struct k3_ring_cfg rxring_cfg = { 1733 .elm_size = K3_RINGACC_RING_ELSIZE_8, 1734 .mode = K3_RINGACC_RING_MODE_RING, 1735 .flags = 0, 1736 }; 1737 struct k3_ring_cfg fdqring_cfg = { 1738 .elm_size = K3_RINGACC_RING_ELSIZE_8, 1739 .flags = K3_RINGACC_RING_SHARED, 1740 }; 1741 struct k3_udma_glue_rx_flow_cfg rx_flow_cfg = { 1742 .rx_cfg = rxring_cfg, 1743 .rxfdq_cfg = fdqring_cfg, 1744 .ring_rxq_id = K3_RINGACC_RING_ID_ANY, 1745 .src_tag_lo_sel = 1746 K3_UDMA_GLUE_SRC_TAG_LO_USE_REMOTE_SRC_TAG, 1747 }; 1748 1749 rx_flow_cfg.ring_rxfdq0_id = fdqring_id; 1750 rx_flow_cfg.rx_cfg.size = max_desc_num; 1751 rx_flow_cfg.rxfdq_cfg.size = max_desc_num; 1752 rx_flow_cfg.rxfdq_cfg.mode = common->pdata.fdqring_mode; 1753 1754 ret = k3_udma_glue_rx_flow_init(rx_chn->rx_chn, 1755 i, &rx_flow_cfg); 1756 if (ret) { 1757 dev_err(dev, "Failed to init rx flow%d %d\n", i, ret); 1758 goto err; 1759 } 1760 if (!i) 1761 fdqring_id = 1762 k3_udma_glue_rx_flow_get_fdq_id(rx_chn->rx_chn, 1763 i); 1764 1765 rx_chn->irq = k3_udma_glue_rx_get_irq(rx_chn->rx_chn, i); 1766 1767 if (rx_chn->irq <= 0) { 1768 dev_err(dev, "Failed to get rx dma irq %d\n", 1769 rx_chn->irq); 1770 ret = -ENXIO; 1771 goto err; 1772 } 1773 } 1774 1775 ret = devm_request_irq(dev, rx_chn->irq, 1776 am65_cpsw_nuss_rx_irq, 1777 IRQF_TRIGGER_HIGH, dev_name(dev), common); 1778 if (ret) { 1779 dev_err(dev, "failure requesting rx irq %u, %d\n", 1780 rx_chn->irq, ret); 1781 rx_chn->irq = -EINVAL; 1782 goto err; 1783 } 1784 1785 return 0; 1786 1787 err: 1788 am65_cpsw_nuss_free_rx_chns(common); 1789 1790 return ret; 1791 } 1792 1793 static int am65_cpsw_nuss_init_host_p(struct am65_cpsw_common *common) 1794 { 1795 struct am65_cpsw_host *host_p = am65_common_get_host(common); 1796 1797 host_p->common = common; 1798 host_p->port_base = common->cpsw_base + AM65_CPSW_NU_PORTS_BASE; 1799 host_p->stat_base = common->cpsw_base + AM65_CPSW_NU_STATS_BASE; 1800 1801 return 0; 1802 } 1803 1804 static int am65_cpsw_am654_get_efuse_macid(struct device_node *of_node, 1805 int slave, u8 *mac_addr) 1806 { 1807 u32 mac_lo, mac_hi, offset; 1808 struct regmap *syscon; 1809 int ret; 1810 1811 syscon = syscon_regmap_lookup_by_phandle(of_node, "ti,syscon-efuse"); 1812 if (IS_ERR(syscon)) { 1813 if (PTR_ERR(syscon) == -ENODEV) 1814 return 0; 1815 return PTR_ERR(syscon); 1816 } 1817 1818 ret = of_property_read_u32_index(of_node, "ti,syscon-efuse", 1, 1819 &offset); 1820 if (ret) 1821 return ret; 1822 1823 regmap_read(syscon, offset, &mac_lo); 1824 regmap_read(syscon, offset + 4, &mac_hi); 1825 1826 mac_addr[0] = (mac_hi >> 8) & 0xff; 1827 mac_addr[1] = mac_hi & 0xff; 1828 mac_addr[2] = (mac_lo >> 24) & 0xff; 1829 mac_addr[3] = (mac_lo >> 16) & 0xff; 1830 mac_addr[4] = (mac_lo >> 8) & 0xff; 1831 mac_addr[5] = mac_lo & 0xff; 1832 1833 return 0; 1834 } 1835 1836 static int am65_cpsw_init_cpts(struct am65_cpsw_common *common) 1837 { 1838 struct device *dev = common->dev; 1839 struct device_node *node; 1840 struct am65_cpts *cpts; 1841 void __iomem *reg_base; 1842 1843 if (!IS_ENABLED(CONFIG_TI_K3_AM65_CPTS)) 1844 return 0; 1845 1846 node = of_get_child_by_name(dev->of_node, "cpts"); 1847 if (!node) { 1848 dev_err(dev, "%s cpts not found\n", __func__); 1849 return -ENOENT; 1850 } 1851 1852 reg_base = common->cpsw_base + AM65_CPSW_NU_CPTS_BASE; 1853 cpts = am65_cpts_create(dev, reg_base, node); 1854 if (IS_ERR(cpts)) { 1855 int ret = PTR_ERR(cpts); 1856 1857 of_node_put(node); 1858 if (ret == -EOPNOTSUPP) { 1859 dev_info(dev, "cpts disabled\n"); 1860 return 0; 1861 } 1862 1863 dev_err(dev, "cpts create err %d\n", ret); 1864 return ret; 1865 } 1866 common->cpts = cpts; 1867 /* Forbid PM runtime if CPTS is running. 1868 * K3 CPSWxG modules may completely lose context during ON->OFF 1869 * transitions depending on integration. 1870 * AM65x/J721E MCU CPSW2G: false 1871 * J721E MAIN_CPSW9G: true 1872 */ 1873 pm_runtime_forbid(dev); 1874 1875 return 0; 1876 } 1877 1878 static int am65_cpsw_nuss_init_slave_ports(struct am65_cpsw_common *common) 1879 { 1880 struct device_node *node, *port_np; 1881 struct device *dev = common->dev; 1882 int ret; 1883 1884 node = of_get_child_by_name(dev->of_node, "ethernet-ports"); 1885 if (!node) 1886 return -ENOENT; 1887 1888 for_each_child_of_node(node, port_np) { 1889 struct am65_cpsw_port *port; 1890 u32 port_id; 1891 1892 /* it is not a slave port node, continue */ 1893 if (strcmp(port_np->name, "port")) 1894 continue; 1895 1896 ret = of_property_read_u32(port_np, "reg", &port_id); 1897 if (ret < 0) { 1898 dev_err(dev, "%pOF error reading port_id %d\n", 1899 port_np, ret); 1900 goto of_node_put; 1901 } 1902 1903 if (!port_id || port_id > common->port_num) { 1904 dev_err(dev, "%pOF has invalid port_id %u %s\n", 1905 port_np, port_id, port_np->name); 1906 ret = -EINVAL; 1907 goto of_node_put; 1908 } 1909 1910 port = am65_common_get_port(common, port_id); 1911 port->port_id = port_id; 1912 port->common = common; 1913 port->port_base = common->cpsw_base + AM65_CPSW_NU_PORTS_BASE + 1914 AM65_CPSW_NU_PORTS_OFFSET * (port_id); 1915 if (common->pdata.extra_modes) 1916 port->sgmii_base = common->ss_base + AM65_CPSW_SGMII_BASE * (port_id); 1917 port->stat_base = common->cpsw_base + AM65_CPSW_NU_STATS_BASE + 1918 (AM65_CPSW_NU_STATS_PORT_OFFSET * port_id); 1919 port->name = of_get_property(port_np, "label", NULL); 1920 port->fetch_ram_base = 1921 common->cpsw_base + AM65_CPSW_NU_FRAM_BASE + 1922 (AM65_CPSW_NU_FRAM_PORT_OFFSET * (port_id - 1)); 1923 1924 port->slave.mac_sl = cpsw_sl_get("am65", dev, port->port_base); 1925 if (IS_ERR(port->slave.mac_sl)) { 1926 ret = PTR_ERR(port->slave.mac_sl); 1927 goto of_node_put; 1928 } 1929 1930 port->disabled = !of_device_is_available(port_np); 1931 if (port->disabled) { 1932 common->disabled_ports_mask |= BIT(port->port_id); 1933 continue; 1934 } 1935 1936 port->slave.ifphy = devm_of_phy_get(dev, port_np, NULL); 1937 if (IS_ERR(port->slave.ifphy)) { 1938 ret = PTR_ERR(port->slave.ifphy); 1939 dev_err(dev, "%pOF error retrieving port phy: %d\n", 1940 port_np, ret); 1941 goto of_node_put; 1942 } 1943 1944 port->slave.mac_only = 1945 of_property_read_bool(port_np, "ti,mac-only"); 1946 1947 /* get phy/link info */ 1948 port->slave.phy_node = port_np; 1949 ret = of_get_phy_mode(port_np, &port->slave.phy_if); 1950 if (ret) { 1951 dev_err(dev, "%pOF read phy-mode err %d\n", 1952 port_np, ret); 1953 goto of_node_put; 1954 } 1955 1956 ret = phy_set_mode_ext(port->slave.ifphy, PHY_MODE_ETHERNET, port->slave.phy_if); 1957 if (ret) 1958 goto of_node_put; 1959 1960 ret = of_get_mac_address(port_np, port->slave.mac_addr); 1961 if (ret) { 1962 am65_cpsw_am654_get_efuse_macid(port_np, 1963 port->port_id, 1964 port->slave.mac_addr); 1965 if (!is_valid_ether_addr(port->slave.mac_addr)) { 1966 eth_random_addr(port->slave.mac_addr); 1967 dev_err(dev, "Use random MAC address\n"); 1968 } 1969 } 1970 } 1971 of_node_put(node); 1972 1973 /* is there at least one ext.port */ 1974 if (!(~common->disabled_ports_mask & GENMASK(common->port_num, 1))) { 1975 dev_err(dev, "No Ext. port are available\n"); 1976 return -ENODEV; 1977 } 1978 1979 return 0; 1980 1981 of_node_put: 1982 of_node_put(port_np); 1983 of_node_put(node); 1984 return ret; 1985 } 1986 1987 static void am65_cpsw_pcpu_stats_free(void *data) 1988 { 1989 struct am65_cpsw_ndev_stats __percpu *stats = data; 1990 1991 free_percpu(stats); 1992 } 1993 1994 static void am65_cpsw_nuss_phylink_cleanup(struct am65_cpsw_common *common) 1995 { 1996 struct am65_cpsw_port *port; 1997 int i; 1998 1999 for (i = 0; i < common->port_num; i++) { 2000 port = &common->ports[i]; 2001 if (port->slave.phylink) 2002 phylink_destroy(port->slave.phylink); 2003 } 2004 } 2005 2006 static int 2007 am65_cpsw_nuss_init_port_ndev(struct am65_cpsw_common *common, u32 port_idx) 2008 { 2009 struct am65_cpsw_ndev_priv *ndev_priv; 2010 struct device *dev = common->dev; 2011 struct am65_cpsw_port *port; 2012 struct phylink *phylink; 2013 int ret; 2014 2015 port = &common->ports[port_idx]; 2016 2017 if (port->disabled) 2018 return 0; 2019 2020 /* alloc netdev */ 2021 port->ndev = devm_alloc_etherdev_mqs(common->dev, 2022 sizeof(struct am65_cpsw_ndev_priv), 2023 AM65_CPSW_MAX_TX_QUEUES, 2024 AM65_CPSW_MAX_RX_QUEUES); 2025 if (!port->ndev) { 2026 dev_err(dev, "error allocating slave net_device %u\n", 2027 port->port_id); 2028 return -ENOMEM; 2029 } 2030 2031 ndev_priv = netdev_priv(port->ndev); 2032 ndev_priv->port = port; 2033 ndev_priv->msg_enable = AM65_CPSW_DEBUG; 2034 SET_NETDEV_DEV(port->ndev, dev); 2035 2036 eth_hw_addr_set(port->ndev, port->slave.mac_addr); 2037 2038 port->ndev->min_mtu = AM65_CPSW_MIN_PACKET_SIZE; 2039 port->ndev->max_mtu = AM65_CPSW_MAX_PACKET_SIZE; 2040 port->ndev->hw_features = NETIF_F_SG | 2041 NETIF_F_RXCSUM | 2042 NETIF_F_HW_CSUM | 2043 NETIF_F_HW_TC; 2044 port->ndev->features = port->ndev->hw_features | 2045 NETIF_F_HW_VLAN_CTAG_FILTER; 2046 port->ndev->vlan_features |= NETIF_F_SG; 2047 port->ndev->netdev_ops = &am65_cpsw_nuss_netdev_ops; 2048 port->ndev->ethtool_ops = &am65_cpsw_ethtool_ops_slave; 2049 2050 /* Configuring Phylink */ 2051 port->slave.phylink_config.dev = &port->ndev->dev; 2052 port->slave.phylink_config.type = PHYLINK_NETDEV; 2053 port->slave.phylink_config.mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 | MAC_1000FD; 2054 port->slave.phylink_config.mac_managed_pm = true; /* MAC does PM */ 2055 2056 if (phy_interface_mode_is_rgmii(port->slave.phy_if)) { 2057 phy_interface_set_rgmii(port->slave.phylink_config.supported_interfaces); 2058 } else if (port->slave.phy_if == PHY_INTERFACE_MODE_RMII) { 2059 __set_bit(PHY_INTERFACE_MODE_RMII, 2060 port->slave.phylink_config.supported_interfaces); 2061 } else if (common->pdata.extra_modes & BIT(port->slave.phy_if)) { 2062 __set_bit(PHY_INTERFACE_MODE_QSGMII, 2063 port->slave.phylink_config.supported_interfaces); 2064 } else { 2065 dev_err(dev, "selected phy-mode is not supported\n"); 2066 return -EOPNOTSUPP; 2067 } 2068 2069 phylink = phylink_create(&port->slave.phylink_config, 2070 of_node_to_fwnode(port->slave.phy_node), 2071 port->slave.phy_if, 2072 &am65_cpsw_phylink_mac_ops); 2073 if (IS_ERR(phylink)) 2074 return PTR_ERR(phylink); 2075 2076 port->slave.phylink = phylink; 2077 2078 /* Disable TX checksum offload by default due to HW bug */ 2079 if (common->pdata.quirks & AM65_CPSW_QUIRK_I2027_NO_TX_CSUM) 2080 port->ndev->features &= ~NETIF_F_HW_CSUM; 2081 2082 ndev_priv->stats = netdev_alloc_pcpu_stats(struct am65_cpsw_ndev_stats); 2083 if (!ndev_priv->stats) 2084 return -ENOMEM; 2085 2086 ret = devm_add_action_or_reset(dev, am65_cpsw_pcpu_stats_free, 2087 ndev_priv->stats); 2088 if (ret) 2089 dev_err(dev, "failed to add percpu stat free action %d\n", ret); 2090 2091 if (!common->dma_ndev) 2092 common->dma_ndev = port->ndev; 2093 2094 return ret; 2095 } 2096 2097 static int am65_cpsw_nuss_init_ndevs(struct am65_cpsw_common *common) 2098 { 2099 int ret; 2100 int i; 2101 2102 for (i = 0; i < common->port_num; i++) { 2103 ret = am65_cpsw_nuss_init_port_ndev(common, i); 2104 if (ret) 2105 return ret; 2106 } 2107 2108 netif_napi_add(common->dma_ndev, &common->napi_rx, 2109 am65_cpsw_nuss_rx_poll); 2110 2111 return ret; 2112 } 2113 2114 static int am65_cpsw_nuss_ndev_add_tx_napi(struct am65_cpsw_common *common) 2115 { 2116 int i; 2117 2118 for (i = 0; i < common->tx_ch_num; i++) { 2119 struct am65_cpsw_tx_chn *tx_chn = &common->tx_chns[i]; 2120 2121 netif_napi_add_tx(common->dma_ndev, &tx_chn->napi_tx, 2122 am65_cpsw_nuss_tx_poll); 2123 } 2124 2125 return 0; 2126 } 2127 2128 static void am65_cpsw_nuss_cleanup_ndev(struct am65_cpsw_common *common) 2129 { 2130 struct am65_cpsw_port *port; 2131 int i; 2132 2133 for (i = 0; i < common->port_num; i++) { 2134 port = &common->ports[i]; 2135 if (port->ndev) 2136 unregister_netdev(port->ndev); 2137 } 2138 } 2139 2140 static void am65_cpsw_port_offload_fwd_mark_update(struct am65_cpsw_common *common) 2141 { 2142 int set_val = 0; 2143 int i; 2144 2145 if (common->br_members == (GENMASK(common->port_num, 1) & ~common->disabled_ports_mask)) 2146 set_val = 1; 2147 2148 dev_dbg(common->dev, "set offload_fwd_mark %d\n", set_val); 2149 2150 for (i = 1; i <= common->port_num; i++) { 2151 struct am65_cpsw_port *port = am65_common_get_port(common, i); 2152 struct am65_cpsw_ndev_priv *priv; 2153 2154 if (!port->ndev) 2155 continue; 2156 2157 priv = am65_ndev_to_priv(port->ndev); 2158 priv->offload_fwd_mark = set_val; 2159 } 2160 } 2161 2162 bool am65_cpsw_port_dev_check(const struct net_device *ndev) 2163 { 2164 if (ndev->netdev_ops == &am65_cpsw_nuss_netdev_ops) { 2165 struct am65_cpsw_common *common = am65_ndev_to_common(ndev); 2166 2167 return !common->is_emac_mode; 2168 } 2169 2170 return false; 2171 } 2172 2173 static int am65_cpsw_netdevice_port_link(struct net_device *ndev, 2174 struct net_device *br_ndev, 2175 struct netlink_ext_ack *extack) 2176 { 2177 struct am65_cpsw_common *common = am65_ndev_to_common(ndev); 2178 struct am65_cpsw_ndev_priv *priv = am65_ndev_to_priv(ndev); 2179 int err; 2180 2181 if (!common->br_members) { 2182 common->hw_bridge_dev = br_ndev; 2183 } else { 2184 /* This is adding the port to a second bridge, this is 2185 * unsupported 2186 */ 2187 if (common->hw_bridge_dev != br_ndev) 2188 return -EOPNOTSUPP; 2189 } 2190 2191 err = switchdev_bridge_port_offload(ndev, ndev, NULL, NULL, NULL, 2192 false, extack); 2193 if (err) 2194 return err; 2195 2196 common->br_members |= BIT(priv->port->port_id); 2197 2198 am65_cpsw_port_offload_fwd_mark_update(common); 2199 2200 return NOTIFY_DONE; 2201 } 2202 2203 static void am65_cpsw_netdevice_port_unlink(struct net_device *ndev) 2204 { 2205 struct am65_cpsw_common *common = am65_ndev_to_common(ndev); 2206 struct am65_cpsw_ndev_priv *priv = am65_ndev_to_priv(ndev); 2207 2208 switchdev_bridge_port_unoffload(ndev, NULL, NULL, NULL); 2209 2210 common->br_members &= ~BIT(priv->port->port_id); 2211 2212 am65_cpsw_port_offload_fwd_mark_update(common); 2213 2214 if (!common->br_members) 2215 common->hw_bridge_dev = NULL; 2216 } 2217 2218 /* netdev notifier */ 2219 static int am65_cpsw_netdevice_event(struct notifier_block *unused, 2220 unsigned long event, void *ptr) 2221 { 2222 struct netlink_ext_ack *extack = netdev_notifier_info_to_extack(ptr); 2223 struct net_device *ndev = netdev_notifier_info_to_dev(ptr); 2224 struct netdev_notifier_changeupper_info *info; 2225 int ret = NOTIFY_DONE; 2226 2227 if (!am65_cpsw_port_dev_check(ndev)) 2228 return NOTIFY_DONE; 2229 2230 switch (event) { 2231 case NETDEV_CHANGEUPPER: 2232 info = ptr; 2233 2234 if (netif_is_bridge_master(info->upper_dev)) { 2235 if (info->linking) 2236 ret = am65_cpsw_netdevice_port_link(ndev, 2237 info->upper_dev, 2238 extack); 2239 else 2240 am65_cpsw_netdevice_port_unlink(ndev); 2241 } 2242 break; 2243 default: 2244 return NOTIFY_DONE; 2245 } 2246 2247 return notifier_from_errno(ret); 2248 } 2249 2250 static int am65_cpsw_register_notifiers(struct am65_cpsw_common *cpsw) 2251 { 2252 int ret = 0; 2253 2254 if (AM65_CPSW_IS_CPSW2G(cpsw) || 2255 !IS_REACHABLE(CONFIG_TI_K3_AM65_CPSW_SWITCHDEV)) 2256 return 0; 2257 2258 cpsw->am65_cpsw_netdevice_nb.notifier_call = &am65_cpsw_netdevice_event; 2259 ret = register_netdevice_notifier(&cpsw->am65_cpsw_netdevice_nb); 2260 if (ret) { 2261 dev_err(cpsw->dev, "can't register netdevice notifier\n"); 2262 return ret; 2263 } 2264 2265 ret = am65_cpsw_switchdev_register_notifiers(cpsw); 2266 if (ret) 2267 unregister_netdevice_notifier(&cpsw->am65_cpsw_netdevice_nb); 2268 2269 return ret; 2270 } 2271 2272 static void am65_cpsw_unregister_notifiers(struct am65_cpsw_common *cpsw) 2273 { 2274 if (AM65_CPSW_IS_CPSW2G(cpsw) || 2275 !IS_REACHABLE(CONFIG_TI_K3_AM65_CPSW_SWITCHDEV)) 2276 return; 2277 2278 am65_cpsw_switchdev_unregister_notifiers(cpsw); 2279 unregister_netdevice_notifier(&cpsw->am65_cpsw_netdevice_nb); 2280 } 2281 2282 static const struct devlink_ops am65_cpsw_devlink_ops = {}; 2283 2284 static void am65_cpsw_init_stp_ale_entry(struct am65_cpsw_common *cpsw) 2285 { 2286 cpsw_ale_add_mcast(cpsw->ale, eth_stp_addr, ALE_PORT_HOST, ALE_SUPER, 0, 2287 ALE_MCAST_BLOCK_LEARN_FWD); 2288 } 2289 2290 static void am65_cpsw_init_host_port_switch(struct am65_cpsw_common *common) 2291 { 2292 struct am65_cpsw_host *host = am65_common_get_host(common); 2293 2294 writel(common->default_vlan, host->port_base + AM65_CPSW_PORT_VLAN_REG_OFFSET); 2295 2296 am65_cpsw_init_stp_ale_entry(common); 2297 2298 cpsw_ale_control_set(common->ale, HOST_PORT_NUM, ALE_P0_UNI_FLOOD, 1); 2299 dev_dbg(common->dev, "Set P0_UNI_FLOOD\n"); 2300 cpsw_ale_control_set(common->ale, HOST_PORT_NUM, ALE_PORT_NOLEARN, 0); 2301 } 2302 2303 static void am65_cpsw_init_host_port_emac(struct am65_cpsw_common *common) 2304 { 2305 struct am65_cpsw_host *host = am65_common_get_host(common); 2306 2307 writel(0, host->port_base + AM65_CPSW_PORT_VLAN_REG_OFFSET); 2308 2309 cpsw_ale_control_set(common->ale, HOST_PORT_NUM, ALE_P0_UNI_FLOOD, 0); 2310 dev_dbg(common->dev, "unset P0_UNI_FLOOD\n"); 2311 2312 /* learning make no sense in multi-mac mode */ 2313 cpsw_ale_control_set(common->ale, HOST_PORT_NUM, ALE_PORT_NOLEARN, 1); 2314 } 2315 2316 static int am65_cpsw_dl_switch_mode_get(struct devlink *dl, u32 id, 2317 struct devlink_param_gset_ctx *ctx) 2318 { 2319 struct am65_cpsw_devlink *dl_priv = devlink_priv(dl); 2320 struct am65_cpsw_common *common = dl_priv->common; 2321 2322 dev_dbg(common->dev, "%s id:%u\n", __func__, id); 2323 2324 if (id != AM65_CPSW_DL_PARAM_SWITCH_MODE) 2325 return -EOPNOTSUPP; 2326 2327 ctx->val.vbool = !common->is_emac_mode; 2328 2329 return 0; 2330 } 2331 2332 static void am65_cpsw_init_port_emac_ale(struct am65_cpsw_port *port) 2333 { 2334 struct am65_cpsw_slave_data *slave = &port->slave; 2335 struct am65_cpsw_common *common = port->common; 2336 u32 port_mask; 2337 2338 writel(slave->port_vlan, port->port_base + AM65_CPSW_PORT_VLAN_REG_OFFSET); 2339 2340 if (slave->mac_only) 2341 /* enable mac-only mode on port */ 2342 cpsw_ale_control_set(common->ale, port->port_id, 2343 ALE_PORT_MACONLY, 1); 2344 2345 cpsw_ale_control_set(common->ale, port->port_id, ALE_PORT_NOLEARN, 1); 2346 2347 port_mask = BIT(port->port_id) | ALE_PORT_HOST; 2348 2349 cpsw_ale_add_ucast(common->ale, port->ndev->dev_addr, 2350 HOST_PORT_NUM, ALE_SECURE, slave->port_vlan); 2351 cpsw_ale_add_mcast(common->ale, port->ndev->broadcast, 2352 port_mask, ALE_VLAN, slave->port_vlan, ALE_MCAST_FWD_2); 2353 } 2354 2355 static void am65_cpsw_init_port_switch_ale(struct am65_cpsw_port *port) 2356 { 2357 struct am65_cpsw_slave_data *slave = &port->slave; 2358 struct am65_cpsw_common *cpsw = port->common; 2359 u32 port_mask; 2360 2361 cpsw_ale_control_set(cpsw->ale, port->port_id, 2362 ALE_PORT_NOLEARN, 0); 2363 2364 cpsw_ale_add_ucast(cpsw->ale, port->ndev->dev_addr, 2365 HOST_PORT_NUM, ALE_SECURE | ALE_BLOCKED | ALE_VLAN, 2366 slave->port_vlan); 2367 2368 port_mask = BIT(port->port_id) | ALE_PORT_HOST; 2369 2370 cpsw_ale_add_mcast(cpsw->ale, port->ndev->broadcast, 2371 port_mask, ALE_VLAN, slave->port_vlan, 2372 ALE_MCAST_FWD_2); 2373 2374 writel(slave->port_vlan, port->port_base + AM65_CPSW_PORT_VLAN_REG_OFFSET); 2375 2376 cpsw_ale_control_set(cpsw->ale, port->port_id, 2377 ALE_PORT_MACONLY, 0); 2378 } 2379 2380 static int am65_cpsw_dl_switch_mode_set(struct devlink *dl, u32 id, 2381 struct devlink_param_gset_ctx *ctx) 2382 { 2383 struct am65_cpsw_devlink *dl_priv = devlink_priv(dl); 2384 struct am65_cpsw_common *cpsw = dl_priv->common; 2385 bool switch_en = ctx->val.vbool; 2386 bool if_running = false; 2387 int i; 2388 2389 dev_dbg(cpsw->dev, "%s id:%u\n", __func__, id); 2390 2391 if (id != AM65_CPSW_DL_PARAM_SWITCH_MODE) 2392 return -EOPNOTSUPP; 2393 2394 if (switch_en == !cpsw->is_emac_mode) 2395 return 0; 2396 2397 if (!switch_en && cpsw->br_members) { 2398 dev_err(cpsw->dev, "Remove ports from bridge before disabling switch mode\n"); 2399 return -EINVAL; 2400 } 2401 2402 rtnl_lock(); 2403 2404 cpsw->is_emac_mode = !switch_en; 2405 2406 for (i = 0; i < cpsw->port_num; i++) { 2407 struct net_device *sl_ndev = cpsw->ports[i].ndev; 2408 2409 if (!sl_ndev || !netif_running(sl_ndev)) 2410 continue; 2411 2412 if_running = true; 2413 } 2414 2415 if (!if_running) { 2416 /* all ndevs are down */ 2417 for (i = 0; i < cpsw->port_num; i++) { 2418 struct net_device *sl_ndev = cpsw->ports[i].ndev; 2419 struct am65_cpsw_slave_data *slave; 2420 2421 if (!sl_ndev) 2422 continue; 2423 2424 slave = am65_ndev_to_slave(sl_ndev); 2425 if (switch_en) 2426 slave->port_vlan = cpsw->default_vlan; 2427 else 2428 slave->port_vlan = 0; 2429 } 2430 2431 goto exit; 2432 } 2433 2434 cpsw_ale_control_set(cpsw->ale, 0, ALE_BYPASS, 1); 2435 /* clean up ALE table */ 2436 cpsw_ale_control_set(cpsw->ale, HOST_PORT_NUM, ALE_CLEAR, 1); 2437 cpsw_ale_control_get(cpsw->ale, HOST_PORT_NUM, ALE_AGEOUT); 2438 2439 if (switch_en) { 2440 dev_info(cpsw->dev, "Enable switch mode\n"); 2441 2442 am65_cpsw_init_host_port_switch(cpsw); 2443 2444 for (i = 0; i < cpsw->port_num; i++) { 2445 struct net_device *sl_ndev = cpsw->ports[i].ndev; 2446 struct am65_cpsw_slave_data *slave; 2447 struct am65_cpsw_port *port; 2448 2449 if (!sl_ndev) 2450 continue; 2451 2452 port = am65_ndev_to_port(sl_ndev); 2453 slave = am65_ndev_to_slave(sl_ndev); 2454 slave->port_vlan = cpsw->default_vlan; 2455 2456 if (netif_running(sl_ndev)) 2457 am65_cpsw_init_port_switch_ale(port); 2458 } 2459 2460 } else { 2461 dev_info(cpsw->dev, "Disable switch mode\n"); 2462 2463 am65_cpsw_init_host_port_emac(cpsw); 2464 2465 for (i = 0; i < cpsw->port_num; i++) { 2466 struct net_device *sl_ndev = cpsw->ports[i].ndev; 2467 struct am65_cpsw_port *port; 2468 2469 if (!sl_ndev) 2470 continue; 2471 2472 port = am65_ndev_to_port(sl_ndev); 2473 port->slave.port_vlan = 0; 2474 if (netif_running(sl_ndev)) 2475 am65_cpsw_init_port_emac_ale(port); 2476 } 2477 } 2478 cpsw_ale_control_set(cpsw->ale, HOST_PORT_NUM, ALE_BYPASS, 0); 2479 exit: 2480 rtnl_unlock(); 2481 2482 return 0; 2483 } 2484 2485 static const struct devlink_param am65_cpsw_devlink_params[] = { 2486 DEVLINK_PARAM_DRIVER(AM65_CPSW_DL_PARAM_SWITCH_MODE, "switch_mode", 2487 DEVLINK_PARAM_TYPE_BOOL, 2488 BIT(DEVLINK_PARAM_CMODE_RUNTIME), 2489 am65_cpsw_dl_switch_mode_get, 2490 am65_cpsw_dl_switch_mode_set, NULL), 2491 }; 2492 2493 static int am65_cpsw_nuss_register_devlink(struct am65_cpsw_common *common) 2494 { 2495 struct devlink_port_attrs attrs = {}; 2496 struct am65_cpsw_devlink *dl_priv; 2497 struct device *dev = common->dev; 2498 struct devlink_port *dl_port; 2499 struct am65_cpsw_port *port; 2500 int ret = 0; 2501 int i; 2502 2503 common->devlink = 2504 devlink_alloc(&am65_cpsw_devlink_ops, sizeof(*dl_priv), dev); 2505 if (!common->devlink) 2506 return -ENOMEM; 2507 2508 dl_priv = devlink_priv(common->devlink); 2509 dl_priv->common = common; 2510 2511 /* Provide devlink hook to switch mode when multiple external ports 2512 * are present NUSS switchdev driver is enabled. 2513 */ 2514 if (!AM65_CPSW_IS_CPSW2G(common) && 2515 IS_ENABLED(CONFIG_TI_K3_AM65_CPSW_SWITCHDEV)) { 2516 ret = devlink_params_register(common->devlink, 2517 am65_cpsw_devlink_params, 2518 ARRAY_SIZE(am65_cpsw_devlink_params)); 2519 if (ret) { 2520 dev_err(dev, "devlink params reg fail ret:%d\n", ret); 2521 goto dl_unreg; 2522 } 2523 } 2524 2525 for (i = 1; i <= common->port_num; i++) { 2526 port = am65_common_get_port(common, i); 2527 dl_port = &port->devlink_port; 2528 2529 if (port->ndev) 2530 attrs.flavour = DEVLINK_PORT_FLAVOUR_PHYSICAL; 2531 else 2532 attrs.flavour = DEVLINK_PORT_FLAVOUR_UNUSED; 2533 attrs.phys.port_number = port->port_id; 2534 attrs.switch_id.id_len = sizeof(resource_size_t); 2535 memcpy(attrs.switch_id.id, common->switch_id, attrs.switch_id.id_len); 2536 devlink_port_attrs_set(dl_port, &attrs); 2537 2538 ret = devlink_port_register(common->devlink, dl_port, port->port_id); 2539 if (ret) { 2540 dev_err(dev, "devlink_port reg fail for port %d, ret:%d\n", 2541 port->port_id, ret); 2542 goto dl_port_unreg; 2543 } 2544 } 2545 devlink_register(common->devlink); 2546 return ret; 2547 2548 dl_port_unreg: 2549 for (i = i - 1; i >= 1; i--) { 2550 port = am65_common_get_port(common, i); 2551 dl_port = &port->devlink_port; 2552 2553 devlink_port_unregister(dl_port); 2554 } 2555 dl_unreg: 2556 devlink_free(common->devlink); 2557 return ret; 2558 } 2559 2560 static void am65_cpsw_unregister_devlink(struct am65_cpsw_common *common) 2561 { 2562 struct devlink_port *dl_port; 2563 struct am65_cpsw_port *port; 2564 int i; 2565 2566 devlink_unregister(common->devlink); 2567 2568 for (i = 1; i <= common->port_num; i++) { 2569 port = am65_common_get_port(common, i); 2570 dl_port = &port->devlink_port; 2571 2572 devlink_port_unregister(dl_port); 2573 } 2574 2575 if (!AM65_CPSW_IS_CPSW2G(common) && 2576 IS_ENABLED(CONFIG_TI_K3_AM65_CPSW_SWITCHDEV)) 2577 devlink_params_unregister(common->devlink, 2578 am65_cpsw_devlink_params, 2579 ARRAY_SIZE(am65_cpsw_devlink_params)); 2580 2581 devlink_free(common->devlink); 2582 } 2583 2584 static int am65_cpsw_nuss_register_ndevs(struct am65_cpsw_common *common) 2585 { 2586 struct device *dev = common->dev; 2587 struct am65_cpsw_port *port; 2588 int ret = 0, i; 2589 2590 ret = am65_cpsw_nuss_ndev_add_tx_napi(common); 2591 if (ret) 2592 return ret; 2593 2594 ret = am65_cpsw_nuss_register_devlink(common); 2595 if (ret) 2596 return ret; 2597 2598 for (i = 0; i < common->port_num; i++) { 2599 port = &common->ports[i]; 2600 2601 if (!port->ndev) 2602 continue; 2603 2604 SET_NETDEV_DEVLINK_PORT(port->ndev, &port->devlink_port); 2605 2606 ret = register_netdev(port->ndev); 2607 if (ret) { 2608 dev_err(dev, "error registering slave net device%i %d\n", 2609 i, ret); 2610 goto err_cleanup_ndev; 2611 } 2612 } 2613 2614 ret = am65_cpsw_register_notifiers(common); 2615 if (ret) 2616 goto err_cleanup_ndev; 2617 2618 /* can't auto unregister ndev using devm_add_action() due to 2619 * devres release sequence in DD core for DMA 2620 */ 2621 2622 return 0; 2623 2624 err_cleanup_ndev: 2625 am65_cpsw_nuss_cleanup_ndev(common); 2626 am65_cpsw_unregister_devlink(common); 2627 2628 return ret; 2629 } 2630 2631 int am65_cpsw_nuss_update_tx_chns(struct am65_cpsw_common *common, int num_tx) 2632 { 2633 int ret; 2634 2635 common->tx_ch_num = num_tx; 2636 ret = am65_cpsw_nuss_init_tx_chns(common); 2637 if (ret) 2638 return ret; 2639 2640 return am65_cpsw_nuss_ndev_add_tx_napi(common); 2641 } 2642 2643 struct am65_cpsw_soc_pdata { 2644 u32 quirks_dis; 2645 }; 2646 2647 static const struct am65_cpsw_soc_pdata am65x_soc_sr2_0 = { 2648 .quirks_dis = AM65_CPSW_QUIRK_I2027_NO_TX_CSUM, 2649 }; 2650 2651 static const struct soc_device_attribute am65_cpsw_socinfo[] = { 2652 { .family = "AM65X", 2653 .revision = "SR2.0", 2654 .data = &am65x_soc_sr2_0 2655 }, 2656 {/* sentinel */} 2657 }; 2658 2659 static const struct am65_cpsw_pdata am65x_sr1_0 = { 2660 .quirks = AM65_CPSW_QUIRK_I2027_NO_TX_CSUM, 2661 .ale_dev_id = "am65x-cpsw2g", 2662 .fdqring_mode = K3_RINGACC_RING_MODE_MESSAGE, 2663 }; 2664 2665 static const struct am65_cpsw_pdata j721e_pdata = { 2666 .quirks = 0, 2667 .ale_dev_id = "am65x-cpsw2g", 2668 .fdqring_mode = K3_RINGACC_RING_MODE_MESSAGE, 2669 }; 2670 2671 static const struct am65_cpsw_pdata am64x_cpswxg_pdata = { 2672 .quirks = 0, 2673 .ale_dev_id = "am64-cpswxg", 2674 .fdqring_mode = K3_RINGACC_RING_MODE_RING, 2675 }; 2676 2677 static const struct am65_cpsw_pdata j7200_cpswxg_pdata = { 2678 .quirks = 0, 2679 .ale_dev_id = "am64-cpswxg", 2680 .fdqring_mode = K3_RINGACC_RING_MODE_RING, 2681 .extra_modes = BIT(PHY_INTERFACE_MODE_QSGMII), 2682 }; 2683 2684 static const struct of_device_id am65_cpsw_nuss_of_mtable[] = { 2685 { .compatible = "ti,am654-cpsw-nuss", .data = &am65x_sr1_0}, 2686 { .compatible = "ti,j721e-cpsw-nuss", .data = &j721e_pdata}, 2687 { .compatible = "ti,am642-cpsw-nuss", .data = &am64x_cpswxg_pdata}, 2688 { .compatible = "ti,j7200-cpswxg-nuss", .data = &j7200_cpswxg_pdata}, 2689 { /* sentinel */ }, 2690 }; 2691 MODULE_DEVICE_TABLE(of, am65_cpsw_nuss_of_mtable); 2692 2693 static void am65_cpsw_nuss_apply_socinfo(struct am65_cpsw_common *common) 2694 { 2695 const struct soc_device_attribute *soc; 2696 2697 soc = soc_device_match(am65_cpsw_socinfo); 2698 if (soc && soc->data) { 2699 const struct am65_cpsw_soc_pdata *socdata = soc->data; 2700 2701 /* disable quirks */ 2702 common->pdata.quirks &= ~socdata->quirks_dis; 2703 } 2704 } 2705 2706 static int am65_cpsw_nuss_probe(struct platform_device *pdev) 2707 { 2708 struct cpsw_ale_params ale_params = { 0 }; 2709 const struct of_device_id *of_id; 2710 struct device *dev = &pdev->dev; 2711 struct am65_cpsw_common *common; 2712 struct device_node *node; 2713 struct resource *res; 2714 struct clk *clk; 2715 u64 id_temp; 2716 int ret, i; 2717 int ale_entries; 2718 2719 common = devm_kzalloc(dev, sizeof(struct am65_cpsw_common), GFP_KERNEL); 2720 if (!common) 2721 return -ENOMEM; 2722 common->dev = dev; 2723 2724 of_id = of_match_device(am65_cpsw_nuss_of_mtable, dev); 2725 if (!of_id) 2726 return -EINVAL; 2727 common->pdata = *(const struct am65_cpsw_pdata *)of_id->data; 2728 2729 am65_cpsw_nuss_apply_socinfo(common); 2730 2731 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cpsw_nuss"); 2732 common->ss_base = devm_ioremap_resource(&pdev->dev, res); 2733 if (IS_ERR(common->ss_base)) 2734 return PTR_ERR(common->ss_base); 2735 common->cpsw_base = common->ss_base + AM65_CPSW_CPSW_NU_BASE; 2736 /* Use device's physical base address as switch id */ 2737 id_temp = cpu_to_be64(res->start); 2738 memcpy(common->switch_id, &id_temp, sizeof(res->start)); 2739 2740 node = of_get_child_by_name(dev->of_node, "ethernet-ports"); 2741 if (!node) 2742 return -ENOENT; 2743 common->port_num = of_get_child_count(node); 2744 of_node_put(node); 2745 if (common->port_num < 1 || common->port_num > AM65_CPSW_MAX_PORTS) 2746 return -ENOENT; 2747 2748 init_completion(&common->tdown_complete); 2749 common->tx_ch_num = 1; 2750 common->pf_p0_rx_ptype_rrobin = false; 2751 common->default_vlan = 1; 2752 2753 common->ports = devm_kcalloc(dev, common->port_num, 2754 sizeof(*common->ports), 2755 GFP_KERNEL); 2756 if (!common->ports) 2757 return -ENOMEM; 2758 2759 clk = devm_clk_get(dev, "fck"); 2760 if (IS_ERR(clk)) 2761 return dev_err_probe(dev, PTR_ERR(clk), "getting fck clock\n"); 2762 common->bus_freq = clk_get_rate(clk); 2763 2764 pm_runtime_enable(dev); 2765 ret = pm_runtime_resume_and_get(dev); 2766 if (ret < 0) { 2767 pm_runtime_disable(dev); 2768 return ret; 2769 } 2770 2771 node = of_get_child_by_name(dev->of_node, "mdio"); 2772 if (!node) { 2773 dev_warn(dev, "MDIO node not found\n"); 2774 } else if (of_device_is_available(node)) { 2775 struct platform_device *mdio_pdev; 2776 2777 mdio_pdev = of_platform_device_create(node, NULL, dev); 2778 if (!mdio_pdev) { 2779 ret = -ENODEV; 2780 goto err_pm_clear; 2781 } 2782 2783 common->mdio_dev = &mdio_pdev->dev; 2784 } 2785 of_node_put(node); 2786 2787 am65_cpsw_nuss_get_ver(common); 2788 2789 ret = am65_cpsw_nuss_init_host_p(common); 2790 if (ret) 2791 goto err_of_clear; 2792 2793 ret = am65_cpsw_nuss_init_slave_ports(common); 2794 if (ret) 2795 goto err_of_clear; 2796 2797 /* init common data */ 2798 ale_params.dev = dev; 2799 ale_params.ale_ageout = AM65_CPSW_ALE_AGEOUT_DEFAULT; 2800 ale_params.ale_ports = common->port_num + 1; 2801 ale_params.ale_regs = common->cpsw_base + AM65_CPSW_NU_ALE_BASE; 2802 ale_params.dev_id = common->pdata.ale_dev_id; 2803 ale_params.bus_freq = common->bus_freq; 2804 2805 common->ale = cpsw_ale_create(&ale_params); 2806 if (IS_ERR(common->ale)) { 2807 dev_err(dev, "error initializing ale engine\n"); 2808 ret = PTR_ERR(common->ale); 2809 goto err_of_clear; 2810 } 2811 2812 ale_entries = common->ale->params.ale_entries; 2813 common->ale_context = devm_kzalloc(dev, 2814 ale_entries * ALE_ENTRY_WORDS * sizeof(u32), 2815 GFP_KERNEL); 2816 ret = am65_cpsw_init_cpts(common); 2817 if (ret) 2818 goto err_of_clear; 2819 2820 /* init ports */ 2821 for (i = 0; i < common->port_num; i++) 2822 am65_cpsw_nuss_slave_disable_unused(&common->ports[i]); 2823 2824 dev_set_drvdata(dev, common); 2825 2826 common->is_emac_mode = true; 2827 2828 ret = am65_cpsw_nuss_init_ndevs(common); 2829 if (ret) 2830 goto err_free_phylink; 2831 2832 ret = am65_cpsw_nuss_register_ndevs(common); 2833 if (ret) 2834 goto err_free_phylink; 2835 2836 pm_runtime_put(dev); 2837 return 0; 2838 2839 err_free_phylink: 2840 am65_cpsw_nuss_phylink_cleanup(common); 2841 err_of_clear: 2842 of_platform_device_destroy(common->mdio_dev, NULL); 2843 err_pm_clear: 2844 pm_runtime_put_sync(dev); 2845 pm_runtime_disable(dev); 2846 return ret; 2847 } 2848 2849 static int am65_cpsw_nuss_remove(struct platform_device *pdev) 2850 { 2851 struct device *dev = &pdev->dev; 2852 struct am65_cpsw_common *common; 2853 int ret; 2854 2855 common = dev_get_drvdata(dev); 2856 2857 ret = pm_runtime_resume_and_get(&pdev->dev); 2858 if (ret < 0) 2859 return ret; 2860 2861 am65_cpsw_nuss_phylink_cleanup(common); 2862 am65_cpsw_unregister_devlink(common); 2863 am65_cpsw_unregister_notifiers(common); 2864 2865 /* must unregister ndevs here because DD release_driver routine calls 2866 * dma_deconfigure(dev) before devres_release_all(dev) 2867 */ 2868 am65_cpsw_nuss_cleanup_ndev(common); 2869 2870 of_platform_device_destroy(common->mdio_dev, NULL); 2871 2872 pm_runtime_put_sync(&pdev->dev); 2873 pm_runtime_disable(&pdev->dev); 2874 return 0; 2875 } 2876 2877 #ifdef CONFIG_PM_SLEEP 2878 static int am65_cpsw_nuss_suspend(struct device *dev) 2879 { 2880 struct am65_cpsw_common *common = dev_get_drvdata(dev); 2881 struct am65_cpsw_port *port; 2882 struct net_device *ndev; 2883 int i, ret; 2884 struct am65_cpsw_host *host_p = am65_common_get_host(common); 2885 2886 cpsw_ale_dump(common->ale, common->ale_context); 2887 host_p->vid_context = readl(host_p->port_base + AM65_CPSW_PORT_VLAN_REG_OFFSET); 2888 for (i = 0; i < common->port_num; i++) { 2889 port = &common->ports[i]; 2890 ndev = port->ndev; 2891 2892 if (!ndev) 2893 continue; 2894 2895 port->vid_context = readl(port->port_base + AM65_CPSW_PORT_VLAN_REG_OFFSET); 2896 netif_device_detach(ndev); 2897 if (netif_running(ndev)) { 2898 rtnl_lock(); 2899 ret = am65_cpsw_nuss_ndo_slave_stop(ndev); 2900 rtnl_unlock(); 2901 if (ret < 0) { 2902 netdev_err(ndev, "failed to stop: %d", ret); 2903 return ret; 2904 } 2905 } 2906 } 2907 2908 am65_cpts_suspend(common->cpts); 2909 2910 return 0; 2911 } 2912 2913 static int am65_cpsw_nuss_resume(struct device *dev) 2914 { 2915 struct am65_cpsw_common *common = dev_get_drvdata(dev); 2916 struct am65_cpsw_port *port; 2917 struct net_device *ndev; 2918 int i, ret; 2919 struct am65_cpsw_host *host_p = am65_common_get_host(common); 2920 2921 am65_cpts_resume(common->cpts); 2922 2923 for (i = 0; i < common->port_num; i++) { 2924 port = &common->ports[i]; 2925 ndev = port->ndev; 2926 2927 if (!ndev) 2928 continue; 2929 2930 if (netif_running(ndev)) { 2931 rtnl_lock(); 2932 ret = am65_cpsw_nuss_ndo_slave_open(ndev); 2933 rtnl_unlock(); 2934 if (ret < 0) { 2935 netdev_err(ndev, "failed to start: %d", ret); 2936 return ret; 2937 } 2938 } 2939 2940 netif_device_attach(ndev); 2941 writel(port->vid_context, port->port_base + AM65_CPSW_PORT_VLAN_REG_OFFSET); 2942 } 2943 2944 writel(host_p->vid_context, host_p->port_base + AM65_CPSW_PORT_VLAN_REG_OFFSET); 2945 cpsw_ale_restore(common->ale, common->ale_context); 2946 2947 return 0; 2948 } 2949 #endif /* CONFIG_PM_SLEEP */ 2950 2951 static const struct dev_pm_ops am65_cpsw_nuss_dev_pm_ops = { 2952 SET_SYSTEM_SLEEP_PM_OPS(am65_cpsw_nuss_suspend, am65_cpsw_nuss_resume) 2953 }; 2954 2955 static struct platform_driver am65_cpsw_nuss_driver = { 2956 .driver = { 2957 .name = AM65_CPSW_DRV_NAME, 2958 .of_match_table = am65_cpsw_nuss_of_mtable, 2959 .pm = &am65_cpsw_nuss_dev_pm_ops, 2960 }, 2961 .probe = am65_cpsw_nuss_probe, 2962 .remove = am65_cpsw_nuss_remove, 2963 }; 2964 2965 module_platform_driver(am65_cpsw_nuss_driver); 2966 2967 MODULE_LICENSE("GPL v2"); 2968 MODULE_AUTHOR("Grygorii Strashko <grygorii.strashko@ti.com>"); 2969 MODULE_DESCRIPTION("TI AM65 CPSW Ethernet driver"); 2970