1 // SPDX-License-Identifier: GPL-2.0 2 /* Texas Instruments K3 AM65 Ethernet Switch SubSystem Driver 3 * 4 * Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/ 5 * 6 */ 7 8 #include <linux/clk.h> 9 #include <linux/etherdevice.h> 10 #include <linux/if_vlan.h> 11 #include <linux/interrupt.h> 12 #include <linux/kernel.h> 13 #include <linux/kmemleak.h> 14 #include <linux/module.h> 15 #include <linux/netdevice.h> 16 #include <linux/net_tstamp.h> 17 #include <linux/of.h> 18 #include <linux/of_mdio.h> 19 #include <linux/of_net.h> 20 #include <linux/of_device.h> 21 #include <linux/phylink.h> 22 #include <linux/phy/phy.h> 23 #include <linux/platform_device.h> 24 #include <linux/pm_runtime.h> 25 #include <linux/regmap.h> 26 #include <linux/mfd/syscon.h> 27 #include <linux/sys_soc.h> 28 #include <linux/dma/ti-cppi5.h> 29 #include <linux/dma/k3-udma-glue.h> 30 #include <net/switchdev.h> 31 32 #include "cpsw_ale.h" 33 #include "cpsw_sl.h" 34 #include "am65-cpsw-nuss.h" 35 #include "am65-cpsw-switchdev.h" 36 #include "k3-cppi-desc-pool.h" 37 #include "am65-cpts.h" 38 39 #define AM65_CPSW_SS_BASE 0x0 40 #define AM65_CPSW_SGMII_BASE 0x100 41 #define AM65_CPSW_XGMII_BASE 0x2100 42 #define AM65_CPSW_CPSW_NU_BASE 0x20000 43 #define AM65_CPSW_NU_PORTS_BASE 0x1000 44 #define AM65_CPSW_NU_FRAM_BASE 0x12000 45 #define AM65_CPSW_NU_STATS_BASE 0x1a000 46 #define AM65_CPSW_NU_ALE_BASE 0x1e000 47 #define AM65_CPSW_NU_CPTS_BASE 0x1d000 48 49 #define AM65_CPSW_NU_PORTS_OFFSET 0x1000 50 #define AM65_CPSW_NU_STATS_PORT_OFFSET 0x200 51 #define AM65_CPSW_NU_FRAM_PORT_OFFSET 0x200 52 53 #define AM65_CPSW_MAX_PORTS 8 54 55 #define AM65_CPSW_MIN_PACKET_SIZE VLAN_ETH_ZLEN 56 #define AM65_CPSW_MAX_PACKET_SIZE (VLAN_ETH_FRAME_LEN + ETH_FCS_LEN) 57 58 #define AM65_CPSW_REG_CTL 0x004 59 #define AM65_CPSW_REG_STAT_PORT_EN 0x014 60 #define AM65_CPSW_REG_PTYPE 0x018 61 62 #define AM65_CPSW_P0_REG_CTL 0x004 63 #define AM65_CPSW_PORT0_REG_FLOW_ID_OFFSET 0x008 64 65 #define AM65_CPSW_PORT_REG_PRI_CTL 0x01c 66 #define AM65_CPSW_PORT_REG_RX_PRI_MAP 0x020 67 #define AM65_CPSW_PORT_REG_RX_MAXLEN 0x024 68 69 #define AM65_CPSW_PORTN_REG_SA_L 0x308 70 #define AM65_CPSW_PORTN_REG_SA_H 0x30c 71 #define AM65_CPSW_PORTN_REG_TS_CTL 0x310 72 #define AM65_CPSW_PORTN_REG_TS_SEQ_LTYPE_REG 0x314 73 #define AM65_CPSW_PORTN_REG_TS_VLAN_LTYPE_REG 0x318 74 #define AM65_CPSW_PORTN_REG_TS_CTL_LTYPE2 0x31C 75 76 #define AM65_CPSW_CTL_VLAN_AWARE BIT(1) 77 #define AM65_CPSW_CTL_P0_ENABLE BIT(2) 78 #define AM65_CPSW_CTL_P0_TX_CRC_REMOVE BIT(13) 79 #define AM65_CPSW_CTL_P0_RX_PAD BIT(14) 80 81 /* AM65_CPSW_P0_REG_CTL */ 82 #define AM65_CPSW_P0_REG_CTL_RX_CHECKSUM_EN BIT(0) 83 84 /* AM65_CPSW_PORT_REG_PRI_CTL */ 85 #define AM65_CPSW_PORT_REG_PRI_CTL_RX_PTYPE_RROBIN BIT(8) 86 87 /* AM65_CPSW_PN_TS_CTL register fields */ 88 #define AM65_CPSW_PN_TS_CTL_TX_ANX_F_EN BIT(4) 89 #define AM65_CPSW_PN_TS_CTL_TX_VLAN_LT1_EN BIT(5) 90 #define AM65_CPSW_PN_TS_CTL_TX_VLAN_LT2_EN BIT(6) 91 #define AM65_CPSW_PN_TS_CTL_TX_ANX_D_EN BIT(7) 92 #define AM65_CPSW_PN_TS_CTL_TX_ANX_E_EN BIT(10) 93 #define AM65_CPSW_PN_TS_CTL_TX_HOST_TS_EN BIT(11) 94 #define AM65_CPSW_PN_TS_CTL_MSG_TYPE_EN_SHIFT 16 95 96 /* AM65_CPSW_PORTN_REG_TS_SEQ_LTYPE_REG register fields */ 97 #define AM65_CPSW_PN_TS_SEQ_ID_OFFSET_SHIFT 16 98 99 /* AM65_CPSW_PORTN_REG_TS_CTL_LTYPE2 */ 100 #define AM65_CPSW_PN_TS_CTL_LTYPE2_TS_107 BIT(16) 101 #define AM65_CPSW_PN_TS_CTL_LTYPE2_TS_129 BIT(17) 102 #define AM65_CPSW_PN_TS_CTL_LTYPE2_TS_130 BIT(18) 103 #define AM65_CPSW_PN_TS_CTL_LTYPE2_TS_131 BIT(19) 104 #define AM65_CPSW_PN_TS_CTL_LTYPE2_TS_132 BIT(20) 105 #define AM65_CPSW_PN_TS_CTL_LTYPE2_TS_319 BIT(21) 106 #define AM65_CPSW_PN_TS_CTL_LTYPE2_TS_320 BIT(22) 107 #define AM65_CPSW_PN_TS_CTL_LTYPE2_TS_TTL_NONZERO BIT(23) 108 109 /* The PTP event messages - Sync, Delay_Req, Pdelay_Req, and Pdelay_Resp. */ 110 #define AM65_CPSW_TS_EVENT_MSG_TYPE_BITS (BIT(0) | BIT(1) | BIT(2) | BIT(3)) 111 112 #define AM65_CPSW_TS_SEQ_ID_OFFSET (0x1e) 113 114 #define AM65_CPSW_TS_TX_ANX_ALL_EN \ 115 (AM65_CPSW_PN_TS_CTL_TX_ANX_D_EN | \ 116 AM65_CPSW_PN_TS_CTL_TX_ANX_E_EN | \ 117 AM65_CPSW_PN_TS_CTL_TX_ANX_F_EN) 118 119 #define AM65_CPSW_ALE_AGEOUT_DEFAULT 30 120 /* Number of TX/RX descriptors */ 121 #define AM65_CPSW_MAX_TX_DESC 500 122 #define AM65_CPSW_MAX_RX_DESC 500 123 124 #define AM65_CPSW_NAV_PS_DATA_SIZE 16 125 #define AM65_CPSW_NAV_SW_DATA_SIZE 16 126 127 #define AM65_CPSW_DEBUG (NETIF_MSG_HW | NETIF_MSG_DRV | NETIF_MSG_LINK | \ 128 NETIF_MSG_IFUP | NETIF_MSG_PROBE | NETIF_MSG_IFDOWN | \ 129 NETIF_MSG_RX_ERR | NETIF_MSG_TX_ERR) 130 131 static void am65_cpsw_port_set_sl_mac(struct am65_cpsw_port *slave, 132 const u8 *dev_addr) 133 { 134 u32 mac_hi = (dev_addr[0] << 0) | (dev_addr[1] << 8) | 135 (dev_addr[2] << 16) | (dev_addr[3] << 24); 136 u32 mac_lo = (dev_addr[4] << 0) | (dev_addr[5] << 8); 137 138 writel(mac_hi, slave->port_base + AM65_CPSW_PORTN_REG_SA_H); 139 writel(mac_lo, slave->port_base + AM65_CPSW_PORTN_REG_SA_L); 140 } 141 142 static void am65_cpsw_sl_ctl_reset(struct am65_cpsw_port *port) 143 { 144 cpsw_sl_reset(port->slave.mac_sl, 100); 145 /* Max length register has to be restored after MAC SL reset */ 146 writel(AM65_CPSW_MAX_PACKET_SIZE, 147 port->port_base + AM65_CPSW_PORT_REG_RX_MAXLEN); 148 } 149 150 static void am65_cpsw_nuss_get_ver(struct am65_cpsw_common *common) 151 { 152 common->nuss_ver = readl(common->ss_base); 153 common->cpsw_ver = readl(common->cpsw_base); 154 dev_info(common->dev, 155 "initializing am65 cpsw nuss version 0x%08X, cpsw version 0x%08X Ports: %u quirks:%08x\n", 156 common->nuss_ver, 157 common->cpsw_ver, 158 common->port_num + 1, 159 common->pdata.quirks); 160 } 161 162 static int am65_cpsw_nuss_ndo_slave_add_vid(struct net_device *ndev, 163 __be16 proto, u16 vid) 164 { 165 struct am65_cpsw_common *common = am65_ndev_to_common(ndev); 166 struct am65_cpsw_port *port = am65_ndev_to_port(ndev); 167 u32 port_mask, unreg_mcast = 0; 168 int ret; 169 170 if (!common->is_emac_mode) 171 return 0; 172 173 if (!netif_running(ndev) || !vid) 174 return 0; 175 176 ret = pm_runtime_get_sync(common->dev); 177 if (ret < 0) { 178 pm_runtime_put_noidle(common->dev); 179 return ret; 180 } 181 182 port_mask = BIT(port->port_id) | ALE_PORT_HOST; 183 if (!vid) 184 unreg_mcast = port_mask; 185 dev_info(common->dev, "Adding vlan %d to vlan filter\n", vid); 186 ret = cpsw_ale_vlan_add_modify(common->ale, vid, port_mask, 187 unreg_mcast, port_mask, 0); 188 189 pm_runtime_put(common->dev); 190 return ret; 191 } 192 193 static int am65_cpsw_nuss_ndo_slave_kill_vid(struct net_device *ndev, 194 __be16 proto, u16 vid) 195 { 196 struct am65_cpsw_common *common = am65_ndev_to_common(ndev); 197 struct am65_cpsw_port *port = am65_ndev_to_port(ndev); 198 int ret; 199 200 if (!common->is_emac_mode) 201 return 0; 202 203 if (!netif_running(ndev) || !vid) 204 return 0; 205 206 ret = pm_runtime_get_sync(common->dev); 207 if (ret < 0) { 208 pm_runtime_put_noidle(common->dev); 209 return ret; 210 } 211 212 dev_info(common->dev, "Removing vlan %d from vlan filter\n", vid); 213 ret = cpsw_ale_del_vlan(common->ale, vid, 214 BIT(port->port_id) | ALE_PORT_HOST); 215 216 pm_runtime_put(common->dev); 217 return ret; 218 } 219 220 static void am65_cpsw_slave_set_promisc(struct am65_cpsw_port *port, 221 bool promisc) 222 { 223 struct am65_cpsw_common *common = port->common; 224 225 if (promisc && !common->is_emac_mode) { 226 dev_dbg(common->dev, "promisc mode requested in switch mode"); 227 return; 228 } 229 230 if (promisc) { 231 /* Enable promiscuous mode */ 232 cpsw_ale_control_set(common->ale, port->port_id, 233 ALE_PORT_MACONLY_CAF, 1); 234 dev_dbg(common->dev, "promisc enabled\n"); 235 } else { 236 /* Disable promiscuous mode */ 237 cpsw_ale_control_set(common->ale, port->port_id, 238 ALE_PORT_MACONLY_CAF, 0); 239 dev_dbg(common->dev, "promisc disabled\n"); 240 } 241 } 242 243 static void am65_cpsw_nuss_ndo_slave_set_rx_mode(struct net_device *ndev) 244 { 245 struct am65_cpsw_common *common = am65_ndev_to_common(ndev); 246 struct am65_cpsw_port *port = am65_ndev_to_port(ndev); 247 u32 port_mask; 248 bool promisc; 249 250 promisc = !!(ndev->flags & IFF_PROMISC); 251 am65_cpsw_slave_set_promisc(port, promisc); 252 253 if (promisc) 254 return; 255 256 /* Restore allmulti on vlans if necessary */ 257 cpsw_ale_set_allmulti(common->ale, 258 ndev->flags & IFF_ALLMULTI, port->port_id); 259 260 port_mask = ALE_PORT_HOST; 261 /* Clear all mcast from ALE */ 262 cpsw_ale_flush_multicast(common->ale, port_mask, -1); 263 264 if (!netdev_mc_empty(ndev)) { 265 struct netdev_hw_addr *ha; 266 267 /* program multicast address list into ALE register */ 268 netdev_for_each_mc_addr(ha, ndev) { 269 cpsw_ale_add_mcast(common->ale, ha->addr, 270 port_mask, 0, 0, 0); 271 } 272 } 273 } 274 275 static void am65_cpsw_nuss_ndo_host_tx_timeout(struct net_device *ndev, 276 unsigned int txqueue) 277 { 278 struct am65_cpsw_common *common = am65_ndev_to_common(ndev); 279 struct am65_cpsw_tx_chn *tx_chn; 280 struct netdev_queue *netif_txq; 281 unsigned long trans_start; 282 283 netif_txq = netdev_get_tx_queue(ndev, txqueue); 284 tx_chn = &common->tx_chns[txqueue]; 285 trans_start = READ_ONCE(netif_txq->trans_start); 286 287 netdev_err(ndev, "txq:%d DRV_XOFF:%d tmo:%u dql_avail:%d free_desc:%zu\n", 288 txqueue, 289 netif_tx_queue_stopped(netif_txq), 290 jiffies_to_msecs(jiffies - trans_start), 291 dql_avail(&netif_txq->dql), 292 k3_cppi_desc_pool_avail(tx_chn->desc_pool)); 293 294 if (netif_tx_queue_stopped(netif_txq)) { 295 /* try recover if stopped by us */ 296 txq_trans_update(netif_txq); 297 netif_tx_wake_queue(netif_txq); 298 } 299 } 300 301 static int am65_cpsw_nuss_rx_push(struct am65_cpsw_common *common, 302 struct sk_buff *skb) 303 { 304 struct am65_cpsw_rx_chn *rx_chn = &common->rx_chns; 305 struct cppi5_host_desc_t *desc_rx; 306 struct device *dev = common->dev; 307 u32 pkt_len = skb_tailroom(skb); 308 dma_addr_t desc_dma; 309 dma_addr_t buf_dma; 310 void *swdata; 311 312 desc_rx = k3_cppi_desc_pool_alloc(rx_chn->desc_pool); 313 if (!desc_rx) { 314 dev_err(dev, "Failed to allocate RXFDQ descriptor\n"); 315 return -ENOMEM; 316 } 317 desc_dma = k3_cppi_desc_pool_virt2dma(rx_chn->desc_pool, desc_rx); 318 319 buf_dma = dma_map_single(rx_chn->dma_dev, skb->data, pkt_len, 320 DMA_FROM_DEVICE); 321 if (unlikely(dma_mapping_error(rx_chn->dma_dev, buf_dma))) { 322 k3_cppi_desc_pool_free(rx_chn->desc_pool, desc_rx); 323 dev_err(dev, "Failed to map rx skb buffer\n"); 324 return -EINVAL; 325 } 326 327 cppi5_hdesc_init(desc_rx, CPPI5_INFO0_HDESC_EPIB_PRESENT, 328 AM65_CPSW_NAV_PS_DATA_SIZE); 329 k3_udma_glue_rx_dma_to_cppi5_addr(rx_chn->rx_chn, &buf_dma); 330 cppi5_hdesc_attach_buf(desc_rx, buf_dma, skb_tailroom(skb), buf_dma, skb_tailroom(skb)); 331 swdata = cppi5_hdesc_get_swdata(desc_rx); 332 *((void **)swdata) = skb; 333 334 return k3_udma_glue_push_rx_chn(rx_chn->rx_chn, 0, desc_rx, desc_dma); 335 } 336 337 void am65_cpsw_nuss_set_p0_ptype(struct am65_cpsw_common *common) 338 { 339 struct am65_cpsw_host *host_p = am65_common_get_host(common); 340 u32 val, pri_map; 341 342 /* P0 set Receive Priority Type */ 343 val = readl(host_p->port_base + AM65_CPSW_PORT_REG_PRI_CTL); 344 345 if (common->pf_p0_rx_ptype_rrobin) { 346 val |= AM65_CPSW_PORT_REG_PRI_CTL_RX_PTYPE_RROBIN; 347 /* Enet Ports fifos works in fixed priority mode only, so 348 * reset P0_Rx_Pri_Map so all packet will go in Enet fifo 0 349 */ 350 pri_map = 0x0; 351 } else { 352 val &= ~AM65_CPSW_PORT_REG_PRI_CTL_RX_PTYPE_RROBIN; 353 /* restore P0_Rx_Pri_Map */ 354 pri_map = 0x76543210; 355 } 356 357 writel(pri_map, host_p->port_base + AM65_CPSW_PORT_REG_RX_PRI_MAP); 358 writel(val, host_p->port_base + AM65_CPSW_PORT_REG_PRI_CTL); 359 } 360 361 static void am65_cpsw_init_host_port_switch(struct am65_cpsw_common *common); 362 static void am65_cpsw_init_host_port_emac(struct am65_cpsw_common *common); 363 static void am65_cpsw_init_port_switch_ale(struct am65_cpsw_port *port); 364 static void am65_cpsw_init_port_emac_ale(struct am65_cpsw_port *port); 365 366 static int am65_cpsw_nuss_common_open(struct am65_cpsw_common *common, 367 netdev_features_t features) 368 { 369 struct am65_cpsw_host *host_p = am65_common_get_host(common); 370 int port_idx, i, ret; 371 struct sk_buff *skb; 372 u32 val, port_mask; 373 374 if (common->usage_count) 375 return 0; 376 377 /* Control register */ 378 writel(AM65_CPSW_CTL_P0_ENABLE | AM65_CPSW_CTL_P0_TX_CRC_REMOVE | 379 AM65_CPSW_CTL_VLAN_AWARE | AM65_CPSW_CTL_P0_RX_PAD, 380 common->cpsw_base + AM65_CPSW_REG_CTL); 381 /* Max length register */ 382 writel(AM65_CPSW_MAX_PACKET_SIZE, 383 host_p->port_base + AM65_CPSW_PORT_REG_RX_MAXLEN); 384 /* set base flow_id */ 385 writel(common->rx_flow_id_base, 386 host_p->port_base + AM65_CPSW_PORT0_REG_FLOW_ID_OFFSET); 387 /* en tx crc offload */ 388 writel(AM65_CPSW_P0_REG_CTL_RX_CHECKSUM_EN, host_p->port_base + AM65_CPSW_P0_REG_CTL); 389 390 am65_cpsw_nuss_set_p0_ptype(common); 391 392 /* enable statistic */ 393 val = BIT(HOST_PORT_NUM); 394 for (port_idx = 0; port_idx < common->port_num; port_idx++) { 395 struct am65_cpsw_port *port = &common->ports[port_idx]; 396 397 if (!port->disabled) 398 val |= BIT(port->port_id); 399 } 400 writel(val, common->cpsw_base + AM65_CPSW_REG_STAT_PORT_EN); 401 402 /* disable priority elevation */ 403 writel(0, common->cpsw_base + AM65_CPSW_REG_PTYPE); 404 405 cpsw_ale_start(common->ale); 406 407 /* limit to one RX flow only */ 408 cpsw_ale_control_set(common->ale, HOST_PORT_NUM, 409 ALE_DEFAULT_THREAD_ID, 0); 410 cpsw_ale_control_set(common->ale, HOST_PORT_NUM, 411 ALE_DEFAULT_THREAD_ENABLE, 1); 412 /* switch to vlan unaware mode */ 413 cpsw_ale_control_set(common->ale, HOST_PORT_NUM, ALE_VLAN_AWARE, 1); 414 cpsw_ale_control_set(common->ale, HOST_PORT_NUM, 415 ALE_PORT_STATE, ALE_PORT_STATE_FORWARD); 416 417 /* default vlan cfg: create mask based on enabled ports */ 418 port_mask = GENMASK(common->port_num, 0) & 419 ~common->disabled_ports_mask; 420 421 cpsw_ale_add_vlan(common->ale, 0, port_mask, 422 port_mask, port_mask, 423 port_mask & ~ALE_PORT_HOST); 424 425 if (common->is_emac_mode) 426 am65_cpsw_init_host_port_emac(common); 427 else 428 am65_cpsw_init_host_port_switch(common); 429 430 for (i = 0; i < common->rx_chns.descs_num; i++) { 431 skb = __netdev_alloc_skb_ip_align(NULL, 432 AM65_CPSW_MAX_PACKET_SIZE, 433 GFP_KERNEL); 434 if (!skb) { 435 dev_err(common->dev, "cannot allocate skb\n"); 436 return -ENOMEM; 437 } 438 439 ret = am65_cpsw_nuss_rx_push(common, skb); 440 if (ret < 0) { 441 dev_err(common->dev, 442 "cannot submit skb to channel rx, error %d\n", 443 ret); 444 kfree_skb(skb); 445 return ret; 446 } 447 kmemleak_not_leak(skb); 448 } 449 k3_udma_glue_enable_rx_chn(common->rx_chns.rx_chn); 450 451 for (i = 0; i < common->tx_ch_num; i++) { 452 ret = k3_udma_glue_enable_tx_chn(common->tx_chns[i].tx_chn); 453 if (ret) 454 return ret; 455 napi_enable(&common->tx_chns[i].napi_tx); 456 } 457 458 napi_enable(&common->napi_rx); 459 if (common->rx_irq_disabled) { 460 common->rx_irq_disabled = false; 461 enable_irq(common->rx_chns.irq); 462 } 463 464 dev_dbg(common->dev, "cpsw_nuss started\n"); 465 return 0; 466 } 467 468 static void am65_cpsw_nuss_tx_cleanup(void *data, dma_addr_t desc_dma); 469 static void am65_cpsw_nuss_rx_cleanup(void *data, dma_addr_t desc_dma); 470 471 static int am65_cpsw_nuss_common_stop(struct am65_cpsw_common *common) 472 { 473 int i; 474 475 if (common->usage_count != 1) 476 return 0; 477 478 cpsw_ale_control_set(common->ale, HOST_PORT_NUM, 479 ALE_PORT_STATE, ALE_PORT_STATE_DISABLE); 480 481 /* shutdown tx channels */ 482 atomic_set(&common->tdown_cnt, common->tx_ch_num); 483 /* ensure new tdown_cnt value is visible */ 484 smp_mb__after_atomic(); 485 reinit_completion(&common->tdown_complete); 486 487 for (i = 0; i < common->tx_ch_num; i++) 488 k3_udma_glue_tdown_tx_chn(common->tx_chns[i].tx_chn, false); 489 490 i = wait_for_completion_timeout(&common->tdown_complete, 491 msecs_to_jiffies(1000)); 492 if (!i) 493 dev_err(common->dev, "tx timeout\n"); 494 for (i = 0; i < common->tx_ch_num; i++) 495 napi_disable(&common->tx_chns[i].napi_tx); 496 497 for (i = 0; i < common->tx_ch_num; i++) { 498 k3_udma_glue_reset_tx_chn(common->tx_chns[i].tx_chn, 499 &common->tx_chns[i], 500 am65_cpsw_nuss_tx_cleanup); 501 k3_udma_glue_disable_tx_chn(common->tx_chns[i].tx_chn); 502 } 503 504 k3_udma_glue_tdown_rx_chn(common->rx_chns.rx_chn, true); 505 napi_disable(&common->napi_rx); 506 507 for (i = 0; i < AM65_CPSW_MAX_RX_FLOWS; i++) 508 k3_udma_glue_reset_rx_chn(common->rx_chns.rx_chn, i, 509 &common->rx_chns, 510 am65_cpsw_nuss_rx_cleanup, !!i); 511 512 k3_udma_glue_disable_rx_chn(common->rx_chns.rx_chn); 513 514 cpsw_ale_stop(common->ale); 515 516 writel(0, common->cpsw_base + AM65_CPSW_REG_CTL); 517 writel(0, common->cpsw_base + AM65_CPSW_REG_STAT_PORT_EN); 518 519 dev_dbg(common->dev, "cpsw_nuss stopped\n"); 520 return 0; 521 } 522 523 static int am65_cpsw_nuss_ndo_slave_stop(struct net_device *ndev) 524 { 525 struct am65_cpsw_common *common = am65_ndev_to_common(ndev); 526 struct am65_cpsw_port *port = am65_ndev_to_port(ndev); 527 int ret; 528 529 phylink_stop(port->slave.phylink); 530 531 netif_tx_stop_all_queues(ndev); 532 533 phylink_disconnect_phy(port->slave.phylink); 534 535 ret = am65_cpsw_nuss_common_stop(common); 536 if (ret) 537 return ret; 538 539 common->usage_count--; 540 pm_runtime_put(common->dev); 541 return 0; 542 } 543 544 static int cpsw_restore_vlans(struct net_device *vdev, int vid, void *arg) 545 { 546 struct am65_cpsw_port *port = arg; 547 548 if (!vdev) 549 return 0; 550 551 return am65_cpsw_nuss_ndo_slave_add_vid(port->ndev, 0, vid); 552 } 553 554 static int am65_cpsw_nuss_ndo_slave_open(struct net_device *ndev) 555 { 556 struct am65_cpsw_common *common = am65_ndev_to_common(ndev); 557 struct am65_cpsw_port *port = am65_ndev_to_port(ndev); 558 int ret, i; 559 560 ret = pm_runtime_get_sync(common->dev); 561 if (ret < 0) { 562 pm_runtime_put_noidle(common->dev); 563 return ret; 564 } 565 566 /* Notify the stack of the actual queue counts. */ 567 ret = netif_set_real_num_tx_queues(ndev, common->tx_ch_num); 568 if (ret) { 569 dev_err(common->dev, "cannot set real number of tx queues\n"); 570 return ret; 571 } 572 573 ret = netif_set_real_num_rx_queues(ndev, AM65_CPSW_MAX_RX_QUEUES); 574 if (ret) { 575 dev_err(common->dev, "cannot set real number of rx queues\n"); 576 return ret; 577 } 578 579 for (i = 0; i < common->tx_ch_num; i++) 580 netdev_tx_reset_queue(netdev_get_tx_queue(ndev, i)); 581 582 ret = am65_cpsw_nuss_common_open(common, ndev->features); 583 if (ret) 584 return ret; 585 586 common->usage_count++; 587 588 am65_cpsw_port_set_sl_mac(port, ndev->dev_addr); 589 590 if (common->is_emac_mode) 591 am65_cpsw_init_port_emac_ale(port); 592 else 593 am65_cpsw_init_port_switch_ale(port); 594 595 /* mac_sl should be configured via phy-link interface */ 596 am65_cpsw_sl_ctl_reset(port); 597 598 ret = phy_set_mode_ext(port->slave.ifphy, PHY_MODE_ETHERNET, 599 port->slave.phy_if); 600 if (ret) 601 goto error_cleanup; 602 603 ret = phylink_of_phy_connect(port->slave.phylink, port->slave.phy_node, 0); 604 if (ret) 605 goto error_cleanup; 606 607 /* restore vlan configurations */ 608 vlan_for_each(ndev, cpsw_restore_vlans, port); 609 610 phylink_start(port->slave.phylink); 611 612 return 0; 613 614 error_cleanup: 615 am65_cpsw_nuss_ndo_slave_stop(ndev); 616 return ret; 617 } 618 619 static void am65_cpsw_nuss_rx_cleanup(void *data, dma_addr_t desc_dma) 620 { 621 struct am65_cpsw_rx_chn *rx_chn = data; 622 struct cppi5_host_desc_t *desc_rx; 623 struct sk_buff *skb; 624 dma_addr_t buf_dma; 625 u32 buf_dma_len; 626 void **swdata; 627 628 desc_rx = k3_cppi_desc_pool_dma2virt(rx_chn->desc_pool, desc_dma); 629 swdata = cppi5_hdesc_get_swdata(desc_rx); 630 skb = *swdata; 631 cppi5_hdesc_get_obuf(desc_rx, &buf_dma, &buf_dma_len); 632 k3_udma_glue_rx_cppi5_to_dma_addr(rx_chn->rx_chn, &buf_dma); 633 634 dma_unmap_single(rx_chn->dma_dev, buf_dma, buf_dma_len, DMA_FROM_DEVICE); 635 k3_cppi_desc_pool_free(rx_chn->desc_pool, desc_rx); 636 637 dev_kfree_skb_any(skb); 638 } 639 640 static void am65_cpsw_nuss_rx_ts(struct sk_buff *skb, u32 *psdata) 641 { 642 struct skb_shared_hwtstamps *ssh; 643 u64 ns; 644 645 ns = ((u64)psdata[1] << 32) | psdata[0]; 646 647 ssh = skb_hwtstamps(skb); 648 memset(ssh, 0, sizeof(*ssh)); 649 ssh->hwtstamp = ns_to_ktime(ns); 650 } 651 652 /* RX psdata[2] word format - checksum information */ 653 #define AM65_CPSW_RX_PSD_CSUM_ADD GENMASK(15, 0) 654 #define AM65_CPSW_RX_PSD_CSUM_ERR BIT(16) 655 #define AM65_CPSW_RX_PSD_IS_FRAGMENT BIT(17) 656 #define AM65_CPSW_RX_PSD_IS_TCP BIT(18) 657 #define AM65_CPSW_RX_PSD_IPV6_VALID BIT(19) 658 #define AM65_CPSW_RX_PSD_IPV4_VALID BIT(20) 659 660 static void am65_cpsw_nuss_rx_csum(struct sk_buff *skb, u32 csum_info) 661 { 662 /* HW can verify IPv4/IPv6 TCP/UDP packets checksum 663 * csum information provides in psdata[2] word: 664 * AM65_CPSW_RX_PSD_CSUM_ERR bit - indicates csum error 665 * AM65_CPSW_RX_PSD_IPV6_VALID and AM65_CPSW_RX_PSD_IPV4_VALID 666 * bits - indicates IPv4/IPv6 packet 667 * AM65_CPSW_RX_PSD_IS_FRAGMENT bit - indicates fragmented packet 668 * AM65_CPSW_RX_PSD_CSUM_ADD has value 0xFFFF for non fragmented packets 669 * or csum value for fragmented packets if !AM65_CPSW_RX_PSD_CSUM_ERR 670 */ 671 skb_checksum_none_assert(skb); 672 673 if (unlikely(!(skb->dev->features & NETIF_F_RXCSUM))) 674 return; 675 676 if ((csum_info & (AM65_CPSW_RX_PSD_IPV6_VALID | 677 AM65_CPSW_RX_PSD_IPV4_VALID)) && 678 !(csum_info & AM65_CPSW_RX_PSD_CSUM_ERR)) { 679 /* csum for fragmented packets is unsupported */ 680 if (!(csum_info & AM65_CPSW_RX_PSD_IS_FRAGMENT)) 681 skb->ip_summed = CHECKSUM_UNNECESSARY; 682 } 683 } 684 685 static int am65_cpsw_nuss_rx_packets(struct am65_cpsw_common *common, 686 u32 flow_idx) 687 { 688 struct am65_cpsw_rx_chn *rx_chn = &common->rx_chns; 689 u32 buf_dma_len, pkt_len, port_id = 0, csum_info; 690 struct am65_cpsw_ndev_priv *ndev_priv; 691 struct am65_cpsw_ndev_stats *stats; 692 struct cppi5_host_desc_t *desc_rx; 693 struct device *dev = common->dev; 694 struct sk_buff *skb, *new_skb; 695 dma_addr_t desc_dma, buf_dma; 696 struct am65_cpsw_port *port; 697 struct net_device *ndev; 698 void **swdata; 699 u32 *psdata; 700 int ret = 0; 701 702 ret = k3_udma_glue_pop_rx_chn(rx_chn->rx_chn, flow_idx, &desc_dma); 703 if (ret) { 704 if (ret != -ENODATA) 705 dev_err(dev, "RX: pop chn fail %d\n", ret); 706 return ret; 707 } 708 709 if (cppi5_desc_is_tdcm(desc_dma)) { 710 dev_dbg(dev, "%s RX tdown flow: %u\n", __func__, flow_idx); 711 return 0; 712 } 713 714 desc_rx = k3_cppi_desc_pool_dma2virt(rx_chn->desc_pool, desc_dma); 715 dev_dbg(dev, "%s flow_idx: %u desc %pad\n", 716 __func__, flow_idx, &desc_dma); 717 718 swdata = cppi5_hdesc_get_swdata(desc_rx); 719 skb = *swdata; 720 cppi5_hdesc_get_obuf(desc_rx, &buf_dma, &buf_dma_len); 721 k3_udma_glue_rx_cppi5_to_dma_addr(rx_chn->rx_chn, &buf_dma); 722 pkt_len = cppi5_hdesc_get_pktlen(desc_rx); 723 cppi5_desc_get_tags_ids(&desc_rx->hdr, &port_id, NULL); 724 dev_dbg(dev, "%s rx port_id:%d\n", __func__, port_id); 725 port = am65_common_get_port(common, port_id); 726 ndev = port->ndev; 727 skb->dev = ndev; 728 729 psdata = cppi5_hdesc_get_psdata(desc_rx); 730 /* add RX timestamp */ 731 if (port->rx_ts_enabled) 732 am65_cpsw_nuss_rx_ts(skb, psdata); 733 csum_info = psdata[2]; 734 dev_dbg(dev, "%s rx csum_info:%#x\n", __func__, csum_info); 735 736 dma_unmap_single(rx_chn->dma_dev, buf_dma, buf_dma_len, DMA_FROM_DEVICE); 737 738 k3_cppi_desc_pool_free(rx_chn->desc_pool, desc_rx); 739 740 new_skb = netdev_alloc_skb_ip_align(ndev, AM65_CPSW_MAX_PACKET_SIZE); 741 if (new_skb) { 742 ndev_priv = netdev_priv(ndev); 743 am65_cpsw_nuss_set_offload_fwd_mark(skb, ndev_priv->offload_fwd_mark); 744 skb_put(skb, pkt_len); 745 skb->protocol = eth_type_trans(skb, ndev); 746 am65_cpsw_nuss_rx_csum(skb, csum_info); 747 napi_gro_receive(&common->napi_rx, skb); 748 749 stats = this_cpu_ptr(ndev_priv->stats); 750 751 u64_stats_update_begin(&stats->syncp); 752 stats->rx_packets++; 753 stats->rx_bytes += pkt_len; 754 u64_stats_update_end(&stats->syncp); 755 kmemleak_not_leak(new_skb); 756 } else { 757 ndev->stats.rx_dropped++; 758 new_skb = skb; 759 } 760 761 if (netif_dormant(ndev)) { 762 dev_kfree_skb_any(new_skb); 763 ndev->stats.rx_dropped++; 764 return 0; 765 } 766 767 ret = am65_cpsw_nuss_rx_push(common, new_skb); 768 if (WARN_ON(ret < 0)) { 769 dev_kfree_skb_any(new_skb); 770 ndev->stats.rx_errors++; 771 ndev->stats.rx_dropped++; 772 } 773 774 return ret; 775 } 776 777 static int am65_cpsw_nuss_rx_poll(struct napi_struct *napi_rx, int budget) 778 { 779 struct am65_cpsw_common *common = am65_cpsw_napi_to_common(napi_rx); 780 int flow = AM65_CPSW_MAX_RX_FLOWS; 781 int cur_budget, ret; 782 int num_rx = 0; 783 784 /* process every flow */ 785 while (flow--) { 786 cur_budget = budget - num_rx; 787 788 while (cur_budget--) { 789 ret = am65_cpsw_nuss_rx_packets(common, flow); 790 if (ret) 791 break; 792 num_rx++; 793 } 794 795 if (num_rx >= budget) 796 break; 797 } 798 799 dev_dbg(common->dev, "%s num_rx:%d %d\n", __func__, num_rx, budget); 800 801 if (num_rx < budget && napi_complete_done(napi_rx, num_rx)) { 802 if (common->rx_irq_disabled) { 803 common->rx_irq_disabled = false; 804 enable_irq(common->rx_chns.irq); 805 } 806 } 807 808 return num_rx; 809 } 810 811 static void am65_cpsw_nuss_xmit_free(struct am65_cpsw_tx_chn *tx_chn, 812 struct cppi5_host_desc_t *desc) 813 { 814 struct cppi5_host_desc_t *first_desc, *next_desc; 815 dma_addr_t buf_dma, next_desc_dma; 816 u32 buf_dma_len; 817 818 first_desc = desc; 819 next_desc = first_desc; 820 821 cppi5_hdesc_get_obuf(first_desc, &buf_dma, &buf_dma_len); 822 k3_udma_glue_tx_cppi5_to_dma_addr(tx_chn->tx_chn, &buf_dma); 823 824 dma_unmap_single(tx_chn->dma_dev, buf_dma, buf_dma_len, DMA_TO_DEVICE); 825 826 next_desc_dma = cppi5_hdesc_get_next_hbdesc(first_desc); 827 k3_udma_glue_tx_cppi5_to_dma_addr(tx_chn->tx_chn, &next_desc_dma); 828 while (next_desc_dma) { 829 next_desc = k3_cppi_desc_pool_dma2virt(tx_chn->desc_pool, 830 next_desc_dma); 831 cppi5_hdesc_get_obuf(next_desc, &buf_dma, &buf_dma_len); 832 k3_udma_glue_tx_cppi5_to_dma_addr(tx_chn->tx_chn, &buf_dma); 833 834 dma_unmap_page(tx_chn->dma_dev, buf_dma, buf_dma_len, 835 DMA_TO_DEVICE); 836 837 next_desc_dma = cppi5_hdesc_get_next_hbdesc(next_desc); 838 k3_udma_glue_tx_cppi5_to_dma_addr(tx_chn->tx_chn, &next_desc_dma); 839 840 k3_cppi_desc_pool_free(tx_chn->desc_pool, next_desc); 841 } 842 843 k3_cppi_desc_pool_free(tx_chn->desc_pool, first_desc); 844 } 845 846 static void am65_cpsw_nuss_tx_cleanup(void *data, dma_addr_t desc_dma) 847 { 848 struct am65_cpsw_tx_chn *tx_chn = data; 849 struct cppi5_host_desc_t *desc_tx; 850 struct sk_buff *skb; 851 void **swdata; 852 853 desc_tx = k3_cppi_desc_pool_dma2virt(tx_chn->desc_pool, desc_dma); 854 swdata = cppi5_hdesc_get_swdata(desc_tx); 855 skb = *(swdata); 856 am65_cpsw_nuss_xmit_free(tx_chn, desc_tx); 857 858 dev_kfree_skb_any(skb); 859 } 860 861 static struct sk_buff * 862 am65_cpsw_nuss_tx_compl_packet(struct am65_cpsw_tx_chn *tx_chn, 863 dma_addr_t desc_dma) 864 { 865 struct am65_cpsw_ndev_priv *ndev_priv; 866 struct am65_cpsw_ndev_stats *stats; 867 struct cppi5_host_desc_t *desc_tx; 868 struct net_device *ndev; 869 struct sk_buff *skb; 870 void **swdata; 871 872 desc_tx = k3_cppi_desc_pool_dma2virt(tx_chn->desc_pool, 873 desc_dma); 874 swdata = cppi5_hdesc_get_swdata(desc_tx); 875 skb = *(swdata); 876 am65_cpsw_nuss_xmit_free(tx_chn, desc_tx); 877 878 ndev = skb->dev; 879 880 am65_cpts_tx_timestamp(tx_chn->common->cpts, skb); 881 882 ndev_priv = netdev_priv(ndev); 883 stats = this_cpu_ptr(ndev_priv->stats); 884 u64_stats_update_begin(&stats->syncp); 885 stats->tx_packets++; 886 stats->tx_bytes += skb->len; 887 u64_stats_update_end(&stats->syncp); 888 889 return skb; 890 } 891 892 static void am65_cpsw_nuss_tx_wake(struct am65_cpsw_tx_chn *tx_chn, struct net_device *ndev, 893 struct netdev_queue *netif_txq) 894 { 895 if (netif_tx_queue_stopped(netif_txq)) { 896 /* Check whether the queue is stopped due to stalled 897 * tx dma, if the queue is stopped then wake the queue 898 * as we have free desc for tx 899 */ 900 __netif_tx_lock(netif_txq, smp_processor_id()); 901 if (netif_running(ndev) && 902 (k3_cppi_desc_pool_avail(tx_chn->desc_pool) >= MAX_SKB_FRAGS)) 903 netif_tx_wake_queue(netif_txq); 904 905 __netif_tx_unlock(netif_txq); 906 } 907 } 908 909 static int am65_cpsw_nuss_tx_compl_packets(struct am65_cpsw_common *common, 910 int chn, unsigned int budget) 911 { 912 struct device *dev = common->dev; 913 struct am65_cpsw_tx_chn *tx_chn; 914 struct netdev_queue *netif_txq; 915 unsigned int total_bytes = 0; 916 struct net_device *ndev; 917 struct sk_buff *skb; 918 dma_addr_t desc_dma; 919 int res, num_tx = 0; 920 921 tx_chn = &common->tx_chns[chn]; 922 923 while (true) { 924 spin_lock(&tx_chn->lock); 925 res = k3_udma_glue_pop_tx_chn(tx_chn->tx_chn, &desc_dma); 926 spin_unlock(&tx_chn->lock); 927 if (res == -ENODATA) 928 break; 929 930 if (cppi5_desc_is_tdcm(desc_dma)) { 931 if (atomic_dec_and_test(&common->tdown_cnt)) 932 complete(&common->tdown_complete); 933 break; 934 } 935 936 skb = am65_cpsw_nuss_tx_compl_packet(tx_chn, desc_dma); 937 total_bytes = skb->len; 938 ndev = skb->dev; 939 napi_consume_skb(skb, budget); 940 num_tx++; 941 942 netif_txq = netdev_get_tx_queue(ndev, chn); 943 944 netdev_tx_completed_queue(netif_txq, num_tx, total_bytes); 945 946 am65_cpsw_nuss_tx_wake(tx_chn, ndev, netif_txq); 947 } 948 949 dev_dbg(dev, "%s:%u pkt:%d\n", __func__, chn, num_tx); 950 951 return num_tx; 952 } 953 954 static int am65_cpsw_nuss_tx_compl_packets_2g(struct am65_cpsw_common *common, 955 int chn, unsigned int budget) 956 { 957 struct device *dev = common->dev; 958 struct am65_cpsw_tx_chn *tx_chn; 959 struct netdev_queue *netif_txq; 960 unsigned int total_bytes = 0; 961 struct net_device *ndev; 962 struct sk_buff *skb; 963 dma_addr_t desc_dma; 964 int res, num_tx = 0; 965 966 tx_chn = &common->tx_chns[chn]; 967 968 while (true) { 969 res = k3_udma_glue_pop_tx_chn(tx_chn->tx_chn, &desc_dma); 970 if (res == -ENODATA) 971 break; 972 973 if (cppi5_desc_is_tdcm(desc_dma)) { 974 if (atomic_dec_and_test(&common->tdown_cnt)) 975 complete(&common->tdown_complete); 976 break; 977 } 978 979 skb = am65_cpsw_nuss_tx_compl_packet(tx_chn, desc_dma); 980 981 ndev = skb->dev; 982 total_bytes += skb->len; 983 napi_consume_skb(skb, budget); 984 num_tx++; 985 } 986 987 if (!num_tx) 988 return 0; 989 990 netif_txq = netdev_get_tx_queue(ndev, chn); 991 992 netdev_tx_completed_queue(netif_txq, num_tx, total_bytes); 993 994 am65_cpsw_nuss_tx_wake(tx_chn, ndev, netif_txq); 995 996 dev_dbg(dev, "%s:%u pkt:%d\n", __func__, chn, num_tx); 997 998 return num_tx; 999 } 1000 1001 static int am65_cpsw_nuss_tx_poll(struct napi_struct *napi_tx, int budget) 1002 { 1003 struct am65_cpsw_tx_chn *tx_chn = am65_cpsw_napi_to_tx_chn(napi_tx); 1004 int num_tx; 1005 1006 if (AM65_CPSW_IS_CPSW2G(tx_chn->common)) 1007 num_tx = am65_cpsw_nuss_tx_compl_packets_2g(tx_chn->common, tx_chn->id, budget); 1008 else 1009 num_tx = am65_cpsw_nuss_tx_compl_packets(tx_chn->common, tx_chn->id, budget); 1010 1011 if (num_tx >= budget) 1012 return budget; 1013 1014 if (napi_complete_done(napi_tx, num_tx)) 1015 enable_irq(tx_chn->irq); 1016 1017 return 0; 1018 } 1019 1020 static irqreturn_t am65_cpsw_nuss_rx_irq(int irq, void *dev_id) 1021 { 1022 struct am65_cpsw_common *common = dev_id; 1023 1024 common->rx_irq_disabled = true; 1025 disable_irq_nosync(irq); 1026 napi_schedule(&common->napi_rx); 1027 1028 return IRQ_HANDLED; 1029 } 1030 1031 static irqreturn_t am65_cpsw_nuss_tx_irq(int irq, void *dev_id) 1032 { 1033 struct am65_cpsw_tx_chn *tx_chn = dev_id; 1034 1035 disable_irq_nosync(irq); 1036 napi_schedule(&tx_chn->napi_tx); 1037 1038 return IRQ_HANDLED; 1039 } 1040 1041 static netdev_tx_t am65_cpsw_nuss_ndo_slave_xmit(struct sk_buff *skb, 1042 struct net_device *ndev) 1043 { 1044 struct am65_cpsw_common *common = am65_ndev_to_common(ndev); 1045 struct cppi5_host_desc_t *first_desc, *next_desc, *cur_desc; 1046 struct am65_cpsw_port *port = am65_ndev_to_port(ndev); 1047 struct device *dev = common->dev; 1048 struct am65_cpsw_tx_chn *tx_chn; 1049 struct netdev_queue *netif_txq; 1050 dma_addr_t desc_dma, buf_dma; 1051 int ret, q_idx, i; 1052 void **swdata; 1053 u32 *psdata; 1054 u32 pkt_len; 1055 1056 /* padding enabled in hw */ 1057 pkt_len = skb_headlen(skb); 1058 1059 /* SKB TX timestamp */ 1060 if (port->tx_ts_enabled) 1061 am65_cpts_prep_tx_timestamp(common->cpts, skb); 1062 1063 q_idx = skb_get_queue_mapping(skb); 1064 dev_dbg(dev, "%s skb_queue:%d\n", __func__, q_idx); 1065 1066 tx_chn = &common->tx_chns[q_idx]; 1067 netif_txq = netdev_get_tx_queue(ndev, q_idx); 1068 1069 /* Map the linear buffer */ 1070 buf_dma = dma_map_single(tx_chn->dma_dev, skb->data, pkt_len, 1071 DMA_TO_DEVICE); 1072 if (unlikely(dma_mapping_error(tx_chn->dma_dev, buf_dma))) { 1073 dev_err(dev, "Failed to map tx skb buffer\n"); 1074 ndev->stats.tx_errors++; 1075 goto err_free_skb; 1076 } 1077 1078 first_desc = k3_cppi_desc_pool_alloc(tx_chn->desc_pool); 1079 if (!first_desc) { 1080 dev_dbg(dev, "Failed to allocate descriptor\n"); 1081 dma_unmap_single(tx_chn->dma_dev, buf_dma, pkt_len, 1082 DMA_TO_DEVICE); 1083 goto busy_stop_q; 1084 } 1085 1086 cppi5_hdesc_init(first_desc, CPPI5_INFO0_HDESC_EPIB_PRESENT, 1087 AM65_CPSW_NAV_PS_DATA_SIZE); 1088 cppi5_desc_set_pktids(&first_desc->hdr, 0, 0x3FFF); 1089 cppi5_hdesc_set_pkttype(first_desc, 0x7); 1090 cppi5_desc_set_tags_ids(&first_desc->hdr, 0, port->port_id); 1091 1092 k3_udma_glue_tx_dma_to_cppi5_addr(tx_chn->tx_chn, &buf_dma); 1093 cppi5_hdesc_attach_buf(first_desc, buf_dma, pkt_len, buf_dma, pkt_len); 1094 swdata = cppi5_hdesc_get_swdata(first_desc); 1095 *(swdata) = skb; 1096 psdata = cppi5_hdesc_get_psdata(first_desc); 1097 1098 /* HW csum offload if enabled */ 1099 psdata[2] = 0; 1100 if (likely(skb->ip_summed == CHECKSUM_PARTIAL)) { 1101 unsigned int cs_start, cs_offset; 1102 1103 cs_start = skb_transport_offset(skb); 1104 cs_offset = cs_start + skb->csum_offset; 1105 /* HW numerates bytes starting from 1 */ 1106 psdata[2] = ((cs_offset + 1) << 24) | 1107 ((cs_start + 1) << 16) | (skb->len - cs_start); 1108 dev_dbg(dev, "%s tx psdata:%#x\n", __func__, psdata[2]); 1109 } 1110 1111 if (!skb_is_nonlinear(skb)) 1112 goto done_tx; 1113 1114 dev_dbg(dev, "fragmented SKB\n"); 1115 1116 /* Handle the case where skb is fragmented in pages */ 1117 cur_desc = first_desc; 1118 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { 1119 skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 1120 u32 frag_size = skb_frag_size(frag); 1121 1122 next_desc = k3_cppi_desc_pool_alloc(tx_chn->desc_pool); 1123 if (!next_desc) { 1124 dev_err(dev, "Failed to allocate descriptor\n"); 1125 goto busy_free_descs; 1126 } 1127 1128 buf_dma = skb_frag_dma_map(tx_chn->dma_dev, frag, 0, frag_size, 1129 DMA_TO_DEVICE); 1130 if (unlikely(dma_mapping_error(tx_chn->dma_dev, buf_dma))) { 1131 dev_err(dev, "Failed to map tx skb page\n"); 1132 k3_cppi_desc_pool_free(tx_chn->desc_pool, next_desc); 1133 ndev->stats.tx_errors++; 1134 goto err_free_descs; 1135 } 1136 1137 cppi5_hdesc_reset_hbdesc(next_desc); 1138 k3_udma_glue_tx_dma_to_cppi5_addr(tx_chn->tx_chn, &buf_dma); 1139 cppi5_hdesc_attach_buf(next_desc, 1140 buf_dma, frag_size, buf_dma, frag_size); 1141 1142 desc_dma = k3_cppi_desc_pool_virt2dma(tx_chn->desc_pool, 1143 next_desc); 1144 k3_udma_glue_tx_dma_to_cppi5_addr(tx_chn->tx_chn, &desc_dma); 1145 cppi5_hdesc_link_hbdesc(cur_desc, desc_dma); 1146 1147 pkt_len += frag_size; 1148 cur_desc = next_desc; 1149 } 1150 WARN_ON(pkt_len != skb->len); 1151 1152 done_tx: 1153 skb_tx_timestamp(skb); 1154 1155 /* report bql before sending packet */ 1156 netdev_tx_sent_queue(netif_txq, pkt_len); 1157 1158 cppi5_hdesc_set_pktlen(first_desc, pkt_len); 1159 desc_dma = k3_cppi_desc_pool_virt2dma(tx_chn->desc_pool, first_desc); 1160 if (AM65_CPSW_IS_CPSW2G(common)) { 1161 ret = k3_udma_glue_push_tx_chn(tx_chn->tx_chn, first_desc, desc_dma); 1162 } else { 1163 spin_lock_bh(&tx_chn->lock); 1164 ret = k3_udma_glue_push_tx_chn(tx_chn->tx_chn, first_desc, desc_dma); 1165 spin_unlock_bh(&tx_chn->lock); 1166 } 1167 if (ret) { 1168 dev_err(dev, "can't push desc %d\n", ret); 1169 /* inform bql */ 1170 netdev_tx_completed_queue(netif_txq, 1, pkt_len); 1171 ndev->stats.tx_errors++; 1172 goto err_free_descs; 1173 } 1174 1175 if (k3_cppi_desc_pool_avail(tx_chn->desc_pool) < MAX_SKB_FRAGS) { 1176 netif_tx_stop_queue(netif_txq); 1177 /* Barrier, so that stop_queue visible to other cpus */ 1178 smp_mb__after_atomic(); 1179 dev_dbg(dev, "netif_tx_stop_queue %d\n", q_idx); 1180 1181 /* re-check for smp */ 1182 if (k3_cppi_desc_pool_avail(tx_chn->desc_pool) >= 1183 MAX_SKB_FRAGS) { 1184 netif_tx_wake_queue(netif_txq); 1185 dev_dbg(dev, "netif_tx_wake_queue %d\n", q_idx); 1186 } 1187 } 1188 1189 return NETDEV_TX_OK; 1190 1191 err_free_descs: 1192 am65_cpsw_nuss_xmit_free(tx_chn, first_desc); 1193 err_free_skb: 1194 ndev->stats.tx_dropped++; 1195 dev_kfree_skb_any(skb); 1196 return NETDEV_TX_OK; 1197 1198 busy_free_descs: 1199 am65_cpsw_nuss_xmit_free(tx_chn, first_desc); 1200 busy_stop_q: 1201 netif_tx_stop_queue(netif_txq); 1202 return NETDEV_TX_BUSY; 1203 } 1204 1205 static int am65_cpsw_nuss_ndo_slave_set_mac_address(struct net_device *ndev, 1206 void *addr) 1207 { 1208 struct am65_cpsw_common *common = am65_ndev_to_common(ndev); 1209 struct am65_cpsw_port *port = am65_ndev_to_port(ndev); 1210 struct sockaddr *sockaddr = (struct sockaddr *)addr; 1211 int ret; 1212 1213 ret = eth_prepare_mac_addr_change(ndev, addr); 1214 if (ret < 0) 1215 return ret; 1216 1217 ret = pm_runtime_get_sync(common->dev); 1218 if (ret < 0) { 1219 pm_runtime_put_noidle(common->dev); 1220 return ret; 1221 } 1222 1223 cpsw_ale_del_ucast(common->ale, ndev->dev_addr, 1224 HOST_PORT_NUM, 0, 0); 1225 cpsw_ale_add_ucast(common->ale, sockaddr->sa_data, 1226 HOST_PORT_NUM, ALE_SECURE, 0); 1227 1228 am65_cpsw_port_set_sl_mac(port, addr); 1229 eth_commit_mac_addr_change(ndev, sockaddr); 1230 1231 pm_runtime_put(common->dev); 1232 1233 return 0; 1234 } 1235 1236 static int am65_cpsw_nuss_hwtstamp_set(struct net_device *ndev, 1237 struct ifreq *ifr) 1238 { 1239 struct am65_cpsw_common *common = am65_ndev_to_common(ndev); 1240 struct am65_cpsw_port *port = am65_ndev_to_port(ndev); 1241 u32 ts_ctrl, seq_id, ts_ctrl_ltype2, ts_vlan_ltype; 1242 struct hwtstamp_config cfg; 1243 1244 if (!IS_ENABLED(CONFIG_TI_K3_AM65_CPTS)) 1245 return -EOPNOTSUPP; 1246 1247 if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg))) 1248 return -EFAULT; 1249 1250 /* TX HW timestamp */ 1251 switch (cfg.tx_type) { 1252 case HWTSTAMP_TX_OFF: 1253 case HWTSTAMP_TX_ON: 1254 break; 1255 default: 1256 return -ERANGE; 1257 } 1258 1259 switch (cfg.rx_filter) { 1260 case HWTSTAMP_FILTER_NONE: 1261 port->rx_ts_enabled = false; 1262 break; 1263 case HWTSTAMP_FILTER_ALL: 1264 case HWTSTAMP_FILTER_SOME: 1265 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: 1266 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: 1267 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: 1268 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: 1269 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 1270 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 1271 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: 1272 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: 1273 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: 1274 case HWTSTAMP_FILTER_PTP_V2_EVENT: 1275 case HWTSTAMP_FILTER_PTP_V2_SYNC: 1276 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 1277 case HWTSTAMP_FILTER_NTP_ALL: 1278 port->rx_ts_enabled = true; 1279 cfg.rx_filter = HWTSTAMP_FILTER_ALL; 1280 break; 1281 default: 1282 return -ERANGE; 1283 } 1284 1285 port->tx_ts_enabled = (cfg.tx_type == HWTSTAMP_TX_ON); 1286 1287 /* cfg TX timestamp */ 1288 seq_id = (AM65_CPSW_TS_SEQ_ID_OFFSET << 1289 AM65_CPSW_PN_TS_SEQ_ID_OFFSET_SHIFT) | ETH_P_1588; 1290 1291 ts_vlan_ltype = ETH_P_8021Q; 1292 1293 ts_ctrl_ltype2 = ETH_P_1588 | 1294 AM65_CPSW_PN_TS_CTL_LTYPE2_TS_107 | 1295 AM65_CPSW_PN_TS_CTL_LTYPE2_TS_129 | 1296 AM65_CPSW_PN_TS_CTL_LTYPE2_TS_130 | 1297 AM65_CPSW_PN_TS_CTL_LTYPE2_TS_131 | 1298 AM65_CPSW_PN_TS_CTL_LTYPE2_TS_132 | 1299 AM65_CPSW_PN_TS_CTL_LTYPE2_TS_319 | 1300 AM65_CPSW_PN_TS_CTL_LTYPE2_TS_320 | 1301 AM65_CPSW_PN_TS_CTL_LTYPE2_TS_TTL_NONZERO; 1302 1303 ts_ctrl = AM65_CPSW_TS_EVENT_MSG_TYPE_BITS << 1304 AM65_CPSW_PN_TS_CTL_MSG_TYPE_EN_SHIFT; 1305 1306 if (port->tx_ts_enabled) 1307 ts_ctrl |= AM65_CPSW_TS_TX_ANX_ALL_EN | 1308 AM65_CPSW_PN_TS_CTL_TX_VLAN_LT1_EN; 1309 1310 writel(seq_id, port->port_base + AM65_CPSW_PORTN_REG_TS_SEQ_LTYPE_REG); 1311 writel(ts_vlan_ltype, port->port_base + 1312 AM65_CPSW_PORTN_REG_TS_VLAN_LTYPE_REG); 1313 writel(ts_ctrl_ltype2, port->port_base + 1314 AM65_CPSW_PORTN_REG_TS_CTL_LTYPE2); 1315 writel(ts_ctrl, port->port_base + AM65_CPSW_PORTN_REG_TS_CTL); 1316 1317 /* en/dis RX timestamp */ 1318 am65_cpts_rx_enable(common->cpts, port->rx_ts_enabled); 1319 1320 return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0; 1321 } 1322 1323 static int am65_cpsw_nuss_hwtstamp_get(struct net_device *ndev, 1324 struct ifreq *ifr) 1325 { 1326 struct am65_cpsw_port *port = am65_ndev_to_port(ndev); 1327 struct hwtstamp_config cfg; 1328 1329 if (!IS_ENABLED(CONFIG_TI_K3_AM65_CPTS)) 1330 return -EOPNOTSUPP; 1331 1332 cfg.flags = 0; 1333 cfg.tx_type = port->tx_ts_enabled ? 1334 HWTSTAMP_TX_ON : HWTSTAMP_TX_OFF; 1335 cfg.rx_filter = port->rx_ts_enabled ? 1336 HWTSTAMP_FILTER_ALL : HWTSTAMP_FILTER_NONE; 1337 1338 return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0; 1339 } 1340 1341 static int am65_cpsw_nuss_ndo_slave_ioctl(struct net_device *ndev, 1342 struct ifreq *req, int cmd) 1343 { 1344 struct am65_cpsw_port *port = am65_ndev_to_port(ndev); 1345 1346 if (!netif_running(ndev)) 1347 return -EINVAL; 1348 1349 switch (cmd) { 1350 case SIOCSHWTSTAMP: 1351 return am65_cpsw_nuss_hwtstamp_set(ndev, req); 1352 case SIOCGHWTSTAMP: 1353 return am65_cpsw_nuss_hwtstamp_get(ndev, req); 1354 } 1355 1356 return phylink_mii_ioctl(port->slave.phylink, req, cmd); 1357 } 1358 1359 static void am65_cpsw_nuss_ndo_get_stats(struct net_device *dev, 1360 struct rtnl_link_stats64 *stats) 1361 { 1362 struct am65_cpsw_ndev_priv *ndev_priv = netdev_priv(dev); 1363 unsigned int start; 1364 int cpu; 1365 1366 for_each_possible_cpu(cpu) { 1367 struct am65_cpsw_ndev_stats *cpu_stats; 1368 u64 rx_packets; 1369 u64 rx_bytes; 1370 u64 tx_packets; 1371 u64 tx_bytes; 1372 1373 cpu_stats = per_cpu_ptr(ndev_priv->stats, cpu); 1374 do { 1375 start = u64_stats_fetch_begin_irq(&cpu_stats->syncp); 1376 rx_packets = cpu_stats->rx_packets; 1377 rx_bytes = cpu_stats->rx_bytes; 1378 tx_packets = cpu_stats->tx_packets; 1379 tx_bytes = cpu_stats->tx_bytes; 1380 } while (u64_stats_fetch_retry_irq(&cpu_stats->syncp, start)); 1381 1382 stats->rx_packets += rx_packets; 1383 stats->rx_bytes += rx_bytes; 1384 stats->tx_packets += tx_packets; 1385 stats->tx_bytes += tx_bytes; 1386 } 1387 1388 stats->rx_errors = dev->stats.rx_errors; 1389 stats->rx_dropped = dev->stats.rx_dropped; 1390 stats->tx_dropped = dev->stats.tx_dropped; 1391 } 1392 1393 static struct devlink_port *am65_cpsw_ndo_get_devlink_port(struct net_device *ndev) 1394 { 1395 struct am65_cpsw_port *port = am65_ndev_to_port(ndev); 1396 1397 return &port->devlink_port; 1398 } 1399 1400 static const struct net_device_ops am65_cpsw_nuss_netdev_ops = { 1401 .ndo_open = am65_cpsw_nuss_ndo_slave_open, 1402 .ndo_stop = am65_cpsw_nuss_ndo_slave_stop, 1403 .ndo_start_xmit = am65_cpsw_nuss_ndo_slave_xmit, 1404 .ndo_set_rx_mode = am65_cpsw_nuss_ndo_slave_set_rx_mode, 1405 .ndo_get_stats64 = am65_cpsw_nuss_ndo_get_stats, 1406 .ndo_validate_addr = eth_validate_addr, 1407 .ndo_set_mac_address = am65_cpsw_nuss_ndo_slave_set_mac_address, 1408 .ndo_tx_timeout = am65_cpsw_nuss_ndo_host_tx_timeout, 1409 .ndo_vlan_rx_add_vid = am65_cpsw_nuss_ndo_slave_add_vid, 1410 .ndo_vlan_rx_kill_vid = am65_cpsw_nuss_ndo_slave_kill_vid, 1411 .ndo_eth_ioctl = am65_cpsw_nuss_ndo_slave_ioctl, 1412 .ndo_setup_tc = am65_cpsw_qos_ndo_setup_tc, 1413 .ndo_get_devlink_port = am65_cpsw_ndo_get_devlink_port, 1414 }; 1415 1416 static void am65_cpsw_nuss_mac_config(struct phylink_config *config, unsigned int mode, 1417 const struct phylink_link_state *state) 1418 { 1419 /* Currently not used */ 1420 } 1421 1422 static void am65_cpsw_nuss_mac_link_down(struct phylink_config *config, unsigned int mode, 1423 phy_interface_t interface) 1424 { 1425 struct am65_cpsw_slave_data *slave = container_of(config, struct am65_cpsw_slave_data, 1426 phylink_config); 1427 struct am65_cpsw_port *port = container_of(slave, struct am65_cpsw_port, slave); 1428 struct am65_cpsw_common *common = port->common; 1429 struct net_device *ndev = port->ndev; 1430 int tmo; 1431 1432 /* disable forwarding */ 1433 cpsw_ale_control_set(common->ale, port->port_id, ALE_PORT_STATE, ALE_PORT_STATE_DISABLE); 1434 1435 cpsw_sl_ctl_set(port->slave.mac_sl, CPSW_SL_CTL_CMD_IDLE); 1436 1437 tmo = cpsw_sl_wait_for_idle(port->slave.mac_sl, 100); 1438 dev_dbg(common->dev, "down msc_sl %08x tmo %d\n", 1439 cpsw_sl_reg_read(port->slave.mac_sl, CPSW_SL_MACSTATUS), tmo); 1440 1441 cpsw_sl_ctl_reset(port->slave.mac_sl); 1442 1443 am65_cpsw_qos_link_down(ndev); 1444 netif_tx_stop_all_queues(ndev); 1445 } 1446 1447 static void am65_cpsw_nuss_mac_link_up(struct phylink_config *config, struct phy_device *phy, 1448 unsigned int mode, phy_interface_t interface, int speed, 1449 int duplex, bool tx_pause, bool rx_pause) 1450 { 1451 struct am65_cpsw_slave_data *slave = container_of(config, struct am65_cpsw_slave_data, 1452 phylink_config); 1453 struct am65_cpsw_port *port = container_of(slave, struct am65_cpsw_port, slave); 1454 struct am65_cpsw_common *common = port->common; 1455 u32 mac_control = CPSW_SL_CTL_GMII_EN; 1456 struct net_device *ndev = port->ndev; 1457 1458 if (speed == SPEED_1000) 1459 mac_control |= CPSW_SL_CTL_GIG; 1460 if (speed == SPEED_10 && interface == PHY_INTERFACE_MODE_RGMII) 1461 /* Can be used with in band mode only */ 1462 mac_control |= CPSW_SL_CTL_EXT_EN; 1463 if (speed == SPEED_100 && interface == PHY_INTERFACE_MODE_RMII) 1464 mac_control |= CPSW_SL_CTL_IFCTL_A; 1465 if (duplex) 1466 mac_control |= CPSW_SL_CTL_FULLDUPLEX; 1467 1468 /* rx_pause/tx_pause */ 1469 if (rx_pause) 1470 mac_control |= CPSW_SL_CTL_RX_FLOW_EN; 1471 1472 if (tx_pause) 1473 mac_control |= CPSW_SL_CTL_TX_FLOW_EN; 1474 1475 cpsw_sl_ctl_set(port->slave.mac_sl, mac_control); 1476 1477 /* enable forwarding */ 1478 cpsw_ale_control_set(common->ale, port->port_id, ALE_PORT_STATE, ALE_PORT_STATE_FORWARD); 1479 1480 am65_cpsw_qos_link_up(ndev, speed); 1481 netif_tx_wake_all_queues(ndev); 1482 } 1483 1484 static const struct phylink_mac_ops am65_cpsw_phylink_mac_ops = { 1485 .validate = phylink_generic_validate, 1486 .mac_config = am65_cpsw_nuss_mac_config, 1487 .mac_link_down = am65_cpsw_nuss_mac_link_down, 1488 .mac_link_up = am65_cpsw_nuss_mac_link_up, 1489 }; 1490 1491 static void am65_cpsw_nuss_slave_disable_unused(struct am65_cpsw_port *port) 1492 { 1493 struct am65_cpsw_common *common = port->common; 1494 1495 if (!port->disabled) 1496 return; 1497 1498 cpsw_ale_control_set(common->ale, port->port_id, 1499 ALE_PORT_STATE, ALE_PORT_STATE_DISABLE); 1500 1501 cpsw_sl_reset(port->slave.mac_sl, 100); 1502 cpsw_sl_ctl_reset(port->slave.mac_sl); 1503 } 1504 1505 static void am65_cpsw_nuss_free_tx_chns(void *data) 1506 { 1507 struct am65_cpsw_common *common = data; 1508 int i; 1509 1510 for (i = 0; i < common->tx_ch_num; i++) { 1511 struct am65_cpsw_tx_chn *tx_chn = &common->tx_chns[i]; 1512 1513 if (!IS_ERR_OR_NULL(tx_chn->desc_pool)) 1514 k3_cppi_desc_pool_destroy(tx_chn->desc_pool); 1515 1516 if (!IS_ERR_OR_NULL(tx_chn->tx_chn)) 1517 k3_udma_glue_release_tx_chn(tx_chn->tx_chn); 1518 1519 memset(tx_chn, 0, sizeof(*tx_chn)); 1520 } 1521 } 1522 1523 void am65_cpsw_nuss_remove_tx_chns(struct am65_cpsw_common *common) 1524 { 1525 struct device *dev = common->dev; 1526 int i; 1527 1528 devm_remove_action(dev, am65_cpsw_nuss_free_tx_chns, common); 1529 1530 for (i = 0; i < common->tx_ch_num; i++) { 1531 struct am65_cpsw_tx_chn *tx_chn = &common->tx_chns[i]; 1532 1533 if (tx_chn->irq) 1534 devm_free_irq(dev, tx_chn->irq, tx_chn); 1535 1536 netif_napi_del(&tx_chn->napi_tx); 1537 1538 if (!IS_ERR_OR_NULL(tx_chn->desc_pool)) 1539 k3_cppi_desc_pool_destroy(tx_chn->desc_pool); 1540 1541 if (!IS_ERR_OR_NULL(tx_chn->tx_chn)) 1542 k3_udma_glue_release_tx_chn(tx_chn->tx_chn); 1543 1544 memset(tx_chn, 0, sizeof(*tx_chn)); 1545 } 1546 } 1547 1548 static int am65_cpsw_nuss_init_tx_chns(struct am65_cpsw_common *common) 1549 { 1550 u32 max_desc_num = ALIGN(AM65_CPSW_MAX_TX_DESC, MAX_SKB_FRAGS); 1551 struct k3_udma_glue_tx_channel_cfg tx_cfg = { 0 }; 1552 struct device *dev = common->dev; 1553 struct k3_ring_cfg ring_cfg = { 1554 .elm_size = K3_RINGACC_RING_ELSIZE_8, 1555 .mode = K3_RINGACC_RING_MODE_RING, 1556 .flags = 0 1557 }; 1558 u32 hdesc_size; 1559 int i, ret = 0; 1560 1561 hdesc_size = cppi5_hdesc_calc_size(true, AM65_CPSW_NAV_PS_DATA_SIZE, 1562 AM65_CPSW_NAV_SW_DATA_SIZE); 1563 1564 tx_cfg.swdata_size = AM65_CPSW_NAV_SW_DATA_SIZE; 1565 tx_cfg.tx_cfg = ring_cfg; 1566 tx_cfg.txcq_cfg = ring_cfg; 1567 tx_cfg.tx_cfg.size = max_desc_num; 1568 tx_cfg.txcq_cfg.size = max_desc_num; 1569 1570 for (i = 0; i < common->tx_ch_num; i++) { 1571 struct am65_cpsw_tx_chn *tx_chn = &common->tx_chns[i]; 1572 1573 snprintf(tx_chn->tx_chn_name, 1574 sizeof(tx_chn->tx_chn_name), "tx%d", i); 1575 1576 spin_lock_init(&tx_chn->lock); 1577 tx_chn->common = common; 1578 tx_chn->id = i; 1579 tx_chn->descs_num = max_desc_num; 1580 1581 tx_chn->tx_chn = 1582 k3_udma_glue_request_tx_chn(dev, 1583 tx_chn->tx_chn_name, 1584 &tx_cfg); 1585 if (IS_ERR(tx_chn->tx_chn)) { 1586 ret = dev_err_probe(dev, PTR_ERR(tx_chn->tx_chn), 1587 "Failed to request tx dma channel\n"); 1588 goto err; 1589 } 1590 tx_chn->dma_dev = k3_udma_glue_tx_get_dma_device(tx_chn->tx_chn); 1591 1592 tx_chn->desc_pool = k3_cppi_desc_pool_create_name(tx_chn->dma_dev, 1593 tx_chn->descs_num, 1594 hdesc_size, 1595 tx_chn->tx_chn_name); 1596 if (IS_ERR(tx_chn->desc_pool)) { 1597 ret = PTR_ERR(tx_chn->desc_pool); 1598 dev_err(dev, "Failed to create poll %d\n", ret); 1599 goto err; 1600 } 1601 1602 tx_chn->irq = k3_udma_glue_tx_get_irq(tx_chn->tx_chn); 1603 if (tx_chn->irq <= 0) { 1604 dev_err(dev, "Failed to get tx dma irq %d\n", 1605 tx_chn->irq); 1606 goto err; 1607 } 1608 1609 snprintf(tx_chn->tx_chn_name, 1610 sizeof(tx_chn->tx_chn_name), "%s-tx%d", 1611 dev_name(dev), tx_chn->id); 1612 } 1613 1614 err: 1615 i = devm_add_action(dev, am65_cpsw_nuss_free_tx_chns, common); 1616 if (i) { 1617 dev_err(dev, "Failed to add free_tx_chns action %d\n", i); 1618 return i; 1619 } 1620 1621 return ret; 1622 } 1623 1624 static void am65_cpsw_nuss_free_rx_chns(void *data) 1625 { 1626 struct am65_cpsw_common *common = data; 1627 struct am65_cpsw_rx_chn *rx_chn; 1628 1629 rx_chn = &common->rx_chns; 1630 1631 if (!IS_ERR_OR_NULL(rx_chn->desc_pool)) 1632 k3_cppi_desc_pool_destroy(rx_chn->desc_pool); 1633 1634 if (!IS_ERR_OR_NULL(rx_chn->rx_chn)) 1635 k3_udma_glue_release_rx_chn(rx_chn->rx_chn); 1636 } 1637 1638 static int am65_cpsw_nuss_init_rx_chns(struct am65_cpsw_common *common) 1639 { 1640 struct am65_cpsw_rx_chn *rx_chn = &common->rx_chns; 1641 struct k3_udma_glue_rx_channel_cfg rx_cfg = { 0 }; 1642 u32 max_desc_num = AM65_CPSW_MAX_RX_DESC; 1643 struct device *dev = common->dev; 1644 u32 hdesc_size; 1645 u32 fdqring_id; 1646 int i, ret = 0; 1647 1648 hdesc_size = cppi5_hdesc_calc_size(true, AM65_CPSW_NAV_PS_DATA_SIZE, 1649 AM65_CPSW_NAV_SW_DATA_SIZE); 1650 1651 rx_cfg.swdata_size = AM65_CPSW_NAV_SW_DATA_SIZE; 1652 rx_cfg.flow_id_num = AM65_CPSW_MAX_RX_FLOWS; 1653 rx_cfg.flow_id_base = common->rx_flow_id_base; 1654 1655 /* init all flows */ 1656 rx_chn->dev = dev; 1657 rx_chn->descs_num = max_desc_num; 1658 1659 rx_chn->rx_chn = k3_udma_glue_request_rx_chn(dev, "rx", &rx_cfg); 1660 if (IS_ERR(rx_chn->rx_chn)) { 1661 ret = dev_err_probe(dev, PTR_ERR(rx_chn->rx_chn), 1662 "Failed to request rx dma channel\n"); 1663 goto err; 1664 } 1665 rx_chn->dma_dev = k3_udma_glue_rx_get_dma_device(rx_chn->rx_chn); 1666 1667 rx_chn->desc_pool = k3_cppi_desc_pool_create_name(rx_chn->dma_dev, 1668 rx_chn->descs_num, 1669 hdesc_size, "rx"); 1670 if (IS_ERR(rx_chn->desc_pool)) { 1671 ret = PTR_ERR(rx_chn->desc_pool); 1672 dev_err(dev, "Failed to create rx poll %d\n", ret); 1673 goto err; 1674 } 1675 1676 common->rx_flow_id_base = 1677 k3_udma_glue_rx_get_flow_id_base(rx_chn->rx_chn); 1678 dev_info(dev, "set new flow-id-base %u\n", common->rx_flow_id_base); 1679 1680 fdqring_id = K3_RINGACC_RING_ID_ANY; 1681 for (i = 0; i < rx_cfg.flow_id_num; i++) { 1682 struct k3_ring_cfg rxring_cfg = { 1683 .elm_size = K3_RINGACC_RING_ELSIZE_8, 1684 .mode = K3_RINGACC_RING_MODE_RING, 1685 .flags = 0, 1686 }; 1687 struct k3_ring_cfg fdqring_cfg = { 1688 .elm_size = K3_RINGACC_RING_ELSIZE_8, 1689 .flags = K3_RINGACC_RING_SHARED, 1690 }; 1691 struct k3_udma_glue_rx_flow_cfg rx_flow_cfg = { 1692 .rx_cfg = rxring_cfg, 1693 .rxfdq_cfg = fdqring_cfg, 1694 .ring_rxq_id = K3_RINGACC_RING_ID_ANY, 1695 .src_tag_lo_sel = 1696 K3_UDMA_GLUE_SRC_TAG_LO_USE_REMOTE_SRC_TAG, 1697 }; 1698 1699 rx_flow_cfg.ring_rxfdq0_id = fdqring_id; 1700 rx_flow_cfg.rx_cfg.size = max_desc_num; 1701 rx_flow_cfg.rxfdq_cfg.size = max_desc_num; 1702 rx_flow_cfg.rxfdq_cfg.mode = common->pdata.fdqring_mode; 1703 1704 ret = k3_udma_glue_rx_flow_init(rx_chn->rx_chn, 1705 i, &rx_flow_cfg); 1706 if (ret) { 1707 dev_err(dev, "Failed to init rx flow%d %d\n", i, ret); 1708 goto err; 1709 } 1710 if (!i) 1711 fdqring_id = 1712 k3_udma_glue_rx_flow_get_fdq_id(rx_chn->rx_chn, 1713 i); 1714 1715 rx_chn->irq = k3_udma_glue_rx_get_irq(rx_chn->rx_chn, i); 1716 1717 if (rx_chn->irq <= 0) { 1718 dev_err(dev, "Failed to get rx dma irq %d\n", 1719 rx_chn->irq); 1720 ret = -ENXIO; 1721 goto err; 1722 } 1723 } 1724 1725 err: 1726 i = devm_add_action(dev, am65_cpsw_nuss_free_rx_chns, common); 1727 if (i) { 1728 dev_err(dev, "Failed to add free_rx_chns action %d\n", i); 1729 return i; 1730 } 1731 1732 return ret; 1733 } 1734 1735 static int am65_cpsw_nuss_init_host_p(struct am65_cpsw_common *common) 1736 { 1737 struct am65_cpsw_host *host_p = am65_common_get_host(common); 1738 1739 host_p->common = common; 1740 host_p->port_base = common->cpsw_base + AM65_CPSW_NU_PORTS_BASE; 1741 host_p->stat_base = common->cpsw_base + AM65_CPSW_NU_STATS_BASE; 1742 1743 return 0; 1744 } 1745 1746 static int am65_cpsw_am654_get_efuse_macid(struct device_node *of_node, 1747 int slave, u8 *mac_addr) 1748 { 1749 u32 mac_lo, mac_hi, offset; 1750 struct regmap *syscon; 1751 int ret; 1752 1753 syscon = syscon_regmap_lookup_by_phandle(of_node, "ti,syscon-efuse"); 1754 if (IS_ERR(syscon)) { 1755 if (PTR_ERR(syscon) == -ENODEV) 1756 return 0; 1757 return PTR_ERR(syscon); 1758 } 1759 1760 ret = of_property_read_u32_index(of_node, "ti,syscon-efuse", 1, 1761 &offset); 1762 if (ret) 1763 return ret; 1764 1765 regmap_read(syscon, offset, &mac_lo); 1766 regmap_read(syscon, offset + 4, &mac_hi); 1767 1768 mac_addr[0] = (mac_hi >> 8) & 0xff; 1769 mac_addr[1] = mac_hi & 0xff; 1770 mac_addr[2] = (mac_lo >> 24) & 0xff; 1771 mac_addr[3] = (mac_lo >> 16) & 0xff; 1772 mac_addr[4] = (mac_lo >> 8) & 0xff; 1773 mac_addr[5] = mac_lo & 0xff; 1774 1775 return 0; 1776 } 1777 1778 static int am65_cpsw_init_cpts(struct am65_cpsw_common *common) 1779 { 1780 struct device *dev = common->dev; 1781 struct device_node *node; 1782 struct am65_cpts *cpts; 1783 void __iomem *reg_base; 1784 1785 if (!IS_ENABLED(CONFIG_TI_K3_AM65_CPTS)) 1786 return 0; 1787 1788 node = of_get_child_by_name(dev->of_node, "cpts"); 1789 if (!node) { 1790 dev_err(dev, "%s cpts not found\n", __func__); 1791 return -ENOENT; 1792 } 1793 1794 reg_base = common->cpsw_base + AM65_CPSW_NU_CPTS_BASE; 1795 cpts = am65_cpts_create(dev, reg_base, node); 1796 if (IS_ERR(cpts)) { 1797 int ret = PTR_ERR(cpts); 1798 1799 if (ret == -EOPNOTSUPP) { 1800 dev_info(dev, "cpts disabled\n"); 1801 return 0; 1802 } 1803 1804 dev_err(dev, "cpts create err %d\n", ret); 1805 return ret; 1806 } 1807 common->cpts = cpts; 1808 /* Forbid PM runtime if CPTS is running. 1809 * K3 CPSWxG modules may completely lose context during ON->OFF 1810 * transitions depending on integration. 1811 * AM65x/J721E MCU CPSW2G: false 1812 * J721E MAIN_CPSW9G: true 1813 */ 1814 pm_runtime_forbid(dev); 1815 1816 return 0; 1817 } 1818 1819 static int am65_cpsw_nuss_init_slave_ports(struct am65_cpsw_common *common) 1820 { 1821 struct device_node *node, *port_np; 1822 struct device *dev = common->dev; 1823 int ret; 1824 1825 node = of_get_child_by_name(dev->of_node, "ethernet-ports"); 1826 if (!node) 1827 return -ENOENT; 1828 1829 for_each_child_of_node(node, port_np) { 1830 struct am65_cpsw_port *port; 1831 u32 port_id; 1832 1833 /* it is not a slave port node, continue */ 1834 if (strcmp(port_np->name, "port")) 1835 continue; 1836 1837 ret = of_property_read_u32(port_np, "reg", &port_id); 1838 if (ret < 0) { 1839 dev_err(dev, "%pOF error reading port_id %d\n", 1840 port_np, ret); 1841 goto of_node_put; 1842 } 1843 1844 if (!port_id || port_id > common->port_num) { 1845 dev_err(dev, "%pOF has invalid port_id %u %s\n", 1846 port_np, port_id, port_np->name); 1847 ret = -EINVAL; 1848 goto of_node_put; 1849 } 1850 1851 port = am65_common_get_port(common, port_id); 1852 port->port_id = port_id; 1853 port->common = common; 1854 port->port_base = common->cpsw_base + AM65_CPSW_NU_PORTS_BASE + 1855 AM65_CPSW_NU_PORTS_OFFSET * (port_id); 1856 port->stat_base = common->cpsw_base + AM65_CPSW_NU_STATS_BASE + 1857 (AM65_CPSW_NU_STATS_PORT_OFFSET * port_id); 1858 port->name = of_get_property(port_np, "label", NULL); 1859 port->fetch_ram_base = 1860 common->cpsw_base + AM65_CPSW_NU_FRAM_BASE + 1861 (AM65_CPSW_NU_FRAM_PORT_OFFSET * (port_id - 1)); 1862 1863 port->slave.mac_sl = cpsw_sl_get("am65", dev, port->port_base); 1864 if (IS_ERR(port->slave.mac_sl)) { 1865 ret = PTR_ERR(port->slave.mac_sl); 1866 goto of_node_put; 1867 } 1868 1869 port->disabled = !of_device_is_available(port_np); 1870 if (port->disabled) { 1871 common->disabled_ports_mask |= BIT(port->port_id); 1872 continue; 1873 } 1874 1875 port->slave.ifphy = devm_of_phy_get(dev, port_np, NULL); 1876 if (IS_ERR(port->slave.ifphy)) { 1877 ret = PTR_ERR(port->slave.ifphy); 1878 dev_err(dev, "%pOF error retrieving port phy: %d\n", 1879 port_np, ret); 1880 goto of_node_put; 1881 } 1882 1883 port->slave.mac_only = 1884 of_property_read_bool(port_np, "ti,mac-only"); 1885 1886 /* get phy/link info */ 1887 port->slave.phy_node = port_np; 1888 ret = of_get_phy_mode(port_np, &port->slave.phy_if); 1889 if (ret) { 1890 dev_err(dev, "%pOF read phy-mode err %d\n", 1891 port_np, ret); 1892 goto of_node_put; 1893 } 1894 1895 ret = of_get_mac_address(port_np, port->slave.mac_addr); 1896 if (ret) { 1897 am65_cpsw_am654_get_efuse_macid(port_np, 1898 port->port_id, 1899 port->slave.mac_addr); 1900 if (!is_valid_ether_addr(port->slave.mac_addr)) { 1901 eth_random_addr(port->slave.mac_addr); 1902 dev_err(dev, "Use random MAC address\n"); 1903 } 1904 } 1905 } 1906 of_node_put(node); 1907 1908 /* is there at least one ext.port */ 1909 if (!(~common->disabled_ports_mask & GENMASK(common->port_num, 1))) { 1910 dev_err(dev, "No Ext. port are available\n"); 1911 return -ENODEV; 1912 } 1913 1914 return 0; 1915 1916 of_node_put: 1917 of_node_put(port_np); 1918 of_node_put(node); 1919 return ret; 1920 } 1921 1922 static void am65_cpsw_pcpu_stats_free(void *data) 1923 { 1924 struct am65_cpsw_ndev_stats __percpu *stats = data; 1925 1926 free_percpu(stats); 1927 } 1928 1929 static void am65_cpsw_nuss_phylink_cleanup(struct am65_cpsw_common *common) 1930 { 1931 struct am65_cpsw_port *port; 1932 int i; 1933 1934 for (i = 0; i < common->port_num; i++) { 1935 port = &common->ports[i]; 1936 if (port->slave.phylink) 1937 phylink_destroy(port->slave.phylink); 1938 } 1939 } 1940 1941 static int 1942 am65_cpsw_nuss_init_port_ndev(struct am65_cpsw_common *common, u32 port_idx) 1943 { 1944 struct am65_cpsw_ndev_priv *ndev_priv; 1945 struct device *dev = common->dev; 1946 struct am65_cpsw_port *port; 1947 struct phylink *phylink; 1948 int ret; 1949 1950 port = &common->ports[port_idx]; 1951 1952 if (port->disabled) 1953 return 0; 1954 1955 /* alloc netdev */ 1956 port->ndev = devm_alloc_etherdev_mqs(common->dev, 1957 sizeof(struct am65_cpsw_ndev_priv), 1958 AM65_CPSW_MAX_TX_QUEUES, 1959 AM65_CPSW_MAX_RX_QUEUES); 1960 if (!port->ndev) { 1961 dev_err(dev, "error allocating slave net_device %u\n", 1962 port->port_id); 1963 return -ENOMEM; 1964 } 1965 1966 ndev_priv = netdev_priv(port->ndev); 1967 ndev_priv->port = port; 1968 ndev_priv->msg_enable = AM65_CPSW_DEBUG; 1969 SET_NETDEV_DEV(port->ndev, dev); 1970 1971 eth_hw_addr_set(port->ndev, port->slave.mac_addr); 1972 1973 port->ndev->min_mtu = AM65_CPSW_MIN_PACKET_SIZE; 1974 port->ndev->max_mtu = AM65_CPSW_MAX_PACKET_SIZE; 1975 port->ndev->hw_features = NETIF_F_SG | 1976 NETIF_F_RXCSUM | 1977 NETIF_F_HW_CSUM | 1978 NETIF_F_HW_TC; 1979 port->ndev->features = port->ndev->hw_features | 1980 NETIF_F_HW_VLAN_CTAG_FILTER; 1981 port->ndev->vlan_features |= NETIF_F_SG; 1982 port->ndev->netdev_ops = &am65_cpsw_nuss_netdev_ops; 1983 port->ndev->ethtool_ops = &am65_cpsw_ethtool_ops_slave; 1984 1985 /* Configuring Phylink */ 1986 port->slave.phylink_config.dev = &port->ndev->dev; 1987 port->slave.phylink_config.type = PHYLINK_NETDEV; 1988 port->slave.phylink_config.mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 | MAC_1000FD; 1989 1990 phy_interface_set_rgmii(port->slave.phylink_config.supported_interfaces); 1991 1992 phylink = phylink_create(&port->slave.phylink_config, dev->fwnode, port->slave.phy_if, 1993 &am65_cpsw_phylink_mac_ops); 1994 if (IS_ERR(phylink)) 1995 return PTR_ERR(phylink); 1996 1997 port->slave.phylink = phylink; 1998 1999 /* Disable TX checksum offload by default due to HW bug */ 2000 if (common->pdata.quirks & AM65_CPSW_QUIRK_I2027_NO_TX_CSUM) 2001 port->ndev->features &= ~NETIF_F_HW_CSUM; 2002 2003 ndev_priv->stats = netdev_alloc_pcpu_stats(struct am65_cpsw_ndev_stats); 2004 if (!ndev_priv->stats) 2005 return -ENOMEM; 2006 2007 ret = devm_add_action_or_reset(dev, am65_cpsw_pcpu_stats_free, 2008 ndev_priv->stats); 2009 if (ret) 2010 dev_err(dev, "failed to add percpu stat free action %d\n", ret); 2011 2012 if (!common->dma_ndev) 2013 common->dma_ndev = port->ndev; 2014 2015 return ret; 2016 } 2017 2018 static int am65_cpsw_nuss_init_ndevs(struct am65_cpsw_common *common) 2019 { 2020 int ret; 2021 int i; 2022 2023 for (i = 0; i < common->port_num; i++) { 2024 ret = am65_cpsw_nuss_init_port_ndev(common, i); 2025 if (ret) 2026 return ret; 2027 } 2028 2029 netif_napi_add(common->dma_ndev, &common->napi_rx, 2030 am65_cpsw_nuss_rx_poll, NAPI_POLL_WEIGHT); 2031 2032 return ret; 2033 } 2034 2035 static int am65_cpsw_nuss_ndev_add_tx_napi(struct am65_cpsw_common *common) 2036 { 2037 struct device *dev = common->dev; 2038 int i, ret = 0; 2039 2040 for (i = 0; i < common->tx_ch_num; i++) { 2041 struct am65_cpsw_tx_chn *tx_chn = &common->tx_chns[i]; 2042 2043 netif_tx_napi_add(common->dma_ndev, &tx_chn->napi_tx, 2044 am65_cpsw_nuss_tx_poll, NAPI_POLL_WEIGHT); 2045 2046 ret = devm_request_irq(dev, tx_chn->irq, 2047 am65_cpsw_nuss_tx_irq, 2048 IRQF_TRIGGER_HIGH, 2049 tx_chn->tx_chn_name, tx_chn); 2050 if (ret) { 2051 dev_err(dev, "failure requesting tx%u irq %u, %d\n", 2052 tx_chn->id, tx_chn->irq, ret); 2053 goto err; 2054 } 2055 } 2056 2057 err: 2058 return ret; 2059 } 2060 2061 static void am65_cpsw_nuss_cleanup_ndev(struct am65_cpsw_common *common) 2062 { 2063 struct am65_cpsw_port *port; 2064 int i; 2065 2066 for (i = 0; i < common->port_num; i++) { 2067 port = &common->ports[i]; 2068 if (port->ndev) 2069 unregister_netdev(port->ndev); 2070 } 2071 } 2072 2073 static void am65_cpsw_port_offload_fwd_mark_update(struct am65_cpsw_common *common) 2074 { 2075 int set_val = 0; 2076 int i; 2077 2078 if (common->br_members == (GENMASK(common->port_num, 1) & ~common->disabled_ports_mask)) 2079 set_val = 1; 2080 2081 dev_dbg(common->dev, "set offload_fwd_mark %d\n", set_val); 2082 2083 for (i = 1; i <= common->port_num; i++) { 2084 struct am65_cpsw_port *port = am65_common_get_port(common, i); 2085 struct am65_cpsw_ndev_priv *priv; 2086 2087 if (!port->ndev) 2088 continue; 2089 2090 priv = am65_ndev_to_priv(port->ndev); 2091 priv->offload_fwd_mark = set_val; 2092 } 2093 } 2094 2095 bool am65_cpsw_port_dev_check(const struct net_device *ndev) 2096 { 2097 if (ndev->netdev_ops == &am65_cpsw_nuss_netdev_ops) { 2098 struct am65_cpsw_common *common = am65_ndev_to_common(ndev); 2099 2100 return !common->is_emac_mode; 2101 } 2102 2103 return false; 2104 } 2105 2106 static int am65_cpsw_netdevice_port_link(struct net_device *ndev, 2107 struct net_device *br_ndev, 2108 struct netlink_ext_ack *extack) 2109 { 2110 struct am65_cpsw_common *common = am65_ndev_to_common(ndev); 2111 struct am65_cpsw_ndev_priv *priv = am65_ndev_to_priv(ndev); 2112 int err; 2113 2114 if (!common->br_members) { 2115 common->hw_bridge_dev = br_ndev; 2116 } else { 2117 /* This is adding the port to a second bridge, this is 2118 * unsupported 2119 */ 2120 if (common->hw_bridge_dev != br_ndev) 2121 return -EOPNOTSUPP; 2122 } 2123 2124 err = switchdev_bridge_port_offload(ndev, ndev, NULL, NULL, NULL, 2125 false, extack); 2126 if (err) 2127 return err; 2128 2129 common->br_members |= BIT(priv->port->port_id); 2130 2131 am65_cpsw_port_offload_fwd_mark_update(common); 2132 2133 return NOTIFY_DONE; 2134 } 2135 2136 static void am65_cpsw_netdevice_port_unlink(struct net_device *ndev) 2137 { 2138 struct am65_cpsw_common *common = am65_ndev_to_common(ndev); 2139 struct am65_cpsw_ndev_priv *priv = am65_ndev_to_priv(ndev); 2140 2141 switchdev_bridge_port_unoffload(ndev, NULL, NULL, NULL); 2142 2143 common->br_members &= ~BIT(priv->port->port_id); 2144 2145 am65_cpsw_port_offload_fwd_mark_update(common); 2146 2147 if (!common->br_members) 2148 common->hw_bridge_dev = NULL; 2149 } 2150 2151 /* netdev notifier */ 2152 static int am65_cpsw_netdevice_event(struct notifier_block *unused, 2153 unsigned long event, void *ptr) 2154 { 2155 struct netlink_ext_ack *extack = netdev_notifier_info_to_extack(ptr); 2156 struct net_device *ndev = netdev_notifier_info_to_dev(ptr); 2157 struct netdev_notifier_changeupper_info *info; 2158 int ret = NOTIFY_DONE; 2159 2160 if (!am65_cpsw_port_dev_check(ndev)) 2161 return NOTIFY_DONE; 2162 2163 switch (event) { 2164 case NETDEV_CHANGEUPPER: 2165 info = ptr; 2166 2167 if (netif_is_bridge_master(info->upper_dev)) { 2168 if (info->linking) 2169 ret = am65_cpsw_netdevice_port_link(ndev, 2170 info->upper_dev, 2171 extack); 2172 else 2173 am65_cpsw_netdevice_port_unlink(ndev); 2174 } 2175 break; 2176 default: 2177 return NOTIFY_DONE; 2178 } 2179 2180 return notifier_from_errno(ret); 2181 } 2182 2183 static int am65_cpsw_register_notifiers(struct am65_cpsw_common *cpsw) 2184 { 2185 int ret = 0; 2186 2187 if (AM65_CPSW_IS_CPSW2G(cpsw) || 2188 !IS_REACHABLE(CONFIG_TI_K3_AM65_CPSW_SWITCHDEV)) 2189 return 0; 2190 2191 cpsw->am65_cpsw_netdevice_nb.notifier_call = &am65_cpsw_netdevice_event; 2192 ret = register_netdevice_notifier(&cpsw->am65_cpsw_netdevice_nb); 2193 if (ret) { 2194 dev_err(cpsw->dev, "can't register netdevice notifier\n"); 2195 return ret; 2196 } 2197 2198 ret = am65_cpsw_switchdev_register_notifiers(cpsw); 2199 if (ret) 2200 unregister_netdevice_notifier(&cpsw->am65_cpsw_netdevice_nb); 2201 2202 return ret; 2203 } 2204 2205 static void am65_cpsw_unregister_notifiers(struct am65_cpsw_common *cpsw) 2206 { 2207 if (AM65_CPSW_IS_CPSW2G(cpsw) || 2208 !IS_REACHABLE(CONFIG_TI_K3_AM65_CPSW_SWITCHDEV)) 2209 return; 2210 2211 am65_cpsw_switchdev_unregister_notifiers(cpsw); 2212 unregister_netdevice_notifier(&cpsw->am65_cpsw_netdevice_nb); 2213 } 2214 2215 static const struct devlink_ops am65_cpsw_devlink_ops = {}; 2216 2217 static void am65_cpsw_init_stp_ale_entry(struct am65_cpsw_common *cpsw) 2218 { 2219 cpsw_ale_add_mcast(cpsw->ale, eth_stp_addr, ALE_PORT_HOST, ALE_SUPER, 0, 2220 ALE_MCAST_BLOCK_LEARN_FWD); 2221 } 2222 2223 static void am65_cpsw_init_host_port_switch(struct am65_cpsw_common *common) 2224 { 2225 struct am65_cpsw_host *host = am65_common_get_host(common); 2226 2227 writel(common->default_vlan, host->port_base + AM65_CPSW_PORT_VLAN_REG_OFFSET); 2228 2229 am65_cpsw_init_stp_ale_entry(common); 2230 2231 cpsw_ale_control_set(common->ale, HOST_PORT_NUM, ALE_P0_UNI_FLOOD, 1); 2232 dev_dbg(common->dev, "Set P0_UNI_FLOOD\n"); 2233 cpsw_ale_control_set(common->ale, HOST_PORT_NUM, ALE_PORT_NOLEARN, 0); 2234 } 2235 2236 static void am65_cpsw_init_host_port_emac(struct am65_cpsw_common *common) 2237 { 2238 struct am65_cpsw_host *host = am65_common_get_host(common); 2239 2240 writel(0, host->port_base + AM65_CPSW_PORT_VLAN_REG_OFFSET); 2241 2242 cpsw_ale_control_set(common->ale, HOST_PORT_NUM, ALE_P0_UNI_FLOOD, 0); 2243 dev_dbg(common->dev, "unset P0_UNI_FLOOD\n"); 2244 2245 /* learning make no sense in multi-mac mode */ 2246 cpsw_ale_control_set(common->ale, HOST_PORT_NUM, ALE_PORT_NOLEARN, 1); 2247 } 2248 2249 static int am65_cpsw_dl_switch_mode_get(struct devlink *dl, u32 id, 2250 struct devlink_param_gset_ctx *ctx) 2251 { 2252 struct am65_cpsw_devlink *dl_priv = devlink_priv(dl); 2253 struct am65_cpsw_common *common = dl_priv->common; 2254 2255 dev_dbg(common->dev, "%s id:%u\n", __func__, id); 2256 2257 if (id != AM65_CPSW_DL_PARAM_SWITCH_MODE) 2258 return -EOPNOTSUPP; 2259 2260 ctx->val.vbool = !common->is_emac_mode; 2261 2262 return 0; 2263 } 2264 2265 static void am65_cpsw_init_port_emac_ale(struct am65_cpsw_port *port) 2266 { 2267 struct am65_cpsw_slave_data *slave = &port->slave; 2268 struct am65_cpsw_common *common = port->common; 2269 u32 port_mask; 2270 2271 writel(slave->port_vlan, port->port_base + AM65_CPSW_PORT_VLAN_REG_OFFSET); 2272 2273 if (slave->mac_only) 2274 /* enable mac-only mode on port */ 2275 cpsw_ale_control_set(common->ale, port->port_id, 2276 ALE_PORT_MACONLY, 1); 2277 2278 cpsw_ale_control_set(common->ale, port->port_id, ALE_PORT_NOLEARN, 1); 2279 2280 port_mask = BIT(port->port_id) | ALE_PORT_HOST; 2281 2282 cpsw_ale_add_ucast(common->ale, port->ndev->dev_addr, 2283 HOST_PORT_NUM, ALE_SECURE, slave->port_vlan); 2284 cpsw_ale_add_mcast(common->ale, port->ndev->broadcast, 2285 port_mask, ALE_VLAN, slave->port_vlan, ALE_MCAST_FWD_2); 2286 } 2287 2288 static void am65_cpsw_init_port_switch_ale(struct am65_cpsw_port *port) 2289 { 2290 struct am65_cpsw_slave_data *slave = &port->slave; 2291 struct am65_cpsw_common *cpsw = port->common; 2292 u32 port_mask; 2293 2294 cpsw_ale_control_set(cpsw->ale, port->port_id, 2295 ALE_PORT_NOLEARN, 0); 2296 2297 cpsw_ale_add_ucast(cpsw->ale, port->ndev->dev_addr, 2298 HOST_PORT_NUM, ALE_SECURE | ALE_BLOCKED | ALE_VLAN, 2299 slave->port_vlan); 2300 2301 port_mask = BIT(port->port_id) | ALE_PORT_HOST; 2302 2303 cpsw_ale_add_mcast(cpsw->ale, port->ndev->broadcast, 2304 port_mask, ALE_VLAN, slave->port_vlan, 2305 ALE_MCAST_FWD_2); 2306 2307 writel(slave->port_vlan, port->port_base + AM65_CPSW_PORT_VLAN_REG_OFFSET); 2308 2309 cpsw_ale_control_set(cpsw->ale, port->port_id, 2310 ALE_PORT_MACONLY, 0); 2311 } 2312 2313 static int am65_cpsw_dl_switch_mode_set(struct devlink *dl, u32 id, 2314 struct devlink_param_gset_ctx *ctx) 2315 { 2316 struct am65_cpsw_devlink *dl_priv = devlink_priv(dl); 2317 struct am65_cpsw_common *cpsw = dl_priv->common; 2318 bool switch_en = ctx->val.vbool; 2319 bool if_running = false; 2320 int i; 2321 2322 dev_dbg(cpsw->dev, "%s id:%u\n", __func__, id); 2323 2324 if (id != AM65_CPSW_DL_PARAM_SWITCH_MODE) 2325 return -EOPNOTSUPP; 2326 2327 if (switch_en == !cpsw->is_emac_mode) 2328 return 0; 2329 2330 if (!switch_en && cpsw->br_members) { 2331 dev_err(cpsw->dev, "Remove ports from bridge before disabling switch mode\n"); 2332 return -EINVAL; 2333 } 2334 2335 rtnl_lock(); 2336 2337 cpsw->is_emac_mode = !switch_en; 2338 2339 for (i = 0; i < cpsw->port_num; i++) { 2340 struct net_device *sl_ndev = cpsw->ports[i].ndev; 2341 2342 if (!sl_ndev || !netif_running(sl_ndev)) 2343 continue; 2344 2345 if_running = true; 2346 } 2347 2348 if (!if_running) { 2349 /* all ndevs are down */ 2350 for (i = 0; i < cpsw->port_num; i++) { 2351 struct net_device *sl_ndev = cpsw->ports[i].ndev; 2352 struct am65_cpsw_slave_data *slave; 2353 2354 if (!sl_ndev) 2355 continue; 2356 2357 slave = am65_ndev_to_slave(sl_ndev); 2358 if (switch_en) 2359 slave->port_vlan = cpsw->default_vlan; 2360 else 2361 slave->port_vlan = 0; 2362 } 2363 2364 goto exit; 2365 } 2366 2367 cpsw_ale_control_set(cpsw->ale, 0, ALE_BYPASS, 1); 2368 /* clean up ALE table */ 2369 cpsw_ale_control_set(cpsw->ale, HOST_PORT_NUM, ALE_CLEAR, 1); 2370 cpsw_ale_control_get(cpsw->ale, HOST_PORT_NUM, ALE_AGEOUT); 2371 2372 if (switch_en) { 2373 dev_info(cpsw->dev, "Enable switch mode\n"); 2374 2375 am65_cpsw_init_host_port_switch(cpsw); 2376 2377 for (i = 0; i < cpsw->port_num; i++) { 2378 struct net_device *sl_ndev = cpsw->ports[i].ndev; 2379 struct am65_cpsw_slave_data *slave; 2380 struct am65_cpsw_port *port; 2381 2382 if (!sl_ndev) 2383 continue; 2384 2385 port = am65_ndev_to_port(sl_ndev); 2386 slave = am65_ndev_to_slave(sl_ndev); 2387 slave->port_vlan = cpsw->default_vlan; 2388 2389 if (netif_running(sl_ndev)) 2390 am65_cpsw_init_port_switch_ale(port); 2391 } 2392 2393 } else { 2394 dev_info(cpsw->dev, "Disable switch mode\n"); 2395 2396 am65_cpsw_init_host_port_emac(cpsw); 2397 2398 for (i = 0; i < cpsw->port_num; i++) { 2399 struct net_device *sl_ndev = cpsw->ports[i].ndev; 2400 struct am65_cpsw_port *port; 2401 2402 if (!sl_ndev) 2403 continue; 2404 2405 port = am65_ndev_to_port(sl_ndev); 2406 port->slave.port_vlan = 0; 2407 if (netif_running(sl_ndev)) 2408 am65_cpsw_init_port_emac_ale(port); 2409 } 2410 } 2411 cpsw_ale_control_set(cpsw->ale, HOST_PORT_NUM, ALE_BYPASS, 0); 2412 exit: 2413 rtnl_unlock(); 2414 2415 return 0; 2416 } 2417 2418 static const struct devlink_param am65_cpsw_devlink_params[] = { 2419 DEVLINK_PARAM_DRIVER(AM65_CPSW_DL_PARAM_SWITCH_MODE, "switch_mode", 2420 DEVLINK_PARAM_TYPE_BOOL, 2421 BIT(DEVLINK_PARAM_CMODE_RUNTIME), 2422 am65_cpsw_dl_switch_mode_get, 2423 am65_cpsw_dl_switch_mode_set, NULL), 2424 }; 2425 2426 static int am65_cpsw_nuss_register_devlink(struct am65_cpsw_common *common) 2427 { 2428 struct devlink_port_attrs attrs = {}; 2429 struct am65_cpsw_devlink *dl_priv; 2430 struct device *dev = common->dev; 2431 struct devlink_port *dl_port; 2432 struct am65_cpsw_port *port; 2433 int ret = 0; 2434 int i; 2435 2436 common->devlink = 2437 devlink_alloc(&am65_cpsw_devlink_ops, sizeof(*dl_priv), dev); 2438 if (!common->devlink) 2439 return -ENOMEM; 2440 2441 dl_priv = devlink_priv(common->devlink); 2442 dl_priv->common = common; 2443 2444 /* Provide devlink hook to switch mode when multiple external ports 2445 * are present NUSS switchdev driver is enabled. 2446 */ 2447 if (!AM65_CPSW_IS_CPSW2G(common) && 2448 IS_ENABLED(CONFIG_TI_K3_AM65_CPSW_SWITCHDEV)) { 2449 ret = devlink_params_register(common->devlink, 2450 am65_cpsw_devlink_params, 2451 ARRAY_SIZE(am65_cpsw_devlink_params)); 2452 if (ret) { 2453 dev_err(dev, "devlink params reg fail ret:%d\n", ret); 2454 goto dl_unreg; 2455 } 2456 } 2457 2458 for (i = 1; i <= common->port_num; i++) { 2459 port = am65_common_get_port(common, i); 2460 dl_port = &port->devlink_port; 2461 2462 attrs.flavour = DEVLINK_PORT_FLAVOUR_PHYSICAL; 2463 attrs.phys.port_number = port->port_id; 2464 attrs.switch_id.id_len = sizeof(resource_size_t); 2465 memcpy(attrs.switch_id.id, common->switch_id, attrs.switch_id.id_len); 2466 devlink_port_attrs_set(dl_port, &attrs); 2467 2468 ret = devlink_port_register(common->devlink, dl_port, port->port_id); 2469 if (ret) { 2470 dev_err(dev, "devlink_port reg fail for port %d, ret:%d\n", 2471 port->port_id, ret); 2472 goto dl_port_unreg; 2473 } 2474 devlink_port_type_eth_set(dl_port, port->ndev); 2475 } 2476 devlink_register(common->devlink); 2477 return ret; 2478 2479 dl_port_unreg: 2480 for (i = i - 1; i >= 1; i--) { 2481 port = am65_common_get_port(common, i); 2482 dl_port = &port->devlink_port; 2483 2484 devlink_port_unregister(dl_port); 2485 } 2486 dl_unreg: 2487 devlink_free(common->devlink); 2488 return ret; 2489 } 2490 2491 static void am65_cpsw_unregister_devlink(struct am65_cpsw_common *common) 2492 { 2493 struct devlink_port *dl_port; 2494 struct am65_cpsw_port *port; 2495 int i; 2496 2497 devlink_unregister(common->devlink); 2498 2499 for (i = 1; i <= common->port_num; i++) { 2500 port = am65_common_get_port(common, i); 2501 dl_port = &port->devlink_port; 2502 2503 devlink_port_unregister(dl_port); 2504 } 2505 2506 if (!AM65_CPSW_IS_CPSW2G(common) && 2507 IS_ENABLED(CONFIG_TI_K3_AM65_CPSW_SWITCHDEV)) 2508 devlink_params_unregister(common->devlink, 2509 am65_cpsw_devlink_params, 2510 ARRAY_SIZE(am65_cpsw_devlink_params)); 2511 2512 devlink_free(common->devlink); 2513 } 2514 2515 static int am65_cpsw_nuss_register_ndevs(struct am65_cpsw_common *common) 2516 { 2517 struct device *dev = common->dev; 2518 struct am65_cpsw_port *port; 2519 int ret = 0, i; 2520 2521 ret = am65_cpsw_nuss_ndev_add_tx_napi(common); 2522 if (ret) 2523 return ret; 2524 2525 ret = devm_request_irq(dev, common->rx_chns.irq, 2526 am65_cpsw_nuss_rx_irq, 2527 IRQF_TRIGGER_HIGH, dev_name(dev), common); 2528 if (ret) { 2529 dev_err(dev, "failure requesting rx irq %u, %d\n", 2530 common->rx_chns.irq, ret); 2531 return ret; 2532 } 2533 2534 for (i = 0; i < common->port_num; i++) { 2535 port = &common->ports[i]; 2536 2537 if (!port->ndev) 2538 continue; 2539 2540 ret = register_netdev(port->ndev); 2541 if (ret) { 2542 dev_err(dev, "error registering slave net device%i %d\n", 2543 i, ret); 2544 goto err_cleanup_ndev; 2545 } 2546 } 2547 2548 ret = am65_cpsw_register_notifiers(common); 2549 if (ret) 2550 goto err_cleanup_ndev; 2551 2552 ret = am65_cpsw_nuss_register_devlink(common); 2553 if (ret) 2554 goto clean_unregister_notifiers; 2555 2556 /* can't auto unregister ndev using devm_add_action() due to 2557 * devres release sequence in DD core for DMA 2558 */ 2559 2560 return 0; 2561 clean_unregister_notifiers: 2562 am65_cpsw_unregister_notifiers(common); 2563 err_cleanup_ndev: 2564 am65_cpsw_nuss_cleanup_ndev(common); 2565 2566 return ret; 2567 } 2568 2569 int am65_cpsw_nuss_update_tx_chns(struct am65_cpsw_common *common, int num_tx) 2570 { 2571 int ret; 2572 2573 common->tx_ch_num = num_tx; 2574 ret = am65_cpsw_nuss_init_tx_chns(common); 2575 if (ret) 2576 return ret; 2577 2578 return am65_cpsw_nuss_ndev_add_tx_napi(common); 2579 } 2580 2581 struct am65_cpsw_soc_pdata { 2582 u32 quirks_dis; 2583 }; 2584 2585 static const struct am65_cpsw_soc_pdata am65x_soc_sr2_0 = { 2586 .quirks_dis = AM65_CPSW_QUIRK_I2027_NO_TX_CSUM, 2587 }; 2588 2589 static const struct soc_device_attribute am65_cpsw_socinfo[] = { 2590 { .family = "AM65X", 2591 .revision = "SR2.0", 2592 .data = &am65x_soc_sr2_0 2593 }, 2594 {/* sentinel */} 2595 }; 2596 2597 static const struct am65_cpsw_pdata am65x_sr1_0 = { 2598 .quirks = AM65_CPSW_QUIRK_I2027_NO_TX_CSUM, 2599 .ale_dev_id = "am65x-cpsw2g", 2600 .fdqring_mode = K3_RINGACC_RING_MODE_MESSAGE, 2601 }; 2602 2603 static const struct am65_cpsw_pdata j721e_pdata = { 2604 .quirks = 0, 2605 .ale_dev_id = "am65x-cpsw2g", 2606 .fdqring_mode = K3_RINGACC_RING_MODE_MESSAGE, 2607 }; 2608 2609 static const struct am65_cpsw_pdata am64x_cpswxg_pdata = { 2610 .quirks = 0, 2611 .ale_dev_id = "am64-cpswxg", 2612 .fdqring_mode = K3_RINGACC_RING_MODE_RING, 2613 }; 2614 2615 static const struct of_device_id am65_cpsw_nuss_of_mtable[] = { 2616 { .compatible = "ti,am654-cpsw-nuss", .data = &am65x_sr1_0}, 2617 { .compatible = "ti,j721e-cpsw-nuss", .data = &j721e_pdata}, 2618 { .compatible = "ti,am642-cpsw-nuss", .data = &am64x_cpswxg_pdata}, 2619 { /* sentinel */ }, 2620 }; 2621 MODULE_DEVICE_TABLE(of, am65_cpsw_nuss_of_mtable); 2622 2623 static void am65_cpsw_nuss_apply_socinfo(struct am65_cpsw_common *common) 2624 { 2625 const struct soc_device_attribute *soc; 2626 2627 soc = soc_device_match(am65_cpsw_socinfo); 2628 if (soc && soc->data) { 2629 const struct am65_cpsw_soc_pdata *socdata = soc->data; 2630 2631 /* disable quirks */ 2632 common->pdata.quirks &= ~socdata->quirks_dis; 2633 } 2634 } 2635 2636 static int am65_cpsw_nuss_probe(struct platform_device *pdev) 2637 { 2638 struct cpsw_ale_params ale_params = { 0 }; 2639 const struct of_device_id *of_id; 2640 struct device *dev = &pdev->dev; 2641 struct am65_cpsw_common *common; 2642 struct device_node *node; 2643 struct resource *res; 2644 struct clk *clk; 2645 u64 id_temp; 2646 int ret, i; 2647 2648 common = devm_kzalloc(dev, sizeof(struct am65_cpsw_common), GFP_KERNEL); 2649 if (!common) 2650 return -ENOMEM; 2651 common->dev = dev; 2652 2653 of_id = of_match_device(am65_cpsw_nuss_of_mtable, dev); 2654 if (!of_id) 2655 return -EINVAL; 2656 common->pdata = *(const struct am65_cpsw_pdata *)of_id->data; 2657 2658 am65_cpsw_nuss_apply_socinfo(common); 2659 2660 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cpsw_nuss"); 2661 common->ss_base = devm_ioremap_resource(&pdev->dev, res); 2662 if (IS_ERR(common->ss_base)) 2663 return PTR_ERR(common->ss_base); 2664 common->cpsw_base = common->ss_base + AM65_CPSW_CPSW_NU_BASE; 2665 /* Use device's physical base address as switch id */ 2666 id_temp = cpu_to_be64(res->start); 2667 memcpy(common->switch_id, &id_temp, sizeof(res->start)); 2668 2669 node = of_get_child_by_name(dev->of_node, "ethernet-ports"); 2670 if (!node) 2671 return -ENOENT; 2672 common->port_num = of_get_child_count(node); 2673 if (common->port_num < 1 || common->port_num > AM65_CPSW_MAX_PORTS) 2674 return -ENOENT; 2675 of_node_put(node); 2676 2677 common->rx_flow_id_base = -1; 2678 init_completion(&common->tdown_complete); 2679 common->tx_ch_num = 1; 2680 common->pf_p0_rx_ptype_rrobin = false; 2681 common->default_vlan = 1; 2682 2683 common->ports = devm_kcalloc(dev, common->port_num, 2684 sizeof(*common->ports), 2685 GFP_KERNEL); 2686 if (!common->ports) 2687 return -ENOMEM; 2688 2689 clk = devm_clk_get(dev, "fck"); 2690 if (IS_ERR(clk)) 2691 return dev_err_probe(dev, PTR_ERR(clk), "getting fck clock\n"); 2692 common->bus_freq = clk_get_rate(clk); 2693 2694 pm_runtime_enable(dev); 2695 ret = pm_runtime_get_sync(dev); 2696 if (ret < 0) { 2697 pm_runtime_put_noidle(dev); 2698 pm_runtime_disable(dev); 2699 return ret; 2700 } 2701 2702 node = of_get_child_by_name(dev->of_node, "mdio"); 2703 if (!node) { 2704 dev_warn(dev, "MDIO node not found\n"); 2705 } else if (of_device_is_available(node)) { 2706 struct platform_device *mdio_pdev; 2707 2708 mdio_pdev = of_platform_device_create(node, NULL, dev); 2709 if (!mdio_pdev) { 2710 ret = -ENODEV; 2711 goto err_pm_clear; 2712 } 2713 2714 common->mdio_dev = &mdio_pdev->dev; 2715 } 2716 of_node_put(node); 2717 2718 am65_cpsw_nuss_get_ver(common); 2719 2720 /* init tx channels */ 2721 ret = am65_cpsw_nuss_init_tx_chns(common); 2722 if (ret) 2723 goto err_of_clear; 2724 ret = am65_cpsw_nuss_init_rx_chns(common); 2725 if (ret) 2726 goto err_of_clear; 2727 2728 ret = am65_cpsw_nuss_init_host_p(common); 2729 if (ret) 2730 goto err_of_clear; 2731 2732 ret = am65_cpsw_nuss_init_slave_ports(common); 2733 if (ret) 2734 goto err_of_clear; 2735 2736 /* init common data */ 2737 ale_params.dev = dev; 2738 ale_params.ale_ageout = AM65_CPSW_ALE_AGEOUT_DEFAULT; 2739 ale_params.ale_ports = common->port_num + 1; 2740 ale_params.ale_regs = common->cpsw_base + AM65_CPSW_NU_ALE_BASE; 2741 ale_params.dev_id = common->pdata.ale_dev_id; 2742 ale_params.bus_freq = common->bus_freq; 2743 2744 common->ale = cpsw_ale_create(&ale_params); 2745 if (IS_ERR(common->ale)) { 2746 dev_err(dev, "error initializing ale engine\n"); 2747 ret = PTR_ERR(common->ale); 2748 goto err_of_clear; 2749 } 2750 2751 ret = am65_cpsw_init_cpts(common); 2752 if (ret) 2753 goto err_of_clear; 2754 2755 /* init ports */ 2756 for (i = 0; i < common->port_num; i++) 2757 am65_cpsw_nuss_slave_disable_unused(&common->ports[i]); 2758 2759 dev_set_drvdata(dev, common); 2760 2761 common->is_emac_mode = true; 2762 2763 ret = am65_cpsw_nuss_init_ndevs(common); 2764 if (ret) 2765 goto err_free_phylink; 2766 2767 ret = am65_cpsw_nuss_register_ndevs(common); 2768 if (ret) 2769 goto err_free_phylink; 2770 2771 pm_runtime_put(dev); 2772 return 0; 2773 2774 err_free_phylink: 2775 am65_cpsw_nuss_phylink_cleanup(common); 2776 err_of_clear: 2777 of_platform_device_destroy(common->mdio_dev, NULL); 2778 err_pm_clear: 2779 pm_runtime_put_sync(dev); 2780 pm_runtime_disable(dev); 2781 return ret; 2782 } 2783 2784 static int am65_cpsw_nuss_remove(struct platform_device *pdev) 2785 { 2786 struct device *dev = &pdev->dev; 2787 struct am65_cpsw_common *common; 2788 int ret; 2789 2790 common = dev_get_drvdata(dev); 2791 2792 ret = pm_runtime_get_sync(&pdev->dev); 2793 if (ret < 0) { 2794 pm_runtime_put_noidle(&pdev->dev); 2795 return ret; 2796 } 2797 2798 am65_cpsw_nuss_phylink_cleanup(common); 2799 am65_cpsw_unregister_devlink(common); 2800 am65_cpsw_unregister_notifiers(common); 2801 2802 /* must unregister ndevs here because DD release_driver routine calls 2803 * dma_deconfigure(dev) before devres_release_all(dev) 2804 */ 2805 am65_cpsw_nuss_cleanup_ndev(common); 2806 2807 of_platform_device_destroy(common->mdio_dev, NULL); 2808 2809 pm_runtime_put_sync(&pdev->dev); 2810 pm_runtime_disable(&pdev->dev); 2811 return 0; 2812 } 2813 2814 static struct platform_driver am65_cpsw_nuss_driver = { 2815 .driver = { 2816 .name = AM65_CPSW_DRV_NAME, 2817 .of_match_table = am65_cpsw_nuss_of_mtable, 2818 }, 2819 .probe = am65_cpsw_nuss_probe, 2820 .remove = am65_cpsw_nuss_remove, 2821 }; 2822 2823 module_platform_driver(am65_cpsw_nuss_driver); 2824 2825 MODULE_LICENSE("GPL v2"); 2826 MODULE_AUTHOR("Grygorii Strashko <grygorii.strashko@ti.com>"); 2827 MODULE_DESCRIPTION("TI AM65 CPSW Ethernet driver"); 2828