1 // SPDX-License-Identifier: GPL-2.0
2 /* Texas Instruments K3 AM65 Ethernet Switch SubSystem Driver
3  *
4  * Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
5  *
6  */
7 
8 #include <linux/clk.h>
9 #include <linux/etherdevice.h>
10 #include <linux/if_vlan.h>
11 #include <linux/interrupt.h>
12 #include <linux/irqdomain.h>
13 #include <linux/kernel.h>
14 #include <linux/kmemleak.h>
15 #include <linux/module.h>
16 #include <linux/netdevice.h>
17 #include <linux/net_tstamp.h>
18 #include <linux/of.h>
19 #include <linux/of_mdio.h>
20 #include <linux/of_net.h>
21 #include <linux/of_device.h>
22 #include <linux/phylink.h>
23 #include <linux/phy/phy.h>
24 #include <linux/platform_device.h>
25 #include <linux/pm_runtime.h>
26 #include <linux/regmap.h>
27 #include <linux/rtnetlink.h>
28 #include <linux/mfd/syscon.h>
29 #include <linux/sys_soc.h>
30 #include <linux/dma/ti-cppi5.h>
31 #include <linux/dma/k3-udma-glue.h>
32 #include <net/switchdev.h>
33 
34 #include "cpsw_ale.h"
35 #include "cpsw_sl.h"
36 #include "am65-cpsw-nuss.h"
37 #include "am65-cpsw-switchdev.h"
38 #include "k3-cppi-desc-pool.h"
39 #include "am65-cpts.h"
40 
41 #define AM65_CPSW_SS_BASE	0x0
42 #define AM65_CPSW_SGMII_BASE	0x100
43 #define AM65_CPSW_XGMII_BASE	0x2100
44 #define AM65_CPSW_CPSW_NU_BASE	0x20000
45 #define AM65_CPSW_NU_PORTS_BASE	0x1000
46 #define AM65_CPSW_NU_FRAM_BASE	0x12000
47 #define AM65_CPSW_NU_STATS_BASE	0x1a000
48 #define AM65_CPSW_NU_ALE_BASE	0x1e000
49 #define AM65_CPSW_NU_CPTS_BASE	0x1d000
50 
51 #define AM65_CPSW_NU_PORTS_OFFSET	0x1000
52 #define AM65_CPSW_NU_STATS_PORT_OFFSET	0x200
53 #define AM65_CPSW_NU_FRAM_PORT_OFFSET	0x200
54 
55 #define AM65_CPSW_MAX_PORTS	8
56 
57 #define AM65_CPSW_MIN_PACKET_SIZE	VLAN_ETH_ZLEN
58 #define AM65_CPSW_MAX_PACKET_SIZE	(VLAN_ETH_FRAME_LEN + ETH_FCS_LEN)
59 
60 #define AM65_CPSW_REG_CTL		0x004
61 #define AM65_CPSW_REG_STAT_PORT_EN	0x014
62 #define AM65_CPSW_REG_PTYPE		0x018
63 
64 #define AM65_CPSW_P0_REG_CTL			0x004
65 #define AM65_CPSW_PORT0_REG_FLOW_ID_OFFSET	0x008
66 
67 #define AM65_CPSW_PORT_REG_PRI_CTL		0x01c
68 #define AM65_CPSW_PORT_REG_RX_PRI_MAP		0x020
69 #define AM65_CPSW_PORT_REG_RX_MAXLEN		0x024
70 
71 #define AM65_CPSW_PORTN_REG_SA_L		0x308
72 #define AM65_CPSW_PORTN_REG_SA_H		0x30c
73 #define AM65_CPSW_PORTN_REG_TS_CTL              0x310
74 #define AM65_CPSW_PORTN_REG_TS_SEQ_LTYPE_REG	0x314
75 #define AM65_CPSW_PORTN_REG_TS_VLAN_LTYPE_REG	0x318
76 #define AM65_CPSW_PORTN_REG_TS_CTL_LTYPE2       0x31C
77 
78 #define AM65_CPSW_SGMII_CONTROL_REG		0x010
79 #define AM65_CPSW_SGMII_MR_ADV_ABILITY_REG	0x018
80 #define AM65_CPSW_SGMII_CONTROL_MR_AN_ENABLE	BIT(0)
81 
82 #define AM65_CPSW_CTL_VLAN_AWARE		BIT(1)
83 #define AM65_CPSW_CTL_P0_ENABLE			BIT(2)
84 #define AM65_CPSW_CTL_P0_TX_CRC_REMOVE		BIT(13)
85 #define AM65_CPSW_CTL_P0_RX_PAD			BIT(14)
86 
87 /* AM65_CPSW_P0_REG_CTL */
88 #define AM65_CPSW_P0_REG_CTL_RX_CHECKSUM_EN	BIT(0)
89 #define AM65_CPSW_P0_REG_CTL_RX_REMAP_VLAN	BIT(16)
90 
91 /* AM65_CPSW_PORT_REG_PRI_CTL */
92 #define AM65_CPSW_PORT_REG_PRI_CTL_RX_PTYPE_RROBIN	BIT(8)
93 
94 /* AM65_CPSW_PN_TS_CTL register fields */
95 #define AM65_CPSW_PN_TS_CTL_TX_ANX_F_EN		BIT(4)
96 #define AM65_CPSW_PN_TS_CTL_TX_VLAN_LT1_EN	BIT(5)
97 #define AM65_CPSW_PN_TS_CTL_TX_VLAN_LT2_EN	BIT(6)
98 #define AM65_CPSW_PN_TS_CTL_TX_ANX_D_EN		BIT(7)
99 #define AM65_CPSW_PN_TS_CTL_TX_ANX_E_EN		BIT(10)
100 #define AM65_CPSW_PN_TS_CTL_TX_HOST_TS_EN	BIT(11)
101 #define AM65_CPSW_PN_TS_CTL_MSG_TYPE_EN_SHIFT	16
102 
103 /* AM65_CPSW_PORTN_REG_TS_SEQ_LTYPE_REG register fields */
104 #define AM65_CPSW_PN_TS_SEQ_ID_OFFSET_SHIFT	16
105 
106 /* AM65_CPSW_PORTN_REG_TS_CTL_LTYPE2 */
107 #define AM65_CPSW_PN_TS_CTL_LTYPE2_TS_107	BIT(16)
108 #define AM65_CPSW_PN_TS_CTL_LTYPE2_TS_129	BIT(17)
109 #define AM65_CPSW_PN_TS_CTL_LTYPE2_TS_130	BIT(18)
110 #define AM65_CPSW_PN_TS_CTL_LTYPE2_TS_131	BIT(19)
111 #define AM65_CPSW_PN_TS_CTL_LTYPE2_TS_132	BIT(20)
112 #define AM65_CPSW_PN_TS_CTL_LTYPE2_TS_319	BIT(21)
113 #define AM65_CPSW_PN_TS_CTL_LTYPE2_TS_320	BIT(22)
114 #define AM65_CPSW_PN_TS_CTL_LTYPE2_TS_TTL_NONZERO BIT(23)
115 
116 /* The PTP event messages - Sync, Delay_Req, Pdelay_Req, and Pdelay_Resp. */
117 #define AM65_CPSW_TS_EVENT_MSG_TYPE_BITS (BIT(0) | BIT(1) | BIT(2) | BIT(3))
118 
119 #define AM65_CPSW_TS_SEQ_ID_OFFSET (0x1e)
120 
121 #define AM65_CPSW_TS_TX_ANX_ALL_EN		\
122 	(AM65_CPSW_PN_TS_CTL_TX_ANX_D_EN |	\
123 	 AM65_CPSW_PN_TS_CTL_TX_ANX_E_EN |	\
124 	 AM65_CPSW_PN_TS_CTL_TX_ANX_F_EN)
125 
126 #define AM65_CPSW_ALE_AGEOUT_DEFAULT	30
127 /* Number of TX/RX descriptors */
128 #define AM65_CPSW_MAX_TX_DESC	500
129 #define AM65_CPSW_MAX_RX_DESC	500
130 
131 #define AM65_CPSW_NAV_PS_DATA_SIZE 16
132 #define AM65_CPSW_NAV_SW_DATA_SIZE 16
133 
134 #define AM65_CPSW_DEBUG	(NETIF_MSG_HW | NETIF_MSG_DRV | NETIF_MSG_LINK | \
135 			 NETIF_MSG_IFUP	| NETIF_MSG_PROBE | NETIF_MSG_IFDOWN | \
136 			 NETIF_MSG_RX_ERR | NETIF_MSG_TX_ERR)
137 
138 static void am65_cpsw_port_set_sl_mac(struct am65_cpsw_port *slave,
139 				      const u8 *dev_addr)
140 {
141 	u32 mac_hi = (dev_addr[0] << 0) | (dev_addr[1] << 8) |
142 		     (dev_addr[2] << 16) | (dev_addr[3] << 24);
143 	u32 mac_lo = (dev_addr[4] << 0) | (dev_addr[5] << 8);
144 
145 	writel(mac_hi, slave->port_base + AM65_CPSW_PORTN_REG_SA_H);
146 	writel(mac_lo, slave->port_base + AM65_CPSW_PORTN_REG_SA_L);
147 }
148 
149 static void am65_cpsw_sl_ctl_reset(struct am65_cpsw_port *port)
150 {
151 	cpsw_sl_reset(port->slave.mac_sl, 100);
152 	/* Max length register has to be restored after MAC SL reset */
153 	writel(AM65_CPSW_MAX_PACKET_SIZE,
154 	       port->port_base + AM65_CPSW_PORT_REG_RX_MAXLEN);
155 }
156 
157 static void am65_cpsw_nuss_get_ver(struct am65_cpsw_common *common)
158 {
159 	common->nuss_ver = readl(common->ss_base);
160 	common->cpsw_ver = readl(common->cpsw_base);
161 	dev_info(common->dev,
162 		 "initializing am65 cpsw nuss version 0x%08X, cpsw version 0x%08X Ports: %u quirks:%08x\n",
163 		common->nuss_ver,
164 		common->cpsw_ver,
165 		common->port_num + 1,
166 		common->pdata.quirks);
167 }
168 
169 static int am65_cpsw_nuss_ndo_slave_add_vid(struct net_device *ndev,
170 					    __be16 proto, u16 vid)
171 {
172 	struct am65_cpsw_common *common = am65_ndev_to_common(ndev);
173 	struct am65_cpsw_port *port = am65_ndev_to_port(ndev);
174 	u32 port_mask, unreg_mcast = 0;
175 	int ret;
176 
177 	if (!common->is_emac_mode)
178 		return 0;
179 
180 	if (!netif_running(ndev) || !vid)
181 		return 0;
182 
183 	ret = pm_runtime_resume_and_get(common->dev);
184 	if (ret < 0)
185 		return ret;
186 
187 	port_mask = BIT(port->port_id) | ALE_PORT_HOST;
188 	if (!vid)
189 		unreg_mcast = port_mask;
190 	dev_info(common->dev, "Adding vlan %d to vlan filter\n", vid);
191 	ret = cpsw_ale_vlan_add_modify(common->ale, vid, port_mask,
192 				       unreg_mcast, port_mask, 0);
193 
194 	pm_runtime_put(common->dev);
195 	return ret;
196 }
197 
198 static int am65_cpsw_nuss_ndo_slave_kill_vid(struct net_device *ndev,
199 					     __be16 proto, u16 vid)
200 {
201 	struct am65_cpsw_common *common = am65_ndev_to_common(ndev);
202 	struct am65_cpsw_port *port = am65_ndev_to_port(ndev);
203 	int ret;
204 
205 	if (!common->is_emac_mode)
206 		return 0;
207 
208 	if (!netif_running(ndev) || !vid)
209 		return 0;
210 
211 	ret = pm_runtime_resume_and_get(common->dev);
212 	if (ret < 0)
213 		return ret;
214 
215 	dev_info(common->dev, "Removing vlan %d from vlan filter\n", vid);
216 	ret = cpsw_ale_del_vlan(common->ale, vid,
217 				BIT(port->port_id) | ALE_PORT_HOST);
218 
219 	pm_runtime_put(common->dev);
220 	return ret;
221 }
222 
223 static void am65_cpsw_slave_set_promisc(struct am65_cpsw_port *port,
224 					bool promisc)
225 {
226 	struct am65_cpsw_common *common = port->common;
227 
228 	if (promisc && !common->is_emac_mode) {
229 		dev_dbg(common->dev, "promisc mode requested in switch mode");
230 		return;
231 	}
232 
233 	if (promisc) {
234 		/* Enable promiscuous mode */
235 		cpsw_ale_control_set(common->ale, port->port_id,
236 				     ALE_PORT_MACONLY_CAF, 1);
237 		dev_dbg(common->dev, "promisc enabled\n");
238 	} else {
239 		/* Disable promiscuous mode */
240 		cpsw_ale_control_set(common->ale, port->port_id,
241 				     ALE_PORT_MACONLY_CAF, 0);
242 		dev_dbg(common->dev, "promisc disabled\n");
243 	}
244 }
245 
246 static void am65_cpsw_nuss_ndo_slave_set_rx_mode(struct net_device *ndev)
247 {
248 	struct am65_cpsw_common *common = am65_ndev_to_common(ndev);
249 	struct am65_cpsw_port *port = am65_ndev_to_port(ndev);
250 	u32 port_mask;
251 	bool promisc;
252 
253 	promisc = !!(ndev->flags & IFF_PROMISC);
254 	am65_cpsw_slave_set_promisc(port, promisc);
255 
256 	if (promisc)
257 		return;
258 
259 	/* Restore allmulti on vlans if necessary */
260 	cpsw_ale_set_allmulti(common->ale,
261 			      ndev->flags & IFF_ALLMULTI, port->port_id);
262 
263 	port_mask = ALE_PORT_HOST;
264 	/* Clear all mcast from ALE */
265 	cpsw_ale_flush_multicast(common->ale, port_mask, -1);
266 
267 	if (!netdev_mc_empty(ndev)) {
268 		struct netdev_hw_addr *ha;
269 
270 		/* program multicast address list into ALE register */
271 		netdev_for_each_mc_addr(ha, ndev) {
272 			cpsw_ale_add_mcast(common->ale, ha->addr,
273 					   port_mask, 0, 0, 0);
274 		}
275 	}
276 }
277 
278 static void am65_cpsw_nuss_ndo_host_tx_timeout(struct net_device *ndev,
279 					       unsigned int txqueue)
280 {
281 	struct am65_cpsw_common *common = am65_ndev_to_common(ndev);
282 	struct am65_cpsw_tx_chn *tx_chn;
283 	struct netdev_queue *netif_txq;
284 	unsigned long trans_start;
285 
286 	netif_txq = netdev_get_tx_queue(ndev, txqueue);
287 	tx_chn = &common->tx_chns[txqueue];
288 	trans_start = READ_ONCE(netif_txq->trans_start);
289 
290 	netdev_err(ndev, "txq:%d DRV_XOFF:%d tmo:%u dql_avail:%d free_desc:%zu\n",
291 		   txqueue,
292 		   netif_tx_queue_stopped(netif_txq),
293 		   jiffies_to_msecs(jiffies - trans_start),
294 		   dql_avail(&netif_txq->dql),
295 		   k3_cppi_desc_pool_avail(tx_chn->desc_pool));
296 
297 	if (netif_tx_queue_stopped(netif_txq)) {
298 		/* try recover if stopped by us */
299 		txq_trans_update(netif_txq);
300 		netif_tx_wake_queue(netif_txq);
301 	}
302 }
303 
304 static int am65_cpsw_nuss_rx_push(struct am65_cpsw_common *common,
305 				  struct sk_buff *skb)
306 {
307 	struct am65_cpsw_rx_chn *rx_chn = &common->rx_chns;
308 	struct cppi5_host_desc_t *desc_rx;
309 	struct device *dev = common->dev;
310 	u32 pkt_len = skb_tailroom(skb);
311 	dma_addr_t desc_dma;
312 	dma_addr_t buf_dma;
313 	void *swdata;
314 
315 	desc_rx = k3_cppi_desc_pool_alloc(rx_chn->desc_pool);
316 	if (!desc_rx) {
317 		dev_err(dev, "Failed to allocate RXFDQ descriptor\n");
318 		return -ENOMEM;
319 	}
320 	desc_dma = k3_cppi_desc_pool_virt2dma(rx_chn->desc_pool, desc_rx);
321 
322 	buf_dma = dma_map_single(rx_chn->dma_dev, skb->data, pkt_len,
323 				 DMA_FROM_DEVICE);
324 	if (unlikely(dma_mapping_error(rx_chn->dma_dev, buf_dma))) {
325 		k3_cppi_desc_pool_free(rx_chn->desc_pool, desc_rx);
326 		dev_err(dev, "Failed to map rx skb buffer\n");
327 		return -EINVAL;
328 	}
329 
330 	cppi5_hdesc_init(desc_rx, CPPI5_INFO0_HDESC_EPIB_PRESENT,
331 			 AM65_CPSW_NAV_PS_DATA_SIZE);
332 	k3_udma_glue_rx_dma_to_cppi5_addr(rx_chn->rx_chn, &buf_dma);
333 	cppi5_hdesc_attach_buf(desc_rx, buf_dma, skb_tailroom(skb), buf_dma, skb_tailroom(skb));
334 	swdata = cppi5_hdesc_get_swdata(desc_rx);
335 	*((void **)swdata) = skb;
336 
337 	return k3_udma_glue_push_rx_chn(rx_chn->rx_chn, 0, desc_rx, desc_dma);
338 }
339 
340 void am65_cpsw_nuss_set_p0_ptype(struct am65_cpsw_common *common)
341 {
342 	struct am65_cpsw_host *host_p = am65_common_get_host(common);
343 	u32 val, pri_map;
344 
345 	/* P0 set Receive Priority Type */
346 	val = readl(host_p->port_base + AM65_CPSW_PORT_REG_PRI_CTL);
347 
348 	if (common->pf_p0_rx_ptype_rrobin) {
349 		val |= AM65_CPSW_PORT_REG_PRI_CTL_RX_PTYPE_RROBIN;
350 		/* Enet Ports fifos works in fixed priority mode only, so
351 		 * reset P0_Rx_Pri_Map so all packet will go in Enet fifo 0
352 		 */
353 		pri_map = 0x0;
354 	} else {
355 		val &= ~AM65_CPSW_PORT_REG_PRI_CTL_RX_PTYPE_RROBIN;
356 		/* restore P0_Rx_Pri_Map */
357 		pri_map = 0x76543210;
358 	}
359 
360 	writel(pri_map, host_p->port_base + AM65_CPSW_PORT_REG_RX_PRI_MAP);
361 	writel(val, host_p->port_base + AM65_CPSW_PORT_REG_PRI_CTL);
362 }
363 
364 static void am65_cpsw_init_host_port_switch(struct am65_cpsw_common *common);
365 static void am65_cpsw_init_host_port_emac(struct am65_cpsw_common *common);
366 static void am65_cpsw_init_port_switch_ale(struct am65_cpsw_port *port);
367 static void am65_cpsw_init_port_emac_ale(struct am65_cpsw_port *port);
368 
369 static int am65_cpsw_nuss_common_open(struct am65_cpsw_common *common)
370 {
371 	struct am65_cpsw_host *host_p = am65_common_get_host(common);
372 	int port_idx, i, ret;
373 	struct sk_buff *skb;
374 	u32 val, port_mask;
375 
376 	if (common->usage_count)
377 		return 0;
378 
379 	/* Control register */
380 	writel(AM65_CPSW_CTL_P0_ENABLE | AM65_CPSW_CTL_P0_TX_CRC_REMOVE |
381 	       AM65_CPSW_CTL_VLAN_AWARE | AM65_CPSW_CTL_P0_RX_PAD,
382 	       common->cpsw_base + AM65_CPSW_REG_CTL);
383 	/* Max length register */
384 	writel(AM65_CPSW_MAX_PACKET_SIZE,
385 	       host_p->port_base + AM65_CPSW_PORT_REG_RX_MAXLEN);
386 	/* set base flow_id */
387 	writel(common->rx_flow_id_base,
388 	       host_p->port_base + AM65_CPSW_PORT0_REG_FLOW_ID_OFFSET);
389 	writel(AM65_CPSW_P0_REG_CTL_RX_CHECKSUM_EN | AM65_CPSW_P0_REG_CTL_RX_REMAP_VLAN,
390 	       host_p->port_base + AM65_CPSW_P0_REG_CTL);
391 
392 	am65_cpsw_nuss_set_p0_ptype(common);
393 
394 	/* enable statistic */
395 	val = BIT(HOST_PORT_NUM);
396 	for (port_idx = 0; port_idx < common->port_num; port_idx++) {
397 		struct am65_cpsw_port *port = &common->ports[port_idx];
398 
399 		if (!port->disabled)
400 			val |=  BIT(port->port_id);
401 	}
402 	writel(val, common->cpsw_base + AM65_CPSW_REG_STAT_PORT_EN);
403 
404 	/* disable priority elevation */
405 	writel(0, common->cpsw_base + AM65_CPSW_REG_PTYPE);
406 
407 	cpsw_ale_start(common->ale);
408 
409 	/* limit to one RX flow only */
410 	cpsw_ale_control_set(common->ale, HOST_PORT_NUM,
411 			     ALE_DEFAULT_THREAD_ID, 0);
412 	cpsw_ale_control_set(common->ale, HOST_PORT_NUM,
413 			     ALE_DEFAULT_THREAD_ENABLE, 1);
414 	/* switch to vlan unaware mode */
415 	cpsw_ale_control_set(common->ale, HOST_PORT_NUM, ALE_VLAN_AWARE, 1);
416 	cpsw_ale_control_set(common->ale, HOST_PORT_NUM,
417 			     ALE_PORT_STATE, ALE_PORT_STATE_FORWARD);
418 
419 	/* default vlan cfg: create mask based on enabled ports */
420 	port_mask = GENMASK(common->port_num, 0) &
421 		    ~common->disabled_ports_mask;
422 
423 	cpsw_ale_add_vlan(common->ale, 0, port_mask,
424 			  port_mask, port_mask,
425 			  port_mask & ~ALE_PORT_HOST);
426 
427 	if (common->is_emac_mode)
428 		am65_cpsw_init_host_port_emac(common);
429 	else
430 		am65_cpsw_init_host_port_switch(common);
431 
432 	am65_cpsw_qos_tx_p0_rate_init(common);
433 
434 	for (i = 0; i < common->rx_chns.descs_num; i++) {
435 		skb = __netdev_alloc_skb_ip_align(NULL,
436 						  AM65_CPSW_MAX_PACKET_SIZE,
437 						  GFP_KERNEL);
438 		if (!skb) {
439 			dev_err(common->dev, "cannot allocate skb\n");
440 			return -ENOMEM;
441 		}
442 
443 		ret = am65_cpsw_nuss_rx_push(common, skb);
444 		if (ret < 0) {
445 			dev_err(common->dev,
446 				"cannot submit skb to channel rx, error %d\n",
447 				ret);
448 			kfree_skb(skb);
449 			return ret;
450 		}
451 		kmemleak_not_leak(skb);
452 	}
453 	k3_udma_glue_enable_rx_chn(common->rx_chns.rx_chn);
454 
455 	for (i = 0; i < common->tx_ch_num; i++) {
456 		ret = k3_udma_glue_enable_tx_chn(common->tx_chns[i].tx_chn);
457 		if (ret)
458 			return ret;
459 		napi_enable(&common->tx_chns[i].napi_tx);
460 	}
461 
462 	napi_enable(&common->napi_rx);
463 	if (common->rx_irq_disabled) {
464 		common->rx_irq_disabled = false;
465 		enable_irq(common->rx_chns.irq);
466 	}
467 
468 	dev_dbg(common->dev, "cpsw_nuss started\n");
469 	return 0;
470 }
471 
472 static void am65_cpsw_nuss_tx_cleanup(void *data, dma_addr_t desc_dma);
473 static void am65_cpsw_nuss_rx_cleanup(void *data, dma_addr_t desc_dma);
474 
475 static int am65_cpsw_nuss_common_stop(struct am65_cpsw_common *common)
476 {
477 	int i;
478 
479 	if (common->usage_count != 1)
480 		return 0;
481 
482 	cpsw_ale_control_set(common->ale, HOST_PORT_NUM,
483 			     ALE_PORT_STATE, ALE_PORT_STATE_DISABLE);
484 
485 	/* shutdown tx channels */
486 	atomic_set(&common->tdown_cnt, common->tx_ch_num);
487 	/* ensure new tdown_cnt value is visible */
488 	smp_mb__after_atomic();
489 	reinit_completion(&common->tdown_complete);
490 
491 	for (i = 0; i < common->tx_ch_num; i++)
492 		k3_udma_glue_tdown_tx_chn(common->tx_chns[i].tx_chn, false);
493 
494 	i = wait_for_completion_timeout(&common->tdown_complete,
495 					msecs_to_jiffies(1000));
496 	if (!i)
497 		dev_err(common->dev, "tx timeout\n");
498 	for (i = 0; i < common->tx_ch_num; i++)
499 		napi_disable(&common->tx_chns[i].napi_tx);
500 
501 	for (i = 0; i < common->tx_ch_num; i++) {
502 		k3_udma_glue_reset_tx_chn(common->tx_chns[i].tx_chn,
503 					  &common->tx_chns[i],
504 					  am65_cpsw_nuss_tx_cleanup);
505 		k3_udma_glue_disable_tx_chn(common->tx_chns[i].tx_chn);
506 	}
507 
508 	reinit_completion(&common->tdown_complete);
509 	k3_udma_glue_tdown_rx_chn(common->rx_chns.rx_chn, true);
510 
511 	if (common->pdata.quirks & AM64_CPSW_QUIRK_DMA_RX_TDOWN_IRQ) {
512 		i = wait_for_completion_timeout(&common->tdown_complete, msecs_to_jiffies(1000));
513 		if (!i)
514 			dev_err(common->dev, "rx teardown timeout\n");
515 	}
516 
517 	napi_disable(&common->napi_rx);
518 
519 	for (i = 0; i < AM65_CPSW_MAX_RX_FLOWS; i++)
520 		k3_udma_glue_reset_rx_chn(common->rx_chns.rx_chn, i,
521 					  &common->rx_chns,
522 					  am65_cpsw_nuss_rx_cleanup, !!i);
523 
524 	k3_udma_glue_disable_rx_chn(common->rx_chns.rx_chn);
525 
526 	cpsw_ale_stop(common->ale);
527 
528 	writel(0, common->cpsw_base + AM65_CPSW_REG_CTL);
529 	writel(0, common->cpsw_base + AM65_CPSW_REG_STAT_PORT_EN);
530 
531 	dev_dbg(common->dev, "cpsw_nuss stopped\n");
532 	return 0;
533 }
534 
535 static int am65_cpsw_nuss_ndo_slave_stop(struct net_device *ndev)
536 {
537 	struct am65_cpsw_common *common = am65_ndev_to_common(ndev);
538 	struct am65_cpsw_port *port = am65_ndev_to_port(ndev);
539 	int ret;
540 
541 	phylink_stop(port->slave.phylink);
542 
543 	netif_tx_stop_all_queues(ndev);
544 
545 	phylink_disconnect_phy(port->slave.phylink);
546 
547 	ret = am65_cpsw_nuss_common_stop(common);
548 	if (ret)
549 		return ret;
550 
551 	common->usage_count--;
552 	pm_runtime_put(common->dev);
553 	return 0;
554 }
555 
556 static int cpsw_restore_vlans(struct net_device *vdev, int vid, void *arg)
557 {
558 	struct am65_cpsw_port *port = arg;
559 
560 	if (!vdev)
561 		return 0;
562 
563 	return am65_cpsw_nuss_ndo_slave_add_vid(port->ndev, 0, vid);
564 }
565 
566 static int am65_cpsw_nuss_ndo_slave_open(struct net_device *ndev)
567 {
568 	struct am65_cpsw_common *common = am65_ndev_to_common(ndev);
569 	struct am65_cpsw_port *port = am65_ndev_to_port(ndev);
570 	int ret, i;
571 	u32 reg;
572 
573 	ret = pm_runtime_resume_and_get(common->dev);
574 	if (ret < 0)
575 		return ret;
576 
577 	/* Idle MAC port */
578 	cpsw_sl_ctl_set(port->slave.mac_sl, CPSW_SL_CTL_CMD_IDLE);
579 	cpsw_sl_wait_for_idle(port->slave.mac_sl, 100);
580 	cpsw_sl_ctl_reset(port->slave.mac_sl);
581 
582 	/* soft reset MAC */
583 	cpsw_sl_reg_write(port->slave.mac_sl, CPSW_SL_SOFT_RESET, 1);
584 	mdelay(1);
585 	reg = cpsw_sl_reg_read(port->slave.mac_sl, CPSW_SL_SOFT_RESET);
586 	if (reg) {
587 		dev_err(common->dev, "soft RESET didn't complete\n");
588 		ret = -ETIMEDOUT;
589 		goto runtime_put;
590 	}
591 
592 	/* Notify the stack of the actual queue counts. */
593 	ret = netif_set_real_num_tx_queues(ndev, common->tx_ch_num);
594 	if (ret) {
595 		dev_err(common->dev, "cannot set real number of tx queues\n");
596 		goto runtime_put;
597 	}
598 
599 	ret = netif_set_real_num_rx_queues(ndev, AM65_CPSW_MAX_RX_QUEUES);
600 	if (ret) {
601 		dev_err(common->dev, "cannot set real number of rx queues\n");
602 		goto runtime_put;
603 	}
604 
605 	for (i = 0; i < common->tx_ch_num; i++) {
606 		struct netdev_queue *txq = netdev_get_tx_queue(ndev, i);
607 
608 		netdev_tx_reset_queue(txq);
609 		txq->tx_maxrate =  common->tx_chns[i].rate_mbps;
610 	}
611 
612 	ret = am65_cpsw_nuss_common_open(common);
613 	if (ret)
614 		goto runtime_put;
615 
616 	common->usage_count++;
617 
618 	am65_cpsw_port_set_sl_mac(port, ndev->dev_addr);
619 
620 	if (common->is_emac_mode)
621 		am65_cpsw_init_port_emac_ale(port);
622 	else
623 		am65_cpsw_init_port_switch_ale(port);
624 
625 	/* mac_sl should be configured via phy-link interface */
626 	am65_cpsw_sl_ctl_reset(port);
627 
628 	ret = phylink_of_phy_connect(port->slave.phylink, port->slave.phy_node, 0);
629 	if (ret)
630 		goto error_cleanup;
631 
632 	/* restore vlan configurations */
633 	vlan_for_each(ndev, cpsw_restore_vlans, port);
634 
635 	phylink_start(port->slave.phylink);
636 
637 	return 0;
638 
639 error_cleanup:
640 	am65_cpsw_nuss_ndo_slave_stop(ndev);
641 	return ret;
642 
643 runtime_put:
644 	pm_runtime_put(common->dev);
645 	return ret;
646 }
647 
648 static void am65_cpsw_nuss_rx_cleanup(void *data, dma_addr_t desc_dma)
649 {
650 	struct am65_cpsw_rx_chn *rx_chn = data;
651 	struct cppi5_host_desc_t *desc_rx;
652 	struct sk_buff *skb;
653 	dma_addr_t buf_dma;
654 	u32 buf_dma_len;
655 	void **swdata;
656 
657 	desc_rx = k3_cppi_desc_pool_dma2virt(rx_chn->desc_pool, desc_dma);
658 	swdata = cppi5_hdesc_get_swdata(desc_rx);
659 	skb = *swdata;
660 	cppi5_hdesc_get_obuf(desc_rx, &buf_dma, &buf_dma_len);
661 	k3_udma_glue_rx_cppi5_to_dma_addr(rx_chn->rx_chn, &buf_dma);
662 
663 	dma_unmap_single(rx_chn->dma_dev, buf_dma, buf_dma_len, DMA_FROM_DEVICE);
664 	k3_cppi_desc_pool_free(rx_chn->desc_pool, desc_rx);
665 
666 	dev_kfree_skb_any(skb);
667 }
668 
669 static void am65_cpsw_nuss_rx_ts(struct sk_buff *skb, u32 *psdata)
670 {
671 	struct skb_shared_hwtstamps *ssh;
672 	u64 ns;
673 
674 	ns = ((u64)psdata[1] << 32) | psdata[0];
675 
676 	ssh = skb_hwtstamps(skb);
677 	memset(ssh, 0, sizeof(*ssh));
678 	ssh->hwtstamp = ns_to_ktime(ns);
679 }
680 
681 /* RX psdata[2] word format - checksum information */
682 #define AM65_CPSW_RX_PSD_CSUM_ADD	GENMASK(15, 0)
683 #define AM65_CPSW_RX_PSD_CSUM_ERR	BIT(16)
684 #define AM65_CPSW_RX_PSD_IS_FRAGMENT	BIT(17)
685 #define AM65_CPSW_RX_PSD_IS_TCP		BIT(18)
686 #define AM65_CPSW_RX_PSD_IPV6_VALID	BIT(19)
687 #define AM65_CPSW_RX_PSD_IPV4_VALID	BIT(20)
688 
689 static void am65_cpsw_nuss_rx_csum(struct sk_buff *skb, u32 csum_info)
690 {
691 	/* HW can verify IPv4/IPv6 TCP/UDP packets checksum
692 	 * csum information provides in psdata[2] word:
693 	 * AM65_CPSW_RX_PSD_CSUM_ERR bit - indicates csum error
694 	 * AM65_CPSW_RX_PSD_IPV6_VALID and AM65_CPSW_RX_PSD_IPV4_VALID
695 	 * bits - indicates IPv4/IPv6 packet
696 	 * AM65_CPSW_RX_PSD_IS_FRAGMENT bit - indicates fragmented packet
697 	 * AM65_CPSW_RX_PSD_CSUM_ADD has value 0xFFFF for non fragmented packets
698 	 * or csum value for fragmented packets if !AM65_CPSW_RX_PSD_CSUM_ERR
699 	 */
700 	skb_checksum_none_assert(skb);
701 
702 	if (unlikely(!(skb->dev->features & NETIF_F_RXCSUM)))
703 		return;
704 
705 	if ((csum_info & (AM65_CPSW_RX_PSD_IPV6_VALID |
706 			  AM65_CPSW_RX_PSD_IPV4_VALID)) &&
707 			  !(csum_info & AM65_CPSW_RX_PSD_CSUM_ERR)) {
708 		/* csum for fragmented packets is unsupported */
709 		if (!(csum_info & AM65_CPSW_RX_PSD_IS_FRAGMENT))
710 			skb->ip_summed = CHECKSUM_UNNECESSARY;
711 	}
712 }
713 
714 static int am65_cpsw_nuss_rx_packets(struct am65_cpsw_common *common,
715 				     u32 flow_idx)
716 {
717 	struct am65_cpsw_rx_chn *rx_chn = &common->rx_chns;
718 	u32 buf_dma_len, pkt_len, port_id = 0, csum_info;
719 	struct am65_cpsw_ndev_priv *ndev_priv;
720 	struct am65_cpsw_ndev_stats *stats;
721 	struct cppi5_host_desc_t *desc_rx;
722 	struct device *dev = common->dev;
723 	struct sk_buff *skb, *new_skb;
724 	dma_addr_t desc_dma, buf_dma;
725 	struct am65_cpsw_port *port;
726 	struct net_device *ndev;
727 	void **swdata;
728 	u32 *psdata;
729 	int ret = 0;
730 
731 	ret = k3_udma_glue_pop_rx_chn(rx_chn->rx_chn, flow_idx, &desc_dma);
732 	if (ret) {
733 		if (ret != -ENODATA)
734 			dev_err(dev, "RX: pop chn fail %d\n", ret);
735 		return ret;
736 	}
737 
738 	if (cppi5_desc_is_tdcm(desc_dma)) {
739 		dev_dbg(dev, "%s RX tdown flow: %u\n", __func__, flow_idx);
740 		if (common->pdata.quirks & AM64_CPSW_QUIRK_DMA_RX_TDOWN_IRQ)
741 			complete(&common->tdown_complete);
742 		return 0;
743 	}
744 
745 	desc_rx = k3_cppi_desc_pool_dma2virt(rx_chn->desc_pool, desc_dma);
746 	dev_dbg(dev, "%s flow_idx: %u desc %pad\n",
747 		__func__, flow_idx, &desc_dma);
748 
749 	swdata = cppi5_hdesc_get_swdata(desc_rx);
750 	skb = *swdata;
751 	cppi5_hdesc_get_obuf(desc_rx, &buf_dma, &buf_dma_len);
752 	k3_udma_glue_rx_cppi5_to_dma_addr(rx_chn->rx_chn, &buf_dma);
753 	pkt_len = cppi5_hdesc_get_pktlen(desc_rx);
754 	cppi5_desc_get_tags_ids(&desc_rx->hdr, &port_id, NULL);
755 	dev_dbg(dev, "%s rx port_id:%d\n", __func__, port_id);
756 	port = am65_common_get_port(common, port_id);
757 	ndev = port->ndev;
758 	skb->dev = ndev;
759 
760 	psdata = cppi5_hdesc_get_psdata(desc_rx);
761 	/* add RX timestamp */
762 	if (port->rx_ts_enabled)
763 		am65_cpsw_nuss_rx_ts(skb, psdata);
764 	csum_info = psdata[2];
765 	dev_dbg(dev, "%s rx csum_info:%#x\n", __func__, csum_info);
766 
767 	dma_unmap_single(rx_chn->dma_dev, buf_dma, buf_dma_len, DMA_FROM_DEVICE);
768 
769 	k3_cppi_desc_pool_free(rx_chn->desc_pool, desc_rx);
770 
771 	new_skb = netdev_alloc_skb_ip_align(ndev, AM65_CPSW_MAX_PACKET_SIZE);
772 	if (new_skb) {
773 		ndev_priv = netdev_priv(ndev);
774 		am65_cpsw_nuss_set_offload_fwd_mark(skb, ndev_priv->offload_fwd_mark);
775 		skb_put(skb, pkt_len);
776 		skb->protocol = eth_type_trans(skb, ndev);
777 		am65_cpsw_nuss_rx_csum(skb, csum_info);
778 		napi_gro_receive(&common->napi_rx, skb);
779 
780 		stats = this_cpu_ptr(ndev_priv->stats);
781 
782 		u64_stats_update_begin(&stats->syncp);
783 		stats->rx_packets++;
784 		stats->rx_bytes += pkt_len;
785 		u64_stats_update_end(&stats->syncp);
786 		kmemleak_not_leak(new_skb);
787 	} else {
788 		ndev->stats.rx_dropped++;
789 		new_skb = skb;
790 	}
791 
792 	if (netif_dormant(ndev)) {
793 		dev_kfree_skb_any(new_skb);
794 		ndev->stats.rx_dropped++;
795 		return 0;
796 	}
797 
798 	ret = am65_cpsw_nuss_rx_push(common, new_skb);
799 	if (WARN_ON(ret < 0)) {
800 		dev_kfree_skb_any(new_skb);
801 		ndev->stats.rx_errors++;
802 		ndev->stats.rx_dropped++;
803 	}
804 
805 	return ret;
806 }
807 
808 static int am65_cpsw_nuss_rx_poll(struct napi_struct *napi_rx, int budget)
809 {
810 	struct am65_cpsw_common *common = am65_cpsw_napi_to_common(napi_rx);
811 	int flow = AM65_CPSW_MAX_RX_FLOWS;
812 	int cur_budget, ret;
813 	int num_rx = 0;
814 
815 	/* process every flow */
816 	while (flow--) {
817 		cur_budget = budget - num_rx;
818 
819 		while (cur_budget--) {
820 			ret = am65_cpsw_nuss_rx_packets(common, flow);
821 			if (ret)
822 				break;
823 			num_rx++;
824 		}
825 
826 		if (num_rx >= budget)
827 			break;
828 	}
829 
830 	dev_dbg(common->dev, "%s num_rx:%d %d\n", __func__, num_rx, budget);
831 
832 	if (num_rx < budget && napi_complete_done(napi_rx, num_rx)) {
833 		if (common->rx_irq_disabled) {
834 			common->rx_irq_disabled = false;
835 			enable_irq(common->rx_chns.irq);
836 		}
837 	}
838 
839 	return num_rx;
840 }
841 
842 static void am65_cpsw_nuss_xmit_free(struct am65_cpsw_tx_chn *tx_chn,
843 				     struct cppi5_host_desc_t *desc)
844 {
845 	struct cppi5_host_desc_t *first_desc, *next_desc;
846 	dma_addr_t buf_dma, next_desc_dma;
847 	u32 buf_dma_len;
848 
849 	first_desc = desc;
850 	next_desc = first_desc;
851 
852 	cppi5_hdesc_get_obuf(first_desc, &buf_dma, &buf_dma_len);
853 	k3_udma_glue_tx_cppi5_to_dma_addr(tx_chn->tx_chn, &buf_dma);
854 
855 	dma_unmap_single(tx_chn->dma_dev, buf_dma, buf_dma_len, DMA_TO_DEVICE);
856 
857 	next_desc_dma = cppi5_hdesc_get_next_hbdesc(first_desc);
858 	k3_udma_glue_tx_cppi5_to_dma_addr(tx_chn->tx_chn, &next_desc_dma);
859 	while (next_desc_dma) {
860 		next_desc = k3_cppi_desc_pool_dma2virt(tx_chn->desc_pool,
861 						       next_desc_dma);
862 		cppi5_hdesc_get_obuf(next_desc, &buf_dma, &buf_dma_len);
863 		k3_udma_glue_tx_cppi5_to_dma_addr(tx_chn->tx_chn, &buf_dma);
864 
865 		dma_unmap_page(tx_chn->dma_dev, buf_dma, buf_dma_len,
866 			       DMA_TO_DEVICE);
867 
868 		next_desc_dma = cppi5_hdesc_get_next_hbdesc(next_desc);
869 		k3_udma_glue_tx_cppi5_to_dma_addr(tx_chn->tx_chn, &next_desc_dma);
870 
871 		k3_cppi_desc_pool_free(tx_chn->desc_pool, next_desc);
872 	}
873 
874 	k3_cppi_desc_pool_free(tx_chn->desc_pool, first_desc);
875 }
876 
877 static void am65_cpsw_nuss_tx_cleanup(void *data, dma_addr_t desc_dma)
878 {
879 	struct am65_cpsw_tx_chn *tx_chn = data;
880 	struct cppi5_host_desc_t *desc_tx;
881 	struct sk_buff *skb;
882 	void **swdata;
883 
884 	desc_tx = k3_cppi_desc_pool_dma2virt(tx_chn->desc_pool, desc_dma);
885 	swdata = cppi5_hdesc_get_swdata(desc_tx);
886 	skb = *(swdata);
887 	am65_cpsw_nuss_xmit_free(tx_chn, desc_tx);
888 
889 	dev_kfree_skb_any(skb);
890 }
891 
892 static struct sk_buff *
893 am65_cpsw_nuss_tx_compl_packet(struct am65_cpsw_tx_chn *tx_chn,
894 			       dma_addr_t desc_dma)
895 {
896 	struct am65_cpsw_ndev_priv *ndev_priv;
897 	struct am65_cpsw_ndev_stats *stats;
898 	struct cppi5_host_desc_t *desc_tx;
899 	struct net_device *ndev;
900 	struct sk_buff *skb;
901 	void **swdata;
902 
903 	desc_tx = k3_cppi_desc_pool_dma2virt(tx_chn->desc_pool,
904 					     desc_dma);
905 	swdata = cppi5_hdesc_get_swdata(desc_tx);
906 	skb = *(swdata);
907 	am65_cpsw_nuss_xmit_free(tx_chn, desc_tx);
908 
909 	ndev = skb->dev;
910 
911 	am65_cpts_tx_timestamp(tx_chn->common->cpts, skb);
912 
913 	ndev_priv = netdev_priv(ndev);
914 	stats = this_cpu_ptr(ndev_priv->stats);
915 	u64_stats_update_begin(&stats->syncp);
916 	stats->tx_packets++;
917 	stats->tx_bytes += skb->len;
918 	u64_stats_update_end(&stats->syncp);
919 
920 	return skb;
921 }
922 
923 static void am65_cpsw_nuss_tx_wake(struct am65_cpsw_tx_chn *tx_chn, struct net_device *ndev,
924 				   struct netdev_queue *netif_txq)
925 {
926 	if (netif_tx_queue_stopped(netif_txq)) {
927 		/* Check whether the queue is stopped due to stalled
928 		 * tx dma, if the queue is stopped then wake the queue
929 		 * as we have free desc for tx
930 		 */
931 		__netif_tx_lock(netif_txq, smp_processor_id());
932 		if (netif_running(ndev) &&
933 		    (k3_cppi_desc_pool_avail(tx_chn->desc_pool) >= MAX_SKB_FRAGS))
934 			netif_tx_wake_queue(netif_txq);
935 
936 		__netif_tx_unlock(netif_txq);
937 	}
938 }
939 
940 static int am65_cpsw_nuss_tx_compl_packets(struct am65_cpsw_common *common,
941 					   int chn, unsigned int budget)
942 {
943 	struct device *dev = common->dev;
944 	struct am65_cpsw_tx_chn *tx_chn;
945 	struct netdev_queue *netif_txq;
946 	unsigned int total_bytes = 0;
947 	struct net_device *ndev;
948 	struct sk_buff *skb;
949 	dma_addr_t desc_dma;
950 	int res, num_tx = 0;
951 
952 	tx_chn = &common->tx_chns[chn];
953 
954 	while (true) {
955 		spin_lock(&tx_chn->lock);
956 		res = k3_udma_glue_pop_tx_chn(tx_chn->tx_chn, &desc_dma);
957 		spin_unlock(&tx_chn->lock);
958 		if (res == -ENODATA)
959 			break;
960 
961 		if (cppi5_desc_is_tdcm(desc_dma)) {
962 			if (atomic_dec_and_test(&common->tdown_cnt))
963 				complete(&common->tdown_complete);
964 			break;
965 		}
966 
967 		skb = am65_cpsw_nuss_tx_compl_packet(tx_chn, desc_dma);
968 		total_bytes = skb->len;
969 		ndev = skb->dev;
970 		napi_consume_skb(skb, budget);
971 		num_tx++;
972 
973 		netif_txq = netdev_get_tx_queue(ndev, chn);
974 
975 		netdev_tx_completed_queue(netif_txq, num_tx, total_bytes);
976 
977 		am65_cpsw_nuss_tx_wake(tx_chn, ndev, netif_txq);
978 	}
979 
980 	dev_dbg(dev, "%s:%u pkt:%d\n", __func__, chn, num_tx);
981 
982 	return num_tx;
983 }
984 
985 static int am65_cpsw_nuss_tx_compl_packets_2g(struct am65_cpsw_common *common,
986 					      int chn, unsigned int budget)
987 {
988 	struct device *dev = common->dev;
989 	struct am65_cpsw_tx_chn *tx_chn;
990 	struct netdev_queue *netif_txq;
991 	unsigned int total_bytes = 0;
992 	struct net_device *ndev;
993 	struct sk_buff *skb;
994 	dma_addr_t desc_dma;
995 	int res, num_tx = 0;
996 
997 	tx_chn = &common->tx_chns[chn];
998 
999 	while (true) {
1000 		res = k3_udma_glue_pop_tx_chn(tx_chn->tx_chn, &desc_dma);
1001 		if (res == -ENODATA)
1002 			break;
1003 
1004 		if (cppi5_desc_is_tdcm(desc_dma)) {
1005 			if (atomic_dec_and_test(&common->tdown_cnt))
1006 				complete(&common->tdown_complete);
1007 			break;
1008 		}
1009 
1010 		skb = am65_cpsw_nuss_tx_compl_packet(tx_chn, desc_dma);
1011 
1012 		ndev = skb->dev;
1013 		total_bytes += skb->len;
1014 		napi_consume_skb(skb, budget);
1015 		num_tx++;
1016 	}
1017 
1018 	if (!num_tx)
1019 		return 0;
1020 
1021 	netif_txq = netdev_get_tx_queue(ndev, chn);
1022 
1023 	netdev_tx_completed_queue(netif_txq, num_tx, total_bytes);
1024 
1025 	am65_cpsw_nuss_tx_wake(tx_chn, ndev, netif_txq);
1026 
1027 	dev_dbg(dev, "%s:%u pkt:%d\n", __func__, chn, num_tx);
1028 
1029 	return num_tx;
1030 }
1031 
1032 static int am65_cpsw_nuss_tx_poll(struct napi_struct *napi_tx, int budget)
1033 {
1034 	struct am65_cpsw_tx_chn *tx_chn = am65_cpsw_napi_to_tx_chn(napi_tx);
1035 	int num_tx;
1036 
1037 	if (AM65_CPSW_IS_CPSW2G(tx_chn->common))
1038 		num_tx = am65_cpsw_nuss_tx_compl_packets_2g(tx_chn->common, tx_chn->id, budget);
1039 	else
1040 		num_tx = am65_cpsw_nuss_tx_compl_packets(tx_chn->common, tx_chn->id, budget);
1041 
1042 	if (num_tx >= budget)
1043 		return budget;
1044 
1045 	if (napi_complete_done(napi_tx, num_tx))
1046 		enable_irq(tx_chn->irq);
1047 
1048 	return 0;
1049 }
1050 
1051 static irqreturn_t am65_cpsw_nuss_rx_irq(int irq, void *dev_id)
1052 {
1053 	struct am65_cpsw_common *common = dev_id;
1054 
1055 	common->rx_irq_disabled = true;
1056 	disable_irq_nosync(irq);
1057 	napi_schedule(&common->napi_rx);
1058 
1059 	return IRQ_HANDLED;
1060 }
1061 
1062 static irqreturn_t am65_cpsw_nuss_tx_irq(int irq, void *dev_id)
1063 {
1064 	struct am65_cpsw_tx_chn *tx_chn = dev_id;
1065 
1066 	disable_irq_nosync(irq);
1067 	napi_schedule(&tx_chn->napi_tx);
1068 
1069 	return IRQ_HANDLED;
1070 }
1071 
1072 static netdev_tx_t am65_cpsw_nuss_ndo_slave_xmit(struct sk_buff *skb,
1073 						 struct net_device *ndev)
1074 {
1075 	struct am65_cpsw_common *common = am65_ndev_to_common(ndev);
1076 	struct cppi5_host_desc_t *first_desc, *next_desc, *cur_desc;
1077 	struct am65_cpsw_port *port = am65_ndev_to_port(ndev);
1078 	struct device *dev = common->dev;
1079 	struct am65_cpsw_tx_chn *tx_chn;
1080 	struct netdev_queue *netif_txq;
1081 	dma_addr_t desc_dma, buf_dma;
1082 	int ret, q_idx, i;
1083 	void **swdata;
1084 	u32 *psdata;
1085 	u32 pkt_len;
1086 
1087 	/* padding enabled in hw */
1088 	pkt_len = skb_headlen(skb);
1089 
1090 	/* SKB TX timestamp */
1091 	if (port->tx_ts_enabled)
1092 		am65_cpts_prep_tx_timestamp(common->cpts, skb);
1093 
1094 	q_idx = skb_get_queue_mapping(skb);
1095 	dev_dbg(dev, "%s skb_queue:%d\n", __func__, q_idx);
1096 
1097 	tx_chn = &common->tx_chns[q_idx];
1098 	netif_txq = netdev_get_tx_queue(ndev, q_idx);
1099 
1100 	/* Map the linear buffer */
1101 	buf_dma = dma_map_single(tx_chn->dma_dev, skb->data, pkt_len,
1102 				 DMA_TO_DEVICE);
1103 	if (unlikely(dma_mapping_error(tx_chn->dma_dev, buf_dma))) {
1104 		dev_err(dev, "Failed to map tx skb buffer\n");
1105 		ndev->stats.tx_errors++;
1106 		goto err_free_skb;
1107 	}
1108 
1109 	first_desc = k3_cppi_desc_pool_alloc(tx_chn->desc_pool);
1110 	if (!first_desc) {
1111 		dev_dbg(dev, "Failed to allocate descriptor\n");
1112 		dma_unmap_single(tx_chn->dma_dev, buf_dma, pkt_len,
1113 				 DMA_TO_DEVICE);
1114 		goto busy_stop_q;
1115 	}
1116 
1117 	cppi5_hdesc_init(first_desc, CPPI5_INFO0_HDESC_EPIB_PRESENT,
1118 			 AM65_CPSW_NAV_PS_DATA_SIZE);
1119 	cppi5_desc_set_pktids(&first_desc->hdr, 0, 0x3FFF);
1120 	cppi5_hdesc_set_pkttype(first_desc, 0x7);
1121 	cppi5_desc_set_tags_ids(&first_desc->hdr, 0, port->port_id);
1122 
1123 	k3_udma_glue_tx_dma_to_cppi5_addr(tx_chn->tx_chn, &buf_dma);
1124 	cppi5_hdesc_attach_buf(first_desc, buf_dma, pkt_len, buf_dma, pkt_len);
1125 	swdata = cppi5_hdesc_get_swdata(first_desc);
1126 	*(swdata) = skb;
1127 	psdata = cppi5_hdesc_get_psdata(first_desc);
1128 
1129 	/* HW csum offload if enabled */
1130 	psdata[2] = 0;
1131 	if (likely(skb->ip_summed == CHECKSUM_PARTIAL)) {
1132 		unsigned int cs_start, cs_offset;
1133 
1134 		cs_start = skb_transport_offset(skb);
1135 		cs_offset = cs_start + skb->csum_offset;
1136 		/* HW numerates bytes starting from 1 */
1137 		psdata[2] = ((cs_offset + 1) << 24) |
1138 			    ((cs_start + 1) << 16) | (skb->len - cs_start);
1139 		dev_dbg(dev, "%s tx psdata:%#x\n", __func__, psdata[2]);
1140 	}
1141 
1142 	if (!skb_is_nonlinear(skb))
1143 		goto done_tx;
1144 
1145 	dev_dbg(dev, "fragmented SKB\n");
1146 
1147 	/* Handle the case where skb is fragmented in pages */
1148 	cur_desc = first_desc;
1149 	for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1150 		skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1151 		u32 frag_size = skb_frag_size(frag);
1152 
1153 		next_desc = k3_cppi_desc_pool_alloc(tx_chn->desc_pool);
1154 		if (!next_desc) {
1155 			dev_err(dev, "Failed to allocate descriptor\n");
1156 			goto busy_free_descs;
1157 		}
1158 
1159 		buf_dma = skb_frag_dma_map(tx_chn->dma_dev, frag, 0, frag_size,
1160 					   DMA_TO_DEVICE);
1161 		if (unlikely(dma_mapping_error(tx_chn->dma_dev, buf_dma))) {
1162 			dev_err(dev, "Failed to map tx skb page\n");
1163 			k3_cppi_desc_pool_free(tx_chn->desc_pool, next_desc);
1164 			ndev->stats.tx_errors++;
1165 			goto err_free_descs;
1166 		}
1167 
1168 		cppi5_hdesc_reset_hbdesc(next_desc);
1169 		k3_udma_glue_tx_dma_to_cppi5_addr(tx_chn->tx_chn, &buf_dma);
1170 		cppi5_hdesc_attach_buf(next_desc,
1171 				       buf_dma, frag_size, buf_dma, frag_size);
1172 
1173 		desc_dma = k3_cppi_desc_pool_virt2dma(tx_chn->desc_pool,
1174 						      next_desc);
1175 		k3_udma_glue_tx_dma_to_cppi5_addr(tx_chn->tx_chn, &desc_dma);
1176 		cppi5_hdesc_link_hbdesc(cur_desc, desc_dma);
1177 
1178 		pkt_len += frag_size;
1179 		cur_desc = next_desc;
1180 	}
1181 	WARN_ON(pkt_len != skb->len);
1182 
1183 done_tx:
1184 	skb_tx_timestamp(skb);
1185 
1186 	/* report bql before sending packet */
1187 	netdev_tx_sent_queue(netif_txq, pkt_len);
1188 
1189 	cppi5_hdesc_set_pktlen(first_desc, pkt_len);
1190 	desc_dma = k3_cppi_desc_pool_virt2dma(tx_chn->desc_pool, first_desc);
1191 	if (AM65_CPSW_IS_CPSW2G(common)) {
1192 		ret = k3_udma_glue_push_tx_chn(tx_chn->tx_chn, first_desc, desc_dma);
1193 	} else {
1194 		spin_lock_bh(&tx_chn->lock);
1195 		ret = k3_udma_glue_push_tx_chn(tx_chn->tx_chn, first_desc, desc_dma);
1196 		spin_unlock_bh(&tx_chn->lock);
1197 	}
1198 	if (ret) {
1199 		dev_err(dev, "can't push desc %d\n", ret);
1200 		/* inform bql */
1201 		netdev_tx_completed_queue(netif_txq, 1, pkt_len);
1202 		ndev->stats.tx_errors++;
1203 		goto err_free_descs;
1204 	}
1205 
1206 	if (k3_cppi_desc_pool_avail(tx_chn->desc_pool) < MAX_SKB_FRAGS) {
1207 		netif_tx_stop_queue(netif_txq);
1208 		/* Barrier, so that stop_queue visible to other cpus */
1209 		smp_mb__after_atomic();
1210 		dev_dbg(dev, "netif_tx_stop_queue %d\n", q_idx);
1211 
1212 		/* re-check for smp */
1213 		if (k3_cppi_desc_pool_avail(tx_chn->desc_pool) >=
1214 		    MAX_SKB_FRAGS) {
1215 			netif_tx_wake_queue(netif_txq);
1216 			dev_dbg(dev, "netif_tx_wake_queue %d\n", q_idx);
1217 		}
1218 	}
1219 
1220 	return NETDEV_TX_OK;
1221 
1222 err_free_descs:
1223 	am65_cpsw_nuss_xmit_free(tx_chn, first_desc);
1224 err_free_skb:
1225 	ndev->stats.tx_dropped++;
1226 	dev_kfree_skb_any(skb);
1227 	return NETDEV_TX_OK;
1228 
1229 busy_free_descs:
1230 	am65_cpsw_nuss_xmit_free(tx_chn, first_desc);
1231 busy_stop_q:
1232 	netif_tx_stop_queue(netif_txq);
1233 	return NETDEV_TX_BUSY;
1234 }
1235 
1236 static int am65_cpsw_nuss_ndo_slave_set_mac_address(struct net_device *ndev,
1237 						    void *addr)
1238 {
1239 	struct am65_cpsw_common *common = am65_ndev_to_common(ndev);
1240 	struct am65_cpsw_port *port = am65_ndev_to_port(ndev);
1241 	struct sockaddr *sockaddr = (struct sockaddr *)addr;
1242 	int ret;
1243 
1244 	ret = eth_prepare_mac_addr_change(ndev, addr);
1245 	if (ret < 0)
1246 		return ret;
1247 
1248 	ret = pm_runtime_resume_and_get(common->dev);
1249 	if (ret < 0)
1250 		return ret;
1251 
1252 	cpsw_ale_del_ucast(common->ale, ndev->dev_addr,
1253 			   HOST_PORT_NUM, 0, 0);
1254 	cpsw_ale_add_ucast(common->ale, sockaddr->sa_data,
1255 			   HOST_PORT_NUM, ALE_SECURE, 0);
1256 
1257 	am65_cpsw_port_set_sl_mac(port, addr);
1258 	eth_commit_mac_addr_change(ndev, sockaddr);
1259 
1260 	pm_runtime_put(common->dev);
1261 
1262 	return 0;
1263 }
1264 
1265 static int am65_cpsw_nuss_hwtstamp_set(struct net_device *ndev,
1266 				       struct ifreq *ifr)
1267 {
1268 	struct am65_cpsw_common *common = am65_ndev_to_common(ndev);
1269 	struct am65_cpsw_port *port = am65_ndev_to_port(ndev);
1270 	u32 ts_ctrl, seq_id, ts_ctrl_ltype2, ts_vlan_ltype;
1271 	struct hwtstamp_config cfg;
1272 
1273 	if (!IS_ENABLED(CONFIG_TI_K3_AM65_CPTS))
1274 		return -EOPNOTSUPP;
1275 
1276 	if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg)))
1277 		return -EFAULT;
1278 
1279 	/* TX HW timestamp */
1280 	switch (cfg.tx_type) {
1281 	case HWTSTAMP_TX_OFF:
1282 	case HWTSTAMP_TX_ON:
1283 		break;
1284 	default:
1285 		return -ERANGE;
1286 	}
1287 
1288 	switch (cfg.rx_filter) {
1289 	case HWTSTAMP_FILTER_NONE:
1290 		port->rx_ts_enabled = false;
1291 		break;
1292 	case HWTSTAMP_FILTER_ALL:
1293 	case HWTSTAMP_FILTER_SOME:
1294 	case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
1295 	case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
1296 	case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
1297 	case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
1298 	case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
1299 	case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
1300 	case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
1301 	case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
1302 	case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
1303 	case HWTSTAMP_FILTER_PTP_V2_EVENT:
1304 	case HWTSTAMP_FILTER_PTP_V2_SYNC:
1305 	case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
1306 	case HWTSTAMP_FILTER_NTP_ALL:
1307 		port->rx_ts_enabled = true;
1308 		cfg.rx_filter = HWTSTAMP_FILTER_ALL;
1309 		break;
1310 	default:
1311 		return -ERANGE;
1312 	}
1313 
1314 	port->tx_ts_enabled = (cfg.tx_type == HWTSTAMP_TX_ON);
1315 
1316 	/* cfg TX timestamp */
1317 	seq_id = (AM65_CPSW_TS_SEQ_ID_OFFSET <<
1318 		  AM65_CPSW_PN_TS_SEQ_ID_OFFSET_SHIFT) | ETH_P_1588;
1319 
1320 	ts_vlan_ltype = ETH_P_8021Q;
1321 
1322 	ts_ctrl_ltype2 = ETH_P_1588 |
1323 			 AM65_CPSW_PN_TS_CTL_LTYPE2_TS_107 |
1324 			 AM65_CPSW_PN_TS_CTL_LTYPE2_TS_129 |
1325 			 AM65_CPSW_PN_TS_CTL_LTYPE2_TS_130 |
1326 			 AM65_CPSW_PN_TS_CTL_LTYPE2_TS_131 |
1327 			 AM65_CPSW_PN_TS_CTL_LTYPE2_TS_132 |
1328 			 AM65_CPSW_PN_TS_CTL_LTYPE2_TS_319 |
1329 			 AM65_CPSW_PN_TS_CTL_LTYPE2_TS_320 |
1330 			 AM65_CPSW_PN_TS_CTL_LTYPE2_TS_TTL_NONZERO;
1331 
1332 	ts_ctrl = AM65_CPSW_TS_EVENT_MSG_TYPE_BITS <<
1333 		  AM65_CPSW_PN_TS_CTL_MSG_TYPE_EN_SHIFT;
1334 
1335 	if (port->tx_ts_enabled)
1336 		ts_ctrl |= AM65_CPSW_TS_TX_ANX_ALL_EN |
1337 			   AM65_CPSW_PN_TS_CTL_TX_VLAN_LT1_EN;
1338 
1339 	writel(seq_id, port->port_base + AM65_CPSW_PORTN_REG_TS_SEQ_LTYPE_REG);
1340 	writel(ts_vlan_ltype, port->port_base +
1341 	       AM65_CPSW_PORTN_REG_TS_VLAN_LTYPE_REG);
1342 	writel(ts_ctrl_ltype2, port->port_base +
1343 	       AM65_CPSW_PORTN_REG_TS_CTL_LTYPE2);
1344 	writel(ts_ctrl, port->port_base + AM65_CPSW_PORTN_REG_TS_CTL);
1345 
1346 	/* en/dis RX timestamp */
1347 	am65_cpts_rx_enable(common->cpts, port->rx_ts_enabled);
1348 
1349 	return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0;
1350 }
1351 
1352 static int am65_cpsw_nuss_hwtstamp_get(struct net_device *ndev,
1353 				       struct ifreq *ifr)
1354 {
1355 	struct am65_cpsw_port *port = am65_ndev_to_port(ndev);
1356 	struct hwtstamp_config cfg;
1357 
1358 	if (!IS_ENABLED(CONFIG_TI_K3_AM65_CPTS))
1359 		return -EOPNOTSUPP;
1360 
1361 	cfg.flags = 0;
1362 	cfg.tx_type = port->tx_ts_enabled ?
1363 		      HWTSTAMP_TX_ON : HWTSTAMP_TX_OFF;
1364 	cfg.rx_filter = port->rx_ts_enabled ?
1365 			HWTSTAMP_FILTER_ALL : HWTSTAMP_FILTER_NONE;
1366 
1367 	return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0;
1368 }
1369 
1370 static int am65_cpsw_nuss_ndo_slave_ioctl(struct net_device *ndev,
1371 					  struct ifreq *req, int cmd)
1372 {
1373 	struct am65_cpsw_port *port = am65_ndev_to_port(ndev);
1374 
1375 	if (!netif_running(ndev))
1376 		return -EINVAL;
1377 
1378 	switch (cmd) {
1379 	case SIOCSHWTSTAMP:
1380 		return am65_cpsw_nuss_hwtstamp_set(ndev, req);
1381 	case SIOCGHWTSTAMP:
1382 		return am65_cpsw_nuss_hwtstamp_get(ndev, req);
1383 	}
1384 
1385 	return phylink_mii_ioctl(port->slave.phylink, req, cmd);
1386 }
1387 
1388 static void am65_cpsw_nuss_ndo_get_stats(struct net_device *dev,
1389 					 struct rtnl_link_stats64 *stats)
1390 {
1391 	struct am65_cpsw_ndev_priv *ndev_priv = netdev_priv(dev);
1392 	unsigned int start;
1393 	int cpu;
1394 
1395 	for_each_possible_cpu(cpu) {
1396 		struct am65_cpsw_ndev_stats *cpu_stats;
1397 		u64 rx_packets;
1398 		u64 rx_bytes;
1399 		u64 tx_packets;
1400 		u64 tx_bytes;
1401 
1402 		cpu_stats = per_cpu_ptr(ndev_priv->stats, cpu);
1403 		do {
1404 			start = u64_stats_fetch_begin(&cpu_stats->syncp);
1405 			rx_packets = cpu_stats->rx_packets;
1406 			rx_bytes   = cpu_stats->rx_bytes;
1407 			tx_packets = cpu_stats->tx_packets;
1408 			tx_bytes   = cpu_stats->tx_bytes;
1409 		} while (u64_stats_fetch_retry(&cpu_stats->syncp, start));
1410 
1411 		stats->rx_packets += rx_packets;
1412 		stats->rx_bytes   += rx_bytes;
1413 		stats->tx_packets += tx_packets;
1414 		stats->tx_bytes   += tx_bytes;
1415 	}
1416 
1417 	stats->rx_errors	= dev->stats.rx_errors;
1418 	stats->rx_dropped	= dev->stats.rx_dropped;
1419 	stats->tx_dropped	= dev->stats.tx_dropped;
1420 }
1421 
1422 static const struct net_device_ops am65_cpsw_nuss_netdev_ops = {
1423 	.ndo_open		= am65_cpsw_nuss_ndo_slave_open,
1424 	.ndo_stop		= am65_cpsw_nuss_ndo_slave_stop,
1425 	.ndo_start_xmit		= am65_cpsw_nuss_ndo_slave_xmit,
1426 	.ndo_set_rx_mode	= am65_cpsw_nuss_ndo_slave_set_rx_mode,
1427 	.ndo_get_stats64        = am65_cpsw_nuss_ndo_get_stats,
1428 	.ndo_validate_addr	= eth_validate_addr,
1429 	.ndo_set_mac_address	= am65_cpsw_nuss_ndo_slave_set_mac_address,
1430 	.ndo_tx_timeout		= am65_cpsw_nuss_ndo_host_tx_timeout,
1431 	.ndo_vlan_rx_add_vid	= am65_cpsw_nuss_ndo_slave_add_vid,
1432 	.ndo_vlan_rx_kill_vid	= am65_cpsw_nuss_ndo_slave_kill_vid,
1433 	.ndo_eth_ioctl		= am65_cpsw_nuss_ndo_slave_ioctl,
1434 	.ndo_setup_tc           = am65_cpsw_qos_ndo_setup_tc,
1435 	.ndo_set_tx_maxrate	= am65_cpsw_qos_ndo_tx_p0_set_maxrate,
1436 };
1437 
1438 static void am65_cpsw_disable_phy(struct phy *phy)
1439 {
1440 	phy_power_off(phy);
1441 	phy_exit(phy);
1442 }
1443 
1444 static int am65_cpsw_enable_phy(struct phy *phy)
1445 {
1446 	int ret;
1447 
1448 	ret = phy_init(phy);
1449 	if (ret < 0)
1450 		return ret;
1451 
1452 	ret = phy_power_on(phy);
1453 	if (ret < 0) {
1454 		phy_exit(phy);
1455 		return ret;
1456 	}
1457 
1458 	return 0;
1459 }
1460 
1461 static void am65_cpsw_disable_serdes_phy(struct am65_cpsw_common *common)
1462 {
1463 	struct am65_cpsw_port *port;
1464 	struct phy *phy;
1465 	int i;
1466 
1467 	for (i = 0; i < common->port_num; i++) {
1468 		port = &common->ports[i];
1469 		phy = port->slave.serdes_phy;
1470 		if (phy)
1471 			am65_cpsw_disable_phy(phy);
1472 	}
1473 }
1474 
1475 static int am65_cpsw_init_serdes_phy(struct device *dev, struct device_node *port_np,
1476 				     struct am65_cpsw_port *port)
1477 {
1478 	const char *name = "serdes";
1479 	struct phy *phy;
1480 	int ret;
1481 
1482 	phy = devm_of_phy_optional_get(dev, port_np, name);
1483 	if (IS_ERR_OR_NULL(phy))
1484 		return PTR_ERR_OR_ZERO(phy);
1485 
1486 	/* Serdes PHY exists. Store it. */
1487 	port->slave.serdes_phy = phy;
1488 
1489 	ret =  am65_cpsw_enable_phy(phy);
1490 	if (ret < 0)
1491 		goto err_phy;
1492 
1493 	return 0;
1494 
1495 err_phy:
1496 	devm_phy_put(dev, phy);
1497 	return ret;
1498 }
1499 
1500 static void am65_cpsw_nuss_mac_config(struct phylink_config *config, unsigned int mode,
1501 				      const struct phylink_link_state *state)
1502 {
1503 	struct am65_cpsw_slave_data *slave = container_of(config, struct am65_cpsw_slave_data,
1504 							  phylink_config);
1505 	struct am65_cpsw_port *port = container_of(slave, struct am65_cpsw_port, slave);
1506 	struct am65_cpsw_common *common = port->common;
1507 
1508 	if (common->pdata.extra_modes & BIT(state->interface)) {
1509 		if (state->interface == PHY_INTERFACE_MODE_SGMII) {
1510 			writel(ADVERTISE_SGMII,
1511 			       port->sgmii_base + AM65_CPSW_SGMII_MR_ADV_ABILITY_REG);
1512 			cpsw_sl_ctl_set(port->slave.mac_sl, CPSW_SL_CTL_EXT_EN);
1513 		} else {
1514 			cpsw_sl_ctl_clr(port->slave.mac_sl, CPSW_SL_CTL_EXT_EN);
1515 		}
1516 
1517 		if (state->interface == PHY_INTERFACE_MODE_USXGMII) {
1518 			cpsw_sl_ctl_set(port->slave.mac_sl,
1519 					CPSW_SL_CTL_XGIG | CPSW_SL_CTL_XGMII_EN);
1520 		} else {
1521 			cpsw_sl_ctl_clr(port->slave.mac_sl,
1522 					CPSW_SL_CTL_XGIG | CPSW_SL_CTL_XGMII_EN);
1523 		}
1524 
1525 		writel(AM65_CPSW_SGMII_CONTROL_MR_AN_ENABLE,
1526 		       port->sgmii_base + AM65_CPSW_SGMII_CONTROL_REG);
1527 	}
1528 }
1529 
1530 static void am65_cpsw_nuss_mac_link_down(struct phylink_config *config, unsigned int mode,
1531 					 phy_interface_t interface)
1532 {
1533 	struct am65_cpsw_slave_data *slave = container_of(config, struct am65_cpsw_slave_data,
1534 							  phylink_config);
1535 	struct am65_cpsw_port *port = container_of(slave, struct am65_cpsw_port, slave);
1536 	struct am65_cpsw_common *common = port->common;
1537 	struct net_device *ndev = port->ndev;
1538 	u32 mac_control;
1539 	int tmo;
1540 
1541 	/* disable forwarding */
1542 	cpsw_ale_control_set(common->ale, port->port_id, ALE_PORT_STATE, ALE_PORT_STATE_DISABLE);
1543 
1544 	cpsw_sl_ctl_set(port->slave.mac_sl, CPSW_SL_CTL_CMD_IDLE);
1545 
1546 	tmo = cpsw_sl_wait_for_idle(port->slave.mac_sl, 100);
1547 	dev_dbg(common->dev, "down msc_sl %08x tmo %d\n",
1548 		cpsw_sl_reg_read(port->slave.mac_sl, CPSW_SL_MACSTATUS), tmo);
1549 
1550 	/* All the bits that am65_cpsw_nuss_mac_link_up() can possibly set */
1551 	mac_control = CPSW_SL_CTL_GMII_EN | CPSW_SL_CTL_GIG | CPSW_SL_CTL_IFCTL_A |
1552 		      CPSW_SL_CTL_FULLDUPLEX | CPSW_SL_CTL_RX_FLOW_EN | CPSW_SL_CTL_TX_FLOW_EN;
1553 	/* If interface mode is RGMII, CPSW_SL_CTL_EXT_EN might have been set for 10 Mbps */
1554 	if (phy_interface_mode_is_rgmii(interface))
1555 		mac_control |= CPSW_SL_CTL_EXT_EN;
1556 	/* Only clear those bits that can be set by am65_cpsw_nuss_mac_link_up() */
1557 	cpsw_sl_ctl_clr(port->slave.mac_sl, mac_control);
1558 
1559 	am65_cpsw_qos_link_down(ndev);
1560 	netif_tx_stop_all_queues(ndev);
1561 }
1562 
1563 static void am65_cpsw_nuss_mac_link_up(struct phylink_config *config, struct phy_device *phy,
1564 				       unsigned int mode, phy_interface_t interface, int speed,
1565 				       int duplex, bool tx_pause, bool rx_pause)
1566 {
1567 	struct am65_cpsw_slave_data *slave = container_of(config, struct am65_cpsw_slave_data,
1568 							  phylink_config);
1569 	struct am65_cpsw_port *port = container_of(slave, struct am65_cpsw_port, slave);
1570 	struct am65_cpsw_common *common = port->common;
1571 	u32 mac_control = CPSW_SL_CTL_GMII_EN;
1572 	struct net_device *ndev = port->ndev;
1573 
1574 	/* Bring the port out of idle state */
1575 	cpsw_sl_ctl_clr(port->slave.mac_sl, CPSW_SL_CTL_CMD_IDLE);
1576 
1577 	if (speed == SPEED_1000)
1578 		mac_control |= CPSW_SL_CTL_GIG;
1579 	/* TODO: Verify whether in-band is necessary for 10 Mbps RGMII */
1580 	if (speed == SPEED_10 && phy_interface_mode_is_rgmii(interface))
1581 		/* Can be used with in band mode only */
1582 		mac_control |= CPSW_SL_CTL_EXT_EN;
1583 	if (speed == SPEED_100 && interface == PHY_INTERFACE_MODE_RMII)
1584 		mac_control |= CPSW_SL_CTL_IFCTL_A;
1585 	if (duplex)
1586 		mac_control |= CPSW_SL_CTL_FULLDUPLEX;
1587 
1588 	/* rx_pause/tx_pause */
1589 	if (rx_pause)
1590 		mac_control |= CPSW_SL_CTL_RX_FLOW_EN;
1591 
1592 	if (tx_pause)
1593 		mac_control |= CPSW_SL_CTL_TX_FLOW_EN;
1594 
1595 	cpsw_sl_ctl_set(port->slave.mac_sl, mac_control);
1596 
1597 	/* enable forwarding */
1598 	cpsw_ale_control_set(common->ale, port->port_id, ALE_PORT_STATE, ALE_PORT_STATE_FORWARD);
1599 
1600 	am65_cpsw_qos_link_up(ndev, speed);
1601 	netif_tx_wake_all_queues(ndev);
1602 }
1603 
1604 static const struct phylink_mac_ops am65_cpsw_phylink_mac_ops = {
1605 	.mac_config = am65_cpsw_nuss_mac_config,
1606 	.mac_link_down = am65_cpsw_nuss_mac_link_down,
1607 	.mac_link_up = am65_cpsw_nuss_mac_link_up,
1608 };
1609 
1610 static void am65_cpsw_nuss_slave_disable_unused(struct am65_cpsw_port *port)
1611 {
1612 	struct am65_cpsw_common *common = port->common;
1613 
1614 	if (!port->disabled)
1615 		return;
1616 
1617 	cpsw_ale_control_set(common->ale, port->port_id,
1618 			     ALE_PORT_STATE, ALE_PORT_STATE_DISABLE);
1619 
1620 	cpsw_sl_reset(port->slave.mac_sl, 100);
1621 	cpsw_sl_ctl_reset(port->slave.mac_sl);
1622 }
1623 
1624 static void am65_cpsw_nuss_free_tx_chns(void *data)
1625 {
1626 	struct am65_cpsw_common *common = data;
1627 	int i;
1628 
1629 	for (i = 0; i < common->tx_ch_num; i++) {
1630 		struct am65_cpsw_tx_chn *tx_chn = &common->tx_chns[i];
1631 
1632 		if (!IS_ERR_OR_NULL(tx_chn->desc_pool))
1633 			k3_cppi_desc_pool_destroy(tx_chn->desc_pool);
1634 
1635 		if (!IS_ERR_OR_NULL(tx_chn->tx_chn))
1636 			k3_udma_glue_release_tx_chn(tx_chn->tx_chn);
1637 
1638 		memset(tx_chn, 0, sizeof(*tx_chn));
1639 	}
1640 }
1641 
1642 void am65_cpsw_nuss_remove_tx_chns(struct am65_cpsw_common *common)
1643 {
1644 	struct device *dev = common->dev;
1645 	int i;
1646 
1647 	devm_remove_action(dev, am65_cpsw_nuss_free_tx_chns, common);
1648 
1649 	common->tx_ch_rate_msk = 0;
1650 	for (i = 0; i < common->tx_ch_num; i++) {
1651 		struct am65_cpsw_tx_chn *tx_chn = &common->tx_chns[i];
1652 
1653 		if (tx_chn->irq)
1654 			devm_free_irq(dev, tx_chn->irq, tx_chn);
1655 
1656 		netif_napi_del(&tx_chn->napi_tx);
1657 
1658 		if (!IS_ERR_OR_NULL(tx_chn->desc_pool))
1659 			k3_cppi_desc_pool_destroy(tx_chn->desc_pool);
1660 
1661 		if (!IS_ERR_OR_NULL(tx_chn->tx_chn))
1662 			k3_udma_glue_release_tx_chn(tx_chn->tx_chn);
1663 
1664 		memset(tx_chn, 0, sizeof(*tx_chn));
1665 	}
1666 }
1667 
1668 static int am65_cpsw_nuss_ndev_add_tx_napi(struct am65_cpsw_common *common)
1669 {
1670 	struct device *dev = common->dev;
1671 	int i, ret = 0;
1672 
1673 	for (i = 0; i < common->tx_ch_num; i++) {
1674 		struct am65_cpsw_tx_chn *tx_chn = &common->tx_chns[i];
1675 
1676 		netif_napi_add_tx(common->dma_ndev, &tx_chn->napi_tx,
1677 				  am65_cpsw_nuss_tx_poll);
1678 
1679 		ret = devm_request_irq(dev, tx_chn->irq,
1680 				       am65_cpsw_nuss_tx_irq,
1681 				       IRQF_TRIGGER_HIGH,
1682 				       tx_chn->tx_chn_name, tx_chn);
1683 		if (ret) {
1684 			dev_err(dev, "failure requesting tx%u irq %u, %d\n",
1685 				tx_chn->id, tx_chn->irq, ret);
1686 			goto err;
1687 		}
1688 	}
1689 
1690 err:
1691 	return ret;
1692 }
1693 
1694 static int am65_cpsw_nuss_init_tx_chns(struct am65_cpsw_common *common)
1695 {
1696 	u32  max_desc_num = ALIGN(AM65_CPSW_MAX_TX_DESC, MAX_SKB_FRAGS);
1697 	struct k3_udma_glue_tx_channel_cfg tx_cfg = { 0 };
1698 	struct device *dev = common->dev;
1699 	struct k3_ring_cfg ring_cfg = {
1700 		.elm_size = K3_RINGACC_RING_ELSIZE_8,
1701 		.mode = K3_RINGACC_RING_MODE_RING,
1702 		.flags = 0
1703 	};
1704 	u32 hdesc_size;
1705 	int i, ret = 0;
1706 
1707 	hdesc_size = cppi5_hdesc_calc_size(true, AM65_CPSW_NAV_PS_DATA_SIZE,
1708 					   AM65_CPSW_NAV_SW_DATA_SIZE);
1709 
1710 	tx_cfg.swdata_size = AM65_CPSW_NAV_SW_DATA_SIZE;
1711 	tx_cfg.tx_cfg = ring_cfg;
1712 	tx_cfg.txcq_cfg = ring_cfg;
1713 	tx_cfg.tx_cfg.size = max_desc_num;
1714 	tx_cfg.txcq_cfg.size = max_desc_num;
1715 
1716 	for (i = 0; i < common->tx_ch_num; i++) {
1717 		struct am65_cpsw_tx_chn *tx_chn = &common->tx_chns[i];
1718 
1719 		snprintf(tx_chn->tx_chn_name,
1720 			 sizeof(tx_chn->tx_chn_name), "tx%d", i);
1721 
1722 		spin_lock_init(&tx_chn->lock);
1723 		tx_chn->common = common;
1724 		tx_chn->id = i;
1725 		tx_chn->descs_num = max_desc_num;
1726 
1727 		tx_chn->tx_chn =
1728 			k3_udma_glue_request_tx_chn(dev,
1729 						    tx_chn->tx_chn_name,
1730 						    &tx_cfg);
1731 		if (IS_ERR(tx_chn->tx_chn)) {
1732 			ret = dev_err_probe(dev, PTR_ERR(tx_chn->tx_chn),
1733 					    "Failed to request tx dma channel\n");
1734 			goto err;
1735 		}
1736 		tx_chn->dma_dev = k3_udma_glue_tx_get_dma_device(tx_chn->tx_chn);
1737 
1738 		tx_chn->desc_pool = k3_cppi_desc_pool_create_name(tx_chn->dma_dev,
1739 								  tx_chn->descs_num,
1740 								  hdesc_size,
1741 								  tx_chn->tx_chn_name);
1742 		if (IS_ERR(tx_chn->desc_pool)) {
1743 			ret = PTR_ERR(tx_chn->desc_pool);
1744 			dev_err(dev, "Failed to create poll %d\n", ret);
1745 			goto err;
1746 		}
1747 
1748 		tx_chn->irq = k3_udma_glue_tx_get_irq(tx_chn->tx_chn);
1749 		if (tx_chn->irq <= 0) {
1750 			dev_err(dev, "Failed to get tx dma irq %d\n",
1751 				tx_chn->irq);
1752 			goto err;
1753 		}
1754 
1755 		snprintf(tx_chn->tx_chn_name,
1756 			 sizeof(tx_chn->tx_chn_name), "%s-tx%d",
1757 			 dev_name(dev), tx_chn->id);
1758 	}
1759 
1760 	ret = am65_cpsw_nuss_ndev_add_tx_napi(common);
1761 	if (ret) {
1762 		dev_err(dev, "Failed to add tx NAPI %d\n", ret);
1763 		goto err;
1764 	}
1765 
1766 err:
1767 	i = devm_add_action(dev, am65_cpsw_nuss_free_tx_chns, common);
1768 	if (i) {
1769 		dev_err(dev, "Failed to add free_tx_chns action %d\n", i);
1770 		return i;
1771 	}
1772 
1773 	return ret;
1774 }
1775 
1776 static void am65_cpsw_nuss_free_rx_chns(void *data)
1777 {
1778 	struct am65_cpsw_common *common = data;
1779 	struct am65_cpsw_rx_chn *rx_chn;
1780 
1781 	rx_chn = &common->rx_chns;
1782 
1783 	if (!IS_ERR_OR_NULL(rx_chn->desc_pool))
1784 		k3_cppi_desc_pool_destroy(rx_chn->desc_pool);
1785 
1786 	if (!IS_ERR_OR_NULL(rx_chn->rx_chn))
1787 		k3_udma_glue_release_rx_chn(rx_chn->rx_chn);
1788 }
1789 
1790 static void am65_cpsw_nuss_remove_rx_chns(void *data)
1791 {
1792 	struct am65_cpsw_common *common = data;
1793 	struct am65_cpsw_rx_chn *rx_chn;
1794 	struct device *dev = common->dev;
1795 
1796 	rx_chn = &common->rx_chns;
1797 	devm_remove_action(dev, am65_cpsw_nuss_free_rx_chns, common);
1798 
1799 	if (!(rx_chn->irq < 0))
1800 		devm_free_irq(dev, rx_chn->irq, common);
1801 
1802 	netif_napi_del(&common->napi_rx);
1803 
1804 	if (!IS_ERR_OR_NULL(rx_chn->desc_pool))
1805 		k3_cppi_desc_pool_destroy(rx_chn->desc_pool);
1806 
1807 	if (!IS_ERR_OR_NULL(rx_chn->rx_chn))
1808 		k3_udma_glue_release_rx_chn(rx_chn->rx_chn);
1809 
1810 	common->rx_flow_id_base = -1;
1811 }
1812 
1813 static int am65_cpsw_nuss_init_rx_chns(struct am65_cpsw_common *common)
1814 {
1815 	struct am65_cpsw_rx_chn *rx_chn = &common->rx_chns;
1816 	struct k3_udma_glue_rx_channel_cfg rx_cfg = { 0 };
1817 	u32  max_desc_num = AM65_CPSW_MAX_RX_DESC;
1818 	struct device *dev = common->dev;
1819 	u32 hdesc_size;
1820 	u32 fdqring_id;
1821 	int i, ret = 0;
1822 
1823 	hdesc_size = cppi5_hdesc_calc_size(true, AM65_CPSW_NAV_PS_DATA_SIZE,
1824 					   AM65_CPSW_NAV_SW_DATA_SIZE);
1825 
1826 	rx_cfg.swdata_size = AM65_CPSW_NAV_SW_DATA_SIZE;
1827 	rx_cfg.flow_id_num = AM65_CPSW_MAX_RX_FLOWS;
1828 	rx_cfg.flow_id_base = common->rx_flow_id_base;
1829 
1830 	/* init all flows */
1831 	rx_chn->dev = dev;
1832 	rx_chn->descs_num = max_desc_num;
1833 
1834 	rx_chn->rx_chn = k3_udma_glue_request_rx_chn(dev, "rx", &rx_cfg);
1835 	if (IS_ERR(rx_chn->rx_chn)) {
1836 		ret = dev_err_probe(dev, PTR_ERR(rx_chn->rx_chn),
1837 				    "Failed to request rx dma channel\n");
1838 		goto err;
1839 	}
1840 	rx_chn->dma_dev = k3_udma_glue_rx_get_dma_device(rx_chn->rx_chn);
1841 
1842 	rx_chn->desc_pool = k3_cppi_desc_pool_create_name(rx_chn->dma_dev,
1843 							  rx_chn->descs_num,
1844 							  hdesc_size, "rx");
1845 	if (IS_ERR(rx_chn->desc_pool)) {
1846 		ret = PTR_ERR(rx_chn->desc_pool);
1847 		dev_err(dev, "Failed to create rx poll %d\n", ret);
1848 		goto err;
1849 	}
1850 
1851 	common->rx_flow_id_base =
1852 			k3_udma_glue_rx_get_flow_id_base(rx_chn->rx_chn);
1853 	dev_info(dev, "set new flow-id-base %u\n", common->rx_flow_id_base);
1854 
1855 	fdqring_id = K3_RINGACC_RING_ID_ANY;
1856 	for (i = 0; i < rx_cfg.flow_id_num; i++) {
1857 		struct k3_ring_cfg rxring_cfg = {
1858 			.elm_size = K3_RINGACC_RING_ELSIZE_8,
1859 			.mode = K3_RINGACC_RING_MODE_RING,
1860 			.flags = 0,
1861 		};
1862 		struct k3_ring_cfg fdqring_cfg = {
1863 			.elm_size = K3_RINGACC_RING_ELSIZE_8,
1864 			.flags = K3_RINGACC_RING_SHARED,
1865 		};
1866 		struct k3_udma_glue_rx_flow_cfg rx_flow_cfg = {
1867 			.rx_cfg = rxring_cfg,
1868 			.rxfdq_cfg = fdqring_cfg,
1869 			.ring_rxq_id = K3_RINGACC_RING_ID_ANY,
1870 			.src_tag_lo_sel =
1871 				K3_UDMA_GLUE_SRC_TAG_LO_USE_REMOTE_SRC_TAG,
1872 		};
1873 
1874 		rx_flow_cfg.ring_rxfdq0_id = fdqring_id;
1875 		rx_flow_cfg.rx_cfg.size = max_desc_num;
1876 		rx_flow_cfg.rxfdq_cfg.size = max_desc_num;
1877 		rx_flow_cfg.rxfdq_cfg.mode = common->pdata.fdqring_mode;
1878 
1879 		ret = k3_udma_glue_rx_flow_init(rx_chn->rx_chn,
1880 						i, &rx_flow_cfg);
1881 		if (ret) {
1882 			dev_err(dev, "Failed to init rx flow%d %d\n", i, ret);
1883 			goto err;
1884 		}
1885 		if (!i)
1886 			fdqring_id =
1887 				k3_udma_glue_rx_flow_get_fdq_id(rx_chn->rx_chn,
1888 								i);
1889 
1890 		rx_chn->irq = k3_udma_glue_rx_get_irq(rx_chn->rx_chn, i);
1891 
1892 		if (rx_chn->irq <= 0) {
1893 			dev_err(dev, "Failed to get rx dma irq %d\n",
1894 				rx_chn->irq);
1895 			ret = -ENXIO;
1896 			goto err;
1897 		}
1898 	}
1899 
1900 	netif_napi_add(common->dma_ndev, &common->napi_rx,
1901 		       am65_cpsw_nuss_rx_poll);
1902 
1903 	ret = devm_request_irq(dev, rx_chn->irq,
1904 			       am65_cpsw_nuss_rx_irq,
1905 			       IRQF_TRIGGER_HIGH, dev_name(dev), common);
1906 	if (ret) {
1907 		dev_err(dev, "failure requesting rx irq %u, %d\n",
1908 			rx_chn->irq, ret);
1909 		goto err;
1910 	}
1911 
1912 err:
1913 	i = devm_add_action(dev, am65_cpsw_nuss_free_rx_chns, common);
1914 	if (i) {
1915 		dev_err(dev, "Failed to add free_rx_chns action %d\n", i);
1916 		return i;
1917 	}
1918 
1919 	return ret;
1920 }
1921 
1922 static int am65_cpsw_nuss_init_host_p(struct am65_cpsw_common *common)
1923 {
1924 	struct am65_cpsw_host *host_p = am65_common_get_host(common);
1925 
1926 	host_p->common = common;
1927 	host_p->port_base = common->cpsw_base + AM65_CPSW_NU_PORTS_BASE;
1928 	host_p->stat_base = common->cpsw_base + AM65_CPSW_NU_STATS_BASE;
1929 
1930 	return 0;
1931 }
1932 
1933 static int am65_cpsw_am654_get_efuse_macid(struct device_node *of_node,
1934 					   int slave, u8 *mac_addr)
1935 {
1936 	u32 mac_lo, mac_hi, offset;
1937 	struct regmap *syscon;
1938 	int ret;
1939 
1940 	syscon = syscon_regmap_lookup_by_phandle(of_node, "ti,syscon-efuse");
1941 	if (IS_ERR(syscon)) {
1942 		if (PTR_ERR(syscon) == -ENODEV)
1943 			return 0;
1944 		return PTR_ERR(syscon);
1945 	}
1946 
1947 	ret = of_property_read_u32_index(of_node, "ti,syscon-efuse", 1,
1948 					 &offset);
1949 	if (ret)
1950 		return ret;
1951 
1952 	regmap_read(syscon, offset, &mac_lo);
1953 	regmap_read(syscon, offset + 4, &mac_hi);
1954 
1955 	mac_addr[0] = (mac_hi >> 8) & 0xff;
1956 	mac_addr[1] = mac_hi & 0xff;
1957 	mac_addr[2] = (mac_lo >> 24) & 0xff;
1958 	mac_addr[3] = (mac_lo >> 16) & 0xff;
1959 	mac_addr[4] = (mac_lo >> 8) & 0xff;
1960 	mac_addr[5] = mac_lo & 0xff;
1961 
1962 	return 0;
1963 }
1964 
1965 static int am65_cpsw_init_cpts(struct am65_cpsw_common *common)
1966 {
1967 	struct device *dev = common->dev;
1968 	struct device_node *node;
1969 	struct am65_cpts *cpts;
1970 	void __iomem *reg_base;
1971 
1972 	if (!IS_ENABLED(CONFIG_TI_K3_AM65_CPTS))
1973 		return 0;
1974 
1975 	node = of_get_child_by_name(dev->of_node, "cpts");
1976 	if (!node) {
1977 		dev_err(dev, "%s cpts not found\n", __func__);
1978 		return -ENOENT;
1979 	}
1980 
1981 	reg_base = common->cpsw_base + AM65_CPSW_NU_CPTS_BASE;
1982 	cpts = am65_cpts_create(dev, reg_base, node);
1983 	if (IS_ERR(cpts)) {
1984 		int ret = PTR_ERR(cpts);
1985 
1986 		of_node_put(node);
1987 		dev_err(dev, "cpts create err %d\n", ret);
1988 		return ret;
1989 	}
1990 	common->cpts = cpts;
1991 	/* Forbid PM runtime if CPTS is running.
1992 	 * K3 CPSWxG modules may completely lose context during ON->OFF
1993 	 * transitions depending on integration.
1994 	 * AM65x/J721E MCU CPSW2G: false
1995 	 * J721E MAIN_CPSW9G: true
1996 	 */
1997 	pm_runtime_forbid(dev);
1998 
1999 	return 0;
2000 }
2001 
2002 static int am65_cpsw_nuss_init_slave_ports(struct am65_cpsw_common *common)
2003 {
2004 	struct device_node *node, *port_np;
2005 	struct device *dev = common->dev;
2006 	int ret;
2007 
2008 	node = of_get_child_by_name(dev->of_node, "ethernet-ports");
2009 	if (!node)
2010 		return -ENOENT;
2011 
2012 	for_each_child_of_node(node, port_np) {
2013 		struct am65_cpsw_port *port;
2014 		u32 port_id;
2015 
2016 		/* it is not a slave port node, continue */
2017 		if (strcmp(port_np->name, "port"))
2018 			continue;
2019 
2020 		ret = of_property_read_u32(port_np, "reg", &port_id);
2021 		if (ret < 0) {
2022 			dev_err(dev, "%pOF error reading port_id %d\n",
2023 				port_np, ret);
2024 			goto of_node_put;
2025 		}
2026 
2027 		if (!port_id || port_id > common->port_num) {
2028 			dev_err(dev, "%pOF has invalid port_id %u %s\n",
2029 				port_np, port_id, port_np->name);
2030 			ret = -EINVAL;
2031 			goto of_node_put;
2032 		}
2033 
2034 		port = am65_common_get_port(common, port_id);
2035 		port->port_id = port_id;
2036 		port->common = common;
2037 		port->port_base = common->cpsw_base + AM65_CPSW_NU_PORTS_BASE +
2038 				  AM65_CPSW_NU_PORTS_OFFSET * (port_id);
2039 		if (common->pdata.extra_modes)
2040 			port->sgmii_base = common->ss_base + AM65_CPSW_SGMII_BASE * (port_id);
2041 		port->stat_base = common->cpsw_base + AM65_CPSW_NU_STATS_BASE +
2042 				  (AM65_CPSW_NU_STATS_PORT_OFFSET * port_id);
2043 		port->name = of_get_property(port_np, "label", NULL);
2044 		port->fetch_ram_base =
2045 				common->cpsw_base + AM65_CPSW_NU_FRAM_BASE +
2046 				(AM65_CPSW_NU_FRAM_PORT_OFFSET * (port_id - 1));
2047 
2048 		port->slave.mac_sl = cpsw_sl_get("am65", dev, port->port_base);
2049 		if (IS_ERR(port->slave.mac_sl)) {
2050 			ret = PTR_ERR(port->slave.mac_sl);
2051 			goto of_node_put;
2052 		}
2053 
2054 		port->disabled = !of_device_is_available(port_np);
2055 		if (port->disabled) {
2056 			common->disabled_ports_mask |= BIT(port->port_id);
2057 			continue;
2058 		}
2059 
2060 		port->slave.ifphy = devm_of_phy_get(dev, port_np, NULL);
2061 		if (IS_ERR(port->slave.ifphy)) {
2062 			ret = PTR_ERR(port->slave.ifphy);
2063 			dev_err(dev, "%pOF error retrieving port phy: %d\n",
2064 				port_np, ret);
2065 			goto of_node_put;
2066 		}
2067 
2068 		/* Initialize the Serdes PHY for the port */
2069 		ret = am65_cpsw_init_serdes_phy(dev, port_np, port);
2070 		if (ret)
2071 			goto of_node_put;
2072 
2073 		port->slave.mac_only =
2074 				of_property_read_bool(port_np, "ti,mac-only");
2075 
2076 		/* get phy/link info */
2077 		port->slave.phy_node = port_np;
2078 		ret = of_get_phy_mode(port_np, &port->slave.phy_if);
2079 		if (ret) {
2080 			dev_err(dev, "%pOF read phy-mode err %d\n",
2081 				port_np, ret);
2082 			goto of_node_put;
2083 		}
2084 
2085 		ret = phy_set_mode_ext(port->slave.ifphy, PHY_MODE_ETHERNET, port->slave.phy_if);
2086 		if (ret)
2087 			goto of_node_put;
2088 
2089 		ret = of_get_mac_address(port_np, port->slave.mac_addr);
2090 		if (ret) {
2091 			am65_cpsw_am654_get_efuse_macid(port_np,
2092 							port->port_id,
2093 							port->slave.mac_addr);
2094 			if (!is_valid_ether_addr(port->slave.mac_addr)) {
2095 				eth_random_addr(port->slave.mac_addr);
2096 				dev_err(dev, "Use random MAC address\n");
2097 			}
2098 		}
2099 	}
2100 	of_node_put(node);
2101 
2102 	/* is there at least one ext.port */
2103 	if (!(~common->disabled_ports_mask & GENMASK(common->port_num, 1))) {
2104 		dev_err(dev, "No Ext. port are available\n");
2105 		return -ENODEV;
2106 	}
2107 
2108 	return 0;
2109 
2110 of_node_put:
2111 	of_node_put(port_np);
2112 	of_node_put(node);
2113 	return ret;
2114 }
2115 
2116 static void am65_cpsw_pcpu_stats_free(void *data)
2117 {
2118 	struct am65_cpsw_ndev_stats __percpu *stats = data;
2119 
2120 	free_percpu(stats);
2121 }
2122 
2123 static void am65_cpsw_nuss_phylink_cleanup(struct am65_cpsw_common *common)
2124 {
2125 	struct am65_cpsw_port *port;
2126 	int i;
2127 
2128 	for (i = 0; i < common->port_num; i++) {
2129 		port = &common->ports[i];
2130 		if (port->slave.phylink)
2131 			phylink_destroy(port->slave.phylink);
2132 	}
2133 }
2134 
2135 static int
2136 am65_cpsw_nuss_init_port_ndev(struct am65_cpsw_common *common, u32 port_idx)
2137 {
2138 	struct am65_cpsw_ndev_priv *ndev_priv;
2139 	struct device *dev = common->dev;
2140 	struct am65_cpsw_port *port;
2141 	struct phylink *phylink;
2142 	int ret;
2143 
2144 	port = &common->ports[port_idx];
2145 
2146 	if (port->disabled)
2147 		return 0;
2148 
2149 	/* alloc netdev */
2150 	port->ndev = devm_alloc_etherdev_mqs(common->dev,
2151 					     sizeof(struct am65_cpsw_ndev_priv),
2152 					     AM65_CPSW_MAX_TX_QUEUES,
2153 					     AM65_CPSW_MAX_RX_QUEUES);
2154 	if (!port->ndev) {
2155 		dev_err(dev, "error allocating slave net_device %u\n",
2156 			port->port_id);
2157 		return -ENOMEM;
2158 	}
2159 
2160 	ndev_priv = netdev_priv(port->ndev);
2161 	ndev_priv->port = port;
2162 	ndev_priv->msg_enable = AM65_CPSW_DEBUG;
2163 	SET_NETDEV_DEV(port->ndev, dev);
2164 
2165 	eth_hw_addr_set(port->ndev, port->slave.mac_addr);
2166 
2167 	port->ndev->min_mtu = AM65_CPSW_MIN_PACKET_SIZE;
2168 	port->ndev->max_mtu = AM65_CPSW_MAX_PACKET_SIZE;
2169 	port->ndev->hw_features = NETIF_F_SG |
2170 				  NETIF_F_RXCSUM |
2171 				  NETIF_F_HW_CSUM |
2172 				  NETIF_F_HW_TC;
2173 	port->ndev->features = port->ndev->hw_features |
2174 			       NETIF_F_HW_VLAN_CTAG_FILTER;
2175 	port->ndev->vlan_features |=  NETIF_F_SG;
2176 	port->ndev->netdev_ops = &am65_cpsw_nuss_netdev_ops;
2177 	port->ndev->ethtool_ops = &am65_cpsw_ethtool_ops_slave;
2178 
2179 	/* Configuring Phylink */
2180 	port->slave.phylink_config.dev = &port->ndev->dev;
2181 	port->slave.phylink_config.type = PHYLINK_NETDEV;
2182 	port->slave.phylink_config.mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 |
2183 						      MAC_1000FD | MAC_5000FD;
2184 	port->slave.phylink_config.mac_managed_pm = true; /* MAC does PM */
2185 
2186 	switch (port->slave.phy_if) {
2187 	case PHY_INTERFACE_MODE_RGMII:
2188 	case PHY_INTERFACE_MODE_RGMII_ID:
2189 	case PHY_INTERFACE_MODE_RGMII_RXID:
2190 	case PHY_INTERFACE_MODE_RGMII_TXID:
2191 		phy_interface_set_rgmii(port->slave.phylink_config.supported_interfaces);
2192 		break;
2193 
2194 	case PHY_INTERFACE_MODE_RMII:
2195 		__set_bit(PHY_INTERFACE_MODE_RMII,
2196 			  port->slave.phylink_config.supported_interfaces);
2197 		break;
2198 
2199 	case PHY_INTERFACE_MODE_QSGMII:
2200 	case PHY_INTERFACE_MODE_SGMII:
2201 	case PHY_INTERFACE_MODE_USXGMII:
2202 		if (common->pdata.extra_modes & BIT(port->slave.phy_if)) {
2203 			__set_bit(port->slave.phy_if,
2204 				  port->slave.phylink_config.supported_interfaces);
2205 		} else {
2206 			dev_err(dev, "selected phy-mode is not supported\n");
2207 			return -EOPNOTSUPP;
2208 		}
2209 		break;
2210 
2211 	default:
2212 		dev_err(dev, "selected phy-mode is not supported\n");
2213 		return -EOPNOTSUPP;
2214 	}
2215 
2216 	phylink = phylink_create(&port->slave.phylink_config,
2217 				 of_node_to_fwnode(port->slave.phy_node),
2218 				 port->slave.phy_if,
2219 				 &am65_cpsw_phylink_mac_ops);
2220 	if (IS_ERR(phylink))
2221 		return PTR_ERR(phylink);
2222 
2223 	port->slave.phylink = phylink;
2224 
2225 	/* Disable TX checksum offload by default due to HW bug */
2226 	if (common->pdata.quirks & AM65_CPSW_QUIRK_I2027_NO_TX_CSUM)
2227 		port->ndev->features &= ~NETIF_F_HW_CSUM;
2228 
2229 	ndev_priv->stats = netdev_alloc_pcpu_stats(struct am65_cpsw_ndev_stats);
2230 	if (!ndev_priv->stats)
2231 		return -ENOMEM;
2232 
2233 	ret = devm_add_action_or_reset(dev, am65_cpsw_pcpu_stats_free,
2234 				       ndev_priv->stats);
2235 	if (ret)
2236 		dev_err(dev, "failed to add percpu stat free action %d\n", ret);
2237 
2238 	if (!common->dma_ndev)
2239 		common->dma_ndev = port->ndev;
2240 
2241 	return ret;
2242 }
2243 
2244 static int am65_cpsw_nuss_init_ndevs(struct am65_cpsw_common *common)
2245 {
2246 	int ret;
2247 	int i;
2248 
2249 	for (i = 0; i < common->port_num; i++) {
2250 		ret = am65_cpsw_nuss_init_port_ndev(common, i);
2251 		if (ret)
2252 			return ret;
2253 	}
2254 
2255 	return ret;
2256 }
2257 
2258 static void am65_cpsw_nuss_cleanup_ndev(struct am65_cpsw_common *common)
2259 {
2260 	struct am65_cpsw_port *port;
2261 	int i;
2262 
2263 	for (i = 0; i < common->port_num; i++) {
2264 		port = &common->ports[i];
2265 		if (port->ndev && port->ndev->reg_state == NETREG_REGISTERED)
2266 			unregister_netdev(port->ndev);
2267 	}
2268 }
2269 
2270 static void am65_cpsw_port_offload_fwd_mark_update(struct am65_cpsw_common *common)
2271 {
2272 	int set_val = 0;
2273 	int i;
2274 
2275 	if (common->br_members == (GENMASK(common->port_num, 1) & ~common->disabled_ports_mask))
2276 		set_val = 1;
2277 
2278 	dev_dbg(common->dev, "set offload_fwd_mark %d\n", set_val);
2279 
2280 	for (i = 1; i <= common->port_num; i++) {
2281 		struct am65_cpsw_port *port = am65_common_get_port(common, i);
2282 		struct am65_cpsw_ndev_priv *priv;
2283 
2284 		if (!port->ndev)
2285 			continue;
2286 
2287 		priv = am65_ndev_to_priv(port->ndev);
2288 		priv->offload_fwd_mark = set_val;
2289 	}
2290 }
2291 
2292 bool am65_cpsw_port_dev_check(const struct net_device *ndev)
2293 {
2294 	if (ndev->netdev_ops == &am65_cpsw_nuss_netdev_ops) {
2295 		struct am65_cpsw_common *common = am65_ndev_to_common(ndev);
2296 
2297 		return !common->is_emac_mode;
2298 	}
2299 
2300 	return false;
2301 }
2302 
2303 static int am65_cpsw_netdevice_port_link(struct net_device *ndev,
2304 					 struct net_device *br_ndev,
2305 					 struct netlink_ext_ack *extack)
2306 {
2307 	struct am65_cpsw_common *common = am65_ndev_to_common(ndev);
2308 	struct am65_cpsw_ndev_priv *priv = am65_ndev_to_priv(ndev);
2309 	int err;
2310 
2311 	if (!common->br_members) {
2312 		common->hw_bridge_dev = br_ndev;
2313 	} else {
2314 		/* This is adding the port to a second bridge, this is
2315 		 * unsupported
2316 		 */
2317 		if (common->hw_bridge_dev != br_ndev)
2318 			return -EOPNOTSUPP;
2319 	}
2320 
2321 	err = switchdev_bridge_port_offload(ndev, ndev, NULL, NULL, NULL,
2322 					    false, extack);
2323 	if (err)
2324 		return err;
2325 
2326 	common->br_members |= BIT(priv->port->port_id);
2327 
2328 	am65_cpsw_port_offload_fwd_mark_update(common);
2329 
2330 	return NOTIFY_DONE;
2331 }
2332 
2333 static void am65_cpsw_netdevice_port_unlink(struct net_device *ndev)
2334 {
2335 	struct am65_cpsw_common *common = am65_ndev_to_common(ndev);
2336 	struct am65_cpsw_ndev_priv *priv = am65_ndev_to_priv(ndev);
2337 
2338 	switchdev_bridge_port_unoffload(ndev, NULL, NULL, NULL);
2339 
2340 	common->br_members &= ~BIT(priv->port->port_id);
2341 
2342 	am65_cpsw_port_offload_fwd_mark_update(common);
2343 
2344 	if (!common->br_members)
2345 		common->hw_bridge_dev = NULL;
2346 }
2347 
2348 /* netdev notifier */
2349 static int am65_cpsw_netdevice_event(struct notifier_block *unused,
2350 				     unsigned long event, void *ptr)
2351 {
2352 	struct netlink_ext_ack *extack = netdev_notifier_info_to_extack(ptr);
2353 	struct net_device *ndev = netdev_notifier_info_to_dev(ptr);
2354 	struct netdev_notifier_changeupper_info *info;
2355 	int ret = NOTIFY_DONE;
2356 
2357 	if (!am65_cpsw_port_dev_check(ndev))
2358 		return NOTIFY_DONE;
2359 
2360 	switch (event) {
2361 	case NETDEV_CHANGEUPPER:
2362 		info = ptr;
2363 
2364 		if (netif_is_bridge_master(info->upper_dev)) {
2365 			if (info->linking)
2366 				ret = am65_cpsw_netdevice_port_link(ndev,
2367 								    info->upper_dev,
2368 								    extack);
2369 			else
2370 				am65_cpsw_netdevice_port_unlink(ndev);
2371 		}
2372 		break;
2373 	default:
2374 		return NOTIFY_DONE;
2375 	}
2376 
2377 	return notifier_from_errno(ret);
2378 }
2379 
2380 static int am65_cpsw_register_notifiers(struct am65_cpsw_common *cpsw)
2381 {
2382 	int ret = 0;
2383 
2384 	if (AM65_CPSW_IS_CPSW2G(cpsw) ||
2385 	    !IS_REACHABLE(CONFIG_TI_K3_AM65_CPSW_SWITCHDEV))
2386 		return 0;
2387 
2388 	cpsw->am65_cpsw_netdevice_nb.notifier_call = &am65_cpsw_netdevice_event;
2389 	ret = register_netdevice_notifier(&cpsw->am65_cpsw_netdevice_nb);
2390 	if (ret) {
2391 		dev_err(cpsw->dev, "can't register netdevice notifier\n");
2392 		return ret;
2393 	}
2394 
2395 	ret = am65_cpsw_switchdev_register_notifiers(cpsw);
2396 	if (ret)
2397 		unregister_netdevice_notifier(&cpsw->am65_cpsw_netdevice_nb);
2398 
2399 	return ret;
2400 }
2401 
2402 static void am65_cpsw_unregister_notifiers(struct am65_cpsw_common *cpsw)
2403 {
2404 	if (AM65_CPSW_IS_CPSW2G(cpsw) ||
2405 	    !IS_REACHABLE(CONFIG_TI_K3_AM65_CPSW_SWITCHDEV))
2406 		return;
2407 
2408 	am65_cpsw_switchdev_unregister_notifiers(cpsw);
2409 	unregister_netdevice_notifier(&cpsw->am65_cpsw_netdevice_nb);
2410 }
2411 
2412 static const struct devlink_ops am65_cpsw_devlink_ops = {};
2413 
2414 static void am65_cpsw_init_stp_ale_entry(struct am65_cpsw_common *cpsw)
2415 {
2416 	cpsw_ale_add_mcast(cpsw->ale, eth_stp_addr, ALE_PORT_HOST, ALE_SUPER, 0,
2417 			   ALE_MCAST_BLOCK_LEARN_FWD);
2418 }
2419 
2420 static void am65_cpsw_init_host_port_switch(struct am65_cpsw_common *common)
2421 {
2422 	struct am65_cpsw_host *host = am65_common_get_host(common);
2423 
2424 	writel(common->default_vlan, host->port_base + AM65_CPSW_PORT_VLAN_REG_OFFSET);
2425 
2426 	am65_cpsw_init_stp_ale_entry(common);
2427 
2428 	cpsw_ale_control_set(common->ale, HOST_PORT_NUM, ALE_P0_UNI_FLOOD, 1);
2429 	dev_dbg(common->dev, "Set P0_UNI_FLOOD\n");
2430 	cpsw_ale_control_set(common->ale, HOST_PORT_NUM, ALE_PORT_NOLEARN, 0);
2431 }
2432 
2433 static void am65_cpsw_init_host_port_emac(struct am65_cpsw_common *common)
2434 {
2435 	struct am65_cpsw_host *host = am65_common_get_host(common);
2436 
2437 	writel(0, host->port_base + AM65_CPSW_PORT_VLAN_REG_OFFSET);
2438 
2439 	cpsw_ale_control_set(common->ale, HOST_PORT_NUM, ALE_P0_UNI_FLOOD, 0);
2440 	dev_dbg(common->dev, "unset P0_UNI_FLOOD\n");
2441 
2442 	/* learning make no sense in multi-mac mode */
2443 	cpsw_ale_control_set(common->ale, HOST_PORT_NUM, ALE_PORT_NOLEARN, 1);
2444 }
2445 
2446 static int am65_cpsw_dl_switch_mode_get(struct devlink *dl, u32 id,
2447 					struct devlink_param_gset_ctx *ctx)
2448 {
2449 	struct am65_cpsw_devlink *dl_priv = devlink_priv(dl);
2450 	struct am65_cpsw_common *common = dl_priv->common;
2451 
2452 	dev_dbg(common->dev, "%s id:%u\n", __func__, id);
2453 
2454 	if (id != AM65_CPSW_DL_PARAM_SWITCH_MODE)
2455 		return -EOPNOTSUPP;
2456 
2457 	ctx->val.vbool = !common->is_emac_mode;
2458 
2459 	return 0;
2460 }
2461 
2462 static void am65_cpsw_init_port_emac_ale(struct  am65_cpsw_port *port)
2463 {
2464 	struct am65_cpsw_slave_data *slave = &port->slave;
2465 	struct am65_cpsw_common *common = port->common;
2466 	u32 port_mask;
2467 
2468 	writel(slave->port_vlan, port->port_base + AM65_CPSW_PORT_VLAN_REG_OFFSET);
2469 
2470 	if (slave->mac_only)
2471 		/* enable mac-only mode on port */
2472 		cpsw_ale_control_set(common->ale, port->port_id,
2473 				     ALE_PORT_MACONLY, 1);
2474 
2475 	cpsw_ale_control_set(common->ale, port->port_id, ALE_PORT_NOLEARN, 1);
2476 
2477 	port_mask = BIT(port->port_id) | ALE_PORT_HOST;
2478 
2479 	cpsw_ale_add_ucast(common->ale, port->ndev->dev_addr,
2480 			   HOST_PORT_NUM, ALE_SECURE, slave->port_vlan);
2481 	cpsw_ale_add_mcast(common->ale, port->ndev->broadcast,
2482 			   port_mask, ALE_VLAN, slave->port_vlan, ALE_MCAST_FWD_2);
2483 }
2484 
2485 static void am65_cpsw_init_port_switch_ale(struct am65_cpsw_port *port)
2486 {
2487 	struct am65_cpsw_slave_data *slave = &port->slave;
2488 	struct am65_cpsw_common *cpsw = port->common;
2489 	u32 port_mask;
2490 
2491 	cpsw_ale_control_set(cpsw->ale, port->port_id,
2492 			     ALE_PORT_NOLEARN, 0);
2493 
2494 	cpsw_ale_add_ucast(cpsw->ale, port->ndev->dev_addr,
2495 			   HOST_PORT_NUM, ALE_SECURE | ALE_BLOCKED | ALE_VLAN,
2496 			   slave->port_vlan);
2497 
2498 	port_mask = BIT(port->port_id) | ALE_PORT_HOST;
2499 
2500 	cpsw_ale_add_mcast(cpsw->ale, port->ndev->broadcast,
2501 			   port_mask, ALE_VLAN, slave->port_vlan,
2502 			   ALE_MCAST_FWD_2);
2503 
2504 	writel(slave->port_vlan, port->port_base + AM65_CPSW_PORT_VLAN_REG_OFFSET);
2505 
2506 	cpsw_ale_control_set(cpsw->ale, port->port_id,
2507 			     ALE_PORT_MACONLY, 0);
2508 }
2509 
2510 static int am65_cpsw_dl_switch_mode_set(struct devlink *dl, u32 id,
2511 					struct devlink_param_gset_ctx *ctx)
2512 {
2513 	struct am65_cpsw_devlink *dl_priv = devlink_priv(dl);
2514 	struct am65_cpsw_common *cpsw = dl_priv->common;
2515 	bool switch_en = ctx->val.vbool;
2516 	bool if_running = false;
2517 	int i;
2518 
2519 	dev_dbg(cpsw->dev, "%s id:%u\n", __func__, id);
2520 
2521 	if (id != AM65_CPSW_DL_PARAM_SWITCH_MODE)
2522 		return -EOPNOTSUPP;
2523 
2524 	if (switch_en == !cpsw->is_emac_mode)
2525 		return 0;
2526 
2527 	if (!switch_en && cpsw->br_members) {
2528 		dev_err(cpsw->dev, "Remove ports from bridge before disabling switch mode\n");
2529 		return -EINVAL;
2530 	}
2531 
2532 	rtnl_lock();
2533 
2534 	cpsw->is_emac_mode = !switch_en;
2535 
2536 	for (i = 0; i < cpsw->port_num; i++) {
2537 		struct net_device *sl_ndev = cpsw->ports[i].ndev;
2538 
2539 		if (!sl_ndev || !netif_running(sl_ndev))
2540 			continue;
2541 
2542 		if_running = true;
2543 	}
2544 
2545 	if (!if_running) {
2546 		/* all ndevs are down */
2547 		for (i = 0; i < cpsw->port_num; i++) {
2548 			struct net_device *sl_ndev = cpsw->ports[i].ndev;
2549 			struct am65_cpsw_slave_data *slave;
2550 
2551 			if (!sl_ndev)
2552 				continue;
2553 
2554 			slave = am65_ndev_to_slave(sl_ndev);
2555 			if (switch_en)
2556 				slave->port_vlan = cpsw->default_vlan;
2557 			else
2558 				slave->port_vlan = 0;
2559 		}
2560 
2561 		goto exit;
2562 	}
2563 
2564 	cpsw_ale_control_set(cpsw->ale, 0, ALE_BYPASS, 1);
2565 	/* clean up ALE table */
2566 	cpsw_ale_control_set(cpsw->ale, HOST_PORT_NUM, ALE_CLEAR, 1);
2567 	cpsw_ale_control_get(cpsw->ale, HOST_PORT_NUM, ALE_AGEOUT);
2568 
2569 	if (switch_en) {
2570 		dev_info(cpsw->dev, "Enable switch mode\n");
2571 
2572 		am65_cpsw_init_host_port_switch(cpsw);
2573 
2574 		for (i = 0; i < cpsw->port_num; i++) {
2575 			struct net_device *sl_ndev = cpsw->ports[i].ndev;
2576 			struct am65_cpsw_slave_data *slave;
2577 			struct am65_cpsw_port *port;
2578 
2579 			if (!sl_ndev)
2580 				continue;
2581 
2582 			port = am65_ndev_to_port(sl_ndev);
2583 			slave = am65_ndev_to_slave(sl_ndev);
2584 			slave->port_vlan = cpsw->default_vlan;
2585 
2586 			if (netif_running(sl_ndev))
2587 				am65_cpsw_init_port_switch_ale(port);
2588 		}
2589 
2590 	} else {
2591 		dev_info(cpsw->dev, "Disable switch mode\n");
2592 
2593 		am65_cpsw_init_host_port_emac(cpsw);
2594 
2595 		for (i = 0; i < cpsw->port_num; i++) {
2596 			struct net_device *sl_ndev = cpsw->ports[i].ndev;
2597 			struct am65_cpsw_port *port;
2598 
2599 			if (!sl_ndev)
2600 				continue;
2601 
2602 			port = am65_ndev_to_port(sl_ndev);
2603 			port->slave.port_vlan = 0;
2604 			if (netif_running(sl_ndev))
2605 				am65_cpsw_init_port_emac_ale(port);
2606 		}
2607 	}
2608 	cpsw_ale_control_set(cpsw->ale, HOST_PORT_NUM, ALE_BYPASS, 0);
2609 exit:
2610 	rtnl_unlock();
2611 
2612 	return 0;
2613 }
2614 
2615 static const struct devlink_param am65_cpsw_devlink_params[] = {
2616 	DEVLINK_PARAM_DRIVER(AM65_CPSW_DL_PARAM_SWITCH_MODE, "switch_mode",
2617 			     DEVLINK_PARAM_TYPE_BOOL,
2618 			     BIT(DEVLINK_PARAM_CMODE_RUNTIME),
2619 			     am65_cpsw_dl_switch_mode_get,
2620 			     am65_cpsw_dl_switch_mode_set, NULL),
2621 };
2622 
2623 static int am65_cpsw_nuss_register_devlink(struct am65_cpsw_common *common)
2624 {
2625 	struct devlink_port_attrs attrs = {};
2626 	struct am65_cpsw_devlink *dl_priv;
2627 	struct device *dev = common->dev;
2628 	struct devlink_port *dl_port;
2629 	struct am65_cpsw_port *port;
2630 	int ret = 0;
2631 	int i;
2632 
2633 	common->devlink =
2634 		devlink_alloc(&am65_cpsw_devlink_ops, sizeof(*dl_priv), dev);
2635 	if (!common->devlink)
2636 		return -ENOMEM;
2637 
2638 	dl_priv = devlink_priv(common->devlink);
2639 	dl_priv->common = common;
2640 
2641 	/* Provide devlink hook to switch mode when multiple external ports
2642 	 * are present NUSS switchdev driver is enabled.
2643 	 */
2644 	if (!AM65_CPSW_IS_CPSW2G(common) &&
2645 	    IS_ENABLED(CONFIG_TI_K3_AM65_CPSW_SWITCHDEV)) {
2646 		ret = devlink_params_register(common->devlink,
2647 					      am65_cpsw_devlink_params,
2648 					      ARRAY_SIZE(am65_cpsw_devlink_params));
2649 		if (ret) {
2650 			dev_err(dev, "devlink params reg fail ret:%d\n", ret);
2651 			goto dl_unreg;
2652 		}
2653 	}
2654 
2655 	for (i = 1; i <= common->port_num; i++) {
2656 		port = am65_common_get_port(common, i);
2657 		dl_port = &port->devlink_port;
2658 
2659 		if (port->ndev)
2660 			attrs.flavour = DEVLINK_PORT_FLAVOUR_PHYSICAL;
2661 		else
2662 			attrs.flavour = DEVLINK_PORT_FLAVOUR_UNUSED;
2663 		attrs.phys.port_number = port->port_id;
2664 		attrs.switch_id.id_len = sizeof(resource_size_t);
2665 		memcpy(attrs.switch_id.id, common->switch_id, attrs.switch_id.id_len);
2666 		devlink_port_attrs_set(dl_port, &attrs);
2667 
2668 		ret = devlink_port_register(common->devlink, dl_port, port->port_id);
2669 		if (ret) {
2670 			dev_err(dev, "devlink_port reg fail for port %d, ret:%d\n",
2671 				port->port_id, ret);
2672 			goto dl_port_unreg;
2673 		}
2674 	}
2675 	devlink_register(common->devlink);
2676 	return ret;
2677 
2678 dl_port_unreg:
2679 	for (i = i - 1; i >= 1; i--) {
2680 		port = am65_common_get_port(common, i);
2681 		dl_port = &port->devlink_port;
2682 
2683 		devlink_port_unregister(dl_port);
2684 	}
2685 dl_unreg:
2686 	devlink_free(common->devlink);
2687 	return ret;
2688 }
2689 
2690 static void am65_cpsw_unregister_devlink(struct am65_cpsw_common *common)
2691 {
2692 	struct devlink_port *dl_port;
2693 	struct am65_cpsw_port *port;
2694 	int i;
2695 
2696 	devlink_unregister(common->devlink);
2697 
2698 	for (i = 1; i <= common->port_num; i++) {
2699 		port = am65_common_get_port(common, i);
2700 		dl_port = &port->devlink_port;
2701 
2702 		devlink_port_unregister(dl_port);
2703 	}
2704 
2705 	if (!AM65_CPSW_IS_CPSW2G(common) &&
2706 	    IS_ENABLED(CONFIG_TI_K3_AM65_CPSW_SWITCHDEV))
2707 		devlink_params_unregister(common->devlink,
2708 					  am65_cpsw_devlink_params,
2709 					  ARRAY_SIZE(am65_cpsw_devlink_params));
2710 
2711 	devlink_free(common->devlink);
2712 }
2713 
2714 static int am65_cpsw_nuss_register_ndevs(struct am65_cpsw_common *common)
2715 {
2716 	struct device *dev = common->dev;
2717 	struct am65_cpsw_port *port;
2718 	int ret = 0, i;
2719 
2720 	/* init tx channels */
2721 	ret = am65_cpsw_nuss_init_tx_chns(common);
2722 	if (ret)
2723 		return ret;
2724 	ret = am65_cpsw_nuss_init_rx_chns(common);
2725 	if (ret)
2726 		return ret;
2727 
2728 	ret = am65_cpsw_nuss_register_devlink(common);
2729 	if (ret)
2730 		return ret;
2731 
2732 	for (i = 0; i < common->port_num; i++) {
2733 		port = &common->ports[i];
2734 
2735 		if (!port->ndev)
2736 			continue;
2737 
2738 		SET_NETDEV_DEVLINK_PORT(port->ndev, &port->devlink_port);
2739 
2740 		ret = register_netdev(port->ndev);
2741 		if (ret) {
2742 			dev_err(dev, "error registering slave net device%i %d\n",
2743 				i, ret);
2744 			goto err_cleanup_ndev;
2745 		}
2746 	}
2747 
2748 	ret = am65_cpsw_register_notifiers(common);
2749 	if (ret)
2750 		goto err_cleanup_ndev;
2751 
2752 	/* can't auto unregister ndev using devm_add_action() due to
2753 	 * devres release sequence in DD core for DMA
2754 	 */
2755 
2756 	return 0;
2757 
2758 err_cleanup_ndev:
2759 	am65_cpsw_nuss_cleanup_ndev(common);
2760 	am65_cpsw_unregister_devlink(common);
2761 
2762 	return ret;
2763 }
2764 
2765 int am65_cpsw_nuss_update_tx_chns(struct am65_cpsw_common *common, int num_tx)
2766 {
2767 	int ret;
2768 
2769 	common->tx_ch_num = num_tx;
2770 	ret = am65_cpsw_nuss_init_tx_chns(common);
2771 
2772 	return ret;
2773 }
2774 
2775 struct am65_cpsw_soc_pdata {
2776 	u32	quirks_dis;
2777 };
2778 
2779 static const struct am65_cpsw_soc_pdata am65x_soc_sr2_0 = {
2780 	.quirks_dis = AM65_CPSW_QUIRK_I2027_NO_TX_CSUM,
2781 };
2782 
2783 static const struct soc_device_attribute am65_cpsw_socinfo[] = {
2784 	{ .family = "AM65X",
2785 	  .revision = "SR2.0",
2786 	  .data = &am65x_soc_sr2_0
2787 	},
2788 	{/* sentinel */}
2789 };
2790 
2791 static const struct am65_cpsw_pdata am65x_sr1_0 = {
2792 	.quirks = AM65_CPSW_QUIRK_I2027_NO_TX_CSUM,
2793 	.ale_dev_id = "am65x-cpsw2g",
2794 	.fdqring_mode = K3_RINGACC_RING_MODE_MESSAGE,
2795 };
2796 
2797 static const struct am65_cpsw_pdata j721e_pdata = {
2798 	.quirks = 0,
2799 	.ale_dev_id = "am65x-cpsw2g",
2800 	.fdqring_mode = K3_RINGACC_RING_MODE_MESSAGE,
2801 };
2802 
2803 static const struct am65_cpsw_pdata am64x_cpswxg_pdata = {
2804 	.quirks = AM64_CPSW_QUIRK_DMA_RX_TDOWN_IRQ,
2805 	.ale_dev_id = "am64-cpswxg",
2806 	.fdqring_mode = K3_RINGACC_RING_MODE_RING,
2807 };
2808 
2809 static const struct am65_cpsw_pdata j7200_cpswxg_pdata = {
2810 	.quirks = 0,
2811 	.ale_dev_id = "am64-cpswxg",
2812 	.fdqring_mode = K3_RINGACC_RING_MODE_RING,
2813 	.extra_modes = BIT(PHY_INTERFACE_MODE_QSGMII) | BIT(PHY_INTERFACE_MODE_SGMII),
2814 };
2815 
2816 static const struct am65_cpsw_pdata j721e_cpswxg_pdata = {
2817 	.quirks = 0,
2818 	.ale_dev_id = "am64-cpswxg",
2819 	.fdqring_mode = K3_RINGACC_RING_MODE_MESSAGE,
2820 	.extra_modes = BIT(PHY_INTERFACE_MODE_QSGMII) | BIT(PHY_INTERFACE_MODE_SGMII),
2821 };
2822 
2823 static const struct am65_cpsw_pdata j784s4_cpswxg_pdata = {
2824 	.quirks = 0,
2825 	.ale_dev_id = "am64-cpswxg",
2826 	.fdqring_mode = K3_RINGACC_RING_MODE_MESSAGE,
2827 	.extra_modes = BIT(PHY_INTERFACE_MODE_QSGMII) | BIT(PHY_INTERFACE_MODE_USXGMII),
2828 };
2829 
2830 static const struct of_device_id am65_cpsw_nuss_of_mtable[] = {
2831 	{ .compatible = "ti,am654-cpsw-nuss", .data = &am65x_sr1_0},
2832 	{ .compatible = "ti,j721e-cpsw-nuss", .data = &j721e_pdata},
2833 	{ .compatible = "ti,am642-cpsw-nuss", .data = &am64x_cpswxg_pdata},
2834 	{ .compatible = "ti,j7200-cpswxg-nuss", .data = &j7200_cpswxg_pdata},
2835 	{ .compatible = "ti,j721e-cpswxg-nuss", .data = &j721e_cpswxg_pdata},
2836 	{ .compatible = "ti,j784s4-cpswxg-nuss", .data = &j784s4_cpswxg_pdata},
2837 	{ /* sentinel */ },
2838 };
2839 MODULE_DEVICE_TABLE(of, am65_cpsw_nuss_of_mtable);
2840 
2841 static void am65_cpsw_nuss_apply_socinfo(struct am65_cpsw_common *common)
2842 {
2843 	const struct soc_device_attribute *soc;
2844 
2845 	soc = soc_device_match(am65_cpsw_socinfo);
2846 	if (soc && soc->data) {
2847 		const struct am65_cpsw_soc_pdata *socdata = soc->data;
2848 
2849 		/* disable quirks */
2850 		common->pdata.quirks &= ~socdata->quirks_dis;
2851 	}
2852 }
2853 
2854 static int am65_cpsw_nuss_probe(struct platform_device *pdev)
2855 {
2856 	struct cpsw_ale_params ale_params = { 0 };
2857 	const struct of_device_id *of_id;
2858 	struct device *dev = &pdev->dev;
2859 	struct am65_cpsw_common *common;
2860 	struct device_node *node;
2861 	struct resource *res;
2862 	struct clk *clk;
2863 	u64 id_temp;
2864 	int ret, i;
2865 	int ale_entries;
2866 
2867 	common = devm_kzalloc(dev, sizeof(struct am65_cpsw_common), GFP_KERNEL);
2868 	if (!common)
2869 		return -ENOMEM;
2870 	common->dev = dev;
2871 
2872 	of_id = of_match_device(am65_cpsw_nuss_of_mtable, dev);
2873 	if (!of_id)
2874 		return -EINVAL;
2875 	common->pdata = *(const struct am65_cpsw_pdata *)of_id->data;
2876 
2877 	am65_cpsw_nuss_apply_socinfo(common);
2878 
2879 	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cpsw_nuss");
2880 	common->ss_base = devm_ioremap_resource(&pdev->dev, res);
2881 	if (IS_ERR(common->ss_base))
2882 		return PTR_ERR(common->ss_base);
2883 	common->cpsw_base = common->ss_base + AM65_CPSW_CPSW_NU_BASE;
2884 	/* Use device's physical base address as switch id */
2885 	id_temp = cpu_to_be64(res->start);
2886 	memcpy(common->switch_id, &id_temp, sizeof(res->start));
2887 
2888 	node = of_get_child_by_name(dev->of_node, "ethernet-ports");
2889 	if (!node)
2890 		return -ENOENT;
2891 	common->port_num = of_get_child_count(node);
2892 	of_node_put(node);
2893 	if (common->port_num < 1 || common->port_num > AM65_CPSW_MAX_PORTS)
2894 		return -ENOENT;
2895 
2896 	common->rx_flow_id_base = -1;
2897 	init_completion(&common->tdown_complete);
2898 	common->tx_ch_num = 1;
2899 	common->pf_p0_rx_ptype_rrobin = false;
2900 	common->default_vlan = 1;
2901 
2902 	common->ports = devm_kcalloc(dev, common->port_num,
2903 				     sizeof(*common->ports),
2904 				     GFP_KERNEL);
2905 	if (!common->ports)
2906 		return -ENOMEM;
2907 
2908 	clk = devm_clk_get(dev, "fck");
2909 	if (IS_ERR(clk))
2910 		return dev_err_probe(dev, PTR_ERR(clk), "getting fck clock\n");
2911 	common->bus_freq = clk_get_rate(clk);
2912 
2913 	pm_runtime_enable(dev);
2914 	ret = pm_runtime_resume_and_get(dev);
2915 	if (ret < 0) {
2916 		pm_runtime_disable(dev);
2917 		return ret;
2918 	}
2919 
2920 	node = of_get_child_by_name(dev->of_node, "mdio");
2921 	if (!node) {
2922 		dev_warn(dev, "MDIO node not found\n");
2923 	} else if (of_device_is_available(node)) {
2924 		struct platform_device *mdio_pdev;
2925 
2926 		mdio_pdev = of_platform_device_create(node, NULL, dev);
2927 		if (!mdio_pdev) {
2928 			ret = -ENODEV;
2929 			goto err_pm_clear;
2930 		}
2931 
2932 		common->mdio_dev =  &mdio_pdev->dev;
2933 	}
2934 	of_node_put(node);
2935 
2936 	am65_cpsw_nuss_get_ver(common);
2937 
2938 	ret = am65_cpsw_nuss_init_host_p(common);
2939 	if (ret)
2940 		goto err_of_clear;
2941 
2942 	ret = am65_cpsw_nuss_init_slave_ports(common);
2943 	if (ret)
2944 		goto err_of_clear;
2945 
2946 	/* init common data */
2947 	ale_params.dev = dev;
2948 	ale_params.ale_ageout = AM65_CPSW_ALE_AGEOUT_DEFAULT;
2949 	ale_params.ale_ports = common->port_num + 1;
2950 	ale_params.ale_regs = common->cpsw_base + AM65_CPSW_NU_ALE_BASE;
2951 	ale_params.dev_id = common->pdata.ale_dev_id;
2952 	ale_params.bus_freq = common->bus_freq;
2953 
2954 	common->ale = cpsw_ale_create(&ale_params);
2955 	if (IS_ERR(common->ale)) {
2956 		dev_err(dev, "error initializing ale engine\n");
2957 		ret = PTR_ERR(common->ale);
2958 		goto err_of_clear;
2959 	}
2960 
2961 	ale_entries = common->ale->params.ale_entries;
2962 	common->ale_context = devm_kzalloc(dev,
2963 					   ale_entries * ALE_ENTRY_WORDS * sizeof(u32),
2964 					   GFP_KERNEL);
2965 	ret = am65_cpsw_init_cpts(common);
2966 	if (ret)
2967 		goto err_of_clear;
2968 
2969 	/* init ports */
2970 	for (i = 0; i < common->port_num; i++)
2971 		am65_cpsw_nuss_slave_disable_unused(&common->ports[i]);
2972 
2973 	dev_set_drvdata(dev, common);
2974 
2975 	common->is_emac_mode = true;
2976 
2977 	ret = am65_cpsw_nuss_init_ndevs(common);
2978 	if (ret)
2979 		goto err_free_phylink;
2980 
2981 	ret = am65_cpsw_nuss_register_ndevs(common);
2982 	if (ret)
2983 		goto err_free_phylink;
2984 
2985 	pm_runtime_put(dev);
2986 	return 0;
2987 
2988 err_free_phylink:
2989 	am65_cpsw_nuss_phylink_cleanup(common);
2990 	am65_cpts_release(common->cpts);
2991 err_of_clear:
2992 	if (common->mdio_dev)
2993 		of_platform_device_destroy(common->mdio_dev, NULL);
2994 err_pm_clear:
2995 	pm_runtime_put_sync(dev);
2996 	pm_runtime_disable(dev);
2997 	return ret;
2998 }
2999 
3000 static int am65_cpsw_nuss_remove(struct platform_device *pdev)
3001 {
3002 	struct device *dev = &pdev->dev;
3003 	struct am65_cpsw_common *common;
3004 	int ret;
3005 
3006 	common = dev_get_drvdata(dev);
3007 
3008 	ret = pm_runtime_resume_and_get(&pdev->dev);
3009 	if (ret < 0)
3010 		return ret;
3011 
3012 	am65_cpsw_unregister_devlink(common);
3013 	am65_cpsw_unregister_notifiers(common);
3014 
3015 	/* must unregister ndevs here because DD release_driver routine calls
3016 	 * dma_deconfigure(dev) before devres_release_all(dev)
3017 	 */
3018 	am65_cpsw_nuss_cleanup_ndev(common);
3019 	am65_cpsw_nuss_phylink_cleanup(common);
3020 	am65_cpts_release(common->cpts);
3021 	am65_cpsw_disable_serdes_phy(common);
3022 
3023 	if (common->mdio_dev)
3024 		of_platform_device_destroy(common->mdio_dev, NULL);
3025 
3026 	pm_runtime_put_sync(&pdev->dev);
3027 	pm_runtime_disable(&pdev->dev);
3028 	return 0;
3029 }
3030 
3031 static int am65_cpsw_nuss_suspend(struct device *dev)
3032 {
3033 	struct am65_cpsw_common *common = dev_get_drvdata(dev);
3034 	struct am65_cpsw_host *host_p = am65_common_get_host(common);
3035 	struct am65_cpsw_port *port;
3036 	struct net_device *ndev;
3037 	int i, ret;
3038 
3039 	cpsw_ale_dump(common->ale, common->ale_context);
3040 	host_p->vid_context = readl(host_p->port_base + AM65_CPSW_PORT_VLAN_REG_OFFSET);
3041 	for (i = 0; i < common->port_num; i++) {
3042 		port = &common->ports[i];
3043 		ndev = port->ndev;
3044 
3045 		if (!ndev)
3046 			continue;
3047 
3048 		port->vid_context = readl(port->port_base + AM65_CPSW_PORT_VLAN_REG_OFFSET);
3049 		netif_device_detach(ndev);
3050 		if (netif_running(ndev)) {
3051 			rtnl_lock();
3052 			ret = am65_cpsw_nuss_ndo_slave_stop(ndev);
3053 			rtnl_unlock();
3054 			if (ret < 0) {
3055 				netdev_err(ndev, "failed to stop: %d", ret);
3056 				return ret;
3057 			}
3058 		}
3059 	}
3060 
3061 	am65_cpts_suspend(common->cpts);
3062 
3063 	am65_cpsw_nuss_remove_rx_chns(common);
3064 	am65_cpsw_nuss_remove_tx_chns(common);
3065 
3066 	return 0;
3067 }
3068 
3069 static int am65_cpsw_nuss_resume(struct device *dev)
3070 {
3071 	struct am65_cpsw_common *common = dev_get_drvdata(dev);
3072 	struct am65_cpsw_port *port;
3073 	struct net_device *ndev;
3074 	int i, ret;
3075 	struct am65_cpsw_host *host_p = am65_common_get_host(common);
3076 
3077 	ret = am65_cpsw_nuss_init_tx_chns(common);
3078 	if (ret)
3079 		return ret;
3080 	ret = am65_cpsw_nuss_init_rx_chns(common);
3081 	if (ret)
3082 		return ret;
3083 
3084 	/* If RX IRQ was disabled before suspend, keep it disabled */
3085 	if (common->rx_irq_disabled)
3086 		disable_irq(common->rx_chns.irq);
3087 
3088 	am65_cpts_resume(common->cpts);
3089 
3090 	for (i = 0; i < common->port_num; i++) {
3091 		port = &common->ports[i];
3092 		ndev = port->ndev;
3093 
3094 		if (!ndev)
3095 			continue;
3096 
3097 		if (netif_running(ndev)) {
3098 			rtnl_lock();
3099 			ret = am65_cpsw_nuss_ndo_slave_open(ndev);
3100 			rtnl_unlock();
3101 			if (ret < 0) {
3102 				netdev_err(ndev, "failed to start: %d", ret);
3103 				return ret;
3104 			}
3105 		}
3106 
3107 		netif_device_attach(ndev);
3108 		writel(port->vid_context, port->port_base + AM65_CPSW_PORT_VLAN_REG_OFFSET);
3109 	}
3110 
3111 	writel(host_p->vid_context, host_p->port_base + AM65_CPSW_PORT_VLAN_REG_OFFSET);
3112 	cpsw_ale_restore(common->ale, common->ale_context);
3113 
3114 	return 0;
3115 }
3116 
3117 static const struct dev_pm_ops am65_cpsw_nuss_dev_pm_ops = {
3118 	SYSTEM_SLEEP_PM_OPS(am65_cpsw_nuss_suspend, am65_cpsw_nuss_resume)
3119 };
3120 
3121 static struct platform_driver am65_cpsw_nuss_driver = {
3122 	.driver = {
3123 		.name	 = AM65_CPSW_DRV_NAME,
3124 		.of_match_table = am65_cpsw_nuss_of_mtable,
3125 		.pm = &am65_cpsw_nuss_dev_pm_ops,
3126 	},
3127 	.probe = am65_cpsw_nuss_probe,
3128 	.remove = am65_cpsw_nuss_remove,
3129 };
3130 
3131 module_platform_driver(am65_cpsw_nuss_driver);
3132 
3133 MODULE_LICENSE("GPL v2");
3134 MODULE_AUTHOR("Grygorii Strashko <grygorii.strashko@ti.com>");
3135 MODULE_DESCRIPTION("TI AM65 CPSW Ethernet driver");
3136