1 // SPDX-License-Identifier: GPL-2.0 2 /* Texas Instruments K3 AM65 Ethernet Switch SubSystem Driver 3 * 4 * Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/ 5 * 6 */ 7 8 #include <linux/clk.h> 9 #include <linux/etherdevice.h> 10 #include <linux/if_vlan.h> 11 #include <linux/interrupt.h> 12 #include <linux/kernel.h> 13 #include <linux/kmemleak.h> 14 #include <linux/module.h> 15 #include <linux/netdevice.h> 16 #include <linux/net_tstamp.h> 17 #include <linux/of.h> 18 #include <linux/of_mdio.h> 19 #include <linux/of_net.h> 20 #include <linux/of_device.h> 21 #include <linux/phy.h> 22 #include <linux/phy/phy.h> 23 #include <linux/platform_device.h> 24 #include <linux/pm_runtime.h> 25 #include <linux/regmap.h> 26 #include <linux/mfd/syscon.h> 27 #include <linux/sys_soc.h> 28 #include <linux/dma/ti-cppi5.h> 29 #include <linux/dma/k3-udma-glue.h> 30 31 #include "cpsw_ale.h" 32 #include "cpsw_sl.h" 33 #include "am65-cpsw-nuss.h" 34 #include "k3-cppi-desc-pool.h" 35 #include "am65-cpts.h" 36 37 #define AM65_CPSW_SS_BASE 0x0 38 #define AM65_CPSW_SGMII_BASE 0x100 39 #define AM65_CPSW_XGMII_BASE 0x2100 40 #define AM65_CPSW_CPSW_NU_BASE 0x20000 41 #define AM65_CPSW_NU_PORTS_BASE 0x1000 42 #define AM65_CPSW_NU_FRAM_BASE 0x12000 43 #define AM65_CPSW_NU_STATS_BASE 0x1a000 44 #define AM65_CPSW_NU_ALE_BASE 0x1e000 45 #define AM65_CPSW_NU_CPTS_BASE 0x1d000 46 47 #define AM65_CPSW_NU_PORTS_OFFSET 0x1000 48 #define AM65_CPSW_NU_STATS_PORT_OFFSET 0x200 49 #define AM65_CPSW_NU_FRAM_PORT_OFFSET 0x200 50 51 #define AM65_CPSW_MAX_PORTS 8 52 53 #define AM65_CPSW_MIN_PACKET_SIZE VLAN_ETH_ZLEN 54 #define AM65_CPSW_MAX_PACKET_SIZE (VLAN_ETH_FRAME_LEN + ETH_FCS_LEN) 55 56 #define AM65_CPSW_REG_CTL 0x004 57 #define AM65_CPSW_REG_STAT_PORT_EN 0x014 58 #define AM65_CPSW_REG_PTYPE 0x018 59 60 #define AM65_CPSW_P0_REG_CTL 0x004 61 #define AM65_CPSW_PORT0_REG_FLOW_ID_OFFSET 0x008 62 63 #define AM65_CPSW_PORT_REG_PRI_CTL 0x01c 64 #define AM65_CPSW_PORT_REG_RX_PRI_MAP 0x020 65 #define AM65_CPSW_PORT_REG_RX_MAXLEN 0x024 66 67 #define AM65_CPSW_PORTN_REG_SA_L 0x308 68 #define AM65_CPSW_PORTN_REG_SA_H 0x30c 69 #define AM65_CPSW_PORTN_REG_TS_CTL 0x310 70 #define AM65_CPSW_PORTN_REG_TS_SEQ_LTYPE_REG 0x314 71 #define AM65_CPSW_PORTN_REG_TS_VLAN_LTYPE_REG 0x318 72 #define AM65_CPSW_PORTN_REG_TS_CTL_LTYPE2 0x31C 73 74 #define AM65_CPSW_CTL_VLAN_AWARE BIT(1) 75 #define AM65_CPSW_CTL_P0_ENABLE BIT(2) 76 #define AM65_CPSW_CTL_P0_TX_CRC_REMOVE BIT(13) 77 #define AM65_CPSW_CTL_P0_RX_PAD BIT(14) 78 79 /* AM65_CPSW_P0_REG_CTL */ 80 #define AM65_CPSW_P0_REG_CTL_RX_CHECKSUM_EN BIT(0) 81 82 /* AM65_CPSW_PORT_REG_PRI_CTL */ 83 #define AM65_CPSW_PORT_REG_PRI_CTL_RX_PTYPE_RROBIN BIT(8) 84 85 /* AM65_CPSW_PN_TS_CTL register fields */ 86 #define AM65_CPSW_PN_TS_CTL_TX_ANX_F_EN BIT(4) 87 #define AM65_CPSW_PN_TS_CTL_TX_VLAN_LT1_EN BIT(5) 88 #define AM65_CPSW_PN_TS_CTL_TX_VLAN_LT2_EN BIT(6) 89 #define AM65_CPSW_PN_TS_CTL_TX_ANX_D_EN BIT(7) 90 #define AM65_CPSW_PN_TS_CTL_TX_ANX_E_EN BIT(10) 91 #define AM65_CPSW_PN_TS_CTL_TX_HOST_TS_EN BIT(11) 92 #define AM65_CPSW_PN_TS_CTL_MSG_TYPE_EN_SHIFT 16 93 94 /* AM65_CPSW_PORTN_REG_TS_SEQ_LTYPE_REG register fields */ 95 #define AM65_CPSW_PN_TS_SEQ_ID_OFFSET_SHIFT 16 96 97 /* AM65_CPSW_PORTN_REG_TS_CTL_LTYPE2 */ 98 #define AM65_CPSW_PN_TS_CTL_LTYPE2_TS_107 BIT(16) 99 #define AM65_CPSW_PN_TS_CTL_LTYPE2_TS_129 BIT(17) 100 #define AM65_CPSW_PN_TS_CTL_LTYPE2_TS_130 BIT(18) 101 #define AM65_CPSW_PN_TS_CTL_LTYPE2_TS_131 BIT(19) 102 #define AM65_CPSW_PN_TS_CTL_LTYPE2_TS_132 BIT(20) 103 #define AM65_CPSW_PN_TS_CTL_LTYPE2_TS_319 BIT(21) 104 #define AM65_CPSW_PN_TS_CTL_LTYPE2_TS_320 BIT(22) 105 #define AM65_CPSW_PN_TS_CTL_LTYPE2_TS_TTL_NONZERO BIT(23) 106 107 /* The PTP event messages - Sync, Delay_Req, Pdelay_Req, and Pdelay_Resp. */ 108 #define AM65_CPSW_TS_EVENT_MSG_TYPE_BITS (BIT(0) | BIT(1) | BIT(2) | BIT(3)) 109 110 #define AM65_CPSW_TS_SEQ_ID_OFFSET (0x1e) 111 112 #define AM65_CPSW_TS_TX_ANX_ALL_EN \ 113 (AM65_CPSW_PN_TS_CTL_TX_ANX_D_EN | \ 114 AM65_CPSW_PN_TS_CTL_TX_ANX_E_EN | \ 115 AM65_CPSW_PN_TS_CTL_TX_ANX_F_EN) 116 117 #define AM65_CPSW_ALE_AGEOUT_DEFAULT 30 118 /* Number of TX/RX descriptors */ 119 #define AM65_CPSW_MAX_TX_DESC 500 120 #define AM65_CPSW_MAX_RX_DESC 500 121 122 #define AM65_CPSW_NAV_PS_DATA_SIZE 16 123 #define AM65_CPSW_NAV_SW_DATA_SIZE 16 124 125 #define AM65_CPSW_DEBUG (NETIF_MSG_HW | NETIF_MSG_DRV | NETIF_MSG_LINK | \ 126 NETIF_MSG_IFUP | NETIF_MSG_PROBE | NETIF_MSG_IFDOWN | \ 127 NETIF_MSG_RX_ERR | NETIF_MSG_TX_ERR) 128 129 static void am65_cpsw_port_set_sl_mac(struct am65_cpsw_port *slave, 130 const u8 *dev_addr) 131 { 132 u32 mac_hi = (dev_addr[0] << 0) | (dev_addr[1] << 8) | 133 (dev_addr[2] << 16) | (dev_addr[3] << 24); 134 u32 mac_lo = (dev_addr[4] << 0) | (dev_addr[5] << 8); 135 136 writel(mac_hi, slave->port_base + AM65_CPSW_PORTN_REG_SA_H); 137 writel(mac_lo, slave->port_base + AM65_CPSW_PORTN_REG_SA_L); 138 } 139 140 static void am65_cpsw_sl_ctl_reset(struct am65_cpsw_port *port) 141 { 142 cpsw_sl_reset(port->slave.mac_sl, 100); 143 /* Max length register has to be restored after MAC SL reset */ 144 writel(AM65_CPSW_MAX_PACKET_SIZE, 145 port->port_base + AM65_CPSW_PORT_REG_RX_MAXLEN); 146 } 147 148 static void am65_cpsw_nuss_get_ver(struct am65_cpsw_common *common) 149 { 150 common->nuss_ver = readl(common->ss_base); 151 common->cpsw_ver = readl(common->cpsw_base); 152 dev_info(common->dev, 153 "initializing am65 cpsw nuss version 0x%08X, cpsw version 0x%08X Ports: %u quirks:%08x\n", 154 common->nuss_ver, 155 common->cpsw_ver, 156 common->port_num + 1, 157 common->pdata.quirks); 158 } 159 160 void am65_cpsw_nuss_adjust_link(struct net_device *ndev) 161 { 162 struct am65_cpsw_common *common = am65_ndev_to_common(ndev); 163 struct am65_cpsw_port *port = am65_ndev_to_port(ndev); 164 struct phy_device *phy = port->slave.phy; 165 u32 mac_control = 0; 166 167 if (!phy) 168 return; 169 170 if (phy->link) { 171 mac_control = CPSW_SL_CTL_GMII_EN; 172 173 if (phy->speed == 1000) 174 mac_control |= CPSW_SL_CTL_GIG; 175 if (phy->speed == 10 && phy_interface_is_rgmii(phy)) 176 /* Can be used with in band mode only */ 177 mac_control |= CPSW_SL_CTL_EXT_EN; 178 if (phy->speed == 100 && phy->interface == PHY_INTERFACE_MODE_RMII) 179 mac_control |= CPSW_SL_CTL_IFCTL_A; 180 if (phy->duplex) 181 mac_control |= CPSW_SL_CTL_FULLDUPLEX; 182 183 /* RGMII speed is 100M if !CPSW_SL_CTL_GIG*/ 184 185 /* rx_pause/tx_pause */ 186 if (port->slave.rx_pause) 187 mac_control |= CPSW_SL_CTL_RX_FLOW_EN; 188 189 if (port->slave.tx_pause) 190 mac_control |= CPSW_SL_CTL_TX_FLOW_EN; 191 192 cpsw_sl_ctl_set(port->slave.mac_sl, mac_control); 193 194 /* enable forwarding */ 195 cpsw_ale_control_set(common->ale, port->port_id, 196 ALE_PORT_STATE, ALE_PORT_STATE_FORWARD); 197 198 am65_cpsw_qos_link_up(ndev, phy->speed); 199 netif_tx_wake_all_queues(ndev); 200 } else { 201 int tmo; 202 203 /* disable forwarding */ 204 cpsw_ale_control_set(common->ale, port->port_id, 205 ALE_PORT_STATE, ALE_PORT_STATE_DISABLE); 206 207 cpsw_sl_ctl_set(port->slave.mac_sl, CPSW_SL_CTL_CMD_IDLE); 208 209 tmo = cpsw_sl_wait_for_idle(port->slave.mac_sl, 100); 210 dev_dbg(common->dev, "donw msc_sl %08x tmo %d\n", 211 cpsw_sl_reg_read(port->slave.mac_sl, CPSW_SL_MACSTATUS), 212 tmo); 213 214 cpsw_sl_ctl_reset(port->slave.mac_sl); 215 216 am65_cpsw_qos_link_down(ndev); 217 netif_tx_stop_all_queues(ndev); 218 } 219 220 phy_print_status(phy); 221 } 222 223 static int am65_cpsw_nuss_ndo_slave_add_vid(struct net_device *ndev, 224 __be16 proto, u16 vid) 225 { 226 struct am65_cpsw_common *common = am65_ndev_to_common(ndev); 227 struct am65_cpsw_port *port = am65_ndev_to_port(ndev); 228 u32 port_mask, unreg_mcast = 0; 229 int ret; 230 231 if (!netif_running(ndev) || !vid) 232 return 0; 233 234 ret = pm_runtime_get_sync(common->dev); 235 if (ret < 0) { 236 pm_runtime_put_noidle(common->dev); 237 return ret; 238 } 239 240 port_mask = BIT(port->port_id) | ALE_PORT_HOST; 241 if (!vid) 242 unreg_mcast = port_mask; 243 dev_info(common->dev, "Adding vlan %d to vlan filter\n", vid); 244 ret = cpsw_ale_vlan_add_modify(common->ale, vid, port_mask, 245 unreg_mcast, port_mask, 0); 246 247 pm_runtime_put(common->dev); 248 return ret; 249 } 250 251 static int am65_cpsw_nuss_ndo_slave_kill_vid(struct net_device *ndev, 252 __be16 proto, u16 vid) 253 { 254 struct am65_cpsw_common *common = am65_ndev_to_common(ndev); 255 struct am65_cpsw_port *port = am65_ndev_to_port(ndev); 256 int ret; 257 258 if (!netif_running(ndev) || !vid) 259 return 0; 260 261 ret = pm_runtime_get_sync(common->dev); 262 if (ret < 0) { 263 pm_runtime_put_noidle(common->dev); 264 return ret; 265 } 266 267 dev_info(common->dev, "Removing vlan %d from vlan filter\n", vid); 268 ret = cpsw_ale_del_vlan(common->ale, vid, 269 BIT(port->port_id) | ALE_PORT_HOST); 270 271 pm_runtime_put(common->dev); 272 return ret; 273 } 274 275 static void am65_cpsw_slave_set_promisc(struct am65_cpsw_port *port, 276 bool promisc) 277 { 278 struct am65_cpsw_common *common = port->common; 279 280 if (promisc) { 281 /* Enable promiscuous mode */ 282 cpsw_ale_control_set(common->ale, port->port_id, 283 ALE_PORT_MACONLY_CAF, 1); 284 dev_dbg(common->dev, "promisc enabled\n"); 285 } else { 286 /* Disable promiscuous mode */ 287 cpsw_ale_control_set(common->ale, port->port_id, 288 ALE_PORT_MACONLY_CAF, 0); 289 dev_dbg(common->dev, "promisc disabled\n"); 290 } 291 } 292 293 static void am65_cpsw_nuss_ndo_slave_set_rx_mode(struct net_device *ndev) 294 { 295 struct am65_cpsw_common *common = am65_ndev_to_common(ndev); 296 struct am65_cpsw_port *port = am65_ndev_to_port(ndev); 297 u32 port_mask; 298 bool promisc; 299 300 promisc = !!(ndev->flags & IFF_PROMISC); 301 am65_cpsw_slave_set_promisc(port, promisc); 302 303 if (promisc) 304 return; 305 306 /* Restore allmulti on vlans if necessary */ 307 cpsw_ale_set_allmulti(common->ale, 308 ndev->flags & IFF_ALLMULTI, port->port_id); 309 310 port_mask = ALE_PORT_HOST; 311 /* Clear all mcast from ALE */ 312 cpsw_ale_flush_multicast(common->ale, port_mask, -1); 313 314 if (!netdev_mc_empty(ndev)) { 315 struct netdev_hw_addr *ha; 316 317 /* program multicast address list into ALE register */ 318 netdev_for_each_mc_addr(ha, ndev) { 319 cpsw_ale_add_mcast(common->ale, ha->addr, 320 port_mask, 0, 0, 0); 321 } 322 } 323 } 324 325 static void am65_cpsw_nuss_ndo_host_tx_timeout(struct net_device *ndev, 326 unsigned int txqueue) 327 { 328 struct am65_cpsw_common *common = am65_ndev_to_common(ndev); 329 struct am65_cpsw_tx_chn *tx_chn; 330 struct netdev_queue *netif_txq; 331 unsigned long trans_start; 332 333 netif_txq = netdev_get_tx_queue(ndev, txqueue); 334 tx_chn = &common->tx_chns[txqueue]; 335 trans_start = netif_txq->trans_start; 336 337 netdev_err(ndev, "txq:%d DRV_XOFF:%d tmo:%u dql_avail:%d free_desc:%zu\n", 338 txqueue, 339 netif_tx_queue_stopped(netif_txq), 340 jiffies_to_msecs(jiffies - trans_start), 341 dql_avail(&netif_txq->dql), 342 k3_cppi_desc_pool_avail(tx_chn->desc_pool)); 343 344 if (netif_tx_queue_stopped(netif_txq)) { 345 /* try recover if stopped by us */ 346 txq_trans_update(netif_txq); 347 netif_tx_wake_queue(netif_txq); 348 } 349 } 350 351 static int am65_cpsw_nuss_rx_push(struct am65_cpsw_common *common, 352 struct sk_buff *skb) 353 { 354 struct am65_cpsw_rx_chn *rx_chn = &common->rx_chns; 355 struct cppi5_host_desc_t *desc_rx; 356 struct device *dev = common->dev; 357 u32 pkt_len = skb_tailroom(skb); 358 dma_addr_t desc_dma; 359 dma_addr_t buf_dma; 360 void *swdata; 361 362 desc_rx = k3_cppi_desc_pool_alloc(rx_chn->desc_pool); 363 if (!desc_rx) { 364 dev_err(dev, "Failed to allocate RXFDQ descriptor\n"); 365 return -ENOMEM; 366 } 367 desc_dma = k3_cppi_desc_pool_virt2dma(rx_chn->desc_pool, desc_rx); 368 369 buf_dma = dma_map_single(rx_chn->dma_dev, skb->data, pkt_len, 370 DMA_FROM_DEVICE); 371 if (unlikely(dma_mapping_error(rx_chn->dma_dev, buf_dma))) { 372 k3_cppi_desc_pool_free(rx_chn->desc_pool, desc_rx); 373 dev_err(dev, "Failed to map rx skb buffer\n"); 374 return -EINVAL; 375 } 376 377 cppi5_hdesc_init(desc_rx, CPPI5_INFO0_HDESC_EPIB_PRESENT, 378 AM65_CPSW_NAV_PS_DATA_SIZE); 379 k3_udma_glue_rx_dma_to_cppi5_addr(rx_chn->rx_chn, &buf_dma); 380 cppi5_hdesc_attach_buf(desc_rx, buf_dma, skb_tailroom(skb), buf_dma, skb_tailroom(skb)); 381 swdata = cppi5_hdesc_get_swdata(desc_rx); 382 *((void **)swdata) = skb; 383 384 return k3_udma_glue_push_rx_chn(rx_chn->rx_chn, 0, desc_rx, desc_dma); 385 } 386 387 void am65_cpsw_nuss_set_p0_ptype(struct am65_cpsw_common *common) 388 { 389 struct am65_cpsw_host *host_p = am65_common_get_host(common); 390 u32 val, pri_map; 391 392 /* P0 set Receive Priority Type */ 393 val = readl(host_p->port_base + AM65_CPSW_PORT_REG_PRI_CTL); 394 395 if (common->pf_p0_rx_ptype_rrobin) { 396 val |= AM65_CPSW_PORT_REG_PRI_CTL_RX_PTYPE_RROBIN; 397 /* Enet Ports fifos works in fixed priority mode only, so 398 * reset P0_Rx_Pri_Map so all packet will go in Enet fifo 0 399 */ 400 pri_map = 0x0; 401 } else { 402 val &= ~AM65_CPSW_PORT_REG_PRI_CTL_RX_PTYPE_RROBIN; 403 /* restore P0_Rx_Pri_Map */ 404 pri_map = 0x76543210; 405 } 406 407 writel(pri_map, host_p->port_base + AM65_CPSW_PORT_REG_RX_PRI_MAP); 408 writel(val, host_p->port_base + AM65_CPSW_PORT_REG_PRI_CTL); 409 } 410 411 static int am65_cpsw_nuss_common_open(struct am65_cpsw_common *common, 412 netdev_features_t features) 413 { 414 struct am65_cpsw_host *host_p = am65_common_get_host(common); 415 int port_idx, i, ret; 416 struct sk_buff *skb; 417 u32 val, port_mask; 418 419 if (common->usage_count) 420 return 0; 421 422 /* Control register */ 423 writel(AM65_CPSW_CTL_P0_ENABLE | AM65_CPSW_CTL_P0_TX_CRC_REMOVE | 424 AM65_CPSW_CTL_VLAN_AWARE | AM65_CPSW_CTL_P0_RX_PAD, 425 common->cpsw_base + AM65_CPSW_REG_CTL); 426 /* Max length register */ 427 writel(AM65_CPSW_MAX_PACKET_SIZE, 428 host_p->port_base + AM65_CPSW_PORT_REG_RX_MAXLEN); 429 /* set base flow_id */ 430 writel(common->rx_flow_id_base, 431 host_p->port_base + AM65_CPSW_PORT0_REG_FLOW_ID_OFFSET); 432 /* en tx crc offload */ 433 writel(AM65_CPSW_P0_REG_CTL_RX_CHECKSUM_EN, host_p->port_base + AM65_CPSW_P0_REG_CTL); 434 435 am65_cpsw_nuss_set_p0_ptype(common); 436 437 /* enable statistic */ 438 val = BIT(HOST_PORT_NUM); 439 for (port_idx = 0; port_idx < common->port_num; port_idx++) { 440 struct am65_cpsw_port *port = &common->ports[port_idx]; 441 442 if (!port->disabled) 443 val |= BIT(port->port_id); 444 } 445 writel(val, common->cpsw_base + AM65_CPSW_REG_STAT_PORT_EN); 446 447 /* disable priority elevation */ 448 writel(0, common->cpsw_base + AM65_CPSW_REG_PTYPE); 449 450 cpsw_ale_start(common->ale); 451 452 /* limit to one RX flow only */ 453 cpsw_ale_control_set(common->ale, HOST_PORT_NUM, 454 ALE_DEFAULT_THREAD_ID, 0); 455 cpsw_ale_control_set(common->ale, HOST_PORT_NUM, 456 ALE_DEFAULT_THREAD_ENABLE, 1); 457 if (AM65_CPSW_IS_CPSW2G(common)) 458 cpsw_ale_control_set(common->ale, HOST_PORT_NUM, 459 ALE_PORT_NOLEARN, 1); 460 /* switch to vlan unaware mode */ 461 cpsw_ale_control_set(common->ale, HOST_PORT_NUM, ALE_VLAN_AWARE, 1); 462 cpsw_ale_control_set(common->ale, HOST_PORT_NUM, 463 ALE_PORT_STATE, ALE_PORT_STATE_FORWARD); 464 465 /* default vlan cfg: create mask based on enabled ports */ 466 port_mask = GENMASK(common->port_num, 0) & 467 ~common->disabled_ports_mask; 468 469 cpsw_ale_add_vlan(common->ale, 0, port_mask, 470 port_mask, port_mask, 471 port_mask & ~ALE_PORT_HOST); 472 473 for (i = 0; i < common->rx_chns.descs_num; i++) { 474 skb = __netdev_alloc_skb_ip_align(NULL, 475 AM65_CPSW_MAX_PACKET_SIZE, 476 GFP_KERNEL); 477 if (!skb) { 478 dev_err(common->dev, "cannot allocate skb\n"); 479 return -ENOMEM; 480 } 481 482 ret = am65_cpsw_nuss_rx_push(common, skb); 483 if (ret < 0) { 484 dev_err(common->dev, 485 "cannot submit skb to channel rx, error %d\n", 486 ret); 487 kfree_skb(skb); 488 return ret; 489 } 490 kmemleak_not_leak(skb); 491 } 492 k3_udma_glue_enable_rx_chn(common->rx_chns.rx_chn); 493 494 for (i = 0; i < common->tx_ch_num; i++) { 495 ret = k3_udma_glue_enable_tx_chn(common->tx_chns[i].tx_chn); 496 if (ret) 497 return ret; 498 napi_enable(&common->tx_chns[i].napi_tx); 499 } 500 501 napi_enable(&common->napi_rx); 502 503 dev_dbg(common->dev, "cpsw_nuss started\n"); 504 return 0; 505 } 506 507 static void am65_cpsw_nuss_tx_cleanup(void *data, dma_addr_t desc_dma); 508 static void am65_cpsw_nuss_rx_cleanup(void *data, dma_addr_t desc_dma); 509 510 static int am65_cpsw_nuss_common_stop(struct am65_cpsw_common *common) 511 { 512 int i; 513 514 if (common->usage_count != 1) 515 return 0; 516 517 cpsw_ale_control_set(common->ale, HOST_PORT_NUM, 518 ALE_PORT_STATE, ALE_PORT_STATE_DISABLE); 519 520 /* shutdown tx channels */ 521 atomic_set(&common->tdown_cnt, common->tx_ch_num); 522 /* ensure new tdown_cnt value is visible */ 523 smp_mb__after_atomic(); 524 reinit_completion(&common->tdown_complete); 525 526 for (i = 0; i < common->tx_ch_num; i++) 527 k3_udma_glue_tdown_tx_chn(common->tx_chns[i].tx_chn, false); 528 529 i = wait_for_completion_timeout(&common->tdown_complete, 530 msecs_to_jiffies(1000)); 531 if (!i) 532 dev_err(common->dev, "tx timeout\n"); 533 for (i = 0; i < common->tx_ch_num; i++) 534 napi_disable(&common->tx_chns[i].napi_tx); 535 536 for (i = 0; i < common->tx_ch_num; i++) { 537 k3_udma_glue_reset_tx_chn(common->tx_chns[i].tx_chn, 538 &common->tx_chns[i], 539 am65_cpsw_nuss_tx_cleanup); 540 k3_udma_glue_disable_tx_chn(common->tx_chns[i].tx_chn); 541 } 542 543 k3_udma_glue_tdown_rx_chn(common->rx_chns.rx_chn, true); 544 napi_disable(&common->napi_rx); 545 546 for (i = 0; i < AM65_CPSW_MAX_RX_FLOWS; i++) 547 k3_udma_glue_reset_rx_chn(common->rx_chns.rx_chn, i, 548 &common->rx_chns, 549 am65_cpsw_nuss_rx_cleanup, !!i); 550 551 k3_udma_glue_disable_rx_chn(common->rx_chns.rx_chn); 552 553 cpsw_ale_stop(common->ale); 554 555 writel(0, common->cpsw_base + AM65_CPSW_REG_CTL); 556 writel(0, common->cpsw_base + AM65_CPSW_REG_STAT_PORT_EN); 557 558 dev_dbg(common->dev, "cpsw_nuss stopped\n"); 559 return 0; 560 } 561 562 static int am65_cpsw_nuss_ndo_slave_stop(struct net_device *ndev) 563 { 564 struct am65_cpsw_common *common = am65_ndev_to_common(ndev); 565 struct am65_cpsw_port *port = am65_ndev_to_port(ndev); 566 int ret; 567 568 if (port->slave.phy) 569 phy_stop(port->slave.phy); 570 571 netif_tx_stop_all_queues(ndev); 572 573 if (port->slave.phy) { 574 phy_disconnect(port->slave.phy); 575 port->slave.phy = NULL; 576 } 577 578 ret = am65_cpsw_nuss_common_stop(common); 579 if (ret) 580 return ret; 581 582 common->usage_count--; 583 pm_runtime_put(common->dev); 584 return 0; 585 } 586 587 static int cpsw_restore_vlans(struct net_device *vdev, int vid, void *arg) 588 { 589 struct am65_cpsw_port *port = arg; 590 591 if (!vdev) 592 return 0; 593 594 return am65_cpsw_nuss_ndo_slave_add_vid(port->ndev, 0, vid); 595 } 596 597 static int am65_cpsw_nuss_ndo_slave_open(struct net_device *ndev) 598 { 599 struct am65_cpsw_common *common = am65_ndev_to_common(ndev); 600 struct am65_cpsw_port *port = am65_ndev_to_port(ndev); 601 u32 port_mask; 602 int ret, i; 603 604 ret = pm_runtime_get_sync(common->dev); 605 if (ret < 0) { 606 pm_runtime_put_noidle(common->dev); 607 return ret; 608 } 609 610 /* Notify the stack of the actual queue counts. */ 611 ret = netif_set_real_num_tx_queues(ndev, common->tx_ch_num); 612 if (ret) { 613 dev_err(common->dev, "cannot set real number of tx queues\n"); 614 return ret; 615 } 616 617 ret = netif_set_real_num_rx_queues(ndev, AM65_CPSW_MAX_RX_QUEUES); 618 if (ret) { 619 dev_err(common->dev, "cannot set real number of rx queues\n"); 620 return ret; 621 } 622 623 for (i = 0; i < common->tx_ch_num; i++) 624 netdev_tx_reset_queue(netdev_get_tx_queue(ndev, i)); 625 626 ret = am65_cpsw_nuss_common_open(common, ndev->features); 627 if (ret) 628 return ret; 629 630 common->usage_count++; 631 632 am65_cpsw_port_set_sl_mac(port, ndev->dev_addr); 633 634 if (port->slave.mac_only) { 635 /* enable mac-only mode on port */ 636 cpsw_ale_control_set(common->ale, port->port_id, 637 ALE_PORT_MACONLY, 1); 638 cpsw_ale_control_set(common->ale, port->port_id, 639 ALE_PORT_NOLEARN, 1); 640 } 641 642 port_mask = BIT(port->port_id) | ALE_PORT_HOST; 643 cpsw_ale_add_ucast(common->ale, ndev->dev_addr, 644 HOST_PORT_NUM, ALE_SECURE, 0); 645 cpsw_ale_add_mcast(common->ale, ndev->broadcast, 646 port_mask, 0, 0, ALE_MCAST_FWD_2); 647 648 /* mac_sl should be configured via phy-link interface */ 649 am65_cpsw_sl_ctl_reset(port); 650 651 ret = phy_set_mode_ext(port->slave.ifphy, PHY_MODE_ETHERNET, 652 port->slave.phy_if); 653 if (ret) 654 goto error_cleanup; 655 656 if (port->slave.phy_node) { 657 port->slave.phy = of_phy_connect(ndev, 658 port->slave.phy_node, 659 &am65_cpsw_nuss_adjust_link, 660 0, port->slave.phy_if); 661 if (!port->slave.phy) { 662 dev_err(common->dev, "phy %pOF not found on slave %d\n", 663 port->slave.phy_node, 664 port->port_id); 665 ret = -ENODEV; 666 goto error_cleanup; 667 } 668 } 669 670 /* restore vlan configurations */ 671 vlan_for_each(ndev, cpsw_restore_vlans, port); 672 673 phy_attached_info(port->slave.phy); 674 phy_start(port->slave.phy); 675 676 return 0; 677 678 error_cleanup: 679 am65_cpsw_nuss_ndo_slave_stop(ndev); 680 return ret; 681 } 682 683 static void am65_cpsw_nuss_rx_cleanup(void *data, dma_addr_t desc_dma) 684 { 685 struct am65_cpsw_rx_chn *rx_chn = data; 686 struct cppi5_host_desc_t *desc_rx; 687 struct sk_buff *skb; 688 dma_addr_t buf_dma; 689 u32 buf_dma_len; 690 void **swdata; 691 692 desc_rx = k3_cppi_desc_pool_dma2virt(rx_chn->desc_pool, desc_dma); 693 swdata = cppi5_hdesc_get_swdata(desc_rx); 694 skb = *swdata; 695 cppi5_hdesc_get_obuf(desc_rx, &buf_dma, &buf_dma_len); 696 k3_udma_glue_rx_cppi5_to_dma_addr(rx_chn->rx_chn, &buf_dma); 697 698 dma_unmap_single(rx_chn->dma_dev, buf_dma, buf_dma_len, DMA_FROM_DEVICE); 699 k3_cppi_desc_pool_free(rx_chn->desc_pool, desc_rx); 700 701 dev_kfree_skb_any(skb); 702 } 703 704 static void am65_cpsw_nuss_rx_ts(struct sk_buff *skb, u32 *psdata) 705 { 706 struct skb_shared_hwtstamps *ssh; 707 u64 ns; 708 709 ns = ((u64)psdata[1] << 32) | psdata[0]; 710 711 ssh = skb_hwtstamps(skb); 712 memset(ssh, 0, sizeof(*ssh)); 713 ssh->hwtstamp = ns_to_ktime(ns); 714 } 715 716 /* RX psdata[2] word format - checksum information */ 717 #define AM65_CPSW_RX_PSD_CSUM_ADD GENMASK(15, 0) 718 #define AM65_CPSW_RX_PSD_CSUM_ERR BIT(16) 719 #define AM65_CPSW_RX_PSD_IS_FRAGMENT BIT(17) 720 #define AM65_CPSW_RX_PSD_IS_TCP BIT(18) 721 #define AM65_CPSW_RX_PSD_IPV6_VALID BIT(19) 722 #define AM65_CPSW_RX_PSD_IPV4_VALID BIT(20) 723 724 static void am65_cpsw_nuss_rx_csum(struct sk_buff *skb, u32 csum_info) 725 { 726 /* HW can verify IPv4/IPv6 TCP/UDP packets checksum 727 * csum information provides in psdata[2] word: 728 * AM65_CPSW_RX_PSD_CSUM_ERR bit - indicates csum error 729 * AM65_CPSW_RX_PSD_IPV6_VALID and AM65_CPSW_RX_PSD_IPV4_VALID 730 * bits - indicates IPv4/IPv6 packet 731 * AM65_CPSW_RX_PSD_IS_FRAGMENT bit - indicates fragmented packet 732 * AM65_CPSW_RX_PSD_CSUM_ADD has value 0xFFFF for non fragmented packets 733 * or csum value for fragmented packets if !AM65_CPSW_RX_PSD_CSUM_ERR 734 */ 735 skb_checksum_none_assert(skb); 736 737 if (unlikely(!(skb->dev->features & NETIF_F_RXCSUM))) 738 return; 739 740 if ((csum_info & (AM65_CPSW_RX_PSD_IPV6_VALID | 741 AM65_CPSW_RX_PSD_IPV4_VALID)) && 742 !(csum_info & AM65_CPSW_RX_PSD_CSUM_ERR)) { 743 /* csum for fragmented packets is unsupported */ 744 if (!(csum_info & AM65_CPSW_RX_PSD_IS_FRAGMENT)) 745 skb->ip_summed = CHECKSUM_UNNECESSARY; 746 } 747 } 748 749 static int am65_cpsw_nuss_rx_packets(struct am65_cpsw_common *common, 750 u32 flow_idx) 751 { 752 struct am65_cpsw_rx_chn *rx_chn = &common->rx_chns; 753 u32 buf_dma_len, pkt_len, port_id = 0, csum_info; 754 struct am65_cpsw_ndev_priv *ndev_priv; 755 struct am65_cpsw_ndev_stats *stats; 756 struct cppi5_host_desc_t *desc_rx; 757 struct device *dev = common->dev; 758 struct sk_buff *skb, *new_skb; 759 dma_addr_t desc_dma, buf_dma; 760 struct am65_cpsw_port *port; 761 struct net_device *ndev; 762 void **swdata; 763 u32 *psdata; 764 int ret = 0; 765 766 ret = k3_udma_glue_pop_rx_chn(rx_chn->rx_chn, flow_idx, &desc_dma); 767 if (ret) { 768 if (ret != -ENODATA) 769 dev_err(dev, "RX: pop chn fail %d\n", ret); 770 return ret; 771 } 772 773 if (cppi5_desc_is_tdcm(desc_dma)) { 774 dev_dbg(dev, "%s RX tdown flow: %u\n", __func__, flow_idx); 775 return 0; 776 } 777 778 desc_rx = k3_cppi_desc_pool_dma2virt(rx_chn->desc_pool, desc_dma); 779 dev_dbg(dev, "%s flow_idx: %u desc %pad\n", 780 __func__, flow_idx, &desc_dma); 781 782 swdata = cppi5_hdesc_get_swdata(desc_rx); 783 skb = *swdata; 784 cppi5_hdesc_get_obuf(desc_rx, &buf_dma, &buf_dma_len); 785 k3_udma_glue_rx_cppi5_to_dma_addr(rx_chn->rx_chn, &buf_dma); 786 pkt_len = cppi5_hdesc_get_pktlen(desc_rx); 787 cppi5_desc_get_tags_ids(&desc_rx->hdr, &port_id, NULL); 788 dev_dbg(dev, "%s rx port_id:%d\n", __func__, port_id); 789 port = am65_common_get_port(common, port_id); 790 ndev = port->ndev; 791 skb->dev = ndev; 792 793 psdata = cppi5_hdesc_get_psdata(desc_rx); 794 /* add RX timestamp */ 795 if (port->rx_ts_enabled) 796 am65_cpsw_nuss_rx_ts(skb, psdata); 797 csum_info = psdata[2]; 798 dev_dbg(dev, "%s rx csum_info:%#x\n", __func__, csum_info); 799 800 dma_unmap_single(rx_chn->dma_dev, buf_dma, buf_dma_len, DMA_FROM_DEVICE); 801 802 k3_cppi_desc_pool_free(rx_chn->desc_pool, desc_rx); 803 804 new_skb = netdev_alloc_skb_ip_align(ndev, AM65_CPSW_MAX_PACKET_SIZE); 805 if (new_skb) { 806 skb_put(skb, pkt_len); 807 skb->protocol = eth_type_trans(skb, ndev); 808 am65_cpsw_nuss_rx_csum(skb, csum_info); 809 napi_gro_receive(&common->napi_rx, skb); 810 811 ndev_priv = netdev_priv(ndev); 812 stats = this_cpu_ptr(ndev_priv->stats); 813 814 u64_stats_update_begin(&stats->syncp); 815 stats->rx_packets++; 816 stats->rx_bytes += pkt_len; 817 u64_stats_update_end(&stats->syncp); 818 kmemleak_not_leak(new_skb); 819 } else { 820 ndev->stats.rx_dropped++; 821 new_skb = skb; 822 } 823 824 if (netif_dormant(ndev)) { 825 dev_kfree_skb_any(new_skb); 826 ndev->stats.rx_dropped++; 827 return 0; 828 } 829 830 ret = am65_cpsw_nuss_rx_push(common, new_skb); 831 if (WARN_ON(ret < 0)) { 832 dev_kfree_skb_any(new_skb); 833 ndev->stats.rx_errors++; 834 ndev->stats.rx_dropped++; 835 } 836 837 return ret; 838 } 839 840 static int am65_cpsw_nuss_rx_poll(struct napi_struct *napi_rx, int budget) 841 { 842 struct am65_cpsw_common *common = am65_cpsw_napi_to_common(napi_rx); 843 int flow = AM65_CPSW_MAX_RX_FLOWS; 844 int cur_budget, ret; 845 int num_rx = 0; 846 847 /* process every flow */ 848 while (flow--) { 849 cur_budget = budget - num_rx; 850 851 while (cur_budget--) { 852 ret = am65_cpsw_nuss_rx_packets(common, flow); 853 if (ret) 854 break; 855 num_rx++; 856 } 857 858 if (num_rx >= budget) 859 break; 860 } 861 862 dev_dbg(common->dev, "%s num_rx:%d %d\n", __func__, num_rx, budget); 863 864 if (num_rx < budget && napi_complete_done(napi_rx, num_rx)) 865 enable_irq(common->rx_chns.irq); 866 867 return num_rx; 868 } 869 870 static void am65_cpsw_nuss_xmit_free(struct am65_cpsw_tx_chn *tx_chn, 871 struct cppi5_host_desc_t *desc) 872 { 873 struct cppi5_host_desc_t *first_desc, *next_desc; 874 dma_addr_t buf_dma, next_desc_dma; 875 u32 buf_dma_len; 876 877 first_desc = desc; 878 next_desc = first_desc; 879 880 cppi5_hdesc_get_obuf(first_desc, &buf_dma, &buf_dma_len); 881 k3_udma_glue_tx_cppi5_to_dma_addr(tx_chn->tx_chn, &buf_dma); 882 883 dma_unmap_single(tx_chn->dma_dev, buf_dma, buf_dma_len, DMA_TO_DEVICE); 884 885 next_desc_dma = cppi5_hdesc_get_next_hbdesc(first_desc); 886 k3_udma_glue_tx_cppi5_to_dma_addr(tx_chn->tx_chn, &next_desc_dma); 887 while (next_desc_dma) { 888 next_desc = k3_cppi_desc_pool_dma2virt(tx_chn->desc_pool, 889 next_desc_dma); 890 cppi5_hdesc_get_obuf(next_desc, &buf_dma, &buf_dma_len); 891 k3_udma_glue_tx_cppi5_to_dma_addr(tx_chn->tx_chn, &buf_dma); 892 893 dma_unmap_page(tx_chn->dma_dev, buf_dma, buf_dma_len, 894 DMA_TO_DEVICE); 895 896 next_desc_dma = cppi5_hdesc_get_next_hbdesc(next_desc); 897 k3_udma_glue_tx_cppi5_to_dma_addr(tx_chn->tx_chn, &next_desc_dma); 898 899 k3_cppi_desc_pool_free(tx_chn->desc_pool, next_desc); 900 } 901 902 k3_cppi_desc_pool_free(tx_chn->desc_pool, first_desc); 903 } 904 905 static void am65_cpsw_nuss_tx_cleanup(void *data, dma_addr_t desc_dma) 906 { 907 struct am65_cpsw_tx_chn *tx_chn = data; 908 struct cppi5_host_desc_t *desc_tx; 909 struct sk_buff *skb; 910 void **swdata; 911 912 desc_tx = k3_cppi_desc_pool_dma2virt(tx_chn->desc_pool, desc_dma); 913 swdata = cppi5_hdesc_get_swdata(desc_tx); 914 skb = *(swdata); 915 am65_cpsw_nuss_xmit_free(tx_chn, desc_tx); 916 917 dev_kfree_skb_any(skb); 918 } 919 920 static struct sk_buff * 921 am65_cpsw_nuss_tx_compl_packet(struct am65_cpsw_tx_chn *tx_chn, 922 dma_addr_t desc_dma) 923 { 924 struct am65_cpsw_ndev_priv *ndev_priv; 925 struct am65_cpsw_ndev_stats *stats; 926 struct cppi5_host_desc_t *desc_tx; 927 struct net_device *ndev; 928 struct sk_buff *skb; 929 void **swdata; 930 931 desc_tx = k3_cppi_desc_pool_dma2virt(tx_chn->desc_pool, 932 desc_dma); 933 swdata = cppi5_hdesc_get_swdata(desc_tx); 934 skb = *(swdata); 935 am65_cpsw_nuss_xmit_free(tx_chn, desc_tx); 936 937 ndev = skb->dev; 938 939 am65_cpts_tx_timestamp(tx_chn->common->cpts, skb); 940 941 ndev_priv = netdev_priv(ndev); 942 stats = this_cpu_ptr(ndev_priv->stats); 943 u64_stats_update_begin(&stats->syncp); 944 stats->tx_packets++; 945 stats->tx_bytes += skb->len; 946 u64_stats_update_end(&stats->syncp); 947 948 return skb; 949 } 950 951 static void am65_cpsw_nuss_tx_wake(struct am65_cpsw_tx_chn *tx_chn, struct net_device *ndev, 952 struct netdev_queue *netif_txq) 953 { 954 if (netif_tx_queue_stopped(netif_txq)) { 955 /* Check whether the queue is stopped due to stalled 956 * tx dma, if the queue is stopped then wake the queue 957 * as we have free desc for tx 958 */ 959 __netif_tx_lock(netif_txq, smp_processor_id()); 960 if (netif_running(ndev) && 961 (k3_cppi_desc_pool_avail(tx_chn->desc_pool) >= MAX_SKB_FRAGS)) 962 netif_tx_wake_queue(netif_txq); 963 964 __netif_tx_unlock(netif_txq); 965 } 966 } 967 968 static int am65_cpsw_nuss_tx_compl_packets(struct am65_cpsw_common *common, 969 int chn, unsigned int budget) 970 { 971 struct device *dev = common->dev; 972 struct am65_cpsw_tx_chn *tx_chn; 973 struct netdev_queue *netif_txq; 974 unsigned int total_bytes = 0; 975 struct net_device *ndev; 976 struct sk_buff *skb; 977 dma_addr_t desc_dma; 978 int res, num_tx = 0; 979 980 tx_chn = &common->tx_chns[chn]; 981 982 while (true) { 983 spin_lock(&tx_chn->lock); 984 res = k3_udma_glue_pop_tx_chn(tx_chn->tx_chn, &desc_dma); 985 spin_unlock(&tx_chn->lock); 986 if (res == -ENODATA) 987 break; 988 989 if (cppi5_desc_is_tdcm(desc_dma)) { 990 if (atomic_dec_and_test(&common->tdown_cnt)) 991 complete(&common->tdown_complete); 992 break; 993 } 994 995 skb = am65_cpsw_nuss_tx_compl_packet(tx_chn, desc_dma); 996 total_bytes = skb->len; 997 ndev = skb->dev; 998 napi_consume_skb(skb, budget); 999 num_tx++; 1000 1001 netif_txq = netdev_get_tx_queue(ndev, chn); 1002 1003 netdev_tx_completed_queue(netif_txq, num_tx, total_bytes); 1004 1005 am65_cpsw_nuss_tx_wake(tx_chn, ndev, netif_txq); 1006 } 1007 1008 dev_dbg(dev, "%s:%u pkt:%d\n", __func__, chn, num_tx); 1009 1010 return num_tx; 1011 } 1012 1013 static int am65_cpsw_nuss_tx_compl_packets_2g(struct am65_cpsw_common *common, 1014 int chn, unsigned int budget) 1015 { 1016 struct device *dev = common->dev; 1017 struct am65_cpsw_tx_chn *tx_chn; 1018 struct netdev_queue *netif_txq; 1019 unsigned int total_bytes = 0; 1020 struct net_device *ndev; 1021 struct sk_buff *skb; 1022 dma_addr_t desc_dma; 1023 int res, num_tx = 0; 1024 1025 tx_chn = &common->tx_chns[chn]; 1026 1027 while (true) { 1028 res = k3_udma_glue_pop_tx_chn(tx_chn->tx_chn, &desc_dma); 1029 if (res == -ENODATA) 1030 break; 1031 1032 if (cppi5_desc_is_tdcm(desc_dma)) { 1033 if (atomic_dec_and_test(&common->tdown_cnt)) 1034 complete(&common->tdown_complete); 1035 break; 1036 } 1037 1038 skb = am65_cpsw_nuss_tx_compl_packet(tx_chn, desc_dma); 1039 1040 ndev = skb->dev; 1041 total_bytes += skb->len; 1042 napi_consume_skb(skb, budget); 1043 num_tx++; 1044 } 1045 1046 if (!num_tx) 1047 return 0; 1048 1049 netif_txq = netdev_get_tx_queue(ndev, chn); 1050 1051 netdev_tx_completed_queue(netif_txq, num_tx, total_bytes); 1052 1053 am65_cpsw_nuss_tx_wake(tx_chn, ndev, netif_txq); 1054 1055 dev_dbg(dev, "%s:%u pkt:%d\n", __func__, chn, num_tx); 1056 1057 return num_tx; 1058 } 1059 1060 static int am65_cpsw_nuss_tx_poll(struct napi_struct *napi_tx, int budget) 1061 { 1062 struct am65_cpsw_tx_chn *tx_chn = am65_cpsw_napi_to_tx_chn(napi_tx); 1063 int num_tx; 1064 1065 if (AM65_CPSW_IS_CPSW2G(tx_chn->common)) 1066 num_tx = am65_cpsw_nuss_tx_compl_packets_2g(tx_chn->common, tx_chn->id, budget); 1067 else 1068 num_tx = am65_cpsw_nuss_tx_compl_packets(tx_chn->common, tx_chn->id, budget); 1069 1070 num_tx = min(num_tx, budget); 1071 if (num_tx < budget) { 1072 napi_complete(napi_tx); 1073 enable_irq(tx_chn->irq); 1074 } 1075 1076 return num_tx; 1077 } 1078 1079 static irqreturn_t am65_cpsw_nuss_rx_irq(int irq, void *dev_id) 1080 { 1081 struct am65_cpsw_common *common = dev_id; 1082 1083 disable_irq_nosync(irq); 1084 napi_schedule(&common->napi_rx); 1085 1086 return IRQ_HANDLED; 1087 } 1088 1089 static irqreturn_t am65_cpsw_nuss_tx_irq(int irq, void *dev_id) 1090 { 1091 struct am65_cpsw_tx_chn *tx_chn = dev_id; 1092 1093 disable_irq_nosync(irq); 1094 napi_schedule(&tx_chn->napi_tx); 1095 1096 return IRQ_HANDLED; 1097 } 1098 1099 static netdev_tx_t am65_cpsw_nuss_ndo_slave_xmit(struct sk_buff *skb, 1100 struct net_device *ndev) 1101 { 1102 struct am65_cpsw_common *common = am65_ndev_to_common(ndev); 1103 struct cppi5_host_desc_t *first_desc, *next_desc, *cur_desc; 1104 struct am65_cpsw_port *port = am65_ndev_to_port(ndev); 1105 struct device *dev = common->dev; 1106 struct am65_cpsw_tx_chn *tx_chn; 1107 struct netdev_queue *netif_txq; 1108 dma_addr_t desc_dma, buf_dma; 1109 int ret, q_idx, i; 1110 void **swdata; 1111 u32 *psdata; 1112 u32 pkt_len; 1113 1114 /* padding enabled in hw */ 1115 pkt_len = skb_headlen(skb); 1116 1117 /* SKB TX timestamp */ 1118 if (port->tx_ts_enabled) 1119 am65_cpts_prep_tx_timestamp(common->cpts, skb); 1120 1121 q_idx = skb_get_queue_mapping(skb); 1122 dev_dbg(dev, "%s skb_queue:%d\n", __func__, q_idx); 1123 1124 tx_chn = &common->tx_chns[q_idx]; 1125 netif_txq = netdev_get_tx_queue(ndev, q_idx); 1126 1127 /* Map the linear buffer */ 1128 buf_dma = dma_map_single(tx_chn->dma_dev, skb->data, pkt_len, 1129 DMA_TO_DEVICE); 1130 if (unlikely(dma_mapping_error(tx_chn->dma_dev, buf_dma))) { 1131 dev_err(dev, "Failed to map tx skb buffer\n"); 1132 ndev->stats.tx_errors++; 1133 goto err_free_skb; 1134 } 1135 1136 first_desc = k3_cppi_desc_pool_alloc(tx_chn->desc_pool); 1137 if (!first_desc) { 1138 dev_dbg(dev, "Failed to allocate descriptor\n"); 1139 dma_unmap_single(tx_chn->dma_dev, buf_dma, pkt_len, 1140 DMA_TO_DEVICE); 1141 goto busy_stop_q; 1142 } 1143 1144 cppi5_hdesc_init(first_desc, CPPI5_INFO0_HDESC_EPIB_PRESENT, 1145 AM65_CPSW_NAV_PS_DATA_SIZE); 1146 cppi5_desc_set_pktids(&first_desc->hdr, 0, 0x3FFF); 1147 cppi5_hdesc_set_pkttype(first_desc, 0x7); 1148 cppi5_desc_set_tags_ids(&first_desc->hdr, 0, port->port_id); 1149 1150 k3_udma_glue_tx_dma_to_cppi5_addr(tx_chn->tx_chn, &buf_dma); 1151 cppi5_hdesc_attach_buf(first_desc, buf_dma, pkt_len, buf_dma, pkt_len); 1152 swdata = cppi5_hdesc_get_swdata(first_desc); 1153 *(swdata) = skb; 1154 psdata = cppi5_hdesc_get_psdata(first_desc); 1155 1156 /* HW csum offload if enabled */ 1157 psdata[2] = 0; 1158 if (likely(skb->ip_summed == CHECKSUM_PARTIAL)) { 1159 unsigned int cs_start, cs_offset; 1160 1161 cs_start = skb_transport_offset(skb); 1162 cs_offset = cs_start + skb->csum_offset; 1163 /* HW numerates bytes starting from 1 */ 1164 psdata[2] = ((cs_offset + 1) << 24) | 1165 ((cs_start + 1) << 16) | (skb->len - cs_start); 1166 dev_dbg(dev, "%s tx psdata:%#x\n", __func__, psdata[2]); 1167 } 1168 1169 if (!skb_is_nonlinear(skb)) 1170 goto done_tx; 1171 1172 dev_dbg(dev, "fragmented SKB\n"); 1173 1174 /* Handle the case where skb is fragmented in pages */ 1175 cur_desc = first_desc; 1176 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { 1177 skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 1178 u32 frag_size = skb_frag_size(frag); 1179 1180 next_desc = k3_cppi_desc_pool_alloc(tx_chn->desc_pool); 1181 if (!next_desc) { 1182 dev_err(dev, "Failed to allocate descriptor\n"); 1183 goto busy_free_descs; 1184 } 1185 1186 buf_dma = skb_frag_dma_map(tx_chn->dma_dev, frag, 0, frag_size, 1187 DMA_TO_DEVICE); 1188 if (unlikely(dma_mapping_error(tx_chn->dma_dev, buf_dma))) { 1189 dev_err(dev, "Failed to map tx skb page\n"); 1190 k3_cppi_desc_pool_free(tx_chn->desc_pool, next_desc); 1191 ndev->stats.tx_errors++; 1192 goto err_free_descs; 1193 } 1194 1195 cppi5_hdesc_reset_hbdesc(next_desc); 1196 k3_udma_glue_tx_dma_to_cppi5_addr(tx_chn->tx_chn, &buf_dma); 1197 cppi5_hdesc_attach_buf(next_desc, 1198 buf_dma, frag_size, buf_dma, frag_size); 1199 1200 desc_dma = k3_cppi_desc_pool_virt2dma(tx_chn->desc_pool, 1201 next_desc); 1202 k3_udma_glue_tx_dma_to_cppi5_addr(tx_chn->tx_chn, &desc_dma); 1203 cppi5_hdesc_link_hbdesc(cur_desc, desc_dma); 1204 1205 pkt_len += frag_size; 1206 cur_desc = next_desc; 1207 } 1208 WARN_ON(pkt_len != skb->len); 1209 1210 done_tx: 1211 skb_tx_timestamp(skb); 1212 1213 /* report bql before sending packet */ 1214 netdev_tx_sent_queue(netif_txq, pkt_len); 1215 1216 cppi5_hdesc_set_pktlen(first_desc, pkt_len); 1217 desc_dma = k3_cppi_desc_pool_virt2dma(tx_chn->desc_pool, first_desc); 1218 if (AM65_CPSW_IS_CPSW2G(common)) { 1219 ret = k3_udma_glue_push_tx_chn(tx_chn->tx_chn, first_desc, desc_dma); 1220 } else { 1221 spin_lock_bh(&tx_chn->lock); 1222 ret = k3_udma_glue_push_tx_chn(tx_chn->tx_chn, first_desc, desc_dma); 1223 spin_unlock_bh(&tx_chn->lock); 1224 } 1225 if (ret) { 1226 dev_err(dev, "can't push desc %d\n", ret); 1227 /* inform bql */ 1228 netdev_tx_completed_queue(netif_txq, 1, pkt_len); 1229 ndev->stats.tx_errors++; 1230 goto err_free_descs; 1231 } 1232 1233 if (k3_cppi_desc_pool_avail(tx_chn->desc_pool) < MAX_SKB_FRAGS) { 1234 netif_tx_stop_queue(netif_txq); 1235 /* Barrier, so that stop_queue visible to other cpus */ 1236 smp_mb__after_atomic(); 1237 dev_dbg(dev, "netif_tx_stop_queue %d\n", q_idx); 1238 1239 /* re-check for smp */ 1240 if (k3_cppi_desc_pool_avail(tx_chn->desc_pool) >= 1241 MAX_SKB_FRAGS) { 1242 netif_tx_wake_queue(netif_txq); 1243 dev_dbg(dev, "netif_tx_wake_queue %d\n", q_idx); 1244 } 1245 } 1246 1247 return NETDEV_TX_OK; 1248 1249 err_free_descs: 1250 am65_cpsw_nuss_xmit_free(tx_chn, first_desc); 1251 err_free_skb: 1252 ndev->stats.tx_dropped++; 1253 dev_kfree_skb_any(skb); 1254 return NETDEV_TX_OK; 1255 1256 busy_free_descs: 1257 am65_cpsw_nuss_xmit_free(tx_chn, first_desc); 1258 busy_stop_q: 1259 netif_tx_stop_queue(netif_txq); 1260 return NETDEV_TX_BUSY; 1261 } 1262 1263 static int am65_cpsw_nuss_ndo_slave_set_mac_address(struct net_device *ndev, 1264 void *addr) 1265 { 1266 struct am65_cpsw_common *common = am65_ndev_to_common(ndev); 1267 struct am65_cpsw_port *port = am65_ndev_to_port(ndev); 1268 struct sockaddr *sockaddr = (struct sockaddr *)addr; 1269 int ret; 1270 1271 ret = eth_prepare_mac_addr_change(ndev, addr); 1272 if (ret < 0) 1273 return ret; 1274 1275 ret = pm_runtime_get_sync(common->dev); 1276 if (ret < 0) { 1277 pm_runtime_put_noidle(common->dev); 1278 return ret; 1279 } 1280 1281 cpsw_ale_del_ucast(common->ale, ndev->dev_addr, 1282 HOST_PORT_NUM, 0, 0); 1283 cpsw_ale_add_ucast(common->ale, sockaddr->sa_data, 1284 HOST_PORT_NUM, ALE_SECURE, 0); 1285 1286 am65_cpsw_port_set_sl_mac(port, addr); 1287 eth_commit_mac_addr_change(ndev, sockaddr); 1288 1289 pm_runtime_put(common->dev); 1290 1291 return 0; 1292 } 1293 1294 static int am65_cpsw_nuss_hwtstamp_set(struct net_device *ndev, 1295 struct ifreq *ifr) 1296 { 1297 struct am65_cpsw_common *common = am65_ndev_to_common(ndev); 1298 struct am65_cpsw_port *port = am65_ndev_to_port(ndev); 1299 u32 ts_ctrl, seq_id, ts_ctrl_ltype2, ts_vlan_ltype; 1300 struct hwtstamp_config cfg; 1301 1302 if (!IS_ENABLED(CONFIG_TI_K3_AM65_CPTS)) 1303 return -EOPNOTSUPP; 1304 1305 if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg))) 1306 return -EFAULT; 1307 1308 /* TX HW timestamp */ 1309 switch (cfg.tx_type) { 1310 case HWTSTAMP_TX_OFF: 1311 case HWTSTAMP_TX_ON: 1312 break; 1313 default: 1314 return -ERANGE; 1315 } 1316 1317 switch (cfg.rx_filter) { 1318 case HWTSTAMP_FILTER_NONE: 1319 port->rx_ts_enabled = false; 1320 break; 1321 case HWTSTAMP_FILTER_ALL: 1322 case HWTSTAMP_FILTER_SOME: 1323 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: 1324 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: 1325 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: 1326 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: 1327 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 1328 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 1329 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: 1330 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: 1331 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: 1332 case HWTSTAMP_FILTER_PTP_V2_EVENT: 1333 case HWTSTAMP_FILTER_PTP_V2_SYNC: 1334 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 1335 case HWTSTAMP_FILTER_NTP_ALL: 1336 port->rx_ts_enabled = true; 1337 cfg.rx_filter = HWTSTAMP_FILTER_ALL; 1338 break; 1339 default: 1340 return -ERANGE; 1341 } 1342 1343 port->tx_ts_enabled = (cfg.tx_type == HWTSTAMP_TX_ON); 1344 1345 /* cfg TX timestamp */ 1346 seq_id = (AM65_CPSW_TS_SEQ_ID_OFFSET << 1347 AM65_CPSW_PN_TS_SEQ_ID_OFFSET_SHIFT) | ETH_P_1588; 1348 1349 ts_vlan_ltype = ETH_P_8021Q; 1350 1351 ts_ctrl_ltype2 = ETH_P_1588 | 1352 AM65_CPSW_PN_TS_CTL_LTYPE2_TS_107 | 1353 AM65_CPSW_PN_TS_CTL_LTYPE2_TS_129 | 1354 AM65_CPSW_PN_TS_CTL_LTYPE2_TS_130 | 1355 AM65_CPSW_PN_TS_CTL_LTYPE2_TS_131 | 1356 AM65_CPSW_PN_TS_CTL_LTYPE2_TS_132 | 1357 AM65_CPSW_PN_TS_CTL_LTYPE2_TS_319 | 1358 AM65_CPSW_PN_TS_CTL_LTYPE2_TS_320 | 1359 AM65_CPSW_PN_TS_CTL_LTYPE2_TS_TTL_NONZERO; 1360 1361 ts_ctrl = AM65_CPSW_TS_EVENT_MSG_TYPE_BITS << 1362 AM65_CPSW_PN_TS_CTL_MSG_TYPE_EN_SHIFT; 1363 1364 if (port->tx_ts_enabled) 1365 ts_ctrl |= AM65_CPSW_TS_TX_ANX_ALL_EN | 1366 AM65_CPSW_PN_TS_CTL_TX_VLAN_LT1_EN; 1367 1368 writel(seq_id, port->port_base + AM65_CPSW_PORTN_REG_TS_SEQ_LTYPE_REG); 1369 writel(ts_vlan_ltype, port->port_base + 1370 AM65_CPSW_PORTN_REG_TS_VLAN_LTYPE_REG); 1371 writel(ts_ctrl_ltype2, port->port_base + 1372 AM65_CPSW_PORTN_REG_TS_CTL_LTYPE2); 1373 writel(ts_ctrl, port->port_base + AM65_CPSW_PORTN_REG_TS_CTL); 1374 1375 /* en/dis RX timestamp */ 1376 am65_cpts_rx_enable(common->cpts, port->rx_ts_enabled); 1377 1378 return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0; 1379 } 1380 1381 static int am65_cpsw_nuss_hwtstamp_get(struct net_device *ndev, 1382 struct ifreq *ifr) 1383 { 1384 struct am65_cpsw_port *port = am65_ndev_to_port(ndev); 1385 struct hwtstamp_config cfg; 1386 1387 if (!IS_ENABLED(CONFIG_TI_K3_AM65_CPTS)) 1388 return -EOPNOTSUPP; 1389 1390 cfg.flags = 0; 1391 cfg.tx_type = port->tx_ts_enabled ? 1392 HWTSTAMP_TX_ON : HWTSTAMP_TX_OFF; 1393 cfg.rx_filter = port->rx_ts_enabled ? 1394 HWTSTAMP_FILTER_ALL : HWTSTAMP_FILTER_NONE; 1395 1396 return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0; 1397 } 1398 1399 static int am65_cpsw_nuss_ndo_slave_ioctl(struct net_device *ndev, 1400 struct ifreq *req, int cmd) 1401 { 1402 struct am65_cpsw_port *port = am65_ndev_to_port(ndev); 1403 1404 if (!netif_running(ndev)) 1405 return -EINVAL; 1406 1407 switch (cmd) { 1408 case SIOCSHWTSTAMP: 1409 return am65_cpsw_nuss_hwtstamp_set(ndev, req); 1410 case SIOCGHWTSTAMP: 1411 return am65_cpsw_nuss_hwtstamp_get(ndev, req); 1412 } 1413 1414 if (!port->slave.phy) 1415 return -EOPNOTSUPP; 1416 1417 return phy_mii_ioctl(port->slave.phy, req, cmd); 1418 } 1419 1420 static void am65_cpsw_nuss_ndo_get_stats(struct net_device *dev, 1421 struct rtnl_link_stats64 *stats) 1422 { 1423 struct am65_cpsw_ndev_priv *ndev_priv = netdev_priv(dev); 1424 unsigned int start; 1425 int cpu; 1426 1427 for_each_possible_cpu(cpu) { 1428 struct am65_cpsw_ndev_stats *cpu_stats; 1429 u64 rx_packets; 1430 u64 rx_bytes; 1431 u64 tx_packets; 1432 u64 tx_bytes; 1433 1434 cpu_stats = per_cpu_ptr(ndev_priv->stats, cpu); 1435 do { 1436 start = u64_stats_fetch_begin_irq(&cpu_stats->syncp); 1437 rx_packets = cpu_stats->rx_packets; 1438 rx_bytes = cpu_stats->rx_bytes; 1439 tx_packets = cpu_stats->tx_packets; 1440 tx_bytes = cpu_stats->tx_bytes; 1441 } while (u64_stats_fetch_retry_irq(&cpu_stats->syncp, start)); 1442 1443 stats->rx_packets += rx_packets; 1444 stats->rx_bytes += rx_bytes; 1445 stats->tx_packets += tx_packets; 1446 stats->tx_bytes += tx_bytes; 1447 } 1448 1449 stats->rx_errors = dev->stats.rx_errors; 1450 stats->rx_dropped = dev->stats.rx_dropped; 1451 stats->tx_dropped = dev->stats.tx_dropped; 1452 } 1453 1454 static const struct net_device_ops am65_cpsw_nuss_netdev_ops = { 1455 .ndo_open = am65_cpsw_nuss_ndo_slave_open, 1456 .ndo_stop = am65_cpsw_nuss_ndo_slave_stop, 1457 .ndo_start_xmit = am65_cpsw_nuss_ndo_slave_xmit, 1458 .ndo_set_rx_mode = am65_cpsw_nuss_ndo_slave_set_rx_mode, 1459 .ndo_get_stats64 = am65_cpsw_nuss_ndo_get_stats, 1460 .ndo_validate_addr = eth_validate_addr, 1461 .ndo_set_mac_address = am65_cpsw_nuss_ndo_slave_set_mac_address, 1462 .ndo_tx_timeout = am65_cpsw_nuss_ndo_host_tx_timeout, 1463 .ndo_vlan_rx_add_vid = am65_cpsw_nuss_ndo_slave_add_vid, 1464 .ndo_vlan_rx_kill_vid = am65_cpsw_nuss_ndo_slave_kill_vid, 1465 .ndo_do_ioctl = am65_cpsw_nuss_ndo_slave_ioctl, 1466 .ndo_setup_tc = am65_cpsw_qos_ndo_setup_tc, 1467 }; 1468 1469 static void am65_cpsw_nuss_slave_disable_unused(struct am65_cpsw_port *port) 1470 { 1471 struct am65_cpsw_common *common = port->common; 1472 1473 if (!port->disabled) 1474 return; 1475 1476 cpsw_ale_control_set(common->ale, port->port_id, 1477 ALE_PORT_STATE, ALE_PORT_STATE_DISABLE); 1478 1479 cpsw_sl_reset(port->slave.mac_sl, 100); 1480 cpsw_sl_ctl_reset(port->slave.mac_sl); 1481 } 1482 1483 static void am65_cpsw_nuss_free_tx_chns(void *data) 1484 { 1485 struct am65_cpsw_common *common = data; 1486 int i; 1487 1488 for (i = 0; i < common->tx_ch_num; i++) { 1489 struct am65_cpsw_tx_chn *tx_chn = &common->tx_chns[i]; 1490 1491 if (!IS_ERR_OR_NULL(tx_chn->tx_chn)) 1492 k3_udma_glue_release_tx_chn(tx_chn->tx_chn); 1493 1494 if (!IS_ERR_OR_NULL(tx_chn->desc_pool)) 1495 k3_cppi_desc_pool_destroy(tx_chn->desc_pool); 1496 1497 memset(tx_chn, 0, sizeof(*tx_chn)); 1498 } 1499 } 1500 1501 void am65_cpsw_nuss_remove_tx_chns(struct am65_cpsw_common *common) 1502 { 1503 struct device *dev = common->dev; 1504 int i; 1505 1506 devm_remove_action(dev, am65_cpsw_nuss_free_tx_chns, common); 1507 1508 for (i = 0; i < common->tx_ch_num; i++) { 1509 struct am65_cpsw_tx_chn *tx_chn = &common->tx_chns[i]; 1510 1511 if (tx_chn->irq) 1512 devm_free_irq(dev, tx_chn->irq, tx_chn); 1513 1514 netif_napi_del(&tx_chn->napi_tx); 1515 1516 if (!IS_ERR_OR_NULL(tx_chn->tx_chn)) 1517 k3_udma_glue_release_tx_chn(tx_chn->tx_chn); 1518 1519 if (!IS_ERR_OR_NULL(tx_chn->desc_pool)) 1520 k3_cppi_desc_pool_destroy(tx_chn->desc_pool); 1521 1522 memset(tx_chn, 0, sizeof(*tx_chn)); 1523 } 1524 } 1525 1526 static int am65_cpsw_nuss_init_tx_chns(struct am65_cpsw_common *common) 1527 { 1528 u32 max_desc_num = ALIGN(AM65_CPSW_MAX_TX_DESC, MAX_SKB_FRAGS); 1529 struct k3_udma_glue_tx_channel_cfg tx_cfg = { 0 }; 1530 struct device *dev = common->dev; 1531 struct k3_ring_cfg ring_cfg = { 1532 .elm_size = K3_RINGACC_RING_ELSIZE_8, 1533 .mode = K3_RINGACC_RING_MODE_RING, 1534 .flags = 0 1535 }; 1536 u32 hdesc_size; 1537 int i, ret = 0; 1538 1539 hdesc_size = cppi5_hdesc_calc_size(true, AM65_CPSW_NAV_PS_DATA_SIZE, 1540 AM65_CPSW_NAV_SW_DATA_SIZE); 1541 1542 tx_cfg.swdata_size = AM65_CPSW_NAV_SW_DATA_SIZE; 1543 tx_cfg.tx_cfg = ring_cfg; 1544 tx_cfg.txcq_cfg = ring_cfg; 1545 tx_cfg.tx_cfg.size = max_desc_num; 1546 tx_cfg.txcq_cfg.size = max_desc_num; 1547 1548 for (i = 0; i < common->tx_ch_num; i++) { 1549 struct am65_cpsw_tx_chn *tx_chn = &common->tx_chns[i]; 1550 1551 snprintf(tx_chn->tx_chn_name, 1552 sizeof(tx_chn->tx_chn_name), "tx%d", i); 1553 1554 spin_lock_init(&tx_chn->lock); 1555 tx_chn->common = common; 1556 tx_chn->id = i; 1557 tx_chn->descs_num = max_desc_num; 1558 1559 tx_chn->tx_chn = 1560 k3_udma_glue_request_tx_chn(dev, 1561 tx_chn->tx_chn_name, 1562 &tx_cfg); 1563 if (IS_ERR(tx_chn->tx_chn)) { 1564 ret = dev_err_probe(dev, PTR_ERR(tx_chn->tx_chn), 1565 "Failed to request tx dma channel\n"); 1566 goto err; 1567 } 1568 tx_chn->dma_dev = k3_udma_glue_tx_get_dma_device(tx_chn->tx_chn); 1569 1570 tx_chn->desc_pool = k3_cppi_desc_pool_create_name(tx_chn->dma_dev, 1571 tx_chn->descs_num, 1572 hdesc_size, 1573 tx_chn->tx_chn_name); 1574 if (IS_ERR(tx_chn->desc_pool)) { 1575 ret = PTR_ERR(tx_chn->desc_pool); 1576 dev_err(dev, "Failed to create poll %d\n", ret); 1577 goto err; 1578 } 1579 1580 tx_chn->irq = k3_udma_glue_tx_get_irq(tx_chn->tx_chn); 1581 if (tx_chn->irq <= 0) { 1582 dev_err(dev, "Failed to get tx dma irq %d\n", 1583 tx_chn->irq); 1584 goto err; 1585 } 1586 1587 snprintf(tx_chn->tx_chn_name, 1588 sizeof(tx_chn->tx_chn_name), "%s-tx%d", 1589 dev_name(dev), tx_chn->id); 1590 } 1591 1592 err: 1593 i = devm_add_action(dev, am65_cpsw_nuss_free_tx_chns, common); 1594 if (i) { 1595 dev_err(dev, "Failed to add free_tx_chns action %d\n", i); 1596 return i; 1597 } 1598 1599 return ret; 1600 } 1601 1602 static void am65_cpsw_nuss_free_rx_chns(void *data) 1603 { 1604 struct am65_cpsw_common *common = data; 1605 struct am65_cpsw_rx_chn *rx_chn; 1606 1607 rx_chn = &common->rx_chns; 1608 1609 if (!IS_ERR_OR_NULL(rx_chn->rx_chn)) 1610 k3_udma_glue_release_rx_chn(rx_chn->rx_chn); 1611 1612 if (!IS_ERR_OR_NULL(rx_chn->desc_pool)) 1613 k3_cppi_desc_pool_destroy(rx_chn->desc_pool); 1614 } 1615 1616 static int am65_cpsw_nuss_init_rx_chns(struct am65_cpsw_common *common) 1617 { 1618 struct am65_cpsw_rx_chn *rx_chn = &common->rx_chns; 1619 struct k3_udma_glue_rx_channel_cfg rx_cfg = { 0 }; 1620 u32 max_desc_num = AM65_CPSW_MAX_RX_DESC; 1621 struct device *dev = common->dev; 1622 u32 hdesc_size; 1623 u32 fdqring_id; 1624 int i, ret = 0; 1625 1626 hdesc_size = cppi5_hdesc_calc_size(true, AM65_CPSW_NAV_PS_DATA_SIZE, 1627 AM65_CPSW_NAV_SW_DATA_SIZE); 1628 1629 rx_cfg.swdata_size = AM65_CPSW_NAV_SW_DATA_SIZE; 1630 rx_cfg.flow_id_num = AM65_CPSW_MAX_RX_FLOWS; 1631 rx_cfg.flow_id_base = common->rx_flow_id_base; 1632 1633 /* init all flows */ 1634 rx_chn->dev = dev; 1635 rx_chn->descs_num = max_desc_num; 1636 1637 rx_chn->rx_chn = k3_udma_glue_request_rx_chn(dev, "rx", &rx_cfg); 1638 if (IS_ERR(rx_chn->rx_chn)) { 1639 ret = dev_err_probe(dev, PTR_ERR(rx_chn->rx_chn), 1640 "Failed to request rx dma channel\n"); 1641 goto err; 1642 } 1643 rx_chn->dma_dev = k3_udma_glue_rx_get_dma_device(rx_chn->rx_chn); 1644 1645 rx_chn->desc_pool = k3_cppi_desc_pool_create_name(rx_chn->dma_dev, 1646 rx_chn->descs_num, 1647 hdesc_size, "rx"); 1648 if (IS_ERR(rx_chn->desc_pool)) { 1649 ret = PTR_ERR(rx_chn->desc_pool); 1650 dev_err(dev, "Failed to create rx poll %d\n", ret); 1651 goto err; 1652 } 1653 1654 common->rx_flow_id_base = 1655 k3_udma_glue_rx_get_flow_id_base(rx_chn->rx_chn); 1656 dev_info(dev, "set new flow-id-base %u\n", common->rx_flow_id_base); 1657 1658 fdqring_id = K3_RINGACC_RING_ID_ANY; 1659 for (i = 0; i < rx_cfg.flow_id_num; i++) { 1660 struct k3_ring_cfg rxring_cfg = { 1661 .elm_size = K3_RINGACC_RING_ELSIZE_8, 1662 .mode = K3_RINGACC_RING_MODE_RING, 1663 .flags = 0, 1664 }; 1665 struct k3_ring_cfg fdqring_cfg = { 1666 .elm_size = K3_RINGACC_RING_ELSIZE_8, 1667 .flags = K3_RINGACC_RING_SHARED, 1668 }; 1669 struct k3_udma_glue_rx_flow_cfg rx_flow_cfg = { 1670 .rx_cfg = rxring_cfg, 1671 .rxfdq_cfg = fdqring_cfg, 1672 .ring_rxq_id = K3_RINGACC_RING_ID_ANY, 1673 .src_tag_lo_sel = 1674 K3_UDMA_GLUE_SRC_TAG_LO_USE_REMOTE_SRC_TAG, 1675 }; 1676 1677 rx_flow_cfg.ring_rxfdq0_id = fdqring_id; 1678 rx_flow_cfg.rx_cfg.size = max_desc_num; 1679 rx_flow_cfg.rxfdq_cfg.size = max_desc_num; 1680 rx_flow_cfg.rxfdq_cfg.mode = common->pdata.fdqring_mode; 1681 1682 ret = k3_udma_glue_rx_flow_init(rx_chn->rx_chn, 1683 i, &rx_flow_cfg); 1684 if (ret) { 1685 dev_err(dev, "Failed to init rx flow%d %d\n", i, ret); 1686 goto err; 1687 } 1688 if (!i) 1689 fdqring_id = 1690 k3_udma_glue_rx_flow_get_fdq_id(rx_chn->rx_chn, 1691 i); 1692 1693 rx_chn->irq = k3_udma_glue_rx_get_irq(rx_chn->rx_chn, i); 1694 1695 if (rx_chn->irq <= 0) { 1696 dev_err(dev, "Failed to get rx dma irq %d\n", 1697 rx_chn->irq); 1698 ret = -ENXIO; 1699 goto err; 1700 } 1701 } 1702 1703 err: 1704 i = devm_add_action(dev, am65_cpsw_nuss_free_rx_chns, common); 1705 if (i) { 1706 dev_err(dev, "Failed to add free_rx_chns action %d\n", i); 1707 return i; 1708 } 1709 1710 return ret; 1711 } 1712 1713 static int am65_cpsw_nuss_init_host_p(struct am65_cpsw_common *common) 1714 { 1715 struct am65_cpsw_host *host_p = am65_common_get_host(common); 1716 1717 host_p->common = common; 1718 host_p->port_base = common->cpsw_base + AM65_CPSW_NU_PORTS_BASE; 1719 host_p->stat_base = common->cpsw_base + AM65_CPSW_NU_STATS_BASE; 1720 1721 return 0; 1722 } 1723 1724 static int am65_cpsw_am654_get_efuse_macid(struct device_node *of_node, 1725 int slave, u8 *mac_addr) 1726 { 1727 u32 mac_lo, mac_hi, offset; 1728 struct regmap *syscon; 1729 int ret; 1730 1731 syscon = syscon_regmap_lookup_by_phandle(of_node, "ti,syscon-efuse"); 1732 if (IS_ERR(syscon)) { 1733 if (PTR_ERR(syscon) == -ENODEV) 1734 return 0; 1735 return PTR_ERR(syscon); 1736 } 1737 1738 ret = of_property_read_u32_index(of_node, "ti,syscon-efuse", 1, 1739 &offset); 1740 if (ret) 1741 return ret; 1742 1743 regmap_read(syscon, offset, &mac_lo); 1744 regmap_read(syscon, offset + 4, &mac_hi); 1745 1746 mac_addr[0] = (mac_hi >> 8) & 0xff; 1747 mac_addr[1] = mac_hi & 0xff; 1748 mac_addr[2] = (mac_lo >> 24) & 0xff; 1749 mac_addr[3] = (mac_lo >> 16) & 0xff; 1750 mac_addr[4] = (mac_lo >> 8) & 0xff; 1751 mac_addr[5] = mac_lo & 0xff; 1752 1753 return 0; 1754 } 1755 1756 static int am65_cpsw_init_cpts(struct am65_cpsw_common *common) 1757 { 1758 struct device *dev = common->dev; 1759 struct device_node *node; 1760 struct am65_cpts *cpts; 1761 void __iomem *reg_base; 1762 1763 if (!IS_ENABLED(CONFIG_TI_K3_AM65_CPTS)) 1764 return 0; 1765 1766 node = of_get_child_by_name(dev->of_node, "cpts"); 1767 if (!node) { 1768 dev_err(dev, "%s cpts not found\n", __func__); 1769 return -ENOENT; 1770 } 1771 1772 reg_base = common->cpsw_base + AM65_CPSW_NU_CPTS_BASE; 1773 cpts = am65_cpts_create(dev, reg_base, node); 1774 if (IS_ERR(cpts)) { 1775 int ret = PTR_ERR(cpts); 1776 1777 if (ret == -EOPNOTSUPP) { 1778 dev_info(dev, "cpts disabled\n"); 1779 return 0; 1780 } 1781 1782 dev_err(dev, "cpts create err %d\n", ret); 1783 return ret; 1784 } 1785 common->cpts = cpts; 1786 /* Forbid PM runtime if CPTS is running. 1787 * K3 CPSWxG modules may completely lose context during ON->OFF 1788 * transitions depending on integration. 1789 * AM65x/J721E MCU CPSW2G: false 1790 * J721E MAIN_CPSW9G: true 1791 */ 1792 pm_runtime_forbid(dev); 1793 1794 return 0; 1795 } 1796 1797 static int am65_cpsw_nuss_init_slave_ports(struct am65_cpsw_common *common) 1798 { 1799 struct device_node *node, *port_np; 1800 struct device *dev = common->dev; 1801 int ret; 1802 1803 node = of_get_child_by_name(dev->of_node, "ethernet-ports"); 1804 if (!node) 1805 return -ENOENT; 1806 1807 for_each_child_of_node(node, port_np) { 1808 struct am65_cpsw_port *port; 1809 const void *mac_addr; 1810 u32 port_id; 1811 1812 /* it is not a slave port node, continue */ 1813 if (strcmp(port_np->name, "port")) 1814 continue; 1815 1816 ret = of_property_read_u32(port_np, "reg", &port_id); 1817 if (ret < 0) { 1818 dev_err(dev, "%pOF error reading port_id %d\n", 1819 port_np, ret); 1820 return ret; 1821 } 1822 1823 if (!port_id || port_id > common->port_num) { 1824 dev_err(dev, "%pOF has invalid port_id %u %s\n", 1825 port_np, port_id, port_np->name); 1826 return -EINVAL; 1827 } 1828 1829 port = am65_common_get_port(common, port_id); 1830 port->port_id = port_id; 1831 port->common = common; 1832 port->port_base = common->cpsw_base + AM65_CPSW_NU_PORTS_BASE + 1833 AM65_CPSW_NU_PORTS_OFFSET * (port_id); 1834 port->stat_base = common->cpsw_base + AM65_CPSW_NU_STATS_BASE + 1835 (AM65_CPSW_NU_STATS_PORT_OFFSET * port_id); 1836 port->name = of_get_property(port_np, "label", NULL); 1837 port->fetch_ram_base = 1838 common->cpsw_base + AM65_CPSW_NU_FRAM_BASE + 1839 (AM65_CPSW_NU_FRAM_PORT_OFFSET * (port_id - 1)); 1840 1841 port->slave.mac_sl = cpsw_sl_get("am65", dev, port->port_base); 1842 if (IS_ERR(port->slave.mac_sl)) 1843 return PTR_ERR(port->slave.mac_sl); 1844 1845 port->disabled = !of_device_is_available(port_np); 1846 if (port->disabled) { 1847 common->disabled_ports_mask |= BIT(port->port_id); 1848 continue; 1849 } 1850 1851 port->slave.ifphy = devm_of_phy_get(dev, port_np, NULL); 1852 if (IS_ERR(port->slave.ifphy)) { 1853 ret = PTR_ERR(port->slave.ifphy); 1854 dev_err(dev, "%pOF error retrieving port phy: %d\n", 1855 port_np, ret); 1856 return ret; 1857 } 1858 1859 port->slave.mac_only = 1860 of_property_read_bool(port_np, "ti,mac-only"); 1861 1862 /* get phy/link info */ 1863 if (of_phy_is_fixed_link(port_np)) { 1864 ret = of_phy_register_fixed_link(port_np); 1865 if (ret) 1866 return dev_err_probe(dev, ret, 1867 "failed to register fixed-link phy %pOF\n", 1868 port_np); 1869 port->slave.phy_node = of_node_get(port_np); 1870 } else { 1871 port->slave.phy_node = 1872 of_parse_phandle(port_np, "phy-handle", 0); 1873 } 1874 1875 if (!port->slave.phy_node) { 1876 dev_err(dev, 1877 "slave[%d] no phy found\n", port_id); 1878 return -ENODEV; 1879 } 1880 1881 ret = of_get_phy_mode(port_np, &port->slave.phy_if); 1882 if (ret) { 1883 dev_err(dev, "%pOF read phy-mode err %d\n", 1884 port_np, ret); 1885 return ret; 1886 } 1887 1888 mac_addr = of_get_mac_address(port_np); 1889 if (!IS_ERR(mac_addr)) { 1890 ether_addr_copy(port->slave.mac_addr, mac_addr); 1891 } else if (am65_cpsw_am654_get_efuse_macid(port_np, 1892 port->port_id, 1893 port->slave.mac_addr) || 1894 !is_valid_ether_addr(port->slave.mac_addr)) { 1895 random_ether_addr(port->slave.mac_addr); 1896 dev_err(dev, "Use random MAC address\n"); 1897 } 1898 } 1899 of_node_put(node); 1900 1901 /* is there at least one ext.port */ 1902 if (!(~common->disabled_ports_mask & GENMASK(common->port_num, 1))) { 1903 dev_err(dev, "No Ext. port are available\n"); 1904 return -ENODEV; 1905 } 1906 1907 return 0; 1908 } 1909 1910 static void am65_cpsw_pcpu_stats_free(void *data) 1911 { 1912 struct am65_cpsw_ndev_stats __percpu *stats = data; 1913 1914 free_percpu(stats); 1915 } 1916 1917 static int 1918 am65_cpsw_nuss_init_port_ndev(struct am65_cpsw_common *common, u32 port_idx) 1919 { 1920 struct am65_cpsw_ndev_priv *ndev_priv; 1921 struct device *dev = common->dev; 1922 struct am65_cpsw_port *port; 1923 int ret; 1924 1925 port = &common->ports[port_idx]; 1926 1927 if (port->disabled) 1928 return 0; 1929 1930 /* alloc netdev */ 1931 port->ndev = devm_alloc_etherdev_mqs(common->dev, 1932 sizeof(struct am65_cpsw_ndev_priv), 1933 AM65_CPSW_MAX_TX_QUEUES, 1934 AM65_CPSW_MAX_RX_QUEUES); 1935 if (!port->ndev) { 1936 dev_err(dev, "error allocating slave net_device %u\n", 1937 port->port_id); 1938 return -ENOMEM; 1939 } 1940 1941 ndev_priv = netdev_priv(port->ndev); 1942 ndev_priv->port = port; 1943 ndev_priv->msg_enable = AM65_CPSW_DEBUG; 1944 SET_NETDEV_DEV(port->ndev, dev); 1945 1946 ether_addr_copy(port->ndev->dev_addr, port->slave.mac_addr); 1947 1948 port->ndev->min_mtu = AM65_CPSW_MIN_PACKET_SIZE; 1949 port->ndev->max_mtu = AM65_CPSW_MAX_PACKET_SIZE; 1950 port->ndev->hw_features = NETIF_F_SG | 1951 NETIF_F_RXCSUM | 1952 NETIF_F_HW_CSUM | 1953 NETIF_F_HW_TC; 1954 port->ndev->features = port->ndev->hw_features | 1955 NETIF_F_HW_VLAN_CTAG_FILTER; 1956 port->ndev->vlan_features |= NETIF_F_SG; 1957 port->ndev->netdev_ops = &am65_cpsw_nuss_netdev_ops; 1958 port->ndev->ethtool_ops = &am65_cpsw_ethtool_ops_slave; 1959 1960 /* Disable TX checksum offload by default due to HW bug */ 1961 if (common->pdata.quirks & AM65_CPSW_QUIRK_I2027_NO_TX_CSUM) 1962 port->ndev->features &= ~NETIF_F_HW_CSUM; 1963 1964 ndev_priv->stats = netdev_alloc_pcpu_stats(struct am65_cpsw_ndev_stats); 1965 if (!ndev_priv->stats) 1966 return -ENOMEM; 1967 1968 ret = devm_add_action_or_reset(dev, am65_cpsw_pcpu_stats_free, 1969 ndev_priv->stats); 1970 if (ret) 1971 dev_err(dev, "failed to add percpu stat free action %d\n", ret); 1972 1973 if (!common->dma_ndev) 1974 common->dma_ndev = port->ndev; 1975 1976 return ret; 1977 } 1978 1979 static int am65_cpsw_nuss_init_ndevs(struct am65_cpsw_common *common) 1980 { 1981 int ret; 1982 int i; 1983 1984 for (i = 0; i < common->port_num; i++) { 1985 ret = am65_cpsw_nuss_init_port_ndev(common, i); 1986 if (ret) 1987 return ret; 1988 } 1989 1990 netif_napi_add(common->dma_ndev, &common->napi_rx, 1991 am65_cpsw_nuss_rx_poll, NAPI_POLL_WEIGHT); 1992 1993 return ret; 1994 } 1995 1996 static int am65_cpsw_nuss_ndev_add_tx_napi(struct am65_cpsw_common *common) 1997 { 1998 struct device *dev = common->dev; 1999 int i, ret = 0; 2000 2001 for (i = 0; i < common->tx_ch_num; i++) { 2002 struct am65_cpsw_tx_chn *tx_chn = &common->tx_chns[i]; 2003 2004 netif_tx_napi_add(common->dma_ndev, &tx_chn->napi_tx, 2005 am65_cpsw_nuss_tx_poll, NAPI_POLL_WEIGHT); 2006 2007 ret = devm_request_irq(dev, tx_chn->irq, 2008 am65_cpsw_nuss_tx_irq, 2009 IRQF_TRIGGER_HIGH, 2010 tx_chn->tx_chn_name, tx_chn); 2011 if (ret) { 2012 dev_err(dev, "failure requesting tx%u irq %u, %d\n", 2013 tx_chn->id, tx_chn->irq, ret); 2014 goto err; 2015 } 2016 } 2017 2018 err: 2019 return ret; 2020 } 2021 2022 static void am65_cpsw_nuss_cleanup_ndev(struct am65_cpsw_common *common) 2023 { 2024 struct am65_cpsw_port *port; 2025 int i; 2026 2027 for (i = 0; i < common->port_num; i++) { 2028 port = &common->ports[i]; 2029 if (port->ndev) 2030 unregister_netdev(port->ndev); 2031 } 2032 } 2033 2034 static int am65_cpsw_nuss_register_ndevs(struct am65_cpsw_common *common) 2035 { 2036 struct device *dev = common->dev; 2037 struct am65_cpsw_port *port; 2038 int ret = 0, i; 2039 2040 ret = am65_cpsw_nuss_ndev_add_tx_napi(common); 2041 if (ret) 2042 return ret; 2043 2044 ret = devm_request_irq(dev, common->rx_chns.irq, 2045 am65_cpsw_nuss_rx_irq, 2046 IRQF_TRIGGER_HIGH, dev_name(dev), common); 2047 if (ret) { 2048 dev_err(dev, "failure requesting rx irq %u, %d\n", 2049 common->rx_chns.irq, ret); 2050 return ret; 2051 } 2052 2053 for (i = 0; i < common->port_num; i++) { 2054 port = &common->ports[i]; 2055 2056 if (!port->ndev) 2057 continue; 2058 2059 ret = register_netdev(port->ndev); 2060 if (ret) { 2061 dev_err(dev, "error registering slave net device%i %d\n", 2062 i, ret); 2063 goto err_cleanup_ndev; 2064 } 2065 } 2066 2067 2068 /* can't auto unregister ndev using devm_add_action() due to 2069 * devres release sequence in DD core for DMA 2070 */ 2071 return 0; 2072 2073 err_cleanup_ndev: 2074 am65_cpsw_nuss_cleanup_ndev(common); 2075 return ret; 2076 } 2077 2078 int am65_cpsw_nuss_update_tx_chns(struct am65_cpsw_common *common, int num_tx) 2079 { 2080 int ret; 2081 2082 common->tx_ch_num = num_tx; 2083 ret = am65_cpsw_nuss_init_tx_chns(common); 2084 if (ret) 2085 return ret; 2086 2087 return am65_cpsw_nuss_ndev_add_tx_napi(common); 2088 } 2089 2090 struct am65_cpsw_soc_pdata { 2091 u32 quirks_dis; 2092 }; 2093 2094 static const struct am65_cpsw_soc_pdata am65x_soc_sr2_0 = { 2095 .quirks_dis = AM65_CPSW_QUIRK_I2027_NO_TX_CSUM, 2096 }; 2097 2098 static const struct soc_device_attribute am65_cpsw_socinfo[] = { 2099 { .family = "AM65X", 2100 .revision = "SR2.0", 2101 .data = &am65x_soc_sr2_0 2102 }, 2103 {/* sentinel */} 2104 }; 2105 2106 static const struct am65_cpsw_pdata am65x_sr1_0 = { 2107 .quirks = AM65_CPSW_QUIRK_I2027_NO_TX_CSUM, 2108 .ale_dev_id = "am65x-cpsw2g", 2109 .fdqring_mode = K3_RINGACC_RING_MODE_MESSAGE, 2110 }; 2111 2112 static const struct am65_cpsw_pdata j721e_pdata = { 2113 .quirks = 0, 2114 .ale_dev_id = "am65x-cpsw2g", 2115 .fdqring_mode = K3_RINGACC_RING_MODE_MESSAGE, 2116 }; 2117 2118 static const struct am65_cpsw_pdata am64x_cpswxg_pdata = { 2119 .quirks = 0, 2120 .ale_dev_id = "am64-cpswxg", 2121 .fdqring_mode = K3_RINGACC_RING_MODE_RING, 2122 }; 2123 2124 static const struct of_device_id am65_cpsw_nuss_of_mtable[] = { 2125 { .compatible = "ti,am654-cpsw-nuss", .data = &am65x_sr1_0}, 2126 { .compatible = "ti,j721e-cpsw-nuss", .data = &j721e_pdata}, 2127 { .compatible = "ti,am642-cpsw-nuss", .data = &am64x_cpswxg_pdata}, 2128 { /* sentinel */ }, 2129 }; 2130 MODULE_DEVICE_TABLE(of, am65_cpsw_nuss_of_mtable); 2131 2132 static void am65_cpsw_nuss_apply_socinfo(struct am65_cpsw_common *common) 2133 { 2134 const struct soc_device_attribute *soc; 2135 2136 soc = soc_device_match(am65_cpsw_socinfo); 2137 if (soc && soc->data) { 2138 const struct am65_cpsw_soc_pdata *socdata = soc->data; 2139 2140 /* disable quirks */ 2141 common->pdata.quirks &= ~socdata->quirks_dis; 2142 } 2143 } 2144 2145 static int am65_cpsw_nuss_probe(struct platform_device *pdev) 2146 { 2147 struct cpsw_ale_params ale_params = { 0 }; 2148 const struct of_device_id *of_id; 2149 struct device *dev = &pdev->dev; 2150 struct am65_cpsw_common *common; 2151 struct device_node *node; 2152 struct resource *res; 2153 struct clk *clk; 2154 int ret, i; 2155 2156 common = devm_kzalloc(dev, sizeof(struct am65_cpsw_common), GFP_KERNEL); 2157 if (!common) 2158 return -ENOMEM; 2159 common->dev = dev; 2160 2161 of_id = of_match_device(am65_cpsw_nuss_of_mtable, dev); 2162 if (!of_id) 2163 return -EINVAL; 2164 common->pdata = *(const struct am65_cpsw_pdata *)of_id->data; 2165 2166 am65_cpsw_nuss_apply_socinfo(common); 2167 2168 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cpsw_nuss"); 2169 common->ss_base = devm_ioremap_resource(&pdev->dev, res); 2170 if (IS_ERR(common->ss_base)) 2171 return PTR_ERR(common->ss_base); 2172 common->cpsw_base = common->ss_base + AM65_CPSW_CPSW_NU_BASE; 2173 2174 node = of_get_child_by_name(dev->of_node, "ethernet-ports"); 2175 if (!node) 2176 return -ENOENT; 2177 common->port_num = of_get_child_count(node); 2178 if (common->port_num < 1 || common->port_num > AM65_CPSW_MAX_PORTS) 2179 return -ENOENT; 2180 of_node_put(node); 2181 2182 common->rx_flow_id_base = -1; 2183 init_completion(&common->tdown_complete); 2184 common->tx_ch_num = 1; 2185 common->pf_p0_rx_ptype_rrobin = false; 2186 2187 common->ports = devm_kcalloc(dev, common->port_num, 2188 sizeof(*common->ports), 2189 GFP_KERNEL); 2190 if (!common->ports) 2191 return -ENOMEM; 2192 2193 clk = devm_clk_get(dev, "fck"); 2194 if (IS_ERR(clk)) 2195 return dev_err_probe(dev, PTR_ERR(clk), "getting fck clock\n"); 2196 common->bus_freq = clk_get_rate(clk); 2197 2198 pm_runtime_enable(dev); 2199 ret = pm_runtime_get_sync(dev); 2200 if (ret < 0) { 2201 pm_runtime_put_noidle(dev); 2202 pm_runtime_disable(dev); 2203 return ret; 2204 } 2205 2206 node = of_get_child_by_name(dev->of_node, "mdio"); 2207 if (!node) { 2208 dev_warn(dev, "MDIO node not found\n"); 2209 } else if (of_device_is_available(node)) { 2210 struct platform_device *mdio_pdev; 2211 2212 mdio_pdev = of_platform_device_create(node, NULL, dev); 2213 if (!mdio_pdev) { 2214 ret = -ENODEV; 2215 goto err_pm_clear; 2216 } 2217 2218 common->mdio_dev = &mdio_pdev->dev; 2219 } 2220 of_node_put(node); 2221 2222 am65_cpsw_nuss_get_ver(common); 2223 2224 /* init tx channels */ 2225 ret = am65_cpsw_nuss_init_tx_chns(common); 2226 if (ret) 2227 goto err_of_clear; 2228 ret = am65_cpsw_nuss_init_rx_chns(common); 2229 if (ret) 2230 goto err_of_clear; 2231 2232 ret = am65_cpsw_nuss_init_host_p(common); 2233 if (ret) 2234 goto err_of_clear; 2235 2236 ret = am65_cpsw_nuss_init_slave_ports(common); 2237 if (ret) 2238 goto err_of_clear; 2239 2240 /* init common data */ 2241 ale_params.dev = dev; 2242 ale_params.ale_ageout = AM65_CPSW_ALE_AGEOUT_DEFAULT; 2243 ale_params.ale_ports = common->port_num + 1; 2244 ale_params.ale_regs = common->cpsw_base + AM65_CPSW_NU_ALE_BASE; 2245 ale_params.dev_id = common->pdata.ale_dev_id; 2246 ale_params.bus_freq = common->bus_freq; 2247 2248 common->ale = cpsw_ale_create(&ale_params); 2249 if (IS_ERR(common->ale)) { 2250 dev_err(dev, "error initializing ale engine\n"); 2251 ret = PTR_ERR(common->ale); 2252 goto err_of_clear; 2253 } 2254 2255 ret = am65_cpsw_init_cpts(common); 2256 if (ret) 2257 goto err_of_clear; 2258 2259 /* init ports */ 2260 for (i = 0; i < common->port_num; i++) 2261 am65_cpsw_nuss_slave_disable_unused(&common->ports[i]); 2262 2263 dev_set_drvdata(dev, common); 2264 2265 ret = am65_cpsw_nuss_init_ndevs(common); 2266 if (ret) 2267 goto err_of_clear; 2268 2269 ret = am65_cpsw_nuss_register_ndevs(common); 2270 if (ret) 2271 goto err_of_clear; 2272 2273 pm_runtime_put(dev); 2274 return 0; 2275 2276 err_of_clear: 2277 of_platform_device_destroy(common->mdio_dev, NULL); 2278 err_pm_clear: 2279 pm_runtime_put_sync(dev); 2280 pm_runtime_disable(dev); 2281 return ret; 2282 } 2283 2284 static int am65_cpsw_nuss_remove(struct platform_device *pdev) 2285 { 2286 struct device *dev = &pdev->dev; 2287 struct am65_cpsw_common *common; 2288 int ret; 2289 2290 common = dev_get_drvdata(dev); 2291 2292 ret = pm_runtime_get_sync(&pdev->dev); 2293 if (ret < 0) { 2294 pm_runtime_put_noidle(&pdev->dev); 2295 return ret; 2296 } 2297 2298 /* must unregister ndevs here because DD release_driver routine calls 2299 * dma_deconfigure(dev) before devres_release_all(dev) 2300 */ 2301 am65_cpsw_nuss_cleanup_ndev(common); 2302 2303 of_platform_device_destroy(common->mdio_dev, NULL); 2304 2305 pm_runtime_put_sync(&pdev->dev); 2306 pm_runtime_disable(&pdev->dev); 2307 return 0; 2308 } 2309 2310 static struct platform_driver am65_cpsw_nuss_driver = { 2311 .driver = { 2312 .name = AM65_CPSW_DRV_NAME, 2313 .of_match_table = am65_cpsw_nuss_of_mtable, 2314 }, 2315 .probe = am65_cpsw_nuss_probe, 2316 .remove = am65_cpsw_nuss_remove, 2317 }; 2318 2319 module_platform_driver(am65_cpsw_nuss_driver); 2320 2321 MODULE_LICENSE("GPL v2"); 2322 MODULE_AUTHOR("Grygorii Strashko <grygorii.strashko@ti.com>"); 2323 MODULE_DESCRIPTION("TI AM65 CPSW Ethernet driver"); 2324