1 // SPDX-License-Identifier: GPL-2.0 2 /* Texas Instruments K3 AM65 Ethernet Switch SubSystem Driver 3 * 4 * Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/ 5 * 6 */ 7 8 #include <linux/clk.h> 9 #include <linux/etherdevice.h> 10 #include <linux/if_vlan.h> 11 #include <linux/interrupt.h> 12 #include <linux/irqdomain.h> 13 #include <linux/kernel.h> 14 #include <linux/kmemleak.h> 15 #include <linux/module.h> 16 #include <linux/netdevice.h> 17 #include <linux/net_tstamp.h> 18 #include <linux/of.h> 19 #include <linux/of_mdio.h> 20 #include <linux/of_net.h> 21 #include <linux/of_device.h> 22 #include <linux/phylink.h> 23 #include <linux/phy/phy.h> 24 #include <linux/platform_device.h> 25 #include <linux/pm_runtime.h> 26 #include <linux/regmap.h> 27 #include <linux/rtnetlink.h> 28 #include <linux/mfd/syscon.h> 29 #include <linux/sys_soc.h> 30 #include <linux/dma/ti-cppi5.h> 31 #include <linux/dma/k3-udma-glue.h> 32 #include <net/switchdev.h> 33 34 #include "cpsw_ale.h" 35 #include "cpsw_sl.h" 36 #include "am65-cpsw-nuss.h" 37 #include "am65-cpsw-switchdev.h" 38 #include "k3-cppi-desc-pool.h" 39 #include "am65-cpts.h" 40 41 #define AM65_CPSW_SS_BASE 0x0 42 #define AM65_CPSW_SGMII_BASE 0x100 43 #define AM65_CPSW_XGMII_BASE 0x2100 44 #define AM65_CPSW_CPSW_NU_BASE 0x20000 45 #define AM65_CPSW_NU_PORTS_BASE 0x1000 46 #define AM65_CPSW_NU_FRAM_BASE 0x12000 47 #define AM65_CPSW_NU_STATS_BASE 0x1a000 48 #define AM65_CPSW_NU_ALE_BASE 0x1e000 49 #define AM65_CPSW_NU_CPTS_BASE 0x1d000 50 51 #define AM65_CPSW_NU_PORTS_OFFSET 0x1000 52 #define AM65_CPSW_NU_STATS_PORT_OFFSET 0x200 53 #define AM65_CPSW_NU_FRAM_PORT_OFFSET 0x200 54 55 #define AM65_CPSW_MAX_PORTS 8 56 57 #define AM65_CPSW_MIN_PACKET_SIZE VLAN_ETH_ZLEN 58 #define AM65_CPSW_MAX_PACKET_SIZE (VLAN_ETH_FRAME_LEN + ETH_FCS_LEN) 59 60 #define AM65_CPSW_REG_CTL 0x004 61 #define AM65_CPSW_REG_STAT_PORT_EN 0x014 62 #define AM65_CPSW_REG_PTYPE 0x018 63 64 #define AM65_CPSW_P0_REG_CTL 0x004 65 #define AM65_CPSW_PORT0_REG_FLOW_ID_OFFSET 0x008 66 67 #define AM65_CPSW_PORT_REG_PRI_CTL 0x01c 68 #define AM65_CPSW_PORT_REG_RX_PRI_MAP 0x020 69 #define AM65_CPSW_PORT_REG_RX_MAXLEN 0x024 70 71 #define AM65_CPSW_PORTN_REG_SA_L 0x308 72 #define AM65_CPSW_PORTN_REG_SA_H 0x30c 73 #define AM65_CPSW_PORTN_REG_TS_CTL 0x310 74 #define AM65_CPSW_PORTN_REG_TS_SEQ_LTYPE_REG 0x314 75 #define AM65_CPSW_PORTN_REG_TS_VLAN_LTYPE_REG 0x318 76 #define AM65_CPSW_PORTN_REG_TS_CTL_LTYPE2 0x31C 77 78 #define AM65_CPSW_SGMII_CONTROL_REG 0x010 79 #define AM65_CPSW_SGMII_CONTROL_MR_AN_ENABLE BIT(0) 80 81 #define AM65_CPSW_CTL_VLAN_AWARE BIT(1) 82 #define AM65_CPSW_CTL_P0_ENABLE BIT(2) 83 #define AM65_CPSW_CTL_P0_TX_CRC_REMOVE BIT(13) 84 #define AM65_CPSW_CTL_P0_RX_PAD BIT(14) 85 86 /* AM65_CPSW_P0_REG_CTL */ 87 #define AM65_CPSW_P0_REG_CTL_RX_CHECKSUM_EN BIT(0) 88 89 /* AM65_CPSW_PORT_REG_PRI_CTL */ 90 #define AM65_CPSW_PORT_REG_PRI_CTL_RX_PTYPE_RROBIN BIT(8) 91 92 /* AM65_CPSW_PN_TS_CTL register fields */ 93 #define AM65_CPSW_PN_TS_CTL_TX_ANX_F_EN BIT(4) 94 #define AM65_CPSW_PN_TS_CTL_TX_VLAN_LT1_EN BIT(5) 95 #define AM65_CPSW_PN_TS_CTL_TX_VLAN_LT2_EN BIT(6) 96 #define AM65_CPSW_PN_TS_CTL_TX_ANX_D_EN BIT(7) 97 #define AM65_CPSW_PN_TS_CTL_TX_ANX_E_EN BIT(10) 98 #define AM65_CPSW_PN_TS_CTL_TX_HOST_TS_EN BIT(11) 99 #define AM65_CPSW_PN_TS_CTL_MSG_TYPE_EN_SHIFT 16 100 101 /* AM65_CPSW_PORTN_REG_TS_SEQ_LTYPE_REG register fields */ 102 #define AM65_CPSW_PN_TS_SEQ_ID_OFFSET_SHIFT 16 103 104 /* AM65_CPSW_PORTN_REG_TS_CTL_LTYPE2 */ 105 #define AM65_CPSW_PN_TS_CTL_LTYPE2_TS_107 BIT(16) 106 #define AM65_CPSW_PN_TS_CTL_LTYPE2_TS_129 BIT(17) 107 #define AM65_CPSW_PN_TS_CTL_LTYPE2_TS_130 BIT(18) 108 #define AM65_CPSW_PN_TS_CTL_LTYPE2_TS_131 BIT(19) 109 #define AM65_CPSW_PN_TS_CTL_LTYPE2_TS_132 BIT(20) 110 #define AM65_CPSW_PN_TS_CTL_LTYPE2_TS_319 BIT(21) 111 #define AM65_CPSW_PN_TS_CTL_LTYPE2_TS_320 BIT(22) 112 #define AM65_CPSW_PN_TS_CTL_LTYPE2_TS_TTL_NONZERO BIT(23) 113 114 /* The PTP event messages - Sync, Delay_Req, Pdelay_Req, and Pdelay_Resp. */ 115 #define AM65_CPSW_TS_EVENT_MSG_TYPE_BITS (BIT(0) | BIT(1) | BIT(2) | BIT(3)) 116 117 #define AM65_CPSW_TS_SEQ_ID_OFFSET (0x1e) 118 119 #define AM65_CPSW_TS_TX_ANX_ALL_EN \ 120 (AM65_CPSW_PN_TS_CTL_TX_ANX_D_EN | \ 121 AM65_CPSW_PN_TS_CTL_TX_ANX_E_EN | \ 122 AM65_CPSW_PN_TS_CTL_TX_ANX_F_EN) 123 124 #define AM65_CPSW_ALE_AGEOUT_DEFAULT 30 125 /* Number of TX/RX descriptors */ 126 #define AM65_CPSW_MAX_TX_DESC 500 127 #define AM65_CPSW_MAX_RX_DESC 500 128 129 #define AM65_CPSW_NAV_PS_DATA_SIZE 16 130 #define AM65_CPSW_NAV_SW_DATA_SIZE 16 131 132 #define AM65_CPSW_DEBUG (NETIF_MSG_HW | NETIF_MSG_DRV | NETIF_MSG_LINK | \ 133 NETIF_MSG_IFUP | NETIF_MSG_PROBE | NETIF_MSG_IFDOWN | \ 134 NETIF_MSG_RX_ERR | NETIF_MSG_TX_ERR) 135 136 static void am65_cpsw_port_set_sl_mac(struct am65_cpsw_port *slave, 137 const u8 *dev_addr) 138 { 139 u32 mac_hi = (dev_addr[0] << 0) | (dev_addr[1] << 8) | 140 (dev_addr[2] << 16) | (dev_addr[3] << 24); 141 u32 mac_lo = (dev_addr[4] << 0) | (dev_addr[5] << 8); 142 143 writel(mac_hi, slave->port_base + AM65_CPSW_PORTN_REG_SA_H); 144 writel(mac_lo, slave->port_base + AM65_CPSW_PORTN_REG_SA_L); 145 } 146 147 static void am65_cpsw_sl_ctl_reset(struct am65_cpsw_port *port) 148 { 149 cpsw_sl_reset(port->slave.mac_sl, 100); 150 /* Max length register has to be restored after MAC SL reset */ 151 writel(AM65_CPSW_MAX_PACKET_SIZE, 152 port->port_base + AM65_CPSW_PORT_REG_RX_MAXLEN); 153 } 154 155 static void am65_cpsw_nuss_get_ver(struct am65_cpsw_common *common) 156 { 157 common->nuss_ver = readl(common->ss_base); 158 common->cpsw_ver = readl(common->cpsw_base); 159 dev_info(common->dev, 160 "initializing am65 cpsw nuss version 0x%08X, cpsw version 0x%08X Ports: %u quirks:%08x\n", 161 common->nuss_ver, 162 common->cpsw_ver, 163 common->port_num + 1, 164 common->pdata.quirks); 165 } 166 167 static int am65_cpsw_nuss_ndo_slave_add_vid(struct net_device *ndev, 168 __be16 proto, u16 vid) 169 { 170 struct am65_cpsw_common *common = am65_ndev_to_common(ndev); 171 struct am65_cpsw_port *port = am65_ndev_to_port(ndev); 172 u32 port_mask, unreg_mcast = 0; 173 int ret; 174 175 if (!common->is_emac_mode) 176 return 0; 177 178 if (!netif_running(ndev) || !vid) 179 return 0; 180 181 ret = pm_runtime_resume_and_get(common->dev); 182 if (ret < 0) 183 return ret; 184 185 port_mask = BIT(port->port_id) | ALE_PORT_HOST; 186 if (!vid) 187 unreg_mcast = port_mask; 188 dev_info(common->dev, "Adding vlan %d to vlan filter\n", vid); 189 ret = cpsw_ale_vlan_add_modify(common->ale, vid, port_mask, 190 unreg_mcast, port_mask, 0); 191 192 pm_runtime_put(common->dev); 193 return ret; 194 } 195 196 static int am65_cpsw_nuss_ndo_slave_kill_vid(struct net_device *ndev, 197 __be16 proto, u16 vid) 198 { 199 struct am65_cpsw_common *common = am65_ndev_to_common(ndev); 200 struct am65_cpsw_port *port = am65_ndev_to_port(ndev); 201 int ret; 202 203 if (!common->is_emac_mode) 204 return 0; 205 206 if (!netif_running(ndev) || !vid) 207 return 0; 208 209 ret = pm_runtime_resume_and_get(common->dev); 210 if (ret < 0) 211 return ret; 212 213 dev_info(common->dev, "Removing vlan %d from vlan filter\n", vid); 214 ret = cpsw_ale_del_vlan(common->ale, vid, 215 BIT(port->port_id) | ALE_PORT_HOST); 216 217 pm_runtime_put(common->dev); 218 return ret; 219 } 220 221 static void am65_cpsw_slave_set_promisc(struct am65_cpsw_port *port, 222 bool promisc) 223 { 224 struct am65_cpsw_common *common = port->common; 225 226 if (promisc && !common->is_emac_mode) { 227 dev_dbg(common->dev, "promisc mode requested in switch mode"); 228 return; 229 } 230 231 if (promisc) { 232 /* Enable promiscuous mode */ 233 cpsw_ale_control_set(common->ale, port->port_id, 234 ALE_PORT_MACONLY_CAF, 1); 235 dev_dbg(common->dev, "promisc enabled\n"); 236 } else { 237 /* Disable promiscuous mode */ 238 cpsw_ale_control_set(common->ale, port->port_id, 239 ALE_PORT_MACONLY_CAF, 0); 240 dev_dbg(common->dev, "promisc disabled\n"); 241 } 242 } 243 244 static void am65_cpsw_nuss_ndo_slave_set_rx_mode(struct net_device *ndev) 245 { 246 struct am65_cpsw_common *common = am65_ndev_to_common(ndev); 247 struct am65_cpsw_port *port = am65_ndev_to_port(ndev); 248 u32 port_mask; 249 bool promisc; 250 251 promisc = !!(ndev->flags & IFF_PROMISC); 252 am65_cpsw_slave_set_promisc(port, promisc); 253 254 if (promisc) 255 return; 256 257 /* Restore allmulti on vlans if necessary */ 258 cpsw_ale_set_allmulti(common->ale, 259 ndev->flags & IFF_ALLMULTI, port->port_id); 260 261 port_mask = ALE_PORT_HOST; 262 /* Clear all mcast from ALE */ 263 cpsw_ale_flush_multicast(common->ale, port_mask, -1); 264 265 if (!netdev_mc_empty(ndev)) { 266 struct netdev_hw_addr *ha; 267 268 /* program multicast address list into ALE register */ 269 netdev_for_each_mc_addr(ha, ndev) { 270 cpsw_ale_add_mcast(common->ale, ha->addr, 271 port_mask, 0, 0, 0); 272 } 273 } 274 } 275 276 static void am65_cpsw_nuss_ndo_host_tx_timeout(struct net_device *ndev, 277 unsigned int txqueue) 278 { 279 struct am65_cpsw_common *common = am65_ndev_to_common(ndev); 280 struct am65_cpsw_tx_chn *tx_chn; 281 struct netdev_queue *netif_txq; 282 unsigned long trans_start; 283 284 netif_txq = netdev_get_tx_queue(ndev, txqueue); 285 tx_chn = &common->tx_chns[txqueue]; 286 trans_start = READ_ONCE(netif_txq->trans_start); 287 288 netdev_err(ndev, "txq:%d DRV_XOFF:%d tmo:%u dql_avail:%d free_desc:%zu\n", 289 txqueue, 290 netif_tx_queue_stopped(netif_txq), 291 jiffies_to_msecs(jiffies - trans_start), 292 dql_avail(&netif_txq->dql), 293 k3_cppi_desc_pool_avail(tx_chn->desc_pool)); 294 295 if (netif_tx_queue_stopped(netif_txq)) { 296 /* try recover if stopped by us */ 297 txq_trans_update(netif_txq); 298 netif_tx_wake_queue(netif_txq); 299 } 300 } 301 302 static int am65_cpsw_nuss_rx_push(struct am65_cpsw_common *common, 303 struct sk_buff *skb) 304 { 305 struct am65_cpsw_rx_chn *rx_chn = &common->rx_chns; 306 struct cppi5_host_desc_t *desc_rx; 307 struct device *dev = common->dev; 308 u32 pkt_len = skb_tailroom(skb); 309 dma_addr_t desc_dma; 310 dma_addr_t buf_dma; 311 void *swdata; 312 313 desc_rx = k3_cppi_desc_pool_alloc(rx_chn->desc_pool); 314 if (!desc_rx) { 315 dev_err(dev, "Failed to allocate RXFDQ descriptor\n"); 316 return -ENOMEM; 317 } 318 desc_dma = k3_cppi_desc_pool_virt2dma(rx_chn->desc_pool, desc_rx); 319 320 buf_dma = dma_map_single(rx_chn->dma_dev, skb->data, pkt_len, 321 DMA_FROM_DEVICE); 322 if (unlikely(dma_mapping_error(rx_chn->dma_dev, buf_dma))) { 323 k3_cppi_desc_pool_free(rx_chn->desc_pool, desc_rx); 324 dev_err(dev, "Failed to map rx skb buffer\n"); 325 return -EINVAL; 326 } 327 328 cppi5_hdesc_init(desc_rx, CPPI5_INFO0_HDESC_EPIB_PRESENT, 329 AM65_CPSW_NAV_PS_DATA_SIZE); 330 k3_udma_glue_rx_dma_to_cppi5_addr(rx_chn->rx_chn, &buf_dma); 331 cppi5_hdesc_attach_buf(desc_rx, buf_dma, skb_tailroom(skb), buf_dma, skb_tailroom(skb)); 332 swdata = cppi5_hdesc_get_swdata(desc_rx); 333 *((void **)swdata) = skb; 334 335 return k3_udma_glue_push_rx_chn(rx_chn->rx_chn, 0, desc_rx, desc_dma); 336 } 337 338 void am65_cpsw_nuss_set_p0_ptype(struct am65_cpsw_common *common) 339 { 340 struct am65_cpsw_host *host_p = am65_common_get_host(common); 341 u32 val, pri_map; 342 343 /* P0 set Receive Priority Type */ 344 val = readl(host_p->port_base + AM65_CPSW_PORT_REG_PRI_CTL); 345 346 if (common->pf_p0_rx_ptype_rrobin) { 347 val |= AM65_CPSW_PORT_REG_PRI_CTL_RX_PTYPE_RROBIN; 348 /* Enet Ports fifos works in fixed priority mode only, so 349 * reset P0_Rx_Pri_Map so all packet will go in Enet fifo 0 350 */ 351 pri_map = 0x0; 352 } else { 353 val &= ~AM65_CPSW_PORT_REG_PRI_CTL_RX_PTYPE_RROBIN; 354 /* restore P0_Rx_Pri_Map */ 355 pri_map = 0x76543210; 356 } 357 358 writel(pri_map, host_p->port_base + AM65_CPSW_PORT_REG_RX_PRI_MAP); 359 writel(val, host_p->port_base + AM65_CPSW_PORT_REG_PRI_CTL); 360 } 361 362 static void am65_cpsw_init_host_port_switch(struct am65_cpsw_common *common); 363 static void am65_cpsw_init_host_port_emac(struct am65_cpsw_common *common); 364 static void am65_cpsw_init_port_switch_ale(struct am65_cpsw_port *port); 365 static void am65_cpsw_init_port_emac_ale(struct am65_cpsw_port *port); 366 367 static int am65_cpsw_nuss_common_open(struct am65_cpsw_common *common) 368 { 369 struct am65_cpsw_host *host_p = am65_common_get_host(common); 370 int port_idx, i, ret; 371 struct sk_buff *skb; 372 u32 val, port_mask; 373 374 if (common->usage_count) 375 return 0; 376 377 /* Control register */ 378 writel(AM65_CPSW_CTL_P0_ENABLE | AM65_CPSW_CTL_P0_TX_CRC_REMOVE | 379 AM65_CPSW_CTL_VLAN_AWARE | AM65_CPSW_CTL_P0_RX_PAD, 380 common->cpsw_base + AM65_CPSW_REG_CTL); 381 /* Max length register */ 382 writel(AM65_CPSW_MAX_PACKET_SIZE, 383 host_p->port_base + AM65_CPSW_PORT_REG_RX_MAXLEN); 384 /* set base flow_id */ 385 writel(common->rx_flow_id_base, 386 host_p->port_base + AM65_CPSW_PORT0_REG_FLOW_ID_OFFSET); 387 /* en tx crc offload */ 388 writel(AM65_CPSW_P0_REG_CTL_RX_CHECKSUM_EN, host_p->port_base + AM65_CPSW_P0_REG_CTL); 389 390 am65_cpsw_nuss_set_p0_ptype(common); 391 392 /* enable statistic */ 393 val = BIT(HOST_PORT_NUM); 394 for (port_idx = 0; port_idx < common->port_num; port_idx++) { 395 struct am65_cpsw_port *port = &common->ports[port_idx]; 396 397 if (!port->disabled) 398 val |= BIT(port->port_id); 399 } 400 writel(val, common->cpsw_base + AM65_CPSW_REG_STAT_PORT_EN); 401 402 /* disable priority elevation */ 403 writel(0, common->cpsw_base + AM65_CPSW_REG_PTYPE); 404 405 cpsw_ale_start(common->ale); 406 407 /* limit to one RX flow only */ 408 cpsw_ale_control_set(common->ale, HOST_PORT_NUM, 409 ALE_DEFAULT_THREAD_ID, 0); 410 cpsw_ale_control_set(common->ale, HOST_PORT_NUM, 411 ALE_DEFAULT_THREAD_ENABLE, 1); 412 /* switch to vlan unaware mode */ 413 cpsw_ale_control_set(common->ale, HOST_PORT_NUM, ALE_VLAN_AWARE, 1); 414 cpsw_ale_control_set(common->ale, HOST_PORT_NUM, 415 ALE_PORT_STATE, ALE_PORT_STATE_FORWARD); 416 417 /* default vlan cfg: create mask based on enabled ports */ 418 port_mask = GENMASK(common->port_num, 0) & 419 ~common->disabled_ports_mask; 420 421 cpsw_ale_add_vlan(common->ale, 0, port_mask, 422 port_mask, port_mask, 423 port_mask & ~ALE_PORT_HOST); 424 425 if (common->is_emac_mode) 426 am65_cpsw_init_host_port_emac(common); 427 else 428 am65_cpsw_init_host_port_switch(common); 429 430 for (i = 0; i < common->rx_chns.descs_num; i++) { 431 skb = __netdev_alloc_skb_ip_align(NULL, 432 AM65_CPSW_MAX_PACKET_SIZE, 433 GFP_KERNEL); 434 if (!skb) { 435 dev_err(common->dev, "cannot allocate skb\n"); 436 return -ENOMEM; 437 } 438 439 ret = am65_cpsw_nuss_rx_push(common, skb); 440 if (ret < 0) { 441 dev_err(common->dev, 442 "cannot submit skb to channel rx, error %d\n", 443 ret); 444 kfree_skb(skb); 445 return ret; 446 } 447 kmemleak_not_leak(skb); 448 } 449 k3_udma_glue_enable_rx_chn(common->rx_chns.rx_chn); 450 451 for (i = 0; i < common->tx_ch_num; i++) { 452 ret = k3_udma_glue_enable_tx_chn(common->tx_chns[i].tx_chn); 453 if (ret) 454 return ret; 455 napi_enable(&common->tx_chns[i].napi_tx); 456 } 457 458 napi_enable(&common->napi_rx); 459 if (common->rx_irq_disabled) { 460 common->rx_irq_disabled = false; 461 enable_irq(common->rx_chns.irq); 462 } 463 464 dev_dbg(common->dev, "cpsw_nuss started\n"); 465 return 0; 466 } 467 468 static void am65_cpsw_nuss_tx_cleanup(void *data, dma_addr_t desc_dma); 469 static void am65_cpsw_nuss_rx_cleanup(void *data, dma_addr_t desc_dma); 470 471 static int am65_cpsw_nuss_common_stop(struct am65_cpsw_common *common) 472 { 473 int i; 474 475 if (common->usage_count != 1) 476 return 0; 477 478 cpsw_ale_control_set(common->ale, HOST_PORT_NUM, 479 ALE_PORT_STATE, ALE_PORT_STATE_DISABLE); 480 481 /* shutdown tx channels */ 482 atomic_set(&common->tdown_cnt, common->tx_ch_num); 483 /* ensure new tdown_cnt value is visible */ 484 smp_mb__after_atomic(); 485 reinit_completion(&common->tdown_complete); 486 487 for (i = 0; i < common->tx_ch_num; i++) 488 k3_udma_glue_tdown_tx_chn(common->tx_chns[i].tx_chn, false); 489 490 i = wait_for_completion_timeout(&common->tdown_complete, 491 msecs_to_jiffies(1000)); 492 if (!i) 493 dev_err(common->dev, "tx timeout\n"); 494 for (i = 0; i < common->tx_ch_num; i++) 495 napi_disable(&common->tx_chns[i].napi_tx); 496 497 for (i = 0; i < common->tx_ch_num; i++) { 498 k3_udma_glue_reset_tx_chn(common->tx_chns[i].tx_chn, 499 &common->tx_chns[i], 500 am65_cpsw_nuss_tx_cleanup); 501 k3_udma_glue_disable_tx_chn(common->tx_chns[i].tx_chn); 502 } 503 504 reinit_completion(&common->tdown_complete); 505 k3_udma_glue_tdown_rx_chn(common->rx_chns.rx_chn, true); 506 507 if (common->pdata.quirks & AM64_CPSW_QUIRK_DMA_RX_TDOWN_IRQ) { 508 i = wait_for_completion_timeout(&common->tdown_complete, msecs_to_jiffies(1000)); 509 if (!i) 510 dev_err(common->dev, "rx teardown timeout\n"); 511 } 512 513 napi_disable(&common->napi_rx); 514 515 for (i = 0; i < AM65_CPSW_MAX_RX_FLOWS; i++) 516 k3_udma_glue_reset_rx_chn(common->rx_chns.rx_chn, i, 517 &common->rx_chns, 518 am65_cpsw_nuss_rx_cleanup, !!i); 519 520 k3_udma_glue_disable_rx_chn(common->rx_chns.rx_chn); 521 522 cpsw_ale_stop(common->ale); 523 524 writel(0, common->cpsw_base + AM65_CPSW_REG_CTL); 525 writel(0, common->cpsw_base + AM65_CPSW_REG_STAT_PORT_EN); 526 527 dev_dbg(common->dev, "cpsw_nuss stopped\n"); 528 return 0; 529 } 530 531 static int am65_cpsw_nuss_ndo_slave_stop(struct net_device *ndev) 532 { 533 struct am65_cpsw_common *common = am65_ndev_to_common(ndev); 534 struct am65_cpsw_port *port = am65_ndev_to_port(ndev); 535 int ret; 536 537 phylink_stop(port->slave.phylink); 538 539 netif_tx_stop_all_queues(ndev); 540 541 phylink_disconnect_phy(port->slave.phylink); 542 543 ret = am65_cpsw_nuss_common_stop(common); 544 if (ret) 545 return ret; 546 547 common->usage_count--; 548 pm_runtime_put(common->dev); 549 return 0; 550 } 551 552 static int cpsw_restore_vlans(struct net_device *vdev, int vid, void *arg) 553 { 554 struct am65_cpsw_port *port = arg; 555 556 if (!vdev) 557 return 0; 558 559 return am65_cpsw_nuss_ndo_slave_add_vid(port->ndev, 0, vid); 560 } 561 562 static int am65_cpsw_nuss_ndo_slave_open(struct net_device *ndev) 563 { 564 struct am65_cpsw_common *common = am65_ndev_to_common(ndev); 565 struct am65_cpsw_port *port = am65_ndev_to_port(ndev); 566 int ret, i; 567 u32 reg; 568 569 ret = pm_runtime_resume_and_get(common->dev); 570 if (ret < 0) 571 return ret; 572 573 /* Idle MAC port */ 574 cpsw_sl_ctl_set(port->slave.mac_sl, CPSW_SL_CTL_CMD_IDLE); 575 cpsw_sl_wait_for_idle(port->slave.mac_sl, 100); 576 cpsw_sl_ctl_reset(port->slave.mac_sl); 577 578 /* soft reset MAC */ 579 cpsw_sl_reg_write(port->slave.mac_sl, CPSW_SL_SOFT_RESET, 1); 580 mdelay(1); 581 reg = cpsw_sl_reg_read(port->slave.mac_sl, CPSW_SL_SOFT_RESET); 582 if (reg) { 583 dev_err(common->dev, "soft RESET didn't complete\n"); 584 ret = -ETIMEDOUT; 585 goto runtime_put; 586 } 587 588 /* Notify the stack of the actual queue counts. */ 589 ret = netif_set_real_num_tx_queues(ndev, common->tx_ch_num); 590 if (ret) { 591 dev_err(common->dev, "cannot set real number of tx queues\n"); 592 goto runtime_put; 593 } 594 595 ret = netif_set_real_num_rx_queues(ndev, AM65_CPSW_MAX_RX_QUEUES); 596 if (ret) { 597 dev_err(common->dev, "cannot set real number of rx queues\n"); 598 goto runtime_put; 599 } 600 601 for (i = 0; i < common->tx_ch_num; i++) 602 netdev_tx_reset_queue(netdev_get_tx_queue(ndev, i)); 603 604 ret = am65_cpsw_nuss_common_open(common); 605 if (ret) 606 goto runtime_put; 607 608 common->usage_count++; 609 610 am65_cpsw_port_set_sl_mac(port, ndev->dev_addr); 611 612 if (common->is_emac_mode) 613 am65_cpsw_init_port_emac_ale(port); 614 else 615 am65_cpsw_init_port_switch_ale(port); 616 617 /* mac_sl should be configured via phy-link interface */ 618 am65_cpsw_sl_ctl_reset(port); 619 620 ret = phylink_of_phy_connect(port->slave.phylink, port->slave.phy_node, 0); 621 if (ret) 622 goto error_cleanup; 623 624 /* restore vlan configurations */ 625 vlan_for_each(ndev, cpsw_restore_vlans, port); 626 627 phylink_start(port->slave.phylink); 628 629 return 0; 630 631 error_cleanup: 632 am65_cpsw_nuss_ndo_slave_stop(ndev); 633 return ret; 634 635 runtime_put: 636 pm_runtime_put(common->dev); 637 return ret; 638 } 639 640 static void am65_cpsw_nuss_rx_cleanup(void *data, dma_addr_t desc_dma) 641 { 642 struct am65_cpsw_rx_chn *rx_chn = data; 643 struct cppi5_host_desc_t *desc_rx; 644 struct sk_buff *skb; 645 dma_addr_t buf_dma; 646 u32 buf_dma_len; 647 void **swdata; 648 649 desc_rx = k3_cppi_desc_pool_dma2virt(rx_chn->desc_pool, desc_dma); 650 swdata = cppi5_hdesc_get_swdata(desc_rx); 651 skb = *swdata; 652 cppi5_hdesc_get_obuf(desc_rx, &buf_dma, &buf_dma_len); 653 k3_udma_glue_rx_cppi5_to_dma_addr(rx_chn->rx_chn, &buf_dma); 654 655 dma_unmap_single(rx_chn->dma_dev, buf_dma, buf_dma_len, DMA_FROM_DEVICE); 656 k3_cppi_desc_pool_free(rx_chn->desc_pool, desc_rx); 657 658 dev_kfree_skb_any(skb); 659 } 660 661 static void am65_cpsw_nuss_rx_ts(struct sk_buff *skb, u32 *psdata) 662 { 663 struct skb_shared_hwtstamps *ssh; 664 u64 ns; 665 666 ns = ((u64)psdata[1] << 32) | psdata[0]; 667 668 ssh = skb_hwtstamps(skb); 669 memset(ssh, 0, sizeof(*ssh)); 670 ssh->hwtstamp = ns_to_ktime(ns); 671 } 672 673 /* RX psdata[2] word format - checksum information */ 674 #define AM65_CPSW_RX_PSD_CSUM_ADD GENMASK(15, 0) 675 #define AM65_CPSW_RX_PSD_CSUM_ERR BIT(16) 676 #define AM65_CPSW_RX_PSD_IS_FRAGMENT BIT(17) 677 #define AM65_CPSW_RX_PSD_IS_TCP BIT(18) 678 #define AM65_CPSW_RX_PSD_IPV6_VALID BIT(19) 679 #define AM65_CPSW_RX_PSD_IPV4_VALID BIT(20) 680 681 static void am65_cpsw_nuss_rx_csum(struct sk_buff *skb, u32 csum_info) 682 { 683 /* HW can verify IPv4/IPv6 TCP/UDP packets checksum 684 * csum information provides in psdata[2] word: 685 * AM65_CPSW_RX_PSD_CSUM_ERR bit - indicates csum error 686 * AM65_CPSW_RX_PSD_IPV6_VALID and AM65_CPSW_RX_PSD_IPV4_VALID 687 * bits - indicates IPv4/IPv6 packet 688 * AM65_CPSW_RX_PSD_IS_FRAGMENT bit - indicates fragmented packet 689 * AM65_CPSW_RX_PSD_CSUM_ADD has value 0xFFFF for non fragmented packets 690 * or csum value for fragmented packets if !AM65_CPSW_RX_PSD_CSUM_ERR 691 */ 692 skb_checksum_none_assert(skb); 693 694 if (unlikely(!(skb->dev->features & NETIF_F_RXCSUM))) 695 return; 696 697 if ((csum_info & (AM65_CPSW_RX_PSD_IPV6_VALID | 698 AM65_CPSW_RX_PSD_IPV4_VALID)) && 699 !(csum_info & AM65_CPSW_RX_PSD_CSUM_ERR)) { 700 /* csum for fragmented packets is unsupported */ 701 if (!(csum_info & AM65_CPSW_RX_PSD_IS_FRAGMENT)) 702 skb->ip_summed = CHECKSUM_UNNECESSARY; 703 } 704 } 705 706 static int am65_cpsw_nuss_rx_packets(struct am65_cpsw_common *common, 707 u32 flow_idx) 708 { 709 struct am65_cpsw_rx_chn *rx_chn = &common->rx_chns; 710 u32 buf_dma_len, pkt_len, port_id = 0, csum_info; 711 struct am65_cpsw_ndev_priv *ndev_priv; 712 struct am65_cpsw_ndev_stats *stats; 713 struct cppi5_host_desc_t *desc_rx; 714 struct device *dev = common->dev; 715 struct sk_buff *skb, *new_skb; 716 dma_addr_t desc_dma, buf_dma; 717 struct am65_cpsw_port *port; 718 struct net_device *ndev; 719 void **swdata; 720 u32 *psdata; 721 int ret = 0; 722 723 ret = k3_udma_glue_pop_rx_chn(rx_chn->rx_chn, flow_idx, &desc_dma); 724 if (ret) { 725 if (ret != -ENODATA) 726 dev_err(dev, "RX: pop chn fail %d\n", ret); 727 return ret; 728 } 729 730 if (cppi5_desc_is_tdcm(desc_dma)) { 731 dev_dbg(dev, "%s RX tdown flow: %u\n", __func__, flow_idx); 732 if (common->pdata.quirks & AM64_CPSW_QUIRK_DMA_RX_TDOWN_IRQ) 733 complete(&common->tdown_complete); 734 return 0; 735 } 736 737 desc_rx = k3_cppi_desc_pool_dma2virt(rx_chn->desc_pool, desc_dma); 738 dev_dbg(dev, "%s flow_idx: %u desc %pad\n", 739 __func__, flow_idx, &desc_dma); 740 741 swdata = cppi5_hdesc_get_swdata(desc_rx); 742 skb = *swdata; 743 cppi5_hdesc_get_obuf(desc_rx, &buf_dma, &buf_dma_len); 744 k3_udma_glue_rx_cppi5_to_dma_addr(rx_chn->rx_chn, &buf_dma); 745 pkt_len = cppi5_hdesc_get_pktlen(desc_rx); 746 cppi5_desc_get_tags_ids(&desc_rx->hdr, &port_id, NULL); 747 dev_dbg(dev, "%s rx port_id:%d\n", __func__, port_id); 748 port = am65_common_get_port(common, port_id); 749 ndev = port->ndev; 750 skb->dev = ndev; 751 752 psdata = cppi5_hdesc_get_psdata(desc_rx); 753 /* add RX timestamp */ 754 if (port->rx_ts_enabled) 755 am65_cpsw_nuss_rx_ts(skb, psdata); 756 csum_info = psdata[2]; 757 dev_dbg(dev, "%s rx csum_info:%#x\n", __func__, csum_info); 758 759 dma_unmap_single(rx_chn->dma_dev, buf_dma, buf_dma_len, DMA_FROM_DEVICE); 760 761 k3_cppi_desc_pool_free(rx_chn->desc_pool, desc_rx); 762 763 new_skb = netdev_alloc_skb_ip_align(ndev, AM65_CPSW_MAX_PACKET_SIZE); 764 if (new_skb) { 765 ndev_priv = netdev_priv(ndev); 766 am65_cpsw_nuss_set_offload_fwd_mark(skb, ndev_priv->offload_fwd_mark); 767 skb_put(skb, pkt_len); 768 skb->protocol = eth_type_trans(skb, ndev); 769 am65_cpsw_nuss_rx_csum(skb, csum_info); 770 napi_gro_receive(&common->napi_rx, skb); 771 772 stats = this_cpu_ptr(ndev_priv->stats); 773 774 u64_stats_update_begin(&stats->syncp); 775 stats->rx_packets++; 776 stats->rx_bytes += pkt_len; 777 u64_stats_update_end(&stats->syncp); 778 kmemleak_not_leak(new_skb); 779 } else { 780 ndev->stats.rx_dropped++; 781 new_skb = skb; 782 } 783 784 if (netif_dormant(ndev)) { 785 dev_kfree_skb_any(new_skb); 786 ndev->stats.rx_dropped++; 787 return 0; 788 } 789 790 ret = am65_cpsw_nuss_rx_push(common, new_skb); 791 if (WARN_ON(ret < 0)) { 792 dev_kfree_skb_any(new_skb); 793 ndev->stats.rx_errors++; 794 ndev->stats.rx_dropped++; 795 } 796 797 return ret; 798 } 799 800 static int am65_cpsw_nuss_rx_poll(struct napi_struct *napi_rx, int budget) 801 { 802 struct am65_cpsw_common *common = am65_cpsw_napi_to_common(napi_rx); 803 int flow = AM65_CPSW_MAX_RX_FLOWS; 804 int cur_budget, ret; 805 int num_rx = 0; 806 807 /* process every flow */ 808 while (flow--) { 809 cur_budget = budget - num_rx; 810 811 while (cur_budget--) { 812 ret = am65_cpsw_nuss_rx_packets(common, flow); 813 if (ret) 814 break; 815 num_rx++; 816 } 817 818 if (num_rx >= budget) 819 break; 820 } 821 822 dev_dbg(common->dev, "%s num_rx:%d %d\n", __func__, num_rx, budget); 823 824 if (num_rx < budget && napi_complete_done(napi_rx, num_rx)) { 825 if (common->rx_irq_disabled) { 826 common->rx_irq_disabled = false; 827 enable_irq(common->rx_chns.irq); 828 } 829 } 830 831 return num_rx; 832 } 833 834 static void am65_cpsw_nuss_xmit_free(struct am65_cpsw_tx_chn *tx_chn, 835 struct cppi5_host_desc_t *desc) 836 { 837 struct cppi5_host_desc_t *first_desc, *next_desc; 838 dma_addr_t buf_dma, next_desc_dma; 839 u32 buf_dma_len; 840 841 first_desc = desc; 842 next_desc = first_desc; 843 844 cppi5_hdesc_get_obuf(first_desc, &buf_dma, &buf_dma_len); 845 k3_udma_glue_tx_cppi5_to_dma_addr(tx_chn->tx_chn, &buf_dma); 846 847 dma_unmap_single(tx_chn->dma_dev, buf_dma, buf_dma_len, DMA_TO_DEVICE); 848 849 next_desc_dma = cppi5_hdesc_get_next_hbdesc(first_desc); 850 k3_udma_glue_tx_cppi5_to_dma_addr(tx_chn->tx_chn, &next_desc_dma); 851 while (next_desc_dma) { 852 next_desc = k3_cppi_desc_pool_dma2virt(tx_chn->desc_pool, 853 next_desc_dma); 854 cppi5_hdesc_get_obuf(next_desc, &buf_dma, &buf_dma_len); 855 k3_udma_glue_tx_cppi5_to_dma_addr(tx_chn->tx_chn, &buf_dma); 856 857 dma_unmap_page(tx_chn->dma_dev, buf_dma, buf_dma_len, 858 DMA_TO_DEVICE); 859 860 next_desc_dma = cppi5_hdesc_get_next_hbdesc(next_desc); 861 k3_udma_glue_tx_cppi5_to_dma_addr(tx_chn->tx_chn, &next_desc_dma); 862 863 k3_cppi_desc_pool_free(tx_chn->desc_pool, next_desc); 864 } 865 866 k3_cppi_desc_pool_free(tx_chn->desc_pool, first_desc); 867 } 868 869 static void am65_cpsw_nuss_tx_cleanup(void *data, dma_addr_t desc_dma) 870 { 871 struct am65_cpsw_tx_chn *tx_chn = data; 872 struct cppi5_host_desc_t *desc_tx; 873 struct sk_buff *skb; 874 void **swdata; 875 876 desc_tx = k3_cppi_desc_pool_dma2virt(tx_chn->desc_pool, desc_dma); 877 swdata = cppi5_hdesc_get_swdata(desc_tx); 878 skb = *(swdata); 879 am65_cpsw_nuss_xmit_free(tx_chn, desc_tx); 880 881 dev_kfree_skb_any(skb); 882 } 883 884 static struct sk_buff * 885 am65_cpsw_nuss_tx_compl_packet(struct am65_cpsw_tx_chn *tx_chn, 886 dma_addr_t desc_dma) 887 { 888 struct am65_cpsw_ndev_priv *ndev_priv; 889 struct am65_cpsw_ndev_stats *stats; 890 struct cppi5_host_desc_t *desc_tx; 891 struct net_device *ndev; 892 struct sk_buff *skb; 893 void **swdata; 894 895 desc_tx = k3_cppi_desc_pool_dma2virt(tx_chn->desc_pool, 896 desc_dma); 897 swdata = cppi5_hdesc_get_swdata(desc_tx); 898 skb = *(swdata); 899 am65_cpsw_nuss_xmit_free(tx_chn, desc_tx); 900 901 ndev = skb->dev; 902 903 am65_cpts_tx_timestamp(tx_chn->common->cpts, skb); 904 905 ndev_priv = netdev_priv(ndev); 906 stats = this_cpu_ptr(ndev_priv->stats); 907 u64_stats_update_begin(&stats->syncp); 908 stats->tx_packets++; 909 stats->tx_bytes += skb->len; 910 u64_stats_update_end(&stats->syncp); 911 912 return skb; 913 } 914 915 static void am65_cpsw_nuss_tx_wake(struct am65_cpsw_tx_chn *tx_chn, struct net_device *ndev, 916 struct netdev_queue *netif_txq) 917 { 918 if (netif_tx_queue_stopped(netif_txq)) { 919 /* Check whether the queue is stopped due to stalled 920 * tx dma, if the queue is stopped then wake the queue 921 * as we have free desc for tx 922 */ 923 __netif_tx_lock(netif_txq, smp_processor_id()); 924 if (netif_running(ndev) && 925 (k3_cppi_desc_pool_avail(tx_chn->desc_pool) >= MAX_SKB_FRAGS)) 926 netif_tx_wake_queue(netif_txq); 927 928 __netif_tx_unlock(netif_txq); 929 } 930 } 931 932 static int am65_cpsw_nuss_tx_compl_packets(struct am65_cpsw_common *common, 933 int chn, unsigned int budget) 934 { 935 struct device *dev = common->dev; 936 struct am65_cpsw_tx_chn *tx_chn; 937 struct netdev_queue *netif_txq; 938 unsigned int total_bytes = 0; 939 struct net_device *ndev; 940 struct sk_buff *skb; 941 dma_addr_t desc_dma; 942 int res, num_tx = 0; 943 944 tx_chn = &common->tx_chns[chn]; 945 946 while (true) { 947 spin_lock(&tx_chn->lock); 948 res = k3_udma_glue_pop_tx_chn(tx_chn->tx_chn, &desc_dma); 949 spin_unlock(&tx_chn->lock); 950 if (res == -ENODATA) 951 break; 952 953 if (cppi5_desc_is_tdcm(desc_dma)) { 954 if (atomic_dec_and_test(&common->tdown_cnt)) 955 complete(&common->tdown_complete); 956 break; 957 } 958 959 skb = am65_cpsw_nuss_tx_compl_packet(tx_chn, desc_dma); 960 total_bytes = skb->len; 961 ndev = skb->dev; 962 napi_consume_skb(skb, budget); 963 num_tx++; 964 965 netif_txq = netdev_get_tx_queue(ndev, chn); 966 967 netdev_tx_completed_queue(netif_txq, num_tx, total_bytes); 968 969 am65_cpsw_nuss_tx_wake(tx_chn, ndev, netif_txq); 970 } 971 972 dev_dbg(dev, "%s:%u pkt:%d\n", __func__, chn, num_tx); 973 974 return num_tx; 975 } 976 977 static int am65_cpsw_nuss_tx_compl_packets_2g(struct am65_cpsw_common *common, 978 int chn, unsigned int budget) 979 { 980 struct device *dev = common->dev; 981 struct am65_cpsw_tx_chn *tx_chn; 982 struct netdev_queue *netif_txq; 983 unsigned int total_bytes = 0; 984 struct net_device *ndev; 985 struct sk_buff *skb; 986 dma_addr_t desc_dma; 987 int res, num_tx = 0; 988 989 tx_chn = &common->tx_chns[chn]; 990 991 while (true) { 992 res = k3_udma_glue_pop_tx_chn(tx_chn->tx_chn, &desc_dma); 993 if (res == -ENODATA) 994 break; 995 996 if (cppi5_desc_is_tdcm(desc_dma)) { 997 if (atomic_dec_and_test(&common->tdown_cnt)) 998 complete(&common->tdown_complete); 999 break; 1000 } 1001 1002 skb = am65_cpsw_nuss_tx_compl_packet(tx_chn, desc_dma); 1003 1004 ndev = skb->dev; 1005 total_bytes += skb->len; 1006 napi_consume_skb(skb, budget); 1007 num_tx++; 1008 } 1009 1010 if (!num_tx) 1011 return 0; 1012 1013 netif_txq = netdev_get_tx_queue(ndev, chn); 1014 1015 netdev_tx_completed_queue(netif_txq, num_tx, total_bytes); 1016 1017 am65_cpsw_nuss_tx_wake(tx_chn, ndev, netif_txq); 1018 1019 dev_dbg(dev, "%s:%u pkt:%d\n", __func__, chn, num_tx); 1020 1021 return num_tx; 1022 } 1023 1024 static int am65_cpsw_nuss_tx_poll(struct napi_struct *napi_tx, int budget) 1025 { 1026 struct am65_cpsw_tx_chn *tx_chn = am65_cpsw_napi_to_tx_chn(napi_tx); 1027 int num_tx; 1028 1029 if (AM65_CPSW_IS_CPSW2G(tx_chn->common)) 1030 num_tx = am65_cpsw_nuss_tx_compl_packets_2g(tx_chn->common, tx_chn->id, budget); 1031 else 1032 num_tx = am65_cpsw_nuss_tx_compl_packets(tx_chn->common, tx_chn->id, budget); 1033 1034 if (num_tx >= budget) 1035 return budget; 1036 1037 if (napi_complete_done(napi_tx, num_tx)) 1038 enable_irq(tx_chn->irq); 1039 1040 return 0; 1041 } 1042 1043 static irqreturn_t am65_cpsw_nuss_rx_irq(int irq, void *dev_id) 1044 { 1045 struct am65_cpsw_common *common = dev_id; 1046 1047 common->rx_irq_disabled = true; 1048 disable_irq_nosync(irq); 1049 napi_schedule(&common->napi_rx); 1050 1051 return IRQ_HANDLED; 1052 } 1053 1054 static irqreturn_t am65_cpsw_nuss_tx_irq(int irq, void *dev_id) 1055 { 1056 struct am65_cpsw_tx_chn *tx_chn = dev_id; 1057 1058 disable_irq_nosync(irq); 1059 napi_schedule(&tx_chn->napi_tx); 1060 1061 return IRQ_HANDLED; 1062 } 1063 1064 static netdev_tx_t am65_cpsw_nuss_ndo_slave_xmit(struct sk_buff *skb, 1065 struct net_device *ndev) 1066 { 1067 struct am65_cpsw_common *common = am65_ndev_to_common(ndev); 1068 struct cppi5_host_desc_t *first_desc, *next_desc, *cur_desc; 1069 struct am65_cpsw_port *port = am65_ndev_to_port(ndev); 1070 struct device *dev = common->dev; 1071 struct am65_cpsw_tx_chn *tx_chn; 1072 struct netdev_queue *netif_txq; 1073 dma_addr_t desc_dma, buf_dma; 1074 int ret, q_idx, i; 1075 void **swdata; 1076 u32 *psdata; 1077 u32 pkt_len; 1078 1079 /* padding enabled in hw */ 1080 pkt_len = skb_headlen(skb); 1081 1082 /* SKB TX timestamp */ 1083 if (port->tx_ts_enabled) 1084 am65_cpts_prep_tx_timestamp(common->cpts, skb); 1085 1086 q_idx = skb_get_queue_mapping(skb); 1087 dev_dbg(dev, "%s skb_queue:%d\n", __func__, q_idx); 1088 1089 tx_chn = &common->tx_chns[q_idx]; 1090 netif_txq = netdev_get_tx_queue(ndev, q_idx); 1091 1092 /* Map the linear buffer */ 1093 buf_dma = dma_map_single(tx_chn->dma_dev, skb->data, pkt_len, 1094 DMA_TO_DEVICE); 1095 if (unlikely(dma_mapping_error(tx_chn->dma_dev, buf_dma))) { 1096 dev_err(dev, "Failed to map tx skb buffer\n"); 1097 ndev->stats.tx_errors++; 1098 goto err_free_skb; 1099 } 1100 1101 first_desc = k3_cppi_desc_pool_alloc(tx_chn->desc_pool); 1102 if (!first_desc) { 1103 dev_dbg(dev, "Failed to allocate descriptor\n"); 1104 dma_unmap_single(tx_chn->dma_dev, buf_dma, pkt_len, 1105 DMA_TO_DEVICE); 1106 goto busy_stop_q; 1107 } 1108 1109 cppi5_hdesc_init(first_desc, CPPI5_INFO0_HDESC_EPIB_PRESENT, 1110 AM65_CPSW_NAV_PS_DATA_SIZE); 1111 cppi5_desc_set_pktids(&first_desc->hdr, 0, 0x3FFF); 1112 cppi5_hdesc_set_pkttype(first_desc, 0x7); 1113 cppi5_desc_set_tags_ids(&first_desc->hdr, 0, port->port_id); 1114 1115 k3_udma_glue_tx_dma_to_cppi5_addr(tx_chn->tx_chn, &buf_dma); 1116 cppi5_hdesc_attach_buf(first_desc, buf_dma, pkt_len, buf_dma, pkt_len); 1117 swdata = cppi5_hdesc_get_swdata(first_desc); 1118 *(swdata) = skb; 1119 psdata = cppi5_hdesc_get_psdata(first_desc); 1120 1121 /* HW csum offload if enabled */ 1122 psdata[2] = 0; 1123 if (likely(skb->ip_summed == CHECKSUM_PARTIAL)) { 1124 unsigned int cs_start, cs_offset; 1125 1126 cs_start = skb_transport_offset(skb); 1127 cs_offset = cs_start + skb->csum_offset; 1128 /* HW numerates bytes starting from 1 */ 1129 psdata[2] = ((cs_offset + 1) << 24) | 1130 ((cs_start + 1) << 16) | (skb->len - cs_start); 1131 dev_dbg(dev, "%s tx psdata:%#x\n", __func__, psdata[2]); 1132 } 1133 1134 if (!skb_is_nonlinear(skb)) 1135 goto done_tx; 1136 1137 dev_dbg(dev, "fragmented SKB\n"); 1138 1139 /* Handle the case where skb is fragmented in pages */ 1140 cur_desc = first_desc; 1141 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { 1142 skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 1143 u32 frag_size = skb_frag_size(frag); 1144 1145 next_desc = k3_cppi_desc_pool_alloc(tx_chn->desc_pool); 1146 if (!next_desc) { 1147 dev_err(dev, "Failed to allocate descriptor\n"); 1148 goto busy_free_descs; 1149 } 1150 1151 buf_dma = skb_frag_dma_map(tx_chn->dma_dev, frag, 0, frag_size, 1152 DMA_TO_DEVICE); 1153 if (unlikely(dma_mapping_error(tx_chn->dma_dev, buf_dma))) { 1154 dev_err(dev, "Failed to map tx skb page\n"); 1155 k3_cppi_desc_pool_free(tx_chn->desc_pool, next_desc); 1156 ndev->stats.tx_errors++; 1157 goto err_free_descs; 1158 } 1159 1160 cppi5_hdesc_reset_hbdesc(next_desc); 1161 k3_udma_glue_tx_dma_to_cppi5_addr(tx_chn->tx_chn, &buf_dma); 1162 cppi5_hdesc_attach_buf(next_desc, 1163 buf_dma, frag_size, buf_dma, frag_size); 1164 1165 desc_dma = k3_cppi_desc_pool_virt2dma(tx_chn->desc_pool, 1166 next_desc); 1167 k3_udma_glue_tx_dma_to_cppi5_addr(tx_chn->tx_chn, &desc_dma); 1168 cppi5_hdesc_link_hbdesc(cur_desc, desc_dma); 1169 1170 pkt_len += frag_size; 1171 cur_desc = next_desc; 1172 } 1173 WARN_ON(pkt_len != skb->len); 1174 1175 done_tx: 1176 skb_tx_timestamp(skb); 1177 1178 /* report bql before sending packet */ 1179 netdev_tx_sent_queue(netif_txq, pkt_len); 1180 1181 cppi5_hdesc_set_pktlen(first_desc, pkt_len); 1182 desc_dma = k3_cppi_desc_pool_virt2dma(tx_chn->desc_pool, first_desc); 1183 if (AM65_CPSW_IS_CPSW2G(common)) { 1184 ret = k3_udma_glue_push_tx_chn(tx_chn->tx_chn, first_desc, desc_dma); 1185 } else { 1186 spin_lock_bh(&tx_chn->lock); 1187 ret = k3_udma_glue_push_tx_chn(tx_chn->tx_chn, first_desc, desc_dma); 1188 spin_unlock_bh(&tx_chn->lock); 1189 } 1190 if (ret) { 1191 dev_err(dev, "can't push desc %d\n", ret); 1192 /* inform bql */ 1193 netdev_tx_completed_queue(netif_txq, 1, pkt_len); 1194 ndev->stats.tx_errors++; 1195 goto err_free_descs; 1196 } 1197 1198 if (k3_cppi_desc_pool_avail(tx_chn->desc_pool) < MAX_SKB_FRAGS) { 1199 netif_tx_stop_queue(netif_txq); 1200 /* Barrier, so that stop_queue visible to other cpus */ 1201 smp_mb__after_atomic(); 1202 dev_dbg(dev, "netif_tx_stop_queue %d\n", q_idx); 1203 1204 /* re-check for smp */ 1205 if (k3_cppi_desc_pool_avail(tx_chn->desc_pool) >= 1206 MAX_SKB_FRAGS) { 1207 netif_tx_wake_queue(netif_txq); 1208 dev_dbg(dev, "netif_tx_wake_queue %d\n", q_idx); 1209 } 1210 } 1211 1212 return NETDEV_TX_OK; 1213 1214 err_free_descs: 1215 am65_cpsw_nuss_xmit_free(tx_chn, first_desc); 1216 err_free_skb: 1217 ndev->stats.tx_dropped++; 1218 dev_kfree_skb_any(skb); 1219 return NETDEV_TX_OK; 1220 1221 busy_free_descs: 1222 am65_cpsw_nuss_xmit_free(tx_chn, first_desc); 1223 busy_stop_q: 1224 netif_tx_stop_queue(netif_txq); 1225 return NETDEV_TX_BUSY; 1226 } 1227 1228 static int am65_cpsw_nuss_ndo_slave_set_mac_address(struct net_device *ndev, 1229 void *addr) 1230 { 1231 struct am65_cpsw_common *common = am65_ndev_to_common(ndev); 1232 struct am65_cpsw_port *port = am65_ndev_to_port(ndev); 1233 struct sockaddr *sockaddr = (struct sockaddr *)addr; 1234 int ret; 1235 1236 ret = eth_prepare_mac_addr_change(ndev, addr); 1237 if (ret < 0) 1238 return ret; 1239 1240 ret = pm_runtime_resume_and_get(common->dev); 1241 if (ret < 0) 1242 return ret; 1243 1244 cpsw_ale_del_ucast(common->ale, ndev->dev_addr, 1245 HOST_PORT_NUM, 0, 0); 1246 cpsw_ale_add_ucast(common->ale, sockaddr->sa_data, 1247 HOST_PORT_NUM, ALE_SECURE, 0); 1248 1249 am65_cpsw_port_set_sl_mac(port, addr); 1250 eth_commit_mac_addr_change(ndev, sockaddr); 1251 1252 pm_runtime_put(common->dev); 1253 1254 return 0; 1255 } 1256 1257 static int am65_cpsw_nuss_hwtstamp_set(struct net_device *ndev, 1258 struct ifreq *ifr) 1259 { 1260 struct am65_cpsw_common *common = am65_ndev_to_common(ndev); 1261 struct am65_cpsw_port *port = am65_ndev_to_port(ndev); 1262 u32 ts_ctrl, seq_id, ts_ctrl_ltype2, ts_vlan_ltype; 1263 struct hwtstamp_config cfg; 1264 1265 if (!IS_ENABLED(CONFIG_TI_K3_AM65_CPTS)) 1266 return -EOPNOTSUPP; 1267 1268 if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg))) 1269 return -EFAULT; 1270 1271 /* TX HW timestamp */ 1272 switch (cfg.tx_type) { 1273 case HWTSTAMP_TX_OFF: 1274 case HWTSTAMP_TX_ON: 1275 break; 1276 default: 1277 return -ERANGE; 1278 } 1279 1280 switch (cfg.rx_filter) { 1281 case HWTSTAMP_FILTER_NONE: 1282 port->rx_ts_enabled = false; 1283 break; 1284 case HWTSTAMP_FILTER_ALL: 1285 case HWTSTAMP_FILTER_SOME: 1286 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: 1287 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: 1288 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: 1289 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: 1290 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 1291 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 1292 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: 1293 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: 1294 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: 1295 case HWTSTAMP_FILTER_PTP_V2_EVENT: 1296 case HWTSTAMP_FILTER_PTP_V2_SYNC: 1297 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 1298 case HWTSTAMP_FILTER_NTP_ALL: 1299 port->rx_ts_enabled = true; 1300 cfg.rx_filter = HWTSTAMP_FILTER_ALL; 1301 break; 1302 default: 1303 return -ERANGE; 1304 } 1305 1306 port->tx_ts_enabled = (cfg.tx_type == HWTSTAMP_TX_ON); 1307 1308 /* cfg TX timestamp */ 1309 seq_id = (AM65_CPSW_TS_SEQ_ID_OFFSET << 1310 AM65_CPSW_PN_TS_SEQ_ID_OFFSET_SHIFT) | ETH_P_1588; 1311 1312 ts_vlan_ltype = ETH_P_8021Q; 1313 1314 ts_ctrl_ltype2 = ETH_P_1588 | 1315 AM65_CPSW_PN_TS_CTL_LTYPE2_TS_107 | 1316 AM65_CPSW_PN_TS_CTL_LTYPE2_TS_129 | 1317 AM65_CPSW_PN_TS_CTL_LTYPE2_TS_130 | 1318 AM65_CPSW_PN_TS_CTL_LTYPE2_TS_131 | 1319 AM65_CPSW_PN_TS_CTL_LTYPE2_TS_132 | 1320 AM65_CPSW_PN_TS_CTL_LTYPE2_TS_319 | 1321 AM65_CPSW_PN_TS_CTL_LTYPE2_TS_320 | 1322 AM65_CPSW_PN_TS_CTL_LTYPE2_TS_TTL_NONZERO; 1323 1324 ts_ctrl = AM65_CPSW_TS_EVENT_MSG_TYPE_BITS << 1325 AM65_CPSW_PN_TS_CTL_MSG_TYPE_EN_SHIFT; 1326 1327 if (port->tx_ts_enabled) 1328 ts_ctrl |= AM65_CPSW_TS_TX_ANX_ALL_EN | 1329 AM65_CPSW_PN_TS_CTL_TX_VLAN_LT1_EN; 1330 1331 writel(seq_id, port->port_base + AM65_CPSW_PORTN_REG_TS_SEQ_LTYPE_REG); 1332 writel(ts_vlan_ltype, port->port_base + 1333 AM65_CPSW_PORTN_REG_TS_VLAN_LTYPE_REG); 1334 writel(ts_ctrl_ltype2, port->port_base + 1335 AM65_CPSW_PORTN_REG_TS_CTL_LTYPE2); 1336 writel(ts_ctrl, port->port_base + AM65_CPSW_PORTN_REG_TS_CTL); 1337 1338 /* en/dis RX timestamp */ 1339 am65_cpts_rx_enable(common->cpts, port->rx_ts_enabled); 1340 1341 return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0; 1342 } 1343 1344 static int am65_cpsw_nuss_hwtstamp_get(struct net_device *ndev, 1345 struct ifreq *ifr) 1346 { 1347 struct am65_cpsw_port *port = am65_ndev_to_port(ndev); 1348 struct hwtstamp_config cfg; 1349 1350 if (!IS_ENABLED(CONFIG_TI_K3_AM65_CPTS)) 1351 return -EOPNOTSUPP; 1352 1353 cfg.flags = 0; 1354 cfg.tx_type = port->tx_ts_enabled ? 1355 HWTSTAMP_TX_ON : HWTSTAMP_TX_OFF; 1356 cfg.rx_filter = port->rx_ts_enabled ? 1357 HWTSTAMP_FILTER_ALL : HWTSTAMP_FILTER_NONE; 1358 1359 return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0; 1360 } 1361 1362 static int am65_cpsw_nuss_ndo_slave_ioctl(struct net_device *ndev, 1363 struct ifreq *req, int cmd) 1364 { 1365 struct am65_cpsw_port *port = am65_ndev_to_port(ndev); 1366 1367 if (!netif_running(ndev)) 1368 return -EINVAL; 1369 1370 switch (cmd) { 1371 case SIOCSHWTSTAMP: 1372 return am65_cpsw_nuss_hwtstamp_set(ndev, req); 1373 case SIOCGHWTSTAMP: 1374 return am65_cpsw_nuss_hwtstamp_get(ndev, req); 1375 } 1376 1377 return phylink_mii_ioctl(port->slave.phylink, req, cmd); 1378 } 1379 1380 static void am65_cpsw_nuss_ndo_get_stats(struct net_device *dev, 1381 struct rtnl_link_stats64 *stats) 1382 { 1383 struct am65_cpsw_ndev_priv *ndev_priv = netdev_priv(dev); 1384 unsigned int start; 1385 int cpu; 1386 1387 for_each_possible_cpu(cpu) { 1388 struct am65_cpsw_ndev_stats *cpu_stats; 1389 u64 rx_packets; 1390 u64 rx_bytes; 1391 u64 tx_packets; 1392 u64 tx_bytes; 1393 1394 cpu_stats = per_cpu_ptr(ndev_priv->stats, cpu); 1395 do { 1396 start = u64_stats_fetch_begin(&cpu_stats->syncp); 1397 rx_packets = cpu_stats->rx_packets; 1398 rx_bytes = cpu_stats->rx_bytes; 1399 tx_packets = cpu_stats->tx_packets; 1400 tx_bytes = cpu_stats->tx_bytes; 1401 } while (u64_stats_fetch_retry(&cpu_stats->syncp, start)); 1402 1403 stats->rx_packets += rx_packets; 1404 stats->rx_bytes += rx_bytes; 1405 stats->tx_packets += tx_packets; 1406 stats->tx_bytes += tx_bytes; 1407 } 1408 1409 stats->rx_errors = dev->stats.rx_errors; 1410 stats->rx_dropped = dev->stats.rx_dropped; 1411 stats->tx_dropped = dev->stats.tx_dropped; 1412 } 1413 1414 static const struct net_device_ops am65_cpsw_nuss_netdev_ops = { 1415 .ndo_open = am65_cpsw_nuss_ndo_slave_open, 1416 .ndo_stop = am65_cpsw_nuss_ndo_slave_stop, 1417 .ndo_start_xmit = am65_cpsw_nuss_ndo_slave_xmit, 1418 .ndo_set_rx_mode = am65_cpsw_nuss_ndo_slave_set_rx_mode, 1419 .ndo_get_stats64 = am65_cpsw_nuss_ndo_get_stats, 1420 .ndo_validate_addr = eth_validate_addr, 1421 .ndo_set_mac_address = am65_cpsw_nuss_ndo_slave_set_mac_address, 1422 .ndo_tx_timeout = am65_cpsw_nuss_ndo_host_tx_timeout, 1423 .ndo_vlan_rx_add_vid = am65_cpsw_nuss_ndo_slave_add_vid, 1424 .ndo_vlan_rx_kill_vid = am65_cpsw_nuss_ndo_slave_kill_vid, 1425 .ndo_eth_ioctl = am65_cpsw_nuss_ndo_slave_ioctl, 1426 .ndo_setup_tc = am65_cpsw_qos_ndo_setup_tc, 1427 }; 1428 1429 static void am65_cpsw_disable_phy(struct phy *phy) 1430 { 1431 phy_power_off(phy); 1432 phy_exit(phy); 1433 } 1434 1435 static int am65_cpsw_enable_phy(struct phy *phy) 1436 { 1437 int ret; 1438 1439 ret = phy_init(phy); 1440 if (ret < 0) 1441 return ret; 1442 1443 ret = phy_power_on(phy); 1444 if (ret < 0) { 1445 phy_exit(phy); 1446 return ret; 1447 } 1448 1449 return 0; 1450 } 1451 1452 static void am65_cpsw_disable_serdes_phy(struct am65_cpsw_common *common) 1453 { 1454 struct am65_cpsw_port *port; 1455 struct phy *phy; 1456 int i; 1457 1458 for (i = 0; i < common->port_num; i++) { 1459 port = &common->ports[i]; 1460 phy = port->slave.serdes_phy; 1461 if (phy) 1462 am65_cpsw_disable_phy(phy); 1463 } 1464 } 1465 1466 static int am65_cpsw_init_serdes_phy(struct device *dev, struct device_node *port_np, 1467 struct am65_cpsw_port *port) 1468 { 1469 const char *name = "serdes-phy"; 1470 struct phy *phy; 1471 int ret; 1472 1473 phy = devm_of_phy_get(dev, port_np, name); 1474 if (PTR_ERR(phy) == -ENODEV) 1475 return 0; 1476 if (IS_ERR(phy)) 1477 return PTR_ERR(phy); 1478 1479 /* Serdes PHY exists. Store it. */ 1480 port->slave.serdes_phy = phy; 1481 1482 ret = am65_cpsw_enable_phy(phy); 1483 if (ret < 0) 1484 goto err_phy; 1485 1486 return 0; 1487 1488 err_phy: 1489 devm_phy_put(dev, phy); 1490 return ret; 1491 } 1492 1493 static void am65_cpsw_nuss_mac_config(struct phylink_config *config, unsigned int mode, 1494 const struct phylink_link_state *state) 1495 { 1496 struct am65_cpsw_slave_data *slave = container_of(config, struct am65_cpsw_slave_data, 1497 phylink_config); 1498 struct am65_cpsw_port *port = container_of(slave, struct am65_cpsw_port, slave); 1499 struct am65_cpsw_common *common = port->common; 1500 1501 if (common->pdata.extra_modes & BIT(state->interface)) 1502 writel(AM65_CPSW_SGMII_CONTROL_MR_AN_ENABLE, 1503 port->sgmii_base + AM65_CPSW_SGMII_CONTROL_REG); 1504 } 1505 1506 static void am65_cpsw_nuss_mac_link_down(struct phylink_config *config, unsigned int mode, 1507 phy_interface_t interface) 1508 { 1509 struct am65_cpsw_slave_data *slave = container_of(config, struct am65_cpsw_slave_data, 1510 phylink_config); 1511 struct am65_cpsw_port *port = container_of(slave, struct am65_cpsw_port, slave); 1512 struct am65_cpsw_common *common = port->common; 1513 struct net_device *ndev = port->ndev; 1514 int tmo; 1515 1516 /* disable forwarding */ 1517 cpsw_ale_control_set(common->ale, port->port_id, ALE_PORT_STATE, ALE_PORT_STATE_DISABLE); 1518 1519 cpsw_sl_ctl_set(port->slave.mac_sl, CPSW_SL_CTL_CMD_IDLE); 1520 1521 tmo = cpsw_sl_wait_for_idle(port->slave.mac_sl, 100); 1522 dev_dbg(common->dev, "down msc_sl %08x tmo %d\n", 1523 cpsw_sl_reg_read(port->slave.mac_sl, CPSW_SL_MACSTATUS), tmo); 1524 1525 cpsw_sl_ctl_reset(port->slave.mac_sl); 1526 1527 am65_cpsw_qos_link_down(ndev); 1528 netif_tx_stop_all_queues(ndev); 1529 } 1530 1531 static void am65_cpsw_nuss_mac_link_up(struct phylink_config *config, struct phy_device *phy, 1532 unsigned int mode, phy_interface_t interface, int speed, 1533 int duplex, bool tx_pause, bool rx_pause) 1534 { 1535 struct am65_cpsw_slave_data *slave = container_of(config, struct am65_cpsw_slave_data, 1536 phylink_config); 1537 struct am65_cpsw_port *port = container_of(slave, struct am65_cpsw_port, slave); 1538 struct am65_cpsw_common *common = port->common; 1539 u32 mac_control = CPSW_SL_CTL_GMII_EN; 1540 struct net_device *ndev = port->ndev; 1541 1542 if (speed == SPEED_1000) 1543 mac_control |= CPSW_SL_CTL_GIG; 1544 if (speed == SPEED_10 && phy_interface_mode_is_rgmii(interface)) 1545 /* Can be used with in band mode only */ 1546 mac_control |= CPSW_SL_CTL_EXT_EN; 1547 if (speed == SPEED_100 && interface == PHY_INTERFACE_MODE_RMII) 1548 mac_control |= CPSW_SL_CTL_IFCTL_A; 1549 if (duplex) 1550 mac_control |= CPSW_SL_CTL_FULLDUPLEX; 1551 1552 /* rx_pause/tx_pause */ 1553 if (rx_pause) 1554 mac_control |= CPSW_SL_CTL_RX_FLOW_EN; 1555 1556 if (tx_pause) 1557 mac_control |= CPSW_SL_CTL_TX_FLOW_EN; 1558 1559 cpsw_sl_ctl_set(port->slave.mac_sl, mac_control); 1560 1561 /* enable forwarding */ 1562 cpsw_ale_control_set(common->ale, port->port_id, ALE_PORT_STATE, ALE_PORT_STATE_FORWARD); 1563 1564 am65_cpsw_qos_link_up(ndev, speed); 1565 netif_tx_wake_all_queues(ndev); 1566 } 1567 1568 static const struct phylink_mac_ops am65_cpsw_phylink_mac_ops = { 1569 .mac_config = am65_cpsw_nuss_mac_config, 1570 .mac_link_down = am65_cpsw_nuss_mac_link_down, 1571 .mac_link_up = am65_cpsw_nuss_mac_link_up, 1572 }; 1573 1574 static void am65_cpsw_nuss_slave_disable_unused(struct am65_cpsw_port *port) 1575 { 1576 struct am65_cpsw_common *common = port->common; 1577 1578 if (!port->disabled) 1579 return; 1580 1581 cpsw_ale_control_set(common->ale, port->port_id, 1582 ALE_PORT_STATE, ALE_PORT_STATE_DISABLE); 1583 1584 cpsw_sl_reset(port->slave.mac_sl, 100); 1585 cpsw_sl_ctl_reset(port->slave.mac_sl); 1586 } 1587 1588 static void am65_cpsw_nuss_free_tx_chns(void *data) 1589 { 1590 struct am65_cpsw_common *common = data; 1591 int i; 1592 1593 for (i = 0; i < common->tx_ch_num; i++) { 1594 struct am65_cpsw_tx_chn *tx_chn = &common->tx_chns[i]; 1595 1596 if (!IS_ERR_OR_NULL(tx_chn->desc_pool)) 1597 k3_cppi_desc_pool_destroy(tx_chn->desc_pool); 1598 1599 if (!IS_ERR_OR_NULL(tx_chn->tx_chn)) 1600 k3_udma_glue_release_tx_chn(tx_chn->tx_chn); 1601 1602 memset(tx_chn, 0, sizeof(*tx_chn)); 1603 } 1604 } 1605 1606 void am65_cpsw_nuss_remove_tx_chns(struct am65_cpsw_common *common) 1607 { 1608 struct device *dev = common->dev; 1609 int i; 1610 1611 devm_remove_action(dev, am65_cpsw_nuss_free_tx_chns, common); 1612 1613 for (i = 0; i < common->tx_ch_num; i++) { 1614 struct am65_cpsw_tx_chn *tx_chn = &common->tx_chns[i]; 1615 1616 if (tx_chn->irq) 1617 devm_free_irq(dev, tx_chn->irq, tx_chn); 1618 1619 netif_napi_del(&tx_chn->napi_tx); 1620 1621 if (!IS_ERR_OR_NULL(tx_chn->desc_pool)) 1622 k3_cppi_desc_pool_destroy(tx_chn->desc_pool); 1623 1624 if (!IS_ERR_OR_NULL(tx_chn->tx_chn)) 1625 k3_udma_glue_release_tx_chn(tx_chn->tx_chn); 1626 1627 memset(tx_chn, 0, sizeof(*tx_chn)); 1628 } 1629 } 1630 1631 static int am65_cpsw_nuss_ndev_add_tx_napi(struct am65_cpsw_common *common) 1632 { 1633 struct device *dev = common->dev; 1634 int i, ret = 0; 1635 1636 for (i = 0; i < common->tx_ch_num; i++) { 1637 struct am65_cpsw_tx_chn *tx_chn = &common->tx_chns[i]; 1638 1639 netif_napi_add_tx(common->dma_ndev, &tx_chn->napi_tx, 1640 am65_cpsw_nuss_tx_poll); 1641 1642 ret = devm_request_irq(dev, tx_chn->irq, 1643 am65_cpsw_nuss_tx_irq, 1644 IRQF_TRIGGER_HIGH, 1645 tx_chn->tx_chn_name, tx_chn); 1646 if (ret) { 1647 dev_err(dev, "failure requesting tx%u irq %u, %d\n", 1648 tx_chn->id, tx_chn->irq, ret); 1649 goto err; 1650 } 1651 } 1652 1653 err: 1654 return ret; 1655 } 1656 1657 static int am65_cpsw_nuss_init_tx_chns(struct am65_cpsw_common *common) 1658 { 1659 u32 max_desc_num = ALIGN(AM65_CPSW_MAX_TX_DESC, MAX_SKB_FRAGS); 1660 struct k3_udma_glue_tx_channel_cfg tx_cfg = { 0 }; 1661 struct device *dev = common->dev; 1662 struct k3_ring_cfg ring_cfg = { 1663 .elm_size = K3_RINGACC_RING_ELSIZE_8, 1664 .mode = K3_RINGACC_RING_MODE_RING, 1665 .flags = 0 1666 }; 1667 u32 hdesc_size; 1668 int i, ret = 0; 1669 1670 hdesc_size = cppi5_hdesc_calc_size(true, AM65_CPSW_NAV_PS_DATA_SIZE, 1671 AM65_CPSW_NAV_SW_DATA_SIZE); 1672 1673 tx_cfg.swdata_size = AM65_CPSW_NAV_SW_DATA_SIZE; 1674 tx_cfg.tx_cfg = ring_cfg; 1675 tx_cfg.txcq_cfg = ring_cfg; 1676 tx_cfg.tx_cfg.size = max_desc_num; 1677 tx_cfg.txcq_cfg.size = max_desc_num; 1678 1679 for (i = 0; i < common->tx_ch_num; i++) { 1680 struct am65_cpsw_tx_chn *tx_chn = &common->tx_chns[i]; 1681 1682 snprintf(tx_chn->tx_chn_name, 1683 sizeof(tx_chn->tx_chn_name), "tx%d", i); 1684 1685 spin_lock_init(&tx_chn->lock); 1686 tx_chn->common = common; 1687 tx_chn->id = i; 1688 tx_chn->descs_num = max_desc_num; 1689 1690 tx_chn->tx_chn = 1691 k3_udma_glue_request_tx_chn(dev, 1692 tx_chn->tx_chn_name, 1693 &tx_cfg); 1694 if (IS_ERR(tx_chn->tx_chn)) { 1695 ret = dev_err_probe(dev, PTR_ERR(tx_chn->tx_chn), 1696 "Failed to request tx dma channel\n"); 1697 goto err; 1698 } 1699 tx_chn->dma_dev = k3_udma_glue_tx_get_dma_device(tx_chn->tx_chn); 1700 1701 tx_chn->desc_pool = k3_cppi_desc_pool_create_name(tx_chn->dma_dev, 1702 tx_chn->descs_num, 1703 hdesc_size, 1704 tx_chn->tx_chn_name); 1705 if (IS_ERR(tx_chn->desc_pool)) { 1706 ret = PTR_ERR(tx_chn->desc_pool); 1707 dev_err(dev, "Failed to create poll %d\n", ret); 1708 goto err; 1709 } 1710 1711 tx_chn->irq = k3_udma_glue_tx_get_irq(tx_chn->tx_chn); 1712 if (tx_chn->irq <= 0) { 1713 dev_err(dev, "Failed to get tx dma irq %d\n", 1714 tx_chn->irq); 1715 goto err; 1716 } 1717 1718 snprintf(tx_chn->tx_chn_name, 1719 sizeof(tx_chn->tx_chn_name), "%s-tx%d", 1720 dev_name(dev), tx_chn->id); 1721 } 1722 1723 ret = am65_cpsw_nuss_ndev_add_tx_napi(common); 1724 if (ret) { 1725 dev_err(dev, "Failed to add tx NAPI %d\n", ret); 1726 goto err; 1727 } 1728 1729 err: 1730 i = devm_add_action(dev, am65_cpsw_nuss_free_tx_chns, common); 1731 if (i) { 1732 dev_err(dev, "Failed to add free_tx_chns action %d\n", i); 1733 return i; 1734 } 1735 1736 return ret; 1737 } 1738 1739 static void am65_cpsw_nuss_free_rx_chns(void *data) 1740 { 1741 struct am65_cpsw_common *common = data; 1742 struct am65_cpsw_rx_chn *rx_chn; 1743 1744 rx_chn = &common->rx_chns; 1745 1746 if (!IS_ERR_OR_NULL(rx_chn->desc_pool)) 1747 k3_cppi_desc_pool_destroy(rx_chn->desc_pool); 1748 1749 if (!IS_ERR_OR_NULL(rx_chn->rx_chn)) 1750 k3_udma_glue_release_rx_chn(rx_chn->rx_chn); 1751 } 1752 1753 static void am65_cpsw_nuss_remove_rx_chns(void *data) 1754 { 1755 struct am65_cpsw_common *common = data; 1756 struct am65_cpsw_rx_chn *rx_chn; 1757 struct device *dev = common->dev; 1758 1759 rx_chn = &common->rx_chns; 1760 devm_remove_action(dev, am65_cpsw_nuss_free_rx_chns, common); 1761 1762 if (!(rx_chn->irq < 0)) 1763 devm_free_irq(dev, rx_chn->irq, common); 1764 1765 netif_napi_del(&common->napi_rx); 1766 1767 if (!IS_ERR_OR_NULL(rx_chn->desc_pool)) 1768 k3_cppi_desc_pool_destroy(rx_chn->desc_pool); 1769 1770 if (!IS_ERR_OR_NULL(rx_chn->rx_chn)) 1771 k3_udma_glue_release_rx_chn(rx_chn->rx_chn); 1772 1773 common->rx_flow_id_base = -1; 1774 } 1775 1776 static int am65_cpsw_nuss_init_rx_chns(struct am65_cpsw_common *common) 1777 { 1778 struct am65_cpsw_rx_chn *rx_chn = &common->rx_chns; 1779 struct k3_udma_glue_rx_channel_cfg rx_cfg = { 0 }; 1780 u32 max_desc_num = AM65_CPSW_MAX_RX_DESC; 1781 struct device *dev = common->dev; 1782 u32 hdesc_size; 1783 u32 fdqring_id; 1784 int i, ret = 0; 1785 1786 hdesc_size = cppi5_hdesc_calc_size(true, AM65_CPSW_NAV_PS_DATA_SIZE, 1787 AM65_CPSW_NAV_SW_DATA_SIZE); 1788 1789 rx_cfg.swdata_size = AM65_CPSW_NAV_SW_DATA_SIZE; 1790 rx_cfg.flow_id_num = AM65_CPSW_MAX_RX_FLOWS; 1791 rx_cfg.flow_id_base = common->rx_flow_id_base; 1792 1793 /* init all flows */ 1794 rx_chn->dev = dev; 1795 rx_chn->descs_num = max_desc_num; 1796 1797 rx_chn->rx_chn = k3_udma_glue_request_rx_chn(dev, "rx", &rx_cfg); 1798 if (IS_ERR(rx_chn->rx_chn)) { 1799 ret = dev_err_probe(dev, PTR_ERR(rx_chn->rx_chn), 1800 "Failed to request rx dma channel\n"); 1801 goto err; 1802 } 1803 rx_chn->dma_dev = k3_udma_glue_rx_get_dma_device(rx_chn->rx_chn); 1804 1805 rx_chn->desc_pool = k3_cppi_desc_pool_create_name(rx_chn->dma_dev, 1806 rx_chn->descs_num, 1807 hdesc_size, "rx"); 1808 if (IS_ERR(rx_chn->desc_pool)) { 1809 ret = PTR_ERR(rx_chn->desc_pool); 1810 dev_err(dev, "Failed to create rx poll %d\n", ret); 1811 goto err; 1812 } 1813 1814 common->rx_flow_id_base = 1815 k3_udma_glue_rx_get_flow_id_base(rx_chn->rx_chn); 1816 dev_info(dev, "set new flow-id-base %u\n", common->rx_flow_id_base); 1817 1818 fdqring_id = K3_RINGACC_RING_ID_ANY; 1819 for (i = 0; i < rx_cfg.flow_id_num; i++) { 1820 struct k3_ring_cfg rxring_cfg = { 1821 .elm_size = K3_RINGACC_RING_ELSIZE_8, 1822 .mode = K3_RINGACC_RING_MODE_RING, 1823 .flags = 0, 1824 }; 1825 struct k3_ring_cfg fdqring_cfg = { 1826 .elm_size = K3_RINGACC_RING_ELSIZE_8, 1827 .flags = K3_RINGACC_RING_SHARED, 1828 }; 1829 struct k3_udma_glue_rx_flow_cfg rx_flow_cfg = { 1830 .rx_cfg = rxring_cfg, 1831 .rxfdq_cfg = fdqring_cfg, 1832 .ring_rxq_id = K3_RINGACC_RING_ID_ANY, 1833 .src_tag_lo_sel = 1834 K3_UDMA_GLUE_SRC_TAG_LO_USE_REMOTE_SRC_TAG, 1835 }; 1836 1837 rx_flow_cfg.ring_rxfdq0_id = fdqring_id; 1838 rx_flow_cfg.rx_cfg.size = max_desc_num; 1839 rx_flow_cfg.rxfdq_cfg.size = max_desc_num; 1840 rx_flow_cfg.rxfdq_cfg.mode = common->pdata.fdqring_mode; 1841 1842 ret = k3_udma_glue_rx_flow_init(rx_chn->rx_chn, 1843 i, &rx_flow_cfg); 1844 if (ret) { 1845 dev_err(dev, "Failed to init rx flow%d %d\n", i, ret); 1846 goto err; 1847 } 1848 if (!i) 1849 fdqring_id = 1850 k3_udma_glue_rx_flow_get_fdq_id(rx_chn->rx_chn, 1851 i); 1852 1853 rx_chn->irq = k3_udma_glue_rx_get_irq(rx_chn->rx_chn, i); 1854 1855 if (rx_chn->irq <= 0) { 1856 dev_err(dev, "Failed to get rx dma irq %d\n", 1857 rx_chn->irq); 1858 ret = -ENXIO; 1859 goto err; 1860 } 1861 } 1862 1863 netif_napi_add(common->dma_ndev, &common->napi_rx, 1864 am65_cpsw_nuss_rx_poll); 1865 1866 ret = devm_request_irq(dev, rx_chn->irq, 1867 am65_cpsw_nuss_rx_irq, 1868 IRQF_TRIGGER_HIGH, dev_name(dev), common); 1869 if (ret) { 1870 dev_err(dev, "failure requesting rx irq %u, %d\n", 1871 rx_chn->irq, ret); 1872 goto err; 1873 } 1874 1875 err: 1876 i = devm_add_action(dev, am65_cpsw_nuss_free_rx_chns, common); 1877 if (i) { 1878 dev_err(dev, "Failed to add free_rx_chns action %d\n", i); 1879 return i; 1880 } 1881 1882 return ret; 1883 } 1884 1885 static int am65_cpsw_nuss_init_host_p(struct am65_cpsw_common *common) 1886 { 1887 struct am65_cpsw_host *host_p = am65_common_get_host(common); 1888 1889 host_p->common = common; 1890 host_p->port_base = common->cpsw_base + AM65_CPSW_NU_PORTS_BASE; 1891 host_p->stat_base = common->cpsw_base + AM65_CPSW_NU_STATS_BASE; 1892 1893 return 0; 1894 } 1895 1896 static int am65_cpsw_am654_get_efuse_macid(struct device_node *of_node, 1897 int slave, u8 *mac_addr) 1898 { 1899 u32 mac_lo, mac_hi, offset; 1900 struct regmap *syscon; 1901 int ret; 1902 1903 syscon = syscon_regmap_lookup_by_phandle(of_node, "ti,syscon-efuse"); 1904 if (IS_ERR(syscon)) { 1905 if (PTR_ERR(syscon) == -ENODEV) 1906 return 0; 1907 return PTR_ERR(syscon); 1908 } 1909 1910 ret = of_property_read_u32_index(of_node, "ti,syscon-efuse", 1, 1911 &offset); 1912 if (ret) 1913 return ret; 1914 1915 regmap_read(syscon, offset, &mac_lo); 1916 regmap_read(syscon, offset + 4, &mac_hi); 1917 1918 mac_addr[0] = (mac_hi >> 8) & 0xff; 1919 mac_addr[1] = mac_hi & 0xff; 1920 mac_addr[2] = (mac_lo >> 24) & 0xff; 1921 mac_addr[3] = (mac_lo >> 16) & 0xff; 1922 mac_addr[4] = (mac_lo >> 8) & 0xff; 1923 mac_addr[5] = mac_lo & 0xff; 1924 1925 return 0; 1926 } 1927 1928 static int am65_cpsw_init_cpts(struct am65_cpsw_common *common) 1929 { 1930 struct device *dev = common->dev; 1931 struct device_node *node; 1932 struct am65_cpts *cpts; 1933 void __iomem *reg_base; 1934 1935 if (!IS_ENABLED(CONFIG_TI_K3_AM65_CPTS)) 1936 return 0; 1937 1938 node = of_get_child_by_name(dev->of_node, "cpts"); 1939 if (!node) { 1940 dev_err(dev, "%s cpts not found\n", __func__); 1941 return -ENOENT; 1942 } 1943 1944 reg_base = common->cpsw_base + AM65_CPSW_NU_CPTS_BASE; 1945 cpts = am65_cpts_create(dev, reg_base, node); 1946 if (IS_ERR(cpts)) { 1947 int ret = PTR_ERR(cpts); 1948 1949 of_node_put(node); 1950 dev_err(dev, "cpts create err %d\n", ret); 1951 return ret; 1952 } 1953 common->cpts = cpts; 1954 /* Forbid PM runtime if CPTS is running. 1955 * K3 CPSWxG modules may completely lose context during ON->OFF 1956 * transitions depending on integration. 1957 * AM65x/J721E MCU CPSW2G: false 1958 * J721E MAIN_CPSW9G: true 1959 */ 1960 pm_runtime_forbid(dev); 1961 1962 return 0; 1963 } 1964 1965 static int am65_cpsw_nuss_init_slave_ports(struct am65_cpsw_common *common) 1966 { 1967 struct device_node *node, *port_np; 1968 struct device *dev = common->dev; 1969 int ret; 1970 1971 node = of_get_child_by_name(dev->of_node, "ethernet-ports"); 1972 if (!node) 1973 return -ENOENT; 1974 1975 for_each_child_of_node(node, port_np) { 1976 struct am65_cpsw_port *port; 1977 u32 port_id; 1978 1979 /* it is not a slave port node, continue */ 1980 if (strcmp(port_np->name, "port")) 1981 continue; 1982 1983 ret = of_property_read_u32(port_np, "reg", &port_id); 1984 if (ret < 0) { 1985 dev_err(dev, "%pOF error reading port_id %d\n", 1986 port_np, ret); 1987 goto of_node_put; 1988 } 1989 1990 if (!port_id || port_id > common->port_num) { 1991 dev_err(dev, "%pOF has invalid port_id %u %s\n", 1992 port_np, port_id, port_np->name); 1993 ret = -EINVAL; 1994 goto of_node_put; 1995 } 1996 1997 port = am65_common_get_port(common, port_id); 1998 port->port_id = port_id; 1999 port->common = common; 2000 port->port_base = common->cpsw_base + AM65_CPSW_NU_PORTS_BASE + 2001 AM65_CPSW_NU_PORTS_OFFSET * (port_id); 2002 if (common->pdata.extra_modes) 2003 port->sgmii_base = common->ss_base + AM65_CPSW_SGMII_BASE * (port_id); 2004 port->stat_base = common->cpsw_base + AM65_CPSW_NU_STATS_BASE + 2005 (AM65_CPSW_NU_STATS_PORT_OFFSET * port_id); 2006 port->name = of_get_property(port_np, "label", NULL); 2007 port->fetch_ram_base = 2008 common->cpsw_base + AM65_CPSW_NU_FRAM_BASE + 2009 (AM65_CPSW_NU_FRAM_PORT_OFFSET * (port_id - 1)); 2010 2011 port->slave.mac_sl = cpsw_sl_get("am65", dev, port->port_base); 2012 if (IS_ERR(port->slave.mac_sl)) { 2013 ret = PTR_ERR(port->slave.mac_sl); 2014 goto of_node_put; 2015 } 2016 2017 port->disabled = !of_device_is_available(port_np); 2018 if (port->disabled) { 2019 common->disabled_ports_mask |= BIT(port->port_id); 2020 continue; 2021 } 2022 2023 port->slave.ifphy = devm_of_phy_get(dev, port_np, NULL); 2024 if (IS_ERR(port->slave.ifphy)) { 2025 ret = PTR_ERR(port->slave.ifphy); 2026 dev_err(dev, "%pOF error retrieving port phy: %d\n", 2027 port_np, ret); 2028 goto of_node_put; 2029 } 2030 2031 /* Initialize the Serdes PHY for the port */ 2032 ret = am65_cpsw_init_serdes_phy(dev, port_np, port); 2033 if (ret) 2034 return ret; 2035 2036 port->slave.mac_only = 2037 of_property_read_bool(port_np, "ti,mac-only"); 2038 2039 /* get phy/link info */ 2040 port->slave.phy_node = port_np; 2041 ret = of_get_phy_mode(port_np, &port->slave.phy_if); 2042 if (ret) { 2043 dev_err(dev, "%pOF read phy-mode err %d\n", 2044 port_np, ret); 2045 goto of_node_put; 2046 } 2047 2048 ret = phy_set_mode_ext(port->slave.ifphy, PHY_MODE_ETHERNET, port->slave.phy_if); 2049 if (ret) 2050 goto of_node_put; 2051 2052 ret = of_get_mac_address(port_np, port->slave.mac_addr); 2053 if (ret) { 2054 am65_cpsw_am654_get_efuse_macid(port_np, 2055 port->port_id, 2056 port->slave.mac_addr); 2057 if (!is_valid_ether_addr(port->slave.mac_addr)) { 2058 eth_random_addr(port->slave.mac_addr); 2059 dev_err(dev, "Use random MAC address\n"); 2060 } 2061 } 2062 } 2063 of_node_put(node); 2064 2065 /* is there at least one ext.port */ 2066 if (!(~common->disabled_ports_mask & GENMASK(common->port_num, 1))) { 2067 dev_err(dev, "No Ext. port are available\n"); 2068 return -ENODEV; 2069 } 2070 2071 return 0; 2072 2073 of_node_put: 2074 of_node_put(port_np); 2075 of_node_put(node); 2076 return ret; 2077 } 2078 2079 static void am65_cpsw_pcpu_stats_free(void *data) 2080 { 2081 struct am65_cpsw_ndev_stats __percpu *stats = data; 2082 2083 free_percpu(stats); 2084 } 2085 2086 static void am65_cpsw_nuss_phylink_cleanup(struct am65_cpsw_common *common) 2087 { 2088 struct am65_cpsw_port *port; 2089 int i; 2090 2091 for (i = 0; i < common->port_num; i++) { 2092 port = &common->ports[i]; 2093 if (port->slave.phylink) 2094 phylink_destroy(port->slave.phylink); 2095 } 2096 } 2097 2098 static int 2099 am65_cpsw_nuss_init_port_ndev(struct am65_cpsw_common *common, u32 port_idx) 2100 { 2101 struct am65_cpsw_ndev_priv *ndev_priv; 2102 struct device *dev = common->dev; 2103 struct am65_cpsw_port *port; 2104 struct phylink *phylink; 2105 int ret; 2106 2107 port = &common->ports[port_idx]; 2108 2109 if (port->disabled) 2110 return 0; 2111 2112 /* alloc netdev */ 2113 port->ndev = devm_alloc_etherdev_mqs(common->dev, 2114 sizeof(struct am65_cpsw_ndev_priv), 2115 AM65_CPSW_MAX_TX_QUEUES, 2116 AM65_CPSW_MAX_RX_QUEUES); 2117 if (!port->ndev) { 2118 dev_err(dev, "error allocating slave net_device %u\n", 2119 port->port_id); 2120 return -ENOMEM; 2121 } 2122 2123 ndev_priv = netdev_priv(port->ndev); 2124 ndev_priv->port = port; 2125 ndev_priv->msg_enable = AM65_CPSW_DEBUG; 2126 SET_NETDEV_DEV(port->ndev, dev); 2127 2128 eth_hw_addr_set(port->ndev, port->slave.mac_addr); 2129 2130 port->ndev->min_mtu = AM65_CPSW_MIN_PACKET_SIZE; 2131 port->ndev->max_mtu = AM65_CPSW_MAX_PACKET_SIZE; 2132 port->ndev->hw_features = NETIF_F_SG | 2133 NETIF_F_RXCSUM | 2134 NETIF_F_HW_CSUM | 2135 NETIF_F_HW_TC; 2136 port->ndev->features = port->ndev->hw_features | 2137 NETIF_F_HW_VLAN_CTAG_FILTER; 2138 port->ndev->vlan_features |= NETIF_F_SG; 2139 port->ndev->netdev_ops = &am65_cpsw_nuss_netdev_ops; 2140 port->ndev->ethtool_ops = &am65_cpsw_ethtool_ops_slave; 2141 2142 /* Configuring Phylink */ 2143 port->slave.phylink_config.dev = &port->ndev->dev; 2144 port->slave.phylink_config.type = PHYLINK_NETDEV; 2145 port->slave.phylink_config.mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 | MAC_1000FD; 2146 port->slave.phylink_config.mac_managed_pm = true; /* MAC does PM */ 2147 2148 if (phy_interface_mode_is_rgmii(port->slave.phy_if)) { 2149 phy_interface_set_rgmii(port->slave.phylink_config.supported_interfaces); 2150 } else if (port->slave.phy_if == PHY_INTERFACE_MODE_RMII) { 2151 __set_bit(PHY_INTERFACE_MODE_RMII, 2152 port->slave.phylink_config.supported_interfaces); 2153 } else if (common->pdata.extra_modes & BIT(port->slave.phy_if)) { 2154 __set_bit(PHY_INTERFACE_MODE_QSGMII, 2155 port->slave.phylink_config.supported_interfaces); 2156 } else { 2157 dev_err(dev, "selected phy-mode is not supported\n"); 2158 return -EOPNOTSUPP; 2159 } 2160 2161 phylink = phylink_create(&port->slave.phylink_config, 2162 of_node_to_fwnode(port->slave.phy_node), 2163 port->slave.phy_if, 2164 &am65_cpsw_phylink_mac_ops); 2165 if (IS_ERR(phylink)) 2166 return PTR_ERR(phylink); 2167 2168 port->slave.phylink = phylink; 2169 2170 /* Disable TX checksum offload by default due to HW bug */ 2171 if (common->pdata.quirks & AM65_CPSW_QUIRK_I2027_NO_TX_CSUM) 2172 port->ndev->features &= ~NETIF_F_HW_CSUM; 2173 2174 ndev_priv->stats = netdev_alloc_pcpu_stats(struct am65_cpsw_ndev_stats); 2175 if (!ndev_priv->stats) 2176 return -ENOMEM; 2177 2178 ret = devm_add_action_or_reset(dev, am65_cpsw_pcpu_stats_free, 2179 ndev_priv->stats); 2180 if (ret) 2181 dev_err(dev, "failed to add percpu stat free action %d\n", ret); 2182 2183 if (!common->dma_ndev) 2184 common->dma_ndev = port->ndev; 2185 2186 return ret; 2187 } 2188 2189 static int am65_cpsw_nuss_init_ndevs(struct am65_cpsw_common *common) 2190 { 2191 int ret; 2192 int i; 2193 2194 for (i = 0; i < common->port_num; i++) { 2195 ret = am65_cpsw_nuss_init_port_ndev(common, i); 2196 if (ret) 2197 return ret; 2198 } 2199 2200 return ret; 2201 } 2202 2203 static void am65_cpsw_nuss_cleanup_ndev(struct am65_cpsw_common *common) 2204 { 2205 struct am65_cpsw_port *port; 2206 int i; 2207 2208 for (i = 0; i < common->port_num; i++) { 2209 port = &common->ports[i]; 2210 if (port->ndev && port->ndev->reg_state == NETREG_REGISTERED) 2211 unregister_netdev(port->ndev); 2212 } 2213 } 2214 2215 static void am65_cpsw_port_offload_fwd_mark_update(struct am65_cpsw_common *common) 2216 { 2217 int set_val = 0; 2218 int i; 2219 2220 if (common->br_members == (GENMASK(common->port_num, 1) & ~common->disabled_ports_mask)) 2221 set_val = 1; 2222 2223 dev_dbg(common->dev, "set offload_fwd_mark %d\n", set_val); 2224 2225 for (i = 1; i <= common->port_num; i++) { 2226 struct am65_cpsw_port *port = am65_common_get_port(common, i); 2227 struct am65_cpsw_ndev_priv *priv; 2228 2229 if (!port->ndev) 2230 continue; 2231 2232 priv = am65_ndev_to_priv(port->ndev); 2233 priv->offload_fwd_mark = set_val; 2234 } 2235 } 2236 2237 bool am65_cpsw_port_dev_check(const struct net_device *ndev) 2238 { 2239 if (ndev->netdev_ops == &am65_cpsw_nuss_netdev_ops) { 2240 struct am65_cpsw_common *common = am65_ndev_to_common(ndev); 2241 2242 return !common->is_emac_mode; 2243 } 2244 2245 return false; 2246 } 2247 2248 static int am65_cpsw_netdevice_port_link(struct net_device *ndev, 2249 struct net_device *br_ndev, 2250 struct netlink_ext_ack *extack) 2251 { 2252 struct am65_cpsw_common *common = am65_ndev_to_common(ndev); 2253 struct am65_cpsw_ndev_priv *priv = am65_ndev_to_priv(ndev); 2254 int err; 2255 2256 if (!common->br_members) { 2257 common->hw_bridge_dev = br_ndev; 2258 } else { 2259 /* This is adding the port to a second bridge, this is 2260 * unsupported 2261 */ 2262 if (common->hw_bridge_dev != br_ndev) 2263 return -EOPNOTSUPP; 2264 } 2265 2266 err = switchdev_bridge_port_offload(ndev, ndev, NULL, NULL, NULL, 2267 false, extack); 2268 if (err) 2269 return err; 2270 2271 common->br_members |= BIT(priv->port->port_id); 2272 2273 am65_cpsw_port_offload_fwd_mark_update(common); 2274 2275 return NOTIFY_DONE; 2276 } 2277 2278 static void am65_cpsw_netdevice_port_unlink(struct net_device *ndev) 2279 { 2280 struct am65_cpsw_common *common = am65_ndev_to_common(ndev); 2281 struct am65_cpsw_ndev_priv *priv = am65_ndev_to_priv(ndev); 2282 2283 switchdev_bridge_port_unoffload(ndev, NULL, NULL, NULL); 2284 2285 common->br_members &= ~BIT(priv->port->port_id); 2286 2287 am65_cpsw_port_offload_fwd_mark_update(common); 2288 2289 if (!common->br_members) 2290 common->hw_bridge_dev = NULL; 2291 } 2292 2293 /* netdev notifier */ 2294 static int am65_cpsw_netdevice_event(struct notifier_block *unused, 2295 unsigned long event, void *ptr) 2296 { 2297 struct netlink_ext_ack *extack = netdev_notifier_info_to_extack(ptr); 2298 struct net_device *ndev = netdev_notifier_info_to_dev(ptr); 2299 struct netdev_notifier_changeupper_info *info; 2300 int ret = NOTIFY_DONE; 2301 2302 if (!am65_cpsw_port_dev_check(ndev)) 2303 return NOTIFY_DONE; 2304 2305 switch (event) { 2306 case NETDEV_CHANGEUPPER: 2307 info = ptr; 2308 2309 if (netif_is_bridge_master(info->upper_dev)) { 2310 if (info->linking) 2311 ret = am65_cpsw_netdevice_port_link(ndev, 2312 info->upper_dev, 2313 extack); 2314 else 2315 am65_cpsw_netdevice_port_unlink(ndev); 2316 } 2317 break; 2318 default: 2319 return NOTIFY_DONE; 2320 } 2321 2322 return notifier_from_errno(ret); 2323 } 2324 2325 static int am65_cpsw_register_notifiers(struct am65_cpsw_common *cpsw) 2326 { 2327 int ret = 0; 2328 2329 if (AM65_CPSW_IS_CPSW2G(cpsw) || 2330 !IS_REACHABLE(CONFIG_TI_K3_AM65_CPSW_SWITCHDEV)) 2331 return 0; 2332 2333 cpsw->am65_cpsw_netdevice_nb.notifier_call = &am65_cpsw_netdevice_event; 2334 ret = register_netdevice_notifier(&cpsw->am65_cpsw_netdevice_nb); 2335 if (ret) { 2336 dev_err(cpsw->dev, "can't register netdevice notifier\n"); 2337 return ret; 2338 } 2339 2340 ret = am65_cpsw_switchdev_register_notifiers(cpsw); 2341 if (ret) 2342 unregister_netdevice_notifier(&cpsw->am65_cpsw_netdevice_nb); 2343 2344 return ret; 2345 } 2346 2347 static void am65_cpsw_unregister_notifiers(struct am65_cpsw_common *cpsw) 2348 { 2349 if (AM65_CPSW_IS_CPSW2G(cpsw) || 2350 !IS_REACHABLE(CONFIG_TI_K3_AM65_CPSW_SWITCHDEV)) 2351 return; 2352 2353 am65_cpsw_switchdev_unregister_notifiers(cpsw); 2354 unregister_netdevice_notifier(&cpsw->am65_cpsw_netdevice_nb); 2355 } 2356 2357 static const struct devlink_ops am65_cpsw_devlink_ops = {}; 2358 2359 static void am65_cpsw_init_stp_ale_entry(struct am65_cpsw_common *cpsw) 2360 { 2361 cpsw_ale_add_mcast(cpsw->ale, eth_stp_addr, ALE_PORT_HOST, ALE_SUPER, 0, 2362 ALE_MCAST_BLOCK_LEARN_FWD); 2363 } 2364 2365 static void am65_cpsw_init_host_port_switch(struct am65_cpsw_common *common) 2366 { 2367 struct am65_cpsw_host *host = am65_common_get_host(common); 2368 2369 writel(common->default_vlan, host->port_base + AM65_CPSW_PORT_VLAN_REG_OFFSET); 2370 2371 am65_cpsw_init_stp_ale_entry(common); 2372 2373 cpsw_ale_control_set(common->ale, HOST_PORT_NUM, ALE_P0_UNI_FLOOD, 1); 2374 dev_dbg(common->dev, "Set P0_UNI_FLOOD\n"); 2375 cpsw_ale_control_set(common->ale, HOST_PORT_NUM, ALE_PORT_NOLEARN, 0); 2376 } 2377 2378 static void am65_cpsw_init_host_port_emac(struct am65_cpsw_common *common) 2379 { 2380 struct am65_cpsw_host *host = am65_common_get_host(common); 2381 2382 writel(0, host->port_base + AM65_CPSW_PORT_VLAN_REG_OFFSET); 2383 2384 cpsw_ale_control_set(common->ale, HOST_PORT_NUM, ALE_P0_UNI_FLOOD, 0); 2385 dev_dbg(common->dev, "unset P0_UNI_FLOOD\n"); 2386 2387 /* learning make no sense in multi-mac mode */ 2388 cpsw_ale_control_set(common->ale, HOST_PORT_NUM, ALE_PORT_NOLEARN, 1); 2389 } 2390 2391 static int am65_cpsw_dl_switch_mode_get(struct devlink *dl, u32 id, 2392 struct devlink_param_gset_ctx *ctx) 2393 { 2394 struct am65_cpsw_devlink *dl_priv = devlink_priv(dl); 2395 struct am65_cpsw_common *common = dl_priv->common; 2396 2397 dev_dbg(common->dev, "%s id:%u\n", __func__, id); 2398 2399 if (id != AM65_CPSW_DL_PARAM_SWITCH_MODE) 2400 return -EOPNOTSUPP; 2401 2402 ctx->val.vbool = !common->is_emac_mode; 2403 2404 return 0; 2405 } 2406 2407 static void am65_cpsw_init_port_emac_ale(struct am65_cpsw_port *port) 2408 { 2409 struct am65_cpsw_slave_data *slave = &port->slave; 2410 struct am65_cpsw_common *common = port->common; 2411 u32 port_mask; 2412 2413 writel(slave->port_vlan, port->port_base + AM65_CPSW_PORT_VLAN_REG_OFFSET); 2414 2415 if (slave->mac_only) 2416 /* enable mac-only mode on port */ 2417 cpsw_ale_control_set(common->ale, port->port_id, 2418 ALE_PORT_MACONLY, 1); 2419 2420 cpsw_ale_control_set(common->ale, port->port_id, ALE_PORT_NOLEARN, 1); 2421 2422 port_mask = BIT(port->port_id) | ALE_PORT_HOST; 2423 2424 cpsw_ale_add_ucast(common->ale, port->ndev->dev_addr, 2425 HOST_PORT_NUM, ALE_SECURE, slave->port_vlan); 2426 cpsw_ale_add_mcast(common->ale, port->ndev->broadcast, 2427 port_mask, ALE_VLAN, slave->port_vlan, ALE_MCAST_FWD_2); 2428 } 2429 2430 static void am65_cpsw_init_port_switch_ale(struct am65_cpsw_port *port) 2431 { 2432 struct am65_cpsw_slave_data *slave = &port->slave; 2433 struct am65_cpsw_common *cpsw = port->common; 2434 u32 port_mask; 2435 2436 cpsw_ale_control_set(cpsw->ale, port->port_id, 2437 ALE_PORT_NOLEARN, 0); 2438 2439 cpsw_ale_add_ucast(cpsw->ale, port->ndev->dev_addr, 2440 HOST_PORT_NUM, ALE_SECURE | ALE_BLOCKED | ALE_VLAN, 2441 slave->port_vlan); 2442 2443 port_mask = BIT(port->port_id) | ALE_PORT_HOST; 2444 2445 cpsw_ale_add_mcast(cpsw->ale, port->ndev->broadcast, 2446 port_mask, ALE_VLAN, slave->port_vlan, 2447 ALE_MCAST_FWD_2); 2448 2449 writel(slave->port_vlan, port->port_base + AM65_CPSW_PORT_VLAN_REG_OFFSET); 2450 2451 cpsw_ale_control_set(cpsw->ale, port->port_id, 2452 ALE_PORT_MACONLY, 0); 2453 } 2454 2455 static int am65_cpsw_dl_switch_mode_set(struct devlink *dl, u32 id, 2456 struct devlink_param_gset_ctx *ctx) 2457 { 2458 struct am65_cpsw_devlink *dl_priv = devlink_priv(dl); 2459 struct am65_cpsw_common *cpsw = dl_priv->common; 2460 bool switch_en = ctx->val.vbool; 2461 bool if_running = false; 2462 int i; 2463 2464 dev_dbg(cpsw->dev, "%s id:%u\n", __func__, id); 2465 2466 if (id != AM65_CPSW_DL_PARAM_SWITCH_MODE) 2467 return -EOPNOTSUPP; 2468 2469 if (switch_en == !cpsw->is_emac_mode) 2470 return 0; 2471 2472 if (!switch_en && cpsw->br_members) { 2473 dev_err(cpsw->dev, "Remove ports from bridge before disabling switch mode\n"); 2474 return -EINVAL; 2475 } 2476 2477 rtnl_lock(); 2478 2479 cpsw->is_emac_mode = !switch_en; 2480 2481 for (i = 0; i < cpsw->port_num; i++) { 2482 struct net_device *sl_ndev = cpsw->ports[i].ndev; 2483 2484 if (!sl_ndev || !netif_running(sl_ndev)) 2485 continue; 2486 2487 if_running = true; 2488 } 2489 2490 if (!if_running) { 2491 /* all ndevs are down */ 2492 for (i = 0; i < cpsw->port_num; i++) { 2493 struct net_device *sl_ndev = cpsw->ports[i].ndev; 2494 struct am65_cpsw_slave_data *slave; 2495 2496 if (!sl_ndev) 2497 continue; 2498 2499 slave = am65_ndev_to_slave(sl_ndev); 2500 if (switch_en) 2501 slave->port_vlan = cpsw->default_vlan; 2502 else 2503 slave->port_vlan = 0; 2504 } 2505 2506 goto exit; 2507 } 2508 2509 cpsw_ale_control_set(cpsw->ale, 0, ALE_BYPASS, 1); 2510 /* clean up ALE table */ 2511 cpsw_ale_control_set(cpsw->ale, HOST_PORT_NUM, ALE_CLEAR, 1); 2512 cpsw_ale_control_get(cpsw->ale, HOST_PORT_NUM, ALE_AGEOUT); 2513 2514 if (switch_en) { 2515 dev_info(cpsw->dev, "Enable switch mode\n"); 2516 2517 am65_cpsw_init_host_port_switch(cpsw); 2518 2519 for (i = 0; i < cpsw->port_num; i++) { 2520 struct net_device *sl_ndev = cpsw->ports[i].ndev; 2521 struct am65_cpsw_slave_data *slave; 2522 struct am65_cpsw_port *port; 2523 2524 if (!sl_ndev) 2525 continue; 2526 2527 port = am65_ndev_to_port(sl_ndev); 2528 slave = am65_ndev_to_slave(sl_ndev); 2529 slave->port_vlan = cpsw->default_vlan; 2530 2531 if (netif_running(sl_ndev)) 2532 am65_cpsw_init_port_switch_ale(port); 2533 } 2534 2535 } else { 2536 dev_info(cpsw->dev, "Disable switch mode\n"); 2537 2538 am65_cpsw_init_host_port_emac(cpsw); 2539 2540 for (i = 0; i < cpsw->port_num; i++) { 2541 struct net_device *sl_ndev = cpsw->ports[i].ndev; 2542 struct am65_cpsw_port *port; 2543 2544 if (!sl_ndev) 2545 continue; 2546 2547 port = am65_ndev_to_port(sl_ndev); 2548 port->slave.port_vlan = 0; 2549 if (netif_running(sl_ndev)) 2550 am65_cpsw_init_port_emac_ale(port); 2551 } 2552 } 2553 cpsw_ale_control_set(cpsw->ale, HOST_PORT_NUM, ALE_BYPASS, 0); 2554 exit: 2555 rtnl_unlock(); 2556 2557 return 0; 2558 } 2559 2560 static const struct devlink_param am65_cpsw_devlink_params[] = { 2561 DEVLINK_PARAM_DRIVER(AM65_CPSW_DL_PARAM_SWITCH_MODE, "switch_mode", 2562 DEVLINK_PARAM_TYPE_BOOL, 2563 BIT(DEVLINK_PARAM_CMODE_RUNTIME), 2564 am65_cpsw_dl_switch_mode_get, 2565 am65_cpsw_dl_switch_mode_set, NULL), 2566 }; 2567 2568 static int am65_cpsw_nuss_register_devlink(struct am65_cpsw_common *common) 2569 { 2570 struct devlink_port_attrs attrs = {}; 2571 struct am65_cpsw_devlink *dl_priv; 2572 struct device *dev = common->dev; 2573 struct devlink_port *dl_port; 2574 struct am65_cpsw_port *port; 2575 int ret = 0; 2576 int i; 2577 2578 common->devlink = 2579 devlink_alloc(&am65_cpsw_devlink_ops, sizeof(*dl_priv), dev); 2580 if (!common->devlink) 2581 return -ENOMEM; 2582 2583 dl_priv = devlink_priv(common->devlink); 2584 dl_priv->common = common; 2585 2586 /* Provide devlink hook to switch mode when multiple external ports 2587 * are present NUSS switchdev driver is enabled. 2588 */ 2589 if (!AM65_CPSW_IS_CPSW2G(common) && 2590 IS_ENABLED(CONFIG_TI_K3_AM65_CPSW_SWITCHDEV)) { 2591 ret = devlink_params_register(common->devlink, 2592 am65_cpsw_devlink_params, 2593 ARRAY_SIZE(am65_cpsw_devlink_params)); 2594 if (ret) { 2595 dev_err(dev, "devlink params reg fail ret:%d\n", ret); 2596 goto dl_unreg; 2597 } 2598 } 2599 2600 for (i = 1; i <= common->port_num; i++) { 2601 port = am65_common_get_port(common, i); 2602 dl_port = &port->devlink_port; 2603 2604 if (port->ndev) 2605 attrs.flavour = DEVLINK_PORT_FLAVOUR_PHYSICAL; 2606 else 2607 attrs.flavour = DEVLINK_PORT_FLAVOUR_UNUSED; 2608 attrs.phys.port_number = port->port_id; 2609 attrs.switch_id.id_len = sizeof(resource_size_t); 2610 memcpy(attrs.switch_id.id, common->switch_id, attrs.switch_id.id_len); 2611 devlink_port_attrs_set(dl_port, &attrs); 2612 2613 ret = devlink_port_register(common->devlink, dl_port, port->port_id); 2614 if (ret) { 2615 dev_err(dev, "devlink_port reg fail for port %d, ret:%d\n", 2616 port->port_id, ret); 2617 goto dl_port_unreg; 2618 } 2619 } 2620 devlink_register(common->devlink); 2621 return ret; 2622 2623 dl_port_unreg: 2624 for (i = i - 1; i >= 1; i--) { 2625 port = am65_common_get_port(common, i); 2626 dl_port = &port->devlink_port; 2627 2628 devlink_port_unregister(dl_port); 2629 } 2630 dl_unreg: 2631 devlink_free(common->devlink); 2632 return ret; 2633 } 2634 2635 static void am65_cpsw_unregister_devlink(struct am65_cpsw_common *common) 2636 { 2637 struct devlink_port *dl_port; 2638 struct am65_cpsw_port *port; 2639 int i; 2640 2641 devlink_unregister(common->devlink); 2642 2643 for (i = 1; i <= common->port_num; i++) { 2644 port = am65_common_get_port(common, i); 2645 dl_port = &port->devlink_port; 2646 2647 devlink_port_unregister(dl_port); 2648 } 2649 2650 if (!AM65_CPSW_IS_CPSW2G(common) && 2651 IS_ENABLED(CONFIG_TI_K3_AM65_CPSW_SWITCHDEV)) 2652 devlink_params_unregister(common->devlink, 2653 am65_cpsw_devlink_params, 2654 ARRAY_SIZE(am65_cpsw_devlink_params)); 2655 2656 devlink_free(common->devlink); 2657 } 2658 2659 static int am65_cpsw_nuss_register_ndevs(struct am65_cpsw_common *common) 2660 { 2661 struct device *dev = common->dev; 2662 struct am65_cpsw_port *port; 2663 int ret = 0, i; 2664 2665 /* init tx channels */ 2666 ret = am65_cpsw_nuss_init_tx_chns(common); 2667 if (ret) 2668 return ret; 2669 ret = am65_cpsw_nuss_init_rx_chns(common); 2670 if (ret) 2671 return ret; 2672 2673 ret = am65_cpsw_nuss_register_devlink(common); 2674 if (ret) 2675 return ret; 2676 2677 for (i = 0; i < common->port_num; i++) { 2678 port = &common->ports[i]; 2679 2680 if (!port->ndev) 2681 continue; 2682 2683 SET_NETDEV_DEVLINK_PORT(port->ndev, &port->devlink_port); 2684 2685 ret = register_netdev(port->ndev); 2686 if (ret) { 2687 dev_err(dev, "error registering slave net device%i %d\n", 2688 i, ret); 2689 goto err_cleanup_ndev; 2690 } 2691 } 2692 2693 ret = am65_cpsw_register_notifiers(common); 2694 if (ret) 2695 goto err_cleanup_ndev; 2696 2697 /* can't auto unregister ndev using devm_add_action() due to 2698 * devres release sequence in DD core for DMA 2699 */ 2700 2701 return 0; 2702 2703 err_cleanup_ndev: 2704 am65_cpsw_nuss_cleanup_ndev(common); 2705 am65_cpsw_unregister_devlink(common); 2706 2707 return ret; 2708 } 2709 2710 int am65_cpsw_nuss_update_tx_chns(struct am65_cpsw_common *common, int num_tx) 2711 { 2712 int ret; 2713 2714 common->tx_ch_num = num_tx; 2715 ret = am65_cpsw_nuss_init_tx_chns(common); 2716 2717 return ret; 2718 } 2719 2720 struct am65_cpsw_soc_pdata { 2721 u32 quirks_dis; 2722 }; 2723 2724 static const struct am65_cpsw_soc_pdata am65x_soc_sr2_0 = { 2725 .quirks_dis = AM65_CPSW_QUIRK_I2027_NO_TX_CSUM, 2726 }; 2727 2728 static const struct soc_device_attribute am65_cpsw_socinfo[] = { 2729 { .family = "AM65X", 2730 .revision = "SR2.0", 2731 .data = &am65x_soc_sr2_0 2732 }, 2733 {/* sentinel */} 2734 }; 2735 2736 static const struct am65_cpsw_pdata am65x_sr1_0 = { 2737 .quirks = AM65_CPSW_QUIRK_I2027_NO_TX_CSUM, 2738 .ale_dev_id = "am65x-cpsw2g", 2739 .fdqring_mode = K3_RINGACC_RING_MODE_MESSAGE, 2740 }; 2741 2742 static const struct am65_cpsw_pdata j721e_pdata = { 2743 .quirks = 0, 2744 .ale_dev_id = "am65x-cpsw2g", 2745 .fdqring_mode = K3_RINGACC_RING_MODE_MESSAGE, 2746 }; 2747 2748 static const struct am65_cpsw_pdata am64x_cpswxg_pdata = { 2749 .quirks = AM64_CPSW_QUIRK_DMA_RX_TDOWN_IRQ, 2750 .ale_dev_id = "am64-cpswxg", 2751 .fdqring_mode = K3_RINGACC_RING_MODE_RING, 2752 }; 2753 2754 static const struct am65_cpsw_pdata j7200_cpswxg_pdata = { 2755 .quirks = 0, 2756 .ale_dev_id = "am64-cpswxg", 2757 .fdqring_mode = K3_RINGACC_RING_MODE_RING, 2758 .extra_modes = BIT(PHY_INTERFACE_MODE_QSGMII), 2759 }; 2760 2761 static const struct am65_cpsw_pdata j721e_cpswxg_pdata = { 2762 .quirks = 0, 2763 .ale_dev_id = "am64-cpswxg", 2764 .fdqring_mode = K3_RINGACC_RING_MODE_MESSAGE, 2765 .extra_modes = BIT(PHY_INTERFACE_MODE_QSGMII), 2766 }; 2767 2768 static const struct of_device_id am65_cpsw_nuss_of_mtable[] = { 2769 { .compatible = "ti,am654-cpsw-nuss", .data = &am65x_sr1_0}, 2770 { .compatible = "ti,j721e-cpsw-nuss", .data = &j721e_pdata}, 2771 { .compatible = "ti,am642-cpsw-nuss", .data = &am64x_cpswxg_pdata}, 2772 { .compatible = "ti,j7200-cpswxg-nuss", .data = &j7200_cpswxg_pdata}, 2773 { .compatible = "ti,j721e-cpswxg-nuss", .data = &j721e_cpswxg_pdata}, 2774 { /* sentinel */ }, 2775 }; 2776 MODULE_DEVICE_TABLE(of, am65_cpsw_nuss_of_mtable); 2777 2778 static void am65_cpsw_nuss_apply_socinfo(struct am65_cpsw_common *common) 2779 { 2780 const struct soc_device_attribute *soc; 2781 2782 soc = soc_device_match(am65_cpsw_socinfo); 2783 if (soc && soc->data) { 2784 const struct am65_cpsw_soc_pdata *socdata = soc->data; 2785 2786 /* disable quirks */ 2787 common->pdata.quirks &= ~socdata->quirks_dis; 2788 } 2789 } 2790 2791 static int am65_cpsw_nuss_probe(struct platform_device *pdev) 2792 { 2793 struct cpsw_ale_params ale_params = { 0 }; 2794 const struct of_device_id *of_id; 2795 struct device *dev = &pdev->dev; 2796 struct am65_cpsw_common *common; 2797 struct device_node *node; 2798 struct resource *res; 2799 struct clk *clk; 2800 u64 id_temp; 2801 int ret, i; 2802 int ale_entries; 2803 2804 common = devm_kzalloc(dev, sizeof(struct am65_cpsw_common), GFP_KERNEL); 2805 if (!common) 2806 return -ENOMEM; 2807 common->dev = dev; 2808 2809 of_id = of_match_device(am65_cpsw_nuss_of_mtable, dev); 2810 if (!of_id) 2811 return -EINVAL; 2812 common->pdata = *(const struct am65_cpsw_pdata *)of_id->data; 2813 2814 am65_cpsw_nuss_apply_socinfo(common); 2815 2816 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cpsw_nuss"); 2817 common->ss_base = devm_ioremap_resource(&pdev->dev, res); 2818 if (IS_ERR(common->ss_base)) 2819 return PTR_ERR(common->ss_base); 2820 common->cpsw_base = common->ss_base + AM65_CPSW_CPSW_NU_BASE; 2821 /* Use device's physical base address as switch id */ 2822 id_temp = cpu_to_be64(res->start); 2823 memcpy(common->switch_id, &id_temp, sizeof(res->start)); 2824 2825 node = of_get_child_by_name(dev->of_node, "ethernet-ports"); 2826 if (!node) 2827 return -ENOENT; 2828 common->port_num = of_get_child_count(node); 2829 of_node_put(node); 2830 if (common->port_num < 1 || common->port_num > AM65_CPSW_MAX_PORTS) 2831 return -ENOENT; 2832 2833 common->rx_flow_id_base = -1; 2834 init_completion(&common->tdown_complete); 2835 common->tx_ch_num = 1; 2836 common->pf_p0_rx_ptype_rrobin = false; 2837 common->default_vlan = 1; 2838 2839 common->ports = devm_kcalloc(dev, common->port_num, 2840 sizeof(*common->ports), 2841 GFP_KERNEL); 2842 if (!common->ports) 2843 return -ENOMEM; 2844 2845 clk = devm_clk_get(dev, "fck"); 2846 if (IS_ERR(clk)) 2847 return dev_err_probe(dev, PTR_ERR(clk), "getting fck clock\n"); 2848 common->bus_freq = clk_get_rate(clk); 2849 2850 pm_runtime_enable(dev); 2851 ret = pm_runtime_resume_and_get(dev); 2852 if (ret < 0) { 2853 pm_runtime_disable(dev); 2854 return ret; 2855 } 2856 2857 node = of_get_child_by_name(dev->of_node, "mdio"); 2858 if (!node) { 2859 dev_warn(dev, "MDIO node not found\n"); 2860 } else if (of_device_is_available(node)) { 2861 struct platform_device *mdio_pdev; 2862 2863 mdio_pdev = of_platform_device_create(node, NULL, dev); 2864 if (!mdio_pdev) { 2865 ret = -ENODEV; 2866 goto err_pm_clear; 2867 } 2868 2869 common->mdio_dev = &mdio_pdev->dev; 2870 } 2871 of_node_put(node); 2872 2873 am65_cpsw_nuss_get_ver(common); 2874 2875 ret = am65_cpsw_nuss_init_host_p(common); 2876 if (ret) 2877 goto err_of_clear; 2878 2879 ret = am65_cpsw_nuss_init_slave_ports(common); 2880 if (ret) 2881 goto err_of_clear; 2882 2883 /* init common data */ 2884 ale_params.dev = dev; 2885 ale_params.ale_ageout = AM65_CPSW_ALE_AGEOUT_DEFAULT; 2886 ale_params.ale_ports = common->port_num + 1; 2887 ale_params.ale_regs = common->cpsw_base + AM65_CPSW_NU_ALE_BASE; 2888 ale_params.dev_id = common->pdata.ale_dev_id; 2889 ale_params.bus_freq = common->bus_freq; 2890 2891 common->ale = cpsw_ale_create(&ale_params); 2892 if (IS_ERR(common->ale)) { 2893 dev_err(dev, "error initializing ale engine\n"); 2894 ret = PTR_ERR(common->ale); 2895 goto err_of_clear; 2896 } 2897 2898 ale_entries = common->ale->params.ale_entries; 2899 common->ale_context = devm_kzalloc(dev, 2900 ale_entries * ALE_ENTRY_WORDS * sizeof(u32), 2901 GFP_KERNEL); 2902 ret = am65_cpsw_init_cpts(common); 2903 if (ret) 2904 goto err_of_clear; 2905 2906 /* init ports */ 2907 for (i = 0; i < common->port_num; i++) 2908 am65_cpsw_nuss_slave_disable_unused(&common->ports[i]); 2909 2910 dev_set_drvdata(dev, common); 2911 2912 common->is_emac_mode = true; 2913 2914 ret = am65_cpsw_nuss_init_ndevs(common); 2915 if (ret) 2916 goto err_free_phylink; 2917 2918 ret = am65_cpsw_nuss_register_ndevs(common); 2919 if (ret) 2920 goto err_free_phylink; 2921 2922 pm_runtime_put(dev); 2923 return 0; 2924 2925 err_free_phylink: 2926 am65_cpsw_nuss_phylink_cleanup(common); 2927 am65_cpts_release(common->cpts); 2928 err_of_clear: 2929 of_platform_device_destroy(common->mdio_dev, NULL); 2930 err_pm_clear: 2931 pm_runtime_put_sync(dev); 2932 pm_runtime_disable(dev); 2933 return ret; 2934 } 2935 2936 static int am65_cpsw_nuss_remove(struct platform_device *pdev) 2937 { 2938 struct device *dev = &pdev->dev; 2939 struct am65_cpsw_common *common; 2940 int ret; 2941 2942 common = dev_get_drvdata(dev); 2943 2944 ret = pm_runtime_resume_and_get(&pdev->dev); 2945 if (ret < 0) 2946 return ret; 2947 2948 am65_cpsw_unregister_devlink(common); 2949 am65_cpsw_unregister_notifiers(common); 2950 2951 /* must unregister ndevs here because DD release_driver routine calls 2952 * dma_deconfigure(dev) before devres_release_all(dev) 2953 */ 2954 am65_cpsw_nuss_cleanup_ndev(common); 2955 am65_cpsw_nuss_phylink_cleanup(common); 2956 am65_cpts_release(common->cpts); 2957 am65_cpsw_disable_serdes_phy(common); 2958 2959 of_platform_device_destroy(common->mdio_dev, NULL); 2960 2961 pm_runtime_put_sync(&pdev->dev); 2962 pm_runtime_disable(&pdev->dev); 2963 return 0; 2964 } 2965 2966 static int am65_cpsw_nuss_suspend(struct device *dev) 2967 { 2968 struct am65_cpsw_common *common = dev_get_drvdata(dev); 2969 struct am65_cpsw_host *host_p = am65_common_get_host(common); 2970 struct am65_cpsw_port *port; 2971 struct net_device *ndev; 2972 int i, ret; 2973 2974 cpsw_ale_dump(common->ale, common->ale_context); 2975 host_p->vid_context = readl(host_p->port_base + AM65_CPSW_PORT_VLAN_REG_OFFSET); 2976 for (i = 0; i < common->port_num; i++) { 2977 port = &common->ports[i]; 2978 ndev = port->ndev; 2979 2980 if (!ndev) 2981 continue; 2982 2983 port->vid_context = readl(port->port_base + AM65_CPSW_PORT_VLAN_REG_OFFSET); 2984 netif_device_detach(ndev); 2985 if (netif_running(ndev)) { 2986 rtnl_lock(); 2987 ret = am65_cpsw_nuss_ndo_slave_stop(ndev); 2988 rtnl_unlock(); 2989 if (ret < 0) { 2990 netdev_err(ndev, "failed to stop: %d", ret); 2991 return ret; 2992 } 2993 } 2994 } 2995 2996 am65_cpts_suspend(common->cpts); 2997 2998 am65_cpsw_nuss_remove_rx_chns(common); 2999 am65_cpsw_nuss_remove_tx_chns(common); 3000 3001 return 0; 3002 } 3003 3004 static int am65_cpsw_nuss_resume(struct device *dev) 3005 { 3006 struct am65_cpsw_common *common = dev_get_drvdata(dev); 3007 struct am65_cpsw_port *port; 3008 struct net_device *ndev; 3009 int i, ret; 3010 struct am65_cpsw_host *host_p = am65_common_get_host(common); 3011 3012 ret = am65_cpsw_nuss_init_tx_chns(common); 3013 if (ret) 3014 return ret; 3015 ret = am65_cpsw_nuss_init_rx_chns(common); 3016 if (ret) 3017 return ret; 3018 3019 /* If RX IRQ was disabled before suspend, keep it disabled */ 3020 if (common->rx_irq_disabled) 3021 disable_irq(common->rx_chns.irq); 3022 3023 am65_cpts_resume(common->cpts); 3024 3025 for (i = 0; i < common->port_num; i++) { 3026 port = &common->ports[i]; 3027 ndev = port->ndev; 3028 3029 if (!ndev) 3030 continue; 3031 3032 if (netif_running(ndev)) { 3033 rtnl_lock(); 3034 ret = am65_cpsw_nuss_ndo_slave_open(ndev); 3035 rtnl_unlock(); 3036 if (ret < 0) { 3037 netdev_err(ndev, "failed to start: %d", ret); 3038 return ret; 3039 } 3040 } 3041 3042 netif_device_attach(ndev); 3043 writel(port->vid_context, port->port_base + AM65_CPSW_PORT_VLAN_REG_OFFSET); 3044 } 3045 3046 writel(host_p->vid_context, host_p->port_base + AM65_CPSW_PORT_VLAN_REG_OFFSET); 3047 cpsw_ale_restore(common->ale, common->ale_context); 3048 3049 return 0; 3050 } 3051 3052 static const struct dev_pm_ops am65_cpsw_nuss_dev_pm_ops = { 3053 SYSTEM_SLEEP_PM_OPS(am65_cpsw_nuss_suspend, am65_cpsw_nuss_resume) 3054 }; 3055 3056 static struct platform_driver am65_cpsw_nuss_driver = { 3057 .driver = { 3058 .name = AM65_CPSW_DRV_NAME, 3059 .of_match_table = am65_cpsw_nuss_of_mtable, 3060 .pm = &am65_cpsw_nuss_dev_pm_ops, 3061 }, 3062 .probe = am65_cpsw_nuss_probe, 3063 .remove = am65_cpsw_nuss_remove, 3064 }; 3065 3066 module_platform_driver(am65_cpsw_nuss_driver); 3067 3068 MODULE_LICENSE("GPL v2"); 3069 MODULE_AUTHOR("Grygorii Strashko <grygorii.strashko@ti.com>"); 3070 MODULE_DESCRIPTION("TI AM65 CPSW Ethernet driver"); 3071