1 // SPDX-License-Identifier: GPL-2.0 2 /* Texas Instruments K3 AM65 Ethernet Switch SubSystem Driver 3 * 4 * Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/ 5 * 6 */ 7 8 #include <linux/clk.h> 9 #include <linux/etherdevice.h> 10 #include <linux/if_vlan.h> 11 #include <linux/interrupt.h> 12 #include <linux/irqdomain.h> 13 #include <linux/kernel.h> 14 #include <linux/kmemleak.h> 15 #include <linux/module.h> 16 #include <linux/netdevice.h> 17 #include <linux/net_tstamp.h> 18 #include <linux/of.h> 19 #include <linux/of_mdio.h> 20 #include <linux/of_net.h> 21 #include <linux/of_device.h> 22 #include <linux/phylink.h> 23 #include <linux/phy/phy.h> 24 #include <linux/platform_device.h> 25 #include <linux/pm_runtime.h> 26 #include <linux/regmap.h> 27 #include <linux/mfd/syscon.h> 28 #include <linux/sys_soc.h> 29 #include <linux/dma/ti-cppi5.h> 30 #include <linux/dma/k3-udma-glue.h> 31 #include <net/switchdev.h> 32 33 #include "cpsw_ale.h" 34 #include "cpsw_sl.h" 35 #include "am65-cpsw-nuss.h" 36 #include "am65-cpsw-switchdev.h" 37 #include "k3-cppi-desc-pool.h" 38 #include "am65-cpts.h" 39 40 #define AM65_CPSW_SS_BASE 0x0 41 #define AM65_CPSW_SGMII_BASE 0x100 42 #define AM65_CPSW_XGMII_BASE 0x2100 43 #define AM65_CPSW_CPSW_NU_BASE 0x20000 44 #define AM65_CPSW_NU_PORTS_BASE 0x1000 45 #define AM65_CPSW_NU_FRAM_BASE 0x12000 46 #define AM65_CPSW_NU_STATS_BASE 0x1a000 47 #define AM65_CPSW_NU_ALE_BASE 0x1e000 48 #define AM65_CPSW_NU_CPTS_BASE 0x1d000 49 50 #define AM65_CPSW_NU_PORTS_OFFSET 0x1000 51 #define AM65_CPSW_NU_STATS_PORT_OFFSET 0x200 52 #define AM65_CPSW_NU_FRAM_PORT_OFFSET 0x200 53 54 #define AM65_CPSW_MAX_PORTS 8 55 56 #define AM65_CPSW_MIN_PACKET_SIZE VLAN_ETH_ZLEN 57 #define AM65_CPSW_MAX_PACKET_SIZE (VLAN_ETH_FRAME_LEN + ETH_FCS_LEN) 58 59 #define AM65_CPSW_REG_CTL 0x004 60 #define AM65_CPSW_REG_STAT_PORT_EN 0x014 61 #define AM65_CPSW_REG_PTYPE 0x018 62 63 #define AM65_CPSW_P0_REG_CTL 0x004 64 #define AM65_CPSW_PORT0_REG_FLOW_ID_OFFSET 0x008 65 66 #define AM65_CPSW_PORT_REG_PRI_CTL 0x01c 67 #define AM65_CPSW_PORT_REG_RX_PRI_MAP 0x020 68 #define AM65_CPSW_PORT_REG_RX_MAXLEN 0x024 69 70 #define AM65_CPSW_PORTN_REG_SA_L 0x308 71 #define AM65_CPSW_PORTN_REG_SA_H 0x30c 72 #define AM65_CPSW_PORTN_REG_TS_CTL 0x310 73 #define AM65_CPSW_PORTN_REG_TS_SEQ_LTYPE_REG 0x314 74 #define AM65_CPSW_PORTN_REG_TS_VLAN_LTYPE_REG 0x318 75 #define AM65_CPSW_PORTN_REG_TS_CTL_LTYPE2 0x31C 76 77 #define AM65_CPSW_SGMII_CONTROL_REG 0x010 78 #define AM65_CPSW_SGMII_CONTROL_MR_AN_ENABLE BIT(0) 79 80 #define AM65_CPSW_CTL_VLAN_AWARE BIT(1) 81 #define AM65_CPSW_CTL_P0_ENABLE BIT(2) 82 #define AM65_CPSW_CTL_P0_TX_CRC_REMOVE BIT(13) 83 #define AM65_CPSW_CTL_P0_RX_PAD BIT(14) 84 85 /* AM65_CPSW_P0_REG_CTL */ 86 #define AM65_CPSW_P0_REG_CTL_RX_CHECKSUM_EN BIT(0) 87 88 /* AM65_CPSW_PORT_REG_PRI_CTL */ 89 #define AM65_CPSW_PORT_REG_PRI_CTL_RX_PTYPE_RROBIN BIT(8) 90 91 /* AM65_CPSW_PN_TS_CTL register fields */ 92 #define AM65_CPSW_PN_TS_CTL_TX_ANX_F_EN BIT(4) 93 #define AM65_CPSW_PN_TS_CTL_TX_VLAN_LT1_EN BIT(5) 94 #define AM65_CPSW_PN_TS_CTL_TX_VLAN_LT2_EN BIT(6) 95 #define AM65_CPSW_PN_TS_CTL_TX_ANX_D_EN BIT(7) 96 #define AM65_CPSW_PN_TS_CTL_TX_ANX_E_EN BIT(10) 97 #define AM65_CPSW_PN_TS_CTL_TX_HOST_TS_EN BIT(11) 98 #define AM65_CPSW_PN_TS_CTL_MSG_TYPE_EN_SHIFT 16 99 100 /* AM65_CPSW_PORTN_REG_TS_SEQ_LTYPE_REG register fields */ 101 #define AM65_CPSW_PN_TS_SEQ_ID_OFFSET_SHIFT 16 102 103 /* AM65_CPSW_PORTN_REG_TS_CTL_LTYPE2 */ 104 #define AM65_CPSW_PN_TS_CTL_LTYPE2_TS_107 BIT(16) 105 #define AM65_CPSW_PN_TS_CTL_LTYPE2_TS_129 BIT(17) 106 #define AM65_CPSW_PN_TS_CTL_LTYPE2_TS_130 BIT(18) 107 #define AM65_CPSW_PN_TS_CTL_LTYPE2_TS_131 BIT(19) 108 #define AM65_CPSW_PN_TS_CTL_LTYPE2_TS_132 BIT(20) 109 #define AM65_CPSW_PN_TS_CTL_LTYPE2_TS_319 BIT(21) 110 #define AM65_CPSW_PN_TS_CTL_LTYPE2_TS_320 BIT(22) 111 #define AM65_CPSW_PN_TS_CTL_LTYPE2_TS_TTL_NONZERO BIT(23) 112 113 /* The PTP event messages - Sync, Delay_Req, Pdelay_Req, and Pdelay_Resp. */ 114 #define AM65_CPSW_TS_EVENT_MSG_TYPE_BITS (BIT(0) | BIT(1) | BIT(2) | BIT(3)) 115 116 #define AM65_CPSW_TS_SEQ_ID_OFFSET (0x1e) 117 118 #define AM65_CPSW_TS_TX_ANX_ALL_EN \ 119 (AM65_CPSW_PN_TS_CTL_TX_ANX_D_EN | \ 120 AM65_CPSW_PN_TS_CTL_TX_ANX_E_EN | \ 121 AM65_CPSW_PN_TS_CTL_TX_ANX_F_EN) 122 123 #define AM65_CPSW_ALE_AGEOUT_DEFAULT 30 124 /* Number of TX/RX descriptors */ 125 #define AM65_CPSW_MAX_TX_DESC 500 126 #define AM65_CPSW_MAX_RX_DESC 500 127 128 #define AM65_CPSW_NAV_PS_DATA_SIZE 16 129 #define AM65_CPSW_NAV_SW_DATA_SIZE 16 130 131 #define AM65_CPSW_DEBUG (NETIF_MSG_HW | NETIF_MSG_DRV | NETIF_MSG_LINK | \ 132 NETIF_MSG_IFUP | NETIF_MSG_PROBE | NETIF_MSG_IFDOWN | \ 133 NETIF_MSG_RX_ERR | NETIF_MSG_TX_ERR) 134 135 static void am65_cpsw_port_set_sl_mac(struct am65_cpsw_port *slave, 136 const u8 *dev_addr) 137 { 138 u32 mac_hi = (dev_addr[0] << 0) | (dev_addr[1] << 8) | 139 (dev_addr[2] << 16) | (dev_addr[3] << 24); 140 u32 mac_lo = (dev_addr[4] << 0) | (dev_addr[5] << 8); 141 142 writel(mac_hi, slave->port_base + AM65_CPSW_PORTN_REG_SA_H); 143 writel(mac_lo, slave->port_base + AM65_CPSW_PORTN_REG_SA_L); 144 } 145 146 static void am65_cpsw_sl_ctl_reset(struct am65_cpsw_port *port) 147 { 148 cpsw_sl_reset(port->slave.mac_sl, 100); 149 /* Max length register has to be restored after MAC SL reset */ 150 writel(AM65_CPSW_MAX_PACKET_SIZE, 151 port->port_base + AM65_CPSW_PORT_REG_RX_MAXLEN); 152 } 153 154 static void am65_cpsw_nuss_get_ver(struct am65_cpsw_common *common) 155 { 156 common->nuss_ver = readl(common->ss_base); 157 common->cpsw_ver = readl(common->cpsw_base); 158 dev_info(common->dev, 159 "initializing am65 cpsw nuss version 0x%08X, cpsw version 0x%08X Ports: %u quirks:%08x\n", 160 common->nuss_ver, 161 common->cpsw_ver, 162 common->port_num + 1, 163 common->pdata.quirks); 164 } 165 166 static int am65_cpsw_nuss_ndo_slave_add_vid(struct net_device *ndev, 167 __be16 proto, u16 vid) 168 { 169 struct am65_cpsw_common *common = am65_ndev_to_common(ndev); 170 struct am65_cpsw_port *port = am65_ndev_to_port(ndev); 171 u32 port_mask, unreg_mcast = 0; 172 int ret; 173 174 if (!common->is_emac_mode) 175 return 0; 176 177 if (!netif_running(ndev) || !vid) 178 return 0; 179 180 ret = pm_runtime_resume_and_get(common->dev); 181 if (ret < 0) 182 return ret; 183 184 port_mask = BIT(port->port_id) | ALE_PORT_HOST; 185 if (!vid) 186 unreg_mcast = port_mask; 187 dev_info(common->dev, "Adding vlan %d to vlan filter\n", vid); 188 ret = cpsw_ale_vlan_add_modify(common->ale, vid, port_mask, 189 unreg_mcast, port_mask, 0); 190 191 pm_runtime_put(common->dev); 192 return ret; 193 } 194 195 static int am65_cpsw_nuss_ndo_slave_kill_vid(struct net_device *ndev, 196 __be16 proto, u16 vid) 197 { 198 struct am65_cpsw_common *common = am65_ndev_to_common(ndev); 199 struct am65_cpsw_port *port = am65_ndev_to_port(ndev); 200 int ret; 201 202 if (!common->is_emac_mode) 203 return 0; 204 205 if (!netif_running(ndev) || !vid) 206 return 0; 207 208 ret = pm_runtime_resume_and_get(common->dev); 209 if (ret < 0) 210 return ret; 211 212 dev_info(common->dev, "Removing vlan %d from vlan filter\n", vid); 213 ret = cpsw_ale_del_vlan(common->ale, vid, 214 BIT(port->port_id) | ALE_PORT_HOST); 215 216 pm_runtime_put(common->dev); 217 return ret; 218 } 219 220 static void am65_cpsw_slave_set_promisc(struct am65_cpsw_port *port, 221 bool promisc) 222 { 223 struct am65_cpsw_common *common = port->common; 224 225 if (promisc && !common->is_emac_mode) { 226 dev_dbg(common->dev, "promisc mode requested in switch mode"); 227 return; 228 } 229 230 if (promisc) { 231 /* Enable promiscuous mode */ 232 cpsw_ale_control_set(common->ale, port->port_id, 233 ALE_PORT_MACONLY_CAF, 1); 234 dev_dbg(common->dev, "promisc enabled\n"); 235 } else { 236 /* Disable promiscuous mode */ 237 cpsw_ale_control_set(common->ale, port->port_id, 238 ALE_PORT_MACONLY_CAF, 0); 239 dev_dbg(common->dev, "promisc disabled\n"); 240 } 241 } 242 243 static void am65_cpsw_nuss_ndo_slave_set_rx_mode(struct net_device *ndev) 244 { 245 struct am65_cpsw_common *common = am65_ndev_to_common(ndev); 246 struct am65_cpsw_port *port = am65_ndev_to_port(ndev); 247 u32 port_mask; 248 bool promisc; 249 250 promisc = !!(ndev->flags & IFF_PROMISC); 251 am65_cpsw_slave_set_promisc(port, promisc); 252 253 if (promisc) 254 return; 255 256 /* Restore allmulti on vlans if necessary */ 257 cpsw_ale_set_allmulti(common->ale, 258 ndev->flags & IFF_ALLMULTI, port->port_id); 259 260 port_mask = ALE_PORT_HOST; 261 /* Clear all mcast from ALE */ 262 cpsw_ale_flush_multicast(common->ale, port_mask, -1); 263 264 if (!netdev_mc_empty(ndev)) { 265 struct netdev_hw_addr *ha; 266 267 /* program multicast address list into ALE register */ 268 netdev_for_each_mc_addr(ha, ndev) { 269 cpsw_ale_add_mcast(common->ale, ha->addr, 270 port_mask, 0, 0, 0); 271 } 272 } 273 } 274 275 static void am65_cpsw_nuss_ndo_host_tx_timeout(struct net_device *ndev, 276 unsigned int txqueue) 277 { 278 struct am65_cpsw_common *common = am65_ndev_to_common(ndev); 279 struct am65_cpsw_tx_chn *tx_chn; 280 struct netdev_queue *netif_txq; 281 unsigned long trans_start; 282 283 netif_txq = netdev_get_tx_queue(ndev, txqueue); 284 tx_chn = &common->tx_chns[txqueue]; 285 trans_start = READ_ONCE(netif_txq->trans_start); 286 287 netdev_err(ndev, "txq:%d DRV_XOFF:%d tmo:%u dql_avail:%d free_desc:%zu\n", 288 txqueue, 289 netif_tx_queue_stopped(netif_txq), 290 jiffies_to_msecs(jiffies - trans_start), 291 dql_avail(&netif_txq->dql), 292 k3_cppi_desc_pool_avail(tx_chn->desc_pool)); 293 294 if (netif_tx_queue_stopped(netif_txq)) { 295 /* try recover if stopped by us */ 296 txq_trans_update(netif_txq); 297 netif_tx_wake_queue(netif_txq); 298 } 299 } 300 301 static int am65_cpsw_nuss_rx_push(struct am65_cpsw_common *common, 302 struct sk_buff *skb) 303 { 304 struct am65_cpsw_rx_chn *rx_chn = &common->rx_chns; 305 struct cppi5_host_desc_t *desc_rx; 306 struct device *dev = common->dev; 307 u32 pkt_len = skb_tailroom(skb); 308 dma_addr_t desc_dma; 309 dma_addr_t buf_dma; 310 void *swdata; 311 312 desc_rx = k3_cppi_desc_pool_alloc(rx_chn->desc_pool); 313 if (!desc_rx) { 314 dev_err(dev, "Failed to allocate RXFDQ descriptor\n"); 315 return -ENOMEM; 316 } 317 desc_dma = k3_cppi_desc_pool_virt2dma(rx_chn->desc_pool, desc_rx); 318 319 buf_dma = dma_map_single(rx_chn->dma_dev, skb->data, pkt_len, 320 DMA_FROM_DEVICE); 321 if (unlikely(dma_mapping_error(rx_chn->dma_dev, buf_dma))) { 322 k3_cppi_desc_pool_free(rx_chn->desc_pool, desc_rx); 323 dev_err(dev, "Failed to map rx skb buffer\n"); 324 return -EINVAL; 325 } 326 327 cppi5_hdesc_init(desc_rx, CPPI5_INFO0_HDESC_EPIB_PRESENT, 328 AM65_CPSW_NAV_PS_DATA_SIZE); 329 k3_udma_glue_rx_dma_to_cppi5_addr(rx_chn->rx_chn, &buf_dma); 330 cppi5_hdesc_attach_buf(desc_rx, buf_dma, skb_tailroom(skb), buf_dma, skb_tailroom(skb)); 331 swdata = cppi5_hdesc_get_swdata(desc_rx); 332 *((void **)swdata) = skb; 333 334 return k3_udma_glue_push_rx_chn(rx_chn->rx_chn, 0, desc_rx, desc_dma); 335 } 336 337 void am65_cpsw_nuss_set_p0_ptype(struct am65_cpsw_common *common) 338 { 339 struct am65_cpsw_host *host_p = am65_common_get_host(common); 340 u32 val, pri_map; 341 342 /* P0 set Receive Priority Type */ 343 val = readl(host_p->port_base + AM65_CPSW_PORT_REG_PRI_CTL); 344 345 if (common->pf_p0_rx_ptype_rrobin) { 346 val |= AM65_CPSW_PORT_REG_PRI_CTL_RX_PTYPE_RROBIN; 347 /* Enet Ports fifos works in fixed priority mode only, so 348 * reset P0_Rx_Pri_Map so all packet will go in Enet fifo 0 349 */ 350 pri_map = 0x0; 351 } else { 352 val &= ~AM65_CPSW_PORT_REG_PRI_CTL_RX_PTYPE_RROBIN; 353 /* restore P0_Rx_Pri_Map */ 354 pri_map = 0x76543210; 355 } 356 357 writel(pri_map, host_p->port_base + AM65_CPSW_PORT_REG_RX_PRI_MAP); 358 writel(val, host_p->port_base + AM65_CPSW_PORT_REG_PRI_CTL); 359 } 360 361 static void am65_cpsw_init_host_port_switch(struct am65_cpsw_common *common); 362 static void am65_cpsw_init_host_port_emac(struct am65_cpsw_common *common); 363 static void am65_cpsw_init_port_switch_ale(struct am65_cpsw_port *port); 364 static void am65_cpsw_init_port_emac_ale(struct am65_cpsw_port *port); 365 366 static int am65_cpsw_nuss_common_open(struct am65_cpsw_common *common, 367 netdev_features_t features) 368 { 369 struct am65_cpsw_host *host_p = am65_common_get_host(common); 370 int port_idx, i, ret; 371 struct sk_buff *skb; 372 u32 val, port_mask; 373 374 if (common->usage_count) 375 return 0; 376 377 /* Control register */ 378 writel(AM65_CPSW_CTL_P0_ENABLE | AM65_CPSW_CTL_P0_TX_CRC_REMOVE | 379 AM65_CPSW_CTL_VLAN_AWARE | AM65_CPSW_CTL_P0_RX_PAD, 380 common->cpsw_base + AM65_CPSW_REG_CTL); 381 /* Max length register */ 382 writel(AM65_CPSW_MAX_PACKET_SIZE, 383 host_p->port_base + AM65_CPSW_PORT_REG_RX_MAXLEN); 384 /* set base flow_id */ 385 writel(common->rx_flow_id_base, 386 host_p->port_base + AM65_CPSW_PORT0_REG_FLOW_ID_OFFSET); 387 /* en tx crc offload */ 388 writel(AM65_CPSW_P0_REG_CTL_RX_CHECKSUM_EN, host_p->port_base + AM65_CPSW_P0_REG_CTL); 389 390 am65_cpsw_nuss_set_p0_ptype(common); 391 392 /* enable statistic */ 393 val = BIT(HOST_PORT_NUM); 394 for (port_idx = 0; port_idx < common->port_num; port_idx++) { 395 struct am65_cpsw_port *port = &common->ports[port_idx]; 396 397 if (!port->disabled) 398 val |= BIT(port->port_id); 399 } 400 writel(val, common->cpsw_base + AM65_CPSW_REG_STAT_PORT_EN); 401 402 /* disable priority elevation */ 403 writel(0, common->cpsw_base + AM65_CPSW_REG_PTYPE); 404 405 cpsw_ale_start(common->ale); 406 407 /* limit to one RX flow only */ 408 cpsw_ale_control_set(common->ale, HOST_PORT_NUM, 409 ALE_DEFAULT_THREAD_ID, 0); 410 cpsw_ale_control_set(common->ale, HOST_PORT_NUM, 411 ALE_DEFAULT_THREAD_ENABLE, 1); 412 /* switch to vlan unaware mode */ 413 cpsw_ale_control_set(common->ale, HOST_PORT_NUM, ALE_VLAN_AWARE, 1); 414 cpsw_ale_control_set(common->ale, HOST_PORT_NUM, 415 ALE_PORT_STATE, ALE_PORT_STATE_FORWARD); 416 417 /* default vlan cfg: create mask based on enabled ports */ 418 port_mask = GENMASK(common->port_num, 0) & 419 ~common->disabled_ports_mask; 420 421 cpsw_ale_add_vlan(common->ale, 0, port_mask, 422 port_mask, port_mask, 423 port_mask & ~ALE_PORT_HOST); 424 425 if (common->is_emac_mode) 426 am65_cpsw_init_host_port_emac(common); 427 else 428 am65_cpsw_init_host_port_switch(common); 429 430 for (i = 0; i < common->rx_chns.descs_num; i++) { 431 skb = __netdev_alloc_skb_ip_align(NULL, 432 AM65_CPSW_MAX_PACKET_SIZE, 433 GFP_KERNEL); 434 if (!skb) { 435 dev_err(common->dev, "cannot allocate skb\n"); 436 return -ENOMEM; 437 } 438 439 ret = am65_cpsw_nuss_rx_push(common, skb); 440 if (ret < 0) { 441 dev_err(common->dev, 442 "cannot submit skb to channel rx, error %d\n", 443 ret); 444 kfree_skb(skb); 445 return ret; 446 } 447 kmemleak_not_leak(skb); 448 } 449 k3_udma_glue_enable_rx_chn(common->rx_chns.rx_chn); 450 451 for (i = 0; i < common->tx_ch_num; i++) { 452 ret = k3_udma_glue_enable_tx_chn(common->tx_chns[i].tx_chn); 453 if (ret) 454 return ret; 455 napi_enable(&common->tx_chns[i].napi_tx); 456 } 457 458 napi_enable(&common->napi_rx); 459 if (common->rx_irq_disabled) { 460 common->rx_irq_disabled = false; 461 enable_irq(common->rx_chns.irq); 462 } 463 464 dev_dbg(common->dev, "cpsw_nuss started\n"); 465 return 0; 466 } 467 468 static void am65_cpsw_nuss_tx_cleanup(void *data, dma_addr_t desc_dma); 469 static void am65_cpsw_nuss_rx_cleanup(void *data, dma_addr_t desc_dma); 470 471 static int am65_cpsw_nuss_common_stop(struct am65_cpsw_common *common) 472 { 473 int i; 474 475 if (common->usage_count != 1) 476 return 0; 477 478 cpsw_ale_control_set(common->ale, HOST_PORT_NUM, 479 ALE_PORT_STATE, ALE_PORT_STATE_DISABLE); 480 481 /* shutdown tx channels */ 482 atomic_set(&common->tdown_cnt, common->tx_ch_num); 483 /* ensure new tdown_cnt value is visible */ 484 smp_mb__after_atomic(); 485 reinit_completion(&common->tdown_complete); 486 487 for (i = 0; i < common->tx_ch_num; i++) 488 k3_udma_glue_tdown_tx_chn(common->tx_chns[i].tx_chn, false); 489 490 i = wait_for_completion_timeout(&common->tdown_complete, 491 msecs_to_jiffies(1000)); 492 if (!i) 493 dev_err(common->dev, "tx timeout\n"); 494 for (i = 0; i < common->tx_ch_num; i++) 495 napi_disable(&common->tx_chns[i].napi_tx); 496 497 for (i = 0; i < common->tx_ch_num; i++) { 498 k3_udma_glue_reset_tx_chn(common->tx_chns[i].tx_chn, 499 &common->tx_chns[i], 500 am65_cpsw_nuss_tx_cleanup); 501 k3_udma_glue_disable_tx_chn(common->tx_chns[i].tx_chn); 502 } 503 504 k3_udma_glue_tdown_rx_chn(common->rx_chns.rx_chn, true); 505 napi_disable(&common->napi_rx); 506 507 for (i = 0; i < AM65_CPSW_MAX_RX_FLOWS; i++) 508 k3_udma_glue_reset_rx_chn(common->rx_chns.rx_chn, i, 509 &common->rx_chns, 510 am65_cpsw_nuss_rx_cleanup, !!i); 511 512 k3_udma_glue_disable_rx_chn(common->rx_chns.rx_chn); 513 514 cpsw_ale_stop(common->ale); 515 516 writel(0, common->cpsw_base + AM65_CPSW_REG_CTL); 517 writel(0, common->cpsw_base + AM65_CPSW_REG_STAT_PORT_EN); 518 519 dev_dbg(common->dev, "cpsw_nuss stopped\n"); 520 return 0; 521 } 522 523 static int am65_cpsw_nuss_ndo_slave_stop(struct net_device *ndev) 524 { 525 struct am65_cpsw_common *common = am65_ndev_to_common(ndev); 526 struct am65_cpsw_port *port = am65_ndev_to_port(ndev); 527 int ret; 528 529 phylink_stop(port->slave.phylink); 530 531 netif_tx_stop_all_queues(ndev); 532 533 phylink_disconnect_phy(port->slave.phylink); 534 535 ret = am65_cpsw_nuss_common_stop(common); 536 if (ret) 537 return ret; 538 539 common->usage_count--; 540 pm_runtime_put(common->dev); 541 return 0; 542 } 543 544 static int cpsw_restore_vlans(struct net_device *vdev, int vid, void *arg) 545 { 546 struct am65_cpsw_port *port = arg; 547 548 if (!vdev) 549 return 0; 550 551 return am65_cpsw_nuss_ndo_slave_add_vid(port->ndev, 0, vid); 552 } 553 554 static int am65_cpsw_nuss_ndo_slave_open(struct net_device *ndev) 555 { 556 struct am65_cpsw_common *common = am65_ndev_to_common(ndev); 557 struct am65_cpsw_port *port = am65_ndev_to_port(ndev); 558 int ret, i; 559 560 ret = pm_runtime_resume_and_get(common->dev); 561 if (ret < 0) 562 return ret; 563 564 /* Notify the stack of the actual queue counts. */ 565 ret = netif_set_real_num_tx_queues(ndev, common->tx_ch_num); 566 if (ret) { 567 dev_err(common->dev, "cannot set real number of tx queues\n"); 568 return ret; 569 } 570 571 ret = netif_set_real_num_rx_queues(ndev, AM65_CPSW_MAX_RX_QUEUES); 572 if (ret) { 573 dev_err(common->dev, "cannot set real number of rx queues\n"); 574 return ret; 575 } 576 577 for (i = 0; i < common->tx_ch_num; i++) 578 netdev_tx_reset_queue(netdev_get_tx_queue(ndev, i)); 579 580 ret = am65_cpsw_nuss_common_open(common, ndev->features); 581 if (ret) 582 return ret; 583 584 common->usage_count++; 585 586 am65_cpsw_port_set_sl_mac(port, ndev->dev_addr); 587 588 if (common->is_emac_mode) 589 am65_cpsw_init_port_emac_ale(port); 590 else 591 am65_cpsw_init_port_switch_ale(port); 592 593 /* mac_sl should be configured via phy-link interface */ 594 am65_cpsw_sl_ctl_reset(port); 595 596 ret = phylink_of_phy_connect(port->slave.phylink, port->slave.phy_node, 0); 597 if (ret) 598 goto error_cleanup; 599 600 /* restore vlan configurations */ 601 vlan_for_each(ndev, cpsw_restore_vlans, port); 602 603 phylink_start(port->slave.phylink); 604 605 return 0; 606 607 error_cleanup: 608 am65_cpsw_nuss_ndo_slave_stop(ndev); 609 return ret; 610 } 611 612 static void am65_cpsw_nuss_rx_cleanup(void *data, dma_addr_t desc_dma) 613 { 614 struct am65_cpsw_rx_chn *rx_chn = data; 615 struct cppi5_host_desc_t *desc_rx; 616 struct sk_buff *skb; 617 dma_addr_t buf_dma; 618 u32 buf_dma_len; 619 void **swdata; 620 621 desc_rx = k3_cppi_desc_pool_dma2virt(rx_chn->desc_pool, desc_dma); 622 swdata = cppi5_hdesc_get_swdata(desc_rx); 623 skb = *swdata; 624 cppi5_hdesc_get_obuf(desc_rx, &buf_dma, &buf_dma_len); 625 k3_udma_glue_rx_cppi5_to_dma_addr(rx_chn->rx_chn, &buf_dma); 626 627 dma_unmap_single(rx_chn->dma_dev, buf_dma, buf_dma_len, DMA_FROM_DEVICE); 628 k3_cppi_desc_pool_free(rx_chn->desc_pool, desc_rx); 629 630 dev_kfree_skb_any(skb); 631 } 632 633 static void am65_cpsw_nuss_rx_ts(struct sk_buff *skb, u32 *psdata) 634 { 635 struct skb_shared_hwtstamps *ssh; 636 u64 ns; 637 638 ns = ((u64)psdata[1] << 32) | psdata[0]; 639 640 ssh = skb_hwtstamps(skb); 641 memset(ssh, 0, sizeof(*ssh)); 642 ssh->hwtstamp = ns_to_ktime(ns); 643 } 644 645 /* RX psdata[2] word format - checksum information */ 646 #define AM65_CPSW_RX_PSD_CSUM_ADD GENMASK(15, 0) 647 #define AM65_CPSW_RX_PSD_CSUM_ERR BIT(16) 648 #define AM65_CPSW_RX_PSD_IS_FRAGMENT BIT(17) 649 #define AM65_CPSW_RX_PSD_IS_TCP BIT(18) 650 #define AM65_CPSW_RX_PSD_IPV6_VALID BIT(19) 651 #define AM65_CPSW_RX_PSD_IPV4_VALID BIT(20) 652 653 static void am65_cpsw_nuss_rx_csum(struct sk_buff *skb, u32 csum_info) 654 { 655 /* HW can verify IPv4/IPv6 TCP/UDP packets checksum 656 * csum information provides in psdata[2] word: 657 * AM65_CPSW_RX_PSD_CSUM_ERR bit - indicates csum error 658 * AM65_CPSW_RX_PSD_IPV6_VALID and AM65_CPSW_RX_PSD_IPV4_VALID 659 * bits - indicates IPv4/IPv6 packet 660 * AM65_CPSW_RX_PSD_IS_FRAGMENT bit - indicates fragmented packet 661 * AM65_CPSW_RX_PSD_CSUM_ADD has value 0xFFFF for non fragmented packets 662 * or csum value for fragmented packets if !AM65_CPSW_RX_PSD_CSUM_ERR 663 */ 664 skb_checksum_none_assert(skb); 665 666 if (unlikely(!(skb->dev->features & NETIF_F_RXCSUM))) 667 return; 668 669 if ((csum_info & (AM65_CPSW_RX_PSD_IPV6_VALID | 670 AM65_CPSW_RX_PSD_IPV4_VALID)) && 671 !(csum_info & AM65_CPSW_RX_PSD_CSUM_ERR)) { 672 /* csum for fragmented packets is unsupported */ 673 if (!(csum_info & AM65_CPSW_RX_PSD_IS_FRAGMENT)) 674 skb->ip_summed = CHECKSUM_UNNECESSARY; 675 } 676 } 677 678 static int am65_cpsw_nuss_rx_packets(struct am65_cpsw_common *common, 679 u32 flow_idx) 680 { 681 struct am65_cpsw_rx_chn *rx_chn = &common->rx_chns; 682 u32 buf_dma_len, pkt_len, port_id = 0, csum_info; 683 struct am65_cpsw_ndev_priv *ndev_priv; 684 struct am65_cpsw_ndev_stats *stats; 685 struct cppi5_host_desc_t *desc_rx; 686 struct device *dev = common->dev; 687 struct sk_buff *skb, *new_skb; 688 dma_addr_t desc_dma, buf_dma; 689 struct am65_cpsw_port *port; 690 struct net_device *ndev; 691 void **swdata; 692 u32 *psdata; 693 int ret = 0; 694 695 ret = k3_udma_glue_pop_rx_chn(rx_chn->rx_chn, flow_idx, &desc_dma); 696 if (ret) { 697 if (ret != -ENODATA) 698 dev_err(dev, "RX: pop chn fail %d\n", ret); 699 return ret; 700 } 701 702 if (cppi5_desc_is_tdcm(desc_dma)) { 703 dev_dbg(dev, "%s RX tdown flow: %u\n", __func__, flow_idx); 704 return 0; 705 } 706 707 desc_rx = k3_cppi_desc_pool_dma2virt(rx_chn->desc_pool, desc_dma); 708 dev_dbg(dev, "%s flow_idx: %u desc %pad\n", 709 __func__, flow_idx, &desc_dma); 710 711 swdata = cppi5_hdesc_get_swdata(desc_rx); 712 skb = *swdata; 713 cppi5_hdesc_get_obuf(desc_rx, &buf_dma, &buf_dma_len); 714 k3_udma_glue_rx_cppi5_to_dma_addr(rx_chn->rx_chn, &buf_dma); 715 pkt_len = cppi5_hdesc_get_pktlen(desc_rx); 716 cppi5_desc_get_tags_ids(&desc_rx->hdr, &port_id, NULL); 717 dev_dbg(dev, "%s rx port_id:%d\n", __func__, port_id); 718 port = am65_common_get_port(common, port_id); 719 ndev = port->ndev; 720 skb->dev = ndev; 721 722 psdata = cppi5_hdesc_get_psdata(desc_rx); 723 /* add RX timestamp */ 724 if (port->rx_ts_enabled) 725 am65_cpsw_nuss_rx_ts(skb, psdata); 726 csum_info = psdata[2]; 727 dev_dbg(dev, "%s rx csum_info:%#x\n", __func__, csum_info); 728 729 dma_unmap_single(rx_chn->dma_dev, buf_dma, buf_dma_len, DMA_FROM_DEVICE); 730 731 k3_cppi_desc_pool_free(rx_chn->desc_pool, desc_rx); 732 733 new_skb = netdev_alloc_skb_ip_align(ndev, AM65_CPSW_MAX_PACKET_SIZE); 734 if (new_skb) { 735 ndev_priv = netdev_priv(ndev); 736 am65_cpsw_nuss_set_offload_fwd_mark(skb, ndev_priv->offload_fwd_mark); 737 skb_put(skb, pkt_len); 738 skb->protocol = eth_type_trans(skb, ndev); 739 am65_cpsw_nuss_rx_csum(skb, csum_info); 740 napi_gro_receive(&common->napi_rx, skb); 741 742 stats = this_cpu_ptr(ndev_priv->stats); 743 744 u64_stats_update_begin(&stats->syncp); 745 stats->rx_packets++; 746 stats->rx_bytes += pkt_len; 747 u64_stats_update_end(&stats->syncp); 748 kmemleak_not_leak(new_skb); 749 } else { 750 ndev->stats.rx_dropped++; 751 new_skb = skb; 752 } 753 754 if (netif_dormant(ndev)) { 755 dev_kfree_skb_any(new_skb); 756 ndev->stats.rx_dropped++; 757 return 0; 758 } 759 760 ret = am65_cpsw_nuss_rx_push(common, new_skb); 761 if (WARN_ON(ret < 0)) { 762 dev_kfree_skb_any(new_skb); 763 ndev->stats.rx_errors++; 764 ndev->stats.rx_dropped++; 765 } 766 767 return ret; 768 } 769 770 static int am65_cpsw_nuss_rx_poll(struct napi_struct *napi_rx, int budget) 771 { 772 struct am65_cpsw_common *common = am65_cpsw_napi_to_common(napi_rx); 773 int flow = AM65_CPSW_MAX_RX_FLOWS; 774 int cur_budget, ret; 775 int num_rx = 0; 776 777 /* process every flow */ 778 while (flow--) { 779 cur_budget = budget - num_rx; 780 781 while (cur_budget--) { 782 ret = am65_cpsw_nuss_rx_packets(common, flow); 783 if (ret) 784 break; 785 num_rx++; 786 } 787 788 if (num_rx >= budget) 789 break; 790 } 791 792 dev_dbg(common->dev, "%s num_rx:%d %d\n", __func__, num_rx, budget); 793 794 if (num_rx < budget && napi_complete_done(napi_rx, num_rx)) { 795 if (common->rx_irq_disabled) { 796 common->rx_irq_disabled = false; 797 enable_irq(common->rx_chns.irq); 798 } 799 } 800 801 return num_rx; 802 } 803 804 static void am65_cpsw_nuss_xmit_free(struct am65_cpsw_tx_chn *tx_chn, 805 struct cppi5_host_desc_t *desc) 806 { 807 struct cppi5_host_desc_t *first_desc, *next_desc; 808 dma_addr_t buf_dma, next_desc_dma; 809 u32 buf_dma_len; 810 811 first_desc = desc; 812 next_desc = first_desc; 813 814 cppi5_hdesc_get_obuf(first_desc, &buf_dma, &buf_dma_len); 815 k3_udma_glue_tx_cppi5_to_dma_addr(tx_chn->tx_chn, &buf_dma); 816 817 dma_unmap_single(tx_chn->dma_dev, buf_dma, buf_dma_len, DMA_TO_DEVICE); 818 819 next_desc_dma = cppi5_hdesc_get_next_hbdesc(first_desc); 820 k3_udma_glue_tx_cppi5_to_dma_addr(tx_chn->tx_chn, &next_desc_dma); 821 while (next_desc_dma) { 822 next_desc = k3_cppi_desc_pool_dma2virt(tx_chn->desc_pool, 823 next_desc_dma); 824 cppi5_hdesc_get_obuf(next_desc, &buf_dma, &buf_dma_len); 825 k3_udma_glue_tx_cppi5_to_dma_addr(tx_chn->tx_chn, &buf_dma); 826 827 dma_unmap_page(tx_chn->dma_dev, buf_dma, buf_dma_len, 828 DMA_TO_DEVICE); 829 830 next_desc_dma = cppi5_hdesc_get_next_hbdesc(next_desc); 831 k3_udma_glue_tx_cppi5_to_dma_addr(tx_chn->tx_chn, &next_desc_dma); 832 833 k3_cppi_desc_pool_free(tx_chn->desc_pool, next_desc); 834 } 835 836 k3_cppi_desc_pool_free(tx_chn->desc_pool, first_desc); 837 } 838 839 static void am65_cpsw_nuss_tx_cleanup(void *data, dma_addr_t desc_dma) 840 { 841 struct am65_cpsw_tx_chn *tx_chn = data; 842 struct cppi5_host_desc_t *desc_tx; 843 struct sk_buff *skb; 844 void **swdata; 845 846 desc_tx = k3_cppi_desc_pool_dma2virt(tx_chn->desc_pool, desc_dma); 847 swdata = cppi5_hdesc_get_swdata(desc_tx); 848 skb = *(swdata); 849 am65_cpsw_nuss_xmit_free(tx_chn, desc_tx); 850 851 dev_kfree_skb_any(skb); 852 } 853 854 static struct sk_buff * 855 am65_cpsw_nuss_tx_compl_packet(struct am65_cpsw_tx_chn *tx_chn, 856 dma_addr_t desc_dma) 857 { 858 struct am65_cpsw_ndev_priv *ndev_priv; 859 struct am65_cpsw_ndev_stats *stats; 860 struct cppi5_host_desc_t *desc_tx; 861 struct net_device *ndev; 862 struct sk_buff *skb; 863 void **swdata; 864 865 desc_tx = k3_cppi_desc_pool_dma2virt(tx_chn->desc_pool, 866 desc_dma); 867 swdata = cppi5_hdesc_get_swdata(desc_tx); 868 skb = *(swdata); 869 am65_cpsw_nuss_xmit_free(tx_chn, desc_tx); 870 871 ndev = skb->dev; 872 873 am65_cpts_tx_timestamp(tx_chn->common->cpts, skb); 874 875 ndev_priv = netdev_priv(ndev); 876 stats = this_cpu_ptr(ndev_priv->stats); 877 u64_stats_update_begin(&stats->syncp); 878 stats->tx_packets++; 879 stats->tx_bytes += skb->len; 880 u64_stats_update_end(&stats->syncp); 881 882 return skb; 883 } 884 885 static void am65_cpsw_nuss_tx_wake(struct am65_cpsw_tx_chn *tx_chn, struct net_device *ndev, 886 struct netdev_queue *netif_txq) 887 { 888 if (netif_tx_queue_stopped(netif_txq)) { 889 /* Check whether the queue is stopped due to stalled 890 * tx dma, if the queue is stopped then wake the queue 891 * as we have free desc for tx 892 */ 893 __netif_tx_lock(netif_txq, smp_processor_id()); 894 if (netif_running(ndev) && 895 (k3_cppi_desc_pool_avail(tx_chn->desc_pool) >= MAX_SKB_FRAGS)) 896 netif_tx_wake_queue(netif_txq); 897 898 __netif_tx_unlock(netif_txq); 899 } 900 } 901 902 static int am65_cpsw_nuss_tx_compl_packets(struct am65_cpsw_common *common, 903 int chn, unsigned int budget) 904 { 905 struct device *dev = common->dev; 906 struct am65_cpsw_tx_chn *tx_chn; 907 struct netdev_queue *netif_txq; 908 unsigned int total_bytes = 0; 909 struct net_device *ndev; 910 struct sk_buff *skb; 911 dma_addr_t desc_dma; 912 int res, num_tx = 0; 913 914 tx_chn = &common->tx_chns[chn]; 915 916 while (true) { 917 spin_lock(&tx_chn->lock); 918 res = k3_udma_glue_pop_tx_chn(tx_chn->tx_chn, &desc_dma); 919 spin_unlock(&tx_chn->lock); 920 if (res == -ENODATA) 921 break; 922 923 if (cppi5_desc_is_tdcm(desc_dma)) { 924 if (atomic_dec_and_test(&common->tdown_cnt)) 925 complete(&common->tdown_complete); 926 break; 927 } 928 929 skb = am65_cpsw_nuss_tx_compl_packet(tx_chn, desc_dma); 930 total_bytes = skb->len; 931 ndev = skb->dev; 932 napi_consume_skb(skb, budget); 933 num_tx++; 934 935 netif_txq = netdev_get_tx_queue(ndev, chn); 936 937 netdev_tx_completed_queue(netif_txq, num_tx, total_bytes); 938 939 am65_cpsw_nuss_tx_wake(tx_chn, ndev, netif_txq); 940 } 941 942 dev_dbg(dev, "%s:%u pkt:%d\n", __func__, chn, num_tx); 943 944 return num_tx; 945 } 946 947 static int am65_cpsw_nuss_tx_compl_packets_2g(struct am65_cpsw_common *common, 948 int chn, unsigned int budget) 949 { 950 struct device *dev = common->dev; 951 struct am65_cpsw_tx_chn *tx_chn; 952 struct netdev_queue *netif_txq; 953 unsigned int total_bytes = 0; 954 struct net_device *ndev; 955 struct sk_buff *skb; 956 dma_addr_t desc_dma; 957 int res, num_tx = 0; 958 959 tx_chn = &common->tx_chns[chn]; 960 961 while (true) { 962 res = k3_udma_glue_pop_tx_chn(tx_chn->tx_chn, &desc_dma); 963 if (res == -ENODATA) 964 break; 965 966 if (cppi5_desc_is_tdcm(desc_dma)) { 967 if (atomic_dec_and_test(&common->tdown_cnt)) 968 complete(&common->tdown_complete); 969 break; 970 } 971 972 skb = am65_cpsw_nuss_tx_compl_packet(tx_chn, desc_dma); 973 974 ndev = skb->dev; 975 total_bytes += skb->len; 976 napi_consume_skb(skb, budget); 977 num_tx++; 978 } 979 980 if (!num_tx) 981 return 0; 982 983 netif_txq = netdev_get_tx_queue(ndev, chn); 984 985 netdev_tx_completed_queue(netif_txq, num_tx, total_bytes); 986 987 am65_cpsw_nuss_tx_wake(tx_chn, ndev, netif_txq); 988 989 dev_dbg(dev, "%s:%u pkt:%d\n", __func__, chn, num_tx); 990 991 return num_tx; 992 } 993 994 static int am65_cpsw_nuss_tx_poll(struct napi_struct *napi_tx, int budget) 995 { 996 struct am65_cpsw_tx_chn *tx_chn = am65_cpsw_napi_to_tx_chn(napi_tx); 997 int num_tx; 998 999 if (AM65_CPSW_IS_CPSW2G(tx_chn->common)) 1000 num_tx = am65_cpsw_nuss_tx_compl_packets_2g(tx_chn->common, tx_chn->id, budget); 1001 else 1002 num_tx = am65_cpsw_nuss_tx_compl_packets(tx_chn->common, tx_chn->id, budget); 1003 1004 if (num_tx >= budget) 1005 return budget; 1006 1007 if (napi_complete_done(napi_tx, num_tx)) 1008 enable_irq(tx_chn->irq); 1009 1010 return 0; 1011 } 1012 1013 static irqreturn_t am65_cpsw_nuss_rx_irq(int irq, void *dev_id) 1014 { 1015 struct am65_cpsw_common *common = dev_id; 1016 1017 common->rx_irq_disabled = true; 1018 disable_irq_nosync(irq); 1019 napi_schedule(&common->napi_rx); 1020 1021 return IRQ_HANDLED; 1022 } 1023 1024 static irqreturn_t am65_cpsw_nuss_tx_irq(int irq, void *dev_id) 1025 { 1026 struct am65_cpsw_tx_chn *tx_chn = dev_id; 1027 1028 disable_irq_nosync(irq); 1029 napi_schedule(&tx_chn->napi_tx); 1030 1031 return IRQ_HANDLED; 1032 } 1033 1034 static netdev_tx_t am65_cpsw_nuss_ndo_slave_xmit(struct sk_buff *skb, 1035 struct net_device *ndev) 1036 { 1037 struct am65_cpsw_common *common = am65_ndev_to_common(ndev); 1038 struct cppi5_host_desc_t *first_desc, *next_desc, *cur_desc; 1039 struct am65_cpsw_port *port = am65_ndev_to_port(ndev); 1040 struct device *dev = common->dev; 1041 struct am65_cpsw_tx_chn *tx_chn; 1042 struct netdev_queue *netif_txq; 1043 dma_addr_t desc_dma, buf_dma; 1044 int ret, q_idx, i; 1045 void **swdata; 1046 u32 *psdata; 1047 u32 pkt_len; 1048 1049 /* padding enabled in hw */ 1050 pkt_len = skb_headlen(skb); 1051 1052 /* SKB TX timestamp */ 1053 if (port->tx_ts_enabled) 1054 am65_cpts_prep_tx_timestamp(common->cpts, skb); 1055 1056 q_idx = skb_get_queue_mapping(skb); 1057 dev_dbg(dev, "%s skb_queue:%d\n", __func__, q_idx); 1058 1059 tx_chn = &common->tx_chns[q_idx]; 1060 netif_txq = netdev_get_tx_queue(ndev, q_idx); 1061 1062 /* Map the linear buffer */ 1063 buf_dma = dma_map_single(tx_chn->dma_dev, skb->data, pkt_len, 1064 DMA_TO_DEVICE); 1065 if (unlikely(dma_mapping_error(tx_chn->dma_dev, buf_dma))) { 1066 dev_err(dev, "Failed to map tx skb buffer\n"); 1067 ndev->stats.tx_errors++; 1068 goto err_free_skb; 1069 } 1070 1071 first_desc = k3_cppi_desc_pool_alloc(tx_chn->desc_pool); 1072 if (!first_desc) { 1073 dev_dbg(dev, "Failed to allocate descriptor\n"); 1074 dma_unmap_single(tx_chn->dma_dev, buf_dma, pkt_len, 1075 DMA_TO_DEVICE); 1076 goto busy_stop_q; 1077 } 1078 1079 cppi5_hdesc_init(first_desc, CPPI5_INFO0_HDESC_EPIB_PRESENT, 1080 AM65_CPSW_NAV_PS_DATA_SIZE); 1081 cppi5_desc_set_pktids(&first_desc->hdr, 0, 0x3FFF); 1082 cppi5_hdesc_set_pkttype(first_desc, 0x7); 1083 cppi5_desc_set_tags_ids(&first_desc->hdr, 0, port->port_id); 1084 1085 k3_udma_glue_tx_dma_to_cppi5_addr(tx_chn->tx_chn, &buf_dma); 1086 cppi5_hdesc_attach_buf(first_desc, buf_dma, pkt_len, buf_dma, pkt_len); 1087 swdata = cppi5_hdesc_get_swdata(first_desc); 1088 *(swdata) = skb; 1089 psdata = cppi5_hdesc_get_psdata(first_desc); 1090 1091 /* HW csum offload if enabled */ 1092 psdata[2] = 0; 1093 if (likely(skb->ip_summed == CHECKSUM_PARTIAL)) { 1094 unsigned int cs_start, cs_offset; 1095 1096 cs_start = skb_transport_offset(skb); 1097 cs_offset = cs_start + skb->csum_offset; 1098 /* HW numerates bytes starting from 1 */ 1099 psdata[2] = ((cs_offset + 1) << 24) | 1100 ((cs_start + 1) << 16) | (skb->len - cs_start); 1101 dev_dbg(dev, "%s tx psdata:%#x\n", __func__, psdata[2]); 1102 } 1103 1104 if (!skb_is_nonlinear(skb)) 1105 goto done_tx; 1106 1107 dev_dbg(dev, "fragmented SKB\n"); 1108 1109 /* Handle the case where skb is fragmented in pages */ 1110 cur_desc = first_desc; 1111 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { 1112 skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 1113 u32 frag_size = skb_frag_size(frag); 1114 1115 next_desc = k3_cppi_desc_pool_alloc(tx_chn->desc_pool); 1116 if (!next_desc) { 1117 dev_err(dev, "Failed to allocate descriptor\n"); 1118 goto busy_free_descs; 1119 } 1120 1121 buf_dma = skb_frag_dma_map(tx_chn->dma_dev, frag, 0, frag_size, 1122 DMA_TO_DEVICE); 1123 if (unlikely(dma_mapping_error(tx_chn->dma_dev, buf_dma))) { 1124 dev_err(dev, "Failed to map tx skb page\n"); 1125 k3_cppi_desc_pool_free(tx_chn->desc_pool, next_desc); 1126 ndev->stats.tx_errors++; 1127 goto err_free_descs; 1128 } 1129 1130 cppi5_hdesc_reset_hbdesc(next_desc); 1131 k3_udma_glue_tx_dma_to_cppi5_addr(tx_chn->tx_chn, &buf_dma); 1132 cppi5_hdesc_attach_buf(next_desc, 1133 buf_dma, frag_size, buf_dma, frag_size); 1134 1135 desc_dma = k3_cppi_desc_pool_virt2dma(tx_chn->desc_pool, 1136 next_desc); 1137 k3_udma_glue_tx_dma_to_cppi5_addr(tx_chn->tx_chn, &desc_dma); 1138 cppi5_hdesc_link_hbdesc(cur_desc, desc_dma); 1139 1140 pkt_len += frag_size; 1141 cur_desc = next_desc; 1142 } 1143 WARN_ON(pkt_len != skb->len); 1144 1145 done_tx: 1146 skb_tx_timestamp(skb); 1147 1148 /* report bql before sending packet */ 1149 netdev_tx_sent_queue(netif_txq, pkt_len); 1150 1151 cppi5_hdesc_set_pktlen(first_desc, pkt_len); 1152 desc_dma = k3_cppi_desc_pool_virt2dma(tx_chn->desc_pool, first_desc); 1153 if (AM65_CPSW_IS_CPSW2G(common)) { 1154 ret = k3_udma_glue_push_tx_chn(tx_chn->tx_chn, first_desc, desc_dma); 1155 } else { 1156 spin_lock_bh(&tx_chn->lock); 1157 ret = k3_udma_glue_push_tx_chn(tx_chn->tx_chn, first_desc, desc_dma); 1158 spin_unlock_bh(&tx_chn->lock); 1159 } 1160 if (ret) { 1161 dev_err(dev, "can't push desc %d\n", ret); 1162 /* inform bql */ 1163 netdev_tx_completed_queue(netif_txq, 1, pkt_len); 1164 ndev->stats.tx_errors++; 1165 goto err_free_descs; 1166 } 1167 1168 if (k3_cppi_desc_pool_avail(tx_chn->desc_pool) < MAX_SKB_FRAGS) { 1169 netif_tx_stop_queue(netif_txq); 1170 /* Barrier, so that stop_queue visible to other cpus */ 1171 smp_mb__after_atomic(); 1172 dev_dbg(dev, "netif_tx_stop_queue %d\n", q_idx); 1173 1174 /* re-check for smp */ 1175 if (k3_cppi_desc_pool_avail(tx_chn->desc_pool) >= 1176 MAX_SKB_FRAGS) { 1177 netif_tx_wake_queue(netif_txq); 1178 dev_dbg(dev, "netif_tx_wake_queue %d\n", q_idx); 1179 } 1180 } 1181 1182 return NETDEV_TX_OK; 1183 1184 err_free_descs: 1185 am65_cpsw_nuss_xmit_free(tx_chn, first_desc); 1186 err_free_skb: 1187 ndev->stats.tx_dropped++; 1188 dev_kfree_skb_any(skb); 1189 return NETDEV_TX_OK; 1190 1191 busy_free_descs: 1192 am65_cpsw_nuss_xmit_free(tx_chn, first_desc); 1193 busy_stop_q: 1194 netif_tx_stop_queue(netif_txq); 1195 return NETDEV_TX_BUSY; 1196 } 1197 1198 static int am65_cpsw_nuss_ndo_slave_set_mac_address(struct net_device *ndev, 1199 void *addr) 1200 { 1201 struct am65_cpsw_common *common = am65_ndev_to_common(ndev); 1202 struct am65_cpsw_port *port = am65_ndev_to_port(ndev); 1203 struct sockaddr *sockaddr = (struct sockaddr *)addr; 1204 int ret; 1205 1206 ret = eth_prepare_mac_addr_change(ndev, addr); 1207 if (ret < 0) 1208 return ret; 1209 1210 ret = pm_runtime_resume_and_get(common->dev); 1211 if (ret < 0) 1212 return ret; 1213 1214 cpsw_ale_del_ucast(common->ale, ndev->dev_addr, 1215 HOST_PORT_NUM, 0, 0); 1216 cpsw_ale_add_ucast(common->ale, sockaddr->sa_data, 1217 HOST_PORT_NUM, ALE_SECURE, 0); 1218 1219 am65_cpsw_port_set_sl_mac(port, addr); 1220 eth_commit_mac_addr_change(ndev, sockaddr); 1221 1222 pm_runtime_put(common->dev); 1223 1224 return 0; 1225 } 1226 1227 static int am65_cpsw_nuss_hwtstamp_set(struct net_device *ndev, 1228 struct ifreq *ifr) 1229 { 1230 struct am65_cpsw_common *common = am65_ndev_to_common(ndev); 1231 struct am65_cpsw_port *port = am65_ndev_to_port(ndev); 1232 u32 ts_ctrl, seq_id, ts_ctrl_ltype2, ts_vlan_ltype; 1233 struct hwtstamp_config cfg; 1234 1235 if (!IS_ENABLED(CONFIG_TI_K3_AM65_CPTS)) 1236 return -EOPNOTSUPP; 1237 1238 if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg))) 1239 return -EFAULT; 1240 1241 /* TX HW timestamp */ 1242 switch (cfg.tx_type) { 1243 case HWTSTAMP_TX_OFF: 1244 case HWTSTAMP_TX_ON: 1245 break; 1246 default: 1247 return -ERANGE; 1248 } 1249 1250 switch (cfg.rx_filter) { 1251 case HWTSTAMP_FILTER_NONE: 1252 port->rx_ts_enabled = false; 1253 break; 1254 case HWTSTAMP_FILTER_ALL: 1255 case HWTSTAMP_FILTER_SOME: 1256 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: 1257 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: 1258 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: 1259 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: 1260 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 1261 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 1262 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: 1263 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: 1264 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: 1265 case HWTSTAMP_FILTER_PTP_V2_EVENT: 1266 case HWTSTAMP_FILTER_PTP_V2_SYNC: 1267 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 1268 case HWTSTAMP_FILTER_NTP_ALL: 1269 port->rx_ts_enabled = true; 1270 cfg.rx_filter = HWTSTAMP_FILTER_ALL; 1271 break; 1272 default: 1273 return -ERANGE; 1274 } 1275 1276 port->tx_ts_enabled = (cfg.tx_type == HWTSTAMP_TX_ON); 1277 1278 /* cfg TX timestamp */ 1279 seq_id = (AM65_CPSW_TS_SEQ_ID_OFFSET << 1280 AM65_CPSW_PN_TS_SEQ_ID_OFFSET_SHIFT) | ETH_P_1588; 1281 1282 ts_vlan_ltype = ETH_P_8021Q; 1283 1284 ts_ctrl_ltype2 = ETH_P_1588 | 1285 AM65_CPSW_PN_TS_CTL_LTYPE2_TS_107 | 1286 AM65_CPSW_PN_TS_CTL_LTYPE2_TS_129 | 1287 AM65_CPSW_PN_TS_CTL_LTYPE2_TS_130 | 1288 AM65_CPSW_PN_TS_CTL_LTYPE2_TS_131 | 1289 AM65_CPSW_PN_TS_CTL_LTYPE2_TS_132 | 1290 AM65_CPSW_PN_TS_CTL_LTYPE2_TS_319 | 1291 AM65_CPSW_PN_TS_CTL_LTYPE2_TS_320 | 1292 AM65_CPSW_PN_TS_CTL_LTYPE2_TS_TTL_NONZERO; 1293 1294 ts_ctrl = AM65_CPSW_TS_EVENT_MSG_TYPE_BITS << 1295 AM65_CPSW_PN_TS_CTL_MSG_TYPE_EN_SHIFT; 1296 1297 if (port->tx_ts_enabled) 1298 ts_ctrl |= AM65_CPSW_TS_TX_ANX_ALL_EN | 1299 AM65_CPSW_PN_TS_CTL_TX_VLAN_LT1_EN; 1300 1301 writel(seq_id, port->port_base + AM65_CPSW_PORTN_REG_TS_SEQ_LTYPE_REG); 1302 writel(ts_vlan_ltype, port->port_base + 1303 AM65_CPSW_PORTN_REG_TS_VLAN_LTYPE_REG); 1304 writel(ts_ctrl_ltype2, port->port_base + 1305 AM65_CPSW_PORTN_REG_TS_CTL_LTYPE2); 1306 writel(ts_ctrl, port->port_base + AM65_CPSW_PORTN_REG_TS_CTL); 1307 1308 /* en/dis RX timestamp */ 1309 am65_cpts_rx_enable(common->cpts, port->rx_ts_enabled); 1310 1311 return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0; 1312 } 1313 1314 static int am65_cpsw_nuss_hwtstamp_get(struct net_device *ndev, 1315 struct ifreq *ifr) 1316 { 1317 struct am65_cpsw_port *port = am65_ndev_to_port(ndev); 1318 struct hwtstamp_config cfg; 1319 1320 if (!IS_ENABLED(CONFIG_TI_K3_AM65_CPTS)) 1321 return -EOPNOTSUPP; 1322 1323 cfg.flags = 0; 1324 cfg.tx_type = port->tx_ts_enabled ? 1325 HWTSTAMP_TX_ON : HWTSTAMP_TX_OFF; 1326 cfg.rx_filter = port->rx_ts_enabled ? 1327 HWTSTAMP_FILTER_ALL : HWTSTAMP_FILTER_NONE; 1328 1329 return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0; 1330 } 1331 1332 static int am65_cpsw_nuss_ndo_slave_ioctl(struct net_device *ndev, 1333 struct ifreq *req, int cmd) 1334 { 1335 struct am65_cpsw_port *port = am65_ndev_to_port(ndev); 1336 1337 if (!netif_running(ndev)) 1338 return -EINVAL; 1339 1340 switch (cmd) { 1341 case SIOCSHWTSTAMP: 1342 return am65_cpsw_nuss_hwtstamp_set(ndev, req); 1343 case SIOCGHWTSTAMP: 1344 return am65_cpsw_nuss_hwtstamp_get(ndev, req); 1345 } 1346 1347 return phylink_mii_ioctl(port->slave.phylink, req, cmd); 1348 } 1349 1350 static void am65_cpsw_nuss_ndo_get_stats(struct net_device *dev, 1351 struct rtnl_link_stats64 *stats) 1352 { 1353 struct am65_cpsw_ndev_priv *ndev_priv = netdev_priv(dev); 1354 unsigned int start; 1355 int cpu; 1356 1357 for_each_possible_cpu(cpu) { 1358 struct am65_cpsw_ndev_stats *cpu_stats; 1359 u64 rx_packets; 1360 u64 rx_bytes; 1361 u64 tx_packets; 1362 u64 tx_bytes; 1363 1364 cpu_stats = per_cpu_ptr(ndev_priv->stats, cpu); 1365 do { 1366 start = u64_stats_fetch_begin_irq(&cpu_stats->syncp); 1367 rx_packets = cpu_stats->rx_packets; 1368 rx_bytes = cpu_stats->rx_bytes; 1369 tx_packets = cpu_stats->tx_packets; 1370 tx_bytes = cpu_stats->tx_bytes; 1371 } while (u64_stats_fetch_retry_irq(&cpu_stats->syncp, start)); 1372 1373 stats->rx_packets += rx_packets; 1374 stats->rx_bytes += rx_bytes; 1375 stats->tx_packets += tx_packets; 1376 stats->tx_bytes += tx_bytes; 1377 } 1378 1379 stats->rx_errors = dev->stats.rx_errors; 1380 stats->rx_dropped = dev->stats.rx_dropped; 1381 stats->tx_dropped = dev->stats.tx_dropped; 1382 } 1383 1384 static struct devlink_port *am65_cpsw_ndo_get_devlink_port(struct net_device *ndev) 1385 { 1386 struct am65_cpsw_port *port = am65_ndev_to_port(ndev); 1387 1388 return &port->devlink_port; 1389 } 1390 1391 static const struct net_device_ops am65_cpsw_nuss_netdev_ops = { 1392 .ndo_open = am65_cpsw_nuss_ndo_slave_open, 1393 .ndo_stop = am65_cpsw_nuss_ndo_slave_stop, 1394 .ndo_start_xmit = am65_cpsw_nuss_ndo_slave_xmit, 1395 .ndo_set_rx_mode = am65_cpsw_nuss_ndo_slave_set_rx_mode, 1396 .ndo_get_stats64 = am65_cpsw_nuss_ndo_get_stats, 1397 .ndo_validate_addr = eth_validate_addr, 1398 .ndo_set_mac_address = am65_cpsw_nuss_ndo_slave_set_mac_address, 1399 .ndo_tx_timeout = am65_cpsw_nuss_ndo_host_tx_timeout, 1400 .ndo_vlan_rx_add_vid = am65_cpsw_nuss_ndo_slave_add_vid, 1401 .ndo_vlan_rx_kill_vid = am65_cpsw_nuss_ndo_slave_kill_vid, 1402 .ndo_eth_ioctl = am65_cpsw_nuss_ndo_slave_ioctl, 1403 .ndo_setup_tc = am65_cpsw_qos_ndo_setup_tc, 1404 .ndo_get_devlink_port = am65_cpsw_ndo_get_devlink_port, 1405 }; 1406 1407 static void am65_cpsw_nuss_mac_config(struct phylink_config *config, unsigned int mode, 1408 const struct phylink_link_state *state) 1409 { 1410 struct am65_cpsw_slave_data *slave = container_of(config, struct am65_cpsw_slave_data, 1411 phylink_config); 1412 struct am65_cpsw_port *port = container_of(slave, struct am65_cpsw_port, slave); 1413 struct am65_cpsw_common *common = port->common; 1414 1415 if (common->pdata.extra_modes & BIT(state->interface)) 1416 writel(AM65_CPSW_SGMII_CONTROL_MR_AN_ENABLE, 1417 port->sgmii_base + AM65_CPSW_SGMII_CONTROL_REG); 1418 } 1419 1420 static void am65_cpsw_nuss_mac_link_down(struct phylink_config *config, unsigned int mode, 1421 phy_interface_t interface) 1422 { 1423 struct am65_cpsw_slave_data *slave = container_of(config, struct am65_cpsw_slave_data, 1424 phylink_config); 1425 struct am65_cpsw_port *port = container_of(slave, struct am65_cpsw_port, slave); 1426 struct am65_cpsw_common *common = port->common; 1427 struct net_device *ndev = port->ndev; 1428 int tmo; 1429 1430 /* disable forwarding */ 1431 cpsw_ale_control_set(common->ale, port->port_id, ALE_PORT_STATE, ALE_PORT_STATE_DISABLE); 1432 1433 cpsw_sl_ctl_set(port->slave.mac_sl, CPSW_SL_CTL_CMD_IDLE); 1434 1435 tmo = cpsw_sl_wait_for_idle(port->slave.mac_sl, 100); 1436 dev_dbg(common->dev, "down msc_sl %08x tmo %d\n", 1437 cpsw_sl_reg_read(port->slave.mac_sl, CPSW_SL_MACSTATUS), tmo); 1438 1439 cpsw_sl_ctl_reset(port->slave.mac_sl); 1440 1441 am65_cpsw_qos_link_down(ndev); 1442 netif_tx_stop_all_queues(ndev); 1443 } 1444 1445 static void am65_cpsw_nuss_mac_link_up(struct phylink_config *config, struct phy_device *phy, 1446 unsigned int mode, phy_interface_t interface, int speed, 1447 int duplex, bool tx_pause, bool rx_pause) 1448 { 1449 struct am65_cpsw_slave_data *slave = container_of(config, struct am65_cpsw_slave_data, 1450 phylink_config); 1451 struct am65_cpsw_port *port = container_of(slave, struct am65_cpsw_port, slave); 1452 struct am65_cpsw_common *common = port->common; 1453 u32 mac_control = CPSW_SL_CTL_GMII_EN; 1454 struct net_device *ndev = port->ndev; 1455 1456 if (speed == SPEED_1000) 1457 mac_control |= CPSW_SL_CTL_GIG; 1458 if (speed == SPEED_10 && interface == PHY_INTERFACE_MODE_RGMII) 1459 /* Can be used with in band mode only */ 1460 mac_control |= CPSW_SL_CTL_EXT_EN; 1461 if (speed == SPEED_100 && interface == PHY_INTERFACE_MODE_RMII) 1462 mac_control |= CPSW_SL_CTL_IFCTL_A; 1463 if (duplex) 1464 mac_control |= CPSW_SL_CTL_FULLDUPLEX; 1465 1466 /* rx_pause/tx_pause */ 1467 if (rx_pause) 1468 mac_control |= CPSW_SL_CTL_RX_FLOW_EN; 1469 1470 if (tx_pause) 1471 mac_control |= CPSW_SL_CTL_TX_FLOW_EN; 1472 1473 cpsw_sl_ctl_set(port->slave.mac_sl, mac_control); 1474 1475 /* enable forwarding */ 1476 cpsw_ale_control_set(common->ale, port->port_id, ALE_PORT_STATE, ALE_PORT_STATE_FORWARD); 1477 1478 am65_cpsw_qos_link_up(ndev, speed); 1479 netif_tx_wake_all_queues(ndev); 1480 } 1481 1482 static const struct phylink_mac_ops am65_cpsw_phylink_mac_ops = { 1483 .validate = phylink_generic_validate, 1484 .mac_config = am65_cpsw_nuss_mac_config, 1485 .mac_link_down = am65_cpsw_nuss_mac_link_down, 1486 .mac_link_up = am65_cpsw_nuss_mac_link_up, 1487 }; 1488 1489 static void am65_cpsw_nuss_slave_disable_unused(struct am65_cpsw_port *port) 1490 { 1491 struct am65_cpsw_common *common = port->common; 1492 1493 if (!port->disabled) 1494 return; 1495 1496 cpsw_ale_control_set(common->ale, port->port_id, 1497 ALE_PORT_STATE, ALE_PORT_STATE_DISABLE); 1498 1499 cpsw_sl_reset(port->slave.mac_sl, 100); 1500 cpsw_sl_ctl_reset(port->slave.mac_sl); 1501 } 1502 1503 static void am65_cpsw_nuss_free_tx_chns(void *data) 1504 { 1505 struct am65_cpsw_common *common = data; 1506 int i; 1507 1508 for (i = 0; i < common->tx_ch_num; i++) { 1509 struct am65_cpsw_tx_chn *tx_chn = &common->tx_chns[i]; 1510 1511 if (!IS_ERR_OR_NULL(tx_chn->desc_pool)) 1512 k3_cppi_desc_pool_destroy(tx_chn->desc_pool); 1513 1514 if (!IS_ERR_OR_NULL(tx_chn->tx_chn)) 1515 k3_udma_glue_release_tx_chn(tx_chn->tx_chn); 1516 1517 memset(tx_chn, 0, sizeof(*tx_chn)); 1518 } 1519 } 1520 1521 void am65_cpsw_nuss_remove_tx_chns(struct am65_cpsw_common *common) 1522 { 1523 struct device *dev = common->dev; 1524 int i; 1525 1526 devm_remove_action(dev, am65_cpsw_nuss_free_tx_chns, common); 1527 1528 for (i = 0; i < common->tx_ch_num; i++) { 1529 struct am65_cpsw_tx_chn *tx_chn = &common->tx_chns[i]; 1530 1531 if (tx_chn->irq) 1532 devm_free_irq(dev, tx_chn->irq, tx_chn); 1533 1534 netif_napi_del(&tx_chn->napi_tx); 1535 1536 if (!IS_ERR_OR_NULL(tx_chn->desc_pool)) 1537 k3_cppi_desc_pool_destroy(tx_chn->desc_pool); 1538 1539 if (!IS_ERR_OR_NULL(tx_chn->tx_chn)) 1540 k3_udma_glue_release_tx_chn(tx_chn->tx_chn); 1541 1542 memset(tx_chn, 0, sizeof(*tx_chn)); 1543 } 1544 } 1545 1546 static int am65_cpsw_nuss_init_tx_chns(struct am65_cpsw_common *common) 1547 { 1548 u32 max_desc_num = ALIGN(AM65_CPSW_MAX_TX_DESC, MAX_SKB_FRAGS); 1549 struct k3_udma_glue_tx_channel_cfg tx_cfg = { 0 }; 1550 struct device *dev = common->dev; 1551 struct k3_ring_cfg ring_cfg = { 1552 .elm_size = K3_RINGACC_RING_ELSIZE_8, 1553 .mode = K3_RINGACC_RING_MODE_RING, 1554 .flags = 0 1555 }; 1556 u32 hdesc_size; 1557 int i, ret = 0; 1558 1559 hdesc_size = cppi5_hdesc_calc_size(true, AM65_CPSW_NAV_PS_DATA_SIZE, 1560 AM65_CPSW_NAV_SW_DATA_SIZE); 1561 1562 tx_cfg.swdata_size = AM65_CPSW_NAV_SW_DATA_SIZE; 1563 tx_cfg.tx_cfg = ring_cfg; 1564 tx_cfg.txcq_cfg = ring_cfg; 1565 tx_cfg.tx_cfg.size = max_desc_num; 1566 tx_cfg.txcq_cfg.size = max_desc_num; 1567 1568 for (i = 0; i < common->tx_ch_num; i++) { 1569 struct am65_cpsw_tx_chn *tx_chn = &common->tx_chns[i]; 1570 1571 snprintf(tx_chn->tx_chn_name, 1572 sizeof(tx_chn->tx_chn_name), "tx%d", i); 1573 1574 spin_lock_init(&tx_chn->lock); 1575 tx_chn->common = common; 1576 tx_chn->id = i; 1577 tx_chn->descs_num = max_desc_num; 1578 1579 tx_chn->tx_chn = 1580 k3_udma_glue_request_tx_chn(dev, 1581 tx_chn->tx_chn_name, 1582 &tx_cfg); 1583 if (IS_ERR(tx_chn->tx_chn)) { 1584 ret = dev_err_probe(dev, PTR_ERR(tx_chn->tx_chn), 1585 "Failed to request tx dma channel\n"); 1586 goto err; 1587 } 1588 tx_chn->dma_dev = k3_udma_glue_tx_get_dma_device(tx_chn->tx_chn); 1589 1590 tx_chn->desc_pool = k3_cppi_desc_pool_create_name(tx_chn->dma_dev, 1591 tx_chn->descs_num, 1592 hdesc_size, 1593 tx_chn->tx_chn_name); 1594 if (IS_ERR(tx_chn->desc_pool)) { 1595 ret = PTR_ERR(tx_chn->desc_pool); 1596 dev_err(dev, "Failed to create poll %d\n", ret); 1597 goto err; 1598 } 1599 1600 tx_chn->irq = k3_udma_glue_tx_get_irq(tx_chn->tx_chn); 1601 if (tx_chn->irq <= 0) { 1602 dev_err(dev, "Failed to get tx dma irq %d\n", 1603 tx_chn->irq); 1604 goto err; 1605 } 1606 1607 snprintf(tx_chn->tx_chn_name, 1608 sizeof(tx_chn->tx_chn_name), "%s-tx%d", 1609 dev_name(dev), tx_chn->id); 1610 } 1611 1612 err: 1613 i = devm_add_action(dev, am65_cpsw_nuss_free_tx_chns, common); 1614 if (i) { 1615 dev_err(dev, "Failed to add free_tx_chns action %d\n", i); 1616 return i; 1617 } 1618 1619 return ret; 1620 } 1621 1622 static void am65_cpsw_nuss_free_rx_chns(void *data) 1623 { 1624 struct am65_cpsw_common *common = data; 1625 struct am65_cpsw_rx_chn *rx_chn; 1626 1627 rx_chn = &common->rx_chns; 1628 1629 if (!IS_ERR_OR_NULL(rx_chn->desc_pool)) 1630 k3_cppi_desc_pool_destroy(rx_chn->desc_pool); 1631 1632 if (!IS_ERR_OR_NULL(rx_chn->rx_chn)) 1633 k3_udma_glue_release_rx_chn(rx_chn->rx_chn); 1634 } 1635 1636 static int am65_cpsw_nuss_init_rx_chns(struct am65_cpsw_common *common) 1637 { 1638 struct am65_cpsw_rx_chn *rx_chn = &common->rx_chns; 1639 struct k3_udma_glue_rx_channel_cfg rx_cfg = { 0 }; 1640 u32 max_desc_num = AM65_CPSW_MAX_RX_DESC; 1641 struct device *dev = common->dev; 1642 u32 hdesc_size; 1643 u32 fdqring_id; 1644 int i, ret = 0; 1645 1646 hdesc_size = cppi5_hdesc_calc_size(true, AM65_CPSW_NAV_PS_DATA_SIZE, 1647 AM65_CPSW_NAV_SW_DATA_SIZE); 1648 1649 rx_cfg.swdata_size = AM65_CPSW_NAV_SW_DATA_SIZE; 1650 rx_cfg.flow_id_num = AM65_CPSW_MAX_RX_FLOWS; 1651 rx_cfg.flow_id_base = common->rx_flow_id_base; 1652 1653 /* init all flows */ 1654 rx_chn->dev = dev; 1655 rx_chn->descs_num = max_desc_num; 1656 1657 rx_chn->rx_chn = k3_udma_glue_request_rx_chn(dev, "rx", &rx_cfg); 1658 if (IS_ERR(rx_chn->rx_chn)) { 1659 ret = dev_err_probe(dev, PTR_ERR(rx_chn->rx_chn), 1660 "Failed to request rx dma channel\n"); 1661 goto err; 1662 } 1663 rx_chn->dma_dev = k3_udma_glue_rx_get_dma_device(rx_chn->rx_chn); 1664 1665 rx_chn->desc_pool = k3_cppi_desc_pool_create_name(rx_chn->dma_dev, 1666 rx_chn->descs_num, 1667 hdesc_size, "rx"); 1668 if (IS_ERR(rx_chn->desc_pool)) { 1669 ret = PTR_ERR(rx_chn->desc_pool); 1670 dev_err(dev, "Failed to create rx poll %d\n", ret); 1671 goto err; 1672 } 1673 1674 common->rx_flow_id_base = 1675 k3_udma_glue_rx_get_flow_id_base(rx_chn->rx_chn); 1676 dev_info(dev, "set new flow-id-base %u\n", common->rx_flow_id_base); 1677 1678 fdqring_id = K3_RINGACC_RING_ID_ANY; 1679 for (i = 0; i < rx_cfg.flow_id_num; i++) { 1680 struct k3_ring_cfg rxring_cfg = { 1681 .elm_size = K3_RINGACC_RING_ELSIZE_8, 1682 .mode = K3_RINGACC_RING_MODE_RING, 1683 .flags = 0, 1684 }; 1685 struct k3_ring_cfg fdqring_cfg = { 1686 .elm_size = K3_RINGACC_RING_ELSIZE_8, 1687 .flags = K3_RINGACC_RING_SHARED, 1688 }; 1689 struct k3_udma_glue_rx_flow_cfg rx_flow_cfg = { 1690 .rx_cfg = rxring_cfg, 1691 .rxfdq_cfg = fdqring_cfg, 1692 .ring_rxq_id = K3_RINGACC_RING_ID_ANY, 1693 .src_tag_lo_sel = 1694 K3_UDMA_GLUE_SRC_TAG_LO_USE_REMOTE_SRC_TAG, 1695 }; 1696 1697 rx_flow_cfg.ring_rxfdq0_id = fdqring_id; 1698 rx_flow_cfg.rx_cfg.size = max_desc_num; 1699 rx_flow_cfg.rxfdq_cfg.size = max_desc_num; 1700 rx_flow_cfg.rxfdq_cfg.mode = common->pdata.fdqring_mode; 1701 1702 ret = k3_udma_glue_rx_flow_init(rx_chn->rx_chn, 1703 i, &rx_flow_cfg); 1704 if (ret) { 1705 dev_err(dev, "Failed to init rx flow%d %d\n", i, ret); 1706 goto err; 1707 } 1708 if (!i) 1709 fdqring_id = 1710 k3_udma_glue_rx_flow_get_fdq_id(rx_chn->rx_chn, 1711 i); 1712 1713 rx_chn->irq = k3_udma_glue_rx_get_irq(rx_chn->rx_chn, i); 1714 1715 if (rx_chn->irq <= 0) { 1716 dev_err(dev, "Failed to get rx dma irq %d\n", 1717 rx_chn->irq); 1718 ret = -ENXIO; 1719 goto err; 1720 } 1721 } 1722 1723 err: 1724 i = devm_add_action(dev, am65_cpsw_nuss_free_rx_chns, common); 1725 if (i) { 1726 dev_err(dev, "Failed to add free_rx_chns action %d\n", i); 1727 return i; 1728 } 1729 1730 return ret; 1731 } 1732 1733 static int am65_cpsw_nuss_init_host_p(struct am65_cpsw_common *common) 1734 { 1735 struct am65_cpsw_host *host_p = am65_common_get_host(common); 1736 1737 host_p->common = common; 1738 host_p->port_base = common->cpsw_base + AM65_CPSW_NU_PORTS_BASE; 1739 host_p->stat_base = common->cpsw_base + AM65_CPSW_NU_STATS_BASE; 1740 1741 return 0; 1742 } 1743 1744 static int am65_cpsw_am654_get_efuse_macid(struct device_node *of_node, 1745 int slave, u8 *mac_addr) 1746 { 1747 u32 mac_lo, mac_hi, offset; 1748 struct regmap *syscon; 1749 int ret; 1750 1751 syscon = syscon_regmap_lookup_by_phandle(of_node, "ti,syscon-efuse"); 1752 if (IS_ERR(syscon)) { 1753 if (PTR_ERR(syscon) == -ENODEV) 1754 return 0; 1755 return PTR_ERR(syscon); 1756 } 1757 1758 ret = of_property_read_u32_index(of_node, "ti,syscon-efuse", 1, 1759 &offset); 1760 if (ret) 1761 return ret; 1762 1763 regmap_read(syscon, offset, &mac_lo); 1764 regmap_read(syscon, offset + 4, &mac_hi); 1765 1766 mac_addr[0] = (mac_hi >> 8) & 0xff; 1767 mac_addr[1] = mac_hi & 0xff; 1768 mac_addr[2] = (mac_lo >> 24) & 0xff; 1769 mac_addr[3] = (mac_lo >> 16) & 0xff; 1770 mac_addr[4] = (mac_lo >> 8) & 0xff; 1771 mac_addr[5] = mac_lo & 0xff; 1772 1773 return 0; 1774 } 1775 1776 static int am65_cpsw_init_cpts(struct am65_cpsw_common *common) 1777 { 1778 struct device *dev = common->dev; 1779 struct device_node *node; 1780 struct am65_cpts *cpts; 1781 void __iomem *reg_base; 1782 1783 if (!IS_ENABLED(CONFIG_TI_K3_AM65_CPTS)) 1784 return 0; 1785 1786 node = of_get_child_by_name(dev->of_node, "cpts"); 1787 if (!node) { 1788 dev_err(dev, "%s cpts not found\n", __func__); 1789 return -ENOENT; 1790 } 1791 1792 reg_base = common->cpsw_base + AM65_CPSW_NU_CPTS_BASE; 1793 cpts = am65_cpts_create(dev, reg_base, node); 1794 if (IS_ERR(cpts)) { 1795 int ret = PTR_ERR(cpts); 1796 1797 of_node_put(node); 1798 if (ret == -EOPNOTSUPP) { 1799 dev_info(dev, "cpts disabled\n"); 1800 return 0; 1801 } 1802 1803 dev_err(dev, "cpts create err %d\n", ret); 1804 return ret; 1805 } 1806 common->cpts = cpts; 1807 /* Forbid PM runtime if CPTS is running. 1808 * K3 CPSWxG modules may completely lose context during ON->OFF 1809 * transitions depending on integration. 1810 * AM65x/J721E MCU CPSW2G: false 1811 * J721E MAIN_CPSW9G: true 1812 */ 1813 pm_runtime_forbid(dev); 1814 1815 return 0; 1816 } 1817 1818 static int am65_cpsw_nuss_init_slave_ports(struct am65_cpsw_common *common) 1819 { 1820 struct device_node *node, *port_np; 1821 struct device *dev = common->dev; 1822 int ret; 1823 1824 node = of_get_child_by_name(dev->of_node, "ethernet-ports"); 1825 if (!node) 1826 return -ENOENT; 1827 1828 for_each_child_of_node(node, port_np) { 1829 struct am65_cpsw_port *port; 1830 u32 port_id; 1831 1832 /* it is not a slave port node, continue */ 1833 if (strcmp(port_np->name, "port")) 1834 continue; 1835 1836 ret = of_property_read_u32(port_np, "reg", &port_id); 1837 if (ret < 0) { 1838 dev_err(dev, "%pOF error reading port_id %d\n", 1839 port_np, ret); 1840 goto of_node_put; 1841 } 1842 1843 if (!port_id || port_id > common->port_num) { 1844 dev_err(dev, "%pOF has invalid port_id %u %s\n", 1845 port_np, port_id, port_np->name); 1846 ret = -EINVAL; 1847 goto of_node_put; 1848 } 1849 1850 port = am65_common_get_port(common, port_id); 1851 port->port_id = port_id; 1852 port->common = common; 1853 port->port_base = common->cpsw_base + AM65_CPSW_NU_PORTS_BASE + 1854 AM65_CPSW_NU_PORTS_OFFSET * (port_id); 1855 if (common->pdata.extra_modes) 1856 port->sgmii_base = common->ss_base + AM65_CPSW_SGMII_BASE * (port_id); 1857 port->stat_base = common->cpsw_base + AM65_CPSW_NU_STATS_BASE + 1858 (AM65_CPSW_NU_STATS_PORT_OFFSET * port_id); 1859 port->name = of_get_property(port_np, "label", NULL); 1860 port->fetch_ram_base = 1861 common->cpsw_base + AM65_CPSW_NU_FRAM_BASE + 1862 (AM65_CPSW_NU_FRAM_PORT_OFFSET * (port_id - 1)); 1863 1864 port->slave.mac_sl = cpsw_sl_get("am65", dev, port->port_base); 1865 if (IS_ERR(port->slave.mac_sl)) { 1866 ret = PTR_ERR(port->slave.mac_sl); 1867 goto of_node_put; 1868 } 1869 1870 port->disabled = !of_device_is_available(port_np); 1871 if (port->disabled) { 1872 common->disabled_ports_mask |= BIT(port->port_id); 1873 continue; 1874 } 1875 1876 port->slave.ifphy = devm_of_phy_get(dev, port_np, NULL); 1877 if (IS_ERR(port->slave.ifphy)) { 1878 ret = PTR_ERR(port->slave.ifphy); 1879 dev_err(dev, "%pOF error retrieving port phy: %d\n", 1880 port_np, ret); 1881 goto of_node_put; 1882 } 1883 1884 port->slave.mac_only = 1885 of_property_read_bool(port_np, "ti,mac-only"); 1886 1887 /* get phy/link info */ 1888 port->slave.phy_node = port_np; 1889 ret = of_get_phy_mode(port_np, &port->slave.phy_if); 1890 if (ret) { 1891 dev_err(dev, "%pOF read phy-mode err %d\n", 1892 port_np, ret); 1893 goto of_node_put; 1894 } 1895 1896 ret = phy_set_mode_ext(port->slave.ifphy, PHY_MODE_ETHERNET, port->slave.phy_if); 1897 if (ret) 1898 goto of_node_put; 1899 1900 ret = of_get_mac_address(port_np, port->slave.mac_addr); 1901 if (ret) { 1902 am65_cpsw_am654_get_efuse_macid(port_np, 1903 port->port_id, 1904 port->slave.mac_addr); 1905 if (!is_valid_ether_addr(port->slave.mac_addr)) { 1906 eth_random_addr(port->slave.mac_addr); 1907 dev_err(dev, "Use random MAC address\n"); 1908 } 1909 } 1910 } 1911 of_node_put(node); 1912 1913 /* is there at least one ext.port */ 1914 if (!(~common->disabled_ports_mask & GENMASK(common->port_num, 1))) { 1915 dev_err(dev, "No Ext. port are available\n"); 1916 return -ENODEV; 1917 } 1918 1919 return 0; 1920 1921 of_node_put: 1922 of_node_put(port_np); 1923 of_node_put(node); 1924 return ret; 1925 } 1926 1927 static void am65_cpsw_pcpu_stats_free(void *data) 1928 { 1929 struct am65_cpsw_ndev_stats __percpu *stats = data; 1930 1931 free_percpu(stats); 1932 } 1933 1934 static void am65_cpsw_nuss_phylink_cleanup(struct am65_cpsw_common *common) 1935 { 1936 struct am65_cpsw_port *port; 1937 int i; 1938 1939 for (i = 0; i < common->port_num; i++) { 1940 port = &common->ports[i]; 1941 if (port->slave.phylink) 1942 phylink_destroy(port->slave.phylink); 1943 } 1944 } 1945 1946 static int 1947 am65_cpsw_nuss_init_port_ndev(struct am65_cpsw_common *common, u32 port_idx) 1948 { 1949 struct am65_cpsw_ndev_priv *ndev_priv; 1950 struct device *dev = common->dev; 1951 struct am65_cpsw_port *port; 1952 struct phylink *phylink; 1953 int ret; 1954 1955 port = &common->ports[port_idx]; 1956 1957 if (port->disabled) 1958 return 0; 1959 1960 /* alloc netdev */ 1961 port->ndev = devm_alloc_etherdev_mqs(common->dev, 1962 sizeof(struct am65_cpsw_ndev_priv), 1963 AM65_CPSW_MAX_TX_QUEUES, 1964 AM65_CPSW_MAX_RX_QUEUES); 1965 if (!port->ndev) { 1966 dev_err(dev, "error allocating slave net_device %u\n", 1967 port->port_id); 1968 return -ENOMEM; 1969 } 1970 1971 ndev_priv = netdev_priv(port->ndev); 1972 ndev_priv->port = port; 1973 ndev_priv->msg_enable = AM65_CPSW_DEBUG; 1974 SET_NETDEV_DEV(port->ndev, dev); 1975 1976 eth_hw_addr_set(port->ndev, port->slave.mac_addr); 1977 1978 port->ndev->min_mtu = AM65_CPSW_MIN_PACKET_SIZE; 1979 port->ndev->max_mtu = AM65_CPSW_MAX_PACKET_SIZE; 1980 port->ndev->hw_features = NETIF_F_SG | 1981 NETIF_F_RXCSUM | 1982 NETIF_F_HW_CSUM | 1983 NETIF_F_HW_TC; 1984 port->ndev->features = port->ndev->hw_features | 1985 NETIF_F_HW_VLAN_CTAG_FILTER; 1986 port->ndev->vlan_features |= NETIF_F_SG; 1987 port->ndev->netdev_ops = &am65_cpsw_nuss_netdev_ops; 1988 port->ndev->ethtool_ops = &am65_cpsw_ethtool_ops_slave; 1989 1990 /* Configuring Phylink */ 1991 port->slave.phylink_config.dev = &port->ndev->dev; 1992 port->slave.phylink_config.type = PHYLINK_NETDEV; 1993 port->slave.phylink_config.mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 | MAC_1000FD; 1994 1995 if (phy_interface_mode_is_rgmii(port->slave.phy_if)) { 1996 phy_interface_set_rgmii(port->slave.phylink_config.supported_interfaces); 1997 } else if (port->slave.phy_if == PHY_INTERFACE_MODE_RMII) { 1998 __set_bit(PHY_INTERFACE_MODE_RMII, 1999 port->slave.phylink_config.supported_interfaces); 2000 } else if (common->pdata.extra_modes & BIT(port->slave.phy_if)) { 2001 __set_bit(PHY_INTERFACE_MODE_QSGMII, 2002 port->slave.phylink_config.supported_interfaces); 2003 } else { 2004 dev_err(dev, "selected phy-mode is not supported\n"); 2005 return -EOPNOTSUPP; 2006 } 2007 2008 phylink = phylink_create(&port->slave.phylink_config, 2009 of_node_to_fwnode(port->slave.phy_node), 2010 port->slave.phy_if, 2011 &am65_cpsw_phylink_mac_ops); 2012 if (IS_ERR(phylink)) 2013 return PTR_ERR(phylink); 2014 2015 port->slave.phylink = phylink; 2016 2017 /* Disable TX checksum offload by default due to HW bug */ 2018 if (common->pdata.quirks & AM65_CPSW_QUIRK_I2027_NO_TX_CSUM) 2019 port->ndev->features &= ~NETIF_F_HW_CSUM; 2020 2021 ndev_priv->stats = netdev_alloc_pcpu_stats(struct am65_cpsw_ndev_stats); 2022 if (!ndev_priv->stats) 2023 return -ENOMEM; 2024 2025 ret = devm_add_action_or_reset(dev, am65_cpsw_pcpu_stats_free, 2026 ndev_priv->stats); 2027 if (ret) 2028 dev_err(dev, "failed to add percpu stat free action %d\n", ret); 2029 2030 if (!common->dma_ndev) 2031 common->dma_ndev = port->ndev; 2032 2033 return ret; 2034 } 2035 2036 static int am65_cpsw_nuss_init_ndevs(struct am65_cpsw_common *common) 2037 { 2038 int ret; 2039 int i; 2040 2041 for (i = 0; i < common->port_num; i++) { 2042 ret = am65_cpsw_nuss_init_port_ndev(common, i); 2043 if (ret) 2044 return ret; 2045 } 2046 2047 netif_napi_add(common->dma_ndev, &common->napi_rx, 2048 am65_cpsw_nuss_rx_poll, NAPI_POLL_WEIGHT); 2049 2050 return ret; 2051 } 2052 2053 static int am65_cpsw_nuss_ndev_add_tx_napi(struct am65_cpsw_common *common) 2054 { 2055 struct device *dev = common->dev; 2056 int i, ret = 0; 2057 2058 for (i = 0; i < common->tx_ch_num; i++) { 2059 struct am65_cpsw_tx_chn *tx_chn = &common->tx_chns[i]; 2060 2061 netif_napi_add_tx(common->dma_ndev, &tx_chn->napi_tx, 2062 am65_cpsw_nuss_tx_poll); 2063 2064 ret = devm_request_irq(dev, tx_chn->irq, 2065 am65_cpsw_nuss_tx_irq, 2066 IRQF_TRIGGER_HIGH, 2067 tx_chn->tx_chn_name, tx_chn); 2068 if (ret) { 2069 dev_err(dev, "failure requesting tx%u irq %u, %d\n", 2070 tx_chn->id, tx_chn->irq, ret); 2071 goto err; 2072 } 2073 } 2074 2075 err: 2076 return ret; 2077 } 2078 2079 static void am65_cpsw_nuss_cleanup_ndev(struct am65_cpsw_common *common) 2080 { 2081 struct am65_cpsw_port *port; 2082 int i; 2083 2084 for (i = 0; i < common->port_num; i++) { 2085 port = &common->ports[i]; 2086 if (port->ndev) 2087 unregister_netdev(port->ndev); 2088 } 2089 } 2090 2091 static void am65_cpsw_port_offload_fwd_mark_update(struct am65_cpsw_common *common) 2092 { 2093 int set_val = 0; 2094 int i; 2095 2096 if (common->br_members == (GENMASK(common->port_num, 1) & ~common->disabled_ports_mask)) 2097 set_val = 1; 2098 2099 dev_dbg(common->dev, "set offload_fwd_mark %d\n", set_val); 2100 2101 for (i = 1; i <= common->port_num; i++) { 2102 struct am65_cpsw_port *port = am65_common_get_port(common, i); 2103 struct am65_cpsw_ndev_priv *priv; 2104 2105 if (!port->ndev) 2106 continue; 2107 2108 priv = am65_ndev_to_priv(port->ndev); 2109 priv->offload_fwd_mark = set_val; 2110 } 2111 } 2112 2113 bool am65_cpsw_port_dev_check(const struct net_device *ndev) 2114 { 2115 if (ndev->netdev_ops == &am65_cpsw_nuss_netdev_ops) { 2116 struct am65_cpsw_common *common = am65_ndev_to_common(ndev); 2117 2118 return !common->is_emac_mode; 2119 } 2120 2121 return false; 2122 } 2123 2124 static int am65_cpsw_netdevice_port_link(struct net_device *ndev, 2125 struct net_device *br_ndev, 2126 struct netlink_ext_ack *extack) 2127 { 2128 struct am65_cpsw_common *common = am65_ndev_to_common(ndev); 2129 struct am65_cpsw_ndev_priv *priv = am65_ndev_to_priv(ndev); 2130 int err; 2131 2132 if (!common->br_members) { 2133 common->hw_bridge_dev = br_ndev; 2134 } else { 2135 /* This is adding the port to a second bridge, this is 2136 * unsupported 2137 */ 2138 if (common->hw_bridge_dev != br_ndev) 2139 return -EOPNOTSUPP; 2140 } 2141 2142 err = switchdev_bridge_port_offload(ndev, ndev, NULL, NULL, NULL, 2143 false, extack); 2144 if (err) 2145 return err; 2146 2147 common->br_members |= BIT(priv->port->port_id); 2148 2149 am65_cpsw_port_offload_fwd_mark_update(common); 2150 2151 return NOTIFY_DONE; 2152 } 2153 2154 static void am65_cpsw_netdevice_port_unlink(struct net_device *ndev) 2155 { 2156 struct am65_cpsw_common *common = am65_ndev_to_common(ndev); 2157 struct am65_cpsw_ndev_priv *priv = am65_ndev_to_priv(ndev); 2158 2159 switchdev_bridge_port_unoffload(ndev, NULL, NULL, NULL); 2160 2161 common->br_members &= ~BIT(priv->port->port_id); 2162 2163 am65_cpsw_port_offload_fwd_mark_update(common); 2164 2165 if (!common->br_members) 2166 common->hw_bridge_dev = NULL; 2167 } 2168 2169 /* netdev notifier */ 2170 static int am65_cpsw_netdevice_event(struct notifier_block *unused, 2171 unsigned long event, void *ptr) 2172 { 2173 struct netlink_ext_ack *extack = netdev_notifier_info_to_extack(ptr); 2174 struct net_device *ndev = netdev_notifier_info_to_dev(ptr); 2175 struct netdev_notifier_changeupper_info *info; 2176 int ret = NOTIFY_DONE; 2177 2178 if (!am65_cpsw_port_dev_check(ndev)) 2179 return NOTIFY_DONE; 2180 2181 switch (event) { 2182 case NETDEV_CHANGEUPPER: 2183 info = ptr; 2184 2185 if (netif_is_bridge_master(info->upper_dev)) { 2186 if (info->linking) 2187 ret = am65_cpsw_netdevice_port_link(ndev, 2188 info->upper_dev, 2189 extack); 2190 else 2191 am65_cpsw_netdevice_port_unlink(ndev); 2192 } 2193 break; 2194 default: 2195 return NOTIFY_DONE; 2196 } 2197 2198 return notifier_from_errno(ret); 2199 } 2200 2201 static int am65_cpsw_register_notifiers(struct am65_cpsw_common *cpsw) 2202 { 2203 int ret = 0; 2204 2205 if (AM65_CPSW_IS_CPSW2G(cpsw) || 2206 !IS_REACHABLE(CONFIG_TI_K3_AM65_CPSW_SWITCHDEV)) 2207 return 0; 2208 2209 cpsw->am65_cpsw_netdevice_nb.notifier_call = &am65_cpsw_netdevice_event; 2210 ret = register_netdevice_notifier(&cpsw->am65_cpsw_netdevice_nb); 2211 if (ret) { 2212 dev_err(cpsw->dev, "can't register netdevice notifier\n"); 2213 return ret; 2214 } 2215 2216 ret = am65_cpsw_switchdev_register_notifiers(cpsw); 2217 if (ret) 2218 unregister_netdevice_notifier(&cpsw->am65_cpsw_netdevice_nb); 2219 2220 return ret; 2221 } 2222 2223 static void am65_cpsw_unregister_notifiers(struct am65_cpsw_common *cpsw) 2224 { 2225 if (AM65_CPSW_IS_CPSW2G(cpsw) || 2226 !IS_REACHABLE(CONFIG_TI_K3_AM65_CPSW_SWITCHDEV)) 2227 return; 2228 2229 am65_cpsw_switchdev_unregister_notifiers(cpsw); 2230 unregister_netdevice_notifier(&cpsw->am65_cpsw_netdevice_nb); 2231 } 2232 2233 static const struct devlink_ops am65_cpsw_devlink_ops = {}; 2234 2235 static void am65_cpsw_init_stp_ale_entry(struct am65_cpsw_common *cpsw) 2236 { 2237 cpsw_ale_add_mcast(cpsw->ale, eth_stp_addr, ALE_PORT_HOST, ALE_SUPER, 0, 2238 ALE_MCAST_BLOCK_LEARN_FWD); 2239 } 2240 2241 static void am65_cpsw_init_host_port_switch(struct am65_cpsw_common *common) 2242 { 2243 struct am65_cpsw_host *host = am65_common_get_host(common); 2244 2245 writel(common->default_vlan, host->port_base + AM65_CPSW_PORT_VLAN_REG_OFFSET); 2246 2247 am65_cpsw_init_stp_ale_entry(common); 2248 2249 cpsw_ale_control_set(common->ale, HOST_PORT_NUM, ALE_P0_UNI_FLOOD, 1); 2250 dev_dbg(common->dev, "Set P0_UNI_FLOOD\n"); 2251 cpsw_ale_control_set(common->ale, HOST_PORT_NUM, ALE_PORT_NOLEARN, 0); 2252 } 2253 2254 static void am65_cpsw_init_host_port_emac(struct am65_cpsw_common *common) 2255 { 2256 struct am65_cpsw_host *host = am65_common_get_host(common); 2257 2258 writel(0, host->port_base + AM65_CPSW_PORT_VLAN_REG_OFFSET); 2259 2260 cpsw_ale_control_set(common->ale, HOST_PORT_NUM, ALE_P0_UNI_FLOOD, 0); 2261 dev_dbg(common->dev, "unset P0_UNI_FLOOD\n"); 2262 2263 /* learning make no sense in multi-mac mode */ 2264 cpsw_ale_control_set(common->ale, HOST_PORT_NUM, ALE_PORT_NOLEARN, 1); 2265 } 2266 2267 static int am65_cpsw_dl_switch_mode_get(struct devlink *dl, u32 id, 2268 struct devlink_param_gset_ctx *ctx) 2269 { 2270 struct am65_cpsw_devlink *dl_priv = devlink_priv(dl); 2271 struct am65_cpsw_common *common = dl_priv->common; 2272 2273 dev_dbg(common->dev, "%s id:%u\n", __func__, id); 2274 2275 if (id != AM65_CPSW_DL_PARAM_SWITCH_MODE) 2276 return -EOPNOTSUPP; 2277 2278 ctx->val.vbool = !common->is_emac_mode; 2279 2280 return 0; 2281 } 2282 2283 static void am65_cpsw_init_port_emac_ale(struct am65_cpsw_port *port) 2284 { 2285 struct am65_cpsw_slave_data *slave = &port->slave; 2286 struct am65_cpsw_common *common = port->common; 2287 u32 port_mask; 2288 2289 writel(slave->port_vlan, port->port_base + AM65_CPSW_PORT_VLAN_REG_OFFSET); 2290 2291 if (slave->mac_only) 2292 /* enable mac-only mode on port */ 2293 cpsw_ale_control_set(common->ale, port->port_id, 2294 ALE_PORT_MACONLY, 1); 2295 2296 cpsw_ale_control_set(common->ale, port->port_id, ALE_PORT_NOLEARN, 1); 2297 2298 port_mask = BIT(port->port_id) | ALE_PORT_HOST; 2299 2300 cpsw_ale_add_ucast(common->ale, port->ndev->dev_addr, 2301 HOST_PORT_NUM, ALE_SECURE, slave->port_vlan); 2302 cpsw_ale_add_mcast(common->ale, port->ndev->broadcast, 2303 port_mask, ALE_VLAN, slave->port_vlan, ALE_MCAST_FWD_2); 2304 } 2305 2306 static void am65_cpsw_init_port_switch_ale(struct am65_cpsw_port *port) 2307 { 2308 struct am65_cpsw_slave_data *slave = &port->slave; 2309 struct am65_cpsw_common *cpsw = port->common; 2310 u32 port_mask; 2311 2312 cpsw_ale_control_set(cpsw->ale, port->port_id, 2313 ALE_PORT_NOLEARN, 0); 2314 2315 cpsw_ale_add_ucast(cpsw->ale, port->ndev->dev_addr, 2316 HOST_PORT_NUM, ALE_SECURE | ALE_BLOCKED | ALE_VLAN, 2317 slave->port_vlan); 2318 2319 port_mask = BIT(port->port_id) | ALE_PORT_HOST; 2320 2321 cpsw_ale_add_mcast(cpsw->ale, port->ndev->broadcast, 2322 port_mask, ALE_VLAN, slave->port_vlan, 2323 ALE_MCAST_FWD_2); 2324 2325 writel(slave->port_vlan, port->port_base + AM65_CPSW_PORT_VLAN_REG_OFFSET); 2326 2327 cpsw_ale_control_set(cpsw->ale, port->port_id, 2328 ALE_PORT_MACONLY, 0); 2329 } 2330 2331 static int am65_cpsw_dl_switch_mode_set(struct devlink *dl, u32 id, 2332 struct devlink_param_gset_ctx *ctx) 2333 { 2334 struct am65_cpsw_devlink *dl_priv = devlink_priv(dl); 2335 struct am65_cpsw_common *cpsw = dl_priv->common; 2336 bool switch_en = ctx->val.vbool; 2337 bool if_running = false; 2338 int i; 2339 2340 dev_dbg(cpsw->dev, "%s id:%u\n", __func__, id); 2341 2342 if (id != AM65_CPSW_DL_PARAM_SWITCH_MODE) 2343 return -EOPNOTSUPP; 2344 2345 if (switch_en == !cpsw->is_emac_mode) 2346 return 0; 2347 2348 if (!switch_en && cpsw->br_members) { 2349 dev_err(cpsw->dev, "Remove ports from bridge before disabling switch mode\n"); 2350 return -EINVAL; 2351 } 2352 2353 rtnl_lock(); 2354 2355 cpsw->is_emac_mode = !switch_en; 2356 2357 for (i = 0; i < cpsw->port_num; i++) { 2358 struct net_device *sl_ndev = cpsw->ports[i].ndev; 2359 2360 if (!sl_ndev || !netif_running(sl_ndev)) 2361 continue; 2362 2363 if_running = true; 2364 } 2365 2366 if (!if_running) { 2367 /* all ndevs are down */ 2368 for (i = 0; i < cpsw->port_num; i++) { 2369 struct net_device *sl_ndev = cpsw->ports[i].ndev; 2370 struct am65_cpsw_slave_data *slave; 2371 2372 if (!sl_ndev) 2373 continue; 2374 2375 slave = am65_ndev_to_slave(sl_ndev); 2376 if (switch_en) 2377 slave->port_vlan = cpsw->default_vlan; 2378 else 2379 slave->port_vlan = 0; 2380 } 2381 2382 goto exit; 2383 } 2384 2385 cpsw_ale_control_set(cpsw->ale, 0, ALE_BYPASS, 1); 2386 /* clean up ALE table */ 2387 cpsw_ale_control_set(cpsw->ale, HOST_PORT_NUM, ALE_CLEAR, 1); 2388 cpsw_ale_control_get(cpsw->ale, HOST_PORT_NUM, ALE_AGEOUT); 2389 2390 if (switch_en) { 2391 dev_info(cpsw->dev, "Enable switch mode\n"); 2392 2393 am65_cpsw_init_host_port_switch(cpsw); 2394 2395 for (i = 0; i < cpsw->port_num; i++) { 2396 struct net_device *sl_ndev = cpsw->ports[i].ndev; 2397 struct am65_cpsw_slave_data *slave; 2398 struct am65_cpsw_port *port; 2399 2400 if (!sl_ndev) 2401 continue; 2402 2403 port = am65_ndev_to_port(sl_ndev); 2404 slave = am65_ndev_to_slave(sl_ndev); 2405 slave->port_vlan = cpsw->default_vlan; 2406 2407 if (netif_running(sl_ndev)) 2408 am65_cpsw_init_port_switch_ale(port); 2409 } 2410 2411 } else { 2412 dev_info(cpsw->dev, "Disable switch mode\n"); 2413 2414 am65_cpsw_init_host_port_emac(cpsw); 2415 2416 for (i = 0; i < cpsw->port_num; i++) { 2417 struct net_device *sl_ndev = cpsw->ports[i].ndev; 2418 struct am65_cpsw_port *port; 2419 2420 if (!sl_ndev) 2421 continue; 2422 2423 port = am65_ndev_to_port(sl_ndev); 2424 port->slave.port_vlan = 0; 2425 if (netif_running(sl_ndev)) 2426 am65_cpsw_init_port_emac_ale(port); 2427 } 2428 } 2429 cpsw_ale_control_set(cpsw->ale, HOST_PORT_NUM, ALE_BYPASS, 0); 2430 exit: 2431 rtnl_unlock(); 2432 2433 return 0; 2434 } 2435 2436 static const struct devlink_param am65_cpsw_devlink_params[] = { 2437 DEVLINK_PARAM_DRIVER(AM65_CPSW_DL_PARAM_SWITCH_MODE, "switch_mode", 2438 DEVLINK_PARAM_TYPE_BOOL, 2439 BIT(DEVLINK_PARAM_CMODE_RUNTIME), 2440 am65_cpsw_dl_switch_mode_get, 2441 am65_cpsw_dl_switch_mode_set, NULL), 2442 }; 2443 2444 static int am65_cpsw_nuss_register_devlink(struct am65_cpsw_common *common) 2445 { 2446 struct devlink_port_attrs attrs = {}; 2447 struct am65_cpsw_devlink *dl_priv; 2448 struct device *dev = common->dev; 2449 struct devlink_port *dl_port; 2450 struct am65_cpsw_port *port; 2451 int ret = 0; 2452 int i; 2453 2454 common->devlink = 2455 devlink_alloc(&am65_cpsw_devlink_ops, sizeof(*dl_priv), dev); 2456 if (!common->devlink) 2457 return -ENOMEM; 2458 2459 dl_priv = devlink_priv(common->devlink); 2460 dl_priv->common = common; 2461 2462 /* Provide devlink hook to switch mode when multiple external ports 2463 * are present NUSS switchdev driver is enabled. 2464 */ 2465 if (!AM65_CPSW_IS_CPSW2G(common) && 2466 IS_ENABLED(CONFIG_TI_K3_AM65_CPSW_SWITCHDEV)) { 2467 ret = devlink_params_register(common->devlink, 2468 am65_cpsw_devlink_params, 2469 ARRAY_SIZE(am65_cpsw_devlink_params)); 2470 if (ret) { 2471 dev_err(dev, "devlink params reg fail ret:%d\n", ret); 2472 goto dl_unreg; 2473 } 2474 } 2475 2476 for (i = 1; i <= common->port_num; i++) { 2477 port = am65_common_get_port(common, i); 2478 dl_port = &port->devlink_port; 2479 2480 attrs.flavour = DEVLINK_PORT_FLAVOUR_PHYSICAL; 2481 attrs.phys.port_number = port->port_id; 2482 attrs.switch_id.id_len = sizeof(resource_size_t); 2483 memcpy(attrs.switch_id.id, common->switch_id, attrs.switch_id.id_len); 2484 devlink_port_attrs_set(dl_port, &attrs); 2485 2486 ret = devlink_port_register(common->devlink, dl_port, port->port_id); 2487 if (ret) { 2488 dev_err(dev, "devlink_port reg fail for port %d, ret:%d\n", 2489 port->port_id, ret); 2490 goto dl_port_unreg; 2491 } 2492 } 2493 devlink_register(common->devlink); 2494 return ret; 2495 2496 dl_port_unreg: 2497 for (i = i - 1; i >= 1; i--) { 2498 port = am65_common_get_port(common, i); 2499 dl_port = &port->devlink_port; 2500 2501 devlink_port_unregister(dl_port); 2502 } 2503 dl_unreg: 2504 devlink_free(common->devlink); 2505 return ret; 2506 } 2507 2508 static void am65_cpsw_unregister_devlink(struct am65_cpsw_common *common) 2509 { 2510 struct devlink_port *dl_port; 2511 struct am65_cpsw_port *port; 2512 int i; 2513 2514 devlink_unregister(common->devlink); 2515 2516 for (i = 1; i <= common->port_num; i++) { 2517 port = am65_common_get_port(common, i); 2518 dl_port = &port->devlink_port; 2519 2520 devlink_port_unregister(dl_port); 2521 } 2522 2523 if (!AM65_CPSW_IS_CPSW2G(common) && 2524 IS_ENABLED(CONFIG_TI_K3_AM65_CPSW_SWITCHDEV)) 2525 devlink_params_unregister(common->devlink, 2526 am65_cpsw_devlink_params, 2527 ARRAY_SIZE(am65_cpsw_devlink_params)); 2528 2529 devlink_free(common->devlink); 2530 } 2531 2532 static int am65_cpsw_nuss_register_ndevs(struct am65_cpsw_common *common) 2533 { 2534 struct device *dev = common->dev; 2535 struct devlink_port *dl_port; 2536 struct am65_cpsw_port *port; 2537 int ret = 0, i; 2538 2539 ret = am65_cpsw_nuss_ndev_add_tx_napi(common); 2540 if (ret) 2541 return ret; 2542 2543 ret = devm_request_irq(dev, common->rx_chns.irq, 2544 am65_cpsw_nuss_rx_irq, 2545 IRQF_TRIGGER_HIGH, dev_name(dev), common); 2546 if (ret) { 2547 dev_err(dev, "failure requesting rx irq %u, %d\n", 2548 common->rx_chns.irq, ret); 2549 return ret; 2550 } 2551 2552 ret = am65_cpsw_nuss_register_devlink(common); 2553 if (ret) 2554 return ret; 2555 2556 for (i = 0; i < common->port_num; i++) { 2557 port = &common->ports[i]; 2558 2559 if (!port->ndev) 2560 continue; 2561 2562 ret = register_netdev(port->ndev); 2563 if (ret) { 2564 dev_err(dev, "error registering slave net device%i %d\n", 2565 i, ret); 2566 goto err_cleanup_ndev; 2567 } 2568 2569 dl_port = &port->devlink_port; 2570 devlink_port_type_eth_set(dl_port, port->ndev); 2571 } 2572 2573 ret = am65_cpsw_register_notifiers(common); 2574 if (ret) 2575 goto err_cleanup_ndev; 2576 2577 /* can't auto unregister ndev using devm_add_action() due to 2578 * devres release sequence in DD core for DMA 2579 */ 2580 2581 return 0; 2582 2583 err_cleanup_ndev: 2584 am65_cpsw_nuss_cleanup_ndev(common); 2585 am65_cpsw_unregister_devlink(common); 2586 2587 return ret; 2588 } 2589 2590 int am65_cpsw_nuss_update_tx_chns(struct am65_cpsw_common *common, int num_tx) 2591 { 2592 int ret; 2593 2594 common->tx_ch_num = num_tx; 2595 ret = am65_cpsw_nuss_init_tx_chns(common); 2596 if (ret) 2597 return ret; 2598 2599 return am65_cpsw_nuss_ndev_add_tx_napi(common); 2600 } 2601 2602 struct am65_cpsw_soc_pdata { 2603 u32 quirks_dis; 2604 }; 2605 2606 static const struct am65_cpsw_soc_pdata am65x_soc_sr2_0 = { 2607 .quirks_dis = AM65_CPSW_QUIRK_I2027_NO_TX_CSUM, 2608 }; 2609 2610 static const struct soc_device_attribute am65_cpsw_socinfo[] = { 2611 { .family = "AM65X", 2612 .revision = "SR2.0", 2613 .data = &am65x_soc_sr2_0 2614 }, 2615 {/* sentinel */} 2616 }; 2617 2618 static const struct am65_cpsw_pdata am65x_sr1_0 = { 2619 .quirks = AM65_CPSW_QUIRK_I2027_NO_TX_CSUM, 2620 .ale_dev_id = "am65x-cpsw2g", 2621 .fdqring_mode = K3_RINGACC_RING_MODE_MESSAGE, 2622 }; 2623 2624 static const struct am65_cpsw_pdata j721e_pdata = { 2625 .quirks = 0, 2626 .ale_dev_id = "am65x-cpsw2g", 2627 .fdqring_mode = K3_RINGACC_RING_MODE_MESSAGE, 2628 }; 2629 2630 static const struct am65_cpsw_pdata am64x_cpswxg_pdata = { 2631 .quirks = 0, 2632 .ale_dev_id = "am64-cpswxg", 2633 .fdqring_mode = K3_RINGACC_RING_MODE_RING, 2634 }; 2635 2636 static const struct am65_cpsw_pdata j7200_cpswxg_pdata = { 2637 .quirks = 0, 2638 .ale_dev_id = "am64-cpswxg", 2639 .fdqring_mode = K3_RINGACC_RING_MODE_RING, 2640 .extra_modes = BIT(PHY_INTERFACE_MODE_QSGMII), 2641 }; 2642 2643 static const struct of_device_id am65_cpsw_nuss_of_mtable[] = { 2644 { .compatible = "ti,am654-cpsw-nuss", .data = &am65x_sr1_0}, 2645 { .compatible = "ti,j721e-cpsw-nuss", .data = &j721e_pdata}, 2646 { .compatible = "ti,am642-cpsw-nuss", .data = &am64x_cpswxg_pdata}, 2647 { .compatible = "ti,j7200-cpswxg-nuss", .data = &j7200_cpswxg_pdata}, 2648 { /* sentinel */ }, 2649 }; 2650 MODULE_DEVICE_TABLE(of, am65_cpsw_nuss_of_mtable); 2651 2652 static void am65_cpsw_nuss_apply_socinfo(struct am65_cpsw_common *common) 2653 { 2654 const struct soc_device_attribute *soc; 2655 2656 soc = soc_device_match(am65_cpsw_socinfo); 2657 if (soc && soc->data) { 2658 const struct am65_cpsw_soc_pdata *socdata = soc->data; 2659 2660 /* disable quirks */ 2661 common->pdata.quirks &= ~socdata->quirks_dis; 2662 } 2663 } 2664 2665 static int am65_cpsw_nuss_probe(struct platform_device *pdev) 2666 { 2667 struct cpsw_ale_params ale_params = { 0 }; 2668 const struct of_device_id *of_id; 2669 struct device *dev = &pdev->dev; 2670 struct am65_cpsw_common *common; 2671 struct device_node *node; 2672 struct resource *res; 2673 struct clk *clk; 2674 u64 id_temp; 2675 int ret, i; 2676 2677 common = devm_kzalloc(dev, sizeof(struct am65_cpsw_common), GFP_KERNEL); 2678 if (!common) 2679 return -ENOMEM; 2680 common->dev = dev; 2681 2682 of_id = of_match_device(am65_cpsw_nuss_of_mtable, dev); 2683 if (!of_id) 2684 return -EINVAL; 2685 common->pdata = *(const struct am65_cpsw_pdata *)of_id->data; 2686 2687 am65_cpsw_nuss_apply_socinfo(common); 2688 2689 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cpsw_nuss"); 2690 common->ss_base = devm_ioremap_resource(&pdev->dev, res); 2691 if (IS_ERR(common->ss_base)) 2692 return PTR_ERR(common->ss_base); 2693 common->cpsw_base = common->ss_base + AM65_CPSW_CPSW_NU_BASE; 2694 /* Use device's physical base address as switch id */ 2695 id_temp = cpu_to_be64(res->start); 2696 memcpy(common->switch_id, &id_temp, sizeof(res->start)); 2697 2698 node = of_get_child_by_name(dev->of_node, "ethernet-ports"); 2699 if (!node) 2700 return -ENOENT; 2701 common->port_num = of_get_child_count(node); 2702 of_node_put(node); 2703 if (common->port_num < 1 || common->port_num > AM65_CPSW_MAX_PORTS) 2704 return -ENOENT; 2705 2706 common->rx_flow_id_base = -1; 2707 init_completion(&common->tdown_complete); 2708 common->tx_ch_num = 1; 2709 common->pf_p0_rx_ptype_rrobin = false; 2710 common->default_vlan = 1; 2711 2712 common->ports = devm_kcalloc(dev, common->port_num, 2713 sizeof(*common->ports), 2714 GFP_KERNEL); 2715 if (!common->ports) 2716 return -ENOMEM; 2717 2718 clk = devm_clk_get(dev, "fck"); 2719 if (IS_ERR(clk)) 2720 return dev_err_probe(dev, PTR_ERR(clk), "getting fck clock\n"); 2721 common->bus_freq = clk_get_rate(clk); 2722 2723 pm_runtime_enable(dev); 2724 ret = pm_runtime_resume_and_get(dev); 2725 if (ret < 0) { 2726 pm_runtime_disable(dev); 2727 return ret; 2728 } 2729 2730 node = of_get_child_by_name(dev->of_node, "mdio"); 2731 if (!node) { 2732 dev_warn(dev, "MDIO node not found\n"); 2733 } else if (of_device_is_available(node)) { 2734 struct platform_device *mdio_pdev; 2735 2736 mdio_pdev = of_platform_device_create(node, NULL, dev); 2737 if (!mdio_pdev) { 2738 ret = -ENODEV; 2739 goto err_pm_clear; 2740 } 2741 2742 common->mdio_dev = &mdio_pdev->dev; 2743 } 2744 of_node_put(node); 2745 2746 am65_cpsw_nuss_get_ver(common); 2747 2748 /* init tx channels */ 2749 ret = am65_cpsw_nuss_init_tx_chns(common); 2750 if (ret) 2751 goto err_of_clear; 2752 ret = am65_cpsw_nuss_init_rx_chns(common); 2753 if (ret) 2754 goto err_of_clear; 2755 2756 ret = am65_cpsw_nuss_init_host_p(common); 2757 if (ret) 2758 goto err_of_clear; 2759 2760 ret = am65_cpsw_nuss_init_slave_ports(common); 2761 if (ret) 2762 goto err_of_clear; 2763 2764 /* init common data */ 2765 ale_params.dev = dev; 2766 ale_params.ale_ageout = AM65_CPSW_ALE_AGEOUT_DEFAULT; 2767 ale_params.ale_ports = common->port_num + 1; 2768 ale_params.ale_regs = common->cpsw_base + AM65_CPSW_NU_ALE_BASE; 2769 ale_params.dev_id = common->pdata.ale_dev_id; 2770 ale_params.bus_freq = common->bus_freq; 2771 2772 common->ale = cpsw_ale_create(&ale_params); 2773 if (IS_ERR(common->ale)) { 2774 dev_err(dev, "error initializing ale engine\n"); 2775 ret = PTR_ERR(common->ale); 2776 goto err_of_clear; 2777 } 2778 2779 ret = am65_cpsw_init_cpts(common); 2780 if (ret) 2781 goto err_of_clear; 2782 2783 /* init ports */ 2784 for (i = 0; i < common->port_num; i++) 2785 am65_cpsw_nuss_slave_disable_unused(&common->ports[i]); 2786 2787 dev_set_drvdata(dev, common); 2788 2789 common->is_emac_mode = true; 2790 2791 ret = am65_cpsw_nuss_init_ndevs(common); 2792 if (ret) 2793 goto err_free_phylink; 2794 2795 ret = am65_cpsw_nuss_register_ndevs(common); 2796 if (ret) 2797 goto err_free_phylink; 2798 2799 pm_runtime_put(dev); 2800 return 0; 2801 2802 err_free_phylink: 2803 am65_cpsw_nuss_phylink_cleanup(common); 2804 err_of_clear: 2805 of_platform_device_destroy(common->mdio_dev, NULL); 2806 err_pm_clear: 2807 pm_runtime_put_sync(dev); 2808 pm_runtime_disable(dev); 2809 return ret; 2810 } 2811 2812 static int am65_cpsw_nuss_remove(struct platform_device *pdev) 2813 { 2814 struct device *dev = &pdev->dev; 2815 struct am65_cpsw_common *common; 2816 int ret; 2817 2818 common = dev_get_drvdata(dev); 2819 2820 ret = pm_runtime_resume_and_get(&pdev->dev); 2821 if (ret < 0) 2822 return ret; 2823 2824 am65_cpsw_nuss_phylink_cleanup(common); 2825 am65_cpsw_unregister_devlink(common); 2826 am65_cpsw_unregister_notifiers(common); 2827 2828 /* must unregister ndevs here because DD release_driver routine calls 2829 * dma_deconfigure(dev) before devres_release_all(dev) 2830 */ 2831 am65_cpsw_nuss_cleanup_ndev(common); 2832 2833 of_platform_device_destroy(common->mdio_dev, NULL); 2834 2835 pm_runtime_put_sync(&pdev->dev); 2836 pm_runtime_disable(&pdev->dev); 2837 return 0; 2838 } 2839 2840 static struct platform_driver am65_cpsw_nuss_driver = { 2841 .driver = { 2842 .name = AM65_CPSW_DRV_NAME, 2843 .of_match_table = am65_cpsw_nuss_of_mtable, 2844 }, 2845 .probe = am65_cpsw_nuss_probe, 2846 .remove = am65_cpsw_nuss_remove, 2847 }; 2848 2849 module_platform_driver(am65_cpsw_nuss_driver); 2850 2851 MODULE_LICENSE("GPL v2"); 2852 MODULE_AUTHOR("Grygorii Strashko <grygorii.strashko@ti.com>"); 2853 MODULE_DESCRIPTION("TI AM65 CPSW Ethernet driver"); 2854