1 // SPDX-License-Identifier: GPL-2.0 2 /* Texas Instruments K3 AM65 Ethernet Switch SubSystem Driver 3 * 4 * Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/ 5 * 6 */ 7 8 #include <linux/clk.h> 9 #include <linux/etherdevice.h> 10 #include <linux/if_vlan.h> 11 #include <linux/interrupt.h> 12 #include <linux/irqdomain.h> 13 #include <linux/kernel.h> 14 #include <linux/kmemleak.h> 15 #include <linux/module.h> 16 #include <linux/netdevice.h> 17 #include <linux/net_tstamp.h> 18 #include <linux/of.h> 19 #include <linux/of_mdio.h> 20 #include <linux/of_net.h> 21 #include <linux/of_device.h> 22 #include <linux/phylink.h> 23 #include <linux/phy/phy.h> 24 #include <linux/platform_device.h> 25 #include <linux/pm_runtime.h> 26 #include <linux/regmap.h> 27 #include <linux/rtnetlink.h> 28 #include <linux/mfd/syscon.h> 29 #include <linux/sys_soc.h> 30 #include <linux/dma/ti-cppi5.h> 31 #include <linux/dma/k3-udma-glue.h> 32 #include <net/switchdev.h> 33 34 #include "cpsw_ale.h" 35 #include "cpsw_sl.h" 36 #include "am65-cpsw-nuss.h" 37 #include "am65-cpsw-switchdev.h" 38 #include "k3-cppi-desc-pool.h" 39 #include "am65-cpts.h" 40 41 #define AM65_CPSW_SS_BASE 0x0 42 #define AM65_CPSW_SGMII_BASE 0x100 43 #define AM65_CPSW_XGMII_BASE 0x2100 44 #define AM65_CPSW_CPSW_NU_BASE 0x20000 45 #define AM65_CPSW_NU_PORTS_BASE 0x1000 46 #define AM65_CPSW_NU_FRAM_BASE 0x12000 47 #define AM65_CPSW_NU_STATS_BASE 0x1a000 48 #define AM65_CPSW_NU_ALE_BASE 0x1e000 49 #define AM65_CPSW_NU_CPTS_BASE 0x1d000 50 51 #define AM65_CPSW_NU_PORTS_OFFSET 0x1000 52 #define AM65_CPSW_NU_STATS_PORT_OFFSET 0x200 53 #define AM65_CPSW_NU_FRAM_PORT_OFFSET 0x200 54 55 #define AM65_CPSW_MAX_PORTS 8 56 57 #define AM65_CPSW_MIN_PACKET_SIZE VLAN_ETH_ZLEN 58 #define AM65_CPSW_MAX_PACKET_SIZE (VLAN_ETH_FRAME_LEN + ETH_FCS_LEN) 59 60 #define AM65_CPSW_REG_CTL 0x004 61 #define AM65_CPSW_REG_STAT_PORT_EN 0x014 62 #define AM65_CPSW_REG_PTYPE 0x018 63 64 #define AM65_CPSW_P0_REG_CTL 0x004 65 #define AM65_CPSW_PORT0_REG_FLOW_ID_OFFSET 0x008 66 67 #define AM65_CPSW_PORT_REG_PRI_CTL 0x01c 68 #define AM65_CPSW_PORT_REG_RX_PRI_MAP 0x020 69 #define AM65_CPSW_PORT_REG_RX_MAXLEN 0x024 70 71 #define AM65_CPSW_PORTN_REG_SA_L 0x308 72 #define AM65_CPSW_PORTN_REG_SA_H 0x30c 73 #define AM65_CPSW_PORTN_REG_TS_CTL 0x310 74 #define AM65_CPSW_PORTN_REG_TS_SEQ_LTYPE_REG 0x314 75 #define AM65_CPSW_PORTN_REG_TS_VLAN_LTYPE_REG 0x318 76 #define AM65_CPSW_PORTN_REG_TS_CTL_LTYPE2 0x31C 77 78 #define AM65_CPSW_SGMII_CONTROL_REG 0x010 79 #define AM65_CPSW_SGMII_CONTROL_MR_AN_ENABLE BIT(0) 80 81 #define AM65_CPSW_CTL_VLAN_AWARE BIT(1) 82 #define AM65_CPSW_CTL_P0_ENABLE BIT(2) 83 #define AM65_CPSW_CTL_P0_TX_CRC_REMOVE BIT(13) 84 #define AM65_CPSW_CTL_P0_RX_PAD BIT(14) 85 86 /* AM65_CPSW_P0_REG_CTL */ 87 #define AM65_CPSW_P0_REG_CTL_RX_CHECKSUM_EN BIT(0) 88 89 /* AM65_CPSW_PORT_REG_PRI_CTL */ 90 #define AM65_CPSW_PORT_REG_PRI_CTL_RX_PTYPE_RROBIN BIT(8) 91 92 /* AM65_CPSW_PN_TS_CTL register fields */ 93 #define AM65_CPSW_PN_TS_CTL_TX_ANX_F_EN BIT(4) 94 #define AM65_CPSW_PN_TS_CTL_TX_VLAN_LT1_EN BIT(5) 95 #define AM65_CPSW_PN_TS_CTL_TX_VLAN_LT2_EN BIT(6) 96 #define AM65_CPSW_PN_TS_CTL_TX_ANX_D_EN BIT(7) 97 #define AM65_CPSW_PN_TS_CTL_TX_ANX_E_EN BIT(10) 98 #define AM65_CPSW_PN_TS_CTL_TX_HOST_TS_EN BIT(11) 99 #define AM65_CPSW_PN_TS_CTL_MSG_TYPE_EN_SHIFT 16 100 101 /* AM65_CPSW_PORTN_REG_TS_SEQ_LTYPE_REG register fields */ 102 #define AM65_CPSW_PN_TS_SEQ_ID_OFFSET_SHIFT 16 103 104 /* AM65_CPSW_PORTN_REG_TS_CTL_LTYPE2 */ 105 #define AM65_CPSW_PN_TS_CTL_LTYPE2_TS_107 BIT(16) 106 #define AM65_CPSW_PN_TS_CTL_LTYPE2_TS_129 BIT(17) 107 #define AM65_CPSW_PN_TS_CTL_LTYPE2_TS_130 BIT(18) 108 #define AM65_CPSW_PN_TS_CTL_LTYPE2_TS_131 BIT(19) 109 #define AM65_CPSW_PN_TS_CTL_LTYPE2_TS_132 BIT(20) 110 #define AM65_CPSW_PN_TS_CTL_LTYPE2_TS_319 BIT(21) 111 #define AM65_CPSW_PN_TS_CTL_LTYPE2_TS_320 BIT(22) 112 #define AM65_CPSW_PN_TS_CTL_LTYPE2_TS_TTL_NONZERO BIT(23) 113 114 /* The PTP event messages - Sync, Delay_Req, Pdelay_Req, and Pdelay_Resp. */ 115 #define AM65_CPSW_TS_EVENT_MSG_TYPE_BITS (BIT(0) | BIT(1) | BIT(2) | BIT(3)) 116 117 #define AM65_CPSW_TS_SEQ_ID_OFFSET (0x1e) 118 119 #define AM65_CPSW_TS_TX_ANX_ALL_EN \ 120 (AM65_CPSW_PN_TS_CTL_TX_ANX_D_EN | \ 121 AM65_CPSW_PN_TS_CTL_TX_ANX_E_EN | \ 122 AM65_CPSW_PN_TS_CTL_TX_ANX_F_EN) 123 124 #define AM65_CPSW_ALE_AGEOUT_DEFAULT 30 125 /* Number of TX/RX descriptors */ 126 #define AM65_CPSW_MAX_TX_DESC 500 127 #define AM65_CPSW_MAX_RX_DESC 500 128 129 #define AM65_CPSW_NAV_PS_DATA_SIZE 16 130 #define AM65_CPSW_NAV_SW_DATA_SIZE 16 131 132 #define AM65_CPSW_DEBUG (NETIF_MSG_HW | NETIF_MSG_DRV | NETIF_MSG_LINK | \ 133 NETIF_MSG_IFUP | NETIF_MSG_PROBE | NETIF_MSG_IFDOWN | \ 134 NETIF_MSG_RX_ERR | NETIF_MSG_TX_ERR) 135 136 static void am65_cpsw_port_set_sl_mac(struct am65_cpsw_port *slave, 137 const u8 *dev_addr) 138 { 139 u32 mac_hi = (dev_addr[0] << 0) | (dev_addr[1] << 8) | 140 (dev_addr[2] << 16) | (dev_addr[3] << 24); 141 u32 mac_lo = (dev_addr[4] << 0) | (dev_addr[5] << 8); 142 143 writel(mac_hi, slave->port_base + AM65_CPSW_PORTN_REG_SA_H); 144 writel(mac_lo, slave->port_base + AM65_CPSW_PORTN_REG_SA_L); 145 } 146 147 static void am65_cpsw_sl_ctl_reset(struct am65_cpsw_port *port) 148 { 149 cpsw_sl_reset(port->slave.mac_sl, 100); 150 /* Max length register has to be restored after MAC SL reset */ 151 writel(AM65_CPSW_MAX_PACKET_SIZE, 152 port->port_base + AM65_CPSW_PORT_REG_RX_MAXLEN); 153 } 154 155 static void am65_cpsw_nuss_get_ver(struct am65_cpsw_common *common) 156 { 157 common->nuss_ver = readl(common->ss_base); 158 common->cpsw_ver = readl(common->cpsw_base); 159 dev_info(common->dev, 160 "initializing am65 cpsw nuss version 0x%08X, cpsw version 0x%08X Ports: %u quirks:%08x\n", 161 common->nuss_ver, 162 common->cpsw_ver, 163 common->port_num + 1, 164 common->pdata.quirks); 165 } 166 167 static int am65_cpsw_nuss_ndo_slave_add_vid(struct net_device *ndev, 168 __be16 proto, u16 vid) 169 { 170 struct am65_cpsw_common *common = am65_ndev_to_common(ndev); 171 struct am65_cpsw_port *port = am65_ndev_to_port(ndev); 172 u32 port_mask, unreg_mcast = 0; 173 int ret; 174 175 if (!common->is_emac_mode) 176 return 0; 177 178 if (!netif_running(ndev) || !vid) 179 return 0; 180 181 ret = pm_runtime_resume_and_get(common->dev); 182 if (ret < 0) 183 return ret; 184 185 port_mask = BIT(port->port_id) | ALE_PORT_HOST; 186 if (!vid) 187 unreg_mcast = port_mask; 188 dev_info(common->dev, "Adding vlan %d to vlan filter\n", vid); 189 ret = cpsw_ale_vlan_add_modify(common->ale, vid, port_mask, 190 unreg_mcast, port_mask, 0); 191 192 pm_runtime_put(common->dev); 193 return ret; 194 } 195 196 static int am65_cpsw_nuss_ndo_slave_kill_vid(struct net_device *ndev, 197 __be16 proto, u16 vid) 198 { 199 struct am65_cpsw_common *common = am65_ndev_to_common(ndev); 200 struct am65_cpsw_port *port = am65_ndev_to_port(ndev); 201 int ret; 202 203 if (!common->is_emac_mode) 204 return 0; 205 206 if (!netif_running(ndev) || !vid) 207 return 0; 208 209 ret = pm_runtime_resume_and_get(common->dev); 210 if (ret < 0) 211 return ret; 212 213 dev_info(common->dev, "Removing vlan %d from vlan filter\n", vid); 214 ret = cpsw_ale_del_vlan(common->ale, vid, 215 BIT(port->port_id) | ALE_PORT_HOST); 216 217 pm_runtime_put(common->dev); 218 return ret; 219 } 220 221 static void am65_cpsw_slave_set_promisc(struct am65_cpsw_port *port, 222 bool promisc) 223 { 224 struct am65_cpsw_common *common = port->common; 225 226 if (promisc && !common->is_emac_mode) { 227 dev_dbg(common->dev, "promisc mode requested in switch mode"); 228 return; 229 } 230 231 if (promisc) { 232 /* Enable promiscuous mode */ 233 cpsw_ale_control_set(common->ale, port->port_id, 234 ALE_PORT_MACONLY_CAF, 1); 235 dev_dbg(common->dev, "promisc enabled\n"); 236 } else { 237 /* Disable promiscuous mode */ 238 cpsw_ale_control_set(common->ale, port->port_id, 239 ALE_PORT_MACONLY_CAF, 0); 240 dev_dbg(common->dev, "promisc disabled\n"); 241 } 242 } 243 244 static void am65_cpsw_nuss_ndo_slave_set_rx_mode(struct net_device *ndev) 245 { 246 struct am65_cpsw_common *common = am65_ndev_to_common(ndev); 247 struct am65_cpsw_port *port = am65_ndev_to_port(ndev); 248 u32 port_mask; 249 bool promisc; 250 251 promisc = !!(ndev->flags & IFF_PROMISC); 252 am65_cpsw_slave_set_promisc(port, promisc); 253 254 if (promisc) 255 return; 256 257 /* Restore allmulti on vlans if necessary */ 258 cpsw_ale_set_allmulti(common->ale, 259 ndev->flags & IFF_ALLMULTI, port->port_id); 260 261 port_mask = ALE_PORT_HOST; 262 /* Clear all mcast from ALE */ 263 cpsw_ale_flush_multicast(common->ale, port_mask, -1); 264 265 if (!netdev_mc_empty(ndev)) { 266 struct netdev_hw_addr *ha; 267 268 /* program multicast address list into ALE register */ 269 netdev_for_each_mc_addr(ha, ndev) { 270 cpsw_ale_add_mcast(common->ale, ha->addr, 271 port_mask, 0, 0, 0); 272 } 273 } 274 } 275 276 static void am65_cpsw_nuss_ndo_host_tx_timeout(struct net_device *ndev, 277 unsigned int txqueue) 278 { 279 struct am65_cpsw_common *common = am65_ndev_to_common(ndev); 280 struct am65_cpsw_tx_chn *tx_chn; 281 struct netdev_queue *netif_txq; 282 unsigned long trans_start; 283 284 netif_txq = netdev_get_tx_queue(ndev, txqueue); 285 tx_chn = &common->tx_chns[txqueue]; 286 trans_start = READ_ONCE(netif_txq->trans_start); 287 288 netdev_err(ndev, "txq:%d DRV_XOFF:%d tmo:%u dql_avail:%d free_desc:%zu\n", 289 txqueue, 290 netif_tx_queue_stopped(netif_txq), 291 jiffies_to_msecs(jiffies - trans_start), 292 dql_avail(&netif_txq->dql), 293 k3_cppi_desc_pool_avail(tx_chn->desc_pool)); 294 295 if (netif_tx_queue_stopped(netif_txq)) { 296 /* try recover if stopped by us */ 297 txq_trans_update(netif_txq); 298 netif_tx_wake_queue(netif_txq); 299 } 300 } 301 302 static int am65_cpsw_nuss_rx_push(struct am65_cpsw_common *common, 303 struct sk_buff *skb) 304 { 305 struct am65_cpsw_rx_chn *rx_chn = &common->rx_chns; 306 struct cppi5_host_desc_t *desc_rx; 307 struct device *dev = common->dev; 308 u32 pkt_len = skb_tailroom(skb); 309 dma_addr_t desc_dma; 310 dma_addr_t buf_dma; 311 void *swdata; 312 313 desc_rx = k3_cppi_desc_pool_alloc(rx_chn->desc_pool); 314 if (!desc_rx) { 315 dev_err(dev, "Failed to allocate RXFDQ descriptor\n"); 316 return -ENOMEM; 317 } 318 desc_dma = k3_cppi_desc_pool_virt2dma(rx_chn->desc_pool, desc_rx); 319 320 buf_dma = dma_map_single(rx_chn->dma_dev, skb->data, pkt_len, 321 DMA_FROM_DEVICE); 322 if (unlikely(dma_mapping_error(rx_chn->dma_dev, buf_dma))) { 323 k3_cppi_desc_pool_free(rx_chn->desc_pool, desc_rx); 324 dev_err(dev, "Failed to map rx skb buffer\n"); 325 return -EINVAL; 326 } 327 328 cppi5_hdesc_init(desc_rx, CPPI5_INFO0_HDESC_EPIB_PRESENT, 329 AM65_CPSW_NAV_PS_DATA_SIZE); 330 k3_udma_glue_rx_dma_to_cppi5_addr(rx_chn->rx_chn, &buf_dma); 331 cppi5_hdesc_attach_buf(desc_rx, buf_dma, skb_tailroom(skb), buf_dma, skb_tailroom(skb)); 332 swdata = cppi5_hdesc_get_swdata(desc_rx); 333 *((void **)swdata) = skb; 334 335 return k3_udma_glue_push_rx_chn(rx_chn->rx_chn, 0, desc_rx, desc_dma); 336 } 337 338 void am65_cpsw_nuss_set_p0_ptype(struct am65_cpsw_common *common) 339 { 340 struct am65_cpsw_host *host_p = am65_common_get_host(common); 341 u32 val, pri_map; 342 343 /* P0 set Receive Priority Type */ 344 val = readl(host_p->port_base + AM65_CPSW_PORT_REG_PRI_CTL); 345 346 if (common->pf_p0_rx_ptype_rrobin) { 347 val |= AM65_CPSW_PORT_REG_PRI_CTL_RX_PTYPE_RROBIN; 348 /* Enet Ports fifos works in fixed priority mode only, so 349 * reset P0_Rx_Pri_Map so all packet will go in Enet fifo 0 350 */ 351 pri_map = 0x0; 352 } else { 353 val &= ~AM65_CPSW_PORT_REG_PRI_CTL_RX_PTYPE_RROBIN; 354 /* restore P0_Rx_Pri_Map */ 355 pri_map = 0x76543210; 356 } 357 358 writel(pri_map, host_p->port_base + AM65_CPSW_PORT_REG_RX_PRI_MAP); 359 writel(val, host_p->port_base + AM65_CPSW_PORT_REG_PRI_CTL); 360 } 361 362 static void am65_cpsw_init_host_port_switch(struct am65_cpsw_common *common); 363 static void am65_cpsw_init_host_port_emac(struct am65_cpsw_common *common); 364 static void am65_cpsw_init_port_switch_ale(struct am65_cpsw_port *port); 365 static void am65_cpsw_init_port_emac_ale(struct am65_cpsw_port *port); 366 367 static int am65_cpsw_nuss_common_open(struct am65_cpsw_common *common) 368 { 369 struct am65_cpsw_host *host_p = am65_common_get_host(common); 370 int port_idx, i, ret; 371 struct sk_buff *skb; 372 u32 val, port_mask; 373 374 if (common->usage_count) 375 return 0; 376 377 /* Control register */ 378 writel(AM65_CPSW_CTL_P0_ENABLE | AM65_CPSW_CTL_P0_TX_CRC_REMOVE | 379 AM65_CPSW_CTL_VLAN_AWARE | AM65_CPSW_CTL_P0_RX_PAD, 380 common->cpsw_base + AM65_CPSW_REG_CTL); 381 /* Max length register */ 382 writel(AM65_CPSW_MAX_PACKET_SIZE, 383 host_p->port_base + AM65_CPSW_PORT_REG_RX_MAXLEN); 384 /* set base flow_id */ 385 writel(common->rx_flow_id_base, 386 host_p->port_base + AM65_CPSW_PORT0_REG_FLOW_ID_OFFSET); 387 /* en tx crc offload */ 388 writel(AM65_CPSW_P0_REG_CTL_RX_CHECKSUM_EN, host_p->port_base + AM65_CPSW_P0_REG_CTL); 389 390 am65_cpsw_nuss_set_p0_ptype(common); 391 392 /* enable statistic */ 393 val = BIT(HOST_PORT_NUM); 394 for (port_idx = 0; port_idx < common->port_num; port_idx++) { 395 struct am65_cpsw_port *port = &common->ports[port_idx]; 396 397 if (!port->disabled) 398 val |= BIT(port->port_id); 399 } 400 writel(val, common->cpsw_base + AM65_CPSW_REG_STAT_PORT_EN); 401 402 /* disable priority elevation */ 403 writel(0, common->cpsw_base + AM65_CPSW_REG_PTYPE); 404 405 cpsw_ale_start(common->ale); 406 407 /* limit to one RX flow only */ 408 cpsw_ale_control_set(common->ale, HOST_PORT_NUM, 409 ALE_DEFAULT_THREAD_ID, 0); 410 cpsw_ale_control_set(common->ale, HOST_PORT_NUM, 411 ALE_DEFAULT_THREAD_ENABLE, 1); 412 /* switch to vlan unaware mode */ 413 cpsw_ale_control_set(common->ale, HOST_PORT_NUM, ALE_VLAN_AWARE, 1); 414 cpsw_ale_control_set(common->ale, HOST_PORT_NUM, 415 ALE_PORT_STATE, ALE_PORT_STATE_FORWARD); 416 417 /* default vlan cfg: create mask based on enabled ports */ 418 port_mask = GENMASK(common->port_num, 0) & 419 ~common->disabled_ports_mask; 420 421 cpsw_ale_add_vlan(common->ale, 0, port_mask, 422 port_mask, port_mask, 423 port_mask & ~ALE_PORT_HOST); 424 425 if (common->is_emac_mode) 426 am65_cpsw_init_host_port_emac(common); 427 else 428 am65_cpsw_init_host_port_switch(common); 429 430 for (i = 0; i < common->rx_chns.descs_num; i++) { 431 skb = __netdev_alloc_skb_ip_align(NULL, 432 AM65_CPSW_MAX_PACKET_SIZE, 433 GFP_KERNEL); 434 if (!skb) { 435 dev_err(common->dev, "cannot allocate skb\n"); 436 return -ENOMEM; 437 } 438 439 ret = am65_cpsw_nuss_rx_push(common, skb); 440 if (ret < 0) { 441 dev_err(common->dev, 442 "cannot submit skb to channel rx, error %d\n", 443 ret); 444 kfree_skb(skb); 445 return ret; 446 } 447 kmemleak_not_leak(skb); 448 } 449 k3_udma_glue_enable_rx_chn(common->rx_chns.rx_chn); 450 451 for (i = 0; i < common->tx_ch_num; i++) { 452 ret = k3_udma_glue_enable_tx_chn(common->tx_chns[i].tx_chn); 453 if (ret) 454 return ret; 455 napi_enable(&common->tx_chns[i].napi_tx); 456 } 457 458 napi_enable(&common->napi_rx); 459 if (common->rx_irq_disabled) { 460 common->rx_irq_disabled = false; 461 enable_irq(common->rx_chns.irq); 462 } 463 464 dev_dbg(common->dev, "cpsw_nuss started\n"); 465 return 0; 466 } 467 468 static void am65_cpsw_nuss_tx_cleanup(void *data, dma_addr_t desc_dma); 469 static void am65_cpsw_nuss_rx_cleanup(void *data, dma_addr_t desc_dma); 470 471 static int am65_cpsw_nuss_common_stop(struct am65_cpsw_common *common) 472 { 473 int i; 474 475 if (common->usage_count != 1) 476 return 0; 477 478 cpsw_ale_control_set(common->ale, HOST_PORT_NUM, 479 ALE_PORT_STATE, ALE_PORT_STATE_DISABLE); 480 481 /* shutdown tx channels */ 482 atomic_set(&common->tdown_cnt, common->tx_ch_num); 483 /* ensure new tdown_cnt value is visible */ 484 smp_mb__after_atomic(); 485 reinit_completion(&common->tdown_complete); 486 487 for (i = 0; i < common->tx_ch_num; i++) 488 k3_udma_glue_tdown_tx_chn(common->tx_chns[i].tx_chn, false); 489 490 i = wait_for_completion_timeout(&common->tdown_complete, 491 msecs_to_jiffies(1000)); 492 if (!i) 493 dev_err(common->dev, "tx timeout\n"); 494 for (i = 0; i < common->tx_ch_num; i++) 495 napi_disable(&common->tx_chns[i].napi_tx); 496 497 for (i = 0; i < common->tx_ch_num; i++) { 498 k3_udma_glue_reset_tx_chn(common->tx_chns[i].tx_chn, 499 &common->tx_chns[i], 500 am65_cpsw_nuss_tx_cleanup); 501 k3_udma_glue_disable_tx_chn(common->tx_chns[i].tx_chn); 502 } 503 504 k3_udma_glue_tdown_rx_chn(common->rx_chns.rx_chn, true); 505 napi_disable(&common->napi_rx); 506 507 for (i = 0; i < AM65_CPSW_MAX_RX_FLOWS; i++) 508 k3_udma_glue_reset_rx_chn(common->rx_chns.rx_chn, i, 509 &common->rx_chns, 510 am65_cpsw_nuss_rx_cleanup, !!i); 511 512 k3_udma_glue_disable_rx_chn(common->rx_chns.rx_chn); 513 514 cpsw_ale_stop(common->ale); 515 516 writel(0, common->cpsw_base + AM65_CPSW_REG_CTL); 517 writel(0, common->cpsw_base + AM65_CPSW_REG_STAT_PORT_EN); 518 519 dev_dbg(common->dev, "cpsw_nuss stopped\n"); 520 return 0; 521 } 522 523 static int am65_cpsw_nuss_ndo_slave_stop(struct net_device *ndev) 524 { 525 struct am65_cpsw_common *common = am65_ndev_to_common(ndev); 526 struct am65_cpsw_port *port = am65_ndev_to_port(ndev); 527 int ret; 528 529 phylink_stop(port->slave.phylink); 530 531 netif_tx_stop_all_queues(ndev); 532 533 phylink_disconnect_phy(port->slave.phylink); 534 535 ret = am65_cpsw_nuss_common_stop(common); 536 if (ret) 537 return ret; 538 539 common->usage_count--; 540 pm_runtime_put(common->dev); 541 return 0; 542 } 543 544 static int cpsw_restore_vlans(struct net_device *vdev, int vid, void *arg) 545 { 546 struct am65_cpsw_port *port = arg; 547 548 if (!vdev) 549 return 0; 550 551 return am65_cpsw_nuss_ndo_slave_add_vid(port->ndev, 0, vid); 552 } 553 554 static int am65_cpsw_nuss_ndo_slave_open(struct net_device *ndev) 555 { 556 struct am65_cpsw_common *common = am65_ndev_to_common(ndev); 557 struct am65_cpsw_port *port = am65_ndev_to_port(ndev); 558 int ret, i; 559 u32 reg; 560 561 ret = pm_runtime_resume_and_get(common->dev); 562 if (ret < 0) 563 return ret; 564 565 /* Idle MAC port */ 566 cpsw_sl_ctl_set(port->slave.mac_sl, CPSW_SL_CTL_CMD_IDLE); 567 cpsw_sl_wait_for_idle(port->slave.mac_sl, 100); 568 cpsw_sl_ctl_reset(port->slave.mac_sl); 569 570 /* soft reset MAC */ 571 cpsw_sl_reg_write(port->slave.mac_sl, CPSW_SL_SOFT_RESET, 1); 572 mdelay(1); 573 reg = cpsw_sl_reg_read(port->slave.mac_sl, CPSW_SL_SOFT_RESET); 574 if (reg) { 575 dev_err(common->dev, "soft RESET didn't complete\n"); 576 ret = -ETIMEDOUT; 577 goto runtime_put; 578 } 579 580 /* Notify the stack of the actual queue counts. */ 581 ret = netif_set_real_num_tx_queues(ndev, common->tx_ch_num); 582 if (ret) { 583 dev_err(common->dev, "cannot set real number of tx queues\n"); 584 goto runtime_put; 585 } 586 587 ret = netif_set_real_num_rx_queues(ndev, AM65_CPSW_MAX_RX_QUEUES); 588 if (ret) { 589 dev_err(common->dev, "cannot set real number of rx queues\n"); 590 goto runtime_put; 591 } 592 593 for (i = 0; i < common->tx_ch_num; i++) 594 netdev_tx_reset_queue(netdev_get_tx_queue(ndev, i)); 595 596 ret = am65_cpsw_nuss_common_open(common); 597 if (ret) 598 goto runtime_put; 599 600 common->usage_count++; 601 602 am65_cpsw_port_set_sl_mac(port, ndev->dev_addr); 603 604 if (common->is_emac_mode) 605 am65_cpsw_init_port_emac_ale(port); 606 else 607 am65_cpsw_init_port_switch_ale(port); 608 609 /* mac_sl should be configured via phy-link interface */ 610 am65_cpsw_sl_ctl_reset(port); 611 612 ret = phylink_of_phy_connect(port->slave.phylink, port->slave.phy_node, 0); 613 if (ret) 614 goto error_cleanup; 615 616 /* restore vlan configurations */ 617 vlan_for_each(ndev, cpsw_restore_vlans, port); 618 619 phylink_start(port->slave.phylink); 620 621 return 0; 622 623 error_cleanup: 624 am65_cpsw_nuss_ndo_slave_stop(ndev); 625 return ret; 626 627 runtime_put: 628 pm_runtime_put(common->dev); 629 return ret; 630 } 631 632 static void am65_cpsw_nuss_rx_cleanup(void *data, dma_addr_t desc_dma) 633 { 634 struct am65_cpsw_rx_chn *rx_chn = data; 635 struct cppi5_host_desc_t *desc_rx; 636 struct sk_buff *skb; 637 dma_addr_t buf_dma; 638 u32 buf_dma_len; 639 void **swdata; 640 641 desc_rx = k3_cppi_desc_pool_dma2virt(rx_chn->desc_pool, desc_dma); 642 swdata = cppi5_hdesc_get_swdata(desc_rx); 643 skb = *swdata; 644 cppi5_hdesc_get_obuf(desc_rx, &buf_dma, &buf_dma_len); 645 k3_udma_glue_rx_cppi5_to_dma_addr(rx_chn->rx_chn, &buf_dma); 646 647 dma_unmap_single(rx_chn->dma_dev, buf_dma, buf_dma_len, DMA_FROM_DEVICE); 648 k3_cppi_desc_pool_free(rx_chn->desc_pool, desc_rx); 649 650 dev_kfree_skb_any(skb); 651 } 652 653 static void am65_cpsw_nuss_rx_ts(struct sk_buff *skb, u32 *psdata) 654 { 655 struct skb_shared_hwtstamps *ssh; 656 u64 ns; 657 658 ns = ((u64)psdata[1] << 32) | psdata[0]; 659 660 ssh = skb_hwtstamps(skb); 661 memset(ssh, 0, sizeof(*ssh)); 662 ssh->hwtstamp = ns_to_ktime(ns); 663 } 664 665 /* RX psdata[2] word format - checksum information */ 666 #define AM65_CPSW_RX_PSD_CSUM_ADD GENMASK(15, 0) 667 #define AM65_CPSW_RX_PSD_CSUM_ERR BIT(16) 668 #define AM65_CPSW_RX_PSD_IS_FRAGMENT BIT(17) 669 #define AM65_CPSW_RX_PSD_IS_TCP BIT(18) 670 #define AM65_CPSW_RX_PSD_IPV6_VALID BIT(19) 671 #define AM65_CPSW_RX_PSD_IPV4_VALID BIT(20) 672 673 static void am65_cpsw_nuss_rx_csum(struct sk_buff *skb, u32 csum_info) 674 { 675 /* HW can verify IPv4/IPv6 TCP/UDP packets checksum 676 * csum information provides in psdata[2] word: 677 * AM65_CPSW_RX_PSD_CSUM_ERR bit - indicates csum error 678 * AM65_CPSW_RX_PSD_IPV6_VALID and AM65_CPSW_RX_PSD_IPV4_VALID 679 * bits - indicates IPv4/IPv6 packet 680 * AM65_CPSW_RX_PSD_IS_FRAGMENT bit - indicates fragmented packet 681 * AM65_CPSW_RX_PSD_CSUM_ADD has value 0xFFFF for non fragmented packets 682 * or csum value for fragmented packets if !AM65_CPSW_RX_PSD_CSUM_ERR 683 */ 684 skb_checksum_none_assert(skb); 685 686 if (unlikely(!(skb->dev->features & NETIF_F_RXCSUM))) 687 return; 688 689 if ((csum_info & (AM65_CPSW_RX_PSD_IPV6_VALID | 690 AM65_CPSW_RX_PSD_IPV4_VALID)) && 691 !(csum_info & AM65_CPSW_RX_PSD_CSUM_ERR)) { 692 /* csum for fragmented packets is unsupported */ 693 if (!(csum_info & AM65_CPSW_RX_PSD_IS_FRAGMENT)) 694 skb->ip_summed = CHECKSUM_UNNECESSARY; 695 } 696 } 697 698 static int am65_cpsw_nuss_rx_packets(struct am65_cpsw_common *common, 699 u32 flow_idx) 700 { 701 struct am65_cpsw_rx_chn *rx_chn = &common->rx_chns; 702 u32 buf_dma_len, pkt_len, port_id = 0, csum_info; 703 struct am65_cpsw_ndev_priv *ndev_priv; 704 struct am65_cpsw_ndev_stats *stats; 705 struct cppi5_host_desc_t *desc_rx; 706 struct device *dev = common->dev; 707 struct sk_buff *skb, *new_skb; 708 dma_addr_t desc_dma, buf_dma; 709 struct am65_cpsw_port *port; 710 struct net_device *ndev; 711 void **swdata; 712 u32 *psdata; 713 int ret = 0; 714 715 ret = k3_udma_glue_pop_rx_chn(rx_chn->rx_chn, flow_idx, &desc_dma); 716 if (ret) { 717 if (ret != -ENODATA) 718 dev_err(dev, "RX: pop chn fail %d\n", ret); 719 return ret; 720 } 721 722 if (cppi5_desc_is_tdcm(desc_dma)) { 723 dev_dbg(dev, "%s RX tdown flow: %u\n", __func__, flow_idx); 724 return 0; 725 } 726 727 desc_rx = k3_cppi_desc_pool_dma2virt(rx_chn->desc_pool, desc_dma); 728 dev_dbg(dev, "%s flow_idx: %u desc %pad\n", 729 __func__, flow_idx, &desc_dma); 730 731 swdata = cppi5_hdesc_get_swdata(desc_rx); 732 skb = *swdata; 733 cppi5_hdesc_get_obuf(desc_rx, &buf_dma, &buf_dma_len); 734 k3_udma_glue_rx_cppi5_to_dma_addr(rx_chn->rx_chn, &buf_dma); 735 pkt_len = cppi5_hdesc_get_pktlen(desc_rx); 736 cppi5_desc_get_tags_ids(&desc_rx->hdr, &port_id, NULL); 737 dev_dbg(dev, "%s rx port_id:%d\n", __func__, port_id); 738 port = am65_common_get_port(common, port_id); 739 ndev = port->ndev; 740 skb->dev = ndev; 741 742 psdata = cppi5_hdesc_get_psdata(desc_rx); 743 /* add RX timestamp */ 744 if (port->rx_ts_enabled) 745 am65_cpsw_nuss_rx_ts(skb, psdata); 746 csum_info = psdata[2]; 747 dev_dbg(dev, "%s rx csum_info:%#x\n", __func__, csum_info); 748 749 dma_unmap_single(rx_chn->dma_dev, buf_dma, buf_dma_len, DMA_FROM_DEVICE); 750 751 k3_cppi_desc_pool_free(rx_chn->desc_pool, desc_rx); 752 753 new_skb = netdev_alloc_skb_ip_align(ndev, AM65_CPSW_MAX_PACKET_SIZE); 754 if (new_skb) { 755 ndev_priv = netdev_priv(ndev); 756 am65_cpsw_nuss_set_offload_fwd_mark(skb, ndev_priv->offload_fwd_mark); 757 skb_put(skb, pkt_len); 758 skb->protocol = eth_type_trans(skb, ndev); 759 am65_cpsw_nuss_rx_csum(skb, csum_info); 760 napi_gro_receive(&common->napi_rx, skb); 761 762 stats = this_cpu_ptr(ndev_priv->stats); 763 764 u64_stats_update_begin(&stats->syncp); 765 stats->rx_packets++; 766 stats->rx_bytes += pkt_len; 767 u64_stats_update_end(&stats->syncp); 768 kmemleak_not_leak(new_skb); 769 } else { 770 ndev->stats.rx_dropped++; 771 new_skb = skb; 772 } 773 774 if (netif_dormant(ndev)) { 775 dev_kfree_skb_any(new_skb); 776 ndev->stats.rx_dropped++; 777 return 0; 778 } 779 780 ret = am65_cpsw_nuss_rx_push(common, new_skb); 781 if (WARN_ON(ret < 0)) { 782 dev_kfree_skb_any(new_skb); 783 ndev->stats.rx_errors++; 784 ndev->stats.rx_dropped++; 785 } 786 787 return ret; 788 } 789 790 static int am65_cpsw_nuss_rx_poll(struct napi_struct *napi_rx, int budget) 791 { 792 struct am65_cpsw_common *common = am65_cpsw_napi_to_common(napi_rx); 793 int flow = AM65_CPSW_MAX_RX_FLOWS; 794 int cur_budget, ret; 795 int num_rx = 0; 796 797 /* process every flow */ 798 while (flow--) { 799 cur_budget = budget - num_rx; 800 801 while (cur_budget--) { 802 ret = am65_cpsw_nuss_rx_packets(common, flow); 803 if (ret) 804 break; 805 num_rx++; 806 } 807 808 if (num_rx >= budget) 809 break; 810 } 811 812 dev_dbg(common->dev, "%s num_rx:%d %d\n", __func__, num_rx, budget); 813 814 if (num_rx < budget && napi_complete_done(napi_rx, num_rx)) { 815 if (common->rx_irq_disabled) { 816 common->rx_irq_disabled = false; 817 enable_irq(common->rx_chns.irq); 818 } 819 } 820 821 return num_rx; 822 } 823 824 static void am65_cpsw_nuss_xmit_free(struct am65_cpsw_tx_chn *tx_chn, 825 struct cppi5_host_desc_t *desc) 826 { 827 struct cppi5_host_desc_t *first_desc, *next_desc; 828 dma_addr_t buf_dma, next_desc_dma; 829 u32 buf_dma_len; 830 831 first_desc = desc; 832 next_desc = first_desc; 833 834 cppi5_hdesc_get_obuf(first_desc, &buf_dma, &buf_dma_len); 835 k3_udma_glue_tx_cppi5_to_dma_addr(tx_chn->tx_chn, &buf_dma); 836 837 dma_unmap_single(tx_chn->dma_dev, buf_dma, buf_dma_len, DMA_TO_DEVICE); 838 839 next_desc_dma = cppi5_hdesc_get_next_hbdesc(first_desc); 840 k3_udma_glue_tx_cppi5_to_dma_addr(tx_chn->tx_chn, &next_desc_dma); 841 while (next_desc_dma) { 842 next_desc = k3_cppi_desc_pool_dma2virt(tx_chn->desc_pool, 843 next_desc_dma); 844 cppi5_hdesc_get_obuf(next_desc, &buf_dma, &buf_dma_len); 845 k3_udma_glue_tx_cppi5_to_dma_addr(tx_chn->tx_chn, &buf_dma); 846 847 dma_unmap_page(tx_chn->dma_dev, buf_dma, buf_dma_len, 848 DMA_TO_DEVICE); 849 850 next_desc_dma = cppi5_hdesc_get_next_hbdesc(next_desc); 851 k3_udma_glue_tx_cppi5_to_dma_addr(tx_chn->tx_chn, &next_desc_dma); 852 853 k3_cppi_desc_pool_free(tx_chn->desc_pool, next_desc); 854 } 855 856 k3_cppi_desc_pool_free(tx_chn->desc_pool, first_desc); 857 } 858 859 static void am65_cpsw_nuss_tx_cleanup(void *data, dma_addr_t desc_dma) 860 { 861 struct am65_cpsw_tx_chn *tx_chn = data; 862 struct cppi5_host_desc_t *desc_tx; 863 struct sk_buff *skb; 864 void **swdata; 865 866 desc_tx = k3_cppi_desc_pool_dma2virt(tx_chn->desc_pool, desc_dma); 867 swdata = cppi5_hdesc_get_swdata(desc_tx); 868 skb = *(swdata); 869 am65_cpsw_nuss_xmit_free(tx_chn, desc_tx); 870 871 dev_kfree_skb_any(skb); 872 } 873 874 static struct sk_buff * 875 am65_cpsw_nuss_tx_compl_packet(struct am65_cpsw_tx_chn *tx_chn, 876 dma_addr_t desc_dma) 877 { 878 struct am65_cpsw_ndev_priv *ndev_priv; 879 struct am65_cpsw_ndev_stats *stats; 880 struct cppi5_host_desc_t *desc_tx; 881 struct net_device *ndev; 882 struct sk_buff *skb; 883 void **swdata; 884 885 desc_tx = k3_cppi_desc_pool_dma2virt(tx_chn->desc_pool, 886 desc_dma); 887 swdata = cppi5_hdesc_get_swdata(desc_tx); 888 skb = *(swdata); 889 am65_cpsw_nuss_xmit_free(tx_chn, desc_tx); 890 891 ndev = skb->dev; 892 893 am65_cpts_tx_timestamp(tx_chn->common->cpts, skb); 894 895 ndev_priv = netdev_priv(ndev); 896 stats = this_cpu_ptr(ndev_priv->stats); 897 u64_stats_update_begin(&stats->syncp); 898 stats->tx_packets++; 899 stats->tx_bytes += skb->len; 900 u64_stats_update_end(&stats->syncp); 901 902 return skb; 903 } 904 905 static void am65_cpsw_nuss_tx_wake(struct am65_cpsw_tx_chn *tx_chn, struct net_device *ndev, 906 struct netdev_queue *netif_txq) 907 { 908 if (netif_tx_queue_stopped(netif_txq)) { 909 /* Check whether the queue is stopped due to stalled 910 * tx dma, if the queue is stopped then wake the queue 911 * as we have free desc for tx 912 */ 913 __netif_tx_lock(netif_txq, smp_processor_id()); 914 if (netif_running(ndev) && 915 (k3_cppi_desc_pool_avail(tx_chn->desc_pool) >= MAX_SKB_FRAGS)) 916 netif_tx_wake_queue(netif_txq); 917 918 __netif_tx_unlock(netif_txq); 919 } 920 } 921 922 static int am65_cpsw_nuss_tx_compl_packets(struct am65_cpsw_common *common, 923 int chn, unsigned int budget) 924 { 925 struct device *dev = common->dev; 926 struct am65_cpsw_tx_chn *tx_chn; 927 struct netdev_queue *netif_txq; 928 unsigned int total_bytes = 0; 929 struct net_device *ndev; 930 struct sk_buff *skb; 931 dma_addr_t desc_dma; 932 int res, num_tx = 0; 933 934 tx_chn = &common->tx_chns[chn]; 935 936 while (true) { 937 spin_lock(&tx_chn->lock); 938 res = k3_udma_glue_pop_tx_chn(tx_chn->tx_chn, &desc_dma); 939 spin_unlock(&tx_chn->lock); 940 if (res == -ENODATA) 941 break; 942 943 if (cppi5_desc_is_tdcm(desc_dma)) { 944 if (atomic_dec_and_test(&common->tdown_cnt)) 945 complete(&common->tdown_complete); 946 break; 947 } 948 949 skb = am65_cpsw_nuss_tx_compl_packet(tx_chn, desc_dma); 950 total_bytes = skb->len; 951 ndev = skb->dev; 952 napi_consume_skb(skb, budget); 953 num_tx++; 954 955 netif_txq = netdev_get_tx_queue(ndev, chn); 956 957 netdev_tx_completed_queue(netif_txq, num_tx, total_bytes); 958 959 am65_cpsw_nuss_tx_wake(tx_chn, ndev, netif_txq); 960 } 961 962 dev_dbg(dev, "%s:%u pkt:%d\n", __func__, chn, num_tx); 963 964 return num_tx; 965 } 966 967 static int am65_cpsw_nuss_tx_compl_packets_2g(struct am65_cpsw_common *common, 968 int chn, unsigned int budget) 969 { 970 struct device *dev = common->dev; 971 struct am65_cpsw_tx_chn *tx_chn; 972 struct netdev_queue *netif_txq; 973 unsigned int total_bytes = 0; 974 struct net_device *ndev; 975 struct sk_buff *skb; 976 dma_addr_t desc_dma; 977 int res, num_tx = 0; 978 979 tx_chn = &common->tx_chns[chn]; 980 981 while (true) { 982 res = k3_udma_glue_pop_tx_chn(tx_chn->tx_chn, &desc_dma); 983 if (res == -ENODATA) 984 break; 985 986 if (cppi5_desc_is_tdcm(desc_dma)) { 987 if (atomic_dec_and_test(&common->tdown_cnt)) 988 complete(&common->tdown_complete); 989 break; 990 } 991 992 skb = am65_cpsw_nuss_tx_compl_packet(tx_chn, desc_dma); 993 994 ndev = skb->dev; 995 total_bytes += skb->len; 996 napi_consume_skb(skb, budget); 997 num_tx++; 998 } 999 1000 if (!num_tx) 1001 return 0; 1002 1003 netif_txq = netdev_get_tx_queue(ndev, chn); 1004 1005 netdev_tx_completed_queue(netif_txq, num_tx, total_bytes); 1006 1007 am65_cpsw_nuss_tx_wake(tx_chn, ndev, netif_txq); 1008 1009 dev_dbg(dev, "%s:%u pkt:%d\n", __func__, chn, num_tx); 1010 1011 return num_tx; 1012 } 1013 1014 static int am65_cpsw_nuss_tx_poll(struct napi_struct *napi_tx, int budget) 1015 { 1016 struct am65_cpsw_tx_chn *tx_chn = am65_cpsw_napi_to_tx_chn(napi_tx); 1017 int num_tx; 1018 1019 if (AM65_CPSW_IS_CPSW2G(tx_chn->common)) 1020 num_tx = am65_cpsw_nuss_tx_compl_packets_2g(tx_chn->common, tx_chn->id, budget); 1021 else 1022 num_tx = am65_cpsw_nuss_tx_compl_packets(tx_chn->common, tx_chn->id, budget); 1023 1024 if (num_tx >= budget) 1025 return budget; 1026 1027 if (napi_complete_done(napi_tx, num_tx)) 1028 enable_irq(tx_chn->irq); 1029 1030 return 0; 1031 } 1032 1033 static irqreturn_t am65_cpsw_nuss_rx_irq(int irq, void *dev_id) 1034 { 1035 struct am65_cpsw_common *common = dev_id; 1036 1037 common->rx_irq_disabled = true; 1038 disable_irq_nosync(irq); 1039 napi_schedule(&common->napi_rx); 1040 1041 return IRQ_HANDLED; 1042 } 1043 1044 static irqreturn_t am65_cpsw_nuss_tx_irq(int irq, void *dev_id) 1045 { 1046 struct am65_cpsw_tx_chn *tx_chn = dev_id; 1047 1048 disable_irq_nosync(irq); 1049 napi_schedule(&tx_chn->napi_tx); 1050 1051 return IRQ_HANDLED; 1052 } 1053 1054 static netdev_tx_t am65_cpsw_nuss_ndo_slave_xmit(struct sk_buff *skb, 1055 struct net_device *ndev) 1056 { 1057 struct am65_cpsw_common *common = am65_ndev_to_common(ndev); 1058 struct cppi5_host_desc_t *first_desc, *next_desc, *cur_desc; 1059 struct am65_cpsw_port *port = am65_ndev_to_port(ndev); 1060 struct device *dev = common->dev; 1061 struct am65_cpsw_tx_chn *tx_chn; 1062 struct netdev_queue *netif_txq; 1063 dma_addr_t desc_dma, buf_dma; 1064 int ret, q_idx, i; 1065 void **swdata; 1066 u32 *psdata; 1067 u32 pkt_len; 1068 1069 /* padding enabled in hw */ 1070 pkt_len = skb_headlen(skb); 1071 1072 /* SKB TX timestamp */ 1073 if (port->tx_ts_enabled) 1074 am65_cpts_prep_tx_timestamp(common->cpts, skb); 1075 1076 q_idx = skb_get_queue_mapping(skb); 1077 dev_dbg(dev, "%s skb_queue:%d\n", __func__, q_idx); 1078 1079 tx_chn = &common->tx_chns[q_idx]; 1080 netif_txq = netdev_get_tx_queue(ndev, q_idx); 1081 1082 /* Map the linear buffer */ 1083 buf_dma = dma_map_single(tx_chn->dma_dev, skb->data, pkt_len, 1084 DMA_TO_DEVICE); 1085 if (unlikely(dma_mapping_error(tx_chn->dma_dev, buf_dma))) { 1086 dev_err(dev, "Failed to map tx skb buffer\n"); 1087 ndev->stats.tx_errors++; 1088 goto err_free_skb; 1089 } 1090 1091 first_desc = k3_cppi_desc_pool_alloc(tx_chn->desc_pool); 1092 if (!first_desc) { 1093 dev_dbg(dev, "Failed to allocate descriptor\n"); 1094 dma_unmap_single(tx_chn->dma_dev, buf_dma, pkt_len, 1095 DMA_TO_DEVICE); 1096 goto busy_stop_q; 1097 } 1098 1099 cppi5_hdesc_init(first_desc, CPPI5_INFO0_HDESC_EPIB_PRESENT, 1100 AM65_CPSW_NAV_PS_DATA_SIZE); 1101 cppi5_desc_set_pktids(&first_desc->hdr, 0, 0x3FFF); 1102 cppi5_hdesc_set_pkttype(first_desc, 0x7); 1103 cppi5_desc_set_tags_ids(&first_desc->hdr, 0, port->port_id); 1104 1105 k3_udma_glue_tx_dma_to_cppi5_addr(tx_chn->tx_chn, &buf_dma); 1106 cppi5_hdesc_attach_buf(first_desc, buf_dma, pkt_len, buf_dma, pkt_len); 1107 swdata = cppi5_hdesc_get_swdata(first_desc); 1108 *(swdata) = skb; 1109 psdata = cppi5_hdesc_get_psdata(first_desc); 1110 1111 /* HW csum offload if enabled */ 1112 psdata[2] = 0; 1113 if (likely(skb->ip_summed == CHECKSUM_PARTIAL)) { 1114 unsigned int cs_start, cs_offset; 1115 1116 cs_start = skb_transport_offset(skb); 1117 cs_offset = cs_start + skb->csum_offset; 1118 /* HW numerates bytes starting from 1 */ 1119 psdata[2] = ((cs_offset + 1) << 24) | 1120 ((cs_start + 1) << 16) | (skb->len - cs_start); 1121 dev_dbg(dev, "%s tx psdata:%#x\n", __func__, psdata[2]); 1122 } 1123 1124 if (!skb_is_nonlinear(skb)) 1125 goto done_tx; 1126 1127 dev_dbg(dev, "fragmented SKB\n"); 1128 1129 /* Handle the case where skb is fragmented in pages */ 1130 cur_desc = first_desc; 1131 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { 1132 skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 1133 u32 frag_size = skb_frag_size(frag); 1134 1135 next_desc = k3_cppi_desc_pool_alloc(tx_chn->desc_pool); 1136 if (!next_desc) { 1137 dev_err(dev, "Failed to allocate descriptor\n"); 1138 goto busy_free_descs; 1139 } 1140 1141 buf_dma = skb_frag_dma_map(tx_chn->dma_dev, frag, 0, frag_size, 1142 DMA_TO_DEVICE); 1143 if (unlikely(dma_mapping_error(tx_chn->dma_dev, buf_dma))) { 1144 dev_err(dev, "Failed to map tx skb page\n"); 1145 k3_cppi_desc_pool_free(tx_chn->desc_pool, next_desc); 1146 ndev->stats.tx_errors++; 1147 goto err_free_descs; 1148 } 1149 1150 cppi5_hdesc_reset_hbdesc(next_desc); 1151 k3_udma_glue_tx_dma_to_cppi5_addr(tx_chn->tx_chn, &buf_dma); 1152 cppi5_hdesc_attach_buf(next_desc, 1153 buf_dma, frag_size, buf_dma, frag_size); 1154 1155 desc_dma = k3_cppi_desc_pool_virt2dma(tx_chn->desc_pool, 1156 next_desc); 1157 k3_udma_glue_tx_dma_to_cppi5_addr(tx_chn->tx_chn, &desc_dma); 1158 cppi5_hdesc_link_hbdesc(cur_desc, desc_dma); 1159 1160 pkt_len += frag_size; 1161 cur_desc = next_desc; 1162 } 1163 WARN_ON(pkt_len != skb->len); 1164 1165 done_tx: 1166 skb_tx_timestamp(skb); 1167 1168 /* report bql before sending packet */ 1169 netdev_tx_sent_queue(netif_txq, pkt_len); 1170 1171 cppi5_hdesc_set_pktlen(first_desc, pkt_len); 1172 desc_dma = k3_cppi_desc_pool_virt2dma(tx_chn->desc_pool, first_desc); 1173 if (AM65_CPSW_IS_CPSW2G(common)) { 1174 ret = k3_udma_glue_push_tx_chn(tx_chn->tx_chn, first_desc, desc_dma); 1175 } else { 1176 spin_lock_bh(&tx_chn->lock); 1177 ret = k3_udma_glue_push_tx_chn(tx_chn->tx_chn, first_desc, desc_dma); 1178 spin_unlock_bh(&tx_chn->lock); 1179 } 1180 if (ret) { 1181 dev_err(dev, "can't push desc %d\n", ret); 1182 /* inform bql */ 1183 netdev_tx_completed_queue(netif_txq, 1, pkt_len); 1184 ndev->stats.tx_errors++; 1185 goto err_free_descs; 1186 } 1187 1188 if (k3_cppi_desc_pool_avail(tx_chn->desc_pool) < MAX_SKB_FRAGS) { 1189 netif_tx_stop_queue(netif_txq); 1190 /* Barrier, so that stop_queue visible to other cpus */ 1191 smp_mb__after_atomic(); 1192 dev_dbg(dev, "netif_tx_stop_queue %d\n", q_idx); 1193 1194 /* re-check for smp */ 1195 if (k3_cppi_desc_pool_avail(tx_chn->desc_pool) >= 1196 MAX_SKB_FRAGS) { 1197 netif_tx_wake_queue(netif_txq); 1198 dev_dbg(dev, "netif_tx_wake_queue %d\n", q_idx); 1199 } 1200 } 1201 1202 return NETDEV_TX_OK; 1203 1204 err_free_descs: 1205 am65_cpsw_nuss_xmit_free(tx_chn, first_desc); 1206 err_free_skb: 1207 ndev->stats.tx_dropped++; 1208 dev_kfree_skb_any(skb); 1209 return NETDEV_TX_OK; 1210 1211 busy_free_descs: 1212 am65_cpsw_nuss_xmit_free(tx_chn, first_desc); 1213 busy_stop_q: 1214 netif_tx_stop_queue(netif_txq); 1215 return NETDEV_TX_BUSY; 1216 } 1217 1218 static int am65_cpsw_nuss_ndo_slave_set_mac_address(struct net_device *ndev, 1219 void *addr) 1220 { 1221 struct am65_cpsw_common *common = am65_ndev_to_common(ndev); 1222 struct am65_cpsw_port *port = am65_ndev_to_port(ndev); 1223 struct sockaddr *sockaddr = (struct sockaddr *)addr; 1224 int ret; 1225 1226 ret = eth_prepare_mac_addr_change(ndev, addr); 1227 if (ret < 0) 1228 return ret; 1229 1230 ret = pm_runtime_resume_and_get(common->dev); 1231 if (ret < 0) 1232 return ret; 1233 1234 cpsw_ale_del_ucast(common->ale, ndev->dev_addr, 1235 HOST_PORT_NUM, 0, 0); 1236 cpsw_ale_add_ucast(common->ale, sockaddr->sa_data, 1237 HOST_PORT_NUM, ALE_SECURE, 0); 1238 1239 am65_cpsw_port_set_sl_mac(port, addr); 1240 eth_commit_mac_addr_change(ndev, sockaddr); 1241 1242 pm_runtime_put(common->dev); 1243 1244 return 0; 1245 } 1246 1247 static int am65_cpsw_nuss_hwtstamp_set(struct net_device *ndev, 1248 struct ifreq *ifr) 1249 { 1250 struct am65_cpsw_common *common = am65_ndev_to_common(ndev); 1251 struct am65_cpsw_port *port = am65_ndev_to_port(ndev); 1252 u32 ts_ctrl, seq_id, ts_ctrl_ltype2, ts_vlan_ltype; 1253 struct hwtstamp_config cfg; 1254 1255 if (!IS_ENABLED(CONFIG_TI_K3_AM65_CPTS)) 1256 return -EOPNOTSUPP; 1257 1258 if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg))) 1259 return -EFAULT; 1260 1261 /* TX HW timestamp */ 1262 switch (cfg.tx_type) { 1263 case HWTSTAMP_TX_OFF: 1264 case HWTSTAMP_TX_ON: 1265 break; 1266 default: 1267 return -ERANGE; 1268 } 1269 1270 switch (cfg.rx_filter) { 1271 case HWTSTAMP_FILTER_NONE: 1272 port->rx_ts_enabled = false; 1273 break; 1274 case HWTSTAMP_FILTER_ALL: 1275 case HWTSTAMP_FILTER_SOME: 1276 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: 1277 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: 1278 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: 1279 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: 1280 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 1281 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 1282 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: 1283 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: 1284 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: 1285 case HWTSTAMP_FILTER_PTP_V2_EVENT: 1286 case HWTSTAMP_FILTER_PTP_V2_SYNC: 1287 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 1288 case HWTSTAMP_FILTER_NTP_ALL: 1289 port->rx_ts_enabled = true; 1290 cfg.rx_filter = HWTSTAMP_FILTER_ALL; 1291 break; 1292 default: 1293 return -ERANGE; 1294 } 1295 1296 port->tx_ts_enabled = (cfg.tx_type == HWTSTAMP_TX_ON); 1297 1298 /* cfg TX timestamp */ 1299 seq_id = (AM65_CPSW_TS_SEQ_ID_OFFSET << 1300 AM65_CPSW_PN_TS_SEQ_ID_OFFSET_SHIFT) | ETH_P_1588; 1301 1302 ts_vlan_ltype = ETH_P_8021Q; 1303 1304 ts_ctrl_ltype2 = ETH_P_1588 | 1305 AM65_CPSW_PN_TS_CTL_LTYPE2_TS_107 | 1306 AM65_CPSW_PN_TS_CTL_LTYPE2_TS_129 | 1307 AM65_CPSW_PN_TS_CTL_LTYPE2_TS_130 | 1308 AM65_CPSW_PN_TS_CTL_LTYPE2_TS_131 | 1309 AM65_CPSW_PN_TS_CTL_LTYPE2_TS_132 | 1310 AM65_CPSW_PN_TS_CTL_LTYPE2_TS_319 | 1311 AM65_CPSW_PN_TS_CTL_LTYPE2_TS_320 | 1312 AM65_CPSW_PN_TS_CTL_LTYPE2_TS_TTL_NONZERO; 1313 1314 ts_ctrl = AM65_CPSW_TS_EVENT_MSG_TYPE_BITS << 1315 AM65_CPSW_PN_TS_CTL_MSG_TYPE_EN_SHIFT; 1316 1317 if (port->tx_ts_enabled) 1318 ts_ctrl |= AM65_CPSW_TS_TX_ANX_ALL_EN | 1319 AM65_CPSW_PN_TS_CTL_TX_VLAN_LT1_EN; 1320 1321 writel(seq_id, port->port_base + AM65_CPSW_PORTN_REG_TS_SEQ_LTYPE_REG); 1322 writel(ts_vlan_ltype, port->port_base + 1323 AM65_CPSW_PORTN_REG_TS_VLAN_LTYPE_REG); 1324 writel(ts_ctrl_ltype2, port->port_base + 1325 AM65_CPSW_PORTN_REG_TS_CTL_LTYPE2); 1326 writel(ts_ctrl, port->port_base + AM65_CPSW_PORTN_REG_TS_CTL); 1327 1328 /* en/dis RX timestamp */ 1329 am65_cpts_rx_enable(common->cpts, port->rx_ts_enabled); 1330 1331 return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0; 1332 } 1333 1334 static int am65_cpsw_nuss_hwtstamp_get(struct net_device *ndev, 1335 struct ifreq *ifr) 1336 { 1337 struct am65_cpsw_port *port = am65_ndev_to_port(ndev); 1338 struct hwtstamp_config cfg; 1339 1340 if (!IS_ENABLED(CONFIG_TI_K3_AM65_CPTS)) 1341 return -EOPNOTSUPP; 1342 1343 cfg.flags = 0; 1344 cfg.tx_type = port->tx_ts_enabled ? 1345 HWTSTAMP_TX_ON : HWTSTAMP_TX_OFF; 1346 cfg.rx_filter = port->rx_ts_enabled ? 1347 HWTSTAMP_FILTER_ALL : HWTSTAMP_FILTER_NONE; 1348 1349 return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0; 1350 } 1351 1352 static int am65_cpsw_nuss_ndo_slave_ioctl(struct net_device *ndev, 1353 struct ifreq *req, int cmd) 1354 { 1355 struct am65_cpsw_port *port = am65_ndev_to_port(ndev); 1356 1357 if (!netif_running(ndev)) 1358 return -EINVAL; 1359 1360 switch (cmd) { 1361 case SIOCSHWTSTAMP: 1362 return am65_cpsw_nuss_hwtstamp_set(ndev, req); 1363 case SIOCGHWTSTAMP: 1364 return am65_cpsw_nuss_hwtstamp_get(ndev, req); 1365 } 1366 1367 return phylink_mii_ioctl(port->slave.phylink, req, cmd); 1368 } 1369 1370 static void am65_cpsw_nuss_ndo_get_stats(struct net_device *dev, 1371 struct rtnl_link_stats64 *stats) 1372 { 1373 struct am65_cpsw_ndev_priv *ndev_priv = netdev_priv(dev); 1374 unsigned int start; 1375 int cpu; 1376 1377 for_each_possible_cpu(cpu) { 1378 struct am65_cpsw_ndev_stats *cpu_stats; 1379 u64 rx_packets; 1380 u64 rx_bytes; 1381 u64 tx_packets; 1382 u64 tx_bytes; 1383 1384 cpu_stats = per_cpu_ptr(ndev_priv->stats, cpu); 1385 do { 1386 start = u64_stats_fetch_begin(&cpu_stats->syncp); 1387 rx_packets = cpu_stats->rx_packets; 1388 rx_bytes = cpu_stats->rx_bytes; 1389 tx_packets = cpu_stats->tx_packets; 1390 tx_bytes = cpu_stats->tx_bytes; 1391 } while (u64_stats_fetch_retry(&cpu_stats->syncp, start)); 1392 1393 stats->rx_packets += rx_packets; 1394 stats->rx_bytes += rx_bytes; 1395 stats->tx_packets += tx_packets; 1396 stats->tx_bytes += tx_bytes; 1397 } 1398 1399 stats->rx_errors = dev->stats.rx_errors; 1400 stats->rx_dropped = dev->stats.rx_dropped; 1401 stats->tx_dropped = dev->stats.tx_dropped; 1402 } 1403 1404 static const struct net_device_ops am65_cpsw_nuss_netdev_ops = { 1405 .ndo_open = am65_cpsw_nuss_ndo_slave_open, 1406 .ndo_stop = am65_cpsw_nuss_ndo_slave_stop, 1407 .ndo_start_xmit = am65_cpsw_nuss_ndo_slave_xmit, 1408 .ndo_set_rx_mode = am65_cpsw_nuss_ndo_slave_set_rx_mode, 1409 .ndo_get_stats64 = am65_cpsw_nuss_ndo_get_stats, 1410 .ndo_validate_addr = eth_validate_addr, 1411 .ndo_set_mac_address = am65_cpsw_nuss_ndo_slave_set_mac_address, 1412 .ndo_tx_timeout = am65_cpsw_nuss_ndo_host_tx_timeout, 1413 .ndo_vlan_rx_add_vid = am65_cpsw_nuss_ndo_slave_add_vid, 1414 .ndo_vlan_rx_kill_vid = am65_cpsw_nuss_ndo_slave_kill_vid, 1415 .ndo_eth_ioctl = am65_cpsw_nuss_ndo_slave_ioctl, 1416 .ndo_setup_tc = am65_cpsw_qos_ndo_setup_tc, 1417 }; 1418 1419 static void am65_cpsw_nuss_mac_config(struct phylink_config *config, unsigned int mode, 1420 const struct phylink_link_state *state) 1421 { 1422 struct am65_cpsw_slave_data *slave = container_of(config, struct am65_cpsw_slave_data, 1423 phylink_config); 1424 struct am65_cpsw_port *port = container_of(slave, struct am65_cpsw_port, slave); 1425 struct am65_cpsw_common *common = port->common; 1426 1427 if (common->pdata.extra_modes & BIT(state->interface)) 1428 writel(AM65_CPSW_SGMII_CONTROL_MR_AN_ENABLE, 1429 port->sgmii_base + AM65_CPSW_SGMII_CONTROL_REG); 1430 } 1431 1432 static void am65_cpsw_nuss_mac_link_down(struct phylink_config *config, unsigned int mode, 1433 phy_interface_t interface) 1434 { 1435 struct am65_cpsw_slave_data *slave = container_of(config, struct am65_cpsw_slave_data, 1436 phylink_config); 1437 struct am65_cpsw_port *port = container_of(slave, struct am65_cpsw_port, slave); 1438 struct am65_cpsw_common *common = port->common; 1439 struct net_device *ndev = port->ndev; 1440 int tmo; 1441 1442 /* disable forwarding */ 1443 cpsw_ale_control_set(common->ale, port->port_id, ALE_PORT_STATE, ALE_PORT_STATE_DISABLE); 1444 1445 cpsw_sl_ctl_set(port->slave.mac_sl, CPSW_SL_CTL_CMD_IDLE); 1446 1447 tmo = cpsw_sl_wait_for_idle(port->slave.mac_sl, 100); 1448 dev_dbg(common->dev, "down msc_sl %08x tmo %d\n", 1449 cpsw_sl_reg_read(port->slave.mac_sl, CPSW_SL_MACSTATUS), tmo); 1450 1451 cpsw_sl_ctl_reset(port->slave.mac_sl); 1452 1453 am65_cpsw_qos_link_down(ndev); 1454 netif_tx_stop_all_queues(ndev); 1455 } 1456 1457 static void am65_cpsw_nuss_mac_link_up(struct phylink_config *config, struct phy_device *phy, 1458 unsigned int mode, phy_interface_t interface, int speed, 1459 int duplex, bool tx_pause, bool rx_pause) 1460 { 1461 struct am65_cpsw_slave_data *slave = container_of(config, struct am65_cpsw_slave_data, 1462 phylink_config); 1463 struct am65_cpsw_port *port = container_of(slave, struct am65_cpsw_port, slave); 1464 struct am65_cpsw_common *common = port->common; 1465 u32 mac_control = CPSW_SL_CTL_GMII_EN; 1466 struct net_device *ndev = port->ndev; 1467 1468 if (speed == SPEED_1000) 1469 mac_control |= CPSW_SL_CTL_GIG; 1470 if (speed == SPEED_10 && phy_interface_mode_is_rgmii(interface)) 1471 /* Can be used with in band mode only */ 1472 mac_control |= CPSW_SL_CTL_EXT_EN; 1473 if (speed == SPEED_100 && interface == PHY_INTERFACE_MODE_RMII) 1474 mac_control |= CPSW_SL_CTL_IFCTL_A; 1475 if (duplex) 1476 mac_control |= CPSW_SL_CTL_FULLDUPLEX; 1477 1478 /* rx_pause/tx_pause */ 1479 if (rx_pause) 1480 mac_control |= CPSW_SL_CTL_RX_FLOW_EN; 1481 1482 if (tx_pause) 1483 mac_control |= CPSW_SL_CTL_TX_FLOW_EN; 1484 1485 cpsw_sl_ctl_set(port->slave.mac_sl, mac_control); 1486 1487 /* enable forwarding */ 1488 cpsw_ale_control_set(common->ale, port->port_id, ALE_PORT_STATE, ALE_PORT_STATE_FORWARD); 1489 1490 am65_cpsw_qos_link_up(ndev, speed); 1491 netif_tx_wake_all_queues(ndev); 1492 } 1493 1494 static const struct phylink_mac_ops am65_cpsw_phylink_mac_ops = { 1495 .mac_config = am65_cpsw_nuss_mac_config, 1496 .mac_link_down = am65_cpsw_nuss_mac_link_down, 1497 .mac_link_up = am65_cpsw_nuss_mac_link_up, 1498 }; 1499 1500 static void am65_cpsw_nuss_slave_disable_unused(struct am65_cpsw_port *port) 1501 { 1502 struct am65_cpsw_common *common = port->common; 1503 1504 if (!port->disabled) 1505 return; 1506 1507 cpsw_ale_control_set(common->ale, port->port_id, 1508 ALE_PORT_STATE, ALE_PORT_STATE_DISABLE); 1509 1510 cpsw_sl_reset(port->slave.mac_sl, 100); 1511 cpsw_sl_ctl_reset(port->slave.mac_sl); 1512 } 1513 1514 static void am65_cpsw_nuss_free_tx_chns(void *data) 1515 { 1516 struct am65_cpsw_common *common = data; 1517 int i; 1518 1519 for (i = 0; i < common->tx_ch_num; i++) { 1520 struct am65_cpsw_tx_chn *tx_chn = &common->tx_chns[i]; 1521 1522 if (!IS_ERR_OR_NULL(tx_chn->desc_pool)) 1523 k3_cppi_desc_pool_destroy(tx_chn->desc_pool); 1524 1525 if (!IS_ERR_OR_NULL(tx_chn->tx_chn)) 1526 k3_udma_glue_release_tx_chn(tx_chn->tx_chn); 1527 1528 memset(tx_chn, 0, sizeof(*tx_chn)); 1529 } 1530 } 1531 1532 void am65_cpsw_nuss_remove_tx_chns(struct am65_cpsw_common *common) 1533 { 1534 struct device *dev = common->dev; 1535 int i; 1536 1537 devm_remove_action(dev, am65_cpsw_nuss_free_tx_chns, common); 1538 1539 for (i = 0; i < common->tx_ch_num; i++) { 1540 struct am65_cpsw_tx_chn *tx_chn = &common->tx_chns[i]; 1541 1542 if (tx_chn->irq) 1543 devm_free_irq(dev, tx_chn->irq, tx_chn); 1544 1545 netif_napi_del(&tx_chn->napi_tx); 1546 1547 if (!IS_ERR_OR_NULL(tx_chn->desc_pool)) 1548 k3_cppi_desc_pool_destroy(tx_chn->desc_pool); 1549 1550 if (!IS_ERR_OR_NULL(tx_chn->tx_chn)) 1551 k3_udma_glue_release_tx_chn(tx_chn->tx_chn); 1552 1553 memset(tx_chn, 0, sizeof(*tx_chn)); 1554 } 1555 } 1556 1557 static int am65_cpsw_nuss_ndev_add_tx_napi(struct am65_cpsw_common *common) 1558 { 1559 struct device *dev = common->dev; 1560 int i, ret = 0; 1561 1562 for (i = 0; i < common->tx_ch_num; i++) { 1563 struct am65_cpsw_tx_chn *tx_chn = &common->tx_chns[i]; 1564 1565 netif_napi_add_tx(common->dma_ndev, &tx_chn->napi_tx, 1566 am65_cpsw_nuss_tx_poll); 1567 1568 ret = devm_request_irq(dev, tx_chn->irq, 1569 am65_cpsw_nuss_tx_irq, 1570 IRQF_TRIGGER_HIGH, 1571 tx_chn->tx_chn_name, tx_chn); 1572 if (ret) { 1573 dev_err(dev, "failure requesting tx%u irq %u, %d\n", 1574 tx_chn->id, tx_chn->irq, ret); 1575 goto err; 1576 } 1577 } 1578 1579 err: 1580 return ret; 1581 } 1582 1583 static int am65_cpsw_nuss_init_tx_chns(struct am65_cpsw_common *common) 1584 { 1585 u32 max_desc_num = ALIGN(AM65_CPSW_MAX_TX_DESC, MAX_SKB_FRAGS); 1586 struct k3_udma_glue_tx_channel_cfg tx_cfg = { 0 }; 1587 struct device *dev = common->dev; 1588 struct k3_ring_cfg ring_cfg = { 1589 .elm_size = K3_RINGACC_RING_ELSIZE_8, 1590 .mode = K3_RINGACC_RING_MODE_RING, 1591 .flags = 0 1592 }; 1593 u32 hdesc_size; 1594 int i, ret = 0; 1595 1596 hdesc_size = cppi5_hdesc_calc_size(true, AM65_CPSW_NAV_PS_DATA_SIZE, 1597 AM65_CPSW_NAV_SW_DATA_SIZE); 1598 1599 tx_cfg.swdata_size = AM65_CPSW_NAV_SW_DATA_SIZE; 1600 tx_cfg.tx_cfg = ring_cfg; 1601 tx_cfg.txcq_cfg = ring_cfg; 1602 tx_cfg.tx_cfg.size = max_desc_num; 1603 tx_cfg.txcq_cfg.size = max_desc_num; 1604 1605 for (i = 0; i < common->tx_ch_num; i++) { 1606 struct am65_cpsw_tx_chn *tx_chn = &common->tx_chns[i]; 1607 1608 snprintf(tx_chn->tx_chn_name, 1609 sizeof(tx_chn->tx_chn_name), "tx%d", i); 1610 1611 spin_lock_init(&tx_chn->lock); 1612 tx_chn->common = common; 1613 tx_chn->id = i; 1614 tx_chn->descs_num = max_desc_num; 1615 1616 tx_chn->tx_chn = 1617 k3_udma_glue_request_tx_chn(dev, 1618 tx_chn->tx_chn_name, 1619 &tx_cfg); 1620 if (IS_ERR(tx_chn->tx_chn)) { 1621 ret = dev_err_probe(dev, PTR_ERR(tx_chn->tx_chn), 1622 "Failed to request tx dma channel\n"); 1623 goto err; 1624 } 1625 tx_chn->dma_dev = k3_udma_glue_tx_get_dma_device(tx_chn->tx_chn); 1626 1627 tx_chn->desc_pool = k3_cppi_desc_pool_create_name(tx_chn->dma_dev, 1628 tx_chn->descs_num, 1629 hdesc_size, 1630 tx_chn->tx_chn_name); 1631 if (IS_ERR(tx_chn->desc_pool)) { 1632 ret = PTR_ERR(tx_chn->desc_pool); 1633 dev_err(dev, "Failed to create poll %d\n", ret); 1634 goto err; 1635 } 1636 1637 tx_chn->irq = k3_udma_glue_tx_get_irq(tx_chn->tx_chn); 1638 if (tx_chn->irq <= 0) { 1639 dev_err(dev, "Failed to get tx dma irq %d\n", 1640 tx_chn->irq); 1641 goto err; 1642 } 1643 1644 snprintf(tx_chn->tx_chn_name, 1645 sizeof(tx_chn->tx_chn_name), "%s-tx%d", 1646 dev_name(dev), tx_chn->id); 1647 } 1648 1649 ret = am65_cpsw_nuss_ndev_add_tx_napi(common); 1650 if (ret) { 1651 dev_err(dev, "Failed to add tx NAPI %d\n", ret); 1652 goto err; 1653 } 1654 1655 err: 1656 i = devm_add_action(dev, am65_cpsw_nuss_free_tx_chns, common); 1657 if (i) { 1658 dev_err(dev, "Failed to add free_tx_chns action %d\n", i); 1659 return i; 1660 } 1661 1662 return ret; 1663 } 1664 1665 static void am65_cpsw_nuss_free_rx_chns(void *data) 1666 { 1667 struct am65_cpsw_common *common = data; 1668 struct am65_cpsw_rx_chn *rx_chn; 1669 1670 rx_chn = &common->rx_chns; 1671 1672 if (!IS_ERR_OR_NULL(rx_chn->desc_pool)) 1673 k3_cppi_desc_pool_destroy(rx_chn->desc_pool); 1674 1675 if (!IS_ERR_OR_NULL(rx_chn->rx_chn)) 1676 k3_udma_glue_release_rx_chn(rx_chn->rx_chn); 1677 } 1678 1679 static void am65_cpsw_nuss_remove_rx_chns(void *data) 1680 { 1681 struct am65_cpsw_common *common = data; 1682 struct am65_cpsw_rx_chn *rx_chn; 1683 struct device *dev = common->dev; 1684 1685 rx_chn = &common->rx_chns; 1686 devm_remove_action(dev, am65_cpsw_nuss_free_rx_chns, common); 1687 1688 if (!(rx_chn->irq < 0)) 1689 devm_free_irq(dev, rx_chn->irq, common); 1690 1691 netif_napi_del(&common->napi_rx); 1692 1693 if (!IS_ERR_OR_NULL(rx_chn->desc_pool)) 1694 k3_cppi_desc_pool_destroy(rx_chn->desc_pool); 1695 1696 if (!IS_ERR_OR_NULL(rx_chn->rx_chn)) 1697 k3_udma_glue_release_rx_chn(rx_chn->rx_chn); 1698 1699 common->rx_flow_id_base = -1; 1700 } 1701 1702 static int am65_cpsw_nuss_init_rx_chns(struct am65_cpsw_common *common) 1703 { 1704 struct am65_cpsw_rx_chn *rx_chn = &common->rx_chns; 1705 struct k3_udma_glue_rx_channel_cfg rx_cfg = { 0 }; 1706 u32 max_desc_num = AM65_CPSW_MAX_RX_DESC; 1707 struct device *dev = common->dev; 1708 u32 hdesc_size; 1709 u32 fdqring_id; 1710 int i, ret = 0; 1711 1712 hdesc_size = cppi5_hdesc_calc_size(true, AM65_CPSW_NAV_PS_DATA_SIZE, 1713 AM65_CPSW_NAV_SW_DATA_SIZE); 1714 1715 rx_cfg.swdata_size = AM65_CPSW_NAV_SW_DATA_SIZE; 1716 rx_cfg.flow_id_num = AM65_CPSW_MAX_RX_FLOWS; 1717 rx_cfg.flow_id_base = common->rx_flow_id_base; 1718 1719 /* init all flows */ 1720 rx_chn->dev = dev; 1721 rx_chn->descs_num = max_desc_num; 1722 1723 rx_chn->rx_chn = k3_udma_glue_request_rx_chn(dev, "rx", &rx_cfg); 1724 if (IS_ERR(rx_chn->rx_chn)) { 1725 ret = dev_err_probe(dev, PTR_ERR(rx_chn->rx_chn), 1726 "Failed to request rx dma channel\n"); 1727 goto err; 1728 } 1729 rx_chn->dma_dev = k3_udma_glue_rx_get_dma_device(rx_chn->rx_chn); 1730 1731 rx_chn->desc_pool = k3_cppi_desc_pool_create_name(rx_chn->dma_dev, 1732 rx_chn->descs_num, 1733 hdesc_size, "rx"); 1734 if (IS_ERR(rx_chn->desc_pool)) { 1735 ret = PTR_ERR(rx_chn->desc_pool); 1736 dev_err(dev, "Failed to create rx poll %d\n", ret); 1737 goto err; 1738 } 1739 1740 common->rx_flow_id_base = 1741 k3_udma_glue_rx_get_flow_id_base(rx_chn->rx_chn); 1742 dev_info(dev, "set new flow-id-base %u\n", common->rx_flow_id_base); 1743 1744 fdqring_id = K3_RINGACC_RING_ID_ANY; 1745 for (i = 0; i < rx_cfg.flow_id_num; i++) { 1746 struct k3_ring_cfg rxring_cfg = { 1747 .elm_size = K3_RINGACC_RING_ELSIZE_8, 1748 .mode = K3_RINGACC_RING_MODE_RING, 1749 .flags = 0, 1750 }; 1751 struct k3_ring_cfg fdqring_cfg = { 1752 .elm_size = K3_RINGACC_RING_ELSIZE_8, 1753 .flags = K3_RINGACC_RING_SHARED, 1754 }; 1755 struct k3_udma_glue_rx_flow_cfg rx_flow_cfg = { 1756 .rx_cfg = rxring_cfg, 1757 .rxfdq_cfg = fdqring_cfg, 1758 .ring_rxq_id = K3_RINGACC_RING_ID_ANY, 1759 .src_tag_lo_sel = 1760 K3_UDMA_GLUE_SRC_TAG_LO_USE_REMOTE_SRC_TAG, 1761 }; 1762 1763 rx_flow_cfg.ring_rxfdq0_id = fdqring_id; 1764 rx_flow_cfg.rx_cfg.size = max_desc_num; 1765 rx_flow_cfg.rxfdq_cfg.size = max_desc_num; 1766 rx_flow_cfg.rxfdq_cfg.mode = common->pdata.fdqring_mode; 1767 1768 ret = k3_udma_glue_rx_flow_init(rx_chn->rx_chn, 1769 i, &rx_flow_cfg); 1770 if (ret) { 1771 dev_err(dev, "Failed to init rx flow%d %d\n", i, ret); 1772 goto err; 1773 } 1774 if (!i) 1775 fdqring_id = 1776 k3_udma_glue_rx_flow_get_fdq_id(rx_chn->rx_chn, 1777 i); 1778 1779 rx_chn->irq = k3_udma_glue_rx_get_irq(rx_chn->rx_chn, i); 1780 1781 if (rx_chn->irq <= 0) { 1782 dev_err(dev, "Failed to get rx dma irq %d\n", 1783 rx_chn->irq); 1784 ret = -ENXIO; 1785 goto err; 1786 } 1787 } 1788 1789 netif_napi_add(common->dma_ndev, &common->napi_rx, 1790 am65_cpsw_nuss_rx_poll); 1791 1792 ret = devm_request_irq(dev, rx_chn->irq, 1793 am65_cpsw_nuss_rx_irq, 1794 IRQF_TRIGGER_HIGH, dev_name(dev), common); 1795 if (ret) { 1796 dev_err(dev, "failure requesting rx irq %u, %d\n", 1797 rx_chn->irq, ret); 1798 goto err; 1799 } 1800 1801 err: 1802 i = devm_add_action(dev, am65_cpsw_nuss_free_rx_chns, common); 1803 if (i) { 1804 dev_err(dev, "Failed to add free_rx_chns action %d\n", i); 1805 return i; 1806 } 1807 1808 return ret; 1809 } 1810 1811 static int am65_cpsw_nuss_init_host_p(struct am65_cpsw_common *common) 1812 { 1813 struct am65_cpsw_host *host_p = am65_common_get_host(common); 1814 1815 host_p->common = common; 1816 host_p->port_base = common->cpsw_base + AM65_CPSW_NU_PORTS_BASE; 1817 host_p->stat_base = common->cpsw_base + AM65_CPSW_NU_STATS_BASE; 1818 1819 return 0; 1820 } 1821 1822 static int am65_cpsw_am654_get_efuse_macid(struct device_node *of_node, 1823 int slave, u8 *mac_addr) 1824 { 1825 u32 mac_lo, mac_hi, offset; 1826 struct regmap *syscon; 1827 int ret; 1828 1829 syscon = syscon_regmap_lookup_by_phandle(of_node, "ti,syscon-efuse"); 1830 if (IS_ERR(syscon)) { 1831 if (PTR_ERR(syscon) == -ENODEV) 1832 return 0; 1833 return PTR_ERR(syscon); 1834 } 1835 1836 ret = of_property_read_u32_index(of_node, "ti,syscon-efuse", 1, 1837 &offset); 1838 if (ret) 1839 return ret; 1840 1841 regmap_read(syscon, offset, &mac_lo); 1842 regmap_read(syscon, offset + 4, &mac_hi); 1843 1844 mac_addr[0] = (mac_hi >> 8) & 0xff; 1845 mac_addr[1] = mac_hi & 0xff; 1846 mac_addr[2] = (mac_lo >> 24) & 0xff; 1847 mac_addr[3] = (mac_lo >> 16) & 0xff; 1848 mac_addr[4] = (mac_lo >> 8) & 0xff; 1849 mac_addr[5] = mac_lo & 0xff; 1850 1851 return 0; 1852 } 1853 1854 static int am65_cpsw_init_cpts(struct am65_cpsw_common *common) 1855 { 1856 struct device *dev = common->dev; 1857 struct device_node *node; 1858 struct am65_cpts *cpts; 1859 void __iomem *reg_base; 1860 1861 if (!IS_ENABLED(CONFIG_TI_K3_AM65_CPTS)) 1862 return 0; 1863 1864 node = of_get_child_by_name(dev->of_node, "cpts"); 1865 if (!node) { 1866 dev_err(dev, "%s cpts not found\n", __func__); 1867 return -ENOENT; 1868 } 1869 1870 reg_base = common->cpsw_base + AM65_CPSW_NU_CPTS_BASE; 1871 cpts = am65_cpts_create(dev, reg_base, node); 1872 if (IS_ERR(cpts)) { 1873 int ret = PTR_ERR(cpts); 1874 1875 of_node_put(node); 1876 if (ret == -EOPNOTSUPP) { 1877 dev_info(dev, "cpts disabled\n"); 1878 return 0; 1879 } 1880 1881 dev_err(dev, "cpts create err %d\n", ret); 1882 return ret; 1883 } 1884 common->cpts = cpts; 1885 /* Forbid PM runtime if CPTS is running. 1886 * K3 CPSWxG modules may completely lose context during ON->OFF 1887 * transitions depending on integration. 1888 * AM65x/J721E MCU CPSW2G: false 1889 * J721E MAIN_CPSW9G: true 1890 */ 1891 pm_runtime_forbid(dev); 1892 1893 return 0; 1894 } 1895 1896 static int am65_cpsw_nuss_init_slave_ports(struct am65_cpsw_common *common) 1897 { 1898 struct device_node *node, *port_np; 1899 struct device *dev = common->dev; 1900 int ret; 1901 1902 node = of_get_child_by_name(dev->of_node, "ethernet-ports"); 1903 if (!node) 1904 return -ENOENT; 1905 1906 for_each_child_of_node(node, port_np) { 1907 struct am65_cpsw_port *port; 1908 u32 port_id; 1909 1910 /* it is not a slave port node, continue */ 1911 if (strcmp(port_np->name, "port")) 1912 continue; 1913 1914 ret = of_property_read_u32(port_np, "reg", &port_id); 1915 if (ret < 0) { 1916 dev_err(dev, "%pOF error reading port_id %d\n", 1917 port_np, ret); 1918 goto of_node_put; 1919 } 1920 1921 if (!port_id || port_id > common->port_num) { 1922 dev_err(dev, "%pOF has invalid port_id %u %s\n", 1923 port_np, port_id, port_np->name); 1924 ret = -EINVAL; 1925 goto of_node_put; 1926 } 1927 1928 port = am65_common_get_port(common, port_id); 1929 port->port_id = port_id; 1930 port->common = common; 1931 port->port_base = common->cpsw_base + AM65_CPSW_NU_PORTS_BASE + 1932 AM65_CPSW_NU_PORTS_OFFSET * (port_id); 1933 if (common->pdata.extra_modes) 1934 port->sgmii_base = common->ss_base + AM65_CPSW_SGMII_BASE * (port_id); 1935 port->stat_base = common->cpsw_base + AM65_CPSW_NU_STATS_BASE + 1936 (AM65_CPSW_NU_STATS_PORT_OFFSET * port_id); 1937 port->name = of_get_property(port_np, "label", NULL); 1938 port->fetch_ram_base = 1939 common->cpsw_base + AM65_CPSW_NU_FRAM_BASE + 1940 (AM65_CPSW_NU_FRAM_PORT_OFFSET * (port_id - 1)); 1941 1942 port->slave.mac_sl = cpsw_sl_get("am65", dev, port->port_base); 1943 if (IS_ERR(port->slave.mac_sl)) { 1944 ret = PTR_ERR(port->slave.mac_sl); 1945 goto of_node_put; 1946 } 1947 1948 port->disabled = !of_device_is_available(port_np); 1949 if (port->disabled) { 1950 common->disabled_ports_mask |= BIT(port->port_id); 1951 continue; 1952 } 1953 1954 port->slave.ifphy = devm_of_phy_get(dev, port_np, NULL); 1955 if (IS_ERR(port->slave.ifphy)) { 1956 ret = PTR_ERR(port->slave.ifphy); 1957 dev_err(dev, "%pOF error retrieving port phy: %d\n", 1958 port_np, ret); 1959 goto of_node_put; 1960 } 1961 1962 port->slave.mac_only = 1963 of_property_read_bool(port_np, "ti,mac-only"); 1964 1965 /* get phy/link info */ 1966 port->slave.phy_node = port_np; 1967 ret = of_get_phy_mode(port_np, &port->slave.phy_if); 1968 if (ret) { 1969 dev_err(dev, "%pOF read phy-mode err %d\n", 1970 port_np, ret); 1971 goto of_node_put; 1972 } 1973 1974 ret = phy_set_mode_ext(port->slave.ifphy, PHY_MODE_ETHERNET, port->slave.phy_if); 1975 if (ret) 1976 goto of_node_put; 1977 1978 ret = of_get_mac_address(port_np, port->slave.mac_addr); 1979 if (ret) { 1980 am65_cpsw_am654_get_efuse_macid(port_np, 1981 port->port_id, 1982 port->slave.mac_addr); 1983 if (!is_valid_ether_addr(port->slave.mac_addr)) { 1984 eth_random_addr(port->slave.mac_addr); 1985 dev_err(dev, "Use random MAC address\n"); 1986 } 1987 } 1988 } 1989 of_node_put(node); 1990 1991 /* is there at least one ext.port */ 1992 if (!(~common->disabled_ports_mask & GENMASK(common->port_num, 1))) { 1993 dev_err(dev, "No Ext. port are available\n"); 1994 return -ENODEV; 1995 } 1996 1997 return 0; 1998 1999 of_node_put: 2000 of_node_put(port_np); 2001 of_node_put(node); 2002 return ret; 2003 } 2004 2005 static void am65_cpsw_pcpu_stats_free(void *data) 2006 { 2007 struct am65_cpsw_ndev_stats __percpu *stats = data; 2008 2009 free_percpu(stats); 2010 } 2011 2012 static void am65_cpsw_nuss_phylink_cleanup(struct am65_cpsw_common *common) 2013 { 2014 struct am65_cpsw_port *port; 2015 int i; 2016 2017 for (i = 0; i < common->port_num; i++) { 2018 port = &common->ports[i]; 2019 if (port->slave.phylink) 2020 phylink_destroy(port->slave.phylink); 2021 } 2022 } 2023 2024 static int 2025 am65_cpsw_nuss_init_port_ndev(struct am65_cpsw_common *common, u32 port_idx) 2026 { 2027 struct am65_cpsw_ndev_priv *ndev_priv; 2028 struct device *dev = common->dev; 2029 struct am65_cpsw_port *port; 2030 struct phylink *phylink; 2031 int ret; 2032 2033 port = &common->ports[port_idx]; 2034 2035 if (port->disabled) 2036 return 0; 2037 2038 /* alloc netdev */ 2039 port->ndev = devm_alloc_etherdev_mqs(common->dev, 2040 sizeof(struct am65_cpsw_ndev_priv), 2041 AM65_CPSW_MAX_TX_QUEUES, 2042 AM65_CPSW_MAX_RX_QUEUES); 2043 if (!port->ndev) { 2044 dev_err(dev, "error allocating slave net_device %u\n", 2045 port->port_id); 2046 return -ENOMEM; 2047 } 2048 2049 ndev_priv = netdev_priv(port->ndev); 2050 ndev_priv->port = port; 2051 ndev_priv->msg_enable = AM65_CPSW_DEBUG; 2052 SET_NETDEV_DEV(port->ndev, dev); 2053 2054 eth_hw_addr_set(port->ndev, port->slave.mac_addr); 2055 2056 port->ndev->min_mtu = AM65_CPSW_MIN_PACKET_SIZE; 2057 port->ndev->max_mtu = AM65_CPSW_MAX_PACKET_SIZE; 2058 port->ndev->hw_features = NETIF_F_SG | 2059 NETIF_F_RXCSUM | 2060 NETIF_F_HW_CSUM | 2061 NETIF_F_HW_TC; 2062 port->ndev->features = port->ndev->hw_features | 2063 NETIF_F_HW_VLAN_CTAG_FILTER; 2064 port->ndev->vlan_features |= NETIF_F_SG; 2065 port->ndev->netdev_ops = &am65_cpsw_nuss_netdev_ops; 2066 port->ndev->ethtool_ops = &am65_cpsw_ethtool_ops_slave; 2067 2068 /* Configuring Phylink */ 2069 port->slave.phylink_config.dev = &port->ndev->dev; 2070 port->slave.phylink_config.type = PHYLINK_NETDEV; 2071 port->slave.phylink_config.mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 | MAC_1000FD; 2072 port->slave.phylink_config.mac_managed_pm = true; /* MAC does PM */ 2073 2074 if (phy_interface_mode_is_rgmii(port->slave.phy_if)) { 2075 phy_interface_set_rgmii(port->slave.phylink_config.supported_interfaces); 2076 } else if (port->slave.phy_if == PHY_INTERFACE_MODE_RMII) { 2077 __set_bit(PHY_INTERFACE_MODE_RMII, 2078 port->slave.phylink_config.supported_interfaces); 2079 } else if (common->pdata.extra_modes & BIT(port->slave.phy_if)) { 2080 __set_bit(PHY_INTERFACE_MODE_QSGMII, 2081 port->slave.phylink_config.supported_interfaces); 2082 } else { 2083 dev_err(dev, "selected phy-mode is not supported\n"); 2084 return -EOPNOTSUPP; 2085 } 2086 2087 phylink = phylink_create(&port->slave.phylink_config, 2088 of_node_to_fwnode(port->slave.phy_node), 2089 port->slave.phy_if, 2090 &am65_cpsw_phylink_mac_ops); 2091 if (IS_ERR(phylink)) 2092 return PTR_ERR(phylink); 2093 2094 port->slave.phylink = phylink; 2095 2096 /* Disable TX checksum offload by default due to HW bug */ 2097 if (common->pdata.quirks & AM65_CPSW_QUIRK_I2027_NO_TX_CSUM) 2098 port->ndev->features &= ~NETIF_F_HW_CSUM; 2099 2100 ndev_priv->stats = netdev_alloc_pcpu_stats(struct am65_cpsw_ndev_stats); 2101 if (!ndev_priv->stats) 2102 return -ENOMEM; 2103 2104 ret = devm_add_action_or_reset(dev, am65_cpsw_pcpu_stats_free, 2105 ndev_priv->stats); 2106 if (ret) 2107 dev_err(dev, "failed to add percpu stat free action %d\n", ret); 2108 2109 if (!common->dma_ndev) 2110 common->dma_ndev = port->ndev; 2111 2112 return ret; 2113 } 2114 2115 static int am65_cpsw_nuss_init_ndevs(struct am65_cpsw_common *common) 2116 { 2117 int ret; 2118 int i; 2119 2120 for (i = 0; i < common->port_num; i++) { 2121 ret = am65_cpsw_nuss_init_port_ndev(common, i); 2122 if (ret) 2123 return ret; 2124 } 2125 2126 return ret; 2127 } 2128 2129 static void am65_cpsw_nuss_cleanup_ndev(struct am65_cpsw_common *common) 2130 { 2131 struct am65_cpsw_port *port; 2132 int i; 2133 2134 for (i = 0; i < common->port_num; i++) { 2135 port = &common->ports[i]; 2136 if (port->ndev && port->ndev->reg_state == NETREG_REGISTERED) 2137 unregister_netdev(port->ndev); 2138 } 2139 } 2140 2141 static void am65_cpsw_port_offload_fwd_mark_update(struct am65_cpsw_common *common) 2142 { 2143 int set_val = 0; 2144 int i; 2145 2146 if (common->br_members == (GENMASK(common->port_num, 1) & ~common->disabled_ports_mask)) 2147 set_val = 1; 2148 2149 dev_dbg(common->dev, "set offload_fwd_mark %d\n", set_val); 2150 2151 for (i = 1; i <= common->port_num; i++) { 2152 struct am65_cpsw_port *port = am65_common_get_port(common, i); 2153 struct am65_cpsw_ndev_priv *priv; 2154 2155 if (!port->ndev) 2156 continue; 2157 2158 priv = am65_ndev_to_priv(port->ndev); 2159 priv->offload_fwd_mark = set_val; 2160 } 2161 } 2162 2163 bool am65_cpsw_port_dev_check(const struct net_device *ndev) 2164 { 2165 if (ndev->netdev_ops == &am65_cpsw_nuss_netdev_ops) { 2166 struct am65_cpsw_common *common = am65_ndev_to_common(ndev); 2167 2168 return !common->is_emac_mode; 2169 } 2170 2171 return false; 2172 } 2173 2174 static int am65_cpsw_netdevice_port_link(struct net_device *ndev, 2175 struct net_device *br_ndev, 2176 struct netlink_ext_ack *extack) 2177 { 2178 struct am65_cpsw_common *common = am65_ndev_to_common(ndev); 2179 struct am65_cpsw_ndev_priv *priv = am65_ndev_to_priv(ndev); 2180 int err; 2181 2182 if (!common->br_members) { 2183 common->hw_bridge_dev = br_ndev; 2184 } else { 2185 /* This is adding the port to a second bridge, this is 2186 * unsupported 2187 */ 2188 if (common->hw_bridge_dev != br_ndev) 2189 return -EOPNOTSUPP; 2190 } 2191 2192 err = switchdev_bridge_port_offload(ndev, ndev, NULL, NULL, NULL, 2193 false, extack); 2194 if (err) 2195 return err; 2196 2197 common->br_members |= BIT(priv->port->port_id); 2198 2199 am65_cpsw_port_offload_fwd_mark_update(common); 2200 2201 return NOTIFY_DONE; 2202 } 2203 2204 static void am65_cpsw_netdevice_port_unlink(struct net_device *ndev) 2205 { 2206 struct am65_cpsw_common *common = am65_ndev_to_common(ndev); 2207 struct am65_cpsw_ndev_priv *priv = am65_ndev_to_priv(ndev); 2208 2209 switchdev_bridge_port_unoffload(ndev, NULL, NULL, NULL); 2210 2211 common->br_members &= ~BIT(priv->port->port_id); 2212 2213 am65_cpsw_port_offload_fwd_mark_update(common); 2214 2215 if (!common->br_members) 2216 common->hw_bridge_dev = NULL; 2217 } 2218 2219 /* netdev notifier */ 2220 static int am65_cpsw_netdevice_event(struct notifier_block *unused, 2221 unsigned long event, void *ptr) 2222 { 2223 struct netlink_ext_ack *extack = netdev_notifier_info_to_extack(ptr); 2224 struct net_device *ndev = netdev_notifier_info_to_dev(ptr); 2225 struct netdev_notifier_changeupper_info *info; 2226 int ret = NOTIFY_DONE; 2227 2228 if (!am65_cpsw_port_dev_check(ndev)) 2229 return NOTIFY_DONE; 2230 2231 switch (event) { 2232 case NETDEV_CHANGEUPPER: 2233 info = ptr; 2234 2235 if (netif_is_bridge_master(info->upper_dev)) { 2236 if (info->linking) 2237 ret = am65_cpsw_netdevice_port_link(ndev, 2238 info->upper_dev, 2239 extack); 2240 else 2241 am65_cpsw_netdevice_port_unlink(ndev); 2242 } 2243 break; 2244 default: 2245 return NOTIFY_DONE; 2246 } 2247 2248 return notifier_from_errno(ret); 2249 } 2250 2251 static int am65_cpsw_register_notifiers(struct am65_cpsw_common *cpsw) 2252 { 2253 int ret = 0; 2254 2255 if (AM65_CPSW_IS_CPSW2G(cpsw) || 2256 !IS_REACHABLE(CONFIG_TI_K3_AM65_CPSW_SWITCHDEV)) 2257 return 0; 2258 2259 cpsw->am65_cpsw_netdevice_nb.notifier_call = &am65_cpsw_netdevice_event; 2260 ret = register_netdevice_notifier(&cpsw->am65_cpsw_netdevice_nb); 2261 if (ret) { 2262 dev_err(cpsw->dev, "can't register netdevice notifier\n"); 2263 return ret; 2264 } 2265 2266 ret = am65_cpsw_switchdev_register_notifiers(cpsw); 2267 if (ret) 2268 unregister_netdevice_notifier(&cpsw->am65_cpsw_netdevice_nb); 2269 2270 return ret; 2271 } 2272 2273 static void am65_cpsw_unregister_notifiers(struct am65_cpsw_common *cpsw) 2274 { 2275 if (AM65_CPSW_IS_CPSW2G(cpsw) || 2276 !IS_REACHABLE(CONFIG_TI_K3_AM65_CPSW_SWITCHDEV)) 2277 return; 2278 2279 am65_cpsw_switchdev_unregister_notifiers(cpsw); 2280 unregister_netdevice_notifier(&cpsw->am65_cpsw_netdevice_nb); 2281 } 2282 2283 static const struct devlink_ops am65_cpsw_devlink_ops = {}; 2284 2285 static void am65_cpsw_init_stp_ale_entry(struct am65_cpsw_common *cpsw) 2286 { 2287 cpsw_ale_add_mcast(cpsw->ale, eth_stp_addr, ALE_PORT_HOST, ALE_SUPER, 0, 2288 ALE_MCAST_BLOCK_LEARN_FWD); 2289 } 2290 2291 static void am65_cpsw_init_host_port_switch(struct am65_cpsw_common *common) 2292 { 2293 struct am65_cpsw_host *host = am65_common_get_host(common); 2294 2295 writel(common->default_vlan, host->port_base + AM65_CPSW_PORT_VLAN_REG_OFFSET); 2296 2297 am65_cpsw_init_stp_ale_entry(common); 2298 2299 cpsw_ale_control_set(common->ale, HOST_PORT_NUM, ALE_P0_UNI_FLOOD, 1); 2300 dev_dbg(common->dev, "Set P0_UNI_FLOOD\n"); 2301 cpsw_ale_control_set(common->ale, HOST_PORT_NUM, ALE_PORT_NOLEARN, 0); 2302 } 2303 2304 static void am65_cpsw_init_host_port_emac(struct am65_cpsw_common *common) 2305 { 2306 struct am65_cpsw_host *host = am65_common_get_host(common); 2307 2308 writel(0, host->port_base + AM65_CPSW_PORT_VLAN_REG_OFFSET); 2309 2310 cpsw_ale_control_set(common->ale, HOST_PORT_NUM, ALE_P0_UNI_FLOOD, 0); 2311 dev_dbg(common->dev, "unset P0_UNI_FLOOD\n"); 2312 2313 /* learning make no sense in multi-mac mode */ 2314 cpsw_ale_control_set(common->ale, HOST_PORT_NUM, ALE_PORT_NOLEARN, 1); 2315 } 2316 2317 static int am65_cpsw_dl_switch_mode_get(struct devlink *dl, u32 id, 2318 struct devlink_param_gset_ctx *ctx) 2319 { 2320 struct am65_cpsw_devlink *dl_priv = devlink_priv(dl); 2321 struct am65_cpsw_common *common = dl_priv->common; 2322 2323 dev_dbg(common->dev, "%s id:%u\n", __func__, id); 2324 2325 if (id != AM65_CPSW_DL_PARAM_SWITCH_MODE) 2326 return -EOPNOTSUPP; 2327 2328 ctx->val.vbool = !common->is_emac_mode; 2329 2330 return 0; 2331 } 2332 2333 static void am65_cpsw_init_port_emac_ale(struct am65_cpsw_port *port) 2334 { 2335 struct am65_cpsw_slave_data *slave = &port->slave; 2336 struct am65_cpsw_common *common = port->common; 2337 u32 port_mask; 2338 2339 writel(slave->port_vlan, port->port_base + AM65_CPSW_PORT_VLAN_REG_OFFSET); 2340 2341 if (slave->mac_only) 2342 /* enable mac-only mode on port */ 2343 cpsw_ale_control_set(common->ale, port->port_id, 2344 ALE_PORT_MACONLY, 1); 2345 2346 cpsw_ale_control_set(common->ale, port->port_id, ALE_PORT_NOLEARN, 1); 2347 2348 port_mask = BIT(port->port_id) | ALE_PORT_HOST; 2349 2350 cpsw_ale_add_ucast(common->ale, port->ndev->dev_addr, 2351 HOST_PORT_NUM, ALE_SECURE, slave->port_vlan); 2352 cpsw_ale_add_mcast(common->ale, port->ndev->broadcast, 2353 port_mask, ALE_VLAN, slave->port_vlan, ALE_MCAST_FWD_2); 2354 } 2355 2356 static void am65_cpsw_init_port_switch_ale(struct am65_cpsw_port *port) 2357 { 2358 struct am65_cpsw_slave_data *slave = &port->slave; 2359 struct am65_cpsw_common *cpsw = port->common; 2360 u32 port_mask; 2361 2362 cpsw_ale_control_set(cpsw->ale, port->port_id, 2363 ALE_PORT_NOLEARN, 0); 2364 2365 cpsw_ale_add_ucast(cpsw->ale, port->ndev->dev_addr, 2366 HOST_PORT_NUM, ALE_SECURE | ALE_BLOCKED | ALE_VLAN, 2367 slave->port_vlan); 2368 2369 port_mask = BIT(port->port_id) | ALE_PORT_HOST; 2370 2371 cpsw_ale_add_mcast(cpsw->ale, port->ndev->broadcast, 2372 port_mask, ALE_VLAN, slave->port_vlan, 2373 ALE_MCAST_FWD_2); 2374 2375 writel(slave->port_vlan, port->port_base + AM65_CPSW_PORT_VLAN_REG_OFFSET); 2376 2377 cpsw_ale_control_set(cpsw->ale, port->port_id, 2378 ALE_PORT_MACONLY, 0); 2379 } 2380 2381 static int am65_cpsw_dl_switch_mode_set(struct devlink *dl, u32 id, 2382 struct devlink_param_gset_ctx *ctx) 2383 { 2384 struct am65_cpsw_devlink *dl_priv = devlink_priv(dl); 2385 struct am65_cpsw_common *cpsw = dl_priv->common; 2386 bool switch_en = ctx->val.vbool; 2387 bool if_running = false; 2388 int i; 2389 2390 dev_dbg(cpsw->dev, "%s id:%u\n", __func__, id); 2391 2392 if (id != AM65_CPSW_DL_PARAM_SWITCH_MODE) 2393 return -EOPNOTSUPP; 2394 2395 if (switch_en == !cpsw->is_emac_mode) 2396 return 0; 2397 2398 if (!switch_en && cpsw->br_members) { 2399 dev_err(cpsw->dev, "Remove ports from bridge before disabling switch mode\n"); 2400 return -EINVAL; 2401 } 2402 2403 rtnl_lock(); 2404 2405 cpsw->is_emac_mode = !switch_en; 2406 2407 for (i = 0; i < cpsw->port_num; i++) { 2408 struct net_device *sl_ndev = cpsw->ports[i].ndev; 2409 2410 if (!sl_ndev || !netif_running(sl_ndev)) 2411 continue; 2412 2413 if_running = true; 2414 } 2415 2416 if (!if_running) { 2417 /* all ndevs are down */ 2418 for (i = 0; i < cpsw->port_num; i++) { 2419 struct net_device *sl_ndev = cpsw->ports[i].ndev; 2420 struct am65_cpsw_slave_data *slave; 2421 2422 if (!sl_ndev) 2423 continue; 2424 2425 slave = am65_ndev_to_slave(sl_ndev); 2426 if (switch_en) 2427 slave->port_vlan = cpsw->default_vlan; 2428 else 2429 slave->port_vlan = 0; 2430 } 2431 2432 goto exit; 2433 } 2434 2435 cpsw_ale_control_set(cpsw->ale, 0, ALE_BYPASS, 1); 2436 /* clean up ALE table */ 2437 cpsw_ale_control_set(cpsw->ale, HOST_PORT_NUM, ALE_CLEAR, 1); 2438 cpsw_ale_control_get(cpsw->ale, HOST_PORT_NUM, ALE_AGEOUT); 2439 2440 if (switch_en) { 2441 dev_info(cpsw->dev, "Enable switch mode\n"); 2442 2443 am65_cpsw_init_host_port_switch(cpsw); 2444 2445 for (i = 0; i < cpsw->port_num; i++) { 2446 struct net_device *sl_ndev = cpsw->ports[i].ndev; 2447 struct am65_cpsw_slave_data *slave; 2448 struct am65_cpsw_port *port; 2449 2450 if (!sl_ndev) 2451 continue; 2452 2453 port = am65_ndev_to_port(sl_ndev); 2454 slave = am65_ndev_to_slave(sl_ndev); 2455 slave->port_vlan = cpsw->default_vlan; 2456 2457 if (netif_running(sl_ndev)) 2458 am65_cpsw_init_port_switch_ale(port); 2459 } 2460 2461 } else { 2462 dev_info(cpsw->dev, "Disable switch mode\n"); 2463 2464 am65_cpsw_init_host_port_emac(cpsw); 2465 2466 for (i = 0; i < cpsw->port_num; i++) { 2467 struct net_device *sl_ndev = cpsw->ports[i].ndev; 2468 struct am65_cpsw_port *port; 2469 2470 if (!sl_ndev) 2471 continue; 2472 2473 port = am65_ndev_to_port(sl_ndev); 2474 port->slave.port_vlan = 0; 2475 if (netif_running(sl_ndev)) 2476 am65_cpsw_init_port_emac_ale(port); 2477 } 2478 } 2479 cpsw_ale_control_set(cpsw->ale, HOST_PORT_NUM, ALE_BYPASS, 0); 2480 exit: 2481 rtnl_unlock(); 2482 2483 return 0; 2484 } 2485 2486 static const struct devlink_param am65_cpsw_devlink_params[] = { 2487 DEVLINK_PARAM_DRIVER(AM65_CPSW_DL_PARAM_SWITCH_MODE, "switch_mode", 2488 DEVLINK_PARAM_TYPE_BOOL, 2489 BIT(DEVLINK_PARAM_CMODE_RUNTIME), 2490 am65_cpsw_dl_switch_mode_get, 2491 am65_cpsw_dl_switch_mode_set, NULL), 2492 }; 2493 2494 static int am65_cpsw_nuss_register_devlink(struct am65_cpsw_common *common) 2495 { 2496 struct devlink_port_attrs attrs = {}; 2497 struct am65_cpsw_devlink *dl_priv; 2498 struct device *dev = common->dev; 2499 struct devlink_port *dl_port; 2500 struct am65_cpsw_port *port; 2501 int ret = 0; 2502 int i; 2503 2504 common->devlink = 2505 devlink_alloc(&am65_cpsw_devlink_ops, sizeof(*dl_priv), dev); 2506 if (!common->devlink) 2507 return -ENOMEM; 2508 2509 dl_priv = devlink_priv(common->devlink); 2510 dl_priv->common = common; 2511 2512 /* Provide devlink hook to switch mode when multiple external ports 2513 * are present NUSS switchdev driver is enabled. 2514 */ 2515 if (!AM65_CPSW_IS_CPSW2G(common) && 2516 IS_ENABLED(CONFIG_TI_K3_AM65_CPSW_SWITCHDEV)) { 2517 ret = devlink_params_register(common->devlink, 2518 am65_cpsw_devlink_params, 2519 ARRAY_SIZE(am65_cpsw_devlink_params)); 2520 if (ret) { 2521 dev_err(dev, "devlink params reg fail ret:%d\n", ret); 2522 goto dl_unreg; 2523 } 2524 } 2525 2526 for (i = 1; i <= common->port_num; i++) { 2527 port = am65_common_get_port(common, i); 2528 dl_port = &port->devlink_port; 2529 2530 if (port->ndev) 2531 attrs.flavour = DEVLINK_PORT_FLAVOUR_PHYSICAL; 2532 else 2533 attrs.flavour = DEVLINK_PORT_FLAVOUR_UNUSED; 2534 attrs.phys.port_number = port->port_id; 2535 attrs.switch_id.id_len = sizeof(resource_size_t); 2536 memcpy(attrs.switch_id.id, common->switch_id, attrs.switch_id.id_len); 2537 devlink_port_attrs_set(dl_port, &attrs); 2538 2539 ret = devlink_port_register(common->devlink, dl_port, port->port_id); 2540 if (ret) { 2541 dev_err(dev, "devlink_port reg fail for port %d, ret:%d\n", 2542 port->port_id, ret); 2543 goto dl_port_unreg; 2544 } 2545 } 2546 devlink_register(common->devlink); 2547 return ret; 2548 2549 dl_port_unreg: 2550 for (i = i - 1; i >= 1; i--) { 2551 port = am65_common_get_port(common, i); 2552 dl_port = &port->devlink_port; 2553 2554 devlink_port_unregister(dl_port); 2555 } 2556 dl_unreg: 2557 devlink_free(common->devlink); 2558 return ret; 2559 } 2560 2561 static void am65_cpsw_unregister_devlink(struct am65_cpsw_common *common) 2562 { 2563 struct devlink_port *dl_port; 2564 struct am65_cpsw_port *port; 2565 int i; 2566 2567 devlink_unregister(common->devlink); 2568 2569 for (i = 1; i <= common->port_num; i++) { 2570 port = am65_common_get_port(common, i); 2571 dl_port = &port->devlink_port; 2572 2573 devlink_port_unregister(dl_port); 2574 } 2575 2576 if (!AM65_CPSW_IS_CPSW2G(common) && 2577 IS_ENABLED(CONFIG_TI_K3_AM65_CPSW_SWITCHDEV)) 2578 devlink_params_unregister(common->devlink, 2579 am65_cpsw_devlink_params, 2580 ARRAY_SIZE(am65_cpsw_devlink_params)); 2581 2582 devlink_free(common->devlink); 2583 } 2584 2585 static int am65_cpsw_nuss_register_ndevs(struct am65_cpsw_common *common) 2586 { 2587 struct device *dev = common->dev; 2588 struct am65_cpsw_port *port; 2589 int ret = 0, i; 2590 2591 /* init tx channels */ 2592 ret = am65_cpsw_nuss_init_tx_chns(common); 2593 if (ret) 2594 return ret; 2595 ret = am65_cpsw_nuss_init_rx_chns(common); 2596 if (ret) 2597 return ret; 2598 2599 ret = am65_cpsw_nuss_register_devlink(common); 2600 if (ret) 2601 return ret; 2602 2603 for (i = 0; i < common->port_num; i++) { 2604 port = &common->ports[i]; 2605 2606 if (!port->ndev) 2607 continue; 2608 2609 SET_NETDEV_DEVLINK_PORT(port->ndev, &port->devlink_port); 2610 2611 ret = register_netdev(port->ndev); 2612 if (ret) { 2613 dev_err(dev, "error registering slave net device%i %d\n", 2614 i, ret); 2615 goto err_cleanup_ndev; 2616 } 2617 } 2618 2619 ret = am65_cpsw_register_notifiers(common); 2620 if (ret) 2621 goto err_cleanup_ndev; 2622 2623 /* can't auto unregister ndev using devm_add_action() due to 2624 * devres release sequence in DD core for DMA 2625 */ 2626 2627 return 0; 2628 2629 err_cleanup_ndev: 2630 am65_cpsw_nuss_cleanup_ndev(common); 2631 am65_cpsw_unregister_devlink(common); 2632 2633 return ret; 2634 } 2635 2636 int am65_cpsw_nuss_update_tx_chns(struct am65_cpsw_common *common, int num_tx) 2637 { 2638 int ret; 2639 2640 common->tx_ch_num = num_tx; 2641 ret = am65_cpsw_nuss_init_tx_chns(common); 2642 2643 return ret; 2644 } 2645 2646 struct am65_cpsw_soc_pdata { 2647 u32 quirks_dis; 2648 }; 2649 2650 static const struct am65_cpsw_soc_pdata am65x_soc_sr2_0 = { 2651 .quirks_dis = AM65_CPSW_QUIRK_I2027_NO_TX_CSUM, 2652 }; 2653 2654 static const struct soc_device_attribute am65_cpsw_socinfo[] = { 2655 { .family = "AM65X", 2656 .revision = "SR2.0", 2657 .data = &am65x_soc_sr2_0 2658 }, 2659 {/* sentinel */} 2660 }; 2661 2662 static const struct am65_cpsw_pdata am65x_sr1_0 = { 2663 .quirks = AM65_CPSW_QUIRK_I2027_NO_TX_CSUM, 2664 .ale_dev_id = "am65x-cpsw2g", 2665 .fdqring_mode = K3_RINGACC_RING_MODE_MESSAGE, 2666 }; 2667 2668 static const struct am65_cpsw_pdata j721e_pdata = { 2669 .quirks = 0, 2670 .ale_dev_id = "am65x-cpsw2g", 2671 .fdqring_mode = K3_RINGACC_RING_MODE_MESSAGE, 2672 }; 2673 2674 static const struct am65_cpsw_pdata am64x_cpswxg_pdata = { 2675 .quirks = 0, 2676 .ale_dev_id = "am64-cpswxg", 2677 .fdqring_mode = K3_RINGACC_RING_MODE_RING, 2678 }; 2679 2680 static const struct am65_cpsw_pdata j7200_cpswxg_pdata = { 2681 .quirks = 0, 2682 .ale_dev_id = "am64-cpswxg", 2683 .fdqring_mode = K3_RINGACC_RING_MODE_RING, 2684 .extra_modes = BIT(PHY_INTERFACE_MODE_QSGMII), 2685 }; 2686 2687 static const struct of_device_id am65_cpsw_nuss_of_mtable[] = { 2688 { .compatible = "ti,am654-cpsw-nuss", .data = &am65x_sr1_0}, 2689 { .compatible = "ti,j721e-cpsw-nuss", .data = &j721e_pdata}, 2690 { .compatible = "ti,am642-cpsw-nuss", .data = &am64x_cpswxg_pdata}, 2691 { .compatible = "ti,j7200-cpswxg-nuss", .data = &j7200_cpswxg_pdata}, 2692 { /* sentinel */ }, 2693 }; 2694 MODULE_DEVICE_TABLE(of, am65_cpsw_nuss_of_mtable); 2695 2696 static void am65_cpsw_nuss_apply_socinfo(struct am65_cpsw_common *common) 2697 { 2698 const struct soc_device_attribute *soc; 2699 2700 soc = soc_device_match(am65_cpsw_socinfo); 2701 if (soc && soc->data) { 2702 const struct am65_cpsw_soc_pdata *socdata = soc->data; 2703 2704 /* disable quirks */ 2705 common->pdata.quirks &= ~socdata->quirks_dis; 2706 } 2707 } 2708 2709 static int am65_cpsw_nuss_probe(struct platform_device *pdev) 2710 { 2711 struct cpsw_ale_params ale_params = { 0 }; 2712 const struct of_device_id *of_id; 2713 struct device *dev = &pdev->dev; 2714 struct am65_cpsw_common *common; 2715 struct device_node *node; 2716 struct resource *res; 2717 struct clk *clk; 2718 u64 id_temp; 2719 int ret, i; 2720 int ale_entries; 2721 2722 common = devm_kzalloc(dev, sizeof(struct am65_cpsw_common), GFP_KERNEL); 2723 if (!common) 2724 return -ENOMEM; 2725 common->dev = dev; 2726 2727 of_id = of_match_device(am65_cpsw_nuss_of_mtable, dev); 2728 if (!of_id) 2729 return -EINVAL; 2730 common->pdata = *(const struct am65_cpsw_pdata *)of_id->data; 2731 2732 am65_cpsw_nuss_apply_socinfo(common); 2733 2734 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cpsw_nuss"); 2735 common->ss_base = devm_ioremap_resource(&pdev->dev, res); 2736 if (IS_ERR(common->ss_base)) 2737 return PTR_ERR(common->ss_base); 2738 common->cpsw_base = common->ss_base + AM65_CPSW_CPSW_NU_BASE; 2739 /* Use device's physical base address as switch id */ 2740 id_temp = cpu_to_be64(res->start); 2741 memcpy(common->switch_id, &id_temp, sizeof(res->start)); 2742 2743 node = of_get_child_by_name(dev->of_node, "ethernet-ports"); 2744 if (!node) 2745 return -ENOENT; 2746 common->port_num = of_get_child_count(node); 2747 of_node_put(node); 2748 if (common->port_num < 1 || common->port_num > AM65_CPSW_MAX_PORTS) 2749 return -ENOENT; 2750 2751 common->rx_flow_id_base = -1; 2752 init_completion(&common->tdown_complete); 2753 common->tx_ch_num = 1; 2754 common->pf_p0_rx_ptype_rrobin = false; 2755 common->default_vlan = 1; 2756 2757 common->ports = devm_kcalloc(dev, common->port_num, 2758 sizeof(*common->ports), 2759 GFP_KERNEL); 2760 if (!common->ports) 2761 return -ENOMEM; 2762 2763 clk = devm_clk_get(dev, "fck"); 2764 if (IS_ERR(clk)) 2765 return dev_err_probe(dev, PTR_ERR(clk), "getting fck clock\n"); 2766 common->bus_freq = clk_get_rate(clk); 2767 2768 pm_runtime_enable(dev); 2769 ret = pm_runtime_resume_and_get(dev); 2770 if (ret < 0) { 2771 pm_runtime_disable(dev); 2772 return ret; 2773 } 2774 2775 node = of_get_child_by_name(dev->of_node, "mdio"); 2776 if (!node) { 2777 dev_warn(dev, "MDIO node not found\n"); 2778 } else if (of_device_is_available(node)) { 2779 struct platform_device *mdio_pdev; 2780 2781 mdio_pdev = of_platform_device_create(node, NULL, dev); 2782 if (!mdio_pdev) { 2783 ret = -ENODEV; 2784 goto err_pm_clear; 2785 } 2786 2787 common->mdio_dev = &mdio_pdev->dev; 2788 } 2789 of_node_put(node); 2790 2791 am65_cpsw_nuss_get_ver(common); 2792 2793 ret = am65_cpsw_nuss_init_host_p(common); 2794 if (ret) 2795 goto err_of_clear; 2796 2797 ret = am65_cpsw_nuss_init_slave_ports(common); 2798 if (ret) 2799 goto err_of_clear; 2800 2801 /* init common data */ 2802 ale_params.dev = dev; 2803 ale_params.ale_ageout = AM65_CPSW_ALE_AGEOUT_DEFAULT; 2804 ale_params.ale_ports = common->port_num + 1; 2805 ale_params.ale_regs = common->cpsw_base + AM65_CPSW_NU_ALE_BASE; 2806 ale_params.dev_id = common->pdata.ale_dev_id; 2807 ale_params.bus_freq = common->bus_freq; 2808 2809 common->ale = cpsw_ale_create(&ale_params); 2810 if (IS_ERR(common->ale)) { 2811 dev_err(dev, "error initializing ale engine\n"); 2812 ret = PTR_ERR(common->ale); 2813 goto err_of_clear; 2814 } 2815 2816 ale_entries = common->ale->params.ale_entries; 2817 common->ale_context = devm_kzalloc(dev, 2818 ale_entries * ALE_ENTRY_WORDS * sizeof(u32), 2819 GFP_KERNEL); 2820 ret = am65_cpsw_init_cpts(common); 2821 if (ret) 2822 goto err_of_clear; 2823 2824 /* init ports */ 2825 for (i = 0; i < common->port_num; i++) 2826 am65_cpsw_nuss_slave_disable_unused(&common->ports[i]); 2827 2828 dev_set_drvdata(dev, common); 2829 2830 common->is_emac_mode = true; 2831 2832 ret = am65_cpsw_nuss_init_ndevs(common); 2833 if (ret) 2834 goto err_free_phylink; 2835 2836 ret = am65_cpsw_nuss_register_ndevs(common); 2837 if (ret) 2838 goto err_free_phylink; 2839 2840 pm_runtime_put(dev); 2841 return 0; 2842 2843 err_free_phylink: 2844 am65_cpsw_nuss_phylink_cleanup(common); 2845 err_of_clear: 2846 of_platform_device_destroy(common->mdio_dev, NULL); 2847 err_pm_clear: 2848 pm_runtime_put_sync(dev); 2849 pm_runtime_disable(dev); 2850 return ret; 2851 } 2852 2853 static int am65_cpsw_nuss_remove(struct platform_device *pdev) 2854 { 2855 struct device *dev = &pdev->dev; 2856 struct am65_cpsw_common *common; 2857 int ret; 2858 2859 common = dev_get_drvdata(dev); 2860 2861 ret = pm_runtime_resume_and_get(&pdev->dev); 2862 if (ret < 0) 2863 return ret; 2864 2865 am65_cpsw_unregister_devlink(common); 2866 am65_cpsw_unregister_notifiers(common); 2867 2868 /* must unregister ndevs here because DD release_driver routine calls 2869 * dma_deconfigure(dev) before devres_release_all(dev) 2870 */ 2871 am65_cpsw_nuss_cleanup_ndev(common); 2872 am65_cpsw_nuss_phylink_cleanup(common); 2873 2874 of_platform_device_destroy(common->mdio_dev, NULL); 2875 2876 pm_runtime_put_sync(&pdev->dev); 2877 pm_runtime_disable(&pdev->dev); 2878 return 0; 2879 } 2880 2881 static int am65_cpsw_nuss_suspend(struct device *dev) 2882 { 2883 struct am65_cpsw_common *common = dev_get_drvdata(dev); 2884 struct am65_cpsw_host *host_p = am65_common_get_host(common); 2885 struct am65_cpsw_port *port; 2886 struct net_device *ndev; 2887 int i, ret; 2888 2889 cpsw_ale_dump(common->ale, common->ale_context); 2890 host_p->vid_context = readl(host_p->port_base + AM65_CPSW_PORT_VLAN_REG_OFFSET); 2891 for (i = 0; i < common->port_num; i++) { 2892 port = &common->ports[i]; 2893 ndev = port->ndev; 2894 2895 if (!ndev) 2896 continue; 2897 2898 port->vid_context = readl(port->port_base + AM65_CPSW_PORT_VLAN_REG_OFFSET); 2899 netif_device_detach(ndev); 2900 if (netif_running(ndev)) { 2901 rtnl_lock(); 2902 ret = am65_cpsw_nuss_ndo_slave_stop(ndev); 2903 rtnl_unlock(); 2904 if (ret < 0) { 2905 netdev_err(ndev, "failed to stop: %d", ret); 2906 return ret; 2907 } 2908 } 2909 } 2910 2911 am65_cpts_suspend(common->cpts); 2912 2913 am65_cpsw_nuss_remove_rx_chns(common); 2914 am65_cpsw_nuss_remove_tx_chns(common); 2915 2916 return 0; 2917 } 2918 2919 static int am65_cpsw_nuss_resume(struct device *dev) 2920 { 2921 struct am65_cpsw_common *common = dev_get_drvdata(dev); 2922 struct am65_cpsw_port *port; 2923 struct net_device *ndev; 2924 int i, ret; 2925 struct am65_cpsw_host *host_p = am65_common_get_host(common); 2926 2927 ret = am65_cpsw_nuss_init_tx_chns(common); 2928 if (ret) 2929 return ret; 2930 ret = am65_cpsw_nuss_init_rx_chns(common); 2931 if (ret) 2932 return ret; 2933 2934 /* If RX IRQ was disabled before suspend, keep it disabled */ 2935 if (common->rx_irq_disabled) 2936 disable_irq(common->rx_chns.irq); 2937 2938 am65_cpts_resume(common->cpts); 2939 2940 for (i = 0; i < common->port_num; i++) { 2941 port = &common->ports[i]; 2942 ndev = port->ndev; 2943 2944 if (!ndev) 2945 continue; 2946 2947 if (netif_running(ndev)) { 2948 rtnl_lock(); 2949 ret = am65_cpsw_nuss_ndo_slave_open(ndev); 2950 rtnl_unlock(); 2951 if (ret < 0) { 2952 netdev_err(ndev, "failed to start: %d", ret); 2953 return ret; 2954 } 2955 } 2956 2957 netif_device_attach(ndev); 2958 writel(port->vid_context, port->port_base + AM65_CPSW_PORT_VLAN_REG_OFFSET); 2959 } 2960 2961 writel(host_p->vid_context, host_p->port_base + AM65_CPSW_PORT_VLAN_REG_OFFSET); 2962 cpsw_ale_restore(common->ale, common->ale_context); 2963 2964 return 0; 2965 } 2966 2967 static const struct dev_pm_ops am65_cpsw_nuss_dev_pm_ops = { 2968 SYSTEM_SLEEP_PM_OPS(am65_cpsw_nuss_suspend, am65_cpsw_nuss_resume) 2969 }; 2970 2971 static struct platform_driver am65_cpsw_nuss_driver = { 2972 .driver = { 2973 .name = AM65_CPSW_DRV_NAME, 2974 .of_match_table = am65_cpsw_nuss_of_mtable, 2975 .pm = &am65_cpsw_nuss_dev_pm_ops, 2976 }, 2977 .probe = am65_cpsw_nuss_probe, 2978 .remove = am65_cpsw_nuss_remove, 2979 }; 2980 2981 module_platform_driver(am65_cpsw_nuss_driver); 2982 2983 MODULE_LICENSE("GPL v2"); 2984 MODULE_AUTHOR("Grygorii Strashko <grygorii.strashko@ti.com>"); 2985 MODULE_DESCRIPTION("TI AM65 CPSW Ethernet driver"); 2986