1 /*
2  * Tehuti Networks(R) Network Driver
3  * Copyright (C) 2007 Tehuti Networks Ltd. All rights reserved
4  *
5  * This program is free software; you can redistribute it and/or modify
6  * it under the terms of the GNU General Public License as published by
7  * the Free Software Foundation; either version 2 of the License, or
8  * (at your option) any later version.
9  */
10 
11 #ifndef _TEHUTI_H
12 #define _TEHUTI_H
13 
14 #include <linux/module.h>
15 #include <linux/kernel.h>
16 #include <linux/netdevice.h>
17 #include <linux/etherdevice.h>
18 #include <linux/pci.h>
19 #include <linux/delay.h>
20 #include <linux/ethtool.h>
21 #include <linux/mii.h>
22 #include <linux/crc32.h>
23 #include <linux/uaccess.h>
24 #include <linux/in.h>
25 #include <linux/ip.h>
26 #include <linux/tcp.h>
27 #include <linux/sched.h>
28 #include <linux/tty.h>
29 #include <linux/if_vlan.h>
30 #include <linux/interrupt.h>
31 #include <linux/vmalloc.h>
32 #include <linux/firmware.h>
33 #include <asm/byteorder.h>
34 #include <linux/dma-mapping.h>
35 #include <linux/slab.h>
36 
37 /* Compile Time Switches */
38 /* start */
39 #define BDX_TSO
40 #define BDX_LLTX
41 #define BDX_DELAY_WPTR
42 /* #define BDX_MSI */
43 /* end */
44 
45 #if !defined CONFIG_PCI_MSI
46 #   undef BDX_MSI
47 #endif
48 
49 #define BDX_DEF_MSG_ENABLE	(NETIF_MSG_DRV          | \
50 				NETIF_MSG_PROBE        | \
51 				NETIF_MSG_LINK)
52 
53 /* ioctl ops */
54 #define BDX_OP_READ  1
55 #define BDX_OP_WRITE 2
56 
57 /* RX copy break size */
58 #define BDX_COPYBREAK    257
59 
60 #define DRIVER_AUTHOR     "Tehuti Networks(R)"
61 #define BDX_DRV_DESC      "Tehuti Networks(R) Network Driver"
62 #define BDX_DRV_NAME      "tehuti"
63 #define BDX_NIC_NAME      "Tehuti 10 Giga TOE SmartNIC"
64 #define BDX_NIC2PORT_NAME "Tehuti 2-Port 10 Giga TOE SmartNIC"
65 #define BDX_DRV_VERSION   "7.29.3"
66 
67 #ifdef BDX_MSI
68 #    define BDX_MSI_STRING "msi "
69 #else
70 #    define BDX_MSI_STRING ""
71 #endif
72 
73 /* netdev tx queue len for Luxor. default value is, btw, 1000
74  * ifcontig eth1 txqueuelen 3000 - to change it at runtime */
75 #define BDX_NDEV_TXQ_LEN 3000
76 
77 /* Max MTU for Jumbo Frame mode, per tehutinetworks.net Features FAQ is 16k */
78 #define BDX_MAX_MTU	(16 * 1024)
79 
80 #define FIFO_SIZE  4096
81 #define FIFO_EXTRA_SPACE            1024
82 
83 #if BITS_PER_LONG == 64
84 #    define H32_64(x)  (u32) ((u64)(x) >> 32)
85 #    define L32_64(x)  (u32) ((u64)(x) & 0xffffffff)
86 #elif BITS_PER_LONG == 32
87 #    define H32_64(x)  0
88 #    define L32_64(x)  ((u32) (x))
89 #else				/* BITS_PER_LONG == ?? */
90 #    error BITS_PER_LONG is undefined. Must be 64 or 32
91 #endif				/* BITS_PER_LONG */
92 
93 #ifdef __BIG_ENDIAN
94 #   define CPU_CHIP_SWAP32(x) swab32(x)
95 #   define CPU_CHIP_SWAP16(x) swab16(x)
96 #else
97 #   define CPU_CHIP_SWAP32(x) (x)
98 #   define CPU_CHIP_SWAP16(x) (x)
99 #endif
100 
101 #define READ_REG(pp, reg)         readl(pp->pBdxRegs + reg)
102 #define WRITE_REG(pp, reg, val)   writel(val, pp->pBdxRegs + reg)
103 
104 #ifndef NET_IP_ALIGN
105 #   define NET_IP_ALIGN 2
106 #endif
107 
108 #ifndef NETDEV_TX_OK
109 #   define NETDEV_TX_OK 0
110 #endif
111 
112 #define LUXOR_MAX_PORT     2
113 #define BDX_MAX_RX_DONE    150
114 #define BDX_TXF_DESC_SZ    16
115 #define BDX_MAX_TX_LEVEL   (priv->txd_fifo0.m.memsz - 16)
116 #define BDX_MIN_TX_LEVEL   256
117 #define BDX_NO_UPD_PACKETS 40
118 
119 struct pci_nic {
120 	int port_num;
121 	void __iomem *regs;
122 	int irq_type;
123 	struct bdx_priv *priv[LUXOR_MAX_PORT];
124 };
125 
126 enum { IRQ_INTX, IRQ_MSI, IRQ_MSIX };
127 
128 #define PCK_TH_MULT   128
129 #define INT_COAL_MULT 2
130 
131 #define BITS_MASK(nbits)			((1<<nbits)-1)
132 #define GET_BITS_SHIFT(x, nbits, nshift)	(((x)>>nshift)&BITS_MASK(nbits))
133 #define BITS_SHIFT_MASK(nbits, nshift)		(BITS_MASK(nbits)<<nshift)
134 #define BITS_SHIFT_VAL(x, nbits, nshift)	(((x)&BITS_MASK(nbits))<<nshift)
135 #define BITS_SHIFT_CLEAR(x, nbits, nshift)	\
136 	((x)&(~BITS_SHIFT_MASK(nbits, nshift)))
137 
138 #define GET_INT_COAL(x)				GET_BITS_SHIFT(x, 15, 0)
139 #define GET_INT_COAL_RC(x)			GET_BITS_SHIFT(x, 1, 15)
140 #define GET_RXF_TH(x)				GET_BITS_SHIFT(x, 4, 16)
141 #define GET_PCK_TH(x)				GET_BITS_SHIFT(x, 4, 20)
142 
143 #define INT_REG_VAL(coal, coal_rc, rxf_th, pck_th)	\
144 	((coal)|((coal_rc)<<15)|((rxf_th)<<16)|((pck_th)<<20))
145 
146 struct fifo {
147 	dma_addr_t da;		/* physical address of fifo (used by HW) */
148 	char *va;		/* virtual address of fifo (used by SW) */
149 	u32 rptr, wptr;		/* cached values of RPTR and WPTR registers,
150 				   they're 32 bits on both 32 and 64 archs */
151 	u16 reg_CFG0, reg_CFG1;
152 	u16 reg_RPTR, reg_WPTR;
153 	u16 memsz;		/* memory size allocated for fifo */
154 	u16 size_mask;
155 	u16 pktsz;		/* skb packet size to allocate */
156 	u16 rcvno;		/* number of buffers that come from this RXF */
157 };
158 
159 struct txf_fifo {
160 	struct fifo m;		/* minimal set of variables used by all fifos */
161 };
162 
163 struct txd_fifo {
164 	struct fifo m;		/* minimal set of variables used by all fifos */
165 };
166 
167 struct rxf_fifo {
168 	struct fifo m;		/* minimal set of variables used by all fifos */
169 };
170 
171 struct rxd_fifo {
172 	struct fifo m;		/* minimal set of variables used by all fifos */
173 };
174 
175 struct rx_map {
176 	u64 dma;
177 	struct sk_buff *skb;
178 };
179 
180 struct rxdb {
181 	int *stack;
182 	struct rx_map *elems;
183 	int nelem;
184 	int top;
185 };
186 
187 union bdx_dma_addr {
188 	dma_addr_t dma;
189 	struct sk_buff *skb;
190 };
191 
192 /* Entry in the db.
193  * if len == 0 addr is dma
194  * if len != 0 addr is skb */
195 struct tx_map {
196 	union bdx_dma_addr addr;
197 	int len;
198 };
199 
200 /* tx database - implemented as circular fifo buffer*/
201 struct txdb {
202 	struct tx_map *start;	/* points to the first element */
203 	struct tx_map *end;	/* points just AFTER the last element */
204 	struct tx_map *rptr;	/* points to the next element to read */
205 	struct tx_map *wptr;	/* points to the next element to write */
206 	int size;		/* number of elements in the db */
207 };
208 
209 /*Internal stats structure*/
210 struct bdx_stats {
211 	u64 InUCast;			/* 0x7200 */
212 	u64 InMCast;			/* 0x7210 */
213 	u64 InBCast;			/* 0x7220 */
214 	u64 InPkts;			/* 0x7230 */
215 	u64 InErrors;			/* 0x7240 */
216 	u64 InDropped;			/* 0x7250 */
217 	u64 FrameTooLong;		/* 0x7260 */
218 	u64 FrameSequenceErrors;	/* 0x7270 */
219 	u64 InVLAN;			/* 0x7280 */
220 	u64 InDroppedDFE;		/* 0x7290 */
221 	u64 InDroppedIntFull;		/* 0x72A0 */
222 	u64 InFrameAlignErrors;		/* 0x72B0 */
223 
224 	/* 0x72C0-0x72E0 RSRV */
225 
226 	u64 OutUCast;			/* 0x72F0 */
227 	u64 OutMCast;			/* 0x7300 */
228 	u64 OutBCast;			/* 0x7310 */
229 	u64 OutPkts;			/* 0x7320 */
230 
231 	/* 0x7330-0x7360 RSRV */
232 
233 	u64 OutVLAN;			/* 0x7370 */
234 	u64 InUCastOctects;		/* 0x7380 */
235 	u64 OutUCastOctects;		/* 0x7390 */
236 
237 	/* 0x73A0-0x73B0 RSRV */
238 
239 	u64 InBCastOctects;		/* 0x73C0 */
240 	u64 OutBCastOctects;		/* 0x73D0 */
241 	u64 InOctects;			/* 0x73E0 */
242 	u64 OutOctects;			/* 0x73F0 */
243 };
244 
245 struct bdx_priv {
246 	void __iomem *pBdxRegs;
247 	struct net_device *ndev;
248 
249 	struct napi_struct napi;
250 
251 	/* RX FIFOs: 1 for data (full) descs, and 2 for free descs */
252 	struct rxd_fifo rxd_fifo0;
253 	struct rxf_fifo rxf_fifo0;
254 	struct rxdb *rxdb;	/* rx dbs to store skb pointers */
255 	int napi_stop;
256 
257 	/* Tx FIFOs: 1 for data desc, 1 for empty (acks) desc */
258 	struct txd_fifo txd_fifo0;
259 	struct txf_fifo txf_fifo0;
260 
261 	struct txdb txdb;
262 	int tx_level;
263 #ifdef BDX_DELAY_WPTR
264 	int tx_update_mark;
265 	int tx_noupd;
266 #endif
267 	spinlock_t tx_lock;	/* NETIF_F_LLTX mode */
268 
269 	/* rarely used */
270 	u8 port;
271 	u32 msg_enable;
272 	int stats_flag;
273 	struct bdx_stats hw_stats;
274 	struct pci_dev *pdev;
275 
276 	struct pci_nic *nic;
277 
278 	u8 txd_size;
279 	u8 txf_size;
280 	u8 rxd_size;
281 	u8 rxf_size;
282 	u32 rdintcm;
283 	u32 tdintcm;
284 };
285 
286 /* RX FREE descriptor - 64bit*/
287 struct rxf_desc {
288 	u32 info;		/* Buffer Count + Info - described below */
289 	u32 va_lo;		/* VAdr[31:0] */
290 	u32 va_hi;		/* VAdr[63:32] */
291 	u32 pa_lo;		/* PAdr[31:0] */
292 	u32 pa_hi;		/* PAdr[63:32] */
293 	u32 len;		/* Buffer Length */
294 };
295 
296 #define GET_RXD_BC(x)			GET_BITS_SHIFT((x), 5, 0)
297 #define GET_RXD_RXFQ(x)			GET_BITS_SHIFT((x), 2, 8)
298 #define GET_RXD_TO(x)			GET_BITS_SHIFT((x), 1, 15)
299 #define GET_RXD_TYPE(x)			GET_BITS_SHIFT((x), 4, 16)
300 #define GET_RXD_ERR(x)			GET_BITS_SHIFT((x), 6, 21)
301 #define GET_RXD_RXP(x)			GET_BITS_SHIFT((x), 1, 27)
302 #define GET_RXD_PKT_ID(x)		GET_BITS_SHIFT((x), 3, 28)
303 #define GET_RXD_VTAG(x)			GET_BITS_SHIFT((x), 1, 31)
304 #define GET_RXD_VLAN_ID(x)		GET_BITS_SHIFT((x), 12, 0)
305 #define GET_RXD_VLAN_TCI(x)		GET_BITS_SHIFT((x), 16, 0)
306 #define GET_RXD_CFI(x)			GET_BITS_SHIFT((x), 1, 12)
307 #define GET_RXD_PRIO(x)			GET_BITS_SHIFT((x), 3, 13)
308 
309 struct rxd_desc {
310 	u32 rxd_val1;
311 	u16 len;
312 	u16 rxd_vlan;
313 	u32 va_lo;
314 	u32 va_hi;
315 };
316 
317 /* PBL describes each virtual buffer to be */
318 /* transmitted from the host.*/
319 struct pbl {
320 	u32 pa_lo;
321 	u32 pa_hi;
322 	u32 len;
323 };
324 
325 /* First word for TXD descriptor. It means: type = 3 for regular Tx packet,
326  * hw_csum = 7 for ip+udp+tcp hw checksums */
327 #define TXD_W1_VAL(bc, checksum, vtag, lgsnd, vlan_id)	\
328 	((bc) | ((checksum)<<5) | ((vtag)<<8) | \
329 	((lgsnd)<<9) | (0x30000) | ((vlan_id)<<20))
330 
331 struct txd_desc {
332 	u32 txd_val1;
333 	u16 mss;
334 	u16 length;
335 	u32 va_lo;
336 	u32 va_hi;
337 	struct pbl pbl[0];	/* Fragments */
338 } __packed;
339 
340 /* Register region size */
341 #define BDX_REGS_SIZE	  0x1000
342 
343 /* Registers from 0x0000-0x00fc were remapped to 0x4000-0x40fc */
344 #define regTXD_CFG1_0   0x4000
345 #define regRXF_CFG1_0   0x4010
346 #define regRXD_CFG1_0   0x4020
347 #define regTXF_CFG1_0   0x4030
348 #define regTXD_CFG0_0   0x4040
349 #define regRXF_CFG0_0   0x4050
350 #define regRXD_CFG0_0   0x4060
351 #define regTXF_CFG0_0   0x4070
352 #define regTXD_WPTR_0   0x4080
353 #define regRXF_WPTR_0   0x4090
354 #define regRXD_WPTR_0   0x40A0
355 #define regTXF_WPTR_0   0x40B0
356 #define regTXD_RPTR_0   0x40C0
357 #define regRXF_RPTR_0   0x40D0
358 #define regRXD_RPTR_0   0x40E0
359 #define regTXF_RPTR_0   0x40F0
360 #define regTXF_RPTR_3   0x40FC
361 
362 /* hardware versioning */
363 #define  FW_VER         0x5010
364 #define  SROM_VER       0x5020
365 #define  FPGA_VER       0x5030
366 #define  FPGA_SEED      0x5040
367 
368 /* Registers from 0x0100-0x0150 were remapped to 0x5100-0x5150 */
369 #define regISR regISR0
370 #define regISR0          0x5100
371 
372 #define regIMR regIMR0
373 #define regIMR0          0x5110
374 
375 #define regRDINTCM0      0x5120
376 #define regRDINTCM2      0x5128
377 
378 #define regTDINTCM0      0x5130
379 
380 #define regISR_MSK0      0x5140
381 
382 #define regINIT_SEMAPHORE 0x5170
383 #define regINIT_STATUS    0x5180
384 
385 #define regMAC_LNK_STAT  0x0200
386 #define MAC_LINK_STAT    0x4	/* Link state */
387 
388 #define regGMAC_RXF_A   0x1240
389 
390 #define regUNC_MAC0_A   0x1250
391 #define regUNC_MAC1_A   0x1260
392 #define regUNC_MAC2_A   0x1270
393 
394 #define regVLAN_0       0x1800
395 
396 #define regMAX_FRAME_A  0x12C0
397 
398 #define regRX_MAC_MCST0    0x1A80
399 #define regRX_MAC_MCST1    0x1A84
400 #define MAC_MCST_NUM       15
401 #define regRX_MCST_HASH0   0x1A00
402 #define MAC_MCST_HASH_NUM  8
403 
404 #define regVPC                  0x2300
405 #define regVIC                  0x2320
406 #define regVGLB                 0x2340
407 
408 #define regCLKPLL               0x5000
409 
410 /*for 10G only*/
411 #define regREVISION        0x6000
412 #define regSCRATCH         0x6004
413 #define regCTRLST          0x6008
414 #define regMAC_ADDR_0      0x600C
415 #define regMAC_ADDR_1      0x6010
416 #define regFRM_LENGTH      0x6014
417 #define regPAUSE_QUANT     0x6018
418 #define regRX_FIFO_SECTION 0x601C
419 #define regTX_FIFO_SECTION 0x6020
420 #define regRX_FULLNESS     0x6024
421 #define regTX_FULLNESS     0x6028
422 #define regHASHTABLE       0x602C
423 #define regMDIO_ST         0x6030
424 #define regMDIO_CTL        0x6034
425 #define regMDIO_DATA       0x6038
426 #define regMDIO_ADDR       0x603C
427 
428 #define regRST_PORT        0x7000
429 #define regDIS_PORT        0x7010
430 #define regRST_QU          0x7020
431 #define regDIS_QU          0x7030
432 
433 #define regCTRLST_TX_ENA   0x0001
434 #define regCTRLST_RX_ENA   0x0002
435 #define regCTRLST_PRM_ENA  0x0010
436 #define regCTRLST_PAD_ENA  0x0020
437 
438 #define regCTRLST_BASE     (regCTRLST_PAD_ENA|regCTRLST_PRM_ENA)
439 
440 #define regRX_FLT   0x1400
441 
442 /* TXD TXF RXF RXD  CONFIG 0x0000 --- 0x007c*/
443 #define  TX_RX_CFG1_BASE          0xffffffff	/*0-31 */
444 #define  TX_RX_CFG0_BASE          0xfffff000	/*31:12 */
445 #define  TX_RX_CFG0_RSVD          0x0ffc	/*11:2 */
446 #define  TX_RX_CFG0_SIZE          0x0003	/*1:0 */
447 
448 /*  TXD TXF RXF RXD  WRITE 0x0080 --- 0x00BC */
449 #define  TXF_WPTR_WR_PTR        0x7ff8	/*14:3 */
450 
451 /*  TXD TXF RXF RXD  READ  0x00CO --- 0x00FC */
452 #define  TXF_RPTR_RD_PTR        0x7ff8	/*14:3 */
453 
454 #define TXF_WPTR_MASK 0x7ff0	/* last 4 bits are dropped
455 				 * size is rounded to 16 */
456 
457 /*  regISR 0x0100 */
458 /*  regIMR 0x0110 */
459 #define  IMR_INPROG   0x80000000	/*31 */
460 #define  IR_LNKCHG1   0x10000000	/*28 */
461 #define  IR_LNKCHG0   0x08000000	/*27 */
462 #define  IR_GPIO      0x04000000	/*26 */
463 #define  IR_RFRSH     0x02000000	/*25 */
464 #define  IR_RSVD      0x01000000	/*24 */
465 #define  IR_SWI       0x00800000	/*23 */
466 #define  IR_RX_FREE_3 0x00400000	/*22 */
467 #define  IR_RX_FREE_2 0x00200000	/*21 */
468 #define  IR_RX_FREE_1 0x00100000	/*20 */
469 #define  IR_RX_FREE_0 0x00080000	/*19 */
470 #define  IR_TX_FREE_3 0x00040000	/*18 */
471 #define  IR_TX_FREE_2 0x00020000	/*17 */
472 #define  IR_TX_FREE_1 0x00010000	/*16 */
473 #define  IR_TX_FREE_0 0x00008000	/*15 */
474 #define  IR_RX_DESC_3 0x00004000	/*14 */
475 #define  IR_RX_DESC_2 0x00002000	/*13 */
476 #define  IR_RX_DESC_1 0x00001000	/*12 */
477 #define  IR_RX_DESC_0 0x00000800	/*11 */
478 #define  IR_PSE       0x00000400	/*10 */
479 #define  IR_TMR3      0x00000200	/*9 */
480 #define  IR_TMR2      0x00000100	/*8 */
481 #define  IR_TMR1      0x00000080	/*7 */
482 #define  IR_TMR0      0x00000040	/*6 */
483 #define  IR_VNT       0x00000020	/*5 */
484 #define  IR_RxFL      0x00000010	/*4 */
485 #define  IR_SDPERR    0x00000008	/*3 */
486 #define  IR_TR        0x00000004	/*2 */
487 #define  IR_PCIE_LINK 0x00000002	/*1 */
488 #define  IR_PCIE_TOUT 0x00000001	/*0 */
489 
490 #define  IR_EXTRA (IR_RX_FREE_0 | IR_LNKCHG0 | IR_PSE | \
491     IR_TMR0 | IR_PCIE_LINK | IR_PCIE_TOUT)
492 #define  IR_RUN (IR_EXTRA | IR_RX_DESC_0 | IR_TX_FREE_0)
493 #define  IR_ALL 0xfdfffff7
494 
495 #define  IR_LNKCHG0_ofst        27
496 
497 #define  GMAC_RX_FILTER_OSEN  0x1000	/* shared OS enable */
498 #define  GMAC_RX_FILTER_TXFC  0x0400	/* Tx flow control */
499 #define  GMAC_RX_FILTER_RSV0  0x0200	/* reserved */
500 #define  GMAC_RX_FILTER_FDA   0x0100	/* filter out direct address */
501 #define  GMAC_RX_FILTER_AOF   0x0080	/* accept over run */
502 #define  GMAC_RX_FILTER_ACF   0x0040	/* accept control frames */
503 #define  GMAC_RX_FILTER_ARUNT 0x0020	/* accept under run */
504 #define  GMAC_RX_FILTER_ACRC  0x0010	/* accept crc error */
505 #define  GMAC_RX_FILTER_AM    0x0008	/* accept multicast */
506 #define  GMAC_RX_FILTER_AB    0x0004	/* accept broadcast */
507 #define  GMAC_RX_FILTER_PRM   0x0001	/* [0:1] promiscuous mode */
508 
509 #define  MAX_FRAME_AB_VAL       0x3fff	/* 13:0 */
510 
511 #define  CLKPLL_PLLLKD          0x0200	/*9 */
512 #define  CLKPLL_RSTEND          0x0100	/*8 */
513 #define  CLKPLL_SFTRST          0x0001	/*0 */
514 
515 #define  CLKPLL_LKD             (CLKPLL_PLLLKD|CLKPLL_RSTEND)
516 
517 /*
518  * PCI-E Device Control Register (Offset 0x88)
519  * Source: Luxor Data Sheet, 7.1.3.3.3
520  */
521 #define PCI_DEV_CTRL_REG 0x88
522 #define GET_DEV_CTRL_MAXPL(x)           GET_BITS_SHIFT(x, 3, 5)
523 #define GET_DEV_CTRL_MRRS(x)            GET_BITS_SHIFT(x, 3, 12)
524 
525 /*
526  * PCI-E Link Status Register (Offset 0x92)
527  * Source: Luxor Data Sheet, 7.1.3.3.7
528  */
529 #define PCI_LINK_STATUS_REG 0x92
530 #define GET_LINK_STATUS_LANES(x)		GET_BITS_SHIFT(x, 6, 4)
531 
532 /* Debugging Macros */
533 
534 #define DBG2(fmt, args...)					\
535 	pr_err("%s:%-5d: " fmt, __func__, __LINE__, ## args)
536 
537 #define BDX_ASSERT(x) BUG_ON(x)
538 
539 #ifdef DEBUG
540 
541 #define ENTER						\
542 do {							\
543 	pr_err("%s:%-5d: ENTER\n", __func__, __LINE__); \
544 } while (0)
545 
546 #define RET(args...)					 \
547 do {							 \
548 	pr_err("%s:%-5d: RETURN\n", __func__, __LINE__); \
549 	return args;					 \
550 } while (0)
551 
552 #define DBG(fmt, args...)					\
553 	pr_err("%s:%-5d: " fmt, __func__, __LINE__, ## args)
554 #else
555 #define ENTER do {  } while (0)
556 #define RET(args...)   return args
557 #define DBG(fmt, args...)			\
558 do {						\
559 	if (0)					\
560 		pr_err(fmt, ##args);		\
561 } while (0)
562 #endif
563 
564 #endif /* _BDX__H */
565