12874c5fdSThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-or-later */ 2ef7f5429SJeff Kirsher /* 3ef7f5429SJeff Kirsher * Tehuti Networks(R) Network Driver 4ef7f5429SJeff Kirsher * Copyright (C) 2007 Tehuti Networks Ltd. All rights reserved 5ef7f5429SJeff Kirsher */ 6ef7f5429SJeff Kirsher 7ef7f5429SJeff Kirsher #ifndef _TEHUTI_H 8ef7f5429SJeff Kirsher #define _TEHUTI_H 9ef7f5429SJeff Kirsher 10ef7f5429SJeff Kirsher #include <linux/module.h> 11ef7f5429SJeff Kirsher #include <linux/kernel.h> 12ef7f5429SJeff Kirsher #include <linux/netdevice.h> 13ef7f5429SJeff Kirsher #include <linux/etherdevice.h> 14ef7f5429SJeff Kirsher #include <linux/pci.h> 15ef7f5429SJeff Kirsher #include <linux/delay.h> 16ef7f5429SJeff Kirsher #include <linux/ethtool.h> 17ef7f5429SJeff Kirsher #include <linux/mii.h> 18ef7f5429SJeff Kirsher #include <linux/crc32.h> 19ef7f5429SJeff Kirsher #include <linux/uaccess.h> 20ef7f5429SJeff Kirsher #include <linux/in.h> 21ef7f5429SJeff Kirsher #include <linux/ip.h> 22ef7f5429SJeff Kirsher #include <linux/tcp.h> 23ef7f5429SJeff Kirsher #include <linux/sched.h> 24ef7f5429SJeff Kirsher #include <linux/tty.h> 25ef7f5429SJeff Kirsher #include <linux/if_vlan.h> 26ef7f5429SJeff Kirsher #include <linux/interrupt.h> 27ef7f5429SJeff Kirsher #include <linux/vmalloc.h> 28ef7f5429SJeff Kirsher #include <linux/firmware.h> 29ef7f5429SJeff Kirsher #include <asm/byteorder.h> 30ef7f5429SJeff Kirsher #include <linux/dma-mapping.h> 31ef7f5429SJeff Kirsher #include <linux/slab.h> 32ef7f5429SJeff Kirsher 33ef7f5429SJeff Kirsher /* Compile Time Switches */ 34ef7f5429SJeff Kirsher /* start */ 35ef7f5429SJeff Kirsher #define BDX_TSO 36ef7f5429SJeff Kirsher #define BDX_LLTX 37ef7f5429SJeff Kirsher #define BDX_DELAY_WPTR 38ef7f5429SJeff Kirsher /* #define BDX_MSI */ 39ef7f5429SJeff Kirsher /* end */ 40ef7f5429SJeff Kirsher 41ef7f5429SJeff Kirsher #if !defined CONFIG_PCI_MSI 42ef7f5429SJeff Kirsher # undef BDX_MSI 43ef7f5429SJeff Kirsher #endif 44ef7f5429SJeff Kirsher 45ef7f5429SJeff Kirsher #define BDX_DEF_MSG_ENABLE (NETIF_MSG_DRV | \ 46ef7f5429SJeff Kirsher NETIF_MSG_PROBE | \ 47ef7f5429SJeff Kirsher NETIF_MSG_LINK) 48ef7f5429SJeff Kirsher 49ef7f5429SJeff Kirsher /* ioctl ops */ 50ef7f5429SJeff Kirsher #define BDX_OP_READ 1 51ef7f5429SJeff Kirsher #define BDX_OP_WRITE 2 52ef7f5429SJeff Kirsher 53ef7f5429SJeff Kirsher /* RX copy break size */ 54ef7f5429SJeff Kirsher #define BDX_COPYBREAK 257 55ef7f5429SJeff Kirsher 56ef7f5429SJeff Kirsher #define DRIVER_AUTHOR "Tehuti Networks(R)" 57ef7f5429SJeff Kirsher #define BDX_DRV_DESC "Tehuti Networks(R) Network Driver" 58ef7f5429SJeff Kirsher #define BDX_DRV_NAME "tehuti" 59ef7f5429SJeff Kirsher #define BDX_NIC_NAME "Tehuti 10 Giga TOE SmartNIC" 60ef7f5429SJeff Kirsher #define BDX_NIC2PORT_NAME "Tehuti 2-Port 10 Giga TOE SmartNIC" 61ef7f5429SJeff Kirsher #define BDX_DRV_VERSION "7.29.3" 62ef7f5429SJeff Kirsher 63ef7f5429SJeff Kirsher #ifdef BDX_MSI 64ef7f5429SJeff Kirsher # define BDX_MSI_STRING "msi " 65ef7f5429SJeff Kirsher #else 66ef7f5429SJeff Kirsher # define BDX_MSI_STRING "" 67ef7f5429SJeff Kirsher #endif 68ef7f5429SJeff Kirsher 69ef7f5429SJeff Kirsher /* netdev tx queue len for Luxor. default value is, btw, 1000 70ef7f5429SJeff Kirsher * ifcontig eth1 txqueuelen 3000 - to change it at runtime */ 71ef7f5429SJeff Kirsher #define BDX_NDEV_TXQ_LEN 3000 72ef7f5429SJeff Kirsher 7344770e11SJarod Wilson /* Max MTU for Jumbo Frame mode, per tehutinetworks.net Features FAQ is 16k */ 7444770e11SJarod Wilson #define BDX_MAX_MTU (16 * 1024) 7544770e11SJarod Wilson 76ef7f5429SJeff Kirsher #define FIFO_SIZE 4096 77ef7f5429SJeff Kirsher #define FIFO_EXTRA_SPACE 1024 78ef7f5429SJeff Kirsher 79ef7f5429SJeff Kirsher #if BITS_PER_LONG == 64 80ef7f5429SJeff Kirsher # define H32_64(x) (u32) ((u64)(x) >> 32) 81ef7f5429SJeff Kirsher # define L32_64(x) (u32) ((u64)(x) & 0xffffffff) 82ef7f5429SJeff Kirsher #elif BITS_PER_LONG == 32 83ef7f5429SJeff Kirsher # define H32_64(x) 0 84ef7f5429SJeff Kirsher # define L32_64(x) ((u32) (x)) 85ef7f5429SJeff Kirsher #else /* BITS_PER_LONG == ?? */ 86ef7f5429SJeff Kirsher # error BITS_PER_LONG is undefined. Must be 64 or 32 87ef7f5429SJeff Kirsher #endif /* BITS_PER_LONG */ 88ef7f5429SJeff Kirsher 89ef7f5429SJeff Kirsher #ifdef __BIG_ENDIAN 90ef7f5429SJeff Kirsher # define CPU_CHIP_SWAP32(x) swab32(x) 91ef7f5429SJeff Kirsher # define CPU_CHIP_SWAP16(x) swab16(x) 92ef7f5429SJeff Kirsher #else 93ef7f5429SJeff Kirsher # define CPU_CHIP_SWAP32(x) (x) 94ef7f5429SJeff Kirsher # define CPU_CHIP_SWAP16(x) (x) 95ef7f5429SJeff Kirsher #endif 96ef7f5429SJeff Kirsher 97ef7f5429SJeff Kirsher #define READ_REG(pp, reg) readl(pp->pBdxRegs + reg) 98ef7f5429SJeff Kirsher #define WRITE_REG(pp, reg, val) writel(val, pp->pBdxRegs + reg) 99ef7f5429SJeff Kirsher 100ef7f5429SJeff Kirsher #ifndef NET_IP_ALIGN 101ef7f5429SJeff Kirsher # define NET_IP_ALIGN 2 102ef7f5429SJeff Kirsher #endif 103ef7f5429SJeff Kirsher 104ef7f5429SJeff Kirsher #ifndef NETDEV_TX_OK 105ef7f5429SJeff Kirsher # define NETDEV_TX_OK 0 106ef7f5429SJeff Kirsher #endif 107ef7f5429SJeff Kirsher 108ef7f5429SJeff Kirsher #define LUXOR_MAX_PORT 2 109ef7f5429SJeff Kirsher #define BDX_MAX_RX_DONE 150 110ef7f5429SJeff Kirsher #define BDX_TXF_DESC_SZ 16 111ef7f5429SJeff Kirsher #define BDX_MAX_TX_LEVEL (priv->txd_fifo0.m.memsz - 16) 112ef7f5429SJeff Kirsher #define BDX_MIN_TX_LEVEL 256 113ef7f5429SJeff Kirsher #define BDX_NO_UPD_PACKETS 40 114ef7f5429SJeff Kirsher 115ef7f5429SJeff Kirsher struct pci_nic { 116ef7f5429SJeff Kirsher int port_num; 117ef7f5429SJeff Kirsher void __iomem *regs; 118ef7f5429SJeff Kirsher int irq_type; 119ef7f5429SJeff Kirsher struct bdx_priv *priv[LUXOR_MAX_PORT]; 120ef7f5429SJeff Kirsher }; 121ef7f5429SJeff Kirsher 122ef7f5429SJeff Kirsher enum { IRQ_INTX, IRQ_MSI, IRQ_MSIX }; 123ef7f5429SJeff Kirsher 124ef7f5429SJeff Kirsher #define PCK_TH_MULT 128 125ef7f5429SJeff Kirsher #define INT_COAL_MULT 2 126ef7f5429SJeff Kirsher 127ef7f5429SJeff Kirsher #define BITS_MASK(nbits) ((1<<nbits)-1) 128ef7f5429SJeff Kirsher #define GET_BITS_SHIFT(x, nbits, nshift) (((x)>>nshift)&BITS_MASK(nbits)) 129ef7f5429SJeff Kirsher #define BITS_SHIFT_MASK(nbits, nshift) (BITS_MASK(nbits)<<nshift) 130ef7f5429SJeff Kirsher #define BITS_SHIFT_VAL(x, nbits, nshift) (((x)&BITS_MASK(nbits))<<nshift) 131ef7f5429SJeff Kirsher #define BITS_SHIFT_CLEAR(x, nbits, nshift) \ 132ef7f5429SJeff Kirsher ((x)&(~BITS_SHIFT_MASK(nbits, nshift))) 133ef7f5429SJeff Kirsher 134ef7f5429SJeff Kirsher #define GET_INT_COAL(x) GET_BITS_SHIFT(x, 15, 0) 135ef7f5429SJeff Kirsher #define GET_INT_COAL_RC(x) GET_BITS_SHIFT(x, 1, 15) 136ef7f5429SJeff Kirsher #define GET_RXF_TH(x) GET_BITS_SHIFT(x, 4, 16) 137ef7f5429SJeff Kirsher #define GET_PCK_TH(x) GET_BITS_SHIFT(x, 4, 20) 138ef7f5429SJeff Kirsher 139ef7f5429SJeff Kirsher #define INT_REG_VAL(coal, coal_rc, rxf_th, pck_th) \ 140ef7f5429SJeff Kirsher ((coal)|((coal_rc)<<15)|((rxf_th)<<16)|((pck_th)<<20)) 141ef7f5429SJeff Kirsher 142ef7f5429SJeff Kirsher struct fifo { 143ef7f5429SJeff Kirsher dma_addr_t da; /* physical address of fifo (used by HW) */ 144ef7f5429SJeff Kirsher char *va; /* virtual address of fifo (used by SW) */ 145ef7f5429SJeff Kirsher u32 rptr, wptr; /* cached values of RPTR and WPTR registers, 146ef7f5429SJeff Kirsher they're 32 bits on both 32 and 64 archs */ 147ef7f5429SJeff Kirsher u16 reg_CFG0, reg_CFG1; 148ef7f5429SJeff Kirsher u16 reg_RPTR, reg_WPTR; 149ef7f5429SJeff Kirsher u16 memsz; /* memory size allocated for fifo */ 150ef7f5429SJeff Kirsher u16 size_mask; 151ef7f5429SJeff Kirsher u16 pktsz; /* skb packet size to allocate */ 152ef7f5429SJeff Kirsher u16 rcvno; /* number of buffers that come from this RXF */ 153ef7f5429SJeff Kirsher }; 154ef7f5429SJeff Kirsher 155ef7f5429SJeff Kirsher struct txf_fifo { 156ef7f5429SJeff Kirsher struct fifo m; /* minimal set of variables used by all fifos */ 157ef7f5429SJeff Kirsher }; 158ef7f5429SJeff Kirsher 159ef7f5429SJeff Kirsher struct txd_fifo { 160ef7f5429SJeff Kirsher struct fifo m; /* minimal set of variables used by all fifos */ 161ef7f5429SJeff Kirsher }; 162ef7f5429SJeff Kirsher 163ef7f5429SJeff Kirsher struct rxf_fifo { 164ef7f5429SJeff Kirsher struct fifo m; /* minimal set of variables used by all fifos */ 165ef7f5429SJeff Kirsher }; 166ef7f5429SJeff Kirsher 167ef7f5429SJeff Kirsher struct rxd_fifo { 168ef7f5429SJeff Kirsher struct fifo m; /* minimal set of variables used by all fifos */ 169ef7f5429SJeff Kirsher }; 170ef7f5429SJeff Kirsher 171ef7f5429SJeff Kirsher struct rx_map { 172ef7f5429SJeff Kirsher u64 dma; 173ef7f5429SJeff Kirsher struct sk_buff *skb; 174ef7f5429SJeff Kirsher }; 175ef7f5429SJeff Kirsher 176ef7f5429SJeff Kirsher struct rxdb { 177ef7f5429SJeff Kirsher int *stack; 178ef7f5429SJeff Kirsher struct rx_map *elems; 179ef7f5429SJeff Kirsher int nelem; 180ef7f5429SJeff Kirsher int top; 181ef7f5429SJeff Kirsher }; 182ef7f5429SJeff Kirsher 183ef7f5429SJeff Kirsher union bdx_dma_addr { 184ef7f5429SJeff Kirsher dma_addr_t dma; 185ef7f5429SJeff Kirsher struct sk_buff *skb; 186ef7f5429SJeff Kirsher }; 187ef7f5429SJeff Kirsher 188ef7f5429SJeff Kirsher /* Entry in the db. 189ef7f5429SJeff Kirsher * if len == 0 addr is dma 190ef7f5429SJeff Kirsher * if len != 0 addr is skb */ 191ef7f5429SJeff Kirsher struct tx_map { 192ef7f5429SJeff Kirsher union bdx_dma_addr addr; 193ef7f5429SJeff Kirsher int len; 194ef7f5429SJeff Kirsher }; 195ef7f5429SJeff Kirsher 196ef7f5429SJeff Kirsher /* tx database - implemented as circular fifo buffer*/ 197ef7f5429SJeff Kirsher struct txdb { 198ef7f5429SJeff Kirsher struct tx_map *start; /* points to the first element */ 199ef7f5429SJeff Kirsher struct tx_map *end; /* points just AFTER the last element */ 200ef7f5429SJeff Kirsher struct tx_map *rptr; /* points to the next element to read */ 201ef7f5429SJeff Kirsher struct tx_map *wptr; /* points to the next element to write */ 202ef7f5429SJeff Kirsher int size; /* number of elements in the db */ 203ef7f5429SJeff Kirsher }; 204ef7f5429SJeff Kirsher 205ef7f5429SJeff Kirsher /*Internal stats structure*/ 206ef7f5429SJeff Kirsher struct bdx_stats { 207ef7f5429SJeff Kirsher u64 InUCast; /* 0x7200 */ 208ef7f5429SJeff Kirsher u64 InMCast; /* 0x7210 */ 209ef7f5429SJeff Kirsher u64 InBCast; /* 0x7220 */ 210ef7f5429SJeff Kirsher u64 InPkts; /* 0x7230 */ 211ef7f5429SJeff Kirsher u64 InErrors; /* 0x7240 */ 212ef7f5429SJeff Kirsher u64 InDropped; /* 0x7250 */ 213ef7f5429SJeff Kirsher u64 FrameTooLong; /* 0x7260 */ 214ef7f5429SJeff Kirsher u64 FrameSequenceErrors; /* 0x7270 */ 215ef7f5429SJeff Kirsher u64 InVLAN; /* 0x7280 */ 216ef7f5429SJeff Kirsher u64 InDroppedDFE; /* 0x7290 */ 217ef7f5429SJeff Kirsher u64 InDroppedIntFull; /* 0x72A0 */ 218ef7f5429SJeff Kirsher u64 InFrameAlignErrors; /* 0x72B0 */ 219ef7f5429SJeff Kirsher 220ef7f5429SJeff Kirsher /* 0x72C0-0x72E0 RSRV */ 221ef7f5429SJeff Kirsher 222ef7f5429SJeff Kirsher u64 OutUCast; /* 0x72F0 */ 223ef7f5429SJeff Kirsher u64 OutMCast; /* 0x7300 */ 224ef7f5429SJeff Kirsher u64 OutBCast; /* 0x7310 */ 225ef7f5429SJeff Kirsher u64 OutPkts; /* 0x7320 */ 226ef7f5429SJeff Kirsher 227ef7f5429SJeff Kirsher /* 0x7330-0x7360 RSRV */ 228ef7f5429SJeff Kirsher 229ef7f5429SJeff Kirsher u64 OutVLAN; /* 0x7370 */ 230ef7f5429SJeff Kirsher u64 InUCastOctects; /* 0x7380 */ 231ef7f5429SJeff Kirsher u64 OutUCastOctects; /* 0x7390 */ 232ef7f5429SJeff Kirsher 233ef7f5429SJeff Kirsher /* 0x73A0-0x73B0 RSRV */ 234ef7f5429SJeff Kirsher 235ef7f5429SJeff Kirsher u64 InBCastOctects; /* 0x73C0 */ 236ef7f5429SJeff Kirsher u64 OutBCastOctects; /* 0x73D0 */ 237ef7f5429SJeff Kirsher u64 InOctects; /* 0x73E0 */ 238ef7f5429SJeff Kirsher u64 OutOctects; /* 0x73F0 */ 239ef7f5429SJeff Kirsher }; 240ef7f5429SJeff Kirsher 241ef7f5429SJeff Kirsher struct bdx_priv { 242ef7f5429SJeff Kirsher void __iomem *pBdxRegs; 243ef7f5429SJeff Kirsher struct net_device *ndev; 244ef7f5429SJeff Kirsher 245ef7f5429SJeff Kirsher struct napi_struct napi; 246ef7f5429SJeff Kirsher 247ef7f5429SJeff Kirsher /* RX FIFOs: 1 for data (full) descs, and 2 for free descs */ 248ef7f5429SJeff Kirsher struct rxd_fifo rxd_fifo0; 249ef7f5429SJeff Kirsher struct rxf_fifo rxf_fifo0; 250ef7f5429SJeff Kirsher struct rxdb *rxdb; /* rx dbs to store skb pointers */ 251ef7f5429SJeff Kirsher int napi_stop; 252ef7f5429SJeff Kirsher 253ef7f5429SJeff Kirsher /* Tx FIFOs: 1 for data desc, 1 for empty (acks) desc */ 254ef7f5429SJeff Kirsher struct txd_fifo txd_fifo0; 255ef7f5429SJeff Kirsher struct txf_fifo txf_fifo0; 256ef7f5429SJeff Kirsher 257ef7f5429SJeff Kirsher struct txdb txdb; 258ef7f5429SJeff Kirsher int tx_level; 259ef7f5429SJeff Kirsher #ifdef BDX_DELAY_WPTR 260ef7f5429SJeff Kirsher int tx_update_mark; 261ef7f5429SJeff Kirsher int tx_noupd; 262ef7f5429SJeff Kirsher #endif 263ef7f5429SJeff Kirsher spinlock_t tx_lock; /* NETIF_F_LLTX mode */ 264ef7f5429SJeff Kirsher 265ef7f5429SJeff Kirsher /* rarely used */ 266ef7f5429SJeff Kirsher u8 port; 267ef7f5429SJeff Kirsher u32 msg_enable; 268ef7f5429SJeff Kirsher int stats_flag; 269ef7f5429SJeff Kirsher struct bdx_stats hw_stats; 270ef7f5429SJeff Kirsher struct pci_dev *pdev; 271ef7f5429SJeff Kirsher 272ef7f5429SJeff Kirsher struct pci_nic *nic; 273ef7f5429SJeff Kirsher 274ef7f5429SJeff Kirsher u8 txd_size; 275ef7f5429SJeff Kirsher u8 txf_size; 276ef7f5429SJeff Kirsher u8 rxd_size; 277ef7f5429SJeff Kirsher u8 rxf_size; 278ef7f5429SJeff Kirsher u32 rdintcm; 279ef7f5429SJeff Kirsher u32 tdintcm; 280ef7f5429SJeff Kirsher }; 281ef7f5429SJeff Kirsher 282ef7f5429SJeff Kirsher /* RX FREE descriptor - 64bit*/ 283ef7f5429SJeff Kirsher struct rxf_desc { 284ef7f5429SJeff Kirsher u32 info; /* Buffer Count + Info - described below */ 285ef7f5429SJeff Kirsher u32 va_lo; /* VAdr[31:0] */ 286ef7f5429SJeff Kirsher u32 va_hi; /* VAdr[63:32] */ 287ef7f5429SJeff Kirsher u32 pa_lo; /* PAdr[31:0] */ 288ef7f5429SJeff Kirsher u32 pa_hi; /* PAdr[63:32] */ 289ef7f5429SJeff Kirsher u32 len; /* Buffer Length */ 290ef7f5429SJeff Kirsher }; 291ef7f5429SJeff Kirsher 292ef7f5429SJeff Kirsher #define GET_RXD_BC(x) GET_BITS_SHIFT((x), 5, 0) 293ef7f5429SJeff Kirsher #define GET_RXD_RXFQ(x) GET_BITS_SHIFT((x), 2, 8) 294ef7f5429SJeff Kirsher #define GET_RXD_TO(x) GET_BITS_SHIFT((x), 1, 15) 295ef7f5429SJeff Kirsher #define GET_RXD_TYPE(x) GET_BITS_SHIFT((x), 4, 16) 296ef7f5429SJeff Kirsher #define GET_RXD_ERR(x) GET_BITS_SHIFT((x), 6, 21) 297ef7f5429SJeff Kirsher #define GET_RXD_RXP(x) GET_BITS_SHIFT((x), 1, 27) 298ef7f5429SJeff Kirsher #define GET_RXD_PKT_ID(x) GET_BITS_SHIFT((x), 3, 28) 299ef7f5429SJeff Kirsher #define GET_RXD_VTAG(x) GET_BITS_SHIFT((x), 1, 31) 300ef7f5429SJeff Kirsher #define GET_RXD_VLAN_ID(x) GET_BITS_SHIFT((x), 12, 0) 301ef7f5429SJeff Kirsher #define GET_RXD_VLAN_TCI(x) GET_BITS_SHIFT((x), 16, 0) 302ef7f5429SJeff Kirsher #define GET_RXD_CFI(x) GET_BITS_SHIFT((x), 1, 12) 303ef7f5429SJeff Kirsher #define GET_RXD_PRIO(x) GET_BITS_SHIFT((x), 3, 13) 304ef7f5429SJeff Kirsher 305ef7f5429SJeff Kirsher struct rxd_desc { 306ef7f5429SJeff Kirsher u32 rxd_val1; 307ef7f5429SJeff Kirsher u16 len; 308ef7f5429SJeff Kirsher u16 rxd_vlan; 309ef7f5429SJeff Kirsher u32 va_lo; 310ef7f5429SJeff Kirsher u32 va_hi; 311ef7f5429SJeff Kirsher }; 312ef7f5429SJeff Kirsher 313ef7f5429SJeff Kirsher /* PBL describes each virtual buffer to be */ 314ef7f5429SJeff Kirsher /* transmitted from the host.*/ 315ef7f5429SJeff Kirsher struct pbl { 316ef7f5429SJeff Kirsher u32 pa_lo; 317ef7f5429SJeff Kirsher u32 pa_hi; 318ef7f5429SJeff Kirsher u32 len; 319ef7f5429SJeff Kirsher }; 320ef7f5429SJeff Kirsher 321ef7f5429SJeff Kirsher /* First word for TXD descriptor. It means: type = 3 for regular Tx packet, 322ef7f5429SJeff Kirsher * hw_csum = 7 for ip+udp+tcp hw checksums */ 323ef7f5429SJeff Kirsher #define TXD_W1_VAL(bc, checksum, vtag, lgsnd, vlan_id) \ 324ef7f5429SJeff Kirsher ((bc) | ((checksum)<<5) | ((vtag)<<8) | \ 325ef7f5429SJeff Kirsher ((lgsnd)<<9) | (0x30000) | ((vlan_id)<<20)) 326ef7f5429SJeff Kirsher 327ef7f5429SJeff Kirsher struct txd_desc { 328ef7f5429SJeff Kirsher u32 txd_val1; 329ef7f5429SJeff Kirsher u16 mss; 330ef7f5429SJeff Kirsher u16 length; 331ef7f5429SJeff Kirsher u32 va_lo; 332ef7f5429SJeff Kirsher u32 va_hi; 33323640d64SGustavo A. R. Silva struct pbl pbl[]; /* Fragments */ 334ef7f5429SJeff Kirsher } __packed; 335ef7f5429SJeff Kirsher 336ef7f5429SJeff Kirsher /* Register region size */ 337ef7f5429SJeff Kirsher #define BDX_REGS_SIZE 0x1000 338ef7f5429SJeff Kirsher 339ef7f5429SJeff Kirsher /* Registers from 0x0000-0x00fc were remapped to 0x4000-0x40fc */ 340ef7f5429SJeff Kirsher #define regTXD_CFG1_0 0x4000 341ef7f5429SJeff Kirsher #define regRXF_CFG1_0 0x4010 342ef7f5429SJeff Kirsher #define regRXD_CFG1_0 0x4020 343ef7f5429SJeff Kirsher #define regTXF_CFG1_0 0x4030 344ef7f5429SJeff Kirsher #define regTXD_CFG0_0 0x4040 345ef7f5429SJeff Kirsher #define regRXF_CFG0_0 0x4050 346ef7f5429SJeff Kirsher #define regRXD_CFG0_0 0x4060 347ef7f5429SJeff Kirsher #define regTXF_CFG0_0 0x4070 348ef7f5429SJeff Kirsher #define regTXD_WPTR_0 0x4080 349ef7f5429SJeff Kirsher #define regRXF_WPTR_0 0x4090 350ef7f5429SJeff Kirsher #define regRXD_WPTR_0 0x40A0 351ef7f5429SJeff Kirsher #define regTXF_WPTR_0 0x40B0 352ef7f5429SJeff Kirsher #define regTXD_RPTR_0 0x40C0 353ef7f5429SJeff Kirsher #define regRXF_RPTR_0 0x40D0 354ef7f5429SJeff Kirsher #define regRXD_RPTR_0 0x40E0 355ef7f5429SJeff Kirsher #define regTXF_RPTR_0 0x40F0 356ef7f5429SJeff Kirsher #define regTXF_RPTR_3 0x40FC 357ef7f5429SJeff Kirsher 358ef7f5429SJeff Kirsher /* hardware versioning */ 359ef7f5429SJeff Kirsher #define FW_VER 0x5010 360ef7f5429SJeff Kirsher #define SROM_VER 0x5020 361ef7f5429SJeff Kirsher #define FPGA_VER 0x5030 362ef7f5429SJeff Kirsher #define FPGA_SEED 0x5040 363ef7f5429SJeff Kirsher 364ef7f5429SJeff Kirsher /* Registers from 0x0100-0x0150 were remapped to 0x5100-0x5150 */ 365ef7f5429SJeff Kirsher #define regISR regISR0 366ef7f5429SJeff Kirsher #define regISR0 0x5100 367ef7f5429SJeff Kirsher 368ef7f5429SJeff Kirsher #define regIMR regIMR0 369ef7f5429SJeff Kirsher #define regIMR0 0x5110 370ef7f5429SJeff Kirsher 371ef7f5429SJeff Kirsher #define regRDINTCM0 0x5120 372ef7f5429SJeff Kirsher #define regRDINTCM2 0x5128 373ef7f5429SJeff Kirsher 374ef7f5429SJeff Kirsher #define regTDINTCM0 0x5130 375ef7f5429SJeff Kirsher 376ef7f5429SJeff Kirsher #define regISR_MSK0 0x5140 377ef7f5429SJeff Kirsher 378ef7f5429SJeff Kirsher #define regINIT_SEMAPHORE 0x5170 379ef7f5429SJeff Kirsher #define regINIT_STATUS 0x5180 380ef7f5429SJeff Kirsher 381ef7f5429SJeff Kirsher #define regMAC_LNK_STAT 0x0200 382ef7f5429SJeff Kirsher #define MAC_LINK_STAT 0x4 /* Link state */ 383ef7f5429SJeff Kirsher 384ef7f5429SJeff Kirsher #define regGMAC_RXF_A 0x1240 385ef7f5429SJeff Kirsher 386ef7f5429SJeff Kirsher #define regUNC_MAC0_A 0x1250 387ef7f5429SJeff Kirsher #define regUNC_MAC1_A 0x1260 388ef7f5429SJeff Kirsher #define regUNC_MAC2_A 0x1270 389ef7f5429SJeff Kirsher 390ef7f5429SJeff Kirsher #define regVLAN_0 0x1800 391ef7f5429SJeff Kirsher 392ef7f5429SJeff Kirsher #define regMAX_FRAME_A 0x12C0 393ef7f5429SJeff Kirsher 394ef7f5429SJeff Kirsher #define regRX_MAC_MCST0 0x1A80 395ef7f5429SJeff Kirsher #define regRX_MAC_MCST1 0x1A84 396ef7f5429SJeff Kirsher #define MAC_MCST_NUM 15 397ef7f5429SJeff Kirsher #define regRX_MCST_HASH0 0x1A00 398ef7f5429SJeff Kirsher #define MAC_MCST_HASH_NUM 8 399ef7f5429SJeff Kirsher 400ef7f5429SJeff Kirsher #define regVPC 0x2300 401ef7f5429SJeff Kirsher #define regVIC 0x2320 402ef7f5429SJeff Kirsher #define regVGLB 0x2340 403ef7f5429SJeff Kirsher 404ef7f5429SJeff Kirsher #define regCLKPLL 0x5000 405ef7f5429SJeff Kirsher 406ef7f5429SJeff Kirsher /*for 10G only*/ 407ef7f5429SJeff Kirsher #define regREVISION 0x6000 408ef7f5429SJeff Kirsher #define regSCRATCH 0x6004 409ef7f5429SJeff Kirsher #define regCTRLST 0x6008 410ef7f5429SJeff Kirsher #define regMAC_ADDR_0 0x600C 411ef7f5429SJeff Kirsher #define regMAC_ADDR_1 0x6010 412ef7f5429SJeff Kirsher #define regFRM_LENGTH 0x6014 413ef7f5429SJeff Kirsher #define regPAUSE_QUANT 0x6018 414ef7f5429SJeff Kirsher #define regRX_FIFO_SECTION 0x601C 415ef7f5429SJeff Kirsher #define regTX_FIFO_SECTION 0x6020 416ef7f5429SJeff Kirsher #define regRX_FULLNESS 0x6024 417ef7f5429SJeff Kirsher #define regTX_FULLNESS 0x6028 418ef7f5429SJeff Kirsher #define regHASHTABLE 0x602C 419ef7f5429SJeff Kirsher #define regMDIO_ST 0x6030 420ef7f5429SJeff Kirsher #define regMDIO_CTL 0x6034 421ef7f5429SJeff Kirsher #define regMDIO_DATA 0x6038 422ef7f5429SJeff Kirsher #define regMDIO_ADDR 0x603C 423ef7f5429SJeff Kirsher 424ef7f5429SJeff Kirsher #define regRST_PORT 0x7000 425ef7f5429SJeff Kirsher #define regDIS_PORT 0x7010 426ef7f5429SJeff Kirsher #define regRST_QU 0x7020 427ef7f5429SJeff Kirsher #define regDIS_QU 0x7030 428ef7f5429SJeff Kirsher 429ef7f5429SJeff Kirsher #define regCTRLST_TX_ENA 0x0001 430ef7f5429SJeff Kirsher #define regCTRLST_RX_ENA 0x0002 431ef7f5429SJeff Kirsher #define regCTRLST_PRM_ENA 0x0010 432ef7f5429SJeff Kirsher #define regCTRLST_PAD_ENA 0x0020 433ef7f5429SJeff Kirsher 434ef7f5429SJeff Kirsher #define regCTRLST_BASE (regCTRLST_PAD_ENA|regCTRLST_PRM_ENA) 435ef7f5429SJeff Kirsher 436ef7f5429SJeff Kirsher #define regRX_FLT 0x1400 437ef7f5429SJeff Kirsher 438ef7f5429SJeff Kirsher /* TXD TXF RXF RXD CONFIG 0x0000 --- 0x007c*/ 439ef7f5429SJeff Kirsher #define TX_RX_CFG1_BASE 0xffffffff /*0-31 */ 440ef7f5429SJeff Kirsher #define TX_RX_CFG0_BASE 0xfffff000 /*31:12 */ 441ef7f5429SJeff Kirsher #define TX_RX_CFG0_RSVD 0x0ffc /*11:2 */ 442ef7f5429SJeff Kirsher #define TX_RX_CFG0_SIZE 0x0003 /*1:0 */ 443ef7f5429SJeff Kirsher 444ef7f5429SJeff Kirsher /* TXD TXF RXF RXD WRITE 0x0080 --- 0x00BC */ 445ef7f5429SJeff Kirsher #define TXF_WPTR_WR_PTR 0x7ff8 /*14:3 */ 446ef7f5429SJeff Kirsher 447ef7f5429SJeff Kirsher /* TXD TXF RXF RXD READ 0x00CO --- 0x00FC */ 448ef7f5429SJeff Kirsher #define TXF_RPTR_RD_PTR 0x7ff8 /*14:3 */ 449ef7f5429SJeff Kirsher 450ef7f5429SJeff Kirsher #define TXF_WPTR_MASK 0x7ff0 /* last 4 bits are dropped 451ef7f5429SJeff Kirsher * size is rounded to 16 */ 452ef7f5429SJeff Kirsher 453ef7f5429SJeff Kirsher /* regISR 0x0100 */ 454ef7f5429SJeff Kirsher /* regIMR 0x0110 */ 455ef7f5429SJeff Kirsher #define IMR_INPROG 0x80000000 /*31 */ 456ef7f5429SJeff Kirsher #define IR_LNKCHG1 0x10000000 /*28 */ 457ef7f5429SJeff Kirsher #define IR_LNKCHG0 0x08000000 /*27 */ 458ef7f5429SJeff Kirsher #define IR_GPIO 0x04000000 /*26 */ 459ef7f5429SJeff Kirsher #define IR_RFRSH 0x02000000 /*25 */ 460ef7f5429SJeff Kirsher #define IR_RSVD 0x01000000 /*24 */ 461ef7f5429SJeff Kirsher #define IR_SWI 0x00800000 /*23 */ 462ef7f5429SJeff Kirsher #define IR_RX_FREE_3 0x00400000 /*22 */ 463ef7f5429SJeff Kirsher #define IR_RX_FREE_2 0x00200000 /*21 */ 464ef7f5429SJeff Kirsher #define IR_RX_FREE_1 0x00100000 /*20 */ 465ef7f5429SJeff Kirsher #define IR_RX_FREE_0 0x00080000 /*19 */ 466ef7f5429SJeff Kirsher #define IR_TX_FREE_3 0x00040000 /*18 */ 467ef7f5429SJeff Kirsher #define IR_TX_FREE_2 0x00020000 /*17 */ 468ef7f5429SJeff Kirsher #define IR_TX_FREE_1 0x00010000 /*16 */ 469ef7f5429SJeff Kirsher #define IR_TX_FREE_0 0x00008000 /*15 */ 470ef7f5429SJeff Kirsher #define IR_RX_DESC_3 0x00004000 /*14 */ 471ef7f5429SJeff Kirsher #define IR_RX_DESC_2 0x00002000 /*13 */ 472ef7f5429SJeff Kirsher #define IR_RX_DESC_1 0x00001000 /*12 */ 473ef7f5429SJeff Kirsher #define IR_RX_DESC_0 0x00000800 /*11 */ 474ef7f5429SJeff Kirsher #define IR_PSE 0x00000400 /*10 */ 475ef7f5429SJeff Kirsher #define IR_TMR3 0x00000200 /*9 */ 476ef7f5429SJeff Kirsher #define IR_TMR2 0x00000100 /*8 */ 477ef7f5429SJeff Kirsher #define IR_TMR1 0x00000080 /*7 */ 478ef7f5429SJeff Kirsher #define IR_TMR0 0x00000040 /*6 */ 479ef7f5429SJeff Kirsher #define IR_VNT 0x00000020 /*5 */ 480ef7f5429SJeff Kirsher #define IR_RxFL 0x00000010 /*4 */ 481ef7f5429SJeff Kirsher #define IR_SDPERR 0x00000008 /*3 */ 482ef7f5429SJeff Kirsher #define IR_TR 0x00000004 /*2 */ 483ef7f5429SJeff Kirsher #define IR_PCIE_LINK 0x00000002 /*1 */ 484ef7f5429SJeff Kirsher #define IR_PCIE_TOUT 0x00000001 /*0 */ 485ef7f5429SJeff Kirsher 486ef7f5429SJeff Kirsher #define IR_EXTRA (IR_RX_FREE_0 | IR_LNKCHG0 | IR_PSE | \ 487ef7f5429SJeff Kirsher IR_TMR0 | IR_PCIE_LINK | IR_PCIE_TOUT) 488ef7f5429SJeff Kirsher #define IR_RUN (IR_EXTRA | IR_RX_DESC_0 | IR_TX_FREE_0) 489ef7f5429SJeff Kirsher #define IR_ALL 0xfdfffff7 490ef7f5429SJeff Kirsher 491ef7f5429SJeff Kirsher #define IR_LNKCHG0_ofst 27 492ef7f5429SJeff Kirsher 493ef7f5429SJeff Kirsher #define GMAC_RX_FILTER_OSEN 0x1000 /* shared OS enable */ 494ef7f5429SJeff Kirsher #define GMAC_RX_FILTER_TXFC 0x0400 /* Tx flow control */ 495ef7f5429SJeff Kirsher #define GMAC_RX_FILTER_RSV0 0x0200 /* reserved */ 496ef7f5429SJeff Kirsher #define GMAC_RX_FILTER_FDA 0x0100 /* filter out direct address */ 497ef7f5429SJeff Kirsher #define GMAC_RX_FILTER_AOF 0x0080 /* accept over run */ 498ef7f5429SJeff Kirsher #define GMAC_RX_FILTER_ACF 0x0040 /* accept control frames */ 499ef7f5429SJeff Kirsher #define GMAC_RX_FILTER_ARUNT 0x0020 /* accept under run */ 500ef7f5429SJeff Kirsher #define GMAC_RX_FILTER_ACRC 0x0010 /* accept crc error */ 501ef7f5429SJeff Kirsher #define GMAC_RX_FILTER_AM 0x0008 /* accept multicast */ 502ef7f5429SJeff Kirsher #define GMAC_RX_FILTER_AB 0x0004 /* accept broadcast */ 503ef7f5429SJeff Kirsher #define GMAC_RX_FILTER_PRM 0x0001 /* [0:1] promiscuous mode */ 504ef7f5429SJeff Kirsher 505ef7f5429SJeff Kirsher #define MAX_FRAME_AB_VAL 0x3fff /* 13:0 */ 506ef7f5429SJeff Kirsher 507ef7f5429SJeff Kirsher #define CLKPLL_PLLLKD 0x0200 /*9 */ 508ef7f5429SJeff Kirsher #define CLKPLL_RSTEND 0x0100 /*8 */ 509ef7f5429SJeff Kirsher #define CLKPLL_SFTRST 0x0001 /*0 */ 510ef7f5429SJeff Kirsher 511ef7f5429SJeff Kirsher #define CLKPLL_LKD (CLKPLL_PLLLKD|CLKPLL_RSTEND) 512ef7f5429SJeff Kirsher 513ef7f5429SJeff Kirsher /* 514ef7f5429SJeff Kirsher * PCI-E Device Control Register (Offset 0x88) 515ef7f5429SJeff Kirsher * Source: Luxor Data Sheet, 7.1.3.3.3 516ef7f5429SJeff Kirsher */ 517ef7f5429SJeff Kirsher #define PCI_DEV_CTRL_REG 0x88 518ef7f5429SJeff Kirsher #define GET_DEV_CTRL_MAXPL(x) GET_BITS_SHIFT(x, 3, 5) 519ef7f5429SJeff Kirsher #define GET_DEV_CTRL_MRRS(x) GET_BITS_SHIFT(x, 3, 12) 520ef7f5429SJeff Kirsher 521ef7f5429SJeff Kirsher /* 522ef7f5429SJeff Kirsher * PCI-E Link Status Register (Offset 0x92) 523ef7f5429SJeff Kirsher * Source: Luxor Data Sheet, 7.1.3.3.7 524ef7f5429SJeff Kirsher */ 525ef7f5429SJeff Kirsher #define PCI_LINK_STATUS_REG 0x92 526ef7f5429SJeff Kirsher #define GET_LINK_STATUS_LANES(x) GET_BITS_SHIFT(x, 6, 4) 527ef7f5429SJeff Kirsher 528ef7f5429SJeff Kirsher /* Debugging Macros */ 529ef7f5429SJeff Kirsher 530ef7f5429SJeff Kirsher #define DBG2(fmt, args...) \ 531ef7f5429SJeff Kirsher pr_err("%s:%-5d: " fmt, __func__, __LINE__, ## args) 532ef7f5429SJeff Kirsher 533ef7f5429SJeff Kirsher #define BDX_ASSERT(x) BUG_ON(x) 534ef7f5429SJeff Kirsher 535ef7f5429SJeff Kirsher #ifdef DEBUG 536ef7f5429SJeff Kirsher 537ef7f5429SJeff Kirsher #define ENTER \ 538ef7f5429SJeff Kirsher do { \ 539ef7f5429SJeff Kirsher pr_err("%s:%-5d: ENTER\n", __func__, __LINE__); \ 540ef7f5429SJeff Kirsher } while (0) 541ef7f5429SJeff Kirsher 542ef7f5429SJeff Kirsher #define RET(args...) \ 543ef7f5429SJeff Kirsher do { \ 544ef7f5429SJeff Kirsher pr_err("%s:%-5d: RETURN\n", __func__, __LINE__); \ 545ef7f5429SJeff Kirsher return args; \ 546ef7f5429SJeff Kirsher } while (0) 547ef7f5429SJeff Kirsher 548ef7f5429SJeff Kirsher #define DBG(fmt, args...) \ 549ef7f5429SJeff Kirsher pr_err("%s:%-5d: " fmt, __func__, __LINE__, ## args) 550ef7f5429SJeff Kirsher #else 551ef7f5429SJeff Kirsher #define ENTER do { } while (0) 552ef7f5429SJeff Kirsher #define RET(args...) return args 553ef7f5429SJeff Kirsher #define DBG(fmt, args...) \ 554ef7f5429SJeff Kirsher do { \ 555ef7f5429SJeff Kirsher if (0) \ 556ef7f5429SJeff Kirsher pr_err(fmt, ##args); \ 557ef7f5429SJeff Kirsher } while (0) 558ef7f5429SJeff Kirsher #endif 559ef7f5429SJeff Kirsher 560ef7f5429SJeff Kirsher #endif /* _BDX__H */ 561