1 /*
2  * Tehuti Networks(R) Network Driver
3  * ethtool interface implementation
4  * Copyright (C) 2007 Tehuti Networks Ltd. All rights reserved
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License as published by
8  * the Free Software Foundation; either version 2 of the License, or
9  * (at your option) any later version.
10  */
11 
12 /*
13  * RX HW/SW interaction overview
14  * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
15  * There are 2 types of RX communication channels between driver and NIC.
16  * 1) RX Free Fifo - RXF - holds descriptors of empty buffers to accept incoming
17  * traffic. This Fifo is filled by SW and is readen by HW. Each descriptor holds
18  * info about buffer's location, size and ID. An ID field is used to identify a
19  * buffer when it's returned with data via RXD Fifo (see below)
20  * 2) RX Data Fifo - RXD - holds descriptors of full buffers. This Fifo is
21  * filled by HW and is readen by SW. Each descriptor holds status and ID.
22  * HW pops descriptor from RXF Fifo, stores ID, fills buffer with incoming data,
23  * via dma moves it into host memory, builds new RXD descriptor with same ID,
24  * pushes it into RXD Fifo and raises interrupt to indicate new RX data.
25  *
26  * Current NIC configuration (registers + firmware) makes NIC use 2 RXF Fifos.
27  * One holds 1.5K packets and another - 26K packets. Depending on incoming
28  * packet size, HW desides on a RXF Fifo to pop buffer from. When packet is
29  * filled with data, HW builds new RXD descriptor for it and push it into single
30  * RXD Fifo.
31  *
32  * RX SW Data Structures
33  * ~~~~~~~~~~~~~~~~~~~~~
34  * skb db - used to keep track of all skbs owned by SW and their dma addresses.
35  * For RX case, ownership lasts from allocating new empty skb for RXF until
36  * accepting full skb from RXD and passing it to OS. Each RXF Fifo has its own
37  * skb db. Implemented as array with bitmask.
38  * fifo - keeps info about fifo's size and location, relevant HW registers,
39  * usage and skb db. Each RXD and RXF Fifo has its own fifo structure.
40  * Implemented as simple struct.
41  *
42  * RX SW Execution Flow
43  * ~~~~~~~~~~~~~~~~~~~~
44  * Upon initialization (ifconfig up) driver creates RX fifos and initializes
45  * relevant registers. At the end of init phase, driver enables interrupts.
46  * NIC sees that there is no RXF buffers and raises
47  * RD_INTR interrupt, isr fills skbs and Rx begins.
48  * Driver has two receive operation modes:
49  *    NAPI - interrupt-driven mixed with polling
50  *    interrupt-driven only
51  *
52  * Interrupt-driven only flow is following. When buffer is ready, HW raises
53  * interrupt and isr is called. isr collects all available packets
54  * (bdx_rx_receive), refills skbs (bdx_rx_alloc_skbs) and exit.
55 
56  * Rx buffer allocation note
57  * ~~~~~~~~~~~~~~~~~~~~~~~~~
58  * Driver cares to feed such amount of RxF descriptors that respective amount of
59  * RxD descriptors can not fill entire RxD fifo. The main reason is lack of
60  * overflow check in Bordeaux for RxD fifo free/used size.
61  * FIXME: this is NOT fully implemented, more work should be done
62  *
63  */
64 
65 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
66 
67 #include "tehuti.h"
68 
69 static const struct pci_device_id bdx_pci_tbl[] = {
70 	{ PCI_VDEVICE(TEHUTI, 0x3009), },
71 	{ PCI_VDEVICE(TEHUTI, 0x3010), },
72 	{ PCI_VDEVICE(TEHUTI, 0x3014), },
73 	{ 0 }
74 };
75 
76 MODULE_DEVICE_TABLE(pci, bdx_pci_tbl);
77 
78 /* Definitions needed by ISR or NAPI functions */
79 static void bdx_rx_alloc_skbs(struct bdx_priv *priv, struct rxf_fifo *f);
80 static void bdx_tx_cleanup(struct bdx_priv *priv);
81 static int bdx_rx_receive(struct bdx_priv *priv, struct rxd_fifo *f, int budget);
82 
83 /* Definitions needed by FW loading */
84 static void bdx_tx_push_desc_safe(struct bdx_priv *priv, void *data, int size);
85 
86 /* Definitions needed by hw_start */
87 static int bdx_tx_init(struct bdx_priv *priv);
88 static int bdx_rx_init(struct bdx_priv *priv);
89 
90 /* Definitions needed by bdx_close */
91 static void bdx_rx_free(struct bdx_priv *priv);
92 static void bdx_tx_free(struct bdx_priv *priv);
93 
94 /* Definitions needed by bdx_probe */
95 static void bdx_set_ethtool_ops(struct net_device *netdev);
96 
97 /*************************************************************************
98  *    Print Info                                                         *
99  *************************************************************************/
100 
101 static void print_hw_id(struct pci_dev *pdev)
102 {
103 	struct pci_nic *nic = pci_get_drvdata(pdev);
104 	u16 pci_link_status = 0;
105 	u16 pci_ctrl = 0;
106 
107 	pci_read_config_word(pdev, PCI_LINK_STATUS_REG, &pci_link_status);
108 	pci_read_config_word(pdev, PCI_DEV_CTRL_REG, &pci_ctrl);
109 
110 	pr_info("%s%s\n", BDX_NIC_NAME,
111 		nic->port_num == 1 ? "" : ", 2-Port");
112 	pr_info("srom 0x%x fpga %d build %u lane# %d max_pl 0x%x mrrs 0x%x\n",
113 		readl(nic->regs + SROM_VER), readl(nic->regs + FPGA_VER) & 0xFFF,
114 		readl(nic->regs + FPGA_SEED),
115 		GET_LINK_STATUS_LANES(pci_link_status),
116 		GET_DEV_CTRL_MAXPL(pci_ctrl), GET_DEV_CTRL_MRRS(pci_ctrl));
117 }
118 
119 static void print_fw_id(struct pci_nic *nic)
120 {
121 	pr_info("fw 0x%x\n", readl(nic->regs + FW_VER));
122 }
123 
124 static void print_eth_id(struct net_device *ndev)
125 {
126 	netdev_info(ndev, "%s, Port %c\n",
127 		    BDX_NIC_NAME, (ndev->if_port == 0) ? 'A' : 'B');
128 
129 }
130 
131 /*************************************************************************
132  *    Code                                                               *
133  *************************************************************************/
134 
135 #define bdx_enable_interrupts(priv)	\
136 	do { WRITE_REG(priv, regIMR, IR_RUN); } while (0)
137 #define bdx_disable_interrupts(priv)	\
138 	do { WRITE_REG(priv, regIMR, 0); } while (0)
139 
140 /**
141  * bdx_fifo_init - create TX/RX descriptor fifo for host-NIC communication.
142  * @priv: NIC private structure
143  * @f: fifo to initialize
144  * @fsz_type: fifo size type: 0-4KB, 1-8KB, 2-16KB, 3-32KB
145  * @reg_XXX: offsets of registers relative to base address
146  *
147  * 1K extra space is allocated at the end of the fifo to simplify
148  * processing of descriptors that wraps around fifo's end
149  *
150  * Returns 0 on success, negative value on failure
151  *
152  */
153 static int
154 bdx_fifo_init(struct bdx_priv *priv, struct fifo *f, int fsz_type,
155 	      u16 reg_CFG0, u16 reg_CFG1, u16 reg_RPTR, u16 reg_WPTR)
156 {
157 	u16 memsz = FIFO_SIZE * (1 << fsz_type);
158 
159 	memset(f, 0, sizeof(struct fifo));
160 	/* pci_alloc_consistent gives us 4k-aligned memory */
161 	f->va = pci_alloc_consistent(priv->pdev,
162 				     memsz + FIFO_EXTRA_SPACE, &f->da);
163 	if (!f->va) {
164 		pr_err("pci_alloc_consistent failed\n");
165 		RET(-ENOMEM);
166 	}
167 	f->reg_CFG0 = reg_CFG0;
168 	f->reg_CFG1 = reg_CFG1;
169 	f->reg_RPTR = reg_RPTR;
170 	f->reg_WPTR = reg_WPTR;
171 	f->rptr = 0;
172 	f->wptr = 0;
173 	f->memsz = memsz;
174 	f->size_mask = memsz - 1;
175 	WRITE_REG(priv, reg_CFG0, (u32) ((f->da & TX_RX_CFG0_BASE) | fsz_type));
176 	WRITE_REG(priv, reg_CFG1, H32_64(f->da));
177 
178 	RET(0);
179 }
180 
181 /**
182  * bdx_fifo_free - free all resources used by fifo
183  * @priv: NIC private structure
184  * @f: fifo to release
185  */
186 static void bdx_fifo_free(struct bdx_priv *priv, struct fifo *f)
187 {
188 	ENTER;
189 	if (f->va) {
190 		pci_free_consistent(priv->pdev,
191 				    f->memsz + FIFO_EXTRA_SPACE, f->va, f->da);
192 		f->va = NULL;
193 	}
194 	RET();
195 }
196 
197 /**
198  * bdx_link_changed - notifies OS about hw link state.
199  * @priv: hw adapter structure
200  */
201 static void bdx_link_changed(struct bdx_priv *priv)
202 {
203 	u32 link = READ_REG(priv, regMAC_LNK_STAT) & MAC_LINK_STAT;
204 
205 	if (!link) {
206 		if (netif_carrier_ok(priv->ndev)) {
207 			netif_stop_queue(priv->ndev);
208 			netif_carrier_off(priv->ndev);
209 			netdev_err(priv->ndev, "Link Down\n");
210 		}
211 	} else {
212 		if (!netif_carrier_ok(priv->ndev)) {
213 			netif_wake_queue(priv->ndev);
214 			netif_carrier_on(priv->ndev);
215 			netdev_err(priv->ndev, "Link Up\n");
216 		}
217 	}
218 }
219 
220 static void bdx_isr_extra(struct bdx_priv *priv, u32 isr)
221 {
222 	if (isr & IR_RX_FREE_0) {
223 		bdx_rx_alloc_skbs(priv, &priv->rxf_fifo0);
224 		DBG("RX_FREE_0\n");
225 	}
226 
227 	if (isr & IR_LNKCHG0)
228 		bdx_link_changed(priv);
229 
230 	if (isr & IR_PCIE_LINK)
231 		netdev_err(priv->ndev, "PCI-E Link Fault\n");
232 
233 	if (isr & IR_PCIE_TOUT)
234 		netdev_err(priv->ndev, "PCI-E Time Out\n");
235 
236 }
237 
238 /**
239  * bdx_isr_napi - Interrupt Service Routine for Bordeaux NIC
240  * @irq: interrupt number
241  * @dev: network device
242  *
243  * Return IRQ_NONE if it was not our interrupt, IRQ_HANDLED - otherwise
244  *
245  * It reads ISR register to know interrupt reasons, and proceed them one by one.
246  * Reasons of interest are:
247  *    RX_DESC - new packet has arrived and RXD fifo holds its descriptor
248  *    RX_FREE - number of free Rx buffers in RXF fifo gets low
249  *    TX_FREE - packet was transmited and RXF fifo holds its descriptor
250  */
251 
252 static irqreturn_t bdx_isr_napi(int irq, void *dev)
253 {
254 	struct net_device *ndev = dev;
255 	struct bdx_priv *priv = netdev_priv(ndev);
256 	u32 isr;
257 
258 	ENTER;
259 	isr = (READ_REG(priv, regISR) & IR_RUN);
260 	if (unlikely(!isr)) {
261 		bdx_enable_interrupts(priv);
262 		return IRQ_NONE;	/* Not our interrupt */
263 	}
264 
265 	if (isr & IR_EXTRA)
266 		bdx_isr_extra(priv, isr);
267 
268 	if (isr & (IR_RX_DESC_0 | IR_TX_FREE_0)) {
269 		if (likely(napi_schedule_prep(&priv->napi))) {
270 			__napi_schedule(&priv->napi);
271 			RET(IRQ_HANDLED);
272 		} else {
273 			/* NOTE: we get here if intr has slipped into window
274 			 * between these lines in bdx_poll:
275 			 *    bdx_enable_interrupts(priv);
276 			 *    return 0;
277 			 * currently intrs are disabled (since we read ISR),
278 			 * and we have failed to register next poll.
279 			 * so we read the regs to trigger chip
280 			 * and allow further interupts. */
281 			READ_REG(priv, regTXF_WPTR_0);
282 			READ_REG(priv, regRXD_WPTR_0);
283 		}
284 	}
285 
286 	bdx_enable_interrupts(priv);
287 	RET(IRQ_HANDLED);
288 }
289 
290 static int bdx_poll(struct napi_struct *napi, int budget)
291 {
292 	struct bdx_priv *priv = container_of(napi, struct bdx_priv, napi);
293 	int work_done;
294 
295 	ENTER;
296 	bdx_tx_cleanup(priv);
297 	work_done = bdx_rx_receive(priv, &priv->rxd_fifo0, budget);
298 	if ((work_done < budget) ||
299 	    (priv->napi_stop++ >= 30)) {
300 		DBG("rx poll is done. backing to isr-driven\n");
301 
302 		/* from time to time we exit to let NAPI layer release
303 		 * device lock and allow waiting tasks (eg rmmod) to advance) */
304 		priv->napi_stop = 0;
305 
306 		napi_complete(napi);
307 		bdx_enable_interrupts(priv);
308 	}
309 	return work_done;
310 }
311 
312 /**
313  * bdx_fw_load - loads firmware to NIC
314  * @priv: NIC private structure
315  *
316  * Firmware is loaded via TXD fifo, so it must be initialized first.
317  * Firware must be loaded once per NIC not per PCI device provided by NIC (NIC
318  * can have few of them). So all drivers use semaphore register to choose one
319  * that will actually load FW to NIC.
320  */
321 
322 static int bdx_fw_load(struct bdx_priv *priv)
323 {
324 	const struct firmware *fw = NULL;
325 	int master, i;
326 	int rc;
327 
328 	ENTER;
329 	master = READ_REG(priv, regINIT_SEMAPHORE);
330 	if (!READ_REG(priv, regINIT_STATUS) && master) {
331 		rc = request_firmware(&fw, "tehuti/bdx.bin", &priv->pdev->dev);
332 		if (rc)
333 			goto out;
334 		bdx_tx_push_desc_safe(priv, (char *)fw->data, fw->size);
335 		mdelay(100);
336 	}
337 	for (i = 0; i < 200; i++) {
338 		if (READ_REG(priv, regINIT_STATUS)) {
339 			rc = 0;
340 			goto out;
341 		}
342 		mdelay(2);
343 	}
344 	rc = -EIO;
345 out:
346 	if (master)
347 		WRITE_REG(priv, regINIT_SEMAPHORE, 1);
348 
349 	release_firmware(fw);
350 
351 	if (rc) {
352 		netdev_err(priv->ndev, "firmware loading failed\n");
353 		if (rc == -EIO)
354 			DBG("VPC = 0x%x VIC = 0x%x INIT_STATUS = 0x%x i=%d\n",
355 			    READ_REG(priv, regVPC),
356 			    READ_REG(priv, regVIC),
357 			    READ_REG(priv, regINIT_STATUS), i);
358 		RET(rc);
359 	} else {
360 		DBG("%s: firmware loading success\n", priv->ndev->name);
361 		RET(0);
362 	}
363 }
364 
365 static void bdx_restore_mac(struct net_device *ndev, struct bdx_priv *priv)
366 {
367 	u32 val;
368 
369 	ENTER;
370 	DBG("mac0=%x mac1=%x mac2=%x\n",
371 	    READ_REG(priv, regUNC_MAC0_A),
372 	    READ_REG(priv, regUNC_MAC1_A), READ_REG(priv, regUNC_MAC2_A));
373 
374 	val = (ndev->dev_addr[0] << 8) | (ndev->dev_addr[1]);
375 	WRITE_REG(priv, regUNC_MAC2_A, val);
376 	val = (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]);
377 	WRITE_REG(priv, regUNC_MAC1_A, val);
378 	val = (ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]);
379 	WRITE_REG(priv, regUNC_MAC0_A, val);
380 
381 	DBG("mac0=%x mac1=%x mac2=%x\n",
382 	    READ_REG(priv, regUNC_MAC0_A),
383 	    READ_REG(priv, regUNC_MAC1_A), READ_REG(priv, regUNC_MAC2_A));
384 	RET();
385 }
386 
387 /**
388  * bdx_hw_start - inits registers and starts HW's Rx and Tx engines
389  * @priv: NIC private structure
390  */
391 static int bdx_hw_start(struct bdx_priv *priv)
392 {
393 	int rc = -EIO;
394 	struct net_device *ndev = priv->ndev;
395 
396 	ENTER;
397 	bdx_link_changed(priv);
398 
399 	/* 10G overall max length (vlan, eth&ip header, ip payload, crc) */
400 	WRITE_REG(priv, regFRM_LENGTH, 0X3FE0);
401 	WRITE_REG(priv, regPAUSE_QUANT, 0x96);
402 	WRITE_REG(priv, regRX_FIFO_SECTION, 0x800010);
403 	WRITE_REG(priv, regTX_FIFO_SECTION, 0xE00010);
404 	WRITE_REG(priv, regRX_FULLNESS, 0);
405 	WRITE_REG(priv, regTX_FULLNESS, 0);
406 	WRITE_REG(priv, regCTRLST,
407 		  regCTRLST_BASE | regCTRLST_RX_ENA | regCTRLST_TX_ENA);
408 
409 	WRITE_REG(priv, regVGLB, 0);
410 	WRITE_REG(priv, regMAX_FRAME_A,
411 		  priv->rxf_fifo0.m.pktsz & MAX_FRAME_AB_VAL);
412 
413 	DBG("RDINTCM=%08x\n", priv->rdintcm);	/*NOTE: test script uses this */
414 	WRITE_REG(priv, regRDINTCM0, priv->rdintcm);
415 	WRITE_REG(priv, regRDINTCM2, 0);	/*cpu_to_le32(rcm.val)); */
416 
417 	DBG("TDINTCM=%08x\n", priv->tdintcm);	/*NOTE: test script uses this */
418 	WRITE_REG(priv, regTDINTCM0, priv->tdintcm);	/* old val = 0x300064 */
419 
420 	/* Enable timer interrupt once in 2 secs. */
421 	/*WRITE_REG(priv, regGTMR0, ((GTMR_SEC * 2) & GTMR_DATA)); */
422 	bdx_restore_mac(priv->ndev, priv);
423 
424 	WRITE_REG(priv, regGMAC_RXF_A, GMAC_RX_FILTER_OSEN |
425 		  GMAC_RX_FILTER_AM | GMAC_RX_FILTER_AB);
426 
427 #define BDX_IRQ_TYPE	((priv->nic->irq_type == IRQ_MSI) ? 0 : IRQF_SHARED)
428 
429 	rc = request_irq(priv->pdev->irq, bdx_isr_napi, BDX_IRQ_TYPE,
430 			 ndev->name, ndev);
431 	if (rc)
432 		goto err_irq;
433 	bdx_enable_interrupts(priv);
434 
435 	RET(0);
436 
437 err_irq:
438 	RET(rc);
439 }
440 
441 static void bdx_hw_stop(struct bdx_priv *priv)
442 {
443 	ENTER;
444 	bdx_disable_interrupts(priv);
445 	free_irq(priv->pdev->irq, priv->ndev);
446 
447 	netif_carrier_off(priv->ndev);
448 	netif_stop_queue(priv->ndev);
449 
450 	RET();
451 }
452 
453 static int bdx_hw_reset_direct(void __iomem *regs)
454 {
455 	u32 val, i;
456 	ENTER;
457 
458 	/* reset sequences: read, write 1, read, write 0 */
459 	val = readl(regs + regCLKPLL);
460 	writel((val | CLKPLL_SFTRST) + 0x8, regs + regCLKPLL);
461 	udelay(50);
462 	val = readl(regs + regCLKPLL);
463 	writel(val & ~CLKPLL_SFTRST, regs + regCLKPLL);
464 
465 	/* check that the PLLs are locked and reset ended */
466 	for (i = 0; i < 70; i++, mdelay(10))
467 		if ((readl(regs + regCLKPLL) & CLKPLL_LKD) == CLKPLL_LKD) {
468 			/* do any PCI-E read transaction */
469 			readl(regs + regRXD_CFG0_0);
470 			return 0;
471 		}
472 	pr_err("HW reset failed\n");
473 	return 1;		/* failure */
474 }
475 
476 static int bdx_hw_reset(struct bdx_priv *priv)
477 {
478 	u32 val, i;
479 	ENTER;
480 
481 	if (priv->port == 0) {
482 		/* reset sequences: read, write 1, read, write 0 */
483 		val = READ_REG(priv, regCLKPLL);
484 		WRITE_REG(priv, regCLKPLL, (val | CLKPLL_SFTRST) + 0x8);
485 		udelay(50);
486 		val = READ_REG(priv, regCLKPLL);
487 		WRITE_REG(priv, regCLKPLL, val & ~CLKPLL_SFTRST);
488 	}
489 	/* check that the PLLs are locked and reset ended */
490 	for (i = 0; i < 70; i++, mdelay(10))
491 		if ((READ_REG(priv, regCLKPLL) & CLKPLL_LKD) == CLKPLL_LKD) {
492 			/* do any PCI-E read transaction */
493 			READ_REG(priv, regRXD_CFG0_0);
494 			return 0;
495 		}
496 	pr_err("HW reset failed\n");
497 	return 1;		/* failure */
498 }
499 
500 static int bdx_sw_reset(struct bdx_priv *priv)
501 {
502 	int i;
503 
504 	ENTER;
505 	/* 1. load MAC (obsolete) */
506 	/* 2. disable Rx (and Tx) */
507 	WRITE_REG(priv, regGMAC_RXF_A, 0);
508 	mdelay(100);
509 	/* 3. disable port */
510 	WRITE_REG(priv, regDIS_PORT, 1);
511 	/* 4. disable queue */
512 	WRITE_REG(priv, regDIS_QU, 1);
513 	/* 5. wait until hw is disabled */
514 	for (i = 0; i < 50; i++) {
515 		if (READ_REG(priv, regRST_PORT) & 1)
516 			break;
517 		mdelay(10);
518 	}
519 	if (i == 50)
520 		netdev_err(priv->ndev, "SW reset timeout. continuing anyway\n");
521 
522 	/* 6. disable intrs */
523 	WRITE_REG(priv, regRDINTCM0, 0);
524 	WRITE_REG(priv, regTDINTCM0, 0);
525 	WRITE_REG(priv, regIMR, 0);
526 	READ_REG(priv, regISR);
527 
528 	/* 7. reset queue */
529 	WRITE_REG(priv, regRST_QU, 1);
530 	/* 8. reset port */
531 	WRITE_REG(priv, regRST_PORT, 1);
532 	/* 9. zero all read and write pointers */
533 	for (i = regTXD_WPTR_0; i <= regTXF_RPTR_3; i += 0x10)
534 		DBG("%x = %x\n", i, READ_REG(priv, i) & TXF_WPTR_WR_PTR);
535 	for (i = regTXD_WPTR_0; i <= regTXF_RPTR_3; i += 0x10)
536 		WRITE_REG(priv, i, 0);
537 	/* 10. unseet port disable */
538 	WRITE_REG(priv, regDIS_PORT, 0);
539 	/* 11. unset queue disable */
540 	WRITE_REG(priv, regDIS_QU, 0);
541 	/* 12. unset queue reset */
542 	WRITE_REG(priv, regRST_QU, 0);
543 	/* 13. unset port reset */
544 	WRITE_REG(priv, regRST_PORT, 0);
545 	/* 14. enable Rx */
546 	/* skiped. will be done later */
547 	/* 15. save MAC (obsolete) */
548 	for (i = regTXD_WPTR_0; i <= regTXF_RPTR_3; i += 0x10)
549 		DBG("%x = %x\n", i, READ_REG(priv, i) & TXF_WPTR_WR_PTR);
550 
551 	RET(0);
552 }
553 
554 /* bdx_reset - performs right type of reset depending on hw type */
555 static int bdx_reset(struct bdx_priv *priv)
556 {
557 	ENTER;
558 	RET((priv->pdev->device == 0x3009)
559 	    ? bdx_hw_reset(priv)
560 	    : bdx_sw_reset(priv));
561 }
562 
563 /**
564  * bdx_close - Disables a network interface
565  * @netdev: network interface device structure
566  *
567  * Returns 0, this is not allowed to fail
568  *
569  * The close entry point is called when an interface is de-activated
570  * by the OS.  The hardware is still under the drivers control, but
571  * needs to be disabled.  A global MAC reset is issued to stop the
572  * hardware, and all transmit and receive resources are freed.
573  **/
574 static int bdx_close(struct net_device *ndev)
575 {
576 	struct bdx_priv *priv = NULL;
577 
578 	ENTER;
579 	priv = netdev_priv(ndev);
580 
581 	napi_disable(&priv->napi);
582 
583 	bdx_reset(priv);
584 	bdx_hw_stop(priv);
585 	bdx_rx_free(priv);
586 	bdx_tx_free(priv);
587 	RET(0);
588 }
589 
590 /**
591  * bdx_open - Called when a network interface is made active
592  * @netdev: network interface device structure
593  *
594  * Returns 0 on success, negative value on failure
595  *
596  * The open entry point is called when a network interface is made
597  * active by the system (IFF_UP).  At this point all resources needed
598  * for transmit and receive operations are allocated, the interrupt
599  * handler is registered with the OS, the watchdog timer is started,
600  * and the stack is notified that the interface is ready.
601  **/
602 static int bdx_open(struct net_device *ndev)
603 {
604 	struct bdx_priv *priv;
605 	int rc;
606 
607 	ENTER;
608 	priv = netdev_priv(ndev);
609 	bdx_reset(priv);
610 	if (netif_running(ndev))
611 		netif_stop_queue(priv->ndev);
612 
613 	if ((rc = bdx_tx_init(priv)) ||
614 	    (rc = bdx_rx_init(priv)) ||
615 	    (rc = bdx_fw_load(priv)))
616 		goto err;
617 
618 	bdx_rx_alloc_skbs(priv, &priv->rxf_fifo0);
619 
620 	rc = bdx_hw_start(priv);
621 	if (rc)
622 		goto err;
623 
624 	napi_enable(&priv->napi);
625 
626 	print_fw_id(priv->nic);
627 
628 	RET(0);
629 
630 err:
631 	bdx_close(ndev);
632 	RET(rc);
633 }
634 
635 static int bdx_range_check(struct bdx_priv *priv, u32 offset)
636 {
637 	return (offset > (u32) (BDX_REGS_SIZE / priv->nic->port_num)) ?
638 		-EINVAL : 0;
639 }
640 
641 static int bdx_ioctl_priv(struct net_device *ndev, struct ifreq *ifr, int cmd)
642 {
643 	struct bdx_priv *priv = netdev_priv(ndev);
644 	u32 data[3];
645 	int error;
646 
647 	ENTER;
648 
649 	DBG("jiffies=%ld cmd=%d\n", jiffies, cmd);
650 	if (cmd != SIOCDEVPRIVATE) {
651 		error = copy_from_user(data, ifr->ifr_data, sizeof(data));
652 		if (error) {
653 			pr_err("can't copy from user\n");
654 			RET(-EFAULT);
655 		}
656 		DBG("%d 0x%x 0x%x\n", data[0], data[1], data[2]);
657 	}
658 
659 	if (!capable(CAP_SYS_RAWIO))
660 		return -EPERM;
661 
662 	switch (data[0]) {
663 
664 	case BDX_OP_READ:
665 		error = bdx_range_check(priv, data[1]);
666 		if (error < 0)
667 			return error;
668 		data[2] = READ_REG(priv, data[1]);
669 		DBG("read_reg(0x%x)=0x%x (dec %d)\n", data[1], data[2],
670 		    data[2]);
671 		error = copy_to_user(ifr->ifr_data, data, sizeof(data));
672 		if (error)
673 			RET(-EFAULT);
674 		break;
675 
676 	case BDX_OP_WRITE:
677 		error = bdx_range_check(priv, data[1]);
678 		if (error < 0)
679 			return error;
680 		WRITE_REG(priv, data[1], data[2]);
681 		DBG("write_reg(0x%x, 0x%x)\n", data[1], data[2]);
682 		break;
683 
684 	default:
685 		RET(-EOPNOTSUPP);
686 	}
687 	return 0;
688 }
689 
690 static int bdx_ioctl(struct net_device *ndev, struct ifreq *ifr, int cmd)
691 {
692 	ENTER;
693 	if (cmd >= SIOCDEVPRIVATE && cmd <= (SIOCDEVPRIVATE + 15))
694 		RET(bdx_ioctl_priv(ndev, ifr, cmd));
695 	else
696 		RET(-EOPNOTSUPP);
697 }
698 
699 /**
700  * __bdx_vlan_rx_vid - private helper for adding/killing VLAN vid
701  * @ndev: network device
702  * @vid:  VLAN vid
703  * @op:   add or kill operation
704  *
705  * Passes VLAN filter table to hardware
706  */
707 static void __bdx_vlan_rx_vid(struct net_device *ndev, uint16_t vid, int enable)
708 {
709 	struct bdx_priv *priv = netdev_priv(ndev);
710 	u32 reg, bit, val;
711 
712 	ENTER;
713 	DBG2("vid=%d value=%d\n", (int)vid, enable);
714 	if (unlikely(vid >= 4096)) {
715 		pr_err("invalid VID: %u (> 4096)\n", vid);
716 		RET();
717 	}
718 	reg = regVLAN_0 + (vid / 32) * 4;
719 	bit = 1 << vid % 32;
720 	val = READ_REG(priv, reg);
721 	DBG2("reg=%x, val=%x, bit=%d\n", reg, val, bit);
722 	if (enable)
723 		val |= bit;
724 	else
725 		val &= ~bit;
726 	DBG2("new val %x\n", val);
727 	WRITE_REG(priv, reg, val);
728 	RET();
729 }
730 
731 /**
732  * bdx_vlan_rx_add_vid - kernel hook for adding VLAN vid to hw filtering table
733  * @ndev: network device
734  * @vid:  VLAN vid to add
735  */
736 static int bdx_vlan_rx_add_vid(struct net_device *ndev, __be16 proto, u16 vid)
737 {
738 	__bdx_vlan_rx_vid(ndev, vid, 1);
739 	return 0;
740 }
741 
742 /**
743  * bdx_vlan_rx_kill_vid - kernel hook for killing VLAN vid in hw filtering table
744  * @ndev: network device
745  * @vid:  VLAN vid to kill
746  */
747 static int bdx_vlan_rx_kill_vid(struct net_device *ndev, __be16 proto, u16 vid)
748 {
749 	__bdx_vlan_rx_vid(ndev, vid, 0);
750 	return 0;
751 }
752 
753 /**
754  * bdx_change_mtu - Change the Maximum Transfer Unit
755  * @netdev: network interface device structure
756  * @new_mtu: new value for maximum frame size
757  *
758  * Returns 0 on success, negative on failure
759  */
760 static int bdx_change_mtu(struct net_device *ndev, int new_mtu)
761 {
762 	ENTER;
763 
764 	if (new_mtu == ndev->mtu)
765 		RET(0);
766 
767 	/* enforce minimum frame size */
768 	if (new_mtu < ETH_ZLEN) {
769 		netdev_err(ndev, "mtu %d is less then minimal %d\n",
770 			   new_mtu, ETH_ZLEN);
771 		RET(-EINVAL);
772 	}
773 
774 	ndev->mtu = new_mtu;
775 	if (netif_running(ndev)) {
776 		bdx_close(ndev);
777 		bdx_open(ndev);
778 	}
779 	RET(0);
780 }
781 
782 static void bdx_setmulti(struct net_device *ndev)
783 {
784 	struct bdx_priv *priv = netdev_priv(ndev);
785 
786 	u32 rxf_val =
787 	    GMAC_RX_FILTER_AM | GMAC_RX_FILTER_AB | GMAC_RX_FILTER_OSEN;
788 	int i;
789 
790 	ENTER;
791 	/* IMF - imperfect (hash) rx multicat filter */
792 	/* PMF - perfect rx multicat filter */
793 
794 	/* FIXME: RXE(OFF) */
795 	if (ndev->flags & IFF_PROMISC) {
796 		rxf_val |= GMAC_RX_FILTER_PRM;
797 	} else if (ndev->flags & IFF_ALLMULTI) {
798 		/* set IMF to accept all multicast frmaes */
799 		for (i = 0; i < MAC_MCST_HASH_NUM; i++)
800 			WRITE_REG(priv, regRX_MCST_HASH0 + i * 4, ~0);
801 	} else if (!netdev_mc_empty(ndev)) {
802 		u8 hash;
803 		struct netdev_hw_addr *ha;
804 		u32 reg, val;
805 
806 		/* set IMF to deny all multicast frames */
807 		for (i = 0; i < MAC_MCST_HASH_NUM; i++)
808 			WRITE_REG(priv, regRX_MCST_HASH0 + i * 4, 0);
809 		/* set PMF to deny all multicast frames */
810 		for (i = 0; i < MAC_MCST_NUM; i++) {
811 			WRITE_REG(priv, regRX_MAC_MCST0 + i * 8, 0);
812 			WRITE_REG(priv, regRX_MAC_MCST1 + i * 8, 0);
813 		}
814 
815 		/* use PMF to accept first MAC_MCST_NUM (15) addresses */
816 		/* TBD: sort addresses and write them in ascending order
817 		 * into RX_MAC_MCST regs. we skip this phase now and accept ALL
818 		 * multicast frames throu IMF */
819 		/* accept the rest of addresses throu IMF */
820 		netdev_for_each_mc_addr(ha, ndev) {
821 			hash = 0;
822 			for (i = 0; i < ETH_ALEN; i++)
823 				hash ^= ha->addr[i];
824 			reg = regRX_MCST_HASH0 + ((hash >> 5) << 2);
825 			val = READ_REG(priv, reg);
826 			val |= (1 << (hash % 32));
827 			WRITE_REG(priv, reg, val);
828 		}
829 
830 	} else {
831 		DBG("only own mac %d\n", netdev_mc_count(ndev));
832 		rxf_val |= GMAC_RX_FILTER_AB;
833 	}
834 	WRITE_REG(priv, regGMAC_RXF_A, rxf_val);
835 	/* enable RX */
836 	/* FIXME: RXE(ON) */
837 	RET();
838 }
839 
840 static int bdx_set_mac(struct net_device *ndev, void *p)
841 {
842 	struct bdx_priv *priv = netdev_priv(ndev);
843 	struct sockaddr *addr = p;
844 
845 	ENTER;
846 	/*
847 	   if (netif_running(dev))
848 	   return -EBUSY
849 	 */
850 	memcpy(ndev->dev_addr, addr->sa_data, ndev->addr_len);
851 	bdx_restore_mac(ndev, priv);
852 	RET(0);
853 }
854 
855 static int bdx_read_mac(struct bdx_priv *priv)
856 {
857 	u16 macAddress[3], i;
858 	ENTER;
859 
860 	macAddress[2] = READ_REG(priv, regUNC_MAC0_A);
861 	macAddress[2] = READ_REG(priv, regUNC_MAC0_A);
862 	macAddress[1] = READ_REG(priv, regUNC_MAC1_A);
863 	macAddress[1] = READ_REG(priv, regUNC_MAC1_A);
864 	macAddress[0] = READ_REG(priv, regUNC_MAC2_A);
865 	macAddress[0] = READ_REG(priv, regUNC_MAC2_A);
866 	for (i = 0; i < 3; i++) {
867 		priv->ndev->dev_addr[i * 2 + 1] = macAddress[i];
868 		priv->ndev->dev_addr[i * 2] = macAddress[i] >> 8;
869 	}
870 	RET(0);
871 }
872 
873 static u64 bdx_read_l2stat(struct bdx_priv *priv, int reg)
874 {
875 	u64 val;
876 
877 	val = READ_REG(priv, reg);
878 	val |= ((u64) READ_REG(priv, reg + 8)) << 32;
879 	return val;
880 }
881 
882 /*Do the statistics-update work*/
883 static void bdx_update_stats(struct bdx_priv *priv)
884 {
885 	struct bdx_stats *stats = &priv->hw_stats;
886 	u64 *stats_vector = (u64 *) stats;
887 	int i;
888 	int addr;
889 
890 	/*Fill HW structure */
891 	addr = 0x7200;
892 	/*First 12 statistics - 0x7200 - 0x72B0 */
893 	for (i = 0; i < 12; i++) {
894 		stats_vector[i] = bdx_read_l2stat(priv, addr);
895 		addr += 0x10;
896 	}
897 	BDX_ASSERT(addr != 0x72C0);
898 	/* 0x72C0-0x72E0 RSRV */
899 	addr = 0x72F0;
900 	for (; i < 16; i++) {
901 		stats_vector[i] = bdx_read_l2stat(priv, addr);
902 		addr += 0x10;
903 	}
904 	BDX_ASSERT(addr != 0x7330);
905 	/* 0x7330-0x7360 RSRV */
906 	addr = 0x7370;
907 	for (; i < 19; i++) {
908 		stats_vector[i] = bdx_read_l2stat(priv, addr);
909 		addr += 0x10;
910 	}
911 	BDX_ASSERT(addr != 0x73A0);
912 	/* 0x73A0-0x73B0 RSRV */
913 	addr = 0x73C0;
914 	for (; i < 23; i++) {
915 		stats_vector[i] = bdx_read_l2stat(priv, addr);
916 		addr += 0x10;
917 	}
918 	BDX_ASSERT(addr != 0x7400);
919 	BDX_ASSERT((sizeof(struct bdx_stats) / sizeof(u64)) != i);
920 }
921 
922 static void print_rxdd(struct rxd_desc *rxdd, u32 rxd_val1, u16 len,
923 		       u16 rxd_vlan);
924 static void print_rxfd(struct rxf_desc *rxfd);
925 
926 /*************************************************************************
927  *     Rx DB                                                             *
928  *************************************************************************/
929 
930 static void bdx_rxdb_destroy(struct rxdb *db)
931 {
932 	vfree(db);
933 }
934 
935 static struct rxdb *bdx_rxdb_create(int nelem)
936 {
937 	struct rxdb *db;
938 	int i;
939 
940 	db = vmalloc(sizeof(struct rxdb)
941 		     + (nelem * sizeof(int))
942 		     + (nelem * sizeof(struct rx_map)));
943 	if (likely(db != NULL)) {
944 		db->stack = (int *)(db + 1);
945 		db->elems = (void *)(db->stack + nelem);
946 		db->nelem = nelem;
947 		db->top = nelem;
948 		for (i = 0; i < nelem; i++)
949 			db->stack[i] = nelem - i - 1;	/* to make first allocs
950 							   close to db struct*/
951 	}
952 
953 	return db;
954 }
955 
956 static inline int bdx_rxdb_alloc_elem(struct rxdb *db)
957 {
958 	BDX_ASSERT(db->top <= 0);
959 	return db->stack[--(db->top)];
960 }
961 
962 static inline void *bdx_rxdb_addr_elem(struct rxdb *db, int n)
963 {
964 	BDX_ASSERT((n < 0) || (n >= db->nelem));
965 	return db->elems + n;
966 }
967 
968 static inline int bdx_rxdb_available(struct rxdb *db)
969 {
970 	return db->top;
971 }
972 
973 static inline void bdx_rxdb_free_elem(struct rxdb *db, int n)
974 {
975 	BDX_ASSERT((n >= db->nelem) || (n < 0));
976 	db->stack[(db->top)++] = n;
977 }
978 
979 /*************************************************************************
980  *     Rx Init                                                           *
981  *************************************************************************/
982 
983 /**
984  * bdx_rx_init - initialize RX all related HW and SW resources
985  * @priv: NIC private structure
986  *
987  * Returns 0 on success, negative value on failure
988  *
989  * It creates rxf and rxd fifos, update relevant HW registers, preallocate
990  * skb for rx. It assumes that Rx is desabled in HW
991  * funcs are grouped for better cache usage
992  *
993  * RxD fifo is smaller than RxF fifo by design. Upon high load, RxD will be
994  * filled and packets will be dropped by nic without getting into host or
995  * cousing interrupt. Anyway, in that condition, host has no chance to process
996  * all packets, but dropping in nic is cheaper, since it takes 0 cpu cycles
997  */
998 
999 /* TBD: ensure proper packet size */
1000 
1001 static int bdx_rx_init(struct bdx_priv *priv)
1002 {
1003 	ENTER;
1004 
1005 	if (bdx_fifo_init(priv, &priv->rxd_fifo0.m, priv->rxd_size,
1006 			  regRXD_CFG0_0, regRXD_CFG1_0,
1007 			  regRXD_RPTR_0, regRXD_WPTR_0))
1008 		goto err_mem;
1009 	if (bdx_fifo_init(priv, &priv->rxf_fifo0.m, priv->rxf_size,
1010 			  regRXF_CFG0_0, regRXF_CFG1_0,
1011 			  regRXF_RPTR_0, regRXF_WPTR_0))
1012 		goto err_mem;
1013 	priv->rxdb = bdx_rxdb_create(priv->rxf_fifo0.m.memsz /
1014 				     sizeof(struct rxf_desc));
1015 	if (!priv->rxdb)
1016 		goto err_mem;
1017 
1018 	priv->rxf_fifo0.m.pktsz = priv->ndev->mtu + VLAN_ETH_HLEN;
1019 	return 0;
1020 
1021 err_mem:
1022 	netdev_err(priv->ndev, "Rx init failed\n");
1023 	return -ENOMEM;
1024 }
1025 
1026 /**
1027  * bdx_rx_free_skbs - frees and unmaps all skbs allocated for the fifo
1028  * @priv: NIC private structure
1029  * @f: RXF fifo
1030  */
1031 static void bdx_rx_free_skbs(struct bdx_priv *priv, struct rxf_fifo *f)
1032 {
1033 	struct rx_map *dm;
1034 	struct rxdb *db = priv->rxdb;
1035 	u16 i;
1036 
1037 	ENTER;
1038 	DBG("total=%d free=%d busy=%d\n", db->nelem, bdx_rxdb_available(db),
1039 	    db->nelem - bdx_rxdb_available(db));
1040 	while (bdx_rxdb_available(db) > 0) {
1041 		i = bdx_rxdb_alloc_elem(db);
1042 		dm = bdx_rxdb_addr_elem(db, i);
1043 		dm->dma = 0;
1044 	}
1045 	for (i = 0; i < db->nelem; i++) {
1046 		dm = bdx_rxdb_addr_elem(db, i);
1047 		if (dm->dma) {
1048 			pci_unmap_single(priv->pdev,
1049 					 dm->dma, f->m.pktsz,
1050 					 PCI_DMA_FROMDEVICE);
1051 			dev_kfree_skb(dm->skb);
1052 		}
1053 	}
1054 }
1055 
1056 /**
1057  * bdx_rx_free - release all Rx resources
1058  * @priv: NIC private structure
1059  *
1060  * It assumes that Rx is desabled in HW
1061  */
1062 static void bdx_rx_free(struct bdx_priv *priv)
1063 {
1064 	ENTER;
1065 	if (priv->rxdb) {
1066 		bdx_rx_free_skbs(priv, &priv->rxf_fifo0);
1067 		bdx_rxdb_destroy(priv->rxdb);
1068 		priv->rxdb = NULL;
1069 	}
1070 	bdx_fifo_free(priv, &priv->rxf_fifo0.m);
1071 	bdx_fifo_free(priv, &priv->rxd_fifo0.m);
1072 
1073 	RET();
1074 }
1075 
1076 /*************************************************************************
1077  *     Rx Engine                                                         *
1078  *************************************************************************/
1079 
1080 /**
1081  * bdx_rx_alloc_skbs - fill rxf fifo with new skbs
1082  * @priv: nic's private structure
1083  * @f: RXF fifo that needs skbs
1084  *
1085  * It allocates skbs, build rxf descs and push it (rxf descr) into rxf fifo.
1086  * skb's virtual and physical addresses are stored in skb db.
1087  * To calculate free space, func uses cached values of RPTR and WPTR
1088  * When needed, it also updates RPTR and WPTR.
1089  */
1090 
1091 /* TBD: do not update WPTR if no desc were written */
1092 
1093 static void bdx_rx_alloc_skbs(struct bdx_priv *priv, struct rxf_fifo *f)
1094 {
1095 	struct sk_buff *skb;
1096 	struct rxf_desc *rxfd;
1097 	struct rx_map *dm;
1098 	int dno, delta, idx;
1099 	struct rxdb *db = priv->rxdb;
1100 
1101 	ENTER;
1102 	dno = bdx_rxdb_available(db) - 1;
1103 	while (dno > 0) {
1104 		skb = netdev_alloc_skb(priv->ndev, f->m.pktsz + NET_IP_ALIGN);
1105 		if (!skb)
1106 			break;
1107 
1108 		skb_reserve(skb, NET_IP_ALIGN);
1109 
1110 		idx = bdx_rxdb_alloc_elem(db);
1111 		dm = bdx_rxdb_addr_elem(db, idx);
1112 		dm->dma = pci_map_single(priv->pdev,
1113 					 skb->data, f->m.pktsz,
1114 					 PCI_DMA_FROMDEVICE);
1115 		dm->skb = skb;
1116 		rxfd = (struct rxf_desc *)(f->m.va + f->m.wptr);
1117 		rxfd->info = CPU_CHIP_SWAP32(0x10003);	/* INFO=1 BC=3 */
1118 		rxfd->va_lo = idx;
1119 		rxfd->pa_lo = CPU_CHIP_SWAP32(L32_64(dm->dma));
1120 		rxfd->pa_hi = CPU_CHIP_SWAP32(H32_64(dm->dma));
1121 		rxfd->len = CPU_CHIP_SWAP32(f->m.pktsz);
1122 		print_rxfd(rxfd);
1123 
1124 		f->m.wptr += sizeof(struct rxf_desc);
1125 		delta = f->m.wptr - f->m.memsz;
1126 		if (unlikely(delta >= 0)) {
1127 			f->m.wptr = delta;
1128 			if (delta > 0) {
1129 				memcpy(f->m.va, f->m.va + f->m.memsz, delta);
1130 				DBG("wrapped descriptor\n");
1131 			}
1132 		}
1133 		dno--;
1134 	}
1135 	/*TBD: to do - delayed rxf wptr like in txd */
1136 	WRITE_REG(priv, f->m.reg_WPTR, f->m.wptr & TXF_WPTR_WR_PTR);
1137 	RET();
1138 }
1139 
1140 static inline void
1141 NETIF_RX_MUX(struct bdx_priv *priv, u32 rxd_val1, u16 rxd_vlan,
1142 	     struct sk_buff *skb)
1143 {
1144 	ENTER;
1145 	DBG("rxdd->flags.bits.vtag=%d\n", GET_RXD_VTAG(rxd_val1));
1146 	if (GET_RXD_VTAG(rxd_val1)) {
1147 		DBG("%s: vlan rcv vlan '%x' vtag '%x'\n",
1148 		    priv->ndev->name,
1149 		    GET_RXD_VLAN_ID(rxd_vlan),
1150 		    GET_RXD_VTAG(rxd_val1));
1151 		__vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), GET_RXD_VLAN_TCI(rxd_vlan));
1152 	}
1153 	netif_receive_skb(skb);
1154 }
1155 
1156 static void bdx_recycle_skb(struct bdx_priv *priv, struct rxd_desc *rxdd)
1157 {
1158 	struct rxf_desc *rxfd;
1159 	struct rx_map *dm;
1160 	struct rxf_fifo *f;
1161 	struct rxdb *db;
1162 	struct sk_buff *skb;
1163 	int delta;
1164 
1165 	ENTER;
1166 	DBG("priv=%p rxdd=%p\n", priv, rxdd);
1167 	f = &priv->rxf_fifo0;
1168 	db = priv->rxdb;
1169 	DBG("db=%p f=%p\n", db, f);
1170 	dm = bdx_rxdb_addr_elem(db, rxdd->va_lo);
1171 	DBG("dm=%p\n", dm);
1172 	skb = dm->skb;
1173 	rxfd = (struct rxf_desc *)(f->m.va + f->m.wptr);
1174 	rxfd->info = CPU_CHIP_SWAP32(0x10003);	/* INFO=1 BC=3 */
1175 	rxfd->va_lo = rxdd->va_lo;
1176 	rxfd->pa_lo = CPU_CHIP_SWAP32(L32_64(dm->dma));
1177 	rxfd->pa_hi = CPU_CHIP_SWAP32(H32_64(dm->dma));
1178 	rxfd->len = CPU_CHIP_SWAP32(f->m.pktsz);
1179 	print_rxfd(rxfd);
1180 
1181 	f->m.wptr += sizeof(struct rxf_desc);
1182 	delta = f->m.wptr - f->m.memsz;
1183 	if (unlikely(delta >= 0)) {
1184 		f->m.wptr = delta;
1185 		if (delta > 0) {
1186 			memcpy(f->m.va, f->m.va + f->m.memsz, delta);
1187 			DBG("wrapped descriptor\n");
1188 		}
1189 	}
1190 	RET();
1191 }
1192 
1193 /**
1194  * bdx_rx_receive - receives full packets from RXD fifo and pass them to OS
1195  * NOTE: a special treatment is given to non-continuous descriptors
1196  * that start near the end, wraps around and continue at the beginning. a second
1197  * part is copied right after the first, and then descriptor is interpreted as
1198  * normal. fifo has an extra space to allow such operations
1199  * @priv: nic's private structure
1200  * @f: RXF fifo that needs skbs
1201  * @budget: maximum number of packets to receive
1202  */
1203 
1204 /* TBD: replace memcpy func call by explicite inline asm */
1205 
1206 static int bdx_rx_receive(struct bdx_priv *priv, struct rxd_fifo *f, int budget)
1207 {
1208 	struct net_device *ndev = priv->ndev;
1209 	struct sk_buff *skb, *skb2;
1210 	struct rxd_desc *rxdd;
1211 	struct rx_map *dm;
1212 	struct rxf_fifo *rxf_fifo;
1213 	int tmp_len, size;
1214 	int done = 0;
1215 	int max_done = BDX_MAX_RX_DONE;
1216 	struct rxdb *db = NULL;
1217 	/* Unmarshalled descriptor - copy of descriptor in host order */
1218 	u32 rxd_val1;
1219 	u16 len;
1220 	u16 rxd_vlan;
1221 
1222 	ENTER;
1223 	max_done = budget;
1224 
1225 	f->m.wptr = READ_REG(priv, f->m.reg_WPTR) & TXF_WPTR_WR_PTR;
1226 
1227 	size = f->m.wptr - f->m.rptr;
1228 	if (size < 0)
1229 		size = f->m.memsz + size;	/* size is negative :-) */
1230 
1231 	while (size > 0) {
1232 
1233 		rxdd = (struct rxd_desc *)(f->m.va + f->m.rptr);
1234 		rxd_val1 = CPU_CHIP_SWAP32(rxdd->rxd_val1);
1235 
1236 		len = CPU_CHIP_SWAP16(rxdd->len);
1237 
1238 		rxd_vlan = CPU_CHIP_SWAP16(rxdd->rxd_vlan);
1239 
1240 		print_rxdd(rxdd, rxd_val1, len, rxd_vlan);
1241 
1242 		tmp_len = GET_RXD_BC(rxd_val1) << 3;
1243 		BDX_ASSERT(tmp_len <= 0);
1244 		size -= tmp_len;
1245 		if (size < 0)	/* test for partially arrived descriptor */
1246 			break;
1247 
1248 		f->m.rptr += tmp_len;
1249 
1250 		tmp_len = f->m.rptr - f->m.memsz;
1251 		if (unlikely(tmp_len >= 0)) {
1252 			f->m.rptr = tmp_len;
1253 			if (tmp_len > 0) {
1254 				DBG("wrapped desc rptr=%d tmp_len=%d\n",
1255 				    f->m.rptr, tmp_len);
1256 				memcpy(f->m.va + f->m.memsz, f->m.va, tmp_len);
1257 			}
1258 		}
1259 
1260 		if (unlikely(GET_RXD_ERR(rxd_val1))) {
1261 			DBG("rxd_err = 0x%x\n", GET_RXD_ERR(rxd_val1));
1262 			ndev->stats.rx_errors++;
1263 			bdx_recycle_skb(priv, rxdd);
1264 			continue;
1265 		}
1266 
1267 		rxf_fifo = &priv->rxf_fifo0;
1268 		db = priv->rxdb;
1269 		dm = bdx_rxdb_addr_elem(db, rxdd->va_lo);
1270 		skb = dm->skb;
1271 
1272 		if (len < BDX_COPYBREAK &&
1273 		    (skb2 = netdev_alloc_skb(priv->ndev, len + NET_IP_ALIGN))) {
1274 			skb_reserve(skb2, NET_IP_ALIGN);
1275 			/*skb_put(skb2, len); */
1276 			pci_dma_sync_single_for_cpu(priv->pdev,
1277 						    dm->dma, rxf_fifo->m.pktsz,
1278 						    PCI_DMA_FROMDEVICE);
1279 			memcpy(skb2->data, skb->data, len);
1280 			bdx_recycle_skb(priv, rxdd);
1281 			skb = skb2;
1282 		} else {
1283 			pci_unmap_single(priv->pdev,
1284 					 dm->dma, rxf_fifo->m.pktsz,
1285 					 PCI_DMA_FROMDEVICE);
1286 			bdx_rxdb_free_elem(db, rxdd->va_lo);
1287 		}
1288 
1289 		ndev->stats.rx_bytes += len;
1290 
1291 		skb_put(skb, len);
1292 		skb->protocol = eth_type_trans(skb, ndev);
1293 
1294 		/* Non-IP packets aren't checksum-offloaded */
1295 		if (GET_RXD_PKT_ID(rxd_val1) == 0)
1296 			skb_checksum_none_assert(skb);
1297 		else
1298 			skb->ip_summed = CHECKSUM_UNNECESSARY;
1299 
1300 		NETIF_RX_MUX(priv, rxd_val1, rxd_vlan, skb);
1301 
1302 		if (++done >= max_done)
1303 			break;
1304 	}
1305 
1306 	ndev->stats.rx_packets += done;
1307 
1308 	/* FIXME: do smth to minimize pci accesses    */
1309 	WRITE_REG(priv, f->m.reg_RPTR, f->m.rptr & TXF_WPTR_WR_PTR);
1310 
1311 	bdx_rx_alloc_skbs(priv, &priv->rxf_fifo0);
1312 
1313 	RET(done);
1314 }
1315 
1316 /*************************************************************************
1317  * Debug / Temprorary Code                                               *
1318  *************************************************************************/
1319 static void print_rxdd(struct rxd_desc *rxdd, u32 rxd_val1, u16 len,
1320 		       u16 rxd_vlan)
1321 {
1322 	DBG("ERROR: rxdd bc %d rxfq %d to %d type %d err %d rxp %d pkt_id %d vtag %d len %d vlan_id %d cfi %d prio %d va_lo %d va_hi %d\n",
1323 	    GET_RXD_BC(rxd_val1), GET_RXD_RXFQ(rxd_val1), GET_RXD_TO(rxd_val1),
1324 	    GET_RXD_TYPE(rxd_val1), GET_RXD_ERR(rxd_val1),
1325 	    GET_RXD_RXP(rxd_val1), GET_RXD_PKT_ID(rxd_val1),
1326 	    GET_RXD_VTAG(rxd_val1), len, GET_RXD_VLAN_ID(rxd_vlan),
1327 	    GET_RXD_CFI(rxd_vlan), GET_RXD_PRIO(rxd_vlan), rxdd->va_lo,
1328 	    rxdd->va_hi);
1329 }
1330 
1331 static void print_rxfd(struct rxf_desc *rxfd)
1332 {
1333 	DBG("=== RxF desc CHIP ORDER/ENDIANNESS =============\n"
1334 	    "info 0x%x va_lo %u pa_lo 0x%x pa_hi 0x%x len 0x%x\n",
1335 	    rxfd->info, rxfd->va_lo, rxfd->pa_lo, rxfd->pa_hi, rxfd->len);
1336 }
1337 
1338 /*
1339  * TX HW/SW interaction overview
1340  * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1341  * There are 2 types of TX communication channels between driver and NIC.
1342  * 1) TX Free Fifo - TXF - holds ack descriptors for sent packets
1343  * 2) TX Data Fifo - TXD - holds descriptors of full buffers.
1344  *
1345  * Currently NIC supports TSO, checksuming and gather DMA
1346  * UFO and IP fragmentation is on the way
1347  *
1348  * RX SW Data Structures
1349  * ~~~~~~~~~~~~~~~~~~~~~
1350  * txdb - used to keep track of all skbs owned by SW and their dma addresses.
1351  * For TX case, ownership lasts from geting packet via hard_xmit and until HW
1352  * acknowledges sent by TXF descriptors.
1353  * Implemented as cyclic buffer.
1354  * fifo - keeps info about fifo's size and location, relevant HW registers,
1355  * usage and skb db. Each RXD and RXF Fifo has its own fifo structure.
1356  * Implemented as simple struct.
1357  *
1358  * TX SW Execution Flow
1359  * ~~~~~~~~~~~~~~~~~~~~
1360  * OS calls driver's hard_xmit method with packet to sent.
1361  * Driver creates DMA mappings, builds TXD descriptors and kicks HW
1362  * by updating TXD WPTR.
1363  * When packet is sent, HW write us TXF descriptor and SW frees original skb.
1364  * To prevent TXD fifo overflow without reading HW registers every time,
1365  * SW deploys "tx level" technique.
1366  * Upon strart up, tx level is initialized to TXD fifo length.
1367  * For every sent packet, SW gets its TXD descriptor sizei
1368  * (from precalculated array) and substructs it from tx level.
1369  * The size is also stored in txdb. When TXF ack arrives, SW fetch size of
1370  * original TXD descriptor from txdb and adds it to tx level.
1371  * When Tx level drops under some predefined treshhold, the driver
1372  * stops the TX queue. When TX level rises above that level,
1373  * the tx queue is enabled again.
1374  *
1375  * This technique avoids eccessive reading of RPTR and WPTR registers.
1376  * As our benchmarks shows, it adds 1.5 Gbit/sec to NIS's throuput.
1377  */
1378 
1379 /*************************************************************************
1380  *     Tx DB                                                             *
1381  *************************************************************************/
1382 static inline int bdx_tx_db_size(struct txdb *db)
1383 {
1384 	int taken = db->wptr - db->rptr;
1385 	if (taken < 0)
1386 		taken = db->size + 1 + taken;	/* (size + 1) equals memsz */
1387 
1388 	return db->size - taken;
1389 }
1390 
1391 /**
1392  * __bdx_tx_db_ptr_next - helper function, increment read/write pointer + wrap
1393  * @db: tx data base
1394  * @pptr: read or write pointer
1395  */
1396 static inline void __bdx_tx_db_ptr_next(struct txdb *db, struct tx_map **pptr)
1397 {
1398 	BDX_ASSERT(db == NULL || pptr == NULL);	/* sanity */
1399 
1400 	BDX_ASSERT(*pptr != db->rptr &&	/* expect either read */
1401 		   *pptr != db->wptr);	/* or write pointer */
1402 
1403 	BDX_ASSERT(*pptr < db->start ||	/* pointer has to be */
1404 		   *pptr >= db->end);	/* in range */
1405 
1406 	++*pptr;
1407 	if (unlikely(*pptr == db->end))
1408 		*pptr = db->start;
1409 }
1410 
1411 /**
1412  * bdx_tx_db_inc_rptr - increment read pointer
1413  * @db: tx data base
1414  */
1415 static inline void bdx_tx_db_inc_rptr(struct txdb *db)
1416 {
1417 	BDX_ASSERT(db->rptr == db->wptr);	/* can't read from empty db */
1418 	__bdx_tx_db_ptr_next(db, &db->rptr);
1419 }
1420 
1421 /**
1422  * bdx_tx_db_inc_wptr - increment write pointer
1423  * @db: tx data base
1424  */
1425 static inline void bdx_tx_db_inc_wptr(struct txdb *db)
1426 {
1427 	__bdx_tx_db_ptr_next(db, &db->wptr);
1428 	BDX_ASSERT(db->rptr == db->wptr);	/* we can not get empty db as
1429 						   a result of write */
1430 }
1431 
1432 /**
1433  * bdx_tx_db_init - creates and initializes tx db
1434  * @d: tx data base
1435  * @sz_type: size of tx fifo
1436  *
1437  * Returns 0 on success, error code otherwise
1438  */
1439 static int bdx_tx_db_init(struct txdb *d, int sz_type)
1440 {
1441 	int memsz = FIFO_SIZE * (1 << (sz_type + 1));
1442 
1443 	d->start = vmalloc(memsz);
1444 	if (!d->start)
1445 		return -ENOMEM;
1446 
1447 	/*
1448 	 * In order to differentiate between db is empty and db is full
1449 	 * states at least one element should always be empty in order to
1450 	 * avoid rptr == wptr which means db is empty
1451 	 */
1452 	d->size = memsz / sizeof(struct tx_map) - 1;
1453 	d->end = d->start + d->size + 1;	/* just after last element */
1454 
1455 	/* all dbs are created equally empty */
1456 	d->rptr = d->start;
1457 	d->wptr = d->start;
1458 
1459 	return 0;
1460 }
1461 
1462 /**
1463  * bdx_tx_db_close - closes tx db and frees all memory
1464  * @d: tx data base
1465  */
1466 static void bdx_tx_db_close(struct txdb *d)
1467 {
1468 	BDX_ASSERT(d == NULL);
1469 
1470 	vfree(d->start);
1471 	d->start = NULL;
1472 }
1473 
1474 /*************************************************************************
1475  *     Tx Engine                                                         *
1476  *************************************************************************/
1477 
1478 /* sizes of tx desc (including padding if needed) as function
1479  * of skb's frag number */
1480 static struct {
1481 	u16 bytes;
1482 	u16 qwords;		/* qword = 64 bit */
1483 } txd_sizes[MAX_SKB_FRAGS + 1];
1484 
1485 /**
1486  * bdx_tx_map_skb - creates and stores dma mappings for skb's data blocks
1487  * @priv: NIC private structure
1488  * @skb: socket buffer to map
1489  * @txdd: TX descriptor to use
1490  *
1491  * It makes dma mappings for skb's data blocks and writes them to PBL of
1492  * new tx descriptor. It also stores them in the tx db, so they could be
1493  * unmaped after data was sent. It is reponsibility of a caller to make
1494  * sure that there is enough space in the tx db. Last element holds pointer
1495  * to skb itself and marked with zero length
1496  */
1497 static inline void
1498 bdx_tx_map_skb(struct bdx_priv *priv, struct sk_buff *skb,
1499 	       struct txd_desc *txdd)
1500 {
1501 	struct txdb *db = &priv->txdb;
1502 	struct pbl *pbl = &txdd->pbl[0];
1503 	int nr_frags = skb_shinfo(skb)->nr_frags;
1504 	int i;
1505 
1506 	db->wptr->len = skb_headlen(skb);
1507 	db->wptr->addr.dma = pci_map_single(priv->pdev, skb->data,
1508 					    db->wptr->len, PCI_DMA_TODEVICE);
1509 	pbl->len = CPU_CHIP_SWAP32(db->wptr->len);
1510 	pbl->pa_lo = CPU_CHIP_SWAP32(L32_64(db->wptr->addr.dma));
1511 	pbl->pa_hi = CPU_CHIP_SWAP32(H32_64(db->wptr->addr.dma));
1512 	DBG("=== pbl   len: 0x%x ================\n", pbl->len);
1513 	DBG("=== pbl pa_lo: 0x%x ================\n", pbl->pa_lo);
1514 	DBG("=== pbl pa_hi: 0x%x ================\n", pbl->pa_hi);
1515 	bdx_tx_db_inc_wptr(db);
1516 
1517 	for (i = 0; i < nr_frags; i++) {
1518 		const struct skb_frag_struct *frag;
1519 
1520 		frag = &skb_shinfo(skb)->frags[i];
1521 		db->wptr->len = skb_frag_size(frag);
1522 		db->wptr->addr.dma = skb_frag_dma_map(&priv->pdev->dev, frag,
1523 						      0, skb_frag_size(frag),
1524 						      DMA_TO_DEVICE);
1525 
1526 		pbl++;
1527 		pbl->len = CPU_CHIP_SWAP32(db->wptr->len);
1528 		pbl->pa_lo = CPU_CHIP_SWAP32(L32_64(db->wptr->addr.dma));
1529 		pbl->pa_hi = CPU_CHIP_SWAP32(H32_64(db->wptr->addr.dma));
1530 		bdx_tx_db_inc_wptr(db);
1531 	}
1532 
1533 	/* add skb clean up info. */
1534 	db->wptr->len = -txd_sizes[nr_frags].bytes;
1535 	db->wptr->addr.skb = skb;
1536 	bdx_tx_db_inc_wptr(db);
1537 }
1538 
1539 /* init_txd_sizes - precalculate sizes of descriptors for skbs up to 16 frags
1540  * number of frags is used as index to fetch correct descriptors size,
1541  * instead of calculating it each time */
1542 static void __init init_txd_sizes(void)
1543 {
1544 	int i, lwords;
1545 
1546 	/* 7 - is number of lwords in txd with one phys buffer
1547 	 * 3 - is number of lwords used for every additional phys buffer */
1548 	for (i = 0; i < MAX_SKB_FRAGS + 1; i++) {
1549 		lwords = 7 + (i * 3);
1550 		if (lwords & 1)
1551 			lwords++;	/* pad it with 1 lword */
1552 		txd_sizes[i].qwords = lwords >> 1;
1553 		txd_sizes[i].bytes = lwords << 2;
1554 	}
1555 }
1556 
1557 /* bdx_tx_init - initialize all Tx related stuff.
1558  * Namely, TXD and TXF fifos, database etc */
1559 static int bdx_tx_init(struct bdx_priv *priv)
1560 {
1561 	if (bdx_fifo_init(priv, &priv->txd_fifo0.m, priv->txd_size,
1562 			  regTXD_CFG0_0,
1563 			  regTXD_CFG1_0, regTXD_RPTR_0, regTXD_WPTR_0))
1564 		goto err_mem;
1565 	if (bdx_fifo_init(priv, &priv->txf_fifo0.m, priv->txf_size,
1566 			  regTXF_CFG0_0,
1567 			  regTXF_CFG1_0, regTXF_RPTR_0, regTXF_WPTR_0))
1568 		goto err_mem;
1569 
1570 	/* The TX db has to keep mappings for all packets sent (on TxD)
1571 	 * and not yet reclaimed (on TxF) */
1572 	if (bdx_tx_db_init(&priv->txdb, max(priv->txd_size, priv->txf_size)))
1573 		goto err_mem;
1574 
1575 	priv->tx_level = BDX_MAX_TX_LEVEL;
1576 #ifdef BDX_DELAY_WPTR
1577 	priv->tx_update_mark = priv->tx_level - 1024;
1578 #endif
1579 	return 0;
1580 
1581 err_mem:
1582 	netdev_err(priv->ndev, "Tx init failed\n");
1583 	return -ENOMEM;
1584 }
1585 
1586 /**
1587  * bdx_tx_space - calculates available space in TX fifo
1588  * @priv: NIC private structure
1589  *
1590  * Returns available space in TX fifo in bytes
1591  */
1592 static inline int bdx_tx_space(struct bdx_priv *priv)
1593 {
1594 	struct txd_fifo *f = &priv->txd_fifo0;
1595 	int fsize;
1596 
1597 	f->m.rptr = READ_REG(priv, f->m.reg_RPTR) & TXF_WPTR_WR_PTR;
1598 	fsize = f->m.rptr - f->m.wptr;
1599 	if (fsize <= 0)
1600 		fsize = f->m.memsz + fsize;
1601 	return fsize;
1602 }
1603 
1604 /**
1605  * bdx_tx_transmit - send packet to NIC
1606  * @skb: packet to send
1607  * @ndev: network device assigned to NIC
1608  * Return codes:
1609  * o NETDEV_TX_OK everything ok.
1610  * o NETDEV_TX_BUSY Cannot transmit packet, try later
1611  *   Usually a bug, means queue start/stop flow control is broken in
1612  *   the driver. Note: the driver must NOT put the skb in its DMA ring.
1613  * o NETDEV_TX_LOCKED Locking failed, please retry quickly.
1614  */
1615 static netdev_tx_t bdx_tx_transmit(struct sk_buff *skb,
1616 				   struct net_device *ndev)
1617 {
1618 	struct bdx_priv *priv = netdev_priv(ndev);
1619 	struct txd_fifo *f = &priv->txd_fifo0;
1620 	int txd_checksum = 7;	/* full checksum */
1621 	int txd_lgsnd = 0;
1622 	int txd_vlan_id = 0;
1623 	int txd_vtag = 0;
1624 	int txd_mss = 0;
1625 
1626 	int nr_frags = skb_shinfo(skb)->nr_frags;
1627 	struct txd_desc *txdd;
1628 	int len;
1629 	unsigned long flags;
1630 
1631 	ENTER;
1632 	local_irq_save(flags);
1633 	if (!spin_trylock(&priv->tx_lock)) {
1634 		local_irq_restore(flags);
1635 		DBG("%s[%s]: TX locked, returning NETDEV_TX_LOCKED\n",
1636 		    BDX_DRV_NAME, ndev->name);
1637 		return NETDEV_TX_LOCKED;
1638 	}
1639 
1640 	/* build tx descriptor */
1641 	BDX_ASSERT(f->m.wptr >= f->m.memsz);	/* started with valid wptr */
1642 	txdd = (struct txd_desc *)(f->m.va + f->m.wptr);
1643 	if (unlikely(skb->ip_summed != CHECKSUM_PARTIAL))
1644 		txd_checksum = 0;
1645 
1646 	if (skb_shinfo(skb)->gso_size) {
1647 		txd_mss = skb_shinfo(skb)->gso_size;
1648 		txd_lgsnd = 1;
1649 		DBG("skb %p skb len %d gso size = %d\n", skb, skb->len,
1650 		    txd_mss);
1651 	}
1652 
1653 	if (skb_vlan_tag_present(skb)) {
1654 		/*Cut VLAN ID to 12 bits */
1655 		txd_vlan_id = skb_vlan_tag_get(skb) & BITS_MASK(12);
1656 		txd_vtag = 1;
1657 	}
1658 
1659 	txdd->length = CPU_CHIP_SWAP16(skb->len);
1660 	txdd->mss = CPU_CHIP_SWAP16(txd_mss);
1661 	txdd->txd_val1 =
1662 	    CPU_CHIP_SWAP32(TXD_W1_VAL
1663 			    (txd_sizes[nr_frags].qwords, txd_checksum, txd_vtag,
1664 			     txd_lgsnd, txd_vlan_id));
1665 	DBG("=== TxD desc =====================\n");
1666 	DBG("=== w1: 0x%x ================\n", txdd->txd_val1);
1667 	DBG("=== w2: mss 0x%x len 0x%x\n", txdd->mss, txdd->length);
1668 
1669 	bdx_tx_map_skb(priv, skb, txdd);
1670 
1671 	/* increment TXD write pointer. In case of
1672 	   fifo wrapping copy reminder of the descriptor
1673 	   to the beginning */
1674 	f->m.wptr += txd_sizes[nr_frags].bytes;
1675 	len = f->m.wptr - f->m.memsz;
1676 	if (unlikely(len >= 0)) {
1677 		f->m.wptr = len;
1678 		if (len > 0) {
1679 			BDX_ASSERT(len > f->m.memsz);
1680 			memcpy(f->m.va, f->m.va + f->m.memsz, len);
1681 		}
1682 	}
1683 	BDX_ASSERT(f->m.wptr >= f->m.memsz);	/* finished with valid wptr */
1684 
1685 	priv->tx_level -= txd_sizes[nr_frags].bytes;
1686 	BDX_ASSERT(priv->tx_level <= 0 || priv->tx_level > BDX_MAX_TX_LEVEL);
1687 #ifdef BDX_DELAY_WPTR
1688 	if (priv->tx_level > priv->tx_update_mark) {
1689 		/* Force memory writes to complete before letting h/w
1690 		   know there are new descriptors to fetch.
1691 		   (might be needed on platforms like IA64)
1692 		   wmb(); */
1693 		WRITE_REG(priv, f->m.reg_WPTR, f->m.wptr & TXF_WPTR_WR_PTR);
1694 	} else {
1695 		if (priv->tx_noupd++ > BDX_NO_UPD_PACKETS) {
1696 			priv->tx_noupd = 0;
1697 			WRITE_REG(priv, f->m.reg_WPTR,
1698 				  f->m.wptr & TXF_WPTR_WR_PTR);
1699 		}
1700 	}
1701 #else
1702 	/* Force memory writes to complete before letting h/w
1703 	   know there are new descriptors to fetch.
1704 	   (might be needed on platforms like IA64)
1705 	   wmb(); */
1706 	WRITE_REG(priv, f->m.reg_WPTR, f->m.wptr & TXF_WPTR_WR_PTR);
1707 
1708 #endif
1709 #ifdef BDX_LLTX
1710 	ndev->trans_start = jiffies; /* NETIF_F_LLTX driver :( */
1711 #endif
1712 	ndev->stats.tx_packets++;
1713 	ndev->stats.tx_bytes += skb->len;
1714 
1715 	if (priv->tx_level < BDX_MIN_TX_LEVEL) {
1716 		DBG("%s: %s: TX Q STOP level %d\n",
1717 		    BDX_DRV_NAME, ndev->name, priv->tx_level);
1718 		netif_stop_queue(ndev);
1719 	}
1720 
1721 	spin_unlock_irqrestore(&priv->tx_lock, flags);
1722 	return NETDEV_TX_OK;
1723 }
1724 
1725 /**
1726  * bdx_tx_cleanup - clean TXF fifo, run in the context of IRQ.
1727  * @priv: bdx adapter
1728  *
1729  * It scans TXF fifo for descriptors, frees DMA mappings and reports to OS
1730  * that those packets were sent
1731  */
1732 static void bdx_tx_cleanup(struct bdx_priv *priv)
1733 {
1734 	struct txf_fifo *f = &priv->txf_fifo0;
1735 	struct txdb *db = &priv->txdb;
1736 	int tx_level = 0;
1737 
1738 	ENTER;
1739 	f->m.wptr = READ_REG(priv, f->m.reg_WPTR) & TXF_WPTR_MASK;
1740 	BDX_ASSERT(f->m.rptr >= f->m.memsz);	/* started with valid rptr */
1741 
1742 	while (f->m.wptr != f->m.rptr) {
1743 		f->m.rptr += BDX_TXF_DESC_SZ;
1744 		f->m.rptr &= f->m.size_mask;
1745 
1746 		/* unmap all the fragments */
1747 		/* first has to come tx_maps containing dma */
1748 		BDX_ASSERT(db->rptr->len == 0);
1749 		do {
1750 			BDX_ASSERT(db->rptr->addr.dma == 0);
1751 			pci_unmap_page(priv->pdev, db->rptr->addr.dma,
1752 				       db->rptr->len, PCI_DMA_TODEVICE);
1753 			bdx_tx_db_inc_rptr(db);
1754 		} while (db->rptr->len > 0);
1755 		tx_level -= db->rptr->len;	/* '-' koz len is negative */
1756 
1757 		/* now should come skb pointer - free it */
1758 		dev_kfree_skb_irq(db->rptr->addr.skb);
1759 		bdx_tx_db_inc_rptr(db);
1760 	}
1761 
1762 	/* let h/w know which TXF descriptors were cleaned */
1763 	BDX_ASSERT((f->m.wptr & TXF_WPTR_WR_PTR) >= f->m.memsz);
1764 	WRITE_REG(priv, f->m.reg_RPTR, f->m.rptr & TXF_WPTR_WR_PTR);
1765 
1766 	/* We reclaimed resources, so in case the Q is stopped by xmit callback,
1767 	 * we resume the transmission and use tx_lock to synchronize with xmit.*/
1768 	spin_lock(&priv->tx_lock);
1769 	priv->tx_level += tx_level;
1770 	BDX_ASSERT(priv->tx_level <= 0 || priv->tx_level > BDX_MAX_TX_LEVEL);
1771 #ifdef BDX_DELAY_WPTR
1772 	if (priv->tx_noupd) {
1773 		priv->tx_noupd = 0;
1774 		WRITE_REG(priv, priv->txd_fifo0.m.reg_WPTR,
1775 			  priv->txd_fifo0.m.wptr & TXF_WPTR_WR_PTR);
1776 	}
1777 #endif
1778 
1779 	if (unlikely(netif_queue_stopped(priv->ndev) &&
1780 		     netif_carrier_ok(priv->ndev) &&
1781 		     (priv->tx_level >= BDX_MIN_TX_LEVEL))) {
1782 		DBG("%s: %s: TX Q WAKE level %d\n",
1783 		    BDX_DRV_NAME, priv->ndev->name, priv->tx_level);
1784 		netif_wake_queue(priv->ndev);
1785 	}
1786 	spin_unlock(&priv->tx_lock);
1787 }
1788 
1789 /**
1790  * bdx_tx_free_skbs - frees all skbs from TXD fifo.
1791  * It gets called when OS stops this dev, eg upon "ifconfig down" or rmmod
1792  */
1793 static void bdx_tx_free_skbs(struct bdx_priv *priv)
1794 {
1795 	struct txdb *db = &priv->txdb;
1796 
1797 	ENTER;
1798 	while (db->rptr != db->wptr) {
1799 		if (likely(db->rptr->len))
1800 			pci_unmap_page(priv->pdev, db->rptr->addr.dma,
1801 				       db->rptr->len, PCI_DMA_TODEVICE);
1802 		else
1803 			dev_kfree_skb(db->rptr->addr.skb);
1804 		bdx_tx_db_inc_rptr(db);
1805 	}
1806 	RET();
1807 }
1808 
1809 /* bdx_tx_free - frees all Tx resources */
1810 static void bdx_tx_free(struct bdx_priv *priv)
1811 {
1812 	ENTER;
1813 	bdx_tx_free_skbs(priv);
1814 	bdx_fifo_free(priv, &priv->txd_fifo0.m);
1815 	bdx_fifo_free(priv, &priv->txf_fifo0.m);
1816 	bdx_tx_db_close(&priv->txdb);
1817 }
1818 
1819 /**
1820  * bdx_tx_push_desc - push descriptor to TxD fifo
1821  * @priv: NIC private structure
1822  * @data: desc's data
1823  * @size: desc's size
1824  *
1825  * Pushes desc to TxD fifo and overlaps it if needed.
1826  * NOTE: this func does not check for available space. this is responsibility
1827  *    of the caller. Neither does it check that data size is smaller than
1828  *    fifo size.
1829  */
1830 static void bdx_tx_push_desc(struct bdx_priv *priv, void *data, int size)
1831 {
1832 	struct txd_fifo *f = &priv->txd_fifo0;
1833 	int i = f->m.memsz - f->m.wptr;
1834 
1835 	if (size == 0)
1836 		return;
1837 
1838 	if (i > size) {
1839 		memcpy(f->m.va + f->m.wptr, data, size);
1840 		f->m.wptr += size;
1841 	} else {
1842 		memcpy(f->m.va + f->m.wptr, data, i);
1843 		f->m.wptr = size - i;
1844 		memcpy(f->m.va, data + i, f->m.wptr);
1845 	}
1846 	WRITE_REG(priv, f->m.reg_WPTR, f->m.wptr & TXF_WPTR_WR_PTR);
1847 }
1848 
1849 /**
1850  * bdx_tx_push_desc_safe - push descriptor to TxD fifo in a safe way
1851  * @priv: NIC private structure
1852  * @data: desc's data
1853  * @size: desc's size
1854  *
1855  * NOTE: this func does check for available space and, if necessary, waits for
1856  *   NIC to read existing data before writing new one.
1857  */
1858 static void bdx_tx_push_desc_safe(struct bdx_priv *priv, void *data, int size)
1859 {
1860 	int timer = 0;
1861 	ENTER;
1862 
1863 	while (size > 0) {
1864 		/* we substruct 8 because when fifo is full rptr == wptr
1865 		   which also means that fifo is empty, we can understand
1866 		   the difference, but could hw do the same ??? :) */
1867 		int avail = bdx_tx_space(priv) - 8;
1868 		if (avail <= 0) {
1869 			if (timer++ > 300) {	/* prevent endless loop */
1870 				DBG("timeout while writing desc to TxD fifo\n");
1871 				break;
1872 			}
1873 			udelay(50);	/* give hw a chance to clean fifo */
1874 			continue;
1875 		}
1876 		avail = min(avail, size);
1877 		DBG("about to push  %d bytes starting %p size %d\n", avail,
1878 		    data, size);
1879 		bdx_tx_push_desc(priv, data, avail);
1880 		size -= avail;
1881 		data += avail;
1882 	}
1883 	RET();
1884 }
1885 
1886 static const struct net_device_ops bdx_netdev_ops = {
1887 	.ndo_open		= bdx_open,
1888 	.ndo_stop		= bdx_close,
1889 	.ndo_start_xmit		= bdx_tx_transmit,
1890 	.ndo_validate_addr	= eth_validate_addr,
1891 	.ndo_do_ioctl		= bdx_ioctl,
1892 	.ndo_set_rx_mode	= bdx_setmulti,
1893 	.ndo_change_mtu		= bdx_change_mtu,
1894 	.ndo_set_mac_address	= bdx_set_mac,
1895 	.ndo_vlan_rx_add_vid	= bdx_vlan_rx_add_vid,
1896 	.ndo_vlan_rx_kill_vid	= bdx_vlan_rx_kill_vid,
1897 };
1898 
1899 /**
1900  * bdx_probe - Device Initialization Routine
1901  * @pdev: PCI device information struct
1902  * @ent: entry in bdx_pci_tbl
1903  *
1904  * Returns 0 on success, negative on failure
1905  *
1906  * bdx_probe initializes an adapter identified by a pci_dev structure.
1907  * The OS initialization, configuring of the adapter private structure,
1908  * and a hardware reset occur.
1909  *
1910  * functions and their order used as explained in
1911  * /usr/src/linux/Documentation/DMA-{API,mapping}.txt
1912  *
1913  */
1914 
1915 /* TBD: netif_msg should be checked and implemented. I disable it for now */
1916 static int
1917 bdx_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
1918 {
1919 	struct net_device *ndev;
1920 	struct bdx_priv *priv;
1921 	int err, pci_using_dac, port;
1922 	unsigned long pciaddr;
1923 	u32 regionSize;
1924 	struct pci_nic *nic;
1925 
1926 	ENTER;
1927 
1928 	nic = vmalloc(sizeof(*nic));
1929 	if (!nic)
1930 		RET(-ENOMEM);
1931 
1932     /************** pci *****************/
1933 	err = pci_enable_device(pdev);
1934 	if (err)			/* it triggers interrupt, dunno why. */
1935 		goto err_pci;		/* it's not a problem though */
1936 
1937 	if (!(err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) &&
1938 	    !(err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)))) {
1939 		pci_using_dac = 1;
1940 	} else {
1941 		if ((err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) ||
1942 		    (err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)))) {
1943 			pr_err("No usable DMA configuration, aborting\n");
1944 			goto err_dma;
1945 		}
1946 		pci_using_dac = 0;
1947 	}
1948 
1949 	err = pci_request_regions(pdev, BDX_DRV_NAME);
1950 	if (err)
1951 		goto err_dma;
1952 
1953 	pci_set_master(pdev);
1954 
1955 	pciaddr = pci_resource_start(pdev, 0);
1956 	if (!pciaddr) {
1957 		err = -EIO;
1958 		pr_err("no MMIO resource\n");
1959 		goto err_out_res;
1960 	}
1961 	regionSize = pci_resource_len(pdev, 0);
1962 	if (regionSize < BDX_REGS_SIZE) {
1963 		err = -EIO;
1964 		pr_err("MMIO resource (%x) too small\n", regionSize);
1965 		goto err_out_res;
1966 	}
1967 
1968 	nic->regs = ioremap(pciaddr, regionSize);
1969 	if (!nic->regs) {
1970 		err = -EIO;
1971 		pr_err("ioremap failed\n");
1972 		goto err_out_res;
1973 	}
1974 
1975 	if (pdev->irq < 2) {
1976 		err = -EIO;
1977 		pr_err("invalid irq (%d)\n", pdev->irq);
1978 		goto err_out_iomap;
1979 	}
1980 	pci_set_drvdata(pdev, nic);
1981 
1982 	if (pdev->device == 0x3014)
1983 		nic->port_num = 2;
1984 	else
1985 		nic->port_num = 1;
1986 
1987 	print_hw_id(pdev);
1988 
1989 	bdx_hw_reset_direct(nic->regs);
1990 
1991 	nic->irq_type = IRQ_INTX;
1992 #ifdef BDX_MSI
1993 	if ((readl(nic->regs + FPGA_VER) & 0xFFF) >= 378) {
1994 		err = pci_enable_msi(pdev);
1995 		if (err)
1996 			pr_err("Can't eneble msi. error is %d\n", err);
1997 		else
1998 			nic->irq_type = IRQ_MSI;
1999 	} else
2000 		DBG("HW does not support MSI\n");
2001 #endif
2002 
2003     /************** netdev **************/
2004 	for (port = 0; port < nic->port_num; port++) {
2005 		ndev = alloc_etherdev(sizeof(struct bdx_priv));
2006 		if (!ndev) {
2007 			err = -ENOMEM;
2008 			goto err_out_iomap;
2009 		}
2010 
2011 		ndev->netdev_ops = &bdx_netdev_ops;
2012 		ndev->tx_queue_len = BDX_NDEV_TXQ_LEN;
2013 
2014 		bdx_set_ethtool_ops(ndev);	/* ethtool interface */
2015 
2016 		/* these fields are used for info purposes only
2017 		 * so we can have them same for all ports of the board */
2018 		ndev->if_port = port;
2019 		ndev->features = NETIF_F_IP_CSUM | NETIF_F_SG | NETIF_F_TSO
2020 		    | NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX |
2021 		    NETIF_F_HW_VLAN_CTAG_FILTER | NETIF_F_RXCSUM
2022 		    ;
2023 		ndev->hw_features = NETIF_F_IP_CSUM | NETIF_F_SG |
2024 			NETIF_F_TSO | NETIF_F_HW_VLAN_CTAG_TX;
2025 
2026 		if (pci_using_dac)
2027 			ndev->features |= NETIF_F_HIGHDMA;
2028 
2029 	/************** priv ****************/
2030 		priv = nic->priv[port] = netdev_priv(ndev);
2031 
2032 		priv->pBdxRegs = nic->regs + port * 0x8000;
2033 		priv->port = port;
2034 		priv->pdev = pdev;
2035 		priv->ndev = ndev;
2036 		priv->nic = nic;
2037 		priv->msg_enable = BDX_DEF_MSG_ENABLE;
2038 
2039 		netif_napi_add(ndev, &priv->napi, bdx_poll, 64);
2040 
2041 		if ((readl(nic->regs + FPGA_VER) & 0xFFF) == 308) {
2042 			DBG("HW statistics not supported\n");
2043 			priv->stats_flag = 0;
2044 		} else {
2045 			priv->stats_flag = 1;
2046 		}
2047 
2048 		/* Initialize fifo sizes. */
2049 		priv->txd_size = 2;
2050 		priv->txf_size = 2;
2051 		priv->rxd_size = 2;
2052 		priv->rxf_size = 3;
2053 
2054 		/* Initialize the initial coalescing registers. */
2055 		priv->rdintcm = INT_REG_VAL(0x20, 1, 4, 12);
2056 		priv->tdintcm = INT_REG_VAL(0x20, 1, 0, 12);
2057 
2058 		/* ndev->xmit_lock spinlock is not used.
2059 		 * Private priv->tx_lock is used for synchronization
2060 		 * between transmit and TX irq cleanup.  In addition
2061 		 * set multicast list callback has to use priv->tx_lock.
2062 		 */
2063 #ifdef BDX_LLTX
2064 		ndev->features |= NETIF_F_LLTX;
2065 #endif
2066 		spin_lock_init(&priv->tx_lock);
2067 
2068 		/*bdx_hw_reset(priv); */
2069 		if (bdx_read_mac(priv)) {
2070 			pr_err("load MAC address failed\n");
2071 			goto err_out_iomap;
2072 		}
2073 		SET_NETDEV_DEV(ndev, &pdev->dev);
2074 		err = register_netdev(ndev);
2075 		if (err) {
2076 			pr_err("register_netdev failed\n");
2077 			goto err_out_free;
2078 		}
2079 		netif_carrier_off(ndev);
2080 		netif_stop_queue(ndev);
2081 
2082 		print_eth_id(ndev);
2083 	}
2084 	RET(0);
2085 
2086 err_out_free:
2087 	free_netdev(ndev);
2088 err_out_iomap:
2089 	iounmap(nic->regs);
2090 err_out_res:
2091 	pci_release_regions(pdev);
2092 err_dma:
2093 	pci_disable_device(pdev);
2094 err_pci:
2095 	vfree(nic);
2096 
2097 	RET(err);
2098 }
2099 
2100 /****************** Ethtool interface *********************/
2101 /* get strings for statistics counters */
2102 static const char
2103  bdx_stat_names[][ETH_GSTRING_LEN] = {
2104 	"InUCast",		/* 0x7200 */
2105 	"InMCast",		/* 0x7210 */
2106 	"InBCast",		/* 0x7220 */
2107 	"InPkts",		/* 0x7230 */
2108 	"InErrors",		/* 0x7240 */
2109 	"InDropped",		/* 0x7250 */
2110 	"FrameTooLong",		/* 0x7260 */
2111 	"FrameSequenceErrors",	/* 0x7270 */
2112 	"InVLAN",		/* 0x7280 */
2113 	"InDroppedDFE",		/* 0x7290 */
2114 	"InDroppedIntFull",	/* 0x72A0 */
2115 	"InFrameAlignErrors",	/* 0x72B0 */
2116 
2117 	/* 0x72C0-0x72E0 RSRV */
2118 
2119 	"OutUCast",		/* 0x72F0 */
2120 	"OutMCast",		/* 0x7300 */
2121 	"OutBCast",		/* 0x7310 */
2122 	"OutPkts",		/* 0x7320 */
2123 
2124 	/* 0x7330-0x7360 RSRV */
2125 
2126 	"OutVLAN",		/* 0x7370 */
2127 	"InUCastOctects",	/* 0x7380 */
2128 	"OutUCastOctects",	/* 0x7390 */
2129 
2130 	/* 0x73A0-0x73B0 RSRV */
2131 
2132 	"InBCastOctects",	/* 0x73C0 */
2133 	"OutBCastOctects",	/* 0x73D0 */
2134 	"InOctects",		/* 0x73E0 */
2135 	"OutOctects",		/* 0x73F0 */
2136 };
2137 
2138 /*
2139  * bdx_get_settings - get device-specific settings
2140  * @netdev
2141  * @ecmd
2142  */
2143 static int bdx_get_settings(struct net_device *netdev, struct ethtool_cmd *ecmd)
2144 {
2145 	u32 rdintcm;
2146 	u32 tdintcm;
2147 	struct bdx_priv *priv = netdev_priv(netdev);
2148 
2149 	rdintcm = priv->rdintcm;
2150 	tdintcm = priv->tdintcm;
2151 
2152 	ecmd->supported = (SUPPORTED_10000baseT_Full | SUPPORTED_FIBRE);
2153 	ecmd->advertising = (ADVERTISED_10000baseT_Full | ADVERTISED_FIBRE);
2154 	ethtool_cmd_speed_set(ecmd, SPEED_10000);
2155 	ecmd->duplex = DUPLEX_FULL;
2156 	ecmd->port = PORT_FIBRE;
2157 	ecmd->transceiver = XCVR_EXTERNAL;	/* what does it mean? */
2158 	ecmd->autoneg = AUTONEG_DISABLE;
2159 
2160 	/* PCK_TH measures in multiples of FIFO bytes
2161 	   We translate to packets */
2162 	ecmd->maxtxpkt =
2163 	    ((GET_PCK_TH(tdintcm) * PCK_TH_MULT) / BDX_TXF_DESC_SZ);
2164 	ecmd->maxrxpkt =
2165 	    ((GET_PCK_TH(rdintcm) * PCK_TH_MULT) / sizeof(struct rxf_desc));
2166 
2167 	return 0;
2168 }
2169 
2170 /*
2171  * bdx_get_drvinfo - report driver information
2172  * @netdev
2173  * @drvinfo
2174  */
2175 static void
2176 bdx_get_drvinfo(struct net_device *netdev, struct ethtool_drvinfo *drvinfo)
2177 {
2178 	struct bdx_priv *priv = netdev_priv(netdev);
2179 
2180 	strlcpy(drvinfo->driver, BDX_DRV_NAME, sizeof(drvinfo->driver));
2181 	strlcpy(drvinfo->version, BDX_DRV_VERSION, sizeof(drvinfo->version));
2182 	strlcpy(drvinfo->fw_version, "N/A", sizeof(drvinfo->fw_version));
2183 	strlcpy(drvinfo->bus_info, pci_name(priv->pdev),
2184 		sizeof(drvinfo->bus_info));
2185 }
2186 
2187 /*
2188  * bdx_get_coalesce - get interrupt coalescing parameters
2189  * @netdev
2190  * @ecoal
2191  */
2192 static int
2193 bdx_get_coalesce(struct net_device *netdev, struct ethtool_coalesce *ecoal)
2194 {
2195 	u32 rdintcm;
2196 	u32 tdintcm;
2197 	struct bdx_priv *priv = netdev_priv(netdev);
2198 
2199 	rdintcm = priv->rdintcm;
2200 	tdintcm = priv->tdintcm;
2201 
2202 	/* PCK_TH measures in multiples of FIFO bytes
2203 	   We translate to packets */
2204 	ecoal->rx_coalesce_usecs = GET_INT_COAL(rdintcm) * INT_COAL_MULT;
2205 	ecoal->rx_max_coalesced_frames =
2206 	    ((GET_PCK_TH(rdintcm) * PCK_TH_MULT) / sizeof(struct rxf_desc));
2207 
2208 	ecoal->tx_coalesce_usecs = GET_INT_COAL(tdintcm) * INT_COAL_MULT;
2209 	ecoal->tx_max_coalesced_frames =
2210 	    ((GET_PCK_TH(tdintcm) * PCK_TH_MULT) / BDX_TXF_DESC_SZ);
2211 
2212 	/* adaptive parameters ignored */
2213 	return 0;
2214 }
2215 
2216 /*
2217  * bdx_set_coalesce - set interrupt coalescing parameters
2218  * @netdev
2219  * @ecoal
2220  */
2221 static int
2222 bdx_set_coalesce(struct net_device *netdev, struct ethtool_coalesce *ecoal)
2223 {
2224 	u32 rdintcm;
2225 	u32 tdintcm;
2226 	struct bdx_priv *priv = netdev_priv(netdev);
2227 	int rx_coal;
2228 	int tx_coal;
2229 	int rx_max_coal;
2230 	int tx_max_coal;
2231 
2232 	/* Check for valid input */
2233 	rx_coal = ecoal->rx_coalesce_usecs / INT_COAL_MULT;
2234 	tx_coal = ecoal->tx_coalesce_usecs / INT_COAL_MULT;
2235 	rx_max_coal = ecoal->rx_max_coalesced_frames;
2236 	tx_max_coal = ecoal->tx_max_coalesced_frames;
2237 
2238 	/* Translate from packets to multiples of FIFO bytes */
2239 	rx_max_coal =
2240 	    (((rx_max_coal * sizeof(struct rxf_desc)) + PCK_TH_MULT - 1)
2241 	     / PCK_TH_MULT);
2242 	tx_max_coal =
2243 	    (((tx_max_coal * BDX_TXF_DESC_SZ) + PCK_TH_MULT - 1)
2244 	     / PCK_TH_MULT);
2245 
2246 	if ((rx_coal > 0x7FFF) || (tx_coal > 0x7FFF) ||
2247 	    (rx_max_coal > 0xF) || (tx_max_coal > 0xF))
2248 		return -EINVAL;
2249 
2250 	rdintcm = INT_REG_VAL(rx_coal, GET_INT_COAL_RC(priv->rdintcm),
2251 			      GET_RXF_TH(priv->rdintcm), rx_max_coal);
2252 	tdintcm = INT_REG_VAL(tx_coal, GET_INT_COAL_RC(priv->tdintcm), 0,
2253 			      tx_max_coal);
2254 
2255 	priv->rdintcm = rdintcm;
2256 	priv->tdintcm = tdintcm;
2257 
2258 	WRITE_REG(priv, regRDINTCM0, rdintcm);
2259 	WRITE_REG(priv, regTDINTCM0, tdintcm);
2260 
2261 	return 0;
2262 }
2263 
2264 /* Convert RX fifo size to number of pending packets */
2265 static inline int bdx_rx_fifo_size_to_packets(int rx_size)
2266 {
2267 	return (FIFO_SIZE * (1 << rx_size)) / sizeof(struct rxf_desc);
2268 }
2269 
2270 /* Convert TX fifo size to number of pending packets */
2271 static inline int bdx_tx_fifo_size_to_packets(int tx_size)
2272 {
2273 	return (FIFO_SIZE * (1 << tx_size)) / BDX_TXF_DESC_SZ;
2274 }
2275 
2276 /*
2277  * bdx_get_ringparam - report ring sizes
2278  * @netdev
2279  * @ring
2280  */
2281 static void
2282 bdx_get_ringparam(struct net_device *netdev, struct ethtool_ringparam *ring)
2283 {
2284 	struct bdx_priv *priv = netdev_priv(netdev);
2285 
2286 	/*max_pending - the maximum-sized FIFO we allow */
2287 	ring->rx_max_pending = bdx_rx_fifo_size_to_packets(3);
2288 	ring->tx_max_pending = bdx_tx_fifo_size_to_packets(3);
2289 	ring->rx_pending = bdx_rx_fifo_size_to_packets(priv->rxf_size);
2290 	ring->tx_pending = bdx_tx_fifo_size_to_packets(priv->txd_size);
2291 }
2292 
2293 /*
2294  * bdx_set_ringparam - set ring sizes
2295  * @netdev
2296  * @ring
2297  */
2298 static int
2299 bdx_set_ringparam(struct net_device *netdev, struct ethtool_ringparam *ring)
2300 {
2301 	struct bdx_priv *priv = netdev_priv(netdev);
2302 	int rx_size = 0;
2303 	int tx_size = 0;
2304 
2305 	for (; rx_size < 4; rx_size++) {
2306 		if (bdx_rx_fifo_size_to_packets(rx_size) >= ring->rx_pending)
2307 			break;
2308 	}
2309 	if (rx_size == 4)
2310 		rx_size = 3;
2311 
2312 	for (; tx_size < 4; tx_size++) {
2313 		if (bdx_tx_fifo_size_to_packets(tx_size) >= ring->tx_pending)
2314 			break;
2315 	}
2316 	if (tx_size == 4)
2317 		tx_size = 3;
2318 
2319 	/*Is there anything to do? */
2320 	if ((rx_size == priv->rxf_size) &&
2321 	    (tx_size == priv->txd_size))
2322 		return 0;
2323 
2324 	priv->rxf_size = rx_size;
2325 	if (rx_size > 1)
2326 		priv->rxd_size = rx_size - 1;
2327 	else
2328 		priv->rxd_size = rx_size;
2329 
2330 	priv->txf_size = priv->txd_size = tx_size;
2331 
2332 	if (netif_running(netdev)) {
2333 		bdx_close(netdev);
2334 		bdx_open(netdev);
2335 	}
2336 	return 0;
2337 }
2338 
2339 /*
2340  * bdx_get_strings - return a set of strings that describe the requested objects
2341  * @netdev
2342  * @data
2343  */
2344 static void bdx_get_strings(struct net_device *netdev, u32 stringset, u8 *data)
2345 {
2346 	switch (stringset) {
2347 	case ETH_SS_STATS:
2348 		memcpy(data, *bdx_stat_names, sizeof(bdx_stat_names));
2349 		break;
2350 	}
2351 }
2352 
2353 /*
2354  * bdx_get_sset_count - return number of statistics or tests
2355  * @netdev
2356  */
2357 static int bdx_get_sset_count(struct net_device *netdev, int stringset)
2358 {
2359 	struct bdx_priv *priv = netdev_priv(netdev);
2360 
2361 	switch (stringset) {
2362 	case ETH_SS_STATS:
2363 		BDX_ASSERT(ARRAY_SIZE(bdx_stat_names)
2364 			   != sizeof(struct bdx_stats) / sizeof(u64));
2365 		return (priv->stats_flag) ? ARRAY_SIZE(bdx_stat_names)	: 0;
2366 	}
2367 
2368 	return -EINVAL;
2369 }
2370 
2371 /*
2372  * bdx_get_ethtool_stats - return device's hardware L2 statistics
2373  * @netdev
2374  * @stats
2375  * @data
2376  */
2377 static void bdx_get_ethtool_stats(struct net_device *netdev,
2378 				  struct ethtool_stats *stats, u64 *data)
2379 {
2380 	struct bdx_priv *priv = netdev_priv(netdev);
2381 
2382 	if (priv->stats_flag) {
2383 
2384 		/* Update stats from HW */
2385 		bdx_update_stats(priv);
2386 
2387 		/* Copy data to user buffer */
2388 		memcpy(data, &priv->hw_stats, sizeof(priv->hw_stats));
2389 	}
2390 }
2391 
2392 /*
2393  * bdx_set_ethtool_ops - ethtool interface implementation
2394  * @netdev
2395  */
2396 static void bdx_set_ethtool_ops(struct net_device *netdev)
2397 {
2398 	static const struct ethtool_ops bdx_ethtool_ops = {
2399 		.get_settings = bdx_get_settings,
2400 		.get_drvinfo = bdx_get_drvinfo,
2401 		.get_link = ethtool_op_get_link,
2402 		.get_coalesce = bdx_get_coalesce,
2403 		.set_coalesce = bdx_set_coalesce,
2404 		.get_ringparam = bdx_get_ringparam,
2405 		.set_ringparam = bdx_set_ringparam,
2406 		.get_strings = bdx_get_strings,
2407 		.get_sset_count = bdx_get_sset_count,
2408 		.get_ethtool_stats = bdx_get_ethtool_stats,
2409 	};
2410 
2411 	netdev->ethtool_ops = &bdx_ethtool_ops;
2412 }
2413 
2414 /**
2415  * bdx_remove - Device Removal Routine
2416  * @pdev: PCI device information struct
2417  *
2418  * bdx_remove is called by the PCI subsystem to alert the driver
2419  * that it should release a PCI device.  The could be caused by a
2420  * Hot-Plug event, or because the driver is going to be removed from
2421  * memory.
2422  **/
2423 static void bdx_remove(struct pci_dev *pdev)
2424 {
2425 	struct pci_nic *nic = pci_get_drvdata(pdev);
2426 	struct net_device *ndev;
2427 	int port;
2428 
2429 	for (port = 0; port < nic->port_num; port++) {
2430 		ndev = nic->priv[port]->ndev;
2431 		unregister_netdev(ndev);
2432 		free_netdev(ndev);
2433 	}
2434 
2435 	/*bdx_hw_reset_direct(nic->regs); */
2436 #ifdef BDX_MSI
2437 	if (nic->irq_type == IRQ_MSI)
2438 		pci_disable_msi(pdev);
2439 #endif
2440 
2441 	iounmap(nic->regs);
2442 	pci_release_regions(pdev);
2443 	pci_disable_device(pdev);
2444 	vfree(nic);
2445 
2446 	RET();
2447 }
2448 
2449 static struct pci_driver bdx_pci_driver = {
2450 	.name = BDX_DRV_NAME,
2451 	.id_table = bdx_pci_tbl,
2452 	.probe = bdx_probe,
2453 	.remove = bdx_remove,
2454 };
2455 
2456 /*
2457  * print_driver_id - print parameters of the driver build
2458  */
2459 static void __init print_driver_id(void)
2460 {
2461 	pr_info("%s, %s\n", BDX_DRV_DESC, BDX_DRV_VERSION);
2462 	pr_info("Options: hw_csum %s\n", BDX_MSI_STRING);
2463 }
2464 
2465 static int __init bdx_module_init(void)
2466 {
2467 	ENTER;
2468 	init_txd_sizes();
2469 	print_driver_id();
2470 	RET(pci_register_driver(&bdx_pci_driver));
2471 }
2472 
2473 module_init(bdx_module_init);
2474 
2475 static void __exit bdx_module_exit(void)
2476 {
2477 	ENTER;
2478 	pci_unregister_driver(&bdx_pci_driver);
2479 	RET();
2480 }
2481 
2482 module_exit(bdx_module_exit);
2483 
2484 MODULE_LICENSE("GPL");
2485 MODULE_AUTHOR(DRIVER_AUTHOR);
2486 MODULE_DESCRIPTION(BDX_DRV_DESC);
2487 MODULE_FIRMWARE("tehuti/bdx.bin");
2488