1 /* 2 * Tehuti Networks(R) Network Driver 3 * ethtool interface implementation 4 * Copyright (C) 2007 Tehuti Networks Ltd. All rights reserved 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 */ 11 12 /* 13 * RX HW/SW interaction overview 14 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 15 * There are 2 types of RX communication channels between driver and NIC. 16 * 1) RX Free Fifo - RXF - holds descriptors of empty buffers to accept incoming 17 * traffic. This Fifo is filled by SW and is readen by HW. Each descriptor holds 18 * info about buffer's location, size and ID. An ID field is used to identify a 19 * buffer when it's returned with data via RXD Fifo (see below) 20 * 2) RX Data Fifo - RXD - holds descriptors of full buffers. This Fifo is 21 * filled by HW and is readen by SW. Each descriptor holds status and ID. 22 * HW pops descriptor from RXF Fifo, stores ID, fills buffer with incoming data, 23 * via dma moves it into host memory, builds new RXD descriptor with same ID, 24 * pushes it into RXD Fifo and raises interrupt to indicate new RX data. 25 * 26 * Current NIC configuration (registers + firmware) makes NIC use 2 RXF Fifos. 27 * One holds 1.5K packets and another - 26K packets. Depending on incoming 28 * packet size, HW desides on a RXF Fifo to pop buffer from. When packet is 29 * filled with data, HW builds new RXD descriptor for it and push it into single 30 * RXD Fifo. 31 * 32 * RX SW Data Structures 33 * ~~~~~~~~~~~~~~~~~~~~~ 34 * skb db - used to keep track of all skbs owned by SW and their dma addresses. 35 * For RX case, ownership lasts from allocating new empty skb for RXF until 36 * accepting full skb from RXD and passing it to OS. Each RXF Fifo has its own 37 * skb db. Implemented as array with bitmask. 38 * fifo - keeps info about fifo's size and location, relevant HW registers, 39 * usage and skb db. Each RXD and RXF Fifo has its own fifo structure. 40 * Implemented as simple struct. 41 * 42 * RX SW Execution Flow 43 * ~~~~~~~~~~~~~~~~~~~~ 44 * Upon initialization (ifconfig up) driver creates RX fifos and initializes 45 * relevant registers. At the end of init phase, driver enables interrupts. 46 * NIC sees that there is no RXF buffers and raises 47 * RD_INTR interrupt, isr fills skbs and Rx begins. 48 * Driver has two receive operation modes: 49 * NAPI - interrupt-driven mixed with polling 50 * interrupt-driven only 51 * 52 * Interrupt-driven only flow is following. When buffer is ready, HW raises 53 * interrupt and isr is called. isr collects all available packets 54 * (bdx_rx_receive), refills skbs (bdx_rx_alloc_skbs) and exit. 55 56 * Rx buffer allocation note 57 * ~~~~~~~~~~~~~~~~~~~~~~~~~ 58 * Driver cares to feed such amount of RxF descriptors that respective amount of 59 * RxD descriptors can not fill entire RxD fifo. The main reason is lack of 60 * overflow check in Bordeaux for RxD fifo free/used size. 61 * FIXME: this is NOT fully implemented, more work should be done 62 * 63 */ 64 65 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 66 67 #include "tehuti.h" 68 69 static DEFINE_PCI_DEVICE_TABLE(bdx_pci_tbl) = { 70 { PCI_VDEVICE(TEHUTI, 0x3009), }, 71 { PCI_VDEVICE(TEHUTI, 0x3010), }, 72 { PCI_VDEVICE(TEHUTI, 0x3014), }, 73 { 0 } 74 }; 75 76 MODULE_DEVICE_TABLE(pci, bdx_pci_tbl); 77 78 /* Definitions needed by ISR or NAPI functions */ 79 static void bdx_rx_alloc_skbs(struct bdx_priv *priv, struct rxf_fifo *f); 80 static void bdx_tx_cleanup(struct bdx_priv *priv); 81 static int bdx_rx_receive(struct bdx_priv *priv, struct rxd_fifo *f, int budget); 82 83 /* Definitions needed by FW loading */ 84 static void bdx_tx_push_desc_safe(struct bdx_priv *priv, void *data, int size); 85 86 /* Definitions needed by hw_start */ 87 static int bdx_tx_init(struct bdx_priv *priv); 88 static int bdx_rx_init(struct bdx_priv *priv); 89 90 /* Definitions needed by bdx_close */ 91 static void bdx_rx_free(struct bdx_priv *priv); 92 static void bdx_tx_free(struct bdx_priv *priv); 93 94 /* Definitions needed by bdx_probe */ 95 static void bdx_set_ethtool_ops(struct net_device *netdev); 96 97 /************************************************************************* 98 * Print Info * 99 *************************************************************************/ 100 101 static void print_hw_id(struct pci_dev *pdev) 102 { 103 struct pci_nic *nic = pci_get_drvdata(pdev); 104 u16 pci_link_status = 0; 105 u16 pci_ctrl = 0; 106 107 pci_read_config_word(pdev, PCI_LINK_STATUS_REG, &pci_link_status); 108 pci_read_config_word(pdev, PCI_DEV_CTRL_REG, &pci_ctrl); 109 110 pr_info("%s%s\n", BDX_NIC_NAME, 111 nic->port_num == 1 ? "" : ", 2-Port"); 112 pr_info("srom 0x%x fpga %d build %u lane# %d max_pl 0x%x mrrs 0x%x\n", 113 readl(nic->regs + SROM_VER), readl(nic->regs + FPGA_VER) & 0xFFF, 114 readl(nic->regs + FPGA_SEED), 115 GET_LINK_STATUS_LANES(pci_link_status), 116 GET_DEV_CTRL_MAXPL(pci_ctrl), GET_DEV_CTRL_MRRS(pci_ctrl)); 117 } 118 119 static void print_fw_id(struct pci_nic *nic) 120 { 121 pr_info("fw 0x%x\n", readl(nic->regs + FW_VER)); 122 } 123 124 static void print_eth_id(struct net_device *ndev) 125 { 126 netdev_info(ndev, "%s, Port %c\n", 127 BDX_NIC_NAME, (ndev->if_port == 0) ? 'A' : 'B'); 128 129 } 130 131 /************************************************************************* 132 * Code * 133 *************************************************************************/ 134 135 #define bdx_enable_interrupts(priv) \ 136 do { WRITE_REG(priv, regIMR, IR_RUN); } while (0) 137 #define bdx_disable_interrupts(priv) \ 138 do { WRITE_REG(priv, regIMR, 0); } while (0) 139 140 /* bdx_fifo_init 141 * create TX/RX descriptor fifo for host-NIC communication. 142 * 1K extra space is allocated at the end of the fifo to simplify 143 * processing of descriptors that wraps around fifo's end 144 * @priv - NIC private structure 145 * @f - fifo to initialize 146 * @fsz_type - fifo size type: 0-4KB, 1-8KB, 2-16KB, 3-32KB 147 * @reg_XXX - offsets of registers relative to base address 148 * 149 * Returns 0 on success, negative value on failure 150 * 151 */ 152 static int 153 bdx_fifo_init(struct bdx_priv *priv, struct fifo *f, int fsz_type, 154 u16 reg_CFG0, u16 reg_CFG1, u16 reg_RPTR, u16 reg_WPTR) 155 { 156 u16 memsz = FIFO_SIZE * (1 << fsz_type); 157 158 memset(f, 0, sizeof(struct fifo)); 159 /* pci_alloc_consistent gives us 4k-aligned memory */ 160 f->va = pci_alloc_consistent(priv->pdev, 161 memsz + FIFO_EXTRA_SPACE, &f->da); 162 if (!f->va) { 163 pr_err("pci_alloc_consistent failed\n"); 164 RET(-ENOMEM); 165 } 166 f->reg_CFG0 = reg_CFG0; 167 f->reg_CFG1 = reg_CFG1; 168 f->reg_RPTR = reg_RPTR; 169 f->reg_WPTR = reg_WPTR; 170 f->rptr = 0; 171 f->wptr = 0; 172 f->memsz = memsz; 173 f->size_mask = memsz - 1; 174 WRITE_REG(priv, reg_CFG0, (u32) ((f->da & TX_RX_CFG0_BASE) | fsz_type)); 175 WRITE_REG(priv, reg_CFG1, H32_64(f->da)); 176 177 RET(0); 178 } 179 180 /* bdx_fifo_free - free all resources used by fifo 181 * @priv - NIC private structure 182 * @f - fifo to release 183 */ 184 static void bdx_fifo_free(struct bdx_priv *priv, struct fifo *f) 185 { 186 ENTER; 187 if (f->va) { 188 pci_free_consistent(priv->pdev, 189 f->memsz + FIFO_EXTRA_SPACE, f->va, f->da); 190 f->va = NULL; 191 } 192 RET(); 193 } 194 195 /* 196 * bdx_link_changed - notifies OS about hw link state. 197 * @bdx_priv - hw adapter structure 198 */ 199 static void bdx_link_changed(struct bdx_priv *priv) 200 { 201 u32 link = READ_REG(priv, regMAC_LNK_STAT) & MAC_LINK_STAT; 202 203 if (!link) { 204 if (netif_carrier_ok(priv->ndev)) { 205 netif_stop_queue(priv->ndev); 206 netif_carrier_off(priv->ndev); 207 netdev_err(priv->ndev, "Link Down\n"); 208 } 209 } else { 210 if (!netif_carrier_ok(priv->ndev)) { 211 netif_wake_queue(priv->ndev); 212 netif_carrier_on(priv->ndev); 213 netdev_err(priv->ndev, "Link Up\n"); 214 } 215 } 216 } 217 218 static void bdx_isr_extra(struct bdx_priv *priv, u32 isr) 219 { 220 if (isr & IR_RX_FREE_0) { 221 bdx_rx_alloc_skbs(priv, &priv->rxf_fifo0); 222 DBG("RX_FREE_0\n"); 223 } 224 225 if (isr & IR_LNKCHG0) 226 bdx_link_changed(priv); 227 228 if (isr & IR_PCIE_LINK) 229 netdev_err(priv->ndev, "PCI-E Link Fault\n"); 230 231 if (isr & IR_PCIE_TOUT) 232 netdev_err(priv->ndev, "PCI-E Time Out\n"); 233 234 } 235 236 /* bdx_isr - Interrupt Service Routine for Bordeaux NIC 237 * @irq - interrupt number 238 * @ndev - network device 239 * @regs - CPU registers 240 * 241 * Return IRQ_NONE if it was not our interrupt, IRQ_HANDLED - otherwise 242 * 243 * It reads ISR register to know interrupt reasons, and proceed them one by one. 244 * Reasons of interest are: 245 * RX_DESC - new packet has arrived and RXD fifo holds its descriptor 246 * RX_FREE - number of free Rx buffers in RXF fifo gets low 247 * TX_FREE - packet was transmited and RXF fifo holds its descriptor 248 */ 249 250 static irqreturn_t bdx_isr_napi(int irq, void *dev) 251 { 252 struct net_device *ndev = dev; 253 struct bdx_priv *priv = netdev_priv(ndev); 254 u32 isr; 255 256 ENTER; 257 isr = (READ_REG(priv, regISR) & IR_RUN); 258 if (unlikely(!isr)) { 259 bdx_enable_interrupts(priv); 260 return IRQ_NONE; /* Not our interrupt */ 261 } 262 263 if (isr & IR_EXTRA) 264 bdx_isr_extra(priv, isr); 265 266 if (isr & (IR_RX_DESC_0 | IR_TX_FREE_0)) { 267 if (likely(napi_schedule_prep(&priv->napi))) { 268 __napi_schedule(&priv->napi); 269 RET(IRQ_HANDLED); 270 } else { 271 /* NOTE: we get here if intr has slipped into window 272 * between these lines in bdx_poll: 273 * bdx_enable_interrupts(priv); 274 * return 0; 275 * currently intrs are disabled (since we read ISR), 276 * and we have failed to register next poll. 277 * so we read the regs to trigger chip 278 * and allow further interupts. */ 279 READ_REG(priv, regTXF_WPTR_0); 280 READ_REG(priv, regRXD_WPTR_0); 281 } 282 } 283 284 bdx_enable_interrupts(priv); 285 RET(IRQ_HANDLED); 286 } 287 288 static int bdx_poll(struct napi_struct *napi, int budget) 289 { 290 struct bdx_priv *priv = container_of(napi, struct bdx_priv, napi); 291 int work_done; 292 293 ENTER; 294 bdx_tx_cleanup(priv); 295 work_done = bdx_rx_receive(priv, &priv->rxd_fifo0, budget); 296 if ((work_done < budget) || 297 (priv->napi_stop++ >= 30)) { 298 DBG("rx poll is done. backing to isr-driven\n"); 299 300 /* from time to time we exit to let NAPI layer release 301 * device lock and allow waiting tasks (eg rmmod) to advance) */ 302 priv->napi_stop = 0; 303 304 napi_complete(napi); 305 bdx_enable_interrupts(priv); 306 } 307 return work_done; 308 } 309 310 /* bdx_fw_load - loads firmware to NIC 311 * @priv - NIC private structure 312 * Firmware is loaded via TXD fifo, so it must be initialized first. 313 * Firware must be loaded once per NIC not per PCI device provided by NIC (NIC 314 * can have few of them). So all drivers use semaphore register to choose one 315 * that will actually load FW to NIC. 316 */ 317 318 static int bdx_fw_load(struct bdx_priv *priv) 319 { 320 const struct firmware *fw = NULL; 321 int master, i; 322 int rc; 323 324 ENTER; 325 master = READ_REG(priv, regINIT_SEMAPHORE); 326 if (!READ_REG(priv, regINIT_STATUS) && master) { 327 rc = request_firmware(&fw, "tehuti/bdx.bin", &priv->pdev->dev); 328 if (rc) 329 goto out; 330 bdx_tx_push_desc_safe(priv, (char *)fw->data, fw->size); 331 mdelay(100); 332 } 333 for (i = 0; i < 200; i++) { 334 if (READ_REG(priv, regINIT_STATUS)) { 335 rc = 0; 336 goto out; 337 } 338 mdelay(2); 339 } 340 rc = -EIO; 341 out: 342 if (master) 343 WRITE_REG(priv, regINIT_SEMAPHORE, 1); 344 345 release_firmware(fw); 346 347 if (rc) { 348 netdev_err(priv->ndev, "firmware loading failed\n"); 349 if (rc == -EIO) 350 DBG("VPC = 0x%x VIC = 0x%x INIT_STATUS = 0x%x i=%d\n", 351 READ_REG(priv, regVPC), 352 READ_REG(priv, regVIC), 353 READ_REG(priv, regINIT_STATUS), i); 354 RET(rc); 355 } else { 356 DBG("%s: firmware loading success\n", priv->ndev->name); 357 RET(0); 358 } 359 } 360 361 static void bdx_restore_mac(struct net_device *ndev, struct bdx_priv *priv) 362 { 363 u32 val; 364 365 ENTER; 366 DBG("mac0=%x mac1=%x mac2=%x\n", 367 READ_REG(priv, regUNC_MAC0_A), 368 READ_REG(priv, regUNC_MAC1_A), READ_REG(priv, regUNC_MAC2_A)); 369 370 val = (ndev->dev_addr[0] << 8) | (ndev->dev_addr[1]); 371 WRITE_REG(priv, regUNC_MAC2_A, val); 372 val = (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]); 373 WRITE_REG(priv, regUNC_MAC1_A, val); 374 val = (ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]); 375 WRITE_REG(priv, regUNC_MAC0_A, val); 376 377 DBG("mac0=%x mac1=%x mac2=%x\n", 378 READ_REG(priv, regUNC_MAC0_A), 379 READ_REG(priv, regUNC_MAC1_A), READ_REG(priv, regUNC_MAC2_A)); 380 RET(); 381 } 382 383 /* bdx_hw_start - inits registers and starts HW's Rx and Tx engines 384 * @priv - NIC private structure 385 */ 386 static int bdx_hw_start(struct bdx_priv *priv) 387 { 388 int rc = -EIO; 389 struct net_device *ndev = priv->ndev; 390 391 ENTER; 392 bdx_link_changed(priv); 393 394 /* 10G overall max length (vlan, eth&ip header, ip payload, crc) */ 395 WRITE_REG(priv, regFRM_LENGTH, 0X3FE0); 396 WRITE_REG(priv, regPAUSE_QUANT, 0x96); 397 WRITE_REG(priv, regRX_FIFO_SECTION, 0x800010); 398 WRITE_REG(priv, regTX_FIFO_SECTION, 0xE00010); 399 WRITE_REG(priv, regRX_FULLNESS, 0); 400 WRITE_REG(priv, regTX_FULLNESS, 0); 401 WRITE_REG(priv, regCTRLST, 402 regCTRLST_BASE | regCTRLST_RX_ENA | regCTRLST_TX_ENA); 403 404 WRITE_REG(priv, regVGLB, 0); 405 WRITE_REG(priv, regMAX_FRAME_A, 406 priv->rxf_fifo0.m.pktsz & MAX_FRAME_AB_VAL); 407 408 DBG("RDINTCM=%08x\n", priv->rdintcm); /*NOTE: test script uses this */ 409 WRITE_REG(priv, regRDINTCM0, priv->rdintcm); 410 WRITE_REG(priv, regRDINTCM2, 0); /*cpu_to_le32(rcm.val)); */ 411 412 DBG("TDINTCM=%08x\n", priv->tdintcm); /*NOTE: test script uses this */ 413 WRITE_REG(priv, regTDINTCM0, priv->tdintcm); /* old val = 0x300064 */ 414 415 /* Enable timer interrupt once in 2 secs. */ 416 /*WRITE_REG(priv, regGTMR0, ((GTMR_SEC * 2) & GTMR_DATA)); */ 417 bdx_restore_mac(priv->ndev, priv); 418 419 WRITE_REG(priv, regGMAC_RXF_A, GMAC_RX_FILTER_OSEN | 420 GMAC_RX_FILTER_AM | GMAC_RX_FILTER_AB); 421 422 #define BDX_IRQ_TYPE ((priv->nic->irq_type == IRQ_MSI) ? 0 : IRQF_SHARED) 423 424 rc = request_irq(priv->pdev->irq, bdx_isr_napi, BDX_IRQ_TYPE, 425 ndev->name, ndev); 426 if (rc) 427 goto err_irq; 428 bdx_enable_interrupts(priv); 429 430 RET(0); 431 432 err_irq: 433 RET(rc); 434 } 435 436 static void bdx_hw_stop(struct bdx_priv *priv) 437 { 438 ENTER; 439 bdx_disable_interrupts(priv); 440 free_irq(priv->pdev->irq, priv->ndev); 441 442 netif_carrier_off(priv->ndev); 443 netif_stop_queue(priv->ndev); 444 445 RET(); 446 } 447 448 static int bdx_hw_reset_direct(void __iomem *regs) 449 { 450 u32 val, i; 451 ENTER; 452 453 /* reset sequences: read, write 1, read, write 0 */ 454 val = readl(regs + regCLKPLL); 455 writel((val | CLKPLL_SFTRST) + 0x8, regs + regCLKPLL); 456 udelay(50); 457 val = readl(regs + regCLKPLL); 458 writel(val & ~CLKPLL_SFTRST, regs + regCLKPLL); 459 460 /* check that the PLLs are locked and reset ended */ 461 for (i = 0; i < 70; i++, mdelay(10)) 462 if ((readl(regs + regCLKPLL) & CLKPLL_LKD) == CLKPLL_LKD) { 463 /* do any PCI-E read transaction */ 464 readl(regs + regRXD_CFG0_0); 465 return 0; 466 } 467 pr_err("HW reset failed\n"); 468 return 1; /* failure */ 469 } 470 471 static int bdx_hw_reset(struct bdx_priv *priv) 472 { 473 u32 val, i; 474 ENTER; 475 476 if (priv->port == 0) { 477 /* reset sequences: read, write 1, read, write 0 */ 478 val = READ_REG(priv, regCLKPLL); 479 WRITE_REG(priv, regCLKPLL, (val | CLKPLL_SFTRST) + 0x8); 480 udelay(50); 481 val = READ_REG(priv, regCLKPLL); 482 WRITE_REG(priv, regCLKPLL, val & ~CLKPLL_SFTRST); 483 } 484 /* check that the PLLs are locked and reset ended */ 485 for (i = 0; i < 70; i++, mdelay(10)) 486 if ((READ_REG(priv, regCLKPLL) & CLKPLL_LKD) == CLKPLL_LKD) { 487 /* do any PCI-E read transaction */ 488 READ_REG(priv, regRXD_CFG0_0); 489 return 0; 490 } 491 pr_err("HW reset failed\n"); 492 return 1; /* failure */ 493 } 494 495 static int bdx_sw_reset(struct bdx_priv *priv) 496 { 497 int i; 498 499 ENTER; 500 /* 1. load MAC (obsolete) */ 501 /* 2. disable Rx (and Tx) */ 502 WRITE_REG(priv, regGMAC_RXF_A, 0); 503 mdelay(100); 504 /* 3. disable port */ 505 WRITE_REG(priv, regDIS_PORT, 1); 506 /* 4. disable queue */ 507 WRITE_REG(priv, regDIS_QU, 1); 508 /* 5. wait until hw is disabled */ 509 for (i = 0; i < 50; i++) { 510 if (READ_REG(priv, regRST_PORT) & 1) 511 break; 512 mdelay(10); 513 } 514 if (i == 50) 515 netdev_err(priv->ndev, "SW reset timeout. continuing anyway\n"); 516 517 /* 6. disable intrs */ 518 WRITE_REG(priv, regRDINTCM0, 0); 519 WRITE_REG(priv, regTDINTCM0, 0); 520 WRITE_REG(priv, regIMR, 0); 521 READ_REG(priv, regISR); 522 523 /* 7. reset queue */ 524 WRITE_REG(priv, regRST_QU, 1); 525 /* 8. reset port */ 526 WRITE_REG(priv, regRST_PORT, 1); 527 /* 9. zero all read and write pointers */ 528 for (i = regTXD_WPTR_0; i <= regTXF_RPTR_3; i += 0x10) 529 DBG("%x = %x\n", i, READ_REG(priv, i) & TXF_WPTR_WR_PTR); 530 for (i = regTXD_WPTR_0; i <= regTXF_RPTR_3; i += 0x10) 531 WRITE_REG(priv, i, 0); 532 /* 10. unseet port disable */ 533 WRITE_REG(priv, regDIS_PORT, 0); 534 /* 11. unset queue disable */ 535 WRITE_REG(priv, regDIS_QU, 0); 536 /* 12. unset queue reset */ 537 WRITE_REG(priv, regRST_QU, 0); 538 /* 13. unset port reset */ 539 WRITE_REG(priv, regRST_PORT, 0); 540 /* 14. enable Rx */ 541 /* skiped. will be done later */ 542 /* 15. save MAC (obsolete) */ 543 for (i = regTXD_WPTR_0; i <= regTXF_RPTR_3; i += 0x10) 544 DBG("%x = %x\n", i, READ_REG(priv, i) & TXF_WPTR_WR_PTR); 545 546 RET(0); 547 } 548 549 /* bdx_reset - performs right type of reset depending on hw type */ 550 static int bdx_reset(struct bdx_priv *priv) 551 { 552 ENTER; 553 RET((priv->pdev->device == 0x3009) 554 ? bdx_hw_reset(priv) 555 : bdx_sw_reset(priv)); 556 } 557 558 /** 559 * bdx_close - Disables a network interface 560 * @netdev: network interface device structure 561 * 562 * Returns 0, this is not allowed to fail 563 * 564 * The close entry point is called when an interface is de-activated 565 * by the OS. The hardware is still under the drivers control, but 566 * needs to be disabled. A global MAC reset is issued to stop the 567 * hardware, and all transmit and receive resources are freed. 568 **/ 569 static int bdx_close(struct net_device *ndev) 570 { 571 struct bdx_priv *priv = NULL; 572 573 ENTER; 574 priv = netdev_priv(ndev); 575 576 napi_disable(&priv->napi); 577 578 bdx_reset(priv); 579 bdx_hw_stop(priv); 580 bdx_rx_free(priv); 581 bdx_tx_free(priv); 582 RET(0); 583 } 584 585 /** 586 * bdx_open - Called when a network interface is made active 587 * @netdev: network interface device structure 588 * 589 * Returns 0 on success, negative value on failure 590 * 591 * The open entry point is called when a network interface is made 592 * active by the system (IFF_UP). At this point all resources needed 593 * for transmit and receive operations are allocated, the interrupt 594 * handler is registered with the OS, the watchdog timer is started, 595 * and the stack is notified that the interface is ready. 596 **/ 597 static int bdx_open(struct net_device *ndev) 598 { 599 struct bdx_priv *priv; 600 int rc; 601 602 ENTER; 603 priv = netdev_priv(ndev); 604 bdx_reset(priv); 605 if (netif_running(ndev)) 606 netif_stop_queue(priv->ndev); 607 608 if ((rc = bdx_tx_init(priv)) || 609 (rc = bdx_rx_init(priv)) || 610 (rc = bdx_fw_load(priv))) 611 goto err; 612 613 bdx_rx_alloc_skbs(priv, &priv->rxf_fifo0); 614 615 rc = bdx_hw_start(priv); 616 if (rc) 617 goto err; 618 619 napi_enable(&priv->napi); 620 621 print_fw_id(priv->nic); 622 623 RET(0); 624 625 err: 626 bdx_close(ndev); 627 RET(rc); 628 } 629 630 static int bdx_range_check(struct bdx_priv *priv, u32 offset) 631 { 632 return (offset > (u32) (BDX_REGS_SIZE / priv->nic->port_num)) ? 633 -EINVAL : 0; 634 } 635 636 static int bdx_ioctl_priv(struct net_device *ndev, struct ifreq *ifr, int cmd) 637 { 638 struct bdx_priv *priv = netdev_priv(ndev); 639 u32 data[3]; 640 int error; 641 642 ENTER; 643 644 DBG("jiffies=%ld cmd=%d\n", jiffies, cmd); 645 if (cmd != SIOCDEVPRIVATE) { 646 error = copy_from_user(data, ifr->ifr_data, sizeof(data)); 647 if (error) { 648 pr_err("can't copy from user\n"); 649 RET(-EFAULT); 650 } 651 DBG("%d 0x%x 0x%x\n", data[0], data[1], data[2]); 652 } 653 654 if (!capable(CAP_SYS_RAWIO)) 655 return -EPERM; 656 657 switch (data[0]) { 658 659 case BDX_OP_READ: 660 error = bdx_range_check(priv, data[1]); 661 if (error < 0) 662 return error; 663 data[2] = READ_REG(priv, data[1]); 664 DBG("read_reg(0x%x)=0x%x (dec %d)\n", data[1], data[2], 665 data[2]); 666 error = copy_to_user(ifr->ifr_data, data, sizeof(data)); 667 if (error) 668 RET(-EFAULT); 669 break; 670 671 case BDX_OP_WRITE: 672 error = bdx_range_check(priv, data[1]); 673 if (error < 0) 674 return error; 675 WRITE_REG(priv, data[1], data[2]); 676 DBG("write_reg(0x%x, 0x%x)\n", data[1], data[2]); 677 break; 678 679 default: 680 RET(-EOPNOTSUPP); 681 } 682 return 0; 683 } 684 685 static int bdx_ioctl(struct net_device *ndev, struct ifreq *ifr, int cmd) 686 { 687 ENTER; 688 if (cmd >= SIOCDEVPRIVATE && cmd <= (SIOCDEVPRIVATE + 15)) 689 RET(bdx_ioctl_priv(ndev, ifr, cmd)); 690 else 691 RET(-EOPNOTSUPP); 692 } 693 694 /* 695 * __bdx_vlan_rx_vid - private helper for adding/killing VLAN vid 696 * by passing VLAN filter table to hardware 697 * @ndev network device 698 * @vid VLAN vid 699 * @op add or kill operation 700 */ 701 static void __bdx_vlan_rx_vid(struct net_device *ndev, uint16_t vid, int enable) 702 { 703 struct bdx_priv *priv = netdev_priv(ndev); 704 u32 reg, bit, val; 705 706 ENTER; 707 DBG2("vid=%d value=%d\n", (int)vid, enable); 708 if (unlikely(vid >= 4096)) { 709 pr_err("invalid VID: %u (> 4096)\n", vid); 710 RET(); 711 } 712 reg = regVLAN_0 + (vid / 32) * 4; 713 bit = 1 << vid % 32; 714 val = READ_REG(priv, reg); 715 DBG2("reg=%x, val=%x, bit=%d\n", reg, val, bit); 716 if (enable) 717 val |= bit; 718 else 719 val &= ~bit; 720 DBG2("new val %x\n", val); 721 WRITE_REG(priv, reg, val); 722 RET(); 723 } 724 725 /* 726 * bdx_vlan_rx_add_vid - kernel hook for adding VLAN vid to hw filtering table 727 * @ndev network device 728 * @vid VLAN vid to add 729 */ 730 static int bdx_vlan_rx_add_vid(struct net_device *ndev, uint16_t vid) 731 { 732 __bdx_vlan_rx_vid(ndev, vid, 1); 733 return 0; 734 } 735 736 /* 737 * bdx_vlan_rx_kill_vid - kernel hook for killing VLAN vid in hw filtering table 738 * @ndev network device 739 * @vid VLAN vid to kill 740 */ 741 static int bdx_vlan_rx_kill_vid(struct net_device *ndev, unsigned short vid) 742 { 743 __bdx_vlan_rx_vid(ndev, vid, 0); 744 return 0; 745 } 746 747 /** 748 * bdx_change_mtu - Change the Maximum Transfer Unit 749 * @netdev: network interface device structure 750 * @new_mtu: new value for maximum frame size 751 * 752 * Returns 0 on success, negative on failure 753 */ 754 static int bdx_change_mtu(struct net_device *ndev, int new_mtu) 755 { 756 ENTER; 757 758 if (new_mtu == ndev->mtu) 759 RET(0); 760 761 /* enforce minimum frame size */ 762 if (new_mtu < ETH_ZLEN) { 763 netdev_err(ndev, "mtu %d is less then minimal %d\n", 764 new_mtu, ETH_ZLEN); 765 RET(-EINVAL); 766 } 767 768 ndev->mtu = new_mtu; 769 if (netif_running(ndev)) { 770 bdx_close(ndev); 771 bdx_open(ndev); 772 } 773 RET(0); 774 } 775 776 static void bdx_setmulti(struct net_device *ndev) 777 { 778 struct bdx_priv *priv = netdev_priv(ndev); 779 780 u32 rxf_val = 781 GMAC_RX_FILTER_AM | GMAC_RX_FILTER_AB | GMAC_RX_FILTER_OSEN; 782 int i; 783 784 ENTER; 785 /* IMF - imperfect (hash) rx multicat filter */ 786 /* PMF - perfect rx multicat filter */ 787 788 /* FIXME: RXE(OFF) */ 789 if (ndev->flags & IFF_PROMISC) { 790 rxf_val |= GMAC_RX_FILTER_PRM; 791 } else if (ndev->flags & IFF_ALLMULTI) { 792 /* set IMF to accept all multicast frmaes */ 793 for (i = 0; i < MAC_MCST_HASH_NUM; i++) 794 WRITE_REG(priv, regRX_MCST_HASH0 + i * 4, ~0); 795 } else if (!netdev_mc_empty(ndev)) { 796 u8 hash; 797 struct netdev_hw_addr *ha; 798 u32 reg, val; 799 800 /* set IMF to deny all multicast frames */ 801 for (i = 0; i < MAC_MCST_HASH_NUM; i++) 802 WRITE_REG(priv, regRX_MCST_HASH0 + i * 4, 0); 803 /* set PMF to deny all multicast frames */ 804 for (i = 0; i < MAC_MCST_NUM; i++) { 805 WRITE_REG(priv, regRX_MAC_MCST0 + i * 8, 0); 806 WRITE_REG(priv, regRX_MAC_MCST1 + i * 8, 0); 807 } 808 809 /* use PMF to accept first MAC_MCST_NUM (15) addresses */ 810 /* TBD: sort addresses and write them in ascending order 811 * into RX_MAC_MCST regs. we skip this phase now and accept ALL 812 * multicast frames throu IMF */ 813 /* accept the rest of addresses throu IMF */ 814 netdev_for_each_mc_addr(ha, ndev) { 815 hash = 0; 816 for (i = 0; i < ETH_ALEN; i++) 817 hash ^= ha->addr[i]; 818 reg = regRX_MCST_HASH0 + ((hash >> 5) << 2); 819 val = READ_REG(priv, reg); 820 val |= (1 << (hash % 32)); 821 WRITE_REG(priv, reg, val); 822 } 823 824 } else { 825 DBG("only own mac %d\n", netdev_mc_count(ndev)); 826 rxf_val |= GMAC_RX_FILTER_AB; 827 } 828 WRITE_REG(priv, regGMAC_RXF_A, rxf_val); 829 /* enable RX */ 830 /* FIXME: RXE(ON) */ 831 RET(); 832 } 833 834 static int bdx_set_mac(struct net_device *ndev, void *p) 835 { 836 struct bdx_priv *priv = netdev_priv(ndev); 837 struct sockaddr *addr = p; 838 839 ENTER; 840 /* 841 if (netif_running(dev)) 842 return -EBUSY 843 */ 844 memcpy(ndev->dev_addr, addr->sa_data, ndev->addr_len); 845 bdx_restore_mac(ndev, priv); 846 RET(0); 847 } 848 849 static int bdx_read_mac(struct bdx_priv *priv) 850 { 851 u16 macAddress[3], i; 852 ENTER; 853 854 macAddress[2] = READ_REG(priv, regUNC_MAC0_A); 855 macAddress[2] = READ_REG(priv, regUNC_MAC0_A); 856 macAddress[1] = READ_REG(priv, regUNC_MAC1_A); 857 macAddress[1] = READ_REG(priv, regUNC_MAC1_A); 858 macAddress[0] = READ_REG(priv, regUNC_MAC2_A); 859 macAddress[0] = READ_REG(priv, regUNC_MAC2_A); 860 for (i = 0; i < 3; i++) { 861 priv->ndev->dev_addr[i * 2 + 1] = macAddress[i]; 862 priv->ndev->dev_addr[i * 2] = macAddress[i] >> 8; 863 } 864 RET(0); 865 } 866 867 static u64 bdx_read_l2stat(struct bdx_priv *priv, int reg) 868 { 869 u64 val; 870 871 val = READ_REG(priv, reg); 872 val |= ((u64) READ_REG(priv, reg + 8)) << 32; 873 return val; 874 } 875 876 /*Do the statistics-update work*/ 877 static void bdx_update_stats(struct bdx_priv *priv) 878 { 879 struct bdx_stats *stats = &priv->hw_stats; 880 u64 *stats_vector = (u64 *) stats; 881 int i; 882 int addr; 883 884 /*Fill HW structure */ 885 addr = 0x7200; 886 /*First 12 statistics - 0x7200 - 0x72B0 */ 887 for (i = 0; i < 12; i++) { 888 stats_vector[i] = bdx_read_l2stat(priv, addr); 889 addr += 0x10; 890 } 891 BDX_ASSERT(addr != 0x72C0); 892 /* 0x72C0-0x72E0 RSRV */ 893 addr = 0x72F0; 894 for (; i < 16; i++) { 895 stats_vector[i] = bdx_read_l2stat(priv, addr); 896 addr += 0x10; 897 } 898 BDX_ASSERT(addr != 0x7330); 899 /* 0x7330-0x7360 RSRV */ 900 addr = 0x7370; 901 for (; i < 19; i++) { 902 stats_vector[i] = bdx_read_l2stat(priv, addr); 903 addr += 0x10; 904 } 905 BDX_ASSERT(addr != 0x73A0); 906 /* 0x73A0-0x73B0 RSRV */ 907 addr = 0x73C0; 908 for (; i < 23; i++) { 909 stats_vector[i] = bdx_read_l2stat(priv, addr); 910 addr += 0x10; 911 } 912 BDX_ASSERT(addr != 0x7400); 913 BDX_ASSERT((sizeof(struct bdx_stats) / sizeof(u64)) != i); 914 } 915 916 static void print_rxdd(struct rxd_desc *rxdd, u32 rxd_val1, u16 len, 917 u16 rxd_vlan); 918 static void print_rxfd(struct rxf_desc *rxfd); 919 920 /************************************************************************* 921 * Rx DB * 922 *************************************************************************/ 923 924 static void bdx_rxdb_destroy(struct rxdb *db) 925 { 926 vfree(db); 927 } 928 929 static struct rxdb *bdx_rxdb_create(int nelem) 930 { 931 struct rxdb *db; 932 int i; 933 934 db = vmalloc(sizeof(struct rxdb) 935 + (nelem * sizeof(int)) 936 + (nelem * sizeof(struct rx_map))); 937 if (likely(db != NULL)) { 938 db->stack = (int *)(db + 1); 939 db->elems = (void *)(db->stack + nelem); 940 db->nelem = nelem; 941 db->top = nelem; 942 for (i = 0; i < nelem; i++) 943 db->stack[i] = nelem - i - 1; /* to make first allocs 944 close to db struct*/ 945 } 946 947 return db; 948 } 949 950 static inline int bdx_rxdb_alloc_elem(struct rxdb *db) 951 { 952 BDX_ASSERT(db->top <= 0); 953 return db->stack[--(db->top)]; 954 } 955 956 static inline void *bdx_rxdb_addr_elem(struct rxdb *db, int n) 957 { 958 BDX_ASSERT((n < 0) || (n >= db->nelem)); 959 return db->elems + n; 960 } 961 962 static inline int bdx_rxdb_available(struct rxdb *db) 963 { 964 return db->top; 965 } 966 967 static inline void bdx_rxdb_free_elem(struct rxdb *db, int n) 968 { 969 BDX_ASSERT((n >= db->nelem) || (n < 0)); 970 db->stack[(db->top)++] = n; 971 } 972 973 /************************************************************************* 974 * Rx Init * 975 *************************************************************************/ 976 977 /* bdx_rx_init - initialize RX all related HW and SW resources 978 * @priv - NIC private structure 979 * 980 * Returns 0 on success, negative value on failure 981 * 982 * It creates rxf and rxd fifos, update relevant HW registers, preallocate 983 * skb for rx. It assumes that Rx is desabled in HW 984 * funcs are grouped for better cache usage 985 * 986 * RxD fifo is smaller than RxF fifo by design. Upon high load, RxD will be 987 * filled and packets will be dropped by nic without getting into host or 988 * cousing interrupt. Anyway, in that condition, host has no chance to process 989 * all packets, but dropping in nic is cheaper, since it takes 0 cpu cycles 990 */ 991 992 /* TBD: ensure proper packet size */ 993 994 static int bdx_rx_init(struct bdx_priv *priv) 995 { 996 ENTER; 997 998 if (bdx_fifo_init(priv, &priv->rxd_fifo0.m, priv->rxd_size, 999 regRXD_CFG0_0, regRXD_CFG1_0, 1000 regRXD_RPTR_0, regRXD_WPTR_0)) 1001 goto err_mem; 1002 if (bdx_fifo_init(priv, &priv->rxf_fifo0.m, priv->rxf_size, 1003 regRXF_CFG0_0, regRXF_CFG1_0, 1004 regRXF_RPTR_0, regRXF_WPTR_0)) 1005 goto err_mem; 1006 priv->rxdb = bdx_rxdb_create(priv->rxf_fifo0.m.memsz / 1007 sizeof(struct rxf_desc)); 1008 if (!priv->rxdb) 1009 goto err_mem; 1010 1011 priv->rxf_fifo0.m.pktsz = priv->ndev->mtu + VLAN_ETH_HLEN; 1012 return 0; 1013 1014 err_mem: 1015 netdev_err(priv->ndev, "Rx init failed\n"); 1016 return -ENOMEM; 1017 } 1018 1019 /* bdx_rx_free_skbs - frees and unmaps all skbs allocated for the fifo 1020 * @priv - NIC private structure 1021 * @f - RXF fifo 1022 */ 1023 static void bdx_rx_free_skbs(struct bdx_priv *priv, struct rxf_fifo *f) 1024 { 1025 struct rx_map *dm; 1026 struct rxdb *db = priv->rxdb; 1027 u16 i; 1028 1029 ENTER; 1030 DBG("total=%d free=%d busy=%d\n", db->nelem, bdx_rxdb_available(db), 1031 db->nelem - bdx_rxdb_available(db)); 1032 while (bdx_rxdb_available(db) > 0) { 1033 i = bdx_rxdb_alloc_elem(db); 1034 dm = bdx_rxdb_addr_elem(db, i); 1035 dm->dma = 0; 1036 } 1037 for (i = 0; i < db->nelem; i++) { 1038 dm = bdx_rxdb_addr_elem(db, i); 1039 if (dm->dma) { 1040 pci_unmap_single(priv->pdev, 1041 dm->dma, f->m.pktsz, 1042 PCI_DMA_FROMDEVICE); 1043 dev_kfree_skb(dm->skb); 1044 } 1045 } 1046 } 1047 1048 /* bdx_rx_free - release all Rx resources 1049 * @priv - NIC private structure 1050 * It assumes that Rx is desabled in HW 1051 */ 1052 static void bdx_rx_free(struct bdx_priv *priv) 1053 { 1054 ENTER; 1055 if (priv->rxdb) { 1056 bdx_rx_free_skbs(priv, &priv->rxf_fifo0); 1057 bdx_rxdb_destroy(priv->rxdb); 1058 priv->rxdb = NULL; 1059 } 1060 bdx_fifo_free(priv, &priv->rxf_fifo0.m); 1061 bdx_fifo_free(priv, &priv->rxd_fifo0.m); 1062 1063 RET(); 1064 } 1065 1066 /************************************************************************* 1067 * Rx Engine * 1068 *************************************************************************/ 1069 1070 /* bdx_rx_alloc_skbs - fill rxf fifo with new skbs 1071 * @priv - nic's private structure 1072 * @f - RXF fifo that needs skbs 1073 * It allocates skbs, build rxf descs and push it (rxf descr) into rxf fifo. 1074 * skb's virtual and physical addresses are stored in skb db. 1075 * To calculate free space, func uses cached values of RPTR and WPTR 1076 * When needed, it also updates RPTR and WPTR. 1077 */ 1078 1079 /* TBD: do not update WPTR if no desc were written */ 1080 1081 static void bdx_rx_alloc_skbs(struct bdx_priv *priv, struct rxf_fifo *f) 1082 { 1083 struct sk_buff *skb; 1084 struct rxf_desc *rxfd; 1085 struct rx_map *dm; 1086 int dno, delta, idx; 1087 struct rxdb *db = priv->rxdb; 1088 1089 ENTER; 1090 dno = bdx_rxdb_available(db) - 1; 1091 while (dno > 0) { 1092 skb = netdev_alloc_skb(priv->ndev, f->m.pktsz + NET_IP_ALIGN); 1093 if (!skb) { 1094 pr_err("NO MEM: netdev_alloc_skb failed\n"); 1095 break; 1096 } 1097 skb_reserve(skb, NET_IP_ALIGN); 1098 1099 idx = bdx_rxdb_alloc_elem(db); 1100 dm = bdx_rxdb_addr_elem(db, idx); 1101 dm->dma = pci_map_single(priv->pdev, 1102 skb->data, f->m.pktsz, 1103 PCI_DMA_FROMDEVICE); 1104 dm->skb = skb; 1105 rxfd = (struct rxf_desc *)(f->m.va + f->m.wptr); 1106 rxfd->info = CPU_CHIP_SWAP32(0x10003); /* INFO=1 BC=3 */ 1107 rxfd->va_lo = idx; 1108 rxfd->pa_lo = CPU_CHIP_SWAP32(L32_64(dm->dma)); 1109 rxfd->pa_hi = CPU_CHIP_SWAP32(H32_64(dm->dma)); 1110 rxfd->len = CPU_CHIP_SWAP32(f->m.pktsz); 1111 print_rxfd(rxfd); 1112 1113 f->m.wptr += sizeof(struct rxf_desc); 1114 delta = f->m.wptr - f->m.memsz; 1115 if (unlikely(delta >= 0)) { 1116 f->m.wptr = delta; 1117 if (delta > 0) { 1118 memcpy(f->m.va, f->m.va + f->m.memsz, delta); 1119 DBG("wrapped descriptor\n"); 1120 } 1121 } 1122 dno--; 1123 } 1124 /*TBD: to do - delayed rxf wptr like in txd */ 1125 WRITE_REG(priv, f->m.reg_WPTR, f->m.wptr & TXF_WPTR_WR_PTR); 1126 RET(); 1127 } 1128 1129 static inline void 1130 NETIF_RX_MUX(struct bdx_priv *priv, u32 rxd_val1, u16 rxd_vlan, 1131 struct sk_buff *skb) 1132 { 1133 ENTER; 1134 DBG("rxdd->flags.bits.vtag=%d\n", GET_RXD_VTAG(rxd_val1)); 1135 if (GET_RXD_VTAG(rxd_val1)) { 1136 DBG("%s: vlan rcv vlan '%x' vtag '%x'\n", 1137 priv->ndev->name, 1138 GET_RXD_VLAN_ID(rxd_vlan), 1139 GET_RXD_VTAG(rxd_val1)); 1140 __vlan_hwaccel_put_tag(skb, GET_RXD_VLAN_TCI(rxd_vlan)); 1141 } 1142 netif_receive_skb(skb); 1143 } 1144 1145 static void bdx_recycle_skb(struct bdx_priv *priv, struct rxd_desc *rxdd) 1146 { 1147 struct rxf_desc *rxfd; 1148 struct rx_map *dm; 1149 struct rxf_fifo *f; 1150 struct rxdb *db; 1151 struct sk_buff *skb; 1152 int delta; 1153 1154 ENTER; 1155 DBG("priv=%p rxdd=%p\n", priv, rxdd); 1156 f = &priv->rxf_fifo0; 1157 db = priv->rxdb; 1158 DBG("db=%p f=%p\n", db, f); 1159 dm = bdx_rxdb_addr_elem(db, rxdd->va_lo); 1160 DBG("dm=%p\n", dm); 1161 skb = dm->skb; 1162 rxfd = (struct rxf_desc *)(f->m.va + f->m.wptr); 1163 rxfd->info = CPU_CHIP_SWAP32(0x10003); /* INFO=1 BC=3 */ 1164 rxfd->va_lo = rxdd->va_lo; 1165 rxfd->pa_lo = CPU_CHIP_SWAP32(L32_64(dm->dma)); 1166 rxfd->pa_hi = CPU_CHIP_SWAP32(H32_64(dm->dma)); 1167 rxfd->len = CPU_CHIP_SWAP32(f->m.pktsz); 1168 print_rxfd(rxfd); 1169 1170 f->m.wptr += sizeof(struct rxf_desc); 1171 delta = f->m.wptr - f->m.memsz; 1172 if (unlikely(delta >= 0)) { 1173 f->m.wptr = delta; 1174 if (delta > 0) { 1175 memcpy(f->m.va, f->m.va + f->m.memsz, delta); 1176 DBG("wrapped descriptor\n"); 1177 } 1178 } 1179 RET(); 1180 } 1181 1182 /* bdx_rx_receive - receives full packets from RXD fifo and pass them to OS 1183 * NOTE: a special treatment is given to non-continuous descriptors 1184 * that start near the end, wraps around and continue at the beginning. a second 1185 * part is copied right after the first, and then descriptor is interpreted as 1186 * normal. fifo has an extra space to allow such operations 1187 * @priv - nic's private structure 1188 * @f - RXF fifo that needs skbs 1189 */ 1190 1191 /* TBD: replace memcpy func call by explicite inline asm */ 1192 1193 static int bdx_rx_receive(struct bdx_priv *priv, struct rxd_fifo *f, int budget) 1194 { 1195 struct net_device *ndev = priv->ndev; 1196 struct sk_buff *skb, *skb2; 1197 struct rxd_desc *rxdd; 1198 struct rx_map *dm; 1199 struct rxf_fifo *rxf_fifo; 1200 int tmp_len, size; 1201 int done = 0; 1202 int max_done = BDX_MAX_RX_DONE; 1203 struct rxdb *db = NULL; 1204 /* Unmarshalled descriptor - copy of descriptor in host order */ 1205 u32 rxd_val1; 1206 u16 len; 1207 u16 rxd_vlan; 1208 1209 ENTER; 1210 max_done = budget; 1211 1212 f->m.wptr = READ_REG(priv, f->m.reg_WPTR) & TXF_WPTR_WR_PTR; 1213 1214 size = f->m.wptr - f->m.rptr; 1215 if (size < 0) 1216 size = f->m.memsz + size; /* size is negative :-) */ 1217 1218 while (size > 0) { 1219 1220 rxdd = (struct rxd_desc *)(f->m.va + f->m.rptr); 1221 rxd_val1 = CPU_CHIP_SWAP32(rxdd->rxd_val1); 1222 1223 len = CPU_CHIP_SWAP16(rxdd->len); 1224 1225 rxd_vlan = CPU_CHIP_SWAP16(rxdd->rxd_vlan); 1226 1227 print_rxdd(rxdd, rxd_val1, len, rxd_vlan); 1228 1229 tmp_len = GET_RXD_BC(rxd_val1) << 3; 1230 BDX_ASSERT(tmp_len <= 0); 1231 size -= tmp_len; 1232 if (size < 0) /* test for partially arrived descriptor */ 1233 break; 1234 1235 f->m.rptr += tmp_len; 1236 1237 tmp_len = f->m.rptr - f->m.memsz; 1238 if (unlikely(tmp_len >= 0)) { 1239 f->m.rptr = tmp_len; 1240 if (tmp_len > 0) { 1241 DBG("wrapped desc rptr=%d tmp_len=%d\n", 1242 f->m.rptr, tmp_len); 1243 memcpy(f->m.va + f->m.memsz, f->m.va, tmp_len); 1244 } 1245 } 1246 1247 if (unlikely(GET_RXD_ERR(rxd_val1))) { 1248 DBG("rxd_err = 0x%x\n", GET_RXD_ERR(rxd_val1)); 1249 ndev->stats.rx_errors++; 1250 bdx_recycle_skb(priv, rxdd); 1251 continue; 1252 } 1253 1254 rxf_fifo = &priv->rxf_fifo0; 1255 db = priv->rxdb; 1256 dm = bdx_rxdb_addr_elem(db, rxdd->va_lo); 1257 skb = dm->skb; 1258 1259 if (len < BDX_COPYBREAK && 1260 (skb2 = netdev_alloc_skb(priv->ndev, len + NET_IP_ALIGN))) { 1261 skb_reserve(skb2, NET_IP_ALIGN); 1262 /*skb_put(skb2, len); */ 1263 pci_dma_sync_single_for_cpu(priv->pdev, 1264 dm->dma, rxf_fifo->m.pktsz, 1265 PCI_DMA_FROMDEVICE); 1266 memcpy(skb2->data, skb->data, len); 1267 bdx_recycle_skb(priv, rxdd); 1268 skb = skb2; 1269 } else { 1270 pci_unmap_single(priv->pdev, 1271 dm->dma, rxf_fifo->m.pktsz, 1272 PCI_DMA_FROMDEVICE); 1273 bdx_rxdb_free_elem(db, rxdd->va_lo); 1274 } 1275 1276 ndev->stats.rx_bytes += len; 1277 1278 skb_put(skb, len); 1279 skb->protocol = eth_type_trans(skb, ndev); 1280 1281 /* Non-IP packets aren't checksum-offloaded */ 1282 if (GET_RXD_PKT_ID(rxd_val1) == 0) 1283 skb_checksum_none_assert(skb); 1284 else 1285 skb->ip_summed = CHECKSUM_UNNECESSARY; 1286 1287 NETIF_RX_MUX(priv, rxd_val1, rxd_vlan, skb); 1288 1289 if (++done >= max_done) 1290 break; 1291 } 1292 1293 ndev->stats.rx_packets += done; 1294 1295 /* FIXME: do smth to minimize pci accesses */ 1296 WRITE_REG(priv, f->m.reg_RPTR, f->m.rptr & TXF_WPTR_WR_PTR); 1297 1298 bdx_rx_alloc_skbs(priv, &priv->rxf_fifo0); 1299 1300 RET(done); 1301 } 1302 1303 /************************************************************************* 1304 * Debug / Temprorary Code * 1305 *************************************************************************/ 1306 static void print_rxdd(struct rxd_desc *rxdd, u32 rxd_val1, u16 len, 1307 u16 rxd_vlan) 1308 { 1309 DBG("ERROR: rxdd bc %d rxfq %d to %d type %d err %d rxp %d pkt_id %d vtag %d len %d vlan_id %d cfi %d prio %d va_lo %d va_hi %d\n", 1310 GET_RXD_BC(rxd_val1), GET_RXD_RXFQ(rxd_val1), GET_RXD_TO(rxd_val1), 1311 GET_RXD_TYPE(rxd_val1), GET_RXD_ERR(rxd_val1), 1312 GET_RXD_RXP(rxd_val1), GET_RXD_PKT_ID(rxd_val1), 1313 GET_RXD_VTAG(rxd_val1), len, GET_RXD_VLAN_ID(rxd_vlan), 1314 GET_RXD_CFI(rxd_vlan), GET_RXD_PRIO(rxd_vlan), rxdd->va_lo, 1315 rxdd->va_hi); 1316 } 1317 1318 static void print_rxfd(struct rxf_desc *rxfd) 1319 { 1320 DBG("=== RxF desc CHIP ORDER/ENDIANNESS =============\n" 1321 "info 0x%x va_lo %u pa_lo 0x%x pa_hi 0x%x len 0x%x\n", 1322 rxfd->info, rxfd->va_lo, rxfd->pa_lo, rxfd->pa_hi, rxfd->len); 1323 } 1324 1325 /* 1326 * TX HW/SW interaction overview 1327 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1328 * There are 2 types of TX communication channels between driver and NIC. 1329 * 1) TX Free Fifo - TXF - holds ack descriptors for sent packets 1330 * 2) TX Data Fifo - TXD - holds descriptors of full buffers. 1331 * 1332 * Currently NIC supports TSO, checksuming and gather DMA 1333 * UFO and IP fragmentation is on the way 1334 * 1335 * RX SW Data Structures 1336 * ~~~~~~~~~~~~~~~~~~~~~ 1337 * txdb - used to keep track of all skbs owned by SW and their dma addresses. 1338 * For TX case, ownership lasts from geting packet via hard_xmit and until HW 1339 * acknowledges sent by TXF descriptors. 1340 * Implemented as cyclic buffer. 1341 * fifo - keeps info about fifo's size and location, relevant HW registers, 1342 * usage and skb db. Each RXD and RXF Fifo has its own fifo structure. 1343 * Implemented as simple struct. 1344 * 1345 * TX SW Execution Flow 1346 * ~~~~~~~~~~~~~~~~~~~~ 1347 * OS calls driver's hard_xmit method with packet to sent. 1348 * Driver creates DMA mappings, builds TXD descriptors and kicks HW 1349 * by updating TXD WPTR. 1350 * When packet is sent, HW write us TXF descriptor and SW frees original skb. 1351 * To prevent TXD fifo overflow without reading HW registers every time, 1352 * SW deploys "tx level" technique. 1353 * Upon strart up, tx level is initialized to TXD fifo length. 1354 * For every sent packet, SW gets its TXD descriptor sizei 1355 * (from precalculated array) and substructs it from tx level. 1356 * The size is also stored in txdb. When TXF ack arrives, SW fetch size of 1357 * original TXD descriptor from txdb and adds it to tx level. 1358 * When Tx level drops under some predefined treshhold, the driver 1359 * stops the TX queue. When TX level rises above that level, 1360 * the tx queue is enabled again. 1361 * 1362 * This technique avoids eccessive reading of RPTR and WPTR registers. 1363 * As our benchmarks shows, it adds 1.5 Gbit/sec to NIS's throuput. 1364 */ 1365 1366 /************************************************************************* 1367 * Tx DB * 1368 *************************************************************************/ 1369 static inline int bdx_tx_db_size(struct txdb *db) 1370 { 1371 int taken = db->wptr - db->rptr; 1372 if (taken < 0) 1373 taken = db->size + 1 + taken; /* (size + 1) equals memsz */ 1374 1375 return db->size - taken; 1376 } 1377 1378 /* __bdx_tx_ptr_next - helper function, increment read/write pointer + wrap 1379 * @d - tx data base 1380 * @ptr - read or write pointer 1381 */ 1382 static inline void __bdx_tx_db_ptr_next(struct txdb *db, struct tx_map **pptr) 1383 { 1384 BDX_ASSERT(db == NULL || pptr == NULL); /* sanity */ 1385 1386 BDX_ASSERT(*pptr != db->rptr && /* expect either read */ 1387 *pptr != db->wptr); /* or write pointer */ 1388 1389 BDX_ASSERT(*pptr < db->start || /* pointer has to be */ 1390 *pptr >= db->end); /* in range */ 1391 1392 ++*pptr; 1393 if (unlikely(*pptr == db->end)) 1394 *pptr = db->start; 1395 } 1396 1397 /* bdx_tx_db_inc_rptr - increment read pointer 1398 * @d - tx data base 1399 */ 1400 static inline void bdx_tx_db_inc_rptr(struct txdb *db) 1401 { 1402 BDX_ASSERT(db->rptr == db->wptr); /* can't read from empty db */ 1403 __bdx_tx_db_ptr_next(db, &db->rptr); 1404 } 1405 1406 /* bdx_tx_db_inc_rptr - increment write pointer 1407 * @d - tx data base 1408 */ 1409 static inline void bdx_tx_db_inc_wptr(struct txdb *db) 1410 { 1411 __bdx_tx_db_ptr_next(db, &db->wptr); 1412 BDX_ASSERT(db->rptr == db->wptr); /* we can not get empty db as 1413 a result of write */ 1414 } 1415 1416 /* bdx_tx_db_init - creates and initializes tx db 1417 * @d - tx data base 1418 * @sz_type - size of tx fifo 1419 * Returns 0 on success, error code otherwise 1420 */ 1421 static int bdx_tx_db_init(struct txdb *d, int sz_type) 1422 { 1423 int memsz = FIFO_SIZE * (1 << (sz_type + 1)); 1424 1425 d->start = vmalloc(memsz); 1426 if (!d->start) 1427 return -ENOMEM; 1428 1429 /* 1430 * In order to differentiate between db is empty and db is full 1431 * states at least one element should always be empty in order to 1432 * avoid rptr == wptr which means db is empty 1433 */ 1434 d->size = memsz / sizeof(struct tx_map) - 1; 1435 d->end = d->start + d->size + 1; /* just after last element */ 1436 1437 /* all dbs are created equally empty */ 1438 d->rptr = d->start; 1439 d->wptr = d->start; 1440 1441 return 0; 1442 } 1443 1444 /* bdx_tx_db_close - closes tx db and frees all memory 1445 * @d - tx data base 1446 */ 1447 static void bdx_tx_db_close(struct txdb *d) 1448 { 1449 BDX_ASSERT(d == NULL); 1450 1451 vfree(d->start); 1452 d->start = NULL; 1453 } 1454 1455 /************************************************************************* 1456 * Tx Engine * 1457 *************************************************************************/ 1458 1459 /* sizes of tx desc (including padding if needed) as function 1460 * of skb's frag number */ 1461 static struct { 1462 u16 bytes; 1463 u16 qwords; /* qword = 64 bit */ 1464 } txd_sizes[MAX_SKB_FRAGS + 1]; 1465 1466 /* txdb_map_skb - creates and stores dma mappings for skb's data blocks 1467 * @priv - NIC private structure 1468 * @skb - socket buffer to map 1469 * 1470 * It makes dma mappings for skb's data blocks and writes them to PBL of 1471 * new tx descriptor. It also stores them in the tx db, so they could be 1472 * unmaped after data was sent. It is reponsibility of a caller to make 1473 * sure that there is enough space in the tx db. Last element holds pointer 1474 * to skb itself and marked with zero length 1475 */ 1476 static inline void 1477 bdx_tx_map_skb(struct bdx_priv *priv, struct sk_buff *skb, 1478 struct txd_desc *txdd) 1479 { 1480 struct txdb *db = &priv->txdb; 1481 struct pbl *pbl = &txdd->pbl[0]; 1482 int nr_frags = skb_shinfo(skb)->nr_frags; 1483 int i; 1484 1485 db->wptr->len = skb_headlen(skb); 1486 db->wptr->addr.dma = pci_map_single(priv->pdev, skb->data, 1487 db->wptr->len, PCI_DMA_TODEVICE); 1488 pbl->len = CPU_CHIP_SWAP32(db->wptr->len); 1489 pbl->pa_lo = CPU_CHIP_SWAP32(L32_64(db->wptr->addr.dma)); 1490 pbl->pa_hi = CPU_CHIP_SWAP32(H32_64(db->wptr->addr.dma)); 1491 DBG("=== pbl len: 0x%x ================\n", pbl->len); 1492 DBG("=== pbl pa_lo: 0x%x ================\n", pbl->pa_lo); 1493 DBG("=== pbl pa_hi: 0x%x ================\n", pbl->pa_hi); 1494 bdx_tx_db_inc_wptr(db); 1495 1496 for (i = 0; i < nr_frags; i++) { 1497 const struct skb_frag_struct *frag; 1498 1499 frag = &skb_shinfo(skb)->frags[i]; 1500 db->wptr->len = skb_frag_size(frag); 1501 db->wptr->addr.dma = skb_frag_dma_map(&priv->pdev->dev, frag, 1502 0, skb_frag_size(frag), 1503 DMA_TO_DEVICE); 1504 1505 pbl++; 1506 pbl->len = CPU_CHIP_SWAP32(db->wptr->len); 1507 pbl->pa_lo = CPU_CHIP_SWAP32(L32_64(db->wptr->addr.dma)); 1508 pbl->pa_hi = CPU_CHIP_SWAP32(H32_64(db->wptr->addr.dma)); 1509 bdx_tx_db_inc_wptr(db); 1510 } 1511 1512 /* add skb clean up info. */ 1513 db->wptr->len = -txd_sizes[nr_frags].bytes; 1514 db->wptr->addr.skb = skb; 1515 bdx_tx_db_inc_wptr(db); 1516 } 1517 1518 /* init_txd_sizes - precalculate sizes of descriptors for skbs up to 16 frags 1519 * number of frags is used as index to fetch correct descriptors size, 1520 * instead of calculating it each time */ 1521 static void __init init_txd_sizes(void) 1522 { 1523 int i, lwords; 1524 1525 /* 7 - is number of lwords in txd with one phys buffer 1526 * 3 - is number of lwords used for every additional phys buffer */ 1527 for (i = 0; i < MAX_SKB_FRAGS + 1; i++) { 1528 lwords = 7 + (i * 3); 1529 if (lwords & 1) 1530 lwords++; /* pad it with 1 lword */ 1531 txd_sizes[i].qwords = lwords >> 1; 1532 txd_sizes[i].bytes = lwords << 2; 1533 } 1534 } 1535 1536 /* bdx_tx_init - initialize all Tx related stuff. 1537 * Namely, TXD and TXF fifos, database etc */ 1538 static int bdx_tx_init(struct bdx_priv *priv) 1539 { 1540 if (bdx_fifo_init(priv, &priv->txd_fifo0.m, priv->txd_size, 1541 regTXD_CFG0_0, 1542 regTXD_CFG1_0, regTXD_RPTR_0, regTXD_WPTR_0)) 1543 goto err_mem; 1544 if (bdx_fifo_init(priv, &priv->txf_fifo0.m, priv->txf_size, 1545 regTXF_CFG0_0, 1546 regTXF_CFG1_0, regTXF_RPTR_0, regTXF_WPTR_0)) 1547 goto err_mem; 1548 1549 /* The TX db has to keep mappings for all packets sent (on TxD) 1550 * and not yet reclaimed (on TxF) */ 1551 if (bdx_tx_db_init(&priv->txdb, max(priv->txd_size, priv->txf_size))) 1552 goto err_mem; 1553 1554 priv->tx_level = BDX_MAX_TX_LEVEL; 1555 #ifdef BDX_DELAY_WPTR 1556 priv->tx_update_mark = priv->tx_level - 1024; 1557 #endif 1558 return 0; 1559 1560 err_mem: 1561 netdev_err(priv->ndev, "Tx init failed\n"); 1562 return -ENOMEM; 1563 } 1564 1565 /* 1566 * bdx_tx_space - calculates available space in TX fifo 1567 * @priv - NIC private structure 1568 * Returns available space in TX fifo in bytes 1569 */ 1570 static inline int bdx_tx_space(struct bdx_priv *priv) 1571 { 1572 struct txd_fifo *f = &priv->txd_fifo0; 1573 int fsize; 1574 1575 f->m.rptr = READ_REG(priv, f->m.reg_RPTR) & TXF_WPTR_WR_PTR; 1576 fsize = f->m.rptr - f->m.wptr; 1577 if (fsize <= 0) 1578 fsize = f->m.memsz + fsize; 1579 return fsize; 1580 } 1581 1582 /* bdx_tx_transmit - send packet to NIC 1583 * @skb - packet to send 1584 * ndev - network device assigned to NIC 1585 * Return codes: 1586 * o NETDEV_TX_OK everything ok. 1587 * o NETDEV_TX_BUSY Cannot transmit packet, try later 1588 * Usually a bug, means queue start/stop flow control is broken in 1589 * the driver. Note: the driver must NOT put the skb in its DMA ring. 1590 * o NETDEV_TX_LOCKED Locking failed, please retry quickly. 1591 */ 1592 static netdev_tx_t bdx_tx_transmit(struct sk_buff *skb, 1593 struct net_device *ndev) 1594 { 1595 struct bdx_priv *priv = netdev_priv(ndev); 1596 struct txd_fifo *f = &priv->txd_fifo0; 1597 int txd_checksum = 7; /* full checksum */ 1598 int txd_lgsnd = 0; 1599 int txd_vlan_id = 0; 1600 int txd_vtag = 0; 1601 int txd_mss = 0; 1602 1603 int nr_frags = skb_shinfo(skb)->nr_frags; 1604 struct txd_desc *txdd; 1605 int len; 1606 unsigned long flags; 1607 1608 ENTER; 1609 local_irq_save(flags); 1610 if (!spin_trylock(&priv->tx_lock)) { 1611 local_irq_restore(flags); 1612 DBG("%s[%s]: TX locked, returning NETDEV_TX_LOCKED\n", 1613 BDX_DRV_NAME, ndev->name); 1614 return NETDEV_TX_LOCKED; 1615 } 1616 1617 /* build tx descriptor */ 1618 BDX_ASSERT(f->m.wptr >= f->m.memsz); /* started with valid wptr */ 1619 txdd = (struct txd_desc *)(f->m.va + f->m.wptr); 1620 if (unlikely(skb->ip_summed != CHECKSUM_PARTIAL)) 1621 txd_checksum = 0; 1622 1623 if (skb_shinfo(skb)->gso_size) { 1624 txd_mss = skb_shinfo(skb)->gso_size; 1625 txd_lgsnd = 1; 1626 DBG("skb %p skb len %d gso size = %d\n", skb, skb->len, 1627 txd_mss); 1628 } 1629 1630 if (vlan_tx_tag_present(skb)) { 1631 /*Cut VLAN ID to 12 bits */ 1632 txd_vlan_id = vlan_tx_tag_get(skb) & BITS_MASK(12); 1633 txd_vtag = 1; 1634 } 1635 1636 txdd->length = CPU_CHIP_SWAP16(skb->len); 1637 txdd->mss = CPU_CHIP_SWAP16(txd_mss); 1638 txdd->txd_val1 = 1639 CPU_CHIP_SWAP32(TXD_W1_VAL 1640 (txd_sizes[nr_frags].qwords, txd_checksum, txd_vtag, 1641 txd_lgsnd, txd_vlan_id)); 1642 DBG("=== TxD desc =====================\n"); 1643 DBG("=== w1: 0x%x ================\n", txdd->txd_val1); 1644 DBG("=== w2: mss 0x%x len 0x%x\n", txdd->mss, txdd->length); 1645 1646 bdx_tx_map_skb(priv, skb, txdd); 1647 1648 /* increment TXD write pointer. In case of 1649 fifo wrapping copy reminder of the descriptor 1650 to the beginning */ 1651 f->m.wptr += txd_sizes[nr_frags].bytes; 1652 len = f->m.wptr - f->m.memsz; 1653 if (unlikely(len >= 0)) { 1654 f->m.wptr = len; 1655 if (len > 0) { 1656 BDX_ASSERT(len > f->m.memsz); 1657 memcpy(f->m.va, f->m.va + f->m.memsz, len); 1658 } 1659 } 1660 BDX_ASSERT(f->m.wptr >= f->m.memsz); /* finished with valid wptr */ 1661 1662 priv->tx_level -= txd_sizes[nr_frags].bytes; 1663 BDX_ASSERT(priv->tx_level <= 0 || priv->tx_level > BDX_MAX_TX_LEVEL); 1664 #ifdef BDX_DELAY_WPTR 1665 if (priv->tx_level > priv->tx_update_mark) { 1666 /* Force memory writes to complete before letting h/w 1667 know there are new descriptors to fetch. 1668 (might be needed on platforms like IA64) 1669 wmb(); */ 1670 WRITE_REG(priv, f->m.reg_WPTR, f->m.wptr & TXF_WPTR_WR_PTR); 1671 } else { 1672 if (priv->tx_noupd++ > BDX_NO_UPD_PACKETS) { 1673 priv->tx_noupd = 0; 1674 WRITE_REG(priv, f->m.reg_WPTR, 1675 f->m.wptr & TXF_WPTR_WR_PTR); 1676 } 1677 } 1678 #else 1679 /* Force memory writes to complete before letting h/w 1680 know there are new descriptors to fetch. 1681 (might be needed on platforms like IA64) 1682 wmb(); */ 1683 WRITE_REG(priv, f->m.reg_WPTR, f->m.wptr & TXF_WPTR_WR_PTR); 1684 1685 #endif 1686 #ifdef BDX_LLTX 1687 ndev->trans_start = jiffies; /* NETIF_F_LLTX driver :( */ 1688 #endif 1689 ndev->stats.tx_packets++; 1690 ndev->stats.tx_bytes += skb->len; 1691 1692 if (priv->tx_level < BDX_MIN_TX_LEVEL) { 1693 DBG("%s: %s: TX Q STOP level %d\n", 1694 BDX_DRV_NAME, ndev->name, priv->tx_level); 1695 netif_stop_queue(ndev); 1696 } 1697 1698 spin_unlock_irqrestore(&priv->tx_lock, flags); 1699 return NETDEV_TX_OK; 1700 } 1701 1702 /* bdx_tx_cleanup - clean TXF fifo, run in the context of IRQ. 1703 * @priv - bdx adapter 1704 * It scans TXF fifo for descriptors, frees DMA mappings and reports to OS 1705 * that those packets were sent 1706 */ 1707 static void bdx_tx_cleanup(struct bdx_priv *priv) 1708 { 1709 struct txf_fifo *f = &priv->txf_fifo0; 1710 struct txdb *db = &priv->txdb; 1711 int tx_level = 0; 1712 1713 ENTER; 1714 f->m.wptr = READ_REG(priv, f->m.reg_WPTR) & TXF_WPTR_MASK; 1715 BDX_ASSERT(f->m.rptr >= f->m.memsz); /* started with valid rptr */ 1716 1717 while (f->m.wptr != f->m.rptr) { 1718 f->m.rptr += BDX_TXF_DESC_SZ; 1719 f->m.rptr &= f->m.size_mask; 1720 1721 /* unmap all the fragments */ 1722 /* first has to come tx_maps containing dma */ 1723 BDX_ASSERT(db->rptr->len == 0); 1724 do { 1725 BDX_ASSERT(db->rptr->addr.dma == 0); 1726 pci_unmap_page(priv->pdev, db->rptr->addr.dma, 1727 db->rptr->len, PCI_DMA_TODEVICE); 1728 bdx_tx_db_inc_rptr(db); 1729 } while (db->rptr->len > 0); 1730 tx_level -= db->rptr->len; /* '-' koz len is negative */ 1731 1732 /* now should come skb pointer - free it */ 1733 dev_kfree_skb_irq(db->rptr->addr.skb); 1734 bdx_tx_db_inc_rptr(db); 1735 } 1736 1737 /* let h/w know which TXF descriptors were cleaned */ 1738 BDX_ASSERT((f->m.wptr & TXF_WPTR_WR_PTR) >= f->m.memsz); 1739 WRITE_REG(priv, f->m.reg_RPTR, f->m.rptr & TXF_WPTR_WR_PTR); 1740 1741 /* We reclaimed resources, so in case the Q is stopped by xmit callback, 1742 * we resume the transmition and use tx_lock to synchronize with xmit.*/ 1743 spin_lock(&priv->tx_lock); 1744 priv->tx_level += tx_level; 1745 BDX_ASSERT(priv->tx_level <= 0 || priv->tx_level > BDX_MAX_TX_LEVEL); 1746 #ifdef BDX_DELAY_WPTR 1747 if (priv->tx_noupd) { 1748 priv->tx_noupd = 0; 1749 WRITE_REG(priv, priv->txd_fifo0.m.reg_WPTR, 1750 priv->txd_fifo0.m.wptr & TXF_WPTR_WR_PTR); 1751 } 1752 #endif 1753 1754 if (unlikely(netif_queue_stopped(priv->ndev) && 1755 netif_carrier_ok(priv->ndev) && 1756 (priv->tx_level >= BDX_MIN_TX_LEVEL))) { 1757 DBG("%s: %s: TX Q WAKE level %d\n", 1758 BDX_DRV_NAME, priv->ndev->name, priv->tx_level); 1759 netif_wake_queue(priv->ndev); 1760 } 1761 spin_unlock(&priv->tx_lock); 1762 } 1763 1764 /* bdx_tx_free_skbs - frees all skbs from TXD fifo. 1765 * It gets called when OS stops this dev, eg upon "ifconfig down" or rmmod 1766 */ 1767 static void bdx_tx_free_skbs(struct bdx_priv *priv) 1768 { 1769 struct txdb *db = &priv->txdb; 1770 1771 ENTER; 1772 while (db->rptr != db->wptr) { 1773 if (likely(db->rptr->len)) 1774 pci_unmap_page(priv->pdev, db->rptr->addr.dma, 1775 db->rptr->len, PCI_DMA_TODEVICE); 1776 else 1777 dev_kfree_skb(db->rptr->addr.skb); 1778 bdx_tx_db_inc_rptr(db); 1779 } 1780 RET(); 1781 } 1782 1783 /* bdx_tx_free - frees all Tx resources */ 1784 static void bdx_tx_free(struct bdx_priv *priv) 1785 { 1786 ENTER; 1787 bdx_tx_free_skbs(priv); 1788 bdx_fifo_free(priv, &priv->txd_fifo0.m); 1789 bdx_fifo_free(priv, &priv->txf_fifo0.m); 1790 bdx_tx_db_close(&priv->txdb); 1791 } 1792 1793 /* bdx_tx_push_desc - push descriptor to TxD fifo 1794 * @priv - NIC private structure 1795 * @data - desc's data 1796 * @size - desc's size 1797 * 1798 * Pushes desc to TxD fifo and overlaps it if needed. 1799 * NOTE: this func does not check for available space. this is responsibility 1800 * of the caller. Neither does it check that data size is smaller than 1801 * fifo size. 1802 */ 1803 static void bdx_tx_push_desc(struct bdx_priv *priv, void *data, int size) 1804 { 1805 struct txd_fifo *f = &priv->txd_fifo0; 1806 int i = f->m.memsz - f->m.wptr; 1807 1808 if (size == 0) 1809 return; 1810 1811 if (i > size) { 1812 memcpy(f->m.va + f->m.wptr, data, size); 1813 f->m.wptr += size; 1814 } else { 1815 memcpy(f->m.va + f->m.wptr, data, i); 1816 f->m.wptr = size - i; 1817 memcpy(f->m.va, data + i, f->m.wptr); 1818 } 1819 WRITE_REG(priv, f->m.reg_WPTR, f->m.wptr & TXF_WPTR_WR_PTR); 1820 } 1821 1822 /* bdx_tx_push_desc_safe - push descriptor to TxD fifo in a safe way 1823 * @priv - NIC private structure 1824 * @data - desc's data 1825 * @size - desc's size 1826 * 1827 * NOTE: this func does check for available space and, if necessary, waits for 1828 * NIC to read existing data before writing new one. 1829 */ 1830 static void bdx_tx_push_desc_safe(struct bdx_priv *priv, void *data, int size) 1831 { 1832 int timer = 0; 1833 ENTER; 1834 1835 while (size > 0) { 1836 /* we substruct 8 because when fifo is full rptr == wptr 1837 which also means that fifo is empty, we can understand 1838 the difference, but could hw do the same ??? :) */ 1839 int avail = bdx_tx_space(priv) - 8; 1840 if (avail <= 0) { 1841 if (timer++ > 300) { /* prevent endless loop */ 1842 DBG("timeout while writing desc to TxD fifo\n"); 1843 break; 1844 } 1845 udelay(50); /* give hw a chance to clean fifo */ 1846 continue; 1847 } 1848 avail = min(avail, size); 1849 DBG("about to push %d bytes starting %p size %d\n", avail, 1850 data, size); 1851 bdx_tx_push_desc(priv, data, avail); 1852 size -= avail; 1853 data += avail; 1854 } 1855 RET(); 1856 } 1857 1858 static const struct net_device_ops bdx_netdev_ops = { 1859 .ndo_open = bdx_open, 1860 .ndo_stop = bdx_close, 1861 .ndo_start_xmit = bdx_tx_transmit, 1862 .ndo_validate_addr = eth_validate_addr, 1863 .ndo_do_ioctl = bdx_ioctl, 1864 .ndo_set_rx_mode = bdx_setmulti, 1865 .ndo_change_mtu = bdx_change_mtu, 1866 .ndo_set_mac_address = bdx_set_mac, 1867 .ndo_vlan_rx_add_vid = bdx_vlan_rx_add_vid, 1868 .ndo_vlan_rx_kill_vid = bdx_vlan_rx_kill_vid, 1869 }; 1870 1871 /** 1872 * bdx_probe - Device Initialization Routine 1873 * @pdev: PCI device information struct 1874 * @ent: entry in bdx_pci_tbl 1875 * 1876 * Returns 0 on success, negative on failure 1877 * 1878 * bdx_probe initializes an adapter identified by a pci_dev structure. 1879 * The OS initialization, configuring of the adapter private structure, 1880 * and a hardware reset occur. 1881 * 1882 * functions and their order used as explained in 1883 * /usr/src/linux/Documentation/DMA-{API,mapping}.txt 1884 * 1885 */ 1886 1887 /* TBD: netif_msg should be checked and implemented. I disable it for now */ 1888 static int __devinit 1889 bdx_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 1890 { 1891 struct net_device *ndev; 1892 struct bdx_priv *priv; 1893 int err, pci_using_dac, port; 1894 unsigned long pciaddr; 1895 u32 regionSize; 1896 struct pci_nic *nic; 1897 1898 ENTER; 1899 1900 nic = vmalloc(sizeof(*nic)); 1901 if (!nic) 1902 RET(-ENOMEM); 1903 1904 /************** pci *****************/ 1905 err = pci_enable_device(pdev); 1906 if (err) /* it triggers interrupt, dunno why. */ 1907 goto err_pci; /* it's not a problem though */ 1908 1909 if (!(err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) && 1910 !(err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)))) { 1911 pci_using_dac = 1; 1912 } else { 1913 if ((err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) || 1914 (err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)))) { 1915 pr_err("No usable DMA configuration, aborting\n"); 1916 goto err_dma; 1917 } 1918 pci_using_dac = 0; 1919 } 1920 1921 err = pci_request_regions(pdev, BDX_DRV_NAME); 1922 if (err) 1923 goto err_dma; 1924 1925 pci_set_master(pdev); 1926 1927 pciaddr = pci_resource_start(pdev, 0); 1928 if (!pciaddr) { 1929 err = -EIO; 1930 pr_err("no MMIO resource\n"); 1931 goto err_out_res; 1932 } 1933 regionSize = pci_resource_len(pdev, 0); 1934 if (regionSize < BDX_REGS_SIZE) { 1935 err = -EIO; 1936 pr_err("MMIO resource (%x) too small\n", regionSize); 1937 goto err_out_res; 1938 } 1939 1940 nic->regs = ioremap(pciaddr, regionSize); 1941 if (!nic->regs) { 1942 err = -EIO; 1943 pr_err("ioremap failed\n"); 1944 goto err_out_res; 1945 } 1946 1947 if (pdev->irq < 2) { 1948 err = -EIO; 1949 pr_err("invalid irq (%d)\n", pdev->irq); 1950 goto err_out_iomap; 1951 } 1952 pci_set_drvdata(pdev, nic); 1953 1954 if (pdev->device == 0x3014) 1955 nic->port_num = 2; 1956 else 1957 nic->port_num = 1; 1958 1959 print_hw_id(pdev); 1960 1961 bdx_hw_reset_direct(nic->regs); 1962 1963 nic->irq_type = IRQ_INTX; 1964 #ifdef BDX_MSI 1965 if ((readl(nic->regs + FPGA_VER) & 0xFFF) >= 378) { 1966 err = pci_enable_msi(pdev); 1967 if (err) 1968 pr_err("Can't eneble msi. error is %d\n", err); 1969 else 1970 nic->irq_type = IRQ_MSI; 1971 } else 1972 DBG("HW does not support MSI\n"); 1973 #endif 1974 1975 /************** netdev **************/ 1976 for (port = 0; port < nic->port_num; port++) { 1977 ndev = alloc_etherdev(sizeof(struct bdx_priv)); 1978 if (!ndev) { 1979 err = -ENOMEM; 1980 goto err_out_iomap; 1981 } 1982 1983 ndev->netdev_ops = &bdx_netdev_ops; 1984 ndev->tx_queue_len = BDX_NDEV_TXQ_LEN; 1985 1986 bdx_set_ethtool_ops(ndev); /* ethtool interface */ 1987 1988 /* these fields are used for info purposes only 1989 * so we can have them same for all ports of the board */ 1990 ndev->if_port = port; 1991 ndev->features = NETIF_F_IP_CSUM | NETIF_F_SG | NETIF_F_TSO 1992 | NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX | 1993 NETIF_F_HW_VLAN_FILTER | NETIF_F_RXCSUM 1994 /*| NETIF_F_FRAGLIST */ 1995 ; 1996 ndev->hw_features = NETIF_F_IP_CSUM | NETIF_F_SG | 1997 NETIF_F_TSO | NETIF_F_HW_VLAN_TX; 1998 1999 if (pci_using_dac) 2000 ndev->features |= NETIF_F_HIGHDMA; 2001 2002 /************** priv ****************/ 2003 priv = nic->priv[port] = netdev_priv(ndev); 2004 2005 priv->pBdxRegs = nic->regs + port * 0x8000; 2006 priv->port = port; 2007 priv->pdev = pdev; 2008 priv->ndev = ndev; 2009 priv->nic = nic; 2010 priv->msg_enable = BDX_DEF_MSG_ENABLE; 2011 2012 netif_napi_add(ndev, &priv->napi, bdx_poll, 64); 2013 2014 if ((readl(nic->regs + FPGA_VER) & 0xFFF) == 308) { 2015 DBG("HW statistics not supported\n"); 2016 priv->stats_flag = 0; 2017 } else { 2018 priv->stats_flag = 1; 2019 } 2020 2021 /* Initialize fifo sizes. */ 2022 priv->txd_size = 2; 2023 priv->txf_size = 2; 2024 priv->rxd_size = 2; 2025 priv->rxf_size = 3; 2026 2027 /* Initialize the initial coalescing registers. */ 2028 priv->rdintcm = INT_REG_VAL(0x20, 1, 4, 12); 2029 priv->tdintcm = INT_REG_VAL(0x20, 1, 0, 12); 2030 2031 /* ndev->xmit_lock spinlock is not used. 2032 * Private priv->tx_lock is used for synchronization 2033 * between transmit and TX irq cleanup. In addition 2034 * set multicast list callback has to use priv->tx_lock. 2035 */ 2036 #ifdef BDX_LLTX 2037 ndev->features |= NETIF_F_LLTX; 2038 #endif 2039 spin_lock_init(&priv->tx_lock); 2040 2041 /*bdx_hw_reset(priv); */ 2042 if (bdx_read_mac(priv)) { 2043 pr_err("load MAC address failed\n"); 2044 goto err_out_iomap; 2045 } 2046 SET_NETDEV_DEV(ndev, &pdev->dev); 2047 err = register_netdev(ndev); 2048 if (err) { 2049 pr_err("register_netdev failed\n"); 2050 goto err_out_free; 2051 } 2052 netif_carrier_off(ndev); 2053 netif_stop_queue(ndev); 2054 2055 print_eth_id(ndev); 2056 } 2057 RET(0); 2058 2059 err_out_free: 2060 free_netdev(ndev); 2061 err_out_iomap: 2062 iounmap(nic->regs); 2063 err_out_res: 2064 pci_release_regions(pdev); 2065 err_dma: 2066 pci_disable_device(pdev); 2067 err_pci: 2068 vfree(nic); 2069 2070 RET(err); 2071 } 2072 2073 /****************** Ethtool interface *********************/ 2074 /* get strings for statistics counters */ 2075 static const char 2076 bdx_stat_names[][ETH_GSTRING_LEN] = { 2077 "InUCast", /* 0x7200 */ 2078 "InMCast", /* 0x7210 */ 2079 "InBCast", /* 0x7220 */ 2080 "InPkts", /* 0x7230 */ 2081 "InErrors", /* 0x7240 */ 2082 "InDropped", /* 0x7250 */ 2083 "FrameTooLong", /* 0x7260 */ 2084 "FrameSequenceErrors", /* 0x7270 */ 2085 "InVLAN", /* 0x7280 */ 2086 "InDroppedDFE", /* 0x7290 */ 2087 "InDroppedIntFull", /* 0x72A0 */ 2088 "InFrameAlignErrors", /* 0x72B0 */ 2089 2090 /* 0x72C0-0x72E0 RSRV */ 2091 2092 "OutUCast", /* 0x72F0 */ 2093 "OutMCast", /* 0x7300 */ 2094 "OutBCast", /* 0x7310 */ 2095 "OutPkts", /* 0x7320 */ 2096 2097 /* 0x7330-0x7360 RSRV */ 2098 2099 "OutVLAN", /* 0x7370 */ 2100 "InUCastOctects", /* 0x7380 */ 2101 "OutUCastOctects", /* 0x7390 */ 2102 2103 /* 0x73A0-0x73B0 RSRV */ 2104 2105 "InBCastOctects", /* 0x73C0 */ 2106 "OutBCastOctects", /* 0x73D0 */ 2107 "InOctects", /* 0x73E0 */ 2108 "OutOctects", /* 0x73F0 */ 2109 }; 2110 2111 /* 2112 * bdx_get_settings - get device-specific settings 2113 * @netdev 2114 * @ecmd 2115 */ 2116 static int bdx_get_settings(struct net_device *netdev, struct ethtool_cmd *ecmd) 2117 { 2118 u32 rdintcm; 2119 u32 tdintcm; 2120 struct bdx_priv *priv = netdev_priv(netdev); 2121 2122 rdintcm = priv->rdintcm; 2123 tdintcm = priv->tdintcm; 2124 2125 ecmd->supported = (SUPPORTED_10000baseT_Full | SUPPORTED_FIBRE); 2126 ecmd->advertising = (ADVERTISED_10000baseT_Full | ADVERTISED_FIBRE); 2127 ethtool_cmd_speed_set(ecmd, SPEED_10000); 2128 ecmd->duplex = DUPLEX_FULL; 2129 ecmd->port = PORT_FIBRE; 2130 ecmd->transceiver = XCVR_EXTERNAL; /* what does it mean? */ 2131 ecmd->autoneg = AUTONEG_DISABLE; 2132 2133 /* PCK_TH measures in multiples of FIFO bytes 2134 We translate to packets */ 2135 ecmd->maxtxpkt = 2136 ((GET_PCK_TH(tdintcm) * PCK_TH_MULT) / BDX_TXF_DESC_SZ); 2137 ecmd->maxrxpkt = 2138 ((GET_PCK_TH(rdintcm) * PCK_TH_MULT) / sizeof(struct rxf_desc)); 2139 2140 return 0; 2141 } 2142 2143 /* 2144 * bdx_get_drvinfo - report driver information 2145 * @netdev 2146 * @drvinfo 2147 */ 2148 static void 2149 bdx_get_drvinfo(struct net_device *netdev, struct ethtool_drvinfo *drvinfo) 2150 { 2151 struct bdx_priv *priv = netdev_priv(netdev); 2152 2153 strlcat(drvinfo->driver, BDX_DRV_NAME, sizeof(drvinfo->driver)); 2154 strlcat(drvinfo->version, BDX_DRV_VERSION, sizeof(drvinfo->version)); 2155 strlcat(drvinfo->fw_version, "N/A", sizeof(drvinfo->fw_version)); 2156 strlcat(drvinfo->bus_info, pci_name(priv->pdev), 2157 sizeof(drvinfo->bus_info)); 2158 2159 drvinfo->n_stats = ((priv->stats_flag) ? ARRAY_SIZE(bdx_stat_names) : 0); 2160 drvinfo->testinfo_len = 0; 2161 drvinfo->regdump_len = 0; 2162 drvinfo->eedump_len = 0; 2163 } 2164 2165 /* 2166 * bdx_get_coalesce - get interrupt coalescing parameters 2167 * @netdev 2168 * @ecoal 2169 */ 2170 static int 2171 bdx_get_coalesce(struct net_device *netdev, struct ethtool_coalesce *ecoal) 2172 { 2173 u32 rdintcm; 2174 u32 tdintcm; 2175 struct bdx_priv *priv = netdev_priv(netdev); 2176 2177 rdintcm = priv->rdintcm; 2178 tdintcm = priv->tdintcm; 2179 2180 /* PCK_TH measures in multiples of FIFO bytes 2181 We translate to packets */ 2182 ecoal->rx_coalesce_usecs = GET_INT_COAL(rdintcm) * INT_COAL_MULT; 2183 ecoal->rx_max_coalesced_frames = 2184 ((GET_PCK_TH(rdintcm) * PCK_TH_MULT) / sizeof(struct rxf_desc)); 2185 2186 ecoal->tx_coalesce_usecs = GET_INT_COAL(tdintcm) * INT_COAL_MULT; 2187 ecoal->tx_max_coalesced_frames = 2188 ((GET_PCK_TH(tdintcm) * PCK_TH_MULT) / BDX_TXF_DESC_SZ); 2189 2190 /* adaptive parameters ignored */ 2191 return 0; 2192 } 2193 2194 /* 2195 * bdx_set_coalesce - set interrupt coalescing parameters 2196 * @netdev 2197 * @ecoal 2198 */ 2199 static int 2200 bdx_set_coalesce(struct net_device *netdev, struct ethtool_coalesce *ecoal) 2201 { 2202 u32 rdintcm; 2203 u32 tdintcm; 2204 struct bdx_priv *priv = netdev_priv(netdev); 2205 int rx_coal; 2206 int tx_coal; 2207 int rx_max_coal; 2208 int tx_max_coal; 2209 2210 /* Check for valid input */ 2211 rx_coal = ecoal->rx_coalesce_usecs / INT_COAL_MULT; 2212 tx_coal = ecoal->tx_coalesce_usecs / INT_COAL_MULT; 2213 rx_max_coal = ecoal->rx_max_coalesced_frames; 2214 tx_max_coal = ecoal->tx_max_coalesced_frames; 2215 2216 /* Translate from packets to multiples of FIFO bytes */ 2217 rx_max_coal = 2218 (((rx_max_coal * sizeof(struct rxf_desc)) + PCK_TH_MULT - 1) 2219 / PCK_TH_MULT); 2220 tx_max_coal = 2221 (((tx_max_coal * BDX_TXF_DESC_SZ) + PCK_TH_MULT - 1) 2222 / PCK_TH_MULT); 2223 2224 if ((rx_coal > 0x7FFF) || (tx_coal > 0x7FFF) || 2225 (rx_max_coal > 0xF) || (tx_max_coal > 0xF)) 2226 return -EINVAL; 2227 2228 rdintcm = INT_REG_VAL(rx_coal, GET_INT_COAL_RC(priv->rdintcm), 2229 GET_RXF_TH(priv->rdintcm), rx_max_coal); 2230 tdintcm = INT_REG_VAL(tx_coal, GET_INT_COAL_RC(priv->tdintcm), 0, 2231 tx_max_coal); 2232 2233 priv->rdintcm = rdintcm; 2234 priv->tdintcm = tdintcm; 2235 2236 WRITE_REG(priv, regRDINTCM0, rdintcm); 2237 WRITE_REG(priv, regTDINTCM0, tdintcm); 2238 2239 return 0; 2240 } 2241 2242 /* Convert RX fifo size to number of pending packets */ 2243 static inline int bdx_rx_fifo_size_to_packets(int rx_size) 2244 { 2245 return (FIFO_SIZE * (1 << rx_size)) / sizeof(struct rxf_desc); 2246 } 2247 2248 /* Convert TX fifo size to number of pending packets */ 2249 static inline int bdx_tx_fifo_size_to_packets(int tx_size) 2250 { 2251 return (FIFO_SIZE * (1 << tx_size)) / BDX_TXF_DESC_SZ; 2252 } 2253 2254 /* 2255 * bdx_get_ringparam - report ring sizes 2256 * @netdev 2257 * @ring 2258 */ 2259 static void 2260 bdx_get_ringparam(struct net_device *netdev, struct ethtool_ringparam *ring) 2261 { 2262 struct bdx_priv *priv = netdev_priv(netdev); 2263 2264 /*max_pending - the maximum-sized FIFO we allow */ 2265 ring->rx_max_pending = bdx_rx_fifo_size_to_packets(3); 2266 ring->tx_max_pending = bdx_tx_fifo_size_to_packets(3); 2267 ring->rx_pending = bdx_rx_fifo_size_to_packets(priv->rxf_size); 2268 ring->tx_pending = bdx_tx_fifo_size_to_packets(priv->txd_size); 2269 } 2270 2271 /* 2272 * bdx_set_ringparam - set ring sizes 2273 * @netdev 2274 * @ring 2275 */ 2276 static int 2277 bdx_set_ringparam(struct net_device *netdev, struct ethtool_ringparam *ring) 2278 { 2279 struct bdx_priv *priv = netdev_priv(netdev); 2280 int rx_size = 0; 2281 int tx_size = 0; 2282 2283 for (; rx_size < 4; rx_size++) { 2284 if (bdx_rx_fifo_size_to_packets(rx_size) >= ring->rx_pending) 2285 break; 2286 } 2287 if (rx_size == 4) 2288 rx_size = 3; 2289 2290 for (; tx_size < 4; tx_size++) { 2291 if (bdx_tx_fifo_size_to_packets(tx_size) >= ring->tx_pending) 2292 break; 2293 } 2294 if (tx_size == 4) 2295 tx_size = 3; 2296 2297 /*Is there anything to do? */ 2298 if ((rx_size == priv->rxf_size) && 2299 (tx_size == priv->txd_size)) 2300 return 0; 2301 2302 priv->rxf_size = rx_size; 2303 if (rx_size > 1) 2304 priv->rxd_size = rx_size - 1; 2305 else 2306 priv->rxd_size = rx_size; 2307 2308 priv->txf_size = priv->txd_size = tx_size; 2309 2310 if (netif_running(netdev)) { 2311 bdx_close(netdev); 2312 bdx_open(netdev); 2313 } 2314 return 0; 2315 } 2316 2317 /* 2318 * bdx_get_strings - return a set of strings that describe the requested objects 2319 * @netdev 2320 * @data 2321 */ 2322 static void bdx_get_strings(struct net_device *netdev, u32 stringset, u8 *data) 2323 { 2324 switch (stringset) { 2325 case ETH_SS_STATS: 2326 memcpy(data, *bdx_stat_names, sizeof(bdx_stat_names)); 2327 break; 2328 } 2329 } 2330 2331 /* 2332 * bdx_get_sset_count - return number of statistics or tests 2333 * @netdev 2334 */ 2335 static int bdx_get_sset_count(struct net_device *netdev, int stringset) 2336 { 2337 struct bdx_priv *priv = netdev_priv(netdev); 2338 2339 switch (stringset) { 2340 case ETH_SS_STATS: 2341 BDX_ASSERT(ARRAY_SIZE(bdx_stat_names) 2342 != sizeof(struct bdx_stats) / sizeof(u64)); 2343 return (priv->stats_flag) ? ARRAY_SIZE(bdx_stat_names) : 0; 2344 } 2345 2346 return -EINVAL; 2347 } 2348 2349 /* 2350 * bdx_get_ethtool_stats - return device's hardware L2 statistics 2351 * @netdev 2352 * @stats 2353 * @data 2354 */ 2355 static void bdx_get_ethtool_stats(struct net_device *netdev, 2356 struct ethtool_stats *stats, u64 *data) 2357 { 2358 struct bdx_priv *priv = netdev_priv(netdev); 2359 2360 if (priv->stats_flag) { 2361 2362 /* Update stats from HW */ 2363 bdx_update_stats(priv); 2364 2365 /* Copy data to user buffer */ 2366 memcpy(data, &priv->hw_stats, sizeof(priv->hw_stats)); 2367 } 2368 } 2369 2370 /* 2371 * bdx_set_ethtool_ops - ethtool interface implementation 2372 * @netdev 2373 */ 2374 static void bdx_set_ethtool_ops(struct net_device *netdev) 2375 { 2376 static const struct ethtool_ops bdx_ethtool_ops = { 2377 .get_settings = bdx_get_settings, 2378 .get_drvinfo = bdx_get_drvinfo, 2379 .get_link = ethtool_op_get_link, 2380 .get_coalesce = bdx_get_coalesce, 2381 .set_coalesce = bdx_set_coalesce, 2382 .get_ringparam = bdx_get_ringparam, 2383 .set_ringparam = bdx_set_ringparam, 2384 .get_strings = bdx_get_strings, 2385 .get_sset_count = bdx_get_sset_count, 2386 .get_ethtool_stats = bdx_get_ethtool_stats, 2387 }; 2388 2389 SET_ETHTOOL_OPS(netdev, &bdx_ethtool_ops); 2390 } 2391 2392 /** 2393 * bdx_remove - Device Removal Routine 2394 * @pdev: PCI device information struct 2395 * 2396 * bdx_remove is called by the PCI subsystem to alert the driver 2397 * that it should release a PCI device. The could be caused by a 2398 * Hot-Plug event, or because the driver is going to be removed from 2399 * memory. 2400 **/ 2401 static void __devexit bdx_remove(struct pci_dev *pdev) 2402 { 2403 struct pci_nic *nic = pci_get_drvdata(pdev); 2404 struct net_device *ndev; 2405 int port; 2406 2407 for (port = 0; port < nic->port_num; port++) { 2408 ndev = nic->priv[port]->ndev; 2409 unregister_netdev(ndev); 2410 free_netdev(ndev); 2411 } 2412 2413 /*bdx_hw_reset_direct(nic->regs); */ 2414 #ifdef BDX_MSI 2415 if (nic->irq_type == IRQ_MSI) 2416 pci_disable_msi(pdev); 2417 #endif 2418 2419 iounmap(nic->regs); 2420 pci_release_regions(pdev); 2421 pci_disable_device(pdev); 2422 pci_set_drvdata(pdev, NULL); 2423 vfree(nic); 2424 2425 RET(); 2426 } 2427 2428 static struct pci_driver bdx_pci_driver = { 2429 .name = BDX_DRV_NAME, 2430 .id_table = bdx_pci_tbl, 2431 .probe = bdx_probe, 2432 .remove = __devexit_p(bdx_remove), 2433 }; 2434 2435 /* 2436 * print_driver_id - print parameters of the driver build 2437 */ 2438 static void __init print_driver_id(void) 2439 { 2440 pr_info("%s, %s\n", BDX_DRV_DESC, BDX_DRV_VERSION); 2441 pr_info("Options: hw_csum %s\n", BDX_MSI_STRING); 2442 } 2443 2444 static int __init bdx_module_init(void) 2445 { 2446 ENTER; 2447 init_txd_sizes(); 2448 print_driver_id(); 2449 RET(pci_register_driver(&bdx_pci_driver)); 2450 } 2451 2452 module_init(bdx_module_init); 2453 2454 static void __exit bdx_module_exit(void) 2455 { 2456 ENTER; 2457 pci_unregister_driver(&bdx_pci_driver); 2458 RET(); 2459 } 2460 2461 module_exit(bdx_module_exit); 2462 2463 MODULE_LICENSE("GPL"); 2464 MODULE_AUTHOR(DRIVER_AUTHOR); 2465 MODULE_DESCRIPTION(BDX_DRV_DESC); 2466 MODULE_FIRMWARE("tehuti/bdx.bin"); 2467