1 /* Synopsys DesignWare Core Enterprise Ethernet (XLGMAC) Driver 2 * 3 * Copyright (c) 2017 Synopsys, Inc. (www.synopsys.com) 4 * 5 * This program is dual-licensed; you may select either version 2 of 6 * the GNU General Public License ("GPL") or BSD license ("BSD"). 7 * 8 * This Synopsys DWC XLGMAC software driver and associated documentation 9 * (hereinafter the "Software") is an unsupported proprietary work of 10 * Synopsys, Inc. unless otherwise expressly agreed to in writing between 11 * Synopsys and you. The Software IS NOT an item of Licensed Software or a 12 * Licensed Product under any End User Software License Agreement or 13 * Agreement for Licensed Products with Synopsys or any supplement thereto. 14 * Synopsys is a registered trademark of Synopsys, Inc. Other names included 15 * in the SOFTWARE may be the trademarks of their respective owners. 16 */ 17 18 #ifndef __DWC_XLGMAC_H__ 19 #define __DWC_XLGMAC_H__ 20 21 #include <linux/dma-mapping.h> 22 #include <linux/netdevice.h> 23 #include <linux/workqueue.h> 24 #include <linux/phy.h> 25 #include <linux/if_vlan.h> 26 #include <linux/bitops.h> 27 #include <linux/timecounter.h> 28 29 #define XLGMAC_DRV_NAME "dwc-xlgmac" 30 #define XLGMAC_DRV_VERSION "1.0.0" 31 #define XLGMAC_DRV_DESC "Synopsys DWC XLGMAC Driver" 32 33 /* Descriptor related parameters */ 34 #define XLGMAC_TX_DESC_CNT 1024 35 #define XLGMAC_TX_DESC_MIN_FREE (XLGMAC_TX_DESC_CNT >> 3) 36 #define XLGMAC_TX_DESC_MAX_PROC (XLGMAC_TX_DESC_CNT >> 1) 37 #define XLGMAC_RX_DESC_CNT 1024 38 #define XLGMAC_RX_DESC_MAX_DIRTY (XLGMAC_RX_DESC_CNT >> 3) 39 40 /* Descriptors required for maximum contiguous TSO/GSO packet */ 41 #define XLGMAC_TX_MAX_SPLIT ((GSO_MAX_SIZE / XLGMAC_TX_MAX_BUF_SIZE) + 1) 42 43 /* Maximum possible descriptors needed for a SKB */ 44 #define XLGMAC_TX_MAX_DESC_NR (MAX_SKB_FRAGS + XLGMAC_TX_MAX_SPLIT + 2) 45 46 #define XLGMAC_TX_MAX_BUF_SIZE (0x3fff & ~(64 - 1)) 47 #define XLGMAC_RX_MIN_BUF_SIZE (ETH_FRAME_LEN + ETH_FCS_LEN + VLAN_HLEN) 48 #define XLGMAC_RX_BUF_ALIGN 64 49 50 /* Maximum Size for Splitting the Header Data 51 * Keep in sync with SKB_ALLOC_SIZE 52 * 3'b000: 64 bytes, 3'b001: 128 bytes 53 * 3'b010: 256 bytes, 3'b011: 512 bytes 54 * 3'b100: 1023 bytes , 3'b101'3'b111: Reserved 55 */ 56 #define XLGMAC_SPH_HDSMS_SIZE 3 57 #define XLGMAC_SKB_ALLOC_SIZE 512 58 59 #define XLGMAC_MAX_FIFO 81920 60 61 #define XLGMAC_MAX_DMA_CHANNELS 16 62 #define XLGMAC_DMA_STOP_TIMEOUT 5 63 #define XLGMAC_DMA_INTERRUPT_MASK 0x31c7 64 65 /* Default coalescing parameters */ 66 #define XLGMAC_INIT_DMA_TX_USECS 1000 67 #define XLGMAC_INIT_DMA_TX_FRAMES 25 68 #define XLGMAC_INIT_DMA_RX_USECS 30 69 #define XLGMAC_INIT_DMA_RX_FRAMES 25 70 71 /* Flow control queue count */ 72 #define XLGMAC_MAX_FLOW_CONTROL_QUEUES 8 73 74 /* System clock is 125 MHz */ 75 #define XLGMAC_SYSCLOCK 125000000 76 77 /* Maximum MAC address hash table size (256 bits = 8 bytes) */ 78 #define XLGMAC_MAC_HASH_TABLE_SIZE 8 79 80 /* Receive Side Scaling */ 81 #define XLGMAC_RSS_HASH_KEY_SIZE 40 82 #define XLGMAC_RSS_MAX_TABLE_SIZE 256 83 #define XLGMAC_RSS_LOOKUP_TABLE_TYPE 0 84 #define XLGMAC_RSS_HASH_KEY_TYPE 1 85 86 #define XLGMAC_STD_PACKET_MTU 1500 87 #define XLGMAC_JUMBO_PACKET_MTU 9000 88 89 /* Helper macro for descriptor handling 90 * Always use XLGMAC_GET_DESC_DATA to access the descriptor data 91 */ 92 #define XLGMAC_GET_DESC_DATA(ring, idx) ({ \ 93 typeof(ring) _ring = (ring); \ 94 ((_ring)->desc_data_head + \ 95 ((idx) & ((_ring)->dma_desc_count - 1))); \ 96 }) 97 98 #define XLGMAC_GET_REG_BITS(var, pos, len) ({ \ 99 typeof(pos) _pos = (pos); \ 100 typeof(len) _len = (len); \ 101 ((var) & GENMASK(_pos + _len - 1, _pos)) >> (_pos); \ 102 }) 103 104 #define XLGMAC_GET_REG_BITS_LE(var, pos, len) ({ \ 105 typeof(pos) _pos = (pos); \ 106 typeof(len) _len = (len); \ 107 typeof(var) _var = le32_to_cpu((var)); \ 108 ((_var) & GENMASK(_pos + _len - 1, _pos)) >> (_pos); \ 109 }) 110 111 #define XLGMAC_SET_REG_BITS(var, pos, len, val) ({ \ 112 typeof(var) _var = (var); \ 113 typeof(pos) _pos = (pos); \ 114 typeof(len) _len = (len); \ 115 typeof(val) _val = (val); \ 116 _val = (_val << _pos) & GENMASK(_pos + _len - 1, _pos); \ 117 _var = (_var & ~GENMASK(_pos + _len - 1, _pos)) | _val; \ 118 }) 119 120 #define XLGMAC_SET_REG_BITS_LE(var, pos, len, val) ({ \ 121 typeof(var) _var = (var); \ 122 typeof(pos) _pos = (pos); \ 123 typeof(len) _len = (len); \ 124 typeof(val) _val = (val); \ 125 _val = (_val << _pos) & GENMASK(_pos + _len - 1, _pos); \ 126 _var = (_var & ~GENMASK(_pos + _len - 1, _pos)) | _val; \ 127 cpu_to_le32(_var); \ 128 }) 129 130 struct xlgmac_pdata; 131 132 enum xlgmac_int { 133 XLGMAC_INT_DMA_CH_SR_TI, 134 XLGMAC_INT_DMA_CH_SR_TPS, 135 XLGMAC_INT_DMA_CH_SR_TBU, 136 XLGMAC_INT_DMA_CH_SR_RI, 137 XLGMAC_INT_DMA_CH_SR_RBU, 138 XLGMAC_INT_DMA_CH_SR_RPS, 139 XLGMAC_INT_DMA_CH_SR_TI_RI, 140 XLGMAC_INT_DMA_CH_SR_FBE, 141 XLGMAC_INT_DMA_ALL, 142 }; 143 144 struct xlgmac_stats { 145 /* MMC TX counters */ 146 u64 txoctetcount_gb; 147 u64 txframecount_gb; 148 u64 txbroadcastframes_g; 149 u64 txmulticastframes_g; 150 u64 tx64octets_gb; 151 u64 tx65to127octets_gb; 152 u64 tx128to255octets_gb; 153 u64 tx256to511octets_gb; 154 u64 tx512to1023octets_gb; 155 u64 tx1024tomaxoctets_gb; 156 u64 txunicastframes_gb; 157 u64 txmulticastframes_gb; 158 u64 txbroadcastframes_gb; 159 u64 txunderflowerror; 160 u64 txoctetcount_g; 161 u64 txframecount_g; 162 u64 txpauseframes; 163 u64 txvlanframes_g; 164 165 /* MMC RX counters */ 166 u64 rxframecount_gb; 167 u64 rxoctetcount_gb; 168 u64 rxoctetcount_g; 169 u64 rxbroadcastframes_g; 170 u64 rxmulticastframes_g; 171 u64 rxcrcerror; 172 u64 rxrunterror; 173 u64 rxjabbererror; 174 u64 rxundersize_g; 175 u64 rxoversize_g; 176 u64 rx64octets_gb; 177 u64 rx65to127octets_gb; 178 u64 rx128to255octets_gb; 179 u64 rx256to511octets_gb; 180 u64 rx512to1023octets_gb; 181 u64 rx1024tomaxoctets_gb; 182 u64 rxunicastframes_g; 183 u64 rxlengtherror; 184 u64 rxoutofrangetype; 185 u64 rxpauseframes; 186 u64 rxfifooverflow; 187 u64 rxvlanframes_gb; 188 u64 rxwatchdogerror; 189 190 /* Extra counters */ 191 u64 tx_tso_packets; 192 u64 rx_split_header_packets; 193 u64 rx_buffer_unavailable; 194 }; 195 196 struct xlgmac_ring_buf { 197 struct sk_buff *skb; 198 dma_addr_t skb_dma; 199 unsigned int skb_len; 200 }; 201 202 /* Common Tx and Rx DMA hardware descriptor */ 203 struct xlgmac_dma_desc { 204 __le32 desc0; 205 __le32 desc1; 206 __le32 desc2; 207 __le32 desc3; 208 }; 209 210 /* Page allocation related values */ 211 struct xlgmac_page_alloc { 212 struct page *pages; 213 unsigned int pages_len; 214 unsigned int pages_offset; 215 216 dma_addr_t pages_dma; 217 }; 218 219 /* Ring entry buffer data */ 220 struct xlgmac_buffer_data { 221 struct xlgmac_page_alloc pa; 222 struct xlgmac_page_alloc pa_unmap; 223 224 dma_addr_t dma_base; 225 unsigned long dma_off; 226 unsigned int dma_len; 227 }; 228 229 /* Tx-related desc data */ 230 struct xlgmac_tx_desc_data { 231 unsigned int packets; /* BQL packet count */ 232 unsigned int bytes; /* BQL byte count */ 233 }; 234 235 /* Rx-related desc data */ 236 struct xlgmac_rx_desc_data { 237 struct xlgmac_buffer_data hdr; /* Header locations */ 238 struct xlgmac_buffer_data buf; /* Payload locations */ 239 240 unsigned short hdr_len; /* Length of received header */ 241 unsigned short len; /* Length of received packet */ 242 }; 243 244 struct xlgmac_pkt_info { 245 struct sk_buff *skb; 246 247 unsigned int attributes; 248 249 unsigned int errors; 250 251 /* descriptors needed for this packet */ 252 unsigned int desc_count; 253 unsigned int length; 254 255 unsigned int tx_packets; 256 unsigned int tx_bytes; 257 258 unsigned int header_len; 259 unsigned int tcp_header_len; 260 unsigned int tcp_payload_len; 261 unsigned short mss; 262 263 unsigned short vlan_ctag; 264 265 u64 rx_tstamp; 266 267 u32 rss_hash; 268 enum pkt_hash_types rss_hash_type; 269 }; 270 271 struct xlgmac_desc_data { 272 /* dma_desc: Virtual address of descriptor 273 * dma_desc_addr: DMA address of descriptor 274 */ 275 struct xlgmac_dma_desc *dma_desc; 276 dma_addr_t dma_desc_addr; 277 278 /* skb: Virtual address of SKB 279 * skb_dma: DMA address of SKB data 280 * skb_dma_len: Length of SKB DMA area 281 */ 282 struct sk_buff *skb; 283 dma_addr_t skb_dma; 284 unsigned int skb_dma_len; 285 286 /* Tx/Rx -related data */ 287 struct xlgmac_tx_desc_data tx; 288 struct xlgmac_rx_desc_data rx; 289 290 unsigned int mapped_as_page; 291 292 /* Incomplete receive save location. If the budget is exhausted 293 * or the last descriptor (last normal descriptor or a following 294 * context descriptor) has not been DMA'd yet the current state 295 * of the receive processing needs to be saved. 296 */ 297 unsigned int state_saved; 298 struct { 299 struct sk_buff *skb; 300 unsigned int len; 301 unsigned int error; 302 } state; 303 }; 304 305 struct xlgmac_ring { 306 /* Per packet related information */ 307 struct xlgmac_pkt_info pkt_info; 308 309 /* Virtual/DMA addresses of DMA descriptor list and the total count */ 310 struct xlgmac_dma_desc *dma_desc_head; 311 dma_addr_t dma_desc_head_addr; 312 unsigned int dma_desc_count; 313 314 /* Array of descriptor data corresponding the DMA descriptor 315 * (always use the XLGMAC_GET_DESC_DATA macro to access this data) 316 */ 317 struct xlgmac_desc_data *desc_data_head; 318 319 /* Page allocation for RX buffers */ 320 struct xlgmac_page_alloc rx_hdr_pa; 321 struct xlgmac_page_alloc rx_buf_pa; 322 323 /* Ring index values 324 * cur - Tx: index of descriptor to be used for current transfer 325 * Rx: index of descriptor to check for packet availability 326 * dirty - Tx: index of descriptor to check for transfer complete 327 * Rx: index of descriptor to check for buffer reallocation 328 */ 329 unsigned int cur; 330 unsigned int dirty; 331 332 /* Coalesce frame count used for interrupt bit setting */ 333 unsigned int coalesce_count; 334 335 union { 336 struct { 337 unsigned int xmit_more; 338 unsigned int queue_stopped; 339 unsigned short cur_mss; 340 unsigned short cur_vlan_ctag; 341 } tx; 342 }; 343 } ____cacheline_aligned; 344 345 struct xlgmac_channel { 346 char name[16]; 347 348 /* Address of private data area for device */ 349 struct xlgmac_pdata *pdata; 350 351 /* Queue index and base address of queue's DMA registers */ 352 unsigned int queue_index; 353 void __iomem *dma_regs; 354 355 /* Per channel interrupt irq number */ 356 int dma_irq; 357 char dma_irq_name[IFNAMSIZ + 32]; 358 359 /* Netdev related settings */ 360 struct napi_struct napi; 361 362 unsigned int saved_ier; 363 364 unsigned int tx_timer_active; 365 struct timer_list tx_timer; 366 367 struct xlgmac_ring *tx_ring; 368 struct xlgmac_ring *rx_ring; 369 } ____cacheline_aligned; 370 371 struct xlgmac_desc_ops { 372 int (*alloc_channles_and_rings)(struct xlgmac_pdata *pdata); 373 void (*free_channels_and_rings)(struct xlgmac_pdata *pdata); 374 int (*map_tx_skb)(struct xlgmac_channel *channel, 375 struct sk_buff *skb); 376 int (*map_rx_buffer)(struct xlgmac_pdata *pdata, 377 struct xlgmac_ring *ring, 378 struct xlgmac_desc_data *desc_data); 379 void (*unmap_desc_data)(struct xlgmac_pdata *pdata, 380 struct xlgmac_desc_data *desc_data); 381 void (*tx_desc_init)(struct xlgmac_pdata *pdata); 382 void (*rx_desc_init)(struct xlgmac_pdata *pdata); 383 }; 384 385 struct xlgmac_hw_ops { 386 int (*init)(struct xlgmac_pdata *pdata); 387 int (*exit)(struct xlgmac_pdata *pdata); 388 389 int (*tx_complete)(struct xlgmac_dma_desc *dma_desc); 390 391 void (*enable_tx)(struct xlgmac_pdata *pdata); 392 void (*disable_tx)(struct xlgmac_pdata *pdata); 393 void (*enable_rx)(struct xlgmac_pdata *pdata); 394 void (*disable_rx)(struct xlgmac_pdata *pdata); 395 396 int (*enable_int)(struct xlgmac_channel *channel, 397 enum xlgmac_int int_id); 398 int (*disable_int)(struct xlgmac_channel *channel, 399 enum xlgmac_int int_id); 400 void (*dev_xmit)(struct xlgmac_channel *channel); 401 int (*dev_read)(struct xlgmac_channel *channel); 402 403 int (*set_mac_address)(struct xlgmac_pdata *pdata, u8 *addr); 404 int (*config_rx_mode)(struct xlgmac_pdata *pdata); 405 int (*enable_rx_csum)(struct xlgmac_pdata *pdata); 406 int (*disable_rx_csum)(struct xlgmac_pdata *pdata); 407 408 /* For MII speed configuration */ 409 int (*set_xlgmii_25000_speed)(struct xlgmac_pdata *pdata); 410 int (*set_xlgmii_40000_speed)(struct xlgmac_pdata *pdata); 411 int (*set_xlgmii_50000_speed)(struct xlgmac_pdata *pdata); 412 int (*set_xlgmii_100000_speed)(struct xlgmac_pdata *pdata); 413 414 /* For descriptor related operation */ 415 void (*tx_desc_init)(struct xlgmac_channel *channel); 416 void (*rx_desc_init)(struct xlgmac_channel *channel); 417 void (*tx_desc_reset)(struct xlgmac_desc_data *desc_data); 418 void (*rx_desc_reset)(struct xlgmac_pdata *pdata, 419 struct xlgmac_desc_data *desc_data, 420 unsigned int index); 421 int (*is_last_desc)(struct xlgmac_dma_desc *dma_desc); 422 int (*is_context_desc)(struct xlgmac_dma_desc *dma_desc); 423 void (*tx_start_xmit)(struct xlgmac_channel *channel, 424 struct xlgmac_ring *ring); 425 426 /* For Flow Control */ 427 int (*config_tx_flow_control)(struct xlgmac_pdata *pdata); 428 int (*config_rx_flow_control)(struct xlgmac_pdata *pdata); 429 430 /* For Vlan related config */ 431 int (*enable_rx_vlan_stripping)(struct xlgmac_pdata *pdata); 432 int (*disable_rx_vlan_stripping)(struct xlgmac_pdata *pdata); 433 int (*enable_rx_vlan_filtering)(struct xlgmac_pdata *pdata); 434 int (*disable_rx_vlan_filtering)(struct xlgmac_pdata *pdata); 435 int (*update_vlan_hash_table)(struct xlgmac_pdata *pdata); 436 437 /* For RX coalescing */ 438 int (*config_rx_coalesce)(struct xlgmac_pdata *pdata); 439 int (*config_tx_coalesce)(struct xlgmac_pdata *pdata); 440 unsigned int (*usec_to_riwt)(struct xlgmac_pdata *pdata, 441 unsigned int usec); 442 unsigned int (*riwt_to_usec)(struct xlgmac_pdata *pdata, 443 unsigned int riwt); 444 445 /* For RX and TX threshold config */ 446 int (*config_rx_threshold)(struct xlgmac_pdata *pdata, 447 unsigned int val); 448 int (*config_tx_threshold)(struct xlgmac_pdata *pdata, 449 unsigned int val); 450 451 /* For RX and TX Store and Forward Mode config */ 452 int (*config_rsf_mode)(struct xlgmac_pdata *pdata, 453 unsigned int val); 454 int (*config_tsf_mode)(struct xlgmac_pdata *pdata, 455 unsigned int val); 456 457 /* For TX DMA Operate on Second Frame config */ 458 int (*config_osp_mode)(struct xlgmac_pdata *pdata); 459 460 /* For RX and TX PBL config */ 461 int (*config_rx_pbl_val)(struct xlgmac_pdata *pdata); 462 int (*get_rx_pbl_val)(struct xlgmac_pdata *pdata); 463 int (*config_tx_pbl_val)(struct xlgmac_pdata *pdata); 464 int (*get_tx_pbl_val)(struct xlgmac_pdata *pdata); 465 int (*config_pblx8)(struct xlgmac_pdata *pdata); 466 467 /* For MMC statistics */ 468 void (*rx_mmc_int)(struct xlgmac_pdata *pdata); 469 void (*tx_mmc_int)(struct xlgmac_pdata *pdata); 470 void (*read_mmc_stats)(struct xlgmac_pdata *pdata); 471 472 /* For Receive Side Scaling */ 473 int (*enable_rss)(struct xlgmac_pdata *pdata); 474 int (*disable_rss)(struct xlgmac_pdata *pdata); 475 int (*set_rss_hash_key)(struct xlgmac_pdata *pdata, 476 const u8 *key); 477 int (*set_rss_lookup_table)(struct xlgmac_pdata *pdata, 478 const u32 *table); 479 }; 480 481 /* This structure contains flags that indicate what hardware features 482 * or configurations are present in the device. 483 */ 484 struct xlgmac_hw_features { 485 /* HW Version */ 486 unsigned int version; 487 488 /* HW Feature Register0 */ 489 unsigned int phyifsel; /* PHY interface support */ 490 unsigned int vlhash; /* VLAN Hash Filter */ 491 unsigned int sma; /* SMA(MDIO) Interface */ 492 unsigned int rwk; /* PMT remote wake-up packet */ 493 unsigned int mgk; /* PMT magic packet */ 494 unsigned int mmc; /* RMON module */ 495 unsigned int aoe; /* ARP Offload */ 496 unsigned int ts; /* IEEE 1588-2008 Advanced Timestamp */ 497 unsigned int eee; /* Energy Efficient Ethernet */ 498 unsigned int tx_coe; /* Tx Checksum Offload */ 499 unsigned int rx_coe; /* Rx Checksum Offload */ 500 unsigned int addn_mac; /* Additional MAC Addresses */ 501 unsigned int ts_src; /* Timestamp Source */ 502 unsigned int sa_vlan_ins; /* Source Address or VLAN Insertion */ 503 504 /* HW Feature Register1 */ 505 unsigned int rx_fifo_size; /* MTL Receive FIFO Size */ 506 unsigned int tx_fifo_size; /* MTL Transmit FIFO Size */ 507 unsigned int adv_ts_hi; /* Advance Timestamping High Word */ 508 unsigned int dma_width; /* DMA width */ 509 unsigned int dcb; /* DCB Feature */ 510 unsigned int sph; /* Split Header Feature */ 511 unsigned int tso; /* TCP Segmentation Offload */ 512 unsigned int dma_debug; /* DMA Debug Registers */ 513 unsigned int rss; /* Receive Side Scaling */ 514 unsigned int tc_cnt; /* Number of Traffic Classes */ 515 unsigned int hash_table_size; /* Hash Table Size */ 516 unsigned int l3l4_filter_num; /* Number of L3-L4 Filters */ 517 518 /* HW Feature Register2 */ 519 unsigned int rx_q_cnt; /* Number of MTL Receive Queues */ 520 unsigned int tx_q_cnt; /* Number of MTL Transmit Queues */ 521 unsigned int rx_ch_cnt; /* Number of DMA Receive Channels */ 522 unsigned int tx_ch_cnt; /* Number of DMA Transmit Channels */ 523 unsigned int pps_out_num; /* Number of PPS outputs */ 524 unsigned int aux_snap_num; /* Number of Aux snapshot inputs */ 525 }; 526 527 struct xlgmac_resources { 528 void __iomem *addr; 529 int irq; 530 }; 531 532 struct xlgmac_pdata { 533 struct net_device *netdev; 534 struct device *dev; 535 536 struct xlgmac_hw_ops hw_ops; 537 struct xlgmac_desc_ops desc_ops; 538 539 /* Device statistics */ 540 struct xlgmac_stats stats; 541 542 u32 msg_enable; 543 544 /* MAC registers base */ 545 void __iomem *mac_regs; 546 547 /* Hardware features of the device */ 548 struct xlgmac_hw_features hw_feat; 549 550 struct work_struct restart_work; 551 552 /* Rings for Tx/Rx on a DMA channel */ 553 struct xlgmac_channel *channel_head; 554 unsigned int channel_count; 555 unsigned int tx_ring_count; 556 unsigned int rx_ring_count; 557 unsigned int tx_desc_count; 558 unsigned int rx_desc_count; 559 unsigned int tx_q_count; 560 unsigned int rx_q_count; 561 562 /* Tx/Rx common settings */ 563 unsigned int pblx8; 564 565 /* Tx settings */ 566 unsigned int tx_sf_mode; 567 unsigned int tx_threshold; 568 unsigned int tx_pbl; 569 unsigned int tx_osp_mode; 570 571 /* Rx settings */ 572 unsigned int rx_sf_mode; 573 unsigned int rx_threshold; 574 unsigned int rx_pbl; 575 576 /* Tx coalescing settings */ 577 unsigned int tx_usecs; 578 unsigned int tx_frames; 579 580 /* Rx coalescing settings */ 581 unsigned int rx_riwt; 582 unsigned int rx_usecs; 583 unsigned int rx_frames; 584 585 /* Current Rx buffer size */ 586 unsigned int rx_buf_size; 587 588 /* Flow control settings */ 589 unsigned int tx_pause; 590 unsigned int rx_pause; 591 592 /* Device interrupt number */ 593 int dev_irq; 594 unsigned int per_channel_irq; 595 int channel_irq[XLGMAC_MAX_DMA_CHANNELS]; 596 597 /* Netdev related settings */ 598 unsigned char mac_addr[ETH_ALEN]; 599 netdev_features_t netdev_features; 600 struct napi_struct napi; 601 602 /* Filtering support */ 603 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)]; 604 605 /* Device clocks */ 606 unsigned long sysclk_rate; 607 608 /* RSS addressing mutex */ 609 struct mutex rss_mutex; 610 611 /* Receive Side Scaling settings */ 612 u8 rss_key[XLGMAC_RSS_HASH_KEY_SIZE]; 613 u32 rss_table[XLGMAC_RSS_MAX_TABLE_SIZE]; 614 u32 rss_options; 615 616 int phy_speed; 617 618 char drv_name[32]; 619 char drv_ver[32]; 620 }; 621 622 void xlgmac_init_desc_ops(struct xlgmac_desc_ops *desc_ops); 623 void xlgmac_init_hw_ops(struct xlgmac_hw_ops *hw_ops); 624 const struct net_device_ops *xlgmac_get_netdev_ops(void); 625 void xlgmac_dump_tx_desc(struct xlgmac_pdata *pdata, 626 struct xlgmac_ring *ring, 627 unsigned int idx, 628 unsigned int count, 629 unsigned int flag); 630 void xlgmac_dump_rx_desc(struct xlgmac_pdata *pdata, 631 struct xlgmac_ring *ring, 632 unsigned int idx); 633 void xlgmac_print_pkt(struct net_device *netdev, 634 struct sk_buff *skb, bool tx_rx); 635 void xlgmac_get_all_hw_features(struct xlgmac_pdata *pdata); 636 void xlgmac_print_all_hw_features(struct xlgmac_pdata *pdata); 637 int xlgmac_drv_probe(struct device *dev, 638 struct xlgmac_resources *res); 639 int xlgmac_drv_remove(struct device *dev); 640 641 /* For debug prints */ 642 #ifdef XLGMAC_DEBUG 643 #define XLGMAC_PR(fmt, args...) \ 644 pr_alert("[%s,%d]:" fmt, __func__, __LINE__, ## args) 645 #else 646 #define XLGMAC_PR(x...) do { } while (0) 647 #endif 648 649 #endif /* __DWC_XLGMAC_H__ */ 650