1 /* Synopsys DesignWare Core Enterprise Ethernet (XLGMAC) Driver
2  *
3  * Copyright (c) 2017 Synopsys, Inc. (www.synopsys.com)
4  *
5  * This program is dual-licensed; you may select either version 2 of
6  * the GNU General Public License ("GPL") or BSD license ("BSD").
7  *
8  * This Synopsys DWC XLGMAC software driver and associated documentation
9  * (hereinafter the "Software") is an unsupported proprietary work of
10  * Synopsys, Inc. unless otherwise expressly agreed to in writing between
11  * Synopsys and you. The Software IS NOT an item of Licensed Software or a
12  * Licensed Product under any End User Software License Agreement or
13  * Agreement for Licensed Products with Synopsys or any supplement thereto.
14  * Synopsys is a registered trademark of Synopsys, Inc. Other names included
15  * in the SOFTWARE may be the trademarks of their respective owners.
16  */
17 
18 #ifndef __DWC_XLGMAC_H__
19 #define __DWC_XLGMAC_H__
20 
21 #include <linux/dma-mapping.h>
22 #include <linux/netdevice.h>
23 #include <linux/workqueue.h>
24 #include <linux/phy.h>
25 #include <linux/if_vlan.h>
26 #include <linux/bitops.h>
27 #include <linux/timecounter.h>
28 
29 #define XLGMAC_DRV_NAME			"dwc-xlgmac"
30 #define XLGMAC_DRV_VERSION		"1.0.0"
31 #define XLGMAC_DRV_DESC			"Synopsys DWC XLGMAC Driver"
32 
33 /* Descriptor related parameters */
34 #define XLGMAC_TX_DESC_CNT		1024
35 #define XLGMAC_TX_DESC_MIN_FREE		(XLGMAC_TX_DESC_CNT >> 3)
36 #define XLGMAC_TX_DESC_MAX_PROC		(XLGMAC_TX_DESC_CNT >> 1)
37 #define XLGMAC_RX_DESC_CNT		1024
38 #define XLGMAC_RX_DESC_MAX_DIRTY	(XLGMAC_RX_DESC_CNT >> 3)
39 
40 /* Descriptors required for maximum contiguous TSO/GSO packet */
41 #define XLGMAC_TX_MAX_SPLIT	((GSO_MAX_SIZE / XLGMAC_TX_MAX_BUF_SIZE) + 1)
42 
43 /* Maximum possible descriptors needed for a SKB */
44 #define XLGMAC_TX_MAX_DESC_NR	(MAX_SKB_FRAGS + XLGMAC_TX_MAX_SPLIT + 2)
45 
46 #define XLGMAC_TX_MAX_BUF_SIZE	(0x3fff & ~(64 - 1))
47 #define XLGMAC_RX_MIN_BUF_SIZE	(ETH_FRAME_LEN + ETH_FCS_LEN + VLAN_HLEN)
48 #define XLGMAC_RX_BUF_ALIGN	64
49 
50 /* Maximum Size for Splitting the Header Data
51  * Keep in sync with SKB_ALLOC_SIZE
52  * 3'b000: 64 bytes, 3'b001: 128 bytes
53  * 3'b010: 256 bytes, 3'b011: 512 bytes
54  * 3'b100: 1023 bytes ,   3'b101'3'b111: Reserved
55  */
56 #define XLGMAC_SPH_HDSMS_SIZE		3
57 #define XLGMAC_SKB_ALLOC_SIZE		512
58 
59 #define XLGMAC_MAX_FIFO			81920
60 
61 #define XLGMAC_MAX_DMA_CHANNELS		16
62 #define XLGMAC_DMA_STOP_TIMEOUT		5
63 #define XLGMAC_DMA_INTERRUPT_MASK	0x31c7
64 
65 /* Default coalescing parameters */
66 #define XLGMAC_INIT_DMA_TX_USECS	1000
67 #define XLGMAC_INIT_DMA_TX_FRAMES	25
68 #define XLGMAC_INIT_DMA_RX_USECS	30
69 #define XLGMAC_INIT_DMA_RX_FRAMES	25
70 #define XLGMAC_MAX_DMA_RIWT		0xff
71 #define XLGMAC_MIN_DMA_RIWT		0x01
72 
73 /* Flow control queue count */
74 #define XLGMAC_MAX_FLOW_CONTROL_QUEUES	8
75 
76 /* System clock is 125 MHz */
77 #define XLGMAC_SYSCLOCK			125000000
78 
79 /* Maximum MAC address hash table size (256 bits = 8 bytes) */
80 #define XLGMAC_MAC_HASH_TABLE_SIZE	8
81 
82 /* Receive Side Scaling */
83 #define XLGMAC_RSS_HASH_KEY_SIZE	40
84 #define XLGMAC_RSS_MAX_TABLE_SIZE	256
85 #define XLGMAC_RSS_LOOKUP_TABLE_TYPE	0
86 #define XLGMAC_RSS_HASH_KEY_TYPE	1
87 
88 #define XLGMAC_STD_PACKET_MTU		1500
89 #define XLGMAC_JUMBO_PACKET_MTU		9000
90 
91 /* Helper macro for descriptor handling
92  *  Always use XLGMAC_GET_DESC_DATA to access the descriptor data
93  */
94 #define XLGMAC_GET_DESC_DATA(ring, idx) ({				\
95 	typeof(ring) _ring = (ring);					\
96 	((_ring)->desc_data_head +					\
97 	 ((idx) & ((_ring)->dma_desc_count - 1)));			\
98 })
99 
100 #define XLGMAC_GET_REG_BITS(var, pos, len) ({				\
101 	typeof(pos) _pos = (pos);					\
102 	typeof(len) _len = (len);					\
103 	((var) & GENMASK(_pos + _len - 1, _pos)) >> (_pos);		\
104 })
105 
106 #define XLGMAC_GET_REG_BITS_LE(var, pos, len) ({			\
107 	typeof(pos) _pos = (pos);					\
108 	typeof(len) _len = (len);					\
109 	typeof(var) _var = le32_to_cpu((var));				\
110 	((_var) & GENMASK(_pos + _len - 1, _pos)) >> (_pos);		\
111 })
112 
113 #define XLGMAC_SET_REG_BITS(var, pos, len, val) ({			\
114 	typeof(var) _var = (var);					\
115 	typeof(pos) _pos = (pos);					\
116 	typeof(len) _len = (len);					\
117 	typeof(val) _val = (val);					\
118 	_val = (_val << _pos) & GENMASK(_pos + _len - 1, _pos);		\
119 	_var = (_var & ~GENMASK(_pos + _len - 1, _pos)) | _val;		\
120 })
121 
122 #define XLGMAC_SET_REG_BITS_LE(var, pos, len, val) ({			\
123 	typeof(var) _var = (var);					\
124 	typeof(pos) _pos = (pos);					\
125 	typeof(len) _len = (len);					\
126 	typeof(val) _val = (val);					\
127 	_val = (_val << _pos) & GENMASK(_pos + _len - 1, _pos);		\
128 	_var = (_var & ~GENMASK(_pos + _len - 1, _pos)) | _val;		\
129 	cpu_to_le32(_var);						\
130 })
131 
132 struct xlgmac_pdata;
133 
134 enum xlgmac_int {
135 	XLGMAC_INT_DMA_CH_SR_TI,
136 	XLGMAC_INT_DMA_CH_SR_TPS,
137 	XLGMAC_INT_DMA_CH_SR_TBU,
138 	XLGMAC_INT_DMA_CH_SR_RI,
139 	XLGMAC_INT_DMA_CH_SR_RBU,
140 	XLGMAC_INT_DMA_CH_SR_RPS,
141 	XLGMAC_INT_DMA_CH_SR_TI_RI,
142 	XLGMAC_INT_DMA_CH_SR_FBE,
143 	XLGMAC_INT_DMA_ALL,
144 };
145 
146 struct xlgmac_stats {
147 	/* MMC TX counters */
148 	u64 txoctetcount_gb;
149 	u64 txframecount_gb;
150 	u64 txbroadcastframes_g;
151 	u64 txmulticastframes_g;
152 	u64 tx64octets_gb;
153 	u64 tx65to127octets_gb;
154 	u64 tx128to255octets_gb;
155 	u64 tx256to511octets_gb;
156 	u64 tx512to1023octets_gb;
157 	u64 tx1024tomaxoctets_gb;
158 	u64 txunicastframes_gb;
159 	u64 txmulticastframes_gb;
160 	u64 txbroadcastframes_gb;
161 	u64 txunderflowerror;
162 	u64 txoctetcount_g;
163 	u64 txframecount_g;
164 	u64 txpauseframes;
165 	u64 txvlanframes_g;
166 
167 	/* MMC RX counters */
168 	u64 rxframecount_gb;
169 	u64 rxoctetcount_gb;
170 	u64 rxoctetcount_g;
171 	u64 rxbroadcastframes_g;
172 	u64 rxmulticastframes_g;
173 	u64 rxcrcerror;
174 	u64 rxrunterror;
175 	u64 rxjabbererror;
176 	u64 rxundersize_g;
177 	u64 rxoversize_g;
178 	u64 rx64octets_gb;
179 	u64 rx65to127octets_gb;
180 	u64 rx128to255octets_gb;
181 	u64 rx256to511octets_gb;
182 	u64 rx512to1023octets_gb;
183 	u64 rx1024tomaxoctets_gb;
184 	u64 rxunicastframes_g;
185 	u64 rxlengtherror;
186 	u64 rxoutofrangetype;
187 	u64 rxpauseframes;
188 	u64 rxfifooverflow;
189 	u64 rxvlanframes_gb;
190 	u64 rxwatchdogerror;
191 
192 	/* Extra counters */
193 	u64 tx_tso_packets;
194 	u64 rx_split_header_packets;
195 	u64 tx_process_stopped;
196 	u64 rx_process_stopped;
197 	u64 tx_buffer_unavailable;
198 	u64 rx_buffer_unavailable;
199 	u64 fatal_bus_error;
200 	u64 tx_vlan_packets;
201 	u64 rx_vlan_packets;
202 	u64 napi_poll_isr;
203 	u64 napi_poll_txtimer;
204 };
205 
206 struct xlgmac_ring_buf {
207 	struct sk_buff *skb;
208 	dma_addr_t skb_dma;
209 	unsigned int skb_len;
210 };
211 
212 /* Common Tx and Rx DMA hardware descriptor */
213 struct xlgmac_dma_desc {
214 	__le32 desc0;
215 	__le32 desc1;
216 	__le32 desc2;
217 	__le32 desc3;
218 };
219 
220 /* Page allocation related values */
221 struct xlgmac_page_alloc {
222 	struct page *pages;
223 	unsigned int pages_len;
224 	unsigned int pages_offset;
225 
226 	dma_addr_t pages_dma;
227 };
228 
229 /* Ring entry buffer data */
230 struct xlgmac_buffer_data {
231 	struct xlgmac_page_alloc pa;
232 	struct xlgmac_page_alloc pa_unmap;
233 
234 	dma_addr_t dma_base;
235 	unsigned long dma_off;
236 	unsigned int dma_len;
237 };
238 
239 /* Tx-related desc data */
240 struct xlgmac_tx_desc_data {
241 	unsigned int packets;		/* BQL packet count */
242 	unsigned int bytes;		/* BQL byte count */
243 };
244 
245 /* Rx-related desc data */
246 struct xlgmac_rx_desc_data {
247 	struct xlgmac_buffer_data hdr;	/* Header locations */
248 	struct xlgmac_buffer_data buf;	/* Payload locations */
249 
250 	unsigned short hdr_len;		/* Length of received header */
251 	unsigned short len;		/* Length of received packet */
252 };
253 
254 struct xlgmac_pkt_info {
255 	struct sk_buff *skb;
256 
257 	unsigned int attributes;
258 
259 	unsigned int errors;
260 
261 	/* descriptors needed for this packet */
262 	unsigned int desc_count;
263 	unsigned int length;
264 
265 	unsigned int tx_packets;
266 	unsigned int tx_bytes;
267 
268 	unsigned int header_len;
269 	unsigned int tcp_header_len;
270 	unsigned int tcp_payload_len;
271 	unsigned short mss;
272 
273 	unsigned short vlan_ctag;
274 
275 	u64 rx_tstamp;
276 
277 	u32 rss_hash;
278 	enum pkt_hash_types rss_hash_type;
279 };
280 
281 struct xlgmac_desc_data {
282 	/* dma_desc: Virtual address of descriptor
283 	 *  dma_desc_addr: DMA address of descriptor
284 	 */
285 	struct xlgmac_dma_desc *dma_desc;
286 	dma_addr_t dma_desc_addr;
287 
288 	/* skb: Virtual address of SKB
289 	 *  skb_dma: DMA address of SKB data
290 	 *  skb_dma_len: Length of SKB DMA area
291 	 */
292 	struct sk_buff *skb;
293 	dma_addr_t skb_dma;
294 	unsigned int skb_dma_len;
295 
296 	/* Tx/Rx -related data */
297 	struct xlgmac_tx_desc_data tx;
298 	struct xlgmac_rx_desc_data rx;
299 
300 	unsigned int mapped_as_page;
301 
302 	/* Incomplete receive save location.  If the budget is exhausted
303 	 * or the last descriptor (last normal descriptor or a following
304 	 * context descriptor) has not been DMA'd yet the current state
305 	 * of the receive processing needs to be saved.
306 	 */
307 	unsigned int state_saved;
308 	struct {
309 		struct sk_buff *skb;
310 		unsigned int len;
311 		unsigned int error;
312 	} state;
313 };
314 
315 struct xlgmac_ring {
316 	/* Per packet related information */
317 	struct xlgmac_pkt_info pkt_info;
318 
319 	/* Virtual/DMA addresses of DMA descriptor list and the total count */
320 	struct xlgmac_dma_desc *dma_desc_head;
321 	dma_addr_t dma_desc_head_addr;
322 	unsigned int dma_desc_count;
323 
324 	/* Array of descriptor data corresponding the DMA descriptor
325 	 * (always use the XLGMAC_GET_DESC_DATA macro to access this data)
326 	 */
327 	struct xlgmac_desc_data *desc_data_head;
328 
329 	/* Page allocation for RX buffers */
330 	struct xlgmac_page_alloc rx_hdr_pa;
331 	struct xlgmac_page_alloc rx_buf_pa;
332 
333 	/* Ring index values
334 	 *  cur   - Tx: index of descriptor to be used for current transfer
335 	 *          Rx: index of descriptor to check for packet availability
336 	 *  dirty - Tx: index of descriptor to check for transfer complete
337 	 *          Rx: index of descriptor to check for buffer reallocation
338 	 */
339 	unsigned int cur;
340 	unsigned int dirty;
341 
342 	/* Coalesce frame count used for interrupt bit setting */
343 	unsigned int coalesce_count;
344 
345 	union {
346 		struct {
347 			unsigned int xmit_more;
348 			unsigned int queue_stopped;
349 			unsigned short cur_mss;
350 			unsigned short cur_vlan_ctag;
351 		} tx;
352 	};
353 } ____cacheline_aligned;
354 
355 struct xlgmac_channel {
356 	char name[16];
357 
358 	/* Address of private data area for device */
359 	struct xlgmac_pdata *pdata;
360 
361 	/* Queue index and base address of queue's DMA registers */
362 	unsigned int queue_index;
363 	void __iomem *dma_regs;
364 
365 	/* Per channel interrupt irq number */
366 	int dma_irq;
367 	char dma_irq_name[IFNAMSIZ + 32];
368 
369 	/* Netdev related settings */
370 	struct napi_struct napi;
371 
372 	unsigned int saved_ier;
373 
374 	unsigned int tx_timer_active;
375 	struct timer_list tx_timer;
376 
377 	struct xlgmac_ring *tx_ring;
378 	struct xlgmac_ring *rx_ring;
379 } ____cacheline_aligned;
380 
381 struct xlgmac_desc_ops {
382 	int (*alloc_channels_and_rings)(struct xlgmac_pdata *pdata);
383 	void (*free_channels_and_rings)(struct xlgmac_pdata *pdata);
384 	int (*map_tx_skb)(struct xlgmac_channel *channel,
385 			  struct sk_buff *skb);
386 	int (*map_rx_buffer)(struct xlgmac_pdata *pdata,
387 			     struct xlgmac_ring *ring,
388 			struct xlgmac_desc_data *desc_data);
389 	void (*unmap_desc_data)(struct xlgmac_pdata *pdata,
390 				struct xlgmac_desc_data *desc_data);
391 	void (*tx_desc_init)(struct xlgmac_pdata *pdata);
392 	void (*rx_desc_init)(struct xlgmac_pdata *pdata);
393 };
394 
395 struct xlgmac_hw_ops {
396 	int (*init)(struct xlgmac_pdata *pdata);
397 	int (*exit)(struct xlgmac_pdata *pdata);
398 
399 	int (*tx_complete)(struct xlgmac_dma_desc *dma_desc);
400 
401 	void (*enable_tx)(struct xlgmac_pdata *pdata);
402 	void (*disable_tx)(struct xlgmac_pdata *pdata);
403 	void (*enable_rx)(struct xlgmac_pdata *pdata);
404 	void (*disable_rx)(struct xlgmac_pdata *pdata);
405 
406 	int (*enable_int)(struct xlgmac_channel *channel,
407 			  enum xlgmac_int int_id);
408 	int (*disable_int)(struct xlgmac_channel *channel,
409 			   enum xlgmac_int int_id);
410 	void (*dev_xmit)(struct xlgmac_channel *channel);
411 	int (*dev_read)(struct xlgmac_channel *channel);
412 
413 	int (*set_mac_address)(struct xlgmac_pdata *pdata, const u8 *addr);
414 	int (*config_rx_mode)(struct xlgmac_pdata *pdata);
415 	int (*enable_rx_csum)(struct xlgmac_pdata *pdata);
416 	int (*disable_rx_csum)(struct xlgmac_pdata *pdata);
417 
418 	/* For MII speed configuration */
419 	int (*set_xlgmii_25000_speed)(struct xlgmac_pdata *pdata);
420 	int (*set_xlgmii_40000_speed)(struct xlgmac_pdata *pdata);
421 	int (*set_xlgmii_50000_speed)(struct xlgmac_pdata *pdata);
422 	int (*set_xlgmii_100000_speed)(struct xlgmac_pdata *pdata);
423 
424 	/* For descriptor related operation */
425 	void (*tx_desc_init)(struct xlgmac_channel *channel);
426 	void (*rx_desc_init)(struct xlgmac_channel *channel);
427 	void (*tx_desc_reset)(struct xlgmac_desc_data *desc_data);
428 	void (*rx_desc_reset)(struct xlgmac_pdata *pdata,
429 			      struct xlgmac_desc_data *desc_data,
430 			unsigned int index);
431 	int (*is_last_desc)(struct xlgmac_dma_desc *dma_desc);
432 	int (*is_context_desc)(struct xlgmac_dma_desc *dma_desc);
433 	void (*tx_start_xmit)(struct xlgmac_channel *channel,
434 			      struct xlgmac_ring *ring);
435 
436 	/* For Flow Control */
437 	int (*config_tx_flow_control)(struct xlgmac_pdata *pdata);
438 	int (*config_rx_flow_control)(struct xlgmac_pdata *pdata);
439 
440 	/* For Vlan related config */
441 	int (*enable_rx_vlan_stripping)(struct xlgmac_pdata *pdata);
442 	int (*disable_rx_vlan_stripping)(struct xlgmac_pdata *pdata);
443 	int (*enable_rx_vlan_filtering)(struct xlgmac_pdata *pdata);
444 	int (*disable_rx_vlan_filtering)(struct xlgmac_pdata *pdata);
445 	int (*update_vlan_hash_table)(struct xlgmac_pdata *pdata);
446 
447 	/* For RX coalescing */
448 	int (*config_rx_coalesce)(struct xlgmac_pdata *pdata);
449 	int (*config_tx_coalesce)(struct xlgmac_pdata *pdata);
450 	unsigned int (*usec_to_riwt)(struct xlgmac_pdata *pdata,
451 				     unsigned int usec);
452 	unsigned int (*riwt_to_usec)(struct xlgmac_pdata *pdata,
453 				     unsigned int riwt);
454 
455 	/* For RX and TX threshold config */
456 	int (*config_rx_threshold)(struct xlgmac_pdata *pdata,
457 				   unsigned int val);
458 	int (*config_tx_threshold)(struct xlgmac_pdata *pdata,
459 				   unsigned int val);
460 
461 	/* For RX and TX Store and Forward Mode config */
462 	int (*config_rsf_mode)(struct xlgmac_pdata *pdata,
463 			       unsigned int val);
464 	int (*config_tsf_mode)(struct xlgmac_pdata *pdata,
465 			       unsigned int val);
466 
467 	/* For TX DMA Operate on Second Frame config */
468 	int (*config_osp_mode)(struct xlgmac_pdata *pdata);
469 
470 	/* For RX and TX PBL config */
471 	int (*config_rx_pbl_val)(struct xlgmac_pdata *pdata);
472 	int (*get_rx_pbl_val)(struct xlgmac_pdata *pdata);
473 	int (*config_tx_pbl_val)(struct xlgmac_pdata *pdata);
474 	int (*get_tx_pbl_val)(struct xlgmac_pdata *pdata);
475 	int (*config_pblx8)(struct xlgmac_pdata *pdata);
476 
477 	/* For MMC statistics */
478 	void (*rx_mmc_int)(struct xlgmac_pdata *pdata);
479 	void (*tx_mmc_int)(struct xlgmac_pdata *pdata);
480 	void (*read_mmc_stats)(struct xlgmac_pdata *pdata);
481 
482 	/* For Receive Side Scaling */
483 	int (*enable_rss)(struct xlgmac_pdata *pdata);
484 	int (*disable_rss)(struct xlgmac_pdata *pdata);
485 	int (*set_rss_hash_key)(struct xlgmac_pdata *pdata,
486 				const u8 *key);
487 	int (*set_rss_lookup_table)(struct xlgmac_pdata *pdata,
488 				    const u32 *table);
489 };
490 
491 /* This structure contains flags that indicate what hardware features
492  * or configurations are present in the device.
493  */
494 struct xlgmac_hw_features {
495 	/* HW Version */
496 	unsigned int version;
497 
498 	/* HW Feature Register0 */
499 	unsigned int phyifsel;		/* PHY interface support */
500 	unsigned int vlhash;		/* VLAN Hash Filter */
501 	unsigned int sma;		/* SMA(MDIO) Interface */
502 	unsigned int rwk;		/* PMT remote wake-up packet */
503 	unsigned int mgk;		/* PMT magic packet */
504 	unsigned int mmc;		/* RMON module */
505 	unsigned int aoe;		/* ARP Offload */
506 	unsigned int ts;		/* IEEE 1588-2008 Advanced Timestamp */
507 	unsigned int eee;		/* Energy Efficient Ethernet */
508 	unsigned int tx_coe;		/* Tx Checksum Offload */
509 	unsigned int rx_coe;		/* Rx Checksum Offload */
510 	unsigned int addn_mac;		/* Additional MAC Addresses */
511 	unsigned int ts_src;		/* Timestamp Source */
512 	unsigned int sa_vlan_ins;	/* Source Address or VLAN Insertion */
513 
514 	/* HW Feature Register1 */
515 	unsigned int rx_fifo_size;	/* MTL Receive FIFO Size */
516 	unsigned int tx_fifo_size;	/* MTL Transmit FIFO Size */
517 	unsigned int adv_ts_hi;		/* Advance Timestamping High Word */
518 	unsigned int dma_width;		/* DMA width */
519 	unsigned int dcb;		/* DCB Feature */
520 	unsigned int sph;		/* Split Header Feature */
521 	unsigned int tso;		/* TCP Segmentation Offload */
522 	unsigned int dma_debug;		/* DMA Debug Registers */
523 	unsigned int rss;		/* Receive Side Scaling */
524 	unsigned int tc_cnt;		/* Number of Traffic Classes */
525 	unsigned int hash_table_size;	/* Hash Table Size */
526 	unsigned int l3l4_filter_num;	/* Number of L3-L4 Filters */
527 
528 	/* HW Feature Register2 */
529 	unsigned int rx_q_cnt;		/* Number of MTL Receive Queues */
530 	unsigned int tx_q_cnt;		/* Number of MTL Transmit Queues */
531 	unsigned int rx_ch_cnt;		/* Number of DMA Receive Channels */
532 	unsigned int tx_ch_cnt;		/* Number of DMA Transmit Channels */
533 	unsigned int pps_out_num;	/* Number of PPS outputs */
534 	unsigned int aux_snap_num;	/* Number of Aux snapshot inputs */
535 };
536 
537 struct xlgmac_resources {
538 	void __iomem *addr;
539 	int irq;
540 };
541 
542 struct xlgmac_pdata {
543 	struct net_device *netdev;
544 	struct device *dev;
545 
546 	struct xlgmac_hw_ops hw_ops;
547 	struct xlgmac_desc_ops desc_ops;
548 
549 	/* Device statistics */
550 	struct xlgmac_stats stats;
551 
552 	u32 msg_enable;
553 
554 	/* MAC registers base */
555 	void __iomem *mac_regs;
556 
557 	/* Hardware features of the device */
558 	struct xlgmac_hw_features hw_feat;
559 
560 	struct work_struct restart_work;
561 
562 	/* Rings for Tx/Rx on a DMA channel */
563 	struct xlgmac_channel *channel_head;
564 	unsigned int channel_count;
565 	unsigned int tx_ring_count;
566 	unsigned int rx_ring_count;
567 	unsigned int tx_desc_count;
568 	unsigned int rx_desc_count;
569 	unsigned int tx_q_count;
570 	unsigned int rx_q_count;
571 
572 	/* Tx/Rx common settings */
573 	unsigned int pblx8;
574 
575 	/* Tx settings */
576 	unsigned int tx_sf_mode;
577 	unsigned int tx_threshold;
578 	unsigned int tx_pbl;
579 	unsigned int tx_osp_mode;
580 
581 	/* Rx settings */
582 	unsigned int rx_sf_mode;
583 	unsigned int rx_threshold;
584 	unsigned int rx_pbl;
585 
586 	/* Tx coalescing settings */
587 	unsigned int tx_usecs;
588 	unsigned int tx_frames;
589 
590 	/* Rx coalescing settings */
591 	unsigned int rx_riwt;
592 	unsigned int rx_usecs;
593 	unsigned int rx_frames;
594 
595 	/* Current Rx buffer size */
596 	unsigned int rx_buf_size;
597 
598 	/* Flow control settings */
599 	unsigned int tx_pause;
600 	unsigned int rx_pause;
601 
602 	/* Device interrupt number */
603 	int dev_irq;
604 	unsigned int per_channel_irq;
605 	int channel_irq[XLGMAC_MAX_DMA_CHANNELS];
606 
607 	/* Netdev related settings */
608 	unsigned char mac_addr[ETH_ALEN];
609 	netdev_features_t netdev_features;
610 	struct napi_struct napi;
611 
612 	/* Filtering support */
613 	unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
614 
615 	/* Device clocks */
616 	unsigned long sysclk_rate;
617 
618 	/* RSS addressing mutex */
619 	struct mutex rss_mutex;
620 
621 	/* Receive Side Scaling settings */
622 	u8 rss_key[XLGMAC_RSS_HASH_KEY_SIZE];
623 	u32 rss_table[XLGMAC_RSS_MAX_TABLE_SIZE];
624 	u32 rss_options;
625 
626 	int phy_speed;
627 
628 	char drv_name[32];
629 	char drv_ver[32];
630 };
631 
632 void xlgmac_init_desc_ops(struct xlgmac_desc_ops *desc_ops);
633 void xlgmac_init_hw_ops(struct xlgmac_hw_ops *hw_ops);
634 const struct net_device_ops *xlgmac_get_netdev_ops(void);
635 const struct ethtool_ops *xlgmac_get_ethtool_ops(void);
636 void xlgmac_dump_tx_desc(struct xlgmac_pdata *pdata,
637 			 struct xlgmac_ring *ring,
638 			 unsigned int idx,
639 			 unsigned int count,
640 			 unsigned int flag);
641 void xlgmac_dump_rx_desc(struct xlgmac_pdata *pdata,
642 			 struct xlgmac_ring *ring,
643 			 unsigned int idx);
644 void xlgmac_print_pkt(struct net_device *netdev,
645 		      struct sk_buff *skb, bool tx_rx);
646 void xlgmac_get_all_hw_features(struct xlgmac_pdata *pdata);
647 void xlgmac_print_all_hw_features(struct xlgmac_pdata *pdata);
648 int xlgmac_drv_probe(struct device *dev,
649 		     struct xlgmac_resources *res);
650 int xlgmac_drv_remove(struct device *dev);
651 
652 /* For debug prints */
653 #ifdef XLGMAC_DEBUG
654 #define XLGMAC_PR(fmt, args...) \
655 	pr_alert("[%s,%d]:" fmt, __func__, __LINE__, ## args)
656 #else
657 #define XLGMAC_PR(x...)		do { } while (0)
658 #endif
659 
660 #endif /* __DWC_XLGMAC_H__ */
661