165e0ace2SJie Deng /* Synopsys DesignWare Core Enterprise Ethernet (XLGMAC) Driver 265e0ace2SJie Deng * 365e0ace2SJie Deng * Copyright (c) 2017 Synopsys, Inc. (www.synopsys.com) 465e0ace2SJie Deng * 565e0ace2SJie Deng * This program is free software; you can redistribute it and/or modify it 665e0ace2SJie Deng * under the terms of the GNU General Public License as published by the 765e0ace2SJie Deng * Free Software Foundation; either version 2 of the License, or (at your 865e0ace2SJie Deng * option) any later version. 965e0ace2SJie Deng * 1065e0ace2SJie Deng * This Synopsys DWC XLGMAC software driver and associated documentation 1165e0ace2SJie Deng * (hereinafter the "Software") is an unsupported proprietary work of 1265e0ace2SJie Deng * Synopsys, Inc. unless otherwise expressly agreed to in writing between 1365e0ace2SJie Deng * Synopsys and you. The Software IS NOT an item of Licensed Software or a 1465e0ace2SJie Deng * Licensed Product under any End User Software License Agreement or 1565e0ace2SJie Deng * Agreement for Licensed Products with Synopsys or any supplement thereto. 1665e0ace2SJie Deng * Synopsys is a registered trademark of Synopsys, Inc. Other names included 1765e0ace2SJie Deng * in the SOFTWARE may be the trademarks of their respective owners. 1865e0ace2SJie Deng */ 1965e0ace2SJie Deng 2065e0ace2SJie Deng #ifndef __DWC_XLGMAC_REG_H__ 2165e0ace2SJie Deng #define __DWC_XLGMAC_REG_H__ 2265e0ace2SJie Deng 2365e0ace2SJie Deng /* MAC register offsets */ 2465e0ace2SJie Deng #define MAC_TCR 0x0000 2565e0ace2SJie Deng #define MAC_RCR 0x0004 2665e0ace2SJie Deng #define MAC_PFR 0x0008 2765e0ace2SJie Deng #define MAC_HTR0 0x0010 2865e0ace2SJie Deng #define MAC_VLANTR 0x0050 2965e0ace2SJie Deng #define MAC_VLANHTR 0x0058 3065e0ace2SJie Deng #define MAC_VLANIR 0x0060 3165e0ace2SJie Deng #define MAC_Q0TFCR 0x0070 3265e0ace2SJie Deng #define MAC_RFCR 0x0090 3365e0ace2SJie Deng #define MAC_RQC0R 0x00a0 3465e0ace2SJie Deng #define MAC_RQC1R 0x00a4 3565e0ace2SJie Deng #define MAC_RQC2R 0x00a8 3665e0ace2SJie Deng #define MAC_RQC3R 0x00ac 3765e0ace2SJie Deng #define MAC_ISR 0x00b0 3865e0ace2SJie Deng #define MAC_IER 0x00b4 3965e0ace2SJie Deng #define MAC_VR 0x0110 4065e0ace2SJie Deng #define MAC_HWF0R 0x011c 4165e0ace2SJie Deng #define MAC_HWF1R 0x0120 4265e0ace2SJie Deng #define MAC_HWF2R 0x0124 4365e0ace2SJie Deng #define MAC_MACA0HR 0x0300 4465e0ace2SJie Deng #define MAC_MACA0LR 0x0304 4565e0ace2SJie Deng #define MAC_MACA1HR 0x0308 4665e0ace2SJie Deng #define MAC_MACA1LR 0x030c 4765e0ace2SJie Deng #define MAC_RSSCR 0x0c80 4865e0ace2SJie Deng #define MAC_RSSAR 0x0c88 4965e0ace2SJie Deng #define MAC_RSSDR 0x0c8c 5065e0ace2SJie Deng 5165e0ace2SJie Deng #define MAC_QTFCR_INC 4 5265e0ace2SJie Deng #define MAC_MACA_INC 4 5365e0ace2SJie Deng #define MAC_HTR_INC 4 5465e0ace2SJie Deng #define MAC_RQC2_INC 4 5565e0ace2SJie Deng #define MAC_RQC2_Q_PER_REG 4 5665e0ace2SJie Deng 5765e0ace2SJie Deng /* MAC register entry bit positions and sizes */ 5865e0ace2SJie Deng #define MAC_HWF0R_ADDMACADRSEL_POS 18 5965e0ace2SJie Deng #define MAC_HWF0R_ADDMACADRSEL_LEN 5 6065e0ace2SJie Deng #define MAC_HWF0R_ARPOFFSEL_POS 9 6165e0ace2SJie Deng #define MAC_HWF0R_ARPOFFSEL_LEN 1 6265e0ace2SJie Deng #define MAC_HWF0R_EEESEL_POS 13 6365e0ace2SJie Deng #define MAC_HWF0R_EEESEL_LEN 1 6465e0ace2SJie Deng #define MAC_HWF0R_PHYIFSEL_POS 1 6565e0ace2SJie Deng #define MAC_HWF0R_PHYIFSEL_LEN 2 6665e0ace2SJie Deng #define MAC_HWF0R_MGKSEL_POS 7 6765e0ace2SJie Deng #define MAC_HWF0R_MGKSEL_LEN 1 6865e0ace2SJie Deng #define MAC_HWF0R_MMCSEL_POS 8 6965e0ace2SJie Deng #define MAC_HWF0R_MMCSEL_LEN 1 7065e0ace2SJie Deng #define MAC_HWF0R_RWKSEL_POS 6 7165e0ace2SJie Deng #define MAC_HWF0R_RWKSEL_LEN 1 7265e0ace2SJie Deng #define MAC_HWF0R_RXCOESEL_POS 16 7365e0ace2SJie Deng #define MAC_HWF0R_RXCOESEL_LEN 1 7465e0ace2SJie Deng #define MAC_HWF0R_SAVLANINS_POS 27 7565e0ace2SJie Deng #define MAC_HWF0R_SAVLANINS_LEN 1 7665e0ace2SJie Deng #define MAC_HWF0R_SMASEL_POS 5 7765e0ace2SJie Deng #define MAC_HWF0R_SMASEL_LEN 1 7865e0ace2SJie Deng #define MAC_HWF0R_TSSEL_POS 12 7965e0ace2SJie Deng #define MAC_HWF0R_TSSEL_LEN 1 8065e0ace2SJie Deng #define MAC_HWF0R_TSSTSSEL_POS 25 8165e0ace2SJie Deng #define MAC_HWF0R_TSSTSSEL_LEN 2 8265e0ace2SJie Deng #define MAC_HWF0R_TXCOESEL_POS 14 8365e0ace2SJie Deng #define MAC_HWF0R_TXCOESEL_LEN 1 8465e0ace2SJie Deng #define MAC_HWF0R_VLHASH_POS 4 8565e0ace2SJie Deng #define MAC_HWF0R_VLHASH_LEN 1 8665e0ace2SJie Deng #define MAC_HWF1R_ADDR64_POS 14 8765e0ace2SJie Deng #define MAC_HWF1R_ADDR64_LEN 2 8865e0ace2SJie Deng #define MAC_HWF1R_ADVTHWORD_POS 13 8965e0ace2SJie Deng #define MAC_HWF1R_ADVTHWORD_LEN 1 9065e0ace2SJie Deng #define MAC_HWF1R_DBGMEMA_POS 19 9165e0ace2SJie Deng #define MAC_HWF1R_DBGMEMA_LEN 1 9265e0ace2SJie Deng #define MAC_HWF1R_DCBEN_POS 16 9365e0ace2SJie Deng #define MAC_HWF1R_DCBEN_LEN 1 9465e0ace2SJie Deng #define MAC_HWF1R_HASHTBLSZ_POS 24 9565e0ace2SJie Deng #define MAC_HWF1R_HASHTBLSZ_LEN 3 9665e0ace2SJie Deng #define MAC_HWF1R_L3L4FNUM_POS 27 9765e0ace2SJie Deng #define MAC_HWF1R_L3L4FNUM_LEN 4 9865e0ace2SJie Deng #define MAC_HWF1R_NUMTC_POS 21 9965e0ace2SJie Deng #define MAC_HWF1R_NUMTC_LEN 3 10065e0ace2SJie Deng #define MAC_HWF1R_RSSEN_POS 20 10165e0ace2SJie Deng #define MAC_HWF1R_RSSEN_LEN 1 10265e0ace2SJie Deng #define MAC_HWF1R_RXFIFOSIZE_POS 0 10365e0ace2SJie Deng #define MAC_HWF1R_RXFIFOSIZE_LEN 5 10465e0ace2SJie Deng #define MAC_HWF1R_SPHEN_POS 17 10565e0ace2SJie Deng #define MAC_HWF1R_SPHEN_LEN 1 10665e0ace2SJie Deng #define MAC_HWF1R_TSOEN_POS 18 10765e0ace2SJie Deng #define MAC_HWF1R_TSOEN_LEN 1 10865e0ace2SJie Deng #define MAC_HWF1R_TXFIFOSIZE_POS 6 10965e0ace2SJie Deng #define MAC_HWF1R_TXFIFOSIZE_LEN 5 11065e0ace2SJie Deng #define MAC_HWF2R_AUXSNAPNUM_POS 28 11165e0ace2SJie Deng #define MAC_HWF2R_AUXSNAPNUM_LEN 3 11265e0ace2SJie Deng #define MAC_HWF2R_PPSOUTNUM_POS 24 11365e0ace2SJie Deng #define MAC_HWF2R_PPSOUTNUM_LEN 3 11465e0ace2SJie Deng #define MAC_HWF2R_RXCHCNT_POS 12 11565e0ace2SJie Deng #define MAC_HWF2R_RXCHCNT_LEN 4 11665e0ace2SJie Deng #define MAC_HWF2R_RXQCNT_POS 0 11765e0ace2SJie Deng #define MAC_HWF2R_RXQCNT_LEN 4 11865e0ace2SJie Deng #define MAC_HWF2R_TXCHCNT_POS 18 11965e0ace2SJie Deng #define MAC_HWF2R_TXCHCNT_LEN 4 12065e0ace2SJie Deng #define MAC_HWF2R_TXQCNT_POS 6 12165e0ace2SJie Deng #define MAC_HWF2R_TXQCNT_LEN 4 12265e0ace2SJie Deng #define MAC_IER_TSIE_POS 12 12365e0ace2SJie Deng #define MAC_IER_TSIE_LEN 1 12465e0ace2SJie Deng #define MAC_ISR_MMCRXIS_POS 9 12565e0ace2SJie Deng #define MAC_ISR_MMCRXIS_LEN 1 12665e0ace2SJie Deng #define MAC_ISR_MMCTXIS_POS 10 12765e0ace2SJie Deng #define MAC_ISR_MMCTXIS_LEN 1 12865e0ace2SJie Deng #define MAC_ISR_PMTIS_POS 4 12965e0ace2SJie Deng #define MAC_ISR_PMTIS_LEN 1 13065e0ace2SJie Deng #define MAC_ISR_TSIS_POS 12 13165e0ace2SJie Deng #define MAC_ISR_TSIS_LEN 1 13265e0ace2SJie Deng #define MAC_MACA1HR_AE_POS 31 13365e0ace2SJie Deng #define MAC_MACA1HR_AE_LEN 1 13465e0ace2SJie Deng #define MAC_PFR_HMC_POS 2 13565e0ace2SJie Deng #define MAC_PFR_HMC_LEN 1 13665e0ace2SJie Deng #define MAC_PFR_HPF_POS 10 13765e0ace2SJie Deng #define MAC_PFR_HPF_LEN 1 13865e0ace2SJie Deng #define MAC_PFR_HUC_POS 1 13965e0ace2SJie Deng #define MAC_PFR_HUC_LEN 1 14065e0ace2SJie Deng #define MAC_PFR_PM_POS 4 14165e0ace2SJie Deng #define MAC_PFR_PM_LEN 1 14265e0ace2SJie Deng #define MAC_PFR_PR_POS 0 14365e0ace2SJie Deng #define MAC_PFR_PR_LEN 1 14465e0ace2SJie Deng #define MAC_PFR_VTFE_POS 16 14565e0ace2SJie Deng #define MAC_PFR_VTFE_LEN 1 14665e0ace2SJie Deng #define MAC_Q0TFCR_PT_POS 16 14765e0ace2SJie Deng #define MAC_Q0TFCR_PT_LEN 16 14865e0ace2SJie Deng #define MAC_Q0TFCR_TFE_POS 1 14965e0ace2SJie Deng #define MAC_Q0TFCR_TFE_LEN 1 15065e0ace2SJie Deng #define MAC_RCR_ACS_POS 1 15165e0ace2SJie Deng #define MAC_RCR_ACS_LEN 1 15265e0ace2SJie Deng #define MAC_RCR_CST_POS 2 15365e0ace2SJie Deng #define MAC_RCR_CST_LEN 1 15465e0ace2SJie Deng #define MAC_RCR_DCRCC_POS 3 15565e0ace2SJie Deng #define MAC_RCR_DCRCC_LEN 1 15665e0ace2SJie Deng #define MAC_RCR_HDSMS_POS 12 15765e0ace2SJie Deng #define MAC_RCR_HDSMS_LEN 3 15865e0ace2SJie Deng #define MAC_RCR_IPC_POS 9 15965e0ace2SJie Deng #define MAC_RCR_IPC_LEN 1 16065e0ace2SJie Deng #define MAC_RCR_JE_POS 8 16165e0ace2SJie Deng #define MAC_RCR_JE_LEN 1 16265e0ace2SJie Deng #define MAC_RCR_LM_POS 10 16365e0ace2SJie Deng #define MAC_RCR_LM_LEN 1 16465e0ace2SJie Deng #define MAC_RCR_RE_POS 0 16565e0ace2SJie Deng #define MAC_RCR_RE_LEN 1 16665e0ace2SJie Deng #define MAC_RFCR_PFCE_POS 8 16765e0ace2SJie Deng #define MAC_RFCR_PFCE_LEN 1 16865e0ace2SJie Deng #define MAC_RFCR_RFE_POS 0 16965e0ace2SJie Deng #define MAC_RFCR_RFE_LEN 1 17065e0ace2SJie Deng #define MAC_RFCR_UP_POS 1 17165e0ace2SJie Deng #define MAC_RFCR_UP_LEN 1 17265e0ace2SJie Deng #define MAC_RQC0R_RXQ0EN_POS 0 17365e0ace2SJie Deng #define MAC_RQC0R_RXQ0EN_LEN 2 17465e0ace2SJie Deng #define MAC_RSSAR_ADDRT_POS 2 17565e0ace2SJie Deng #define MAC_RSSAR_ADDRT_LEN 1 17665e0ace2SJie Deng #define MAC_RSSAR_CT_POS 1 17765e0ace2SJie Deng #define MAC_RSSAR_CT_LEN 1 17865e0ace2SJie Deng #define MAC_RSSAR_OB_POS 0 17965e0ace2SJie Deng #define MAC_RSSAR_OB_LEN 1 18065e0ace2SJie Deng #define MAC_RSSAR_RSSIA_POS 8 18165e0ace2SJie Deng #define MAC_RSSAR_RSSIA_LEN 8 18265e0ace2SJie Deng #define MAC_RSSCR_IP2TE_POS 1 18365e0ace2SJie Deng #define MAC_RSSCR_IP2TE_LEN 1 18465e0ace2SJie Deng #define MAC_RSSCR_RSSE_POS 0 18565e0ace2SJie Deng #define MAC_RSSCR_RSSE_LEN 1 18665e0ace2SJie Deng #define MAC_RSSCR_TCP4TE_POS 2 18765e0ace2SJie Deng #define MAC_RSSCR_TCP4TE_LEN 1 18865e0ace2SJie Deng #define MAC_RSSCR_UDP4TE_POS 3 18965e0ace2SJie Deng #define MAC_RSSCR_UDP4TE_LEN 1 19065e0ace2SJie Deng #define MAC_RSSDR_DMCH_POS 0 19165e0ace2SJie Deng #define MAC_RSSDR_DMCH_LEN 4 19265e0ace2SJie Deng #define MAC_TCR_SS_POS 28 19365e0ace2SJie Deng #define MAC_TCR_SS_LEN 3 19465e0ace2SJie Deng #define MAC_TCR_TE_POS 0 19565e0ace2SJie Deng #define MAC_TCR_TE_LEN 1 19665e0ace2SJie Deng #define MAC_VLANHTR_VLHT_POS 0 19765e0ace2SJie Deng #define MAC_VLANHTR_VLHT_LEN 16 19865e0ace2SJie Deng #define MAC_VLANIR_VLTI_POS 20 19965e0ace2SJie Deng #define MAC_VLANIR_VLTI_LEN 1 20065e0ace2SJie Deng #define MAC_VLANIR_CSVL_POS 19 20165e0ace2SJie Deng #define MAC_VLANIR_CSVL_LEN 1 20265e0ace2SJie Deng #define MAC_VLANTR_DOVLTC_POS 20 20365e0ace2SJie Deng #define MAC_VLANTR_DOVLTC_LEN 1 20465e0ace2SJie Deng #define MAC_VLANTR_ERSVLM_POS 19 20565e0ace2SJie Deng #define MAC_VLANTR_ERSVLM_LEN 1 20665e0ace2SJie Deng #define MAC_VLANTR_ESVL_POS 18 20765e0ace2SJie Deng #define MAC_VLANTR_ESVL_LEN 1 20865e0ace2SJie Deng #define MAC_VLANTR_ETV_POS 16 20965e0ace2SJie Deng #define MAC_VLANTR_ETV_LEN 1 21065e0ace2SJie Deng #define MAC_VLANTR_EVLS_POS 21 21165e0ace2SJie Deng #define MAC_VLANTR_EVLS_LEN 2 21265e0ace2SJie Deng #define MAC_VLANTR_EVLRXS_POS 24 21365e0ace2SJie Deng #define MAC_VLANTR_EVLRXS_LEN 1 21465e0ace2SJie Deng #define MAC_VLANTR_VL_POS 0 21565e0ace2SJie Deng #define MAC_VLANTR_VL_LEN 16 21665e0ace2SJie Deng #define MAC_VLANTR_VTHM_POS 25 21765e0ace2SJie Deng #define MAC_VLANTR_VTHM_LEN 1 21865e0ace2SJie Deng #define MAC_VLANTR_VTIM_POS 17 21965e0ace2SJie Deng #define MAC_VLANTR_VTIM_LEN 1 22065e0ace2SJie Deng #define MAC_VR_DEVID_POS 8 22165e0ace2SJie Deng #define MAC_VR_DEVID_LEN 8 22265e0ace2SJie Deng #define MAC_VR_SNPSVER_POS 0 22365e0ace2SJie Deng #define MAC_VR_SNPSVER_LEN 8 22465e0ace2SJie Deng #define MAC_VR_USERVER_POS 16 22565e0ace2SJie Deng #define MAC_VR_USERVER_LEN 8 22665e0ace2SJie Deng 22765e0ace2SJie Deng /* MMC register offsets */ 22865e0ace2SJie Deng #define MMC_CR 0x0800 22965e0ace2SJie Deng #define MMC_RISR 0x0804 23065e0ace2SJie Deng #define MMC_TISR 0x0808 23165e0ace2SJie Deng #define MMC_RIER 0x080c 23265e0ace2SJie Deng #define MMC_TIER 0x0810 23365e0ace2SJie Deng #define MMC_TXOCTETCOUNT_GB_LO 0x0814 23465e0ace2SJie Deng #define MMC_TXFRAMECOUNT_GB_LO 0x081c 23565e0ace2SJie Deng #define MMC_TXBROADCASTFRAMES_G_LO 0x0824 23665e0ace2SJie Deng #define MMC_TXMULTICASTFRAMES_G_LO 0x082c 23765e0ace2SJie Deng #define MMC_TX64OCTETS_GB_LO 0x0834 23865e0ace2SJie Deng #define MMC_TX65TO127OCTETS_GB_LO 0x083c 23965e0ace2SJie Deng #define MMC_TX128TO255OCTETS_GB_LO 0x0844 24065e0ace2SJie Deng #define MMC_TX256TO511OCTETS_GB_LO 0x084c 24165e0ace2SJie Deng #define MMC_TX512TO1023OCTETS_GB_LO 0x0854 24265e0ace2SJie Deng #define MMC_TX1024TOMAXOCTETS_GB_LO 0x085c 24365e0ace2SJie Deng #define MMC_TXUNICASTFRAMES_GB_LO 0x0864 24465e0ace2SJie Deng #define MMC_TXMULTICASTFRAMES_GB_LO 0x086c 24565e0ace2SJie Deng #define MMC_TXBROADCASTFRAMES_GB_LO 0x0874 24665e0ace2SJie Deng #define MMC_TXUNDERFLOWERROR_LO 0x087c 24765e0ace2SJie Deng #define MMC_TXOCTETCOUNT_G_LO 0x0884 24865e0ace2SJie Deng #define MMC_TXFRAMECOUNT_G_LO 0x088c 24965e0ace2SJie Deng #define MMC_TXPAUSEFRAMES_LO 0x0894 25065e0ace2SJie Deng #define MMC_TXVLANFRAMES_G_LO 0x089c 25165e0ace2SJie Deng #define MMC_RXFRAMECOUNT_GB_LO 0x0900 25265e0ace2SJie Deng #define MMC_RXOCTETCOUNT_GB_LO 0x0908 25365e0ace2SJie Deng #define MMC_RXOCTETCOUNT_G_LO 0x0910 25465e0ace2SJie Deng #define MMC_RXBROADCASTFRAMES_G_LO 0x0918 25565e0ace2SJie Deng #define MMC_RXMULTICASTFRAMES_G_LO 0x0920 25665e0ace2SJie Deng #define MMC_RXCRCERROR_LO 0x0928 25765e0ace2SJie Deng #define MMC_RXRUNTERROR 0x0930 25865e0ace2SJie Deng #define MMC_RXJABBERERROR 0x0934 25965e0ace2SJie Deng #define MMC_RXUNDERSIZE_G 0x0938 26065e0ace2SJie Deng #define MMC_RXOVERSIZE_G 0x093c 26165e0ace2SJie Deng #define MMC_RX64OCTETS_GB_LO 0x0940 26265e0ace2SJie Deng #define MMC_RX65TO127OCTETS_GB_LO 0x0948 26365e0ace2SJie Deng #define MMC_RX128TO255OCTETS_GB_LO 0x0950 26465e0ace2SJie Deng #define MMC_RX256TO511OCTETS_GB_LO 0x0958 26565e0ace2SJie Deng #define MMC_RX512TO1023OCTETS_GB_LO 0x0960 26665e0ace2SJie Deng #define MMC_RX1024TOMAXOCTETS_GB_LO 0x0968 26765e0ace2SJie Deng #define MMC_RXUNICASTFRAMES_G_LO 0x0970 26865e0ace2SJie Deng #define MMC_RXLENGTHERROR_LO 0x0978 26965e0ace2SJie Deng #define MMC_RXOUTOFRANGETYPE_LO 0x0980 27065e0ace2SJie Deng #define MMC_RXPAUSEFRAMES_LO 0x0988 27165e0ace2SJie Deng #define MMC_RXFIFOOVERFLOW_LO 0x0990 27265e0ace2SJie Deng #define MMC_RXVLANFRAMES_GB_LO 0x0998 27365e0ace2SJie Deng #define MMC_RXWATCHDOGERROR 0x09a0 27465e0ace2SJie Deng 27565e0ace2SJie Deng /* MMC register entry bit positions and sizes */ 27665e0ace2SJie Deng #define MMC_CR_CR_POS 0 27765e0ace2SJie Deng #define MMC_CR_CR_LEN 1 27865e0ace2SJie Deng #define MMC_CR_CSR_POS 1 27965e0ace2SJie Deng #define MMC_CR_CSR_LEN 1 28065e0ace2SJie Deng #define MMC_CR_ROR_POS 2 28165e0ace2SJie Deng #define MMC_CR_ROR_LEN 1 28265e0ace2SJie Deng #define MMC_CR_MCF_POS 3 28365e0ace2SJie Deng #define MMC_CR_MCF_LEN 1 28465e0ace2SJie Deng #define MMC_CR_MCT_POS 4 28565e0ace2SJie Deng #define MMC_CR_MCT_LEN 2 28665e0ace2SJie Deng #define MMC_RIER_ALL_INTERRUPTS_POS 0 28765e0ace2SJie Deng #define MMC_RIER_ALL_INTERRUPTS_LEN 23 28865e0ace2SJie Deng #define MMC_RISR_RXFRAMECOUNT_GB_POS 0 28965e0ace2SJie Deng #define MMC_RISR_RXFRAMECOUNT_GB_LEN 1 29065e0ace2SJie Deng #define MMC_RISR_RXOCTETCOUNT_GB_POS 1 29165e0ace2SJie Deng #define MMC_RISR_RXOCTETCOUNT_GB_LEN 1 29265e0ace2SJie Deng #define MMC_RISR_RXOCTETCOUNT_G_POS 2 29365e0ace2SJie Deng #define MMC_RISR_RXOCTETCOUNT_G_LEN 1 29465e0ace2SJie Deng #define MMC_RISR_RXBROADCASTFRAMES_G_POS 3 29565e0ace2SJie Deng #define MMC_RISR_RXBROADCASTFRAMES_G_LEN 1 29665e0ace2SJie Deng #define MMC_RISR_RXMULTICASTFRAMES_G_POS 4 29765e0ace2SJie Deng #define MMC_RISR_RXMULTICASTFRAMES_G_LEN 1 29865e0ace2SJie Deng #define MMC_RISR_RXCRCERROR_POS 5 29965e0ace2SJie Deng #define MMC_RISR_RXCRCERROR_LEN 1 30065e0ace2SJie Deng #define MMC_RISR_RXRUNTERROR_POS 6 30165e0ace2SJie Deng #define MMC_RISR_RXRUNTERROR_LEN 1 30265e0ace2SJie Deng #define MMC_RISR_RXJABBERERROR_POS 7 30365e0ace2SJie Deng #define MMC_RISR_RXJABBERERROR_LEN 1 30465e0ace2SJie Deng #define MMC_RISR_RXUNDERSIZE_G_POS 8 30565e0ace2SJie Deng #define MMC_RISR_RXUNDERSIZE_G_LEN 1 30665e0ace2SJie Deng #define MMC_RISR_RXOVERSIZE_G_POS 9 30765e0ace2SJie Deng #define MMC_RISR_RXOVERSIZE_G_LEN 1 30865e0ace2SJie Deng #define MMC_RISR_RX64OCTETS_GB_POS 10 30965e0ace2SJie Deng #define MMC_RISR_RX64OCTETS_GB_LEN 1 31065e0ace2SJie Deng #define MMC_RISR_RX65TO127OCTETS_GB_POS 11 31165e0ace2SJie Deng #define MMC_RISR_RX65TO127OCTETS_GB_LEN 1 31265e0ace2SJie Deng #define MMC_RISR_RX128TO255OCTETS_GB_POS 12 31365e0ace2SJie Deng #define MMC_RISR_RX128TO255OCTETS_GB_LEN 1 31465e0ace2SJie Deng #define MMC_RISR_RX256TO511OCTETS_GB_POS 13 31565e0ace2SJie Deng #define MMC_RISR_RX256TO511OCTETS_GB_LEN 1 31665e0ace2SJie Deng #define MMC_RISR_RX512TO1023OCTETS_GB_POS 14 31765e0ace2SJie Deng #define MMC_RISR_RX512TO1023OCTETS_GB_LEN 1 31865e0ace2SJie Deng #define MMC_RISR_RX1024TOMAXOCTETS_GB_POS 15 31965e0ace2SJie Deng #define MMC_RISR_RX1024TOMAXOCTETS_GB_LEN 1 32065e0ace2SJie Deng #define MMC_RISR_RXUNICASTFRAMES_G_POS 16 32165e0ace2SJie Deng #define MMC_RISR_RXUNICASTFRAMES_G_LEN 1 32265e0ace2SJie Deng #define MMC_RISR_RXLENGTHERROR_POS 17 32365e0ace2SJie Deng #define MMC_RISR_RXLENGTHERROR_LEN 1 32465e0ace2SJie Deng #define MMC_RISR_RXOUTOFRANGETYPE_POS 18 32565e0ace2SJie Deng #define MMC_RISR_RXOUTOFRANGETYPE_LEN 1 32665e0ace2SJie Deng #define MMC_RISR_RXPAUSEFRAMES_POS 19 32765e0ace2SJie Deng #define MMC_RISR_RXPAUSEFRAMES_LEN 1 32865e0ace2SJie Deng #define MMC_RISR_RXFIFOOVERFLOW_POS 20 32965e0ace2SJie Deng #define MMC_RISR_RXFIFOOVERFLOW_LEN 1 33065e0ace2SJie Deng #define MMC_RISR_RXVLANFRAMES_GB_POS 21 33165e0ace2SJie Deng #define MMC_RISR_RXVLANFRAMES_GB_LEN 1 33265e0ace2SJie Deng #define MMC_RISR_RXWATCHDOGERROR_POS 22 33365e0ace2SJie Deng #define MMC_RISR_RXWATCHDOGERROR_LEN 1 33465e0ace2SJie Deng #define MMC_TIER_ALL_INTERRUPTS_POS 0 33565e0ace2SJie Deng #define MMC_TIER_ALL_INTERRUPTS_LEN 18 33665e0ace2SJie Deng #define MMC_TISR_TXOCTETCOUNT_GB_POS 0 33765e0ace2SJie Deng #define MMC_TISR_TXOCTETCOUNT_GB_LEN 1 33865e0ace2SJie Deng #define MMC_TISR_TXFRAMECOUNT_GB_POS 1 33965e0ace2SJie Deng #define MMC_TISR_TXFRAMECOUNT_GB_LEN 1 34065e0ace2SJie Deng #define MMC_TISR_TXBROADCASTFRAMES_G_POS 2 34165e0ace2SJie Deng #define MMC_TISR_TXBROADCASTFRAMES_G_LEN 1 34265e0ace2SJie Deng #define MMC_TISR_TXMULTICASTFRAMES_G_POS 3 34365e0ace2SJie Deng #define MMC_TISR_TXMULTICASTFRAMES_G_LEN 1 34465e0ace2SJie Deng #define MMC_TISR_TX64OCTETS_GB_POS 4 34565e0ace2SJie Deng #define MMC_TISR_TX64OCTETS_GB_LEN 1 34665e0ace2SJie Deng #define MMC_TISR_TX65TO127OCTETS_GB_POS 5 34765e0ace2SJie Deng #define MMC_TISR_TX65TO127OCTETS_GB_LEN 1 34865e0ace2SJie Deng #define MMC_TISR_TX128TO255OCTETS_GB_POS 6 34965e0ace2SJie Deng #define MMC_TISR_TX128TO255OCTETS_GB_LEN 1 35065e0ace2SJie Deng #define MMC_TISR_TX256TO511OCTETS_GB_POS 7 35165e0ace2SJie Deng #define MMC_TISR_TX256TO511OCTETS_GB_LEN 1 35265e0ace2SJie Deng #define MMC_TISR_TX512TO1023OCTETS_GB_POS 8 35365e0ace2SJie Deng #define MMC_TISR_TX512TO1023OCTETS_GB_LEN 1 35465e0ace2SJie Deng #define MMC_TISR_TX1024TOMAXOCTETS_GB_POS 9 35565e0ace2SJie Deng #define MMC_TISR_TX1024TOMAXOCTETS_GB_LEN 1 35665e0ace2SJie Deng #define MMC_TISR_TXUNICASTFRAMES_GB_POS 10 35765e0ace2SJie Deng #define MMC_TISR_TXUNICASTFRAMES_GB_LEN 1 35865e0ace2SJie Deng #define MMC_TISR_TXMULTICASTFRAMES_GB_POS 11 35965e0ace2SJie Deng #define MMC_TISR_TXMULTICASTFRAMES_GB_LEN 1 36065e0ace2SJie Deng #define MMC_TISR_TXBROADCASTFRAMES_GB_POS 12 36165e0ace2SJie Deng #define MMC_TISR_TXBROADCASTFRAMES_GB_LEN 1 36265e0ace2SJie Deng #define MMC_TISR_TXUNDERFLOWERROR_POS 13 36365e0ace2SJie Deng #define MMC_TISR_TXUNDERFLOWERROR_LEN 1 36465e0ace2SJie Deng #define MMC_TISR_TXOCTETCOUNT_G_POS 14 36565e0ace2SJie Deng #define MMC_TISR_TXOCTETCOUNT_G_LEN 1 36665e0ace2SJie Deng #define MMC_TISR_TXFRAMECOUNT_G_POS 15 36765e0ace2SJie Deng #define MMC_TISR_TXFRAMECOUNT_G_LEN 1 36865e0ace2SJie Deng #define MMC_TISR_TXPAUSEFRAMES_POS 16 36965e0ace2SJie Deng #define MMC_TISR_TXPAUSEFRAMES_LEN 1 37065e0ace2SJie Deng #define MMC_TISR_TXVLANFRAMES_G_POS 17 37165e0ace2SJie Deng #define MMC_TISR_TXVLANFRAMES_G_LEN 1 37265e0ace2SJie Deng 37365e0ace2SJie Deng /* MTL register offsets */ 37465e0ace2SJie Deng #define MTL_OMR 0x1000 37565e0ace2SJie Deng #define MTL_FDDR 0x1010 37665e0ace2SJie Deng #define MTL_RQDCM0R 0x1030 37765e0ace2SJie Deng 37865e0ace2SJie Deng #define MTL_RQDCM_INC 4 37965e0ace2SJie Deng #define MTL_RQDCM_Q_PER_REG 4 38065e0ace2SJie Deng 38165e0ace2SJie Deng /* MTL register entry bit positions and sizes */ 38265e0ace2SJie Deng #define MTL_OMR_ETSALG_POS 5 38365e0ace2SJie Deng #define MTL_OMR_ETSALG_LEN 2 38465e0ace2SJie Deng #define MTL_OMR_RAA_POS 2 38565e0ace2SJie Deng #define MTL_OMR_RAA_LEN 1 38665e0ace2SJie Deng 38765e0ace2SJie Deng /* MTL queue register offsets 38865e0ace2SJie Deng * Multiple queues can be active. The first queue has registers 38965e0ace2SJie Deng * that begin at 0x1100. Each subsequent queue has registers that 39065e0ace2SJie Deng * are accessed using an offset of 0x80 from the previous queue. 39165e0ace2SJie Deng */ 39265e0ace2SJie Deng #define MTL_Q_BASE 0x1100 39365e0ace2SJie Deng #define MTL_Q_INC 0x80 39465e0ace2SJie Deng 39565e0ace2SJie Deng #define MTL_Q_TQOMR 0x00 39665e0ace2SJie Deng #define MTL_Q_RQOMR 0x40 39765e0ace2SJie Deng #define MTL_Q_RQDR 0x48 39865e0ace2SJie Deng #define MTL_Q_RQFCR 0x50 39965e0ace2SJie Deng #define MTL_Q_IER 0x70 40065e0ace2SJie Deng #define MTL_Q_ISR 0x74 40165e0ace2SJie Deng 40265e0ace2SJie Deng /* MTL queue register entry bit positions and sizes */ 40365e0ace2SJie Deng #define MTL_Q_RQDR_PRXQ_POS 16 40465e0ace2SJie Deng #define MTL_Q_RQDR_PRXQ_LEN 14 40565e0ace2SJie Deng #define MTL_Q_RQDR_RXQSTS_POS 4 40665e0ace2SJie Deng #define MTL_Q_RQDR_RXQSTS_LEN 2 40765e0ace2SJie Deng #define MTL_Q_RQFCR_RFA_POS 1 40865e0ace2SJie Deng #define MTL_Q_RQFCR_RFA_LEN 6 40965e0ace2SJie Deng #define MTL_Q_RQFCR_RFD_POS 17 41065e0ace2SJie Deng #define MTL_Q_RQFCR_RFD_LEN 6 41165e0ace2SJie Deng #define MTL_Q_RQOMR_EHFC_POS 7 41265e0ace2SJie Deng #define MTL_Q_RQOMR_EHFC_LEN 1 41365e0ace2SJie Deng #define MTL_Q_RQOMR_RQS_POS 16 41465e0ace2SJie Deng #define MTL_Q_RQOMR_RQS_LEN 9 41565e0ace2SJie Deng #define MTL_Q_RQOMR_RSF_POS 5 41665e0ace2SJie Deng #define MTL_Q_RQOMR_RSF_LEN 1 41765e0ace2SJie Deng #define MTL_Q_RQOMR_FEP_POS 4 41865e0ace2SJie Deng #define MTL_Q_RQOMR_FEP_LEN 1 41965e0ace2SJie Deng #define MTL_Q_RQOMR_FUP_POS 3 42065e0ace2SJie Deng #define MTL_Q_RQOMR_FUP_LEN 1 42165e0ace2SJie Deng #define MTL_Q_RQOMR_RTC_POS 0 42265e0ace2SJie Deng #define MTL_Q_RQOMR_RTC_LEN 2 42365e0ace2SJie Deng #define MTL_Q_TQOMR_FTQ_POS 0 42465e0ace2SJie Deng #define MTL_Q_TQOMR_FTQ_LEN 1 42565e0ace2SJie Deng #define MTL_Q_TQOMR_Q2TCMAP_POS 8 42665e0ace2SJie Deng #define MTL_Q_TQOMR_Q2TCMAP_LEN 3 42765e0ace2SJie Deng #define MTL_Q_TQOMR_TQS_POS 16 42865e0ace2SJie Deng #define MTL_Q_TQOMR_TQS_LEN 10 42965e0ace2SJie Deng #define MTL_Q_TQOMR_TSF_POS 1 43065e0ace2SJie Deng #define MTL_Q_TQOMR_TSF_LEN 1 43165e0ace2SJie Deng #define MTL_Q_TQOMR_TTC_POS 4 43265e0ace2SJie Deng #define MTL_Q_TQOMR_TTC_LEN 3 43365e0ace2SJie Deng #define MTL_Q_TQOMR_TXQEN_POS 2 43465e0ace2SJie Deng #define MTL_Q_TQOMR_TXQEN_LEN 2 43565e0ace2SJie Deng 43665e0ace2SJie Deng /* MTL queue register value */ 43765e0ace2SJie Deng #define MTL_RSF_DISABLE 0x00 43865e0ace2SJie Deng #define MTL_RSF_ENABLE 0x01 43965e0ace2SJie Deng #define MTL_TSF_DISABLE 0x00 44065e0ace2SJie Deng #define MTL_TSF_ENABLE 0x01 44165e0ace2SJie Deng 44265e0ace2SJie Deng #define MTL_RX_THRESHOLD_64 0x00 44365e0ace2SJie Deng #define MTL_RX_THRESHOLD_96 0x02 44465e0ace2SJie Deng #define MTL_RX_THRESHOLD_128 0x03 44565e0ace2SJie Deng #define MTL_TX_THRESHOLD_64 0x00 44665e0ace2SJie Deng #define MTL_TX_THRESHOLD_96 0x02 44765e0ace2SJie Deng #define MTL_TX_THRESHOLD_128 0x03 44865e0ace2SJie Deng #define MTL_TX_THRESHOLD_192 0x04 44965e0ace2SJie Deng #define MTL_TX_THRESHOLD_256 0x05 45065e0ace2SJie Deng #define MTL_TX_THRESHOLD_384 0x06 45165e0ace2SJie Deng #define MTL_TX_THRESHOLD_512 0x07 45265e0ace2SJie Deng 45365e0ace2SJie Deng #define MTL_ETSALG_WRR 0x00 45465e0ace2SJie Deng #define MTL_ETSALG_WFQ 0x01 45565e0ace2SJie Deng #define MTL_ETSALG_DWRR 0x02 45665e0ace2SJie Deng #define MTL_RAA_SP 0x00 45765e0ace2SJie Deng #define MTL_RAA_WSP 0x01 45865e0ace2SJie Deng 45965e0ace2SJie Deng #define MTL_Q_DISABLED 0x00 46065e0ace2SJie Deng #define MTL_Q_ENABLED 0x02 46165e0ace2SJie Deng 46265e0ace2SJie Deng #define MTL_RQDCM0R_Q0MDMACH 0x0 46365e0ace2SJie Deng #define MTL_RQDCM0R_Q1MDMACH 0x00000100 46465e0ace2SJie Deng #define MTL_RQDCM0R_Q2MDMACH 0x00020000 46565e0ace2SJie Deng #define MTL_RQDCM0R_Q3MDMACH 0x03000000 46665e0ace2SJie Deng #define MTL_RQDCM1R_Q4MDMACH 0x00000004 46765e0ace2SJie Deng #define MTL_RQDCM1R_Q5MDMACH 0x00000500 46865e0ace2SJie Deng #define MTL_RQDCM1R_Q6MDMACH 0x00060000 46965e0ace2SJie Deng #define MTL_RQDCM1R_Q7MDMACH 0x07000000 47065e0ace2SJie Deng #define MTL_RQDCM2R_Q8MDMACH 0x00000008 47165e0ace2SJie Deng #define MTL_RQDCM2R_Q9MDMACH 0x00000900 47265e0ace2SJie Deng #define MTL_RQDCM2R_Q10MDMACH 0x000A0000 47365e0ace2SJie Deng #define MTL_RQDCM2R_Q11MDMACH 0x0B000000 47465e0ace2SJie Deng 47565e0ace2SJie Deng /* MTL traffic class register offsets 47665e0ace2SJie Deng * Multiple traffic classes can be active. The first class has registers 47765e0ace2SJie Deng * that begin at 0x1100. Each subsequent queue has registers that 47865e0ace2SJie Deng * are accessed using an offset of 0x80 from the previous queue. 47965e0ace2SJie Deng */ 48065e0ace2SJie Deng #define MTL_TC_BASE MTL_Q_BASE 48165e0ace2SJie Deng #define MTL_TC_INC MTL_Q_INC 48265e0ace2SJie Deng 48365e0ace2SJie Deng #define MTL_TC_ETSCR 0x10 48465e0ace2SJie Deng #define MTL_TC_ETSSR 0x14 48565e0ace2SJie Deng #define MTL_TC_QWR 0x18 48665e0ace2SJie Deng 48765e0ace2SJie Deng /* MTL traffic class register entry bit positions and sizes */ 48865e0ace2SJie Deng #define MTL_TC_ETSCR_TSA_POS 0 48965e0ace2SJie Deng #define MTL_TC_ETSCR_TSA_LEN 2 49065e0ace2SJie Deng #define MTL_TC_QWR_QW_POS 0 49165e0ace2SJie Deng #define MTL_TC_QWR_QW_LEN 21 49265e0ace2SJie Deng 49365e0ace2SJie Deng /* MTL traffic class register value */ 49465e0ace2SJie Deng #define MTL_TSA_SP 0x00 49565e0ace2SJie Deng #define MTL_TSA_ETS 0x02 49665e0ace2SJie Deng 49765e0ace2SJie Deng /* DMA register offsets */ 49865e0ace2SJie Deng #define DMA_MR 0x3000 49965e0ace2SJie Deng #define DMA_SBMR 0x3004 50065e0ace2SJie Deng #define DMA_ISR 0x3008 50165e0ace2SJie Deng #define DMA_DSR0 0x3020 50265e0ace2SJie Deng #define DMA_DSR1 0x3024 50365e0ace2SJie Deng 50465e0ace2SJie Deng /* DMA register entry bit positions and sizes */ 50565e0ace2SJie Deng #define DMA_ISR_MACIS_POS 17 50665e0ace2SJie Deng #define DMA_ISR_MACIS_LEN 1 50765e0ace2SJie Deng #define DMA_ISR_MTLIS_POS 16 50865e0ace2SJie Deng #define DMA_ISR_MTLIS_LEN 1 50965e0ace2SJie Deng #define DMA_MR_SWR_POS 0 51065e0ace2SJie Deng #define DMA_MR_SWR_LEN 1 51165e0ace2SJie Deng #define DMA_SBMR_EAME_POS 11 51265e0ace2SJie Deng #define DMA_SBMR_EAME_LEN 1 51365e0ace2SJie Deng #define DMA_SBMR_BLEN_64_POS 5 51465e0ace2SJie Deng #define DMA_SBMR_BLEN_64_LEN 1 51565e0ace2SJie Deng #define DMA_SBMR_BLEN_128_POS 6 51665e0ace2SJie Deng #define DMA_SBMR_BLEN_128_LEN 1 51765e0ace2SJie Deng #define DMA_SBMR_BLEN_256_POS 7 51865e0ace2SJie Deng #define DMA_SBMR_BLEN_256_LEN 1 51965e0ace2SJie Deng #define DMA_SBMR_UNDEF_POS 0 52065e0ace2SJie Deng #define DMA_SBMR_UNDEF_LEN 1 52165e0ace2SJie Deng 52265e0ace2SJie Deng /* DMA register values */ 52365e0ace2SJie Deng #define DMA_DSR_RPS_LEN 4 52465e0ace2SJie Deng #define DMA_DSR_TPS_LEN 4 52565e0ace2SJie Deng #define DMA_DSR_Q_LEN (DMA_DSR_RPS_LEN + DMA_DSR_TPS_LEN) 52665e0ace2SJie Deng #define DMA_DSR0_TPS_START 12 52765e0ace2SJie Deng #define DMA_DSRX_FIRST_QUEUE 3 52865e0ace2SJie Deng #define DMA_DSRX_INC 4 52965e0ace2SJie Deng #define DMA_DSRX_QPR 4 53065e0ace2SJie Deng #define DMA_DSRX_TPS_START 4 53165e0ace2SJie Deng #define DMA_TPS_STOPPED 0x00 53265e0ace2SJie Deng #define DMA_TPS_SUSPENDED 0x06 53365e0ace2SJie Deng 53465e0ace2SJie Deng /* DMA channel register offsets 53565e0ace2SJie Deng * Multiple channels can be active. The first channel has registers 53665e0ace2SJie Deng * that begin at 0x3100. Each subsequent channel has registers that 53765e0ace2SJie Deng * are accessed using an offset of 0x80 from the previous channel. 53865e0ace2SJie Deng */ 53965e0ace2SJie Deng #define DMA_CH_BASE 0x3100 54065e0ace2SJie Deng #define DMA_CH_INC 0x80 54165e0ace2SJie Deng 54265e0ace2SJie Deng #define DMA_CH_CR 0x00 54365e0ace2SJie Deng #define DMA_CH_TCR 0x04 54465e0ace2SJie Deng #define DMA_CH_RCR 0x08 54565e0ace2SJie Deng #define DMA_CH_TDLR_HI 0x10 54665e0ace2SJie Deng #define DMA_CH_TDLR_LO 0x14 54765e0ace2SJie Deng #define DMA_CH_RDLR_HI 0x18 54865e0ace2SJie Deng #define DMA_CH_RDLR_LO 0x1c 54965e0ace2SJie Deng #define DMA_CH_TDTR_LO 0x24 55065e0ace2SJie Deng #define DMA_CH_RDTR_LO 0x2c 55165e0ace2SJie Deng #define DMA_CH_TDRLR 0x30 55265e0ace2SJie Deng #define DMA_CH_RDRLR 0x34 55365e0ace2SJie Deng #define DMA_CH_IER 0x38 55465e0ace2SJie Deng #define DMA_CH_RIWT 0x3c 55565e0ace2SJie Deng #define DMA_CH_SR 0x60 55665e0ace2SJie Deng 55765e0ace2SJie Deng /* DMA channel register entry bit positions and sizes */ 55865e0ace2SJie Deng #define DMA_CH_CR_PBLX8_POS 16 55965e0ace2SJie Deng #define DMA_CH_CR_PBLX8_LEN 1 56065e0ace2SJie Deng #define DMA_CH_CR_SPH_POS 24 56165e0ace2SJie Deng #define DMA_CH_CR_SPH_LEN 1 56265e0ace2SJie Deng #define DMA_CH_IER_AIE_POS 15 56365e0ace2SJie Deng #define DMA_CH_IER_AIE_LEN 1 56465e0ace2SJie Deng #define DMA_CH_IER_FBEE_POS 12 56565e0ace2SJie Deng #define DMA_CH_IER_FBEE_LEN 1 56665e0ace2SJie Deng #define DMA_CH_IER_NIE_POS 16 56765e0ace2SJie Deng #define DMA_CH_IER_NIE_LEN 1 56865e0ace2SJie Deng #define DMA_CH_IER_RBUE_POS 7 56965e0ace2SJie Deng #define DMA_CH_IER_RBUE_LEN 1 57065e0ace2SJie Deng #define DMA_CH_IER_RIE_POS 6 57165e0ace2SJie Deng #define DMA_CH_IER_RIE_LEN 1 57265e0ace2SJie Deng #define DMA_CH_IER_RSE_POS 8 57365e0ace2SJie Deng #define DMA_CH_IER_RSE_LEN 1 57465e0ace2SJie Deng #define DMA_CH_IER_TBUE_POS 2 57565e0ace2SJie Deng #define DMA_CH_IER_TBUE_LEN 1 57665e0ace2SJie Deng #define DMA_CH_IER_TIE_POS 0 57765e0ace2SJie Deng #define DMA_CH_IER_TIE_LEN 1 57865e0ace2SJie Deng #define DMA_CH_IER_TXSE_POS 1 57965e0ace2SJie Deng #define DMA_CH_IER_TXSE_LEN 1 58065e0ace2SJie Deng #define DMA_CH_RCR_PBL_POS 16 58165e0ace2SJie Deng #define DMA_CH_RCR_PBL_LEN 6 58265e0ace2SJie Deng #define DMA_CH_RCR_RBSZ_POS 1 58365e0ace2SJie Deng #define DMA_CH_RCR_RBSZ_LEN 14 58465e0ace2SJie Deng #define DMA_CH_RCR_SR_POS 0 58565e0ace2SJie Deng #define DMA_CH_RCR_SR_LEN 1 58665e0ace2SJie Deng #define DMA_CH_RIWT_RWT_POS 0 58765e0ace2SJie Deng #define DMA_CH_RIWT_RWT_LEN 8 58865e0ace2SJie Deng #define DMA_CH_SR_FBE_POS 12 58965e0ace2SJie Deng #define DMA_CH_SR_FBE_LEN 1 59065e0ace2SJie Deng #define DMA_CH_SR_RBU_POS 7 59165e0ace2SJie Deng #define DMA_CH_SR_RBU_LEN 1 59265e0ace2SJie Deng #define DMA_CH_SR_RI_POS 6 59365e0ace2SJie Deng #define DMA_CH_SR_RI_LEN 1 59465e0ace2SJie Deng #define DMA_CH_SR_RPS_POS 8 59565e0ace2SJie Deng #define DMA_CH_SR_RPS_LEN 1 59665e0ace2SJie Deng #define DMA_CH_SR_TBU_POS 2 59765e0ace2SJie Deng #define DMA_CH_SR_TBU_LEN 1 59865e0ace2SJie Deng #define DMA_CH_SR_TI_POS 0 59965e0ace2SJie Deng #define DMA_CH_SR_TI_LEN 1 60065e0ace2SJie Deng #define DMA_CH_SR_TPS_POS 1 60165e0ace2SJie Deng #define DMA_CH_SR_TPS_LEN 1 60265e0ace2SJie Deng #define DMA_CH_TCR_OSP_POS 4 60365e0ace2SJie Deng #define DMA_CH_TCR_OSP_LEN 1 60465e0ace2SJie Deng #define DMA_CH_TCR_PBL_POS 16 60565e0ace2SJie Deng #define DMA_CH_TCR_PBL_LEN 6 60665e0ace2SJie Deng #define DMA_CH_TCR_ST_POS 0 60765e0ace2SJie Deng #define DMA_CH_TCR_ST_LEN 1 60865e0ace2SJie Deng #define DMA_CH_TCR_TSE_POS 12 60965e0ace2SJie Deng #define DMA_CH_TCR_TSE_LEN 1 61065e0ace2SJie Deng 61165e0ace2SJie Deng /* DMA channel register values */ 61265e0ace2SJie Deng #define DMA_OSP_DISABLE 0x00 61365e0ace2SJie Deng #define DMA_OSP_ENABLE 0x01 61465e0ace2SJie Deng #define DMA_PBL_1 1 61565e0ace2SJie Deng #define DMA_PBL_2 2 61665e0ace2SJie Deng #define DMA_PBL_4 4 61765e0ace2SJie Deng #define DMA_PBL_8 8 61865e0ace2SJie Deng #define DMA_PBL_16 16 61965e0ace2SJie Deng #define DMA_PBL_32 32 62065e0ace2SJie Deng #define DMA_PBL_64 64 62165e0ace2SJie Deng #define DMA_PBL_128 128 62265e0ace2SJie Deng #define DMA_PBL_256 256 62365e0ace2SJie Deng #define DMA_PBL_X8_DISABLE 0x00 62465e0ace2SJie Deng #define DMA_PBL_X8_ENABLE 0x01 62565e0ace2SJie Deng 62665e0ace2SJie Deng /* Descriptor/Packet entry bit positions and sizes */ 62765e0ace2SJie Deng #define RX_PACKET_ERRORS_CRC_POS 2 62865e0ace2SJie Deng #define RX_PACKET_ERRORS_CRC_LEN 1 62965e0ace2SJie Deng #define RX_PACKET_ERRORS_FRAME_POS 3 63065e0ace2SJie Deng #define RX_PACKET_ERRORS_FRAME_LEN 1 63165e0ace2SJie Deng #define RX_PACKET_ERRORS_LENGTH_POS 0 63265e0ace2SJie Deng #define RX_PACKET_ERRORS_LENGTH_LEN 1 63365e0ace2SJie Deng #define RX_PACKET_ERRORS_OVERRUN_POS 1 63465e0ace2SJie Deng #define RX_PACKET_ERRORS_OVERRUN_LEN 1 63565e0ace2SJie Deng 63665e0ace2SJie Deng #define RX_PACKET_ATTRIBUTES_CSUM_DONE_POS 0 63765e0ace2SJie Deng #define RX_PACKET_ATTRIBUTES_CSUM_DONE_LEN 1 63865e0ace2SJie Deng #define RX_PACKET_ATTRIBUTES_VLAN_CTAG_POS 1 63965e0ace2SJie Deng #define RX_PACKET_ATTRIBUTES_VLAN_CTAG_LEN 1 64065e0ace2SJie Deng #define RX_PACKET_ATTRIBUTES_INCOMPLETE_POS 2 64165e0ace2SJie Deng #define RX_PACKET_ATTRIBUTES_INCOMPLETE_LEN 1 64265e0ace2SJie Deng #define RX_PACKET_ATTRIBUTES_CONTEXT_NEXT_POS 3 64365e0ace2SJie Deng #define RX_PACKET_ATTRIBUTES_CONTEXT_NEXT_LEN 1 64465e0ace2SJie Deng #define RX_PACKET_ATTRIBUTES_CONTEXT_POS 4 64565e0ace2SJie Deng #define RX_PACKET_ATTRIBUTES_CONTEXT_LEN 1 64665e0ace2SJie Deng #define RX_PACKET_ATTRIBUTES_RX_TSTAMP_POS 5 64765e0ace2SJie Deng #define RX_PACKET_ATTRIBUTES_RX_TSTAMP_LEN 1 64865e0ace2SJie Deng #define RX_PACKET_ATTRIBUTES_RSS_HASH_POS 6 64965e0ace2SJie Deng #define RX_PACKET_ATTRIBUTES_RSS_HASH_LEN 1 65065e0ace2SJie Deng 65165e0ace2SJie Deng #define RX_NORMAL_DESC0_OVT_POS 0 65265e0ace2SJie Deng #define RX_NORMAL_DESC0_OVT_LEN 16 65365e0ace2SJie Deng #define RX_NORMAL_DESC2_HL_POS 0 65465e0ace2SJie Deng #define RX_NORMAL_DESC2_HL_LEN 10 65565e0ace2SJie Deng #define RX_NORMAL_DESC3_CDA_POS 27 65665e0ace2SJie Deng #define RX_NORMAL_DESC3_CDA_LEN 1 65765e0ace2SJie Deng #define RX_NORMAL_DESC3_CTXT_POS 30 65865e0ace2SJie Deng #define RX_NORMAL_DESC3_CTXT_LEN 1 65965e0ace2SJie Deng #define RX_NORMAL_DESC3_ES_POS 15 66065e0ace2SJie Deng #define RX_NORMAL_DESC3_ES_LEN 1 66165e0ace2SJie Deng #define RX_NORMAL_DESC3_ETLT_POS 16 66265e0ace2SJie Deng #define RX_NORMAL_DESC3_ETLT_LEN 4 66365e0ace2SJie Deng #define RX_NORMAL_DESC3_FD_POS 29 66465e0ace2SJie Deng #define RX_NORMAL_DESC3_FD_LEN 1 66565e0ace2SJie Deng #define RX_NORMAL_DESC3_INTE_POS 30 66665e0ace2SJie Deng #define RX_NORMAL_DESC3_INTE_LEN 1 66765e0ace2SJie Deng #define RX_NORMAL_DESC3_L34T_POS 20 66865e0ace2SJie Deng #define RX_NORMAL_DESC3_L34T_LEN 4 66965e0ace2SJie Deng #define RX_NORMAL_DESC3_LD_POS 28 67065e0ace2SJie Deng #define RX_NORMAL_DESC3_LD_LEN 1 67165e0ace2SJie Deng #define RX_NORMAL_DESC3_OWN_POS 31 67265e0ace2SJie Deng #define RX_NORMAL_DESC3_OWN_LEN 1 67365e0ace2SJie Deng #define RX_NORMAL_DESC3_PL_POS 0 67465e0ace2SJie Deng #define RX_NORMAL_DESC3_PL_LEN 14 67565e0ace2SJie Deng #define RX_NORMAL_DESC3_RSV_POS 26 67665e0ace2SJie Deng #define RX_NORMAL_DESC3_RSV_LEN 1 67765e0ace2SJie Deng 67865e0ace2SJie Deng #define RX_DESC3_L34T_IPV4_TCP 1 67965e0ace2SJie Deng #define RX_DESC3_L34T_IPV4_UDP 2 68065e0ace2SJie Deng #define RX_DESC3_L34T_IPV4_ICMP 3 68165e0ace2SJie Deng #define RX_DESC3_L34T_IPV6_TCP 9 68265e0ace2SJie Deng #define RX_DESC3_L34T_IPV6_UDP 10 68365e0ace2SJie Deng #define RX_DESC3_L34T_IPV6_ICMP 11 68465e0ace2SJie Deng 68565e0ace2SJie Deng #define RX_CONTEXT_DESC3_TSA_POS 4 68665e0ace2SJie Deng #define RX_CONTEXT_DESC3_TSA_LEN 1 68765e0ace2SJie Deng #define RX_CONTEXT_DESC3_TSD_POS 6 68865e0ace2SJie Deng #define RX_CONTEXT_DESC3_TSD_LEN 1 68965e0ace2SJie Deng 69065e0ace2SJie Deng #define TX_PACKET_ATTRIBUTES_CSUM_ENABLE_POS 0 69165e0ace2SJie Deng #define TX_PACKET_ATTRIBUTES_CSUM_ENABLE_LEN 1 69265e0ace2SJie Deng #define TX_PACKET_ATTRIBUTES_TSO_ENABLE_POS 1 69365e0ace2SJie Deng #define TX_PACKET_ATTRIBUTES_TSO_ENABLE_LEN 1 69465e0ace2SJie Deng #define TX_PACKET_ATTRIBUTES_VLAN_CTAG_POS 2 69565e0ace2SJie Deng #define TX_PACKET_ATTRIBUTES_VLAN_CTAG_LEN 1 69665e0ace2SJie Deng #define TX_PACKET_ATTRIBUTES_PTP_POS 3 69765e0ace2SJie Deng #define TX_PACKET_ATTRIBUTES_PTP_LEN 1 69865e0ace2SJie Deng 69965e0ace2SJie Deng #define TX_CONTEXT_DESC2_MSS_POS 0 70065e0ace2SJie Deng #define TX_CONTEXT_DESC2_MSS_LEN 15 70165e0ace2SJie Deng #define TX_CONTEXT_DESC3_CTXT_POS 30 70265e0ace2SJie Deng #define TX_CONTEXT_DESC3_CTXT_LEN 1 70365e0ace2SJie Deng #define TX_CONTEXT_DESC3_TCMSSV_POS 26 70465e0ace2SJie Deng #define TX_CONTEXT_DESC3_TCMSSV_LEN 1 70565e0ace2SJie Deng #define TX_CONTEXT_DESC3_VLTV_POS 16 70665e0ace2SJie Deng #define TX_CONTEXT_DESC3_VLTV_LEN 1 70765e0ace2SJie Deng #define TX_CONTEXT_DESC3_VT_POS 0 70865e0ace2SJie Deng #define TX_CONTEXT_DESC3_VT_LEN 16 70965e0ace2SJie Deng 71065e0ace2SJie Deng #define TX_NORMAL_DESC2_HL_B1L_POS 0 71165e0ace2SJie Deng #define TX_NORMAL_DESC2_HL_B1L_LEN 14 71265e0ace2SJie Deng #define TX_NORMAL_DESC2_IC_POS 31 71365e0ace2SJie Deng #define TX_NORMAL_DESC2_IC_LEN 1 71465e0ace2SJie Deng #define TX_NORMAL_DESC2_TTSE_POS 30 71565e0ace2SJie Deng #define TX_NORMAL_DESC2_TTSE_LEN 1 71665e0ace2SJie Deng #define TX_NORMAL_DESC2_VTIR_POS 14 71765e0ace2SJie Deng #define TX_NORMAL_DESC2_VTIR_LEN 2 71865e0ace2SJie Deng #define TX_NORMAL_DESC3_CIC_POS 16 71965e0ace2SJie Deng #define TX_NORMAL_DESC3_CIC_LEN 2 72065e0ace2SJie Deng #define TX_NORMAL_DESC3_CPC_POS 26 72165e0ace2SJie Deng #define TX_NORMAL_DESC3_CPC_LEN 2 72265e0ace2SJie Deng #define TX_NORMAL_DESC3_CTXT_POS 30 72365e0ace2SJie Deng #define TX_NORMAL_DESC3_CTXT_LEN 1 72465e0ace2SJie Deng #define TX_NORMAL_DESC3_FD_POS 29 72565e0ace2SJie Deng #define TX_NORMAL_DESC3_FD_LEN 1 72665e0ace2SJie Deng #define TX_NORMAL_DESC3_FL_POS 0 72765e0ace2SJie Deng #define TX_NORMAL_DESC3_FL_LEN 15 72865e0ace2SJie Deng #define TX_NORMAL_DESC3_LD_POS 28 72965e0ace2SJie Deng #define TX_NORMAL_DESC3_LD_LEN 1 73065e0ace2SJie Deng #define TX_NORMAL_DESC3_OWN_POS 31 73165e0ace2SJie Deng #define TX_NORMAL_DESC3_OWN_LEN 1 73265e0ace2SJie Deng #define TX_NORMAL_DESC3_TCPHDRLEN_POS 19 73365e0ace2SJie Deng #define TX_NORMAL_DESC3_TCPHDRLEN_LEN 4 73465e0ace2SJie Deng #define TX_NORMAL_DESC3_TCPPL_POS 0 73565e0ace2SJie Deng #define TX_NORMAL_DESC3_TCPPL_LEN 18 73665e0ace2SJie Deng #define TX_NORMAL_DESC3_TSE_POS 18 73765e0ace2SJie Deng #define TX_NORMAL_DESC3_TSE_LEN 1 73865e0ace2SJie Deng 73965e0ace2SJie Deng #define TX_NORMAL_DESC2_VLAN_INSERT 0x2 74065e0ace2SJie Deng 74165e0ace2SJie Deng #define XLGMAC_MTL_REG(pdata, n, reg) \ 74265e0ace2SJie Deng ((pdata)->mac_regs + MTL_Q_BASE + ((n) * MTL_Q_INC) + (reg)) 74365e0ace2SJie Deng 74465e0ace2SJie Deng #define XLGMAC_DMA_REG(channel, reg) ((channel)->dma_regs + (reg)) 74565e0ace2SJie Deng 74665e0ace2SJie Deng #endif /* __DWC_XLGMAC_REG_H__ */ 747