1 /* Synopsys DesignWare Core Enterprise Ethernet (XLGMAC) Driver 2 * 3 * Copyright (c) 2017 Synopsys, Inc. (www.synopsys.com) 4 * 5 * This program is dual-licensed; you may select either version 2 of 6 * the GNU General Public License ("GPL") or BSD license ("BSD"). 7 * 8 * This Synopsys DWC XLGMAC software driver and associated documentation 9 * (hereinafter the "Software") is an unsupported proprietary work of 10 * Synopsys, Inc. unless otherwise expressly agreed to in writing between 11 * Synopsys and you. The Software IS NOT an item of Licensed Software or a 12 * Licensed Product under any End User Software License Agreement or 13 * Agreement for Licensed Products with Synopsys or any supplement thereto. 14 * Synopsys is a registered trademark of Synopsys, Inc. Other names included 15 * in the SOFTWARE may be the trademarks of their respective owners. 16 */ 17 18 #include <linux/kernel.h> 19 #include <linux/module.h> 20 21 #include "dwc-xlgmac.h" 22 #include "dwc-xlgmac-reg.h" 23 24 MODULE_LICENSE("Dual BSD/GPL"); 25 26 static int debug = -1; 27 module_param(debug, int, 0644); 28 MODULE_PARM_DESC(debug, "DWC ethernet debug level (0=none,...,16=all)"); 29 static const u32 default_msg_level = (NETIF_MSG_LINK | NETIF_MSG_IFDOWN | 30 NETIF_MSG_IFUP); 31 32 static unsigned char dev_addr[6] = {0, 0x55, 0x7b, 0xb5, 0x7d, 0xf7}; 33 34 static void xlgmac_read_mac_addr(struct xlgmac_pdata *pdata) 35 { 36 struct net_device *netdev = pdata->netdev; 37 38 /* Currently it uses a static mac address for test */ 39 memcpy(pdata->mac_addr, dev_addr, netdev->addr_len); 40 } 41 42 static void xlgmac_default_config(struct xlgmac_pdata *pdata) 43 { 44 pdata->tx_osp_mode = DMA_OSP_ENABLE; 45 pdata->tx_sf_mode = MTL_TSF_ENABLE; 46 pdata->rx_sf_mode = MTL_RSF_DISABLE; 47 pdata->pblx8 = DMA_PBL_X8_ENABLE; 48 pdata->tx_pbl = DMA_PBL_32; 49 pdata->rx_pbl = DMA_PBL_32; 50 pdata->tx_threshold = MTL_TX_THRESHOLD_128; 51 pdata->rx_threshold = MTL_RX_THRESHOLD_128; 52 pdata->tx_pause = 1; 53 pdata->rx_pause = 1; 54 pdata->phy_speed = SPEED_25000; 55 pdata->sysclk_rate = XLGMAC_SYSCLOCK; 56 57 strlcpy(pdata->drv_name, XLGMAC_DRV_NAME, sizeof(pdata->drv_name)); 58 strlcpy(pdata->drv_ver, XLGMAC_DRV_VERSION, sizeof(pdata->drv_ver)); 59 } 60 61 static void xlgmac_init_all_ops(struct xlgmac_pdata *pdata) 62 { 63 xlgmac_init_desc_ops(&pdata->desc_ops); 64 xlgmac_init_hw_ops(&pdata->hw_ops); 65 } 66 67 static int xlgmac_init(struct xlgmac_pdata *pdata) 68 { 69 struct xlgmac_hw_ops *hw_ops = &pdata->hw_ops; 70 struct net_device *netdev = pdata->netdev; 71 unsigned int i; 72 int ret; 73 74 /* Set default configuration data */ 75 xlgmac_default_config(pdata); 76 77 /* Set irq, base_addr, MAC address, */ 78 netdev->irq = pdata->dev_irq; 79 netdev->base_addr = (unsigned long)pdata->mac_regs; 80 xlgmac_read_mac_addr(pdata); 81 memcpy(netdev->dev_addr, pdata->mac_addr, netdev->addr_len); 82 83 /* Set all the function pointers */ 84 xlgmac_init_all_ops(pdata); 85 86 /* Issue software reset to device */ 87 hw_ops->exit(pdata); 88 89 /* Populate the hardware features */ 90 xlgmac_get_all_hw_features(pdata); 91 xlgmac_print_all_hw_features(pdata); 92 93 /* TODO: Set the PHY mode to XLGMII */ 94 95 /* Set the DMA mask */ 96 ret = dma_set_mask_and_coherent(pdata->dev, 97 DMA_BIT_MASK(pdata->hw_feat.dma_width)); 98 if (ret) { 99 dev_err(pdata->dev, "dma_set_mask_and_coherent failed\n"); 100 return ret; 101 } 102 103 /* Channel and ring params initializtion 104 * pdata->channel_count; 105 * pdata->tx_ring_count; 106 * pdata->rx_ring_count; 107 * pdata->tx_desc_count; 108 * pdata->rx_desc_count; 109 */ 110 BUILD_BUG_ON_NOT_POWER_OF_2(XLGMAC_TX_DESC_CNT); 111 pdata->tx_desc_count = XLGMAC_TX_DESC_CNT; 112 if (pdata->tx_desc_count & (pdata->tx_desc_count - 1)) { 113 dev_err(pdata->dev, "tx descriptor count (%d) is not valid\n", 114 pdata->tx_desc_count); 115 ret = -EINVAL; 116 return ret; 117 } 118 BUILD_BUG_ON_NOT_POWER_OF_2(XLGMAC_RX_DESC_CNT); 119 pdata->rx_desc_count = XLGMAC_RX_DESC_CNT; 120 if (pdata->rx_desc_count & (pdata->rx_desc_count - 1)) { 121 dev_err(pdata->dev, "rx descriptor count (%d) is not valid\n", 122 pdata->rx_desc_count); 123 ret = -EINVAL; 124 return ret; 125 } 126 127 pdata->tx_ring_count = min_t(unsigned int, num_online_cpus(), 128 pdata->hw_feat.tx_ch_cnt); 129 pdata->tx_ring_count = min_t(unsigned int, pdata->tx_ring_count, 130 pdata->hw_feat.tx_q_cnt); 131 pdata->tx_q_count = pdata->tx_ring_count; 132 ret = netif_set_real_num_tx_queues(netdev, pdata->tx_q_count); 133 if (ret) { 134 dev_err(pdata->dev, "error setting real tx queue count\n"); 135 return ret; 136 } 137 138 pdata->rx_ring_count = min_t(unsigned int, 139 netif_get_num_default_rss_queues(), 140 pdata->hw_feat.rx_ch_cnt); 141 pdata->rx_ring_count = min_t(unsigned int, pdata->rx_ring_count, 142 pdata->hw_feat.rx_q_cnt); 143 pdata->rx_q_count = pdata->rx_ring_count; 144 ret = netif_set_real_num_rx_queues(netdev, pdata->rx_q_count); 145 if (ret) { 146 dev_err(pdata->dev, "error setting real rx queue count\n"); 147 return ret; 148 } 149 150 pdata->channel_count = 151 max_t(unsigned int, pdata->tx_ring_count, pdata->rx_ring_count); 152 153 /* Initialize RSS hash key and lookup table */ 154 netdev_rss_key_fill(pdata->rss_key, sizeof(pdata->rss_key)); 155 156 for (i = 0; i < XLGMAC_RSS_MAX_TABLE_SIZE; i++) 157 pdata->rss_table[i] = XLGMAC_SET_REG_BITS( 158 pdata->rss_table[i], 159 MAC_RSSDR_DMCH_POS, 160 MAC_RSSDR_DMCH_LEN, 161 i % pdata->rx_ring_count); 162 163 pdata->rss_options = XLGMAC_SET_REG_BITS( 164 pdata->rss_options, 165 MAC_RSSCR_IP2TE_POS, 166 MAC_RSSCR_IP2TE_LEN, 1); 167 pdata->rss_options = XLGMAC_SET_REG_BITS( 168 pdata->rss_options, 169 MAC_RSSCR_TCP4TE_POS, 170 MAC_RSSCR_TCP4TE_LEN, 1); 171 pdata->rss_options = XLGMAC_SET_REG_BITS( 172 pdata->rss_options, 173 MAC_RSSCR_UDP4TE_POS, 174 MAC_RSSCR_UDP4TE_LEN, 1); 175 176 /* Set device operations */ 177 netdev->netdev_ops = xlgmac_get_netdev_ops(); 178 179 /* Set device features */ 180 if (pdata->hw_feat.tso) { 181 netdev->hw_features = NETIF_F_TSO; 182 netdev->hw_features |= NETIF_F_TSO6; 183 netdev->hw_features |= NETIF_F_SG; 184 netdev->hw_features |= NETIF_F_IP_CSUM; 185 netdev->hw_features |= NETIF_F_IPV6_CSUM; 186 } else if (pdata->hw_feat.tx_coe) { 187 netdev->hw_features = NETIF_F_IP_CSUM; 188 netdev->hw_features |= NETIF_F_IPV6_CSUM; 189 } 190 191 if (pdata->hw_feat.rx_coe) { 192 netdev->hw_features |= NETIF_F_RXCSUM; 193 netdev->hw_features |= NETIF_F_GRO; 194 } 195 196 if (pdata->hw_feat.rss) 197 netdev->hw_features |= NETIF_F_RXHASH; 198 199 netdev->vlan_features |= netdev->hw_features; 200 201 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX; 202 if (pdata->hw_feat.sa_vlan_ins) 203 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX; 204 if (pdata->hw_feat.vlhash) 205 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_FILTER; 206 207 netdev->features |= netdev->hw_features; 208 pdata->netdev_features = netdev->features; 209 210 netdev->priv_flags |= IFF_UNICAST_FLT; 211 212 /* Use default watchdog timeout */ 213 netdev->watchdog_timeo = 0; 214 215 /* Tx coalesce parameters initialization */ 216 pdata->tx_usecs = XLGMAC_INIT_DMA_TX_USECS; 217 pdata->tx_frames = XLGMAC_INIT_DMA_TX_FRAMES; 218 219 /* Rx coalesce parameters initialization */ 220 pdata->rx_riwt = hw_ops->usec_to_riwt(pdata, XLGMAC_INIT_DMA_RX_USECS); 221 pdata->rx_usecs = XLGMAC_INIT_DMA_RX_USECS; 222 pdata->rx_frames = XLGMAC_INIT_DMA_RX_FRAMES; 223 224 return 0; 225 } 226 227 int xlgmac_drv_probe(struct device *dev, struct xlgmac_resources *res) 228 { 229 struct xlgmac_pdata *pdata; 230 struct net_device *netdev; 231 int ret; 232 233 netdev = alloc_etherdev_mq(sizeof(struct xlgmac_pdata), 234 XLGMAC_MAX_DMA_CHANNELS); 235 236 if (!netdev) { 237 dev_err(dev, "alloc_etherdev failed\n"); 238 return -ENOMEM; 239 } 240 241 SET_NETDEV_DEV(netdev, dev); 242 dev_set_drvdata(dev, netdev); 243 pdata = netdev_priv(netdev); 244 pdata->dev = dev; 245 pdata->netdev = netdev; 246 247 pdata->dev_irq = res->irq; 248 pdata->mac_regs = res->addr; 249 250 mutex_init(&pdata->rss_mutex); 251 pdata->msg_enable = netif_msg_init(debug, default_msg_level); 252 253 ret = xlgmac_init(pdata); 254 if (ret) { 255 dev_err(dev, "xlgmac init failed\n"); 256 goto err_free_netdev; 257 } 258 259 ret = register_netdev(netdev); 260 if (ret) { 261 dev_err(dev, "net device registration failed\n"); 262 goto err_free_netdev; 263 } 264 265 return 0; 266 267 err_free_netdev: 268 free_netdev(netdev); 269 270 return ret; 271 } 272 273 int xlgmac_drv_remove(struct device *dev) 274 { 275 struct net_device *netdev = dev_get_drvdata(dev); 276 277 unregister_netdev(netdev); 278 free_netdev(netdev); 279 280 return 0; 281 } 282 283 void xlgmac_dump_tx_desc(struct xlgmac_pdata *pdata, 284 struct xlgmac_ring *ring, 285 unsigned int idx, 286 unsigned int count, 287 unsigned int flag) 288 { 289 struct xlgmac_desc_data *desc_data; 290 struct xlgmac_dma_desc *dma_desc; 291 292 while (count--) { 293 desc_data = XLGMAC_GET_DESC_DATA(ring, idx); 294 dma_desc = desc_data->dma_desc; 295 296 netdev_dbg(pdata->netdev, "TX: dma_desc=%p, dma_desc_addr=%pad\n", 297 desc_data->dma_desc, &desc_data->dma_desc_addr); 298 netdev_dbg(pdata->netdev, 299 "TX_NORMAL_DESC[%d %s] = %08x:%08x:%08x:%08x\n", idx, 300 (flag == 1) ? "QUEUED FOR TX" : "TX BY DEVICE", 301 le32_to_cpu(dma_desc->desc0), 302 le32_to_cpu(dma_desc->desc1), 303 le32_to_cpu(dma_desc->desc2), 304 le32_to_cpu(dma_desc->desc3)); 305 306 idx++; 307 } 308 } 309 310 void xlgmac_dump_rx_desc(struct xlgmac_pdata *pdata, 311 struct xlgmac_ring *ring, 312 unsigned int idx) 313 { 314 struct xlgmac_desc_data *desc_data; 315 struct xlgmac_dma_desc *dma_desc; 316 317 desc_data = XLGMAC_GET_DESC_DATA(ring, idx); 318 dma_desc = desc_data->dma_desc; 319 320 netdev_dbg(pdata->netdev, "RX: dma_desc=%p, dma_desc_addr=%pad\n", 321 desc_data->dma_desc, &desc_data->dma_desc_addr); 322 netdev_dbg(pdata->netdev, 323 "RX_NORMAL_DESC[%d RX BY DEVICE] = %08x:%08x:%08x:%08x\n", 324 idx, 325 le32_to_cpu(dma_desc->desc0), 326 le32_to_cpu(dma_desc->desc1), 327 le32_to_cpu(dma_desc->desc2), 328 le32_to_cpu(dma_desc->desc3)); 329 } 330 331 void xlgmac_print_pkt(struct net_device *netdev, 332 struct sk_buff *skb, bool tx_rx) 333 { 334 struct ethhdr *eth = (struct ethhdr *)skb->data; 335 unsigned char *buf = skb->data; 336 unsigned char buffer[128]; 337 unsigned int i, j; 338 339 netdev_dbg(netdev, "\n************** SKB dump ****************\n"); 340 341 netdev_dbg(netdev, "%s packet of %d bytes\n", 342 (tx_rx ? "TX" : "RX"), skb->len); 343 344 netdev_dbg(netdev, "Dst MAC addr: %pM\n", eth->h_dest); 345 netdev_dbg(netdev, "Src MAC addr: %pM\n", eth->h_source); 346 netdev_dbg(netdev, "Protocol: %#06hx\n", ntohs(eth->h_proto)); 347 348 for (i = 0, j = 0; i < skb->len;) { 349 j += snprintf(buffer + j, sizeof(buffer) - j, "%02hhx", 350 buf[i++]); 351 352 if ((i % 32) == 0) { 353 netdev_dbg(netdev, " %#06x: %s\n", i - 32, buffer); 354 j = 0; 355 } else if ((i % 16) == 0) { 356 buffer[j++] = ' '; 357 buffer[j++] = ' '; 358 } else if ((i % 4) == 0) { 359 buffer[j++] = ' '; 360 } 361 } 362 if (i % 32) 363 netdev_dbg(netdev, " %#06x: %s\n", i - (i % 32), buffer); 364 365 netdev_dbg(netdev, "\n************** SKB dump ****************\n"); 366 } 367 368 void xlgmac_get_all_hw_features(struct xlgmac_pdata *pdata) 369 { 370 struct xlgmac_hw_features *hw_feat = &pdata->hw_feat; 371 unsigned int mac_hfr0, mac_hfr1, mac_hfr2; 372 373 mac_hfr0 = readl(pdata->mac_regs + MAC_HWF0R); 374 mac_hfr1 = readl(pdata->mac_regs + MAC_HWF1R); 375 mac_hfr2 = readl(pdata->mac_regs + MAC_HWF2R); 376 377 memset(hw_feat, 0, sizeof(*hw_feat)); 378 379 hw_feat->version = readl(pdata->mac_regs + MAC_VR); 380 381 /* Hardware feature register 0 */ 382 hw_feat->phyifsel = XLGMAC_GET_REG_BITS(mac_hfr0, 383 MAC_HWF0R_PHYIFSEL_POS, 384 MAC_HWF0R_PHYIFSEL_LEN); 385 hw_feat->vlhash = XLGMAC_GET_REG_BITS(mac_hfr0, 386 MAC_HWF0R_VLHASH_POS, 387 MAC_HWF0R_VLHASH_LEN); 388 hw_feat->sma = XLGMAC_GET_REG_BITS(mac_hfr0, 389 MAC_HWF0R_SMASEL_POS, 390 MAC_HWF0R_SMASEL_LEN); 391 hw_feat->rwk = XLGMAC_GET_REG_BITS(mac_hfr0, 392 MAC_HWF0R_RWKSEL_POS, 393 MAC_HWF0R_RWKSEL_LEN); 394 hw_feat->mgk = XLGMAC_GET_REG_BITS(mac_hfr0, 395 MAC_HWF0R_MGKSEL_POS, 396 MAC_HWF0R_MGKSEL_LEN); 397 hw_feat->mmc = XLGMAC_GET_REG_BITS(mac_hfr0, 398 MAC_HWF0R_MMCSEL_POS, 399 MAC_HWF0R_MMCSEL_LEN); 400 hw_feat->aoe = XLGMAC_GET_REG_BITS(mac_hfr0, 401 MAC_HWF0R_ARPOFFSEL_POS, 402 MAC_HWF0R_ARPOFFSEL_LEN); 403 hw_feat->ts = XLGMAC_GET_REG_BITS(mac_hfr0, 404 MAC_HWF0R_TSSEL_POS, 405 MAC_HWF0R_TSSEL_LEN); 406 hw_feat->eee = XLGMAC_GET_REG_BITS(mac_hfr0, 407 MAC_HWF0R_EEESEL_POS, 408 MAC_HWF0R_EEESEL_LEN); 409 hw_feat->tx_coe = XLGMAC_GET_REG_BITS(mac_hfr0, 410 MAC_HWF0R_TXCOESEL_POS, 411 MAC_HWF0R_TXCOESEL_LEN); 412 hw_feat->rx_coe = XLGMAC_GET_REG_BITS(mac_hfr0, 413 MAC_HWF0R_RXCOESEL_POS, 414 MAC_HWF0R_RXCOESEL_LEN); 415 hw_feat->addn_mac = XLGMAC_GET_REG_BITS(mac_hfr0, 416 MAC_HWF0R_ADDMACADRSEL_POS, 417 MAC_HWF0R_ADDMACADRSEL_LEN); 418 hw_feat->ts_src = XLGMAC_GET_REG_BITS(mac_hfr0, 419 MAC_HWF0R_TSSTSSEL_POS, 420 MAC_HWF0R_TSSTSSEL_LEN); 421 hw_feat->sa_vlan_ins = XLGMAC_GET_REG_BITS(mac_hfr0, 422 MAC_HWF0R_SAVLANINS_POS, 423 MAC_HWF0R_SAVLANINS_LEN); 424 425 /* Hardware feature register 1 */ 426 hw_feat->rx_fifo_size = XLGMAC_GET_REG_BITS(mac_hfr1, 427 MAC_HWF1R_RXFIFOSIZE_POS, 428 MAC_HWF1R_RXFIFOSIZE_LEN); 429 hw_feat->tx_fifo_size = XLGMAC_GET_REG_BITS(mac_hfr1, 430 MAC_HWF1R_TXFIFOSIZE_POS, 431 MAC_HWF1R_TXFIFOSIZE_LEN); 432 hw_feat->adv_ts_hi = XLGMAC_GET_REG_BITS(mac_hfr1, 433 MAC_HWF1R_ADVTHWORD_POS, 434 MAC_HWF1R_ADVTHWORD_LEN); 435 hw_feat->dma_width = XLGMAC_GET_REG_BITS(mac_hfr1, 436 MAC_HWF1R_ADDR64_POS, 437 MAC_HWF1R_ADDR64_LEN); 438 hw_feat->dcb = XLGMAC_GET_REG_BITS(mac_hfr1, 439 MAC_HWF1R_DCBEN_POS, 440 MAC_HWF1R_DCBEN_LEN); 441 hw_feat->sph = XLGMAC_GET_REG_BITS(mac_hfr1, 442 MAC_HWF1R_SPHEN_POS, 443 MAC_HWF1R_SPHEN_LEN); 444 hw_feat->tso = XLGMAC_GET_REG_BITS(mac_hfr1, 445 MAC_HWF1R_TSOEN_POS, 446 MAC_HWF1R_TSOEN_LEN); 447 hw_feat->dma_debug = XLGMAC_GET_REG_BITS(mac_hfr1, 448 MAC_HWF1R_DBGMEMA_POS, 449 MAC_HWF1R_DBGMEMA_LEN); 450 hw_feat->rss = XLGMAC_GET_REG_BITS(mac_hfr1, 451 MAC_HWF1R_RSSEN_POS, 452 MAC_HWF1R_RSSEN_LEN); 453 hw_feat->tc_cnt = XLGMAC_GET_REG_BITS(mac_hfr1, 454 MAC_HWF1R_NUMTC_POS, 455 MAC_HWF1R_NUMTC_LEN); 456 hw_feat->hash_table_size = XLGMAC_GET_REG_BITS(mac_hfr1, 457 MAC_HWF1R_HASHTBLSZ_POS, 458 MAC_HWF1R_HASHTBLSZ_LEN); 459 hw_feat->l3l4_filter_num = XLGMAC_GET_REG_BITS(mac_hfr1, 460 MAC_HWF1R_L3L4FNUM_POS, 461 MAC_HWF1R_L3L4FNUM_LEN); 462 463 /* Hardware feature register 2 */ 464 hw_feat->rx_q_cnt = XLGMAC_GET_REG_BITS(mac_hfr2, 465 MAC_HWF2R_RXQCNT_POS, 466 MAC_HWF2R_RXQCNT_LEN); 467 hw_feat->tx_q_cnt = XLGMAC_GET_REG_BITS(mac_hfr2, 468 MAC_HWF2R_TXQCNT_POS, 469 MAC_HWF2R_TXQCNT_LEN); 470 hw_feat->rx_ch_cnt = XLGMAC_GET_REG_BITS(mac_hfr2, 471 MAC_HWF2R_RXCHCNT_POS, 472 MAC_HWF2R_RXCHCNT_LEN); 473 hw_feat->tx_ch_cnt = XLGMAC_GET_REG_BITS(mac_hfr2, 474 MAC_HWF2R_TXCHCNT_POS, 475 MAC_HWF2R_TXCHCNT_LEN); 476 hw_feat->pps_out_num = XLGMAC_GET_REG_BITS(mac_hfr2, 477 MAC_HWF2R_PPSOUTNUM_POS, 478 MAC_HWF2R_PPSOUTNUM_LEN); 479 hw_feat->aux_snap_num = XLGMAC_GET_REG_BITS(mac_hfr2, 480 MAC_HWF2R_AUXSNAPNUM_POS, 481 MAC_HWF2R_AUXSNAPNUM_LEN); 482 483 /* Translate the Hash Table size into actual number */ 484 switch (hw_feat->hash_table_size) { 485 case 0: 486 break; 487 case 1: 488 hw_feat->hash_table_size = 64; 489 break; 490 case 2: 491 hw_feat->hash_table_size = 128; 492 break; 493 case 3: 494 hw_feat->hash_table_size = 256; 495 break; 496 } 497 498 /* Translate the address width setting into actual number */ 499 switch (hw_feat->dma_width) { 500 case 0: 501 hw_feat->dma_width = 32; 502 break; 503 case 1: 504 hw_feat->dma_width = 40; 505 break; 506 case 2: 507 hw_feat->dma_width = 48; 508 break; 509 default: 510 hw_feat->dma_width = 32; 511 } 512 513 /* The Queue, Channel and TC counts are zero based so increment them 514 * to get the actual number 515 */ 516 hw_feat->rx_q_cnt++; 517 hw_feat->tx_q_cnt++; 518 hw_feat->rx_ch_cnt++; 519 hw_feat->tx_ch_cnt++; 520 hw_feat->tc_cnt++; 521 } 522 523 void xlgmac_print_all_hw_features(struct xlgmac_pdata *pdata) 524 { 525 char *str = NULL; 526 527 XLGMAC_PR("\n"); 528 XLGMAC_PR("=====================================================\n"); 529 XLGMAC_PR("\n"); 530 XLGMAC_PR("HW support following features\n"); 531 XLGMAC_PR("\n"); 532 /* HW Feature Register0 */ 533 XLGMAC_PR("VLAN Hash Filter Selected : %s\n", 534 pdata->hw_feat.vlhash ? "YES" : "NO"); 535 XLGMAC_PR("SMA (MDIO) Interface : %s\n", 536 pdata->hw_feat.sma ? "YES" : "NO"); 537 XLGMAC_PR("PMT Remote Wake-up Packet Enable : %s\n", 538 pdata->hw_feat.rwk ? "YES" : "NO"); 539 XLGMAC_PR("PMT Magic Packet Enable : %s\n", 540 pdata->hw_feat.mgk ? "YES" : "NO"); 541 XLGMAC_PR("RMON/MMC Module Enable : %s\n", 542 pdata->hw_feat.mmc ? "YES" : "NO"); 543 XLGMAC_PR("ARP Offload Enabled : %s\n", 544 pdata->hw_feat.aoe ? "YES" : "NO"); 545 XLGMAC_PR("IEEE 1588-2008 Timestamp Enabled : %s\n", 546 pdata->hw_feat.ts ? "YES" : "NO"); 547 XLGMAC_PR("Energy Efficient Ethernet Enabled : %s\n", 548 pdata->hw_feat.eee ? "YES" : "NO"); 549 XLGMAC_PR("Transmit Checksum Offload Enabled : %s\n", 550 pdata->hw_feat.tx_coe ? "YES" : "NO"); 551 XLGMAC_PR("Receive Checksum Offload Enabled : %s\n", 552 pdata->hw_feat.rx_coe ? "YES" : "NO"); 553 XLGMAC_PR("Additional MAC Addresses 1-31 Selected : %s\n", 554 pdata->hw_feat.addn_mac ? "YES" : "NO"); 555 556 switch (pdata->hw_feat.ts_src) { 557 case 0: 558 str = "RESERVED"; 559 break; 560 case 1: 561 str = "INTERNAL"; 562 break; 563 case 2: 564 str = "EXTERNAL"; 565 break; 566 case 3: 567 str = "BOTH"; 568 break; 569 } 570 XLGMAC_PR("Timestamp System Time Source : %s\n", str); 571 572 XLGMAC_PR("Source Address or VLAN Insertion Enable : %s\n", 573 pdata->hw_feat.sa_vlan_ins ? "YES" : "NO"); 574 575 /* HW Feature Register1 */ 576 switch (pdata->hw_feat.rx_fifo_size) { 577 case 0: 578 str = "128 bytes"; 579 break; 580 case 1: 581 str = "256 bytes"; 582 break; 583 case 2: 584 str = "512 bytes"; 585 break; 586 case 3: 587 str = "1 KBytes"; 588 break; 589 case 4: 590 str = "2 KBytes"; 591 break; 592 case 5: 593 str = "4 KBytes"; 594 break; 595 case 6: 596 str = "8 KBytes"; 597 break; 598 case 7: 599 str = "16 KBytes"; 600 break; 601 case 8: 602 str = "32 kBytes"; 603 break; 604 case 9: 605 str = "64 KBytes"; 606 break; 607 case 10: 608 str = "128 KBytes"; 609 break; 610 case 11: 611 str = "256 KBytes"; 612 break; 613 default: 614 str = "RESERVED"; 615 } 616 XLGMAC_PR("MTL Receive FIFO Size : %s\n", str); 617 618 switch (pdata->hw_feat.tx_fifo_size) { 619 case 0: 620 str = "128 bytes"; 621 break; 622 case 1: 623 str = "256 bytes"; 624 break; 625 case 2: 626 str = "512 bytes"; 627 break; 628 case 3: 629 str = "1 KBytes"; 630 break; 631 case 4: 632 str = "2 KBytes"; 633 break; 634 case 5: 635 str = "4 KBytes"; 636 break; 637 case 6: 638 str = "8 KBytes"; 639 break; 640 case 7: 641 str = "16 KBytes"; 642 break; 643 case 8: 644 str = "32 kBytes"; 645 break; 646 case 9: 647 str = "64 KBytes"; 648 break; 649 case 10: 650 str = "128 KBytes"; 651 break; 652 case 11: 653 str = "256 KBytes"; 654 break; 655 default: 656 str = "RESERVED"; 657 } 658 XLGMAC_PR("MTL Transmit FIFO Size : %s\n", str); 659 660 XLGMAC_PR("IEEE 1588 High Word Register Enable : %s\n", 661 pdata->hw_feat.adv_ts_hi ? "YES" : "NO"); 662 XLGMAC_PR("Address width : %u\n", 663 pdata->hw_feat.dma_width); 664 XLGMAC_PR("DCB Feature Enable : %s\n", 665 pdata->hw_feat.dcb ? "YES" : "NO"); 666 XLGMAC_PR("Split Header Feature Enable : %s\n", 667 pdata->hw_feat.sph ? "YES" : "NO"); 668 XLGMAC_PR("TCP Segmentation Offload Enable : %s\n", 669 pdata->hw_feat.tso ? "YES" : "NO"); 670 XLGMAC_PR("DMA Debug Registers Enabled : %s\n", 671 pdata->hw_feat.dma_debug ? "YES" : "NO"); 672 XLGMAC_PR("RSS Feature Enabled : %s\n", 673 pdata->hw_feat.rss ? "YES" : "NO"); 674 XLGMAC_PR("Number of Traffic classes : %u\n", 675 (pdata->hw_feat.tc_cnt)); 676 XLGMAC_PR("Hash Table Size : %u\n", 677 pdata->hw_feat.hash_table_size); 678 XLGMAC_PR("Total number of L3 or L4 Filters : %u\n", 679 pdata->hw_feat.l3l4_filter_num); 680 681 /* HW Feature Register2 */ 682 XLGMAC_PR("Number of MTL Receive Queues : %u\n", 683 pdata->hw_feat.rx_q_cnt); 684 XLGMAC_PR("Number of MTL Transmit Queues : %u\n", 685 pdata->hw_feat.tx_q_cnt); 686 XLGMAC_PR("Number of DMA Receive Channels : %u\n", 687 pdata->hw_feat.rx_ch_cnt); 688 XLGMAC_PR("Number of DMA Transmit Channels : %u\n", 689 pdata->hw_feat.tx_ch_cnt); 690 691 switch (pdata->hw_feat.pps_out_num) { 692 case 0: 693 str = "No PPS output"; 694 break; 695 case 1: 696 str = "1 PPS output"; 697 break; 698 case 2: 699 str = "2 PPS output"; 700 break; 701 case 3: 702 str = "3 PPS output"; 703 break; 704 case 4: 705 str = "4 PPS output"; 706 break; 707 default: 708 str = "RESERVED"; 709 } 710 XLGMAC_PR("Number of PPS Outputs : %s\n", str); 711 712 switch (pdata->hw_feat.aux_snap_num) { 713 case 0: 714 str = "No auxiliary input"; 715 break; 716 case 1: 717 str = "1 auxiliary input"; 718 break; 719 case 2: 720 str = "2 auxiliary input"; 721 break; 722 case 3: 723 str = "3 auxiliary input"; 724 break; 725 case 4: 726 str = "4 auxiliary input"; 727 break; 728 default: 729 str = "RESERVED"; 730 } 731 XLGMAC_PR("Number of Auxiliary Snapshot Inputs : %s", str); 732 733 XLGMAC_PR("\n"); 734 XLGMAC_PR("=====================================================\n"); 735 XLGMAC_PR("\n"); 736 } 737