1*fd3040b9SWells Lu /* SPDX-License-Identifier: GPL-2.0 */ 2*fd3040b9SWells Lu /* Copyright Sunplus Technology Co., Ltd. 3*fd3040b9SWells Lu * All rights reserved. 4*fd3040b9SWells Lu */ 5*fd3040b9SWells Lu 6*fd3040b9SWells Lu #ifndef __SPL2SW_REGISTER_H__ 7*fd3040b9SWells Lu #define __SPL2SW_REGISTER_H__ 8*fd3040b9SWells Lu 9*fd3040b9SWells Lu /* Register L2SW */ 10*fd3040b9SWells Lu #define L2SW_SW_INT_STATUS_0 0x0 11*fd3040b9SWells Lu #define L2SW_SW_INT_MASK_0 0x4 12*fd3040b9SWells Lu #define L2SW_FL_CNTL_TH 0x8 13*fd3040b9SWells Lu #define L2SW_CPU_FL_CNTL_TH 0xc 14*fd3040b9SWells Lu #define L2SW_PRI_FL_CNTL 0x10 15*fd3040b9SWells Lu #define L2SW_VLAN_PRI_TH 0x14 16*fd3040b9SWells Lu #define L2SW_EN_TOS_BUS 0x18 17*fd3040b9SWells Lu #define L2SW_TOS_MAP0 0x1c 18*fd3040b9SWells Lu #define L2SW_TOS_MAP1 0x20 19*fd3040b9SWells Lu #define L2SW_TOS_MAP2 0x24 20*fd3040b9SWells Lu #define L2SW_TOS_MAP3 0x28 21*fd3040b9SWells Lu #define L2SW_TOS_MAP4 0x2c 22*fd3040b9SWells Lu #define L2SW_TOS_MAP5 0x30 23*fd3040b9SWells Lu #define L2SW_TOS_MAP6 0x34 24*fd3040b9SWells Lu #define L2SW_TOS_MAP7 0x38 25*fd3040b9SWells Lu #define L2SW_GLOBAL_QUE_STATUS 0x3c 26*fd3040b9SWells Lu #define L2SW_ADDR_TBL_SRCH 0x40 27*fd3040b9SWells Lu #define L2SW_ADDR_TBL_ST 0x44 28*fd3040b9SWells Lu #define L2SW_MAC_AD_SER0 0x48 29*fd3040b9SWells Lu #define L2SW_MAC_AD_SER1 0x4c 30*fd3040b9SWells Lu #define L2SW_WT_MAC_AD0 0x50 31*fd3040b9SWells Lu #define L2SW_W_MAC_15_0 0x54 32*fd3040b9SWells Lu #define L2SW_W_MAC_47_16 0x58 33*fd3040b9SWells Lu #define L2SW_PVID_CONFIG0 0x5c 34*fd3040b9SWells Lu #define L2SW_PVID_CONFIG1 0x60 35*fd3040b9SWells Lu #define L2SW_VLAN_MEMSET_CONFIG0 0x64 36*fd3040b9SWells Lu #define L2SW_VLAN_MEMSET_CONFIG1 0x68 37*fd3040b9SWells Lu #define L2SW_PORT_ABILITY 0x6c 38*fd3040b9SWells Lu #define L2SW_PORT_ST 0x70 39*fd3040b9SWells Lu #define L2SW_CPU_CNTL 0x74 40*fd3040b9SWells Lu #define L2SW_PORT_CNTL0 0x78 41*fd3040b9SWells Lu #define L2SW_PORT_CNTL1 0x7c 42*fd3040b9SWells Lu #define L2SW_PORT_CNTL2 0x80 43*fd3040b9SWells Lu #define L2SW_SW_GLB_CNTL 0x84 44*fd3040b9SWells Lu #define L2SW_L2SW_SW_RESET 0x88 45*fd3040b9SWells Lu #define L2SW_LED_PORT0 0x8c 46*fd3040b9SWells Lu #define L2SW_LED_PORT1 0x90 47*fd3040b9SWells Lu #define L2SW_LED_PORT2 0x94 48*fd3040b9SWells Lu #define L2SW_LED_PORT3 0x98 49*fd3040b9SWells Lu #define L2SW_LED_PORT4 0x9c 50*fd3040b9SWells Lu #define L2SW_WATCH_DOG_TRIG_RST 0xa0 51*fd3040b9SWells Lu #define L2SW_WATCH_DOG_STOP_CPU 0xa4 52*fd3040b9SWells Lu #define L2SW_PHY_CNTL_REG0 0xa8 53*fd3040b9SWells Lu #define L2SW_PHY_CNTL_REG1 0xac 54*fd3040b9SWells Lu #define L2SW_MAC_FORCE_MODE 0xb0 55*fd3040b9SWells Lu #define L2SW_VLAN_GROUP_CONFIG0 0xb4 56*fd3040b9SWells Lu #define L2SW_VLAN_GROUP_CONFIG1 0xb8 57*fd3040b9SWells Lu #define L2SW_FLOW_CTRL_TH3 0xbc 58*fd3040b9SWells Lu #define L2SW_QUEUE_STATUS_0 0xc0 59*fd3040b9SWells Lu #define L2SW_DEBUG_CNTL 0xc4 60*fd3040b9SWells Lu #define L2SW_RESERVED_1 0xc8 61*fd3040b9SWells Lu #define L2SW_MEM_TEST_INFO 0xcc 62*fd3040b9SWells Lu #define L2SW_SW_INT_STATUS_1 0xd0 63*fd3040b9SWells Lu #define L2SW_SW_INT_MASK_1 0xd4 64*fd3040b9SWells Lu #define L2SW_SW_GLOBAL_SIGNAL 0xd8 65*fd3040b9SWells Lu 66*fd3040b9SWells Lu #define L2SW_CPU_TX_TRIG 0x208 67*fd3040b9SWells Lu #define L2SW_TX_HBASE_ADDR_0 0x20c 68*fd3040b9SWells Lu #define L2SW_TX_LBASE_ADDR_0 0x210 69*fd3040b9SWells Lu #define L2SW_RX_HBASE_ADDR_0 0x214 70*fd3040b9SWells Lu #define L2SW_RX_LBASE_ADDR_0 0x218 71*fd3040b9SWells Lu #define L2SW_TX_HW_ADDR_0 0x21c 72*fd3040b9SWells Lu #define L2SW_TX_LW_ADDR_0 0x220 73*fd3040b9SWells Lu #define L2SW_RX_HW_ADDR_0 0x224 74*fd3040b9SWells Lu #define L2SW_RX_LW_ADDR_0 0x228 75*fd3040b9SWells Lu #define L2SW_CPU_PORT_CNTL_REG_0 0x22c 76*fd3040b9SWells Lu #define L2SW_TX_HBASE_ADDR_1 0x230 77*fd3040b9SWells Lu #define L2SW_TX_LBASE_ADDR_1 0x234 78*fd3040b9SWells Lu #define L2SW_RX_HBASE_ADDR_1 0x238 79*fd3040b9SWells Lu #define L2SW_RX_LBASE_ADDR_1 0x23c 80*fd3040b9SWells Lu #define L2SW_TX_HW_ADDR_1 0x240 81*fd3040b9SWells Lu #define L2SW_TX_LW_ADDR_1 0x244 82*fd3040b9SWells Lu #define L2SW_RX_HW_ADDR_1 0x248 83*fd3040b9SWells Lu #define L2SW_RX_LW_ADDR_1 0x24c 84*fd3040b9SWells Lu #define L2SW_CPU_PORT_CNTL_REG_1 0x250 85*fd3040b9SWells Lu 86*fd3040b9SWells Lu #endif 87