1 // SPDX-License-Identifier: GPL-2.0 2 /* sunhme.c: Sparc HME/BigMac 10/100baseT half/full duplex auto switching, 3 * auto carrier detecting ethernet driver. Also known as the 4 * "Happy Meal Ethernet" found on SunSwift SBUS cards. 5 * 6 * Copyright (C) 1996, 1998, 1999, 2002, 2003, 7 * 2006, 2008 David S. Miller (davem@davemloft.net) 8 * 9 * Changes : 10 * 2000/11/11 Willy Tarreau <willy AT meta-x.org> 11 * - port to non-sparc architectures. Tested only on x86 and 12 * only currently works with QFE PCI cards. 13 * - ability to specify the MAC address at module load time by passing this 14 * argument : macaddr=0x00,0x10,0x20,0x30,0x40,0x50 15 */ 16 17 #include <linux/bitops.h> 18 #include <linux/crc32.h> 19 #include <linux/delay.h> 20 #include <linux/dma-mapping.h> 21 #include <linux/errno.h> 22 #include <linux/etherdevice.h> 23 #include <linux/ethtool.h> 24 #include <linux/fcntl.h> 25 #include <linux/in.h> 26 #include <linux/init.h> 27 #include <linux/interrupt.h> 28 #include <linux/io.h> 29 #include <linux/ioport.h> 30 #include <linux/kernel.h> 31 #include <linux/mii.h> 32 #include <linux/mm.h> 33 #include <linux/module.h> 34 #include <linux/netdevice.h> 35 #include <linux/of_device.h> 36 #include <linux/of.h> 37 #include <linux/pci.h> 38 #include <linux/random.h> 39 #include <linux/skbuff.h> 40 #include <linux/slab.h> 41 #include <linux/string.h> 42 #include <linux/types.h> 43 #include <linux/uaccess.h> 44 45 #include <asm/byteorder.h> 46 #include <asm/dma.h> 47 #include <asm/irq.h> 48 49 #ifdef CONFIG_SPARC 50 #include <asm/auxio.h> 51 #include <asm/idprom.h> 52 #include <asm/openprom.h> 53 #include <asm/oplib.h> 54 #include <asm/prom.h> 55 #endif 56 57 #include "sunhme.h" 58 59 #define DRV_NAME "sunhme" 60 61 MODULE_AUTHOR("David S. Miller (davem@davemloft.net)"); 62 MODULE_DESCRIPTION("Sun HappyMealEthernet(HME) 10/100baseT ethernet driver"); 63 MODULE_LICENSE("GPL"); 64 65 static int macaddr[6]; 66 67 /* accept MAC address of the form macaddr=0x08,0x00,0x20,0x30,0x40,0x50 */ 68 module_param_array(macaddr, int, NULL, 0); 69 MODULE_PARM_DESC(macaddr, "Happy Meal MAC address to set"); 70 71 #ifdef CONFIG_SBUS 72 static struct quattro *qfe_sbus_list; 73 #endif 74 75 #ifdef CONFIG_PCI 76 static struct quattro *qfe_pci_list; 77 #endif 78 79 #define hme_debug(fmt, ...) pr_debug("%s: " fmt, __func__, ##__VA_ARGS__) 80 #define HMD hme_debug 81 82 /* "Auto Switch Debug" aka phy debug */ 83 #if 1 84 #define ASD hme_debug 85 #else 86 #define ASD(...) 87 #endif 88 89 #if 0 90 struct hme_tx_logent { 91 unsigned int tstamp; 92 int tx_new, tx_old; 93 unsigned int action; 94 #define TXLOG_ACTION_IRQ 0x01 95 #define TXLOG_ACTION_TXMIT 0x02 96 #define TXLOG_ACTION_TBUSY 0x04 97 #define TXLOG_ACTION_NBUFS 0x08 98 unsigned int status; 99 }; 100 #define TX_LOG_LEN 128 101 static struct hme_tx_logent tx_log[TX_LOG_LEN]; 102 static int txlog_cur_entry; 103 static __inline__ void tx_add_log(struct happy_meal *hp, unsigned int a, unsigned int s) 104 { 105 struct hme_tx_logent *tlp; 106 unsigned long flags; 107 108 local_irq_save(flags); 109 tlp = &tx_log[txlog_cur_entry]; 110 tlp->tstamp = (unsigned int)jiffies; 111 tlp->tx_new = hp->tx_new; 112 tlp->tx_old = hp->tx_old; 113 tlp->action = a; 114 tlp->status = s; 115 txlog_cur_entry = (txlog_cur_entry + 1) & (TX_LOG_LEN - 1); 116 local_irq_restore(flags); 117 } 118 static __inline__ void tx_dump_log(void) 119 { 120 int i, this; 121 122 this = txlog_cur_entry; 123 for (i = 0; i < TX_LOG_LEN; i++) { 124 pr_err("TXLOG[%d]: j[%08x] tx[N(%d)O(%d)] action[%08x] stat[%08x]\n", i, 125 tx_log[this].tstamp, 126 tx_log[this].tx_new, tx_log[this].tx_old, 127 tx_log[this].action, tx_log[this].status); 128 this = (this + 1) & (TX_LOG_LEN - 1); 129 } 130 } 131 #else 132 #define tx_add_log(hp, a, s) 133 #define tx_dump_log() 134 #endif 135 136 #define DEFAULT_IPG0 16 /* For lance-mode only */ 137 #define DEFAULT_IPG1 8 /* For all modes */ 138 #define DEFAULT_IPG2 4 /* For all modes */ 139 #define DEFAULT_JAMSIZE 4 /* Toe jam */ 140 141 /* NOTE: In the descriptor writes one _must_ write the address 142 * member _first_. The card must not be allowed to see 143 * the updated descriptor flags until the address is 144 * correct. I've added a write memory barrier between 145 * the two stores so that I can sleep well at night... -DaveM 146 */ 147 148 #if defined(CONFIG_SBUS) && defined(CONFIG_PCI) 149 static void sbus_hme_write32(void __iomem *reg, u32 val) 150 { 151 sbus_writel(val, reg); 152 } 153 154 static u32 sbus_hme_read32(void __iomem *reg) 155 { 156 return sbus_readl(reg); 157 } 158 159 static void sbus_hme_write_rxd(struct happy_meal_rxd *rxd, u32 flags, u32 addr) 160 { 161 rxd->rx_addr = (__force hme32)addr; 162 dma_wmb(); 163 rxd->rx_flags = (__force hme32)flags; 164 } 165 166 static void sbus_hme_write_txd(struct happy_meal_txd *txd, u32 flags, u32 addr) 167 { 168 txd->tx_addr = (__force hme32)addr; 169 dma_wmb(); 170 txd->tx_flags = (__force hme32)flags; 171 } 172 173 static u32 sbus_hme_read_desc32(hme32 *p) 174 { 175 return (__force u32)*p; 176 } 177 178 static void pci_hme_write32(void __iomem *reg, u32 val) 179 { 180 writel(val, reg); 181 } 182 183 static u32 pci_hme_read32(void __iomem *reg) 184 { 185 return readl(reg); 186 } 187 188 static void pci_hme_write_rxd(struct happy_meal_rxd *rxd, u32 flags, u32 addr) 189 { 190 rxd->rx_addr = (__force hme32)cpu_to_le32(addr); 191 dma_wmb(); 192 rxd->rx_flags = (__force hme32)cpu_to_le32(flags); 193 } 194 195 static void pci_hme_write_txd(struct happy_meal_txd *txd, u32 flags, u32 addr) 196 { 197 txd->tx_addr = (__force hme32)cpu_to_le32(addr); 198 dma_wmb(); 199 txd->tx_flags = (__force hme32)cpu_to_le32(flags); 200 } 201 202 static u32 pci_hme_read_desc32(hme32 *p) 203 { 204 return le32_to_cpup((__le32 *)p); 205 } 206 207 #define hme_write32(__hp, __reg, __val) \ 208 ((__hp)->write32((__reg), (__val))) 209 #define hme_read32(__hp, __reg) \ 210 ((__hp)->read32(__reg)) 211 #define hme_write_rxd(__hp, __rxd, __flags, __addr) \ 212 ((__hp)->write_rxd((__rxd), (__flags), (__addr))) 213 #define hme_write_txd(__hp, __txd, __flags, __addr) \ 214 ((__hp)->write_txd((__txd), (__flags), (__addr))) 215 #define hme_read_desc32(__hp, __p) \ 216 ((__hp)->read_desc32(__p)) 217 #else 218 #ifdef CONFIG_SBUS 219 /* SBUS only compilation */ 220 #define hme_write32(__hp, __reg, __val) \ 221 sbus_writel((__val), (__reg)) 222 #define hme_read32(__hp, __reg) \ 223 sbus_readl(__reg) 224 #define hme_write_rxd(__hp, __rxd, __flags, __addr) \ 225 do { (__rxd)->rx_addr = (__force hme32)(u32)(__addr); \ 226 dma_wmb(); \ 227 (__rxd)->rx_flags = (__force hme32)(u32)(__flags); \ 228 } while(0) 229 #define hme_write_txd(__hp, __txd, __flags, __addr) \ 230 do { (__txd)->tx_addr = (__force hme32)(u32)(__addr); \ 231 dma_wmb(); \ 232 (__txd)->tx_flags = (__force hme32)(u32)(__flags); \ 233 } while(0) 234 #define hme_read_desc32(__hp, __p) ((__force u32)(hme32)*(__p)) 235 #else 236 /* PCI only compilation */ 237 #define hme_write32(__hp, __reg, __val) \ 238 writel((__val), (__reg)) 239 #define hme_read32(__hp, __reg) \ 240 readl(__reg) 241 #define hme_write_rxd(__hp, __rxd, __flags, __addr) \ 242 do { (__rxd)->rx_addr = (__force hme32)cpu_to_le32(__addr); \ 243 dma_wmb(); \ 244 (__rxd)->rx_flags = (__force hme32)cpu_to_le32(__flags); \ 245 } while(0) 246 #define hme_write_txd(__hp, __txd, __flags, __addr) \ 247 do { (__txd)->tx_addr = (__force hme32)cpu_to_le32(__addr); \ 248 dma_wmb(); \ 249 (__txd)->tx_flags = (__force hme32)cpu_to_le32(__flags); \ 250 } while(0) 251 static inline u32 hme_read_desc32(struct happy_meal *hp, hme32 *p) 252 { 253 return le32_to_cpup((__le32 *)p); 254 } 255 #endif 256 #endif 257 258 259 /* Oh yes, the MIF BitBang is mighty fun to program. BitBucket is more like it. */ 260 static void BB_PUT_BIT(struct happy_meal *hp, void __iomem *tregs, int bit) 261 { 262 hme_write32(hp, tregs + TCVR_BBDATA, bit); 263 hme_write32(hp, tregs + TCVR_BBCLOCK, 0); 264 hme_write32(hp, tregs + TCVR_BBCLOCK, 1); 265 } 266 267 #if 0 268 static u32 BB_GET_BIT(struct happy_meal *hp, void __iomem *tregs, int internal) 269 { 270 u32 ret; 271 272 hme_write32(hp, tregs + TCVR_BBCLOCK, 0); 273 hme_write32(hp, tregs + TCVR_BBCLOCK, 1); 274 ret = hme_read32(hp, tregs + TCVR_CFG); 275 if (internal) 276 ret &= TCV_CFG_MDIO0; 277 else 278 ret &= TCV_CFG_MDIO1; 279 280 return ret; 281 } 282 #endif 283 284 static u32 BB_GET_BIT2(struct happy_meal *hp, void __iomem *tregs, int internal) 285 { 286 u32 retval; 287 288 hme_write32(hp, tregs + TCVR_BBCLOCK, 0); 289 udelay(1); 290 retval = hme_read32(hp, tregs + TCVR_CFG); 291 if (internal) 292 retval &= TCV_CFG_MDIO0; 293 else 294 retval &= TCV_CFG_MDIO1; 295 hme_write32(hp, tregs + TCVR_BBCLOCK, 1); 296 297 return retval; 298 } 299 300 #define TCVR_FAILURE 0x80000000 /* Impossible MIF read value */ 301 302 static int happy_meal_bb_read(struct happy_meal *hp, 303 void __iomem *tregs, int reg) 304 { 305 u32 tmp; 306 int retval = 0; 307 int i; 308 309 /* Enable the MIF BitBang outputs. */ 310 hme_write32(hp, tregs + TCVR_BBOENAB, 1); 311 312 /* Force BitBang into the idle state. */ 313 for (i = 0; i < 32; i++) 314 BB_PUT_BIT(hp, tregs, 1); 315 316 /* Give it the read sequence. */ 317 BB_PUT_BIT(hp, tregs, 0); 318 BB_PUT_BIT(hp, tregs, 1); 319 BB_PUT_BIT(hp, tregs, 1); 320 BB_PUT_BIT(hp, tregs, 0); 321 322 /* Give it the PHY address. */ 323 tmp = hp->paddr & 0xff; 324 for (i = 4; i >= 0; i--) 325 BB_PUT_BIT(hp, tregs, ((tmp >> i) & 1)); 326 327 /* Tell it what register we want to read. */ 328 tmp = (reg & 0xff); 329 for (i = 4; i >= 0; i--) 330 BB_PUT_BIT(hp, tregs, ((tmp >> i) & 1)); 331 332 /* Close down the MIF BitBang outputs. */ 333 hme_write32(hp, tregs + TCVR_BBOENAB, 0); 334 335 /* Now read in the value. */ 336 (void) BB_GET_BIT2(hp, tregs, (hp->tcvr_type == internal)); 337 for (i = 15; i >= 0; i--) 338 retval |= BB_GET_BIT2(hp, tregs, (hp->tcvr_type == internal)); 339 (void) BB_GET_BIT2(hp, tregs, (hp->tcvr_type == internal)); 340 (void) BB_GET_BIT2(hp, tregs, (hp->tcvr_type == internal)); 341 (void) BB_GET_BIT2(hp, tregs, (hp->tcvr_type == internal)); 342 ASD("reg=%d value=%x\n", reg, retval); 343 return retval; 344 } 345 346 static void happy_meal_bb_write(struct happy_meal *hp, 347 void __iomem *tregs, int reg, 348 unsigned short value) 349 { 350 u32 tmp; 351 int i; 352 353 ASD("reg=%d value=%x\n", reg, value); 354 355 /* Enable the MIF BitBang outputs. */ 356 hme_write32(hp, tregs + TCVR_BBOENAB, 1); 357 358 /* Force BitBang into the idle state. */ 359 for (i = 0; i < 32; i++) 360 BB_PUT_BIT(hp, tregs, 1); 361 362 /* Give it write sequence. */ 363 BB_PUT_BIT(hp, tregs, 0); 364 BB_PUT_BIT(hp, tregs, 1); 365 BB_PUT_BIT(hp, tregs, 0); 366 BB_PUT_BIT(hp, tregs, 1); 367 368 /* Give it the PHY address. */ 369 tmp = (hp->paddr & 0xff); 370 for (i = 4; i >= 0; i--) 371 BB_PUT_BIT(hp, tregs, ((tmp >> i) & 1)); 372 373 /* Tell it what register we will be writing. */ 374 tmp = (reg & 0xff); 375 for (i = 4; i >= 0; i--) 376 BB_PUT_BIT(hp, tregs, ((tmp >> i) & 1)); 377 378 /* Tell it to become ready for the bits. */ 379 BB_PUT_BIT(hp, tregs, 1); 380 BB_PUT_BIT(hp, tregs, 0); 381 382 for (i = 15; i >= 0; i--) 383 BB_PUT_BIT(hp, tregs, ((value >> i) & 1)); 384 385 /* Close down the MIF BitBang outputs. */ 386 hme_write32(hp, tregs + TCVR_BBOENAB, 0); 387 } 388 389 #define TCVR_READ_TRIES 16 390 391 static int happy_meal_tcvr_read(struct happy_meal *hp, 392 void __iomem *tregs, int reg) 393 { 394 int tries = TCVR_READ_TRIES; 395 int retval; 396 397 if (hp->tcvr_type == none) { 398 ASD("no transceiver, value=TCVR_FAILURE\n"); 399 return TCVR_FAILURE; 400 } 401 402 if (!(hp->happy_flags & HFLAG_FENABLE)) { 403 ASD("doing bit bang\n"); 404 return happy_meal_bb_read(hp, tregs, reg); 405 } 406 407 hme_write32(hp, tregs + TCVR_FRAME, 408 (FRAME_READ | (hp->paddr << 23) | ((reg & 0xff) << 18))); 409 while (!(hme_read32(hp, tregs + TCVR_FRAME) & 0x10000) && --tries) 410 udelay(20); 411 if (!tries) { 412 netdev_err(hp->dev, "Aieee, transceiver MIF read bolixed\n"); 413 return TCVR_FAILURE; 414 } 415 retval = hme_read32(hp, tregs + TCVR_FRAME) & 0xffff; 416 ASD("reg=0x%02x value=%04x\n", reg, retval); 417 return retval; 418 } 419 420 #define TCVR_WRITE_TRIES 16 421 422 static void happy_meal_tcvr_write(struct happy_meal *hp, 423 void __iomem *tregs, int reg, 424 unsigned short value) 425 { 426 int tries = TCVR_WRITE_TRIES; 427 428 ASD("reg=0x%02x value=%04x\n", reg, value); 429 430 /* Welcome to Sun Microsystems, can I take your order please? */ 431 if (!(hp->happy_flags & HFLAG_FENABLE)) { 432 happy_meal_bb_write(hp, tregs, reg, value); 433 return; 434 } 435 436 /* Would you like fries with that? */ 437 hme_write32(hp, tregs + TCVR_FRAME, 438 (FRAME_WRITE | (hp->paddr << 23) | 439 ((reg & 0xff) << 18) | (value & 0xffff))); 440 while (!(hme_read32(hp, tregs + TCVR_FRAME) & 0x10000) && --tries) 441 udelay(20); 442 443 /* Anything else? */ 444 if (!tries) 445 netdev_err(hp->dev, "Aieee, transceiver MIF write bolixed\n"); 446 447 /* Fifty-two cents is your change, have a nice day. */ 448 } 449 450 /* Auto negotiation. The scheme is very simple. We have a timer routine 451 * that keeps watching the auto negotiation process as it progresses. 452 * The DP83840 is first told to start doing it's thing, we set up the time 453 * and place the timer state machine in it's initial state. 454 * 455 * Here the timer peeks at the DP83840 status registers at each click to see 456 * if the auto negotiation has completed, we assume here that the DP83840 PHY 457 * will time out at some point and just tell us what (didn't) happen. For 458 * complete coverage we only allow so many of the ticks at this level to run, 459 * when this has expired we print a warning message and try another strategy. 460 * This "other" strategy is to force the interface into various speed/duplex 461 * configurations and we stop when we see a link-up condition before the 462 * maximum number of "peek" ticks have occurred. 463 * 464 * Once a valid link status has been detected we configure the BigMAC and 465 * the rest of the Happy Meal to speak the most efficient protocol we could 466 * get a clean link for. The priority for link configurations, highest first 467 * is: 468 * 100 Base-T Full Duplex 469 * 100 Base-T Half Duplex 470 * 10 Base-T Full Duplex 471 * 10 Base-T Half Duplex 472 * 473 * We start a new timer now, after a successful auto negotiation status has 474 * been detected. This timer just waits for the link-up bit to get set in 475 * the BMCR of the DP83840. When this occurs we print a kernel log message 476 * describing the link type in use and the fact that it is up. 477 * 478 * If a fatal error of some sort is signalled and detected in the interrupt 479 * service routine, and the chip is reset, or the link is ifconfig'd down 480 * and then back up, this entire process repeats itself all over again. 481 */ 482 static int try_next_permutation(struct happy_meal *hp, void __iomem *tregs) 483 { 484 hp->sw_bmcr = happy_meal_tcvr_read(hp, tregs, MII_BMCR); 485 486 /* Downgrade from full to half duplex. Only possible 487 * via ethtool. 488 */ 489 if (hp->sw_bmcr & BMCR_FULLDPLX) { 490 hp->sw_bmcr &= ~(BMCR_FULLDPLX); 491 happy_meal_tcvr_write(hp, tregs, MII_BMCR, hp->sw_bmcr); 492 return 0; 493 } 494 495 /* Downgrade from 100 to 10. */ 496 if (hp->sw_bmcr & BMCR_SPEED100) { 497 hp->sw_bmcr &= ~(BMCR_SPEED100); 498 happy_meal_tcvr_write(hp, tregs, MII_BMCR, hp->sw_bmcr); 499 return 0; 500 } 501 502 /* We've tried everything. */ 503 return -1; 504 } 505 506 static void display_link_mode(struct happy_meal *hp, void __iomem *tregs) 507 { 508 hp->sw_lpa = happy_meal_tcvr_read(hp, tregs, MII_LPA); 509 510 netdev_info(hp->dev, 511 "Link is up using %s transceiver at %dMb/s, %s Duplex.\n", 512 hp->tcvr_type == external ? "external" : "internal", 513 hp->sw_lpa & (LPA_100HALF | LPA_100FULL) ? 100 : 10, 514 hp->sw_lpa & (LPA_100FULL | LPA_10FULL) ? "Full" : "Half"); 515 } 516 517 static void display_forced_link_mode(struct happy_meal *hp, void __iomem *tregs) 518 { 519 hp->sw_bmcr = happy_meal_tcvr_read(hp, tregs, MII_BMCR); 520 521 netdev_info(hp->dev, 522 "Link has been forced up using %s transceiver at %dMb/s, %s Duplex.\n", 523 hp->tcvr_type == external ? "external" : "internal", 524 hp->sw_bmcr & BMCR_SPEED100 ? 100 : 10, 525 hp->sw_bmcr & BMCR_FULLDPLX ? "Full" : "Half"); 526 } 527 528 static int set_happy_link_modes(struct happy_meal *hp, void __iomem *tregs) 529 { 530 int full; 531 532 /* All we care about is making sure the bigmac tx_cfg has a 533 * proper duplex setting. 534 */ 535 if (hp->timer_state == arbwait) { 536 hp->sw_lpa = happy_meal_tcvr_read(hp, tregs, MII_LPA); 537 if (!(hp->sw_lpa & (LPA_10HALF | LPA_10FULL | LPA_100HALF | LPA_100FULL))) 538 goto no_response; 539 if (hp->sw_lpa & LPA_100FULL) 540 full = 1; 541 else if (hp->sw_lpa & LPA_100HALF) 542 full = 0; 543 else if (hp->sw_lpa & LPA_10FULL) 544 full = 1; 545 else 546 full = 0; 547 } else { 548 /* Forcing a link mode. */ 549 hp->sw_bmcr = happy_meal_tcvr_read(hp, tregs, MII_BMCR); 550 if (hp->sw_bmcr & BMCR_FULLDPLX) 551 full = 1; 552 else 553 full = 0; 554 } 555 556 /* Before changing other bits in the tx_cfg register, and in 557 * general any of other the TX config registers too, you 558 * must: 559 * 1) Clear Enable 560 * 2) Poll with reads until that bit reads back as zero 561 * 3) Make TX configuration changes 562 * 4) Set Enable once more 563 */ 564 hme_write32(hp, hp->bigmacregs + BMAC_TXCFG, 565 hme_read32(hp, hp->bigmacregs + BMAC_TXCFG) & 566 ~(BIGMAC_TXCFG_ENABLE)); 567 while (hme_read32(hp, hp->bigmacregs + BMAC_TXCFG) & BIGMAC_TXCFG_ENABLE) 568 barrier(); 569 if (full) { 570 hp->happy_flags |= HFLAG_FULL; 571 hme_write32(hp, hp->bigmacregs + BMAC_TXCFG, 572 hme_read32(hp, hp->bigmacregs + BMAC_TXCFG) | 573 BIGMAC_TXCFG_FULLDPLX); 574 } else { 575 hp->happy_flags &= ~(HFLAG_FULL); 576 hme_write32(hp, hp->bigmacregs + BMAC_TXCFG, 577 hme_read32(hp, hp->bigmacregs + BMAC_TXCFG) & 578 ~(BIGMAC_TXCFG_FULLDPLX)); 579 } 580 hme_write32(hp, hp->bigmacregs + BMAC_TXCFG, 581 hme_read32(hp, hp->bigmacregs + BMAC_TXCFG) | 582 BIGMAC_TXCFG_ENABLE); 583 return 0; 584 no_response: 585 return 1; 586 } 587 588 static int is_lucent_phy(struct happy_meal *hp) 589 { 590 void __iomem *tregs = hp->tcvregs; 591 unsigned short mr2, mr3; 592 int ret = 0; 593 594 mr2 = happy_meal_tcvr_read(hp, tregs, 2); 595 mr3 = happy_meal_tcvr_read(hp, tregs, 3); 596 if ((mr2 & 0xffff) == 0x0180 && 597 ((mr3 & 0xffff) >> 10) == 0x1d) 598 ret = 1; 599 600 return ret; 601 } 602 603 /* hp->happy_lock must be held */ 604 static void 605 happy_meal_begin_auto_negotiation(struct happy_meal *hp, 606 void __iomem *tregs, 607 const struct ethtool_link_ksettings *ep) 608 { 609 int timeout; 610 611 /* Read all of the registers we are interested in now. */ 612 hp->sw_bmsr = happy_meal_tcvr_read(hp, tregs, MII_BMSR); 613 hp->sw_bmcr = happy_meal_tcvr_read(hp, tregs, MII_BMCR); 614 hp->sw_physid1 = happy_meal_tcvr_read(hp, tregs, MII_PHYSID1); 615 hp->sw_physid2 = happy_meal_tcvr_read(hp, tregs, MII_PHYSID2); 616 617 /* XXX Check BMSR_ANEGCAPABLE, should not be necessary though. */ 618 619 hp->sw_advertise = happy_meal_tcvr_read(hp, tregs, MII_ADVERTISE); 620 if (!ep || ep->base.autoneg == AUTONEG_ENABLE) { 621 /* Advertise everything we can support. */ 622 if (hp->sw_bmsr & BMSR_10HALF) 623 hp->sw_advertise |= (ADVERTISE_10HALF); 624 else 625 hp->sw_advertise &= ~(ADVERTISE_10HALF); 626 627 if (hp->sw_bmsr & BMSR_10FULL) 628 hp->sw_advertise |= (ADVERTISE_10FULL); 629 else 630 hp->sw_advertise &= ~(ADVERTISE_10FULL); 631 if (hp->sw_bmsr & BMSR_100HALF) 632 hp->sw_advertise |= (ADVERTISE_100HALF); 633 else 634 hp->sw_advertise &= ~(ADVERTISE_100HALF); 635 if (hp->sw_bmsr & BMSR_100FULL) 636 hp->sw_advertise |= (ADVERTISE_100FULL); 637 else 638 hp->sw_advertise &= ~(ADVERTISE_100FULL); 639 happy_meal_tcvr_write(hp, tregs, MII_ADVERTISE, hp->sw_advertise); 640 641 /* XXX Currently no Happy Meal cards I know off support 100BaseT4, 642 * XXX and this is because the DP83840 does not support it, changes 643 * XXX would need to be made to the tx/rx logic in the driver as well 644 * XXX so I completely skip checking for it in the BMSR for now. 645 */ 646 647 ASD("Advertising [ %s%s%s%s]\n", 648 hp->sw_advertise & ADVERTISE_10HALF ? "10H " : "", 649 hp->sw_advertise & ADVERTISE_10FULL ? "10F " : "", 650 hp->sw_advertise & ADVERTISE_100HALF ? "100H " : "", 651 hp->sw_advertise & ADVERTISE_100FULL ? "100F " : ""); 652 653 /* Enable Auto-Negotiation, this is usually on already... */ 654 hp->sw_bmcr |= BMCR_ANENABLE; 655 happy_meal_tcvr_write(hp, tregs, MII_BMCR, hp->sw_bmcr); 656 657 /* Restart it to make sure it is going. */ 658 hp->sw_bmcr |= BMCR_ANRESTART; 659 happy_meal_tcvr_write(hp, tregs, MII_BMCR, hp->sw_bmcr); 660 661 /* BMCR_ANRESTART self clears when the process has begun. */ 662 663 timeout = 64; /* More than enough. */ 664 while (--timeout) { 665 hp->sw_bmcr = happy_meal_tcvr_read(hp, tregs, MII_BMCR); 666 if (!(hp->sw_bmcr & BMCR_ANRESTART)) 667 break; /* got it. */ 668 udelay(10); 669 } 670 if (!timeout) { 671 netdev_err(hp->dev, 672 "Happy Meal would not start auto negotiation BMCR=0x%04x\n", 673 hp->sw_bmcr); 674 netdev_notice(hp->dev, 675 "Performing force link detection.\n"); 676 goto force_link; 677 } else { 678 hp->timer_state = arbwait; 679 } 680 } else { 681 force_link: 682 /* Force the link up, trying first a particular mode. 683 * Either we are here at the request of ethtool or 684 * because the Happy Meal would not start to autoneg. 685 */ 686 687 /* Disable auto-negotiation in BMCR, enable the duplex and 688 * speed setting, init the timer state machine, and fire it off. 689 */ 690 if (!ep || ep->base.autoneg == AUTONEG_ENABLE) { 691 hp->sw_bmcr = BMCR_SPEED100; 692 } else { 693 if (ep->base.speed == SPEED_100) 694 hp->sw_bmcr = BMCR_SPEED100; 695 else 696 hp->sw_bmcr = 0; 697 if (ep->base.duplex == DUPLEX_FULL) 698 hp->sw_bmcr |= BMCR_FULLDPLX; 699 } 700 happy_meal_tcvr_write(hp, tregs, MII_BMCR, hp->sw_bmcr); 701 702 if (!is_lucent_phy(hp)) { 703 /* OK, seems we need do disable the transceiver for the first 704 * tick to make sure we get an accurate link state at the 705 * second tick. 706 */ 707 hp->sw_csconfig = happy_meal_tcvr_read(hp, tregs, 708 DP83840_CSCONFIG); 709 hp->sw_csconfig &= ~(CSCONFIG_TCVDISAB); 710 happy_meal_tcvr_write(hp, tregs, DP83840_CSCONFIG, 711 hp->sw_csconfig); 712 } 713 hp->timer_state = ltrywait; 714 } 715 716 hp->timer_ticks = 0; 717 hp->happy_timer.expires = jiffies + (12 * HZ)/10; /* 1.2 sec. */ 718 add_timer(&hp->happy_timer); 719 } 720 721 static void happy_meal_timer(struct timer_list *t) 722 { 723 struct happy_meal *hp = from_timer(hp, t, happy_timer); 724 void __iomem *tregs = hp->tcvregs; 725 int restart_timer = 0; 726 727 spin_lock_irq(&hp->happy_lock); 728 729 hp->timer_ticks++; 730 switch(hp->timer_state) { 731 case arbwait: 732 /* Only allow for 5 ticks, thats 10 seconds and much too 733 * long to wait for arbitration to complete. 734 */ 735 if (hp->timer_ticks >= 10) { 736 /* Enter force mode. */ 737 do_force_mode: 738 hp->sw_bmcr = happy_meal_tcvr_read(hp, tregs, MII_BMCR); 739 netdev_notice(hp->dev, 740 "Auto-Negotiation unsuccessful, trying force link mode\n"); 741 hp->sw_bmcr = BMCR_SPEED100; 742 happy_meal_tcvr_write(hp, tregs, MII_BMCR, hp->sw_bmcr); 743 744 if (!is_lucent_phy(hp)) { 745 /* OK, seems we need do disable the transceiver for the first 746 * tick to make sure we get an accurate link state at the 747 * second tick. 748 */ 749 hp->sw_csconfig = happy_meal_tcvr_read(hp, tregs, DP83840_CSCONFIG); 750 hp->sw_csconfig &= ~(CSCONFIG_TCVDISAB); 751 happy_meal_tcvr_write(hp, tregs, DP83840_CSCONFIG, hp->sw_csconfig); 752 } 753 hp->timer_state = ltrywait; 754 hp->timer_ticks = 0; 755 restart_timer = 1; 756 } else { 757 /* Anything interesting happen? */ 758 hp->sw_bmsr = happy_meal_tcvr_read(hp, tregs, MII_BMSR); 759 if (hp->sw_bmsr & BMSR_ANEGCOMPLETE) { 760 int ret; 761 762 /* Just what we've been waiting for... */ 763 ret = set_happy_link_modes(hp, tregs); 764 if (ret) { 765 /* Ooops, something bad happened, go to force 766 * mode. 767 * 768 * XXX Broken hubs which don't support 802.3u 769 * XXX auto-negotiation make this happen as well. 770 */ 771 goto do_force_mode; 772 } 773 774 /* Success, at least so far, advance our state engine. */ 775 hp->timer_state = lupwait; 776 restart_timer = 1; 777 } else { 778 restart_timer = 1; 779 } 780 } 781 break; 782 783 case lupwait: 784 /* Auto negotiation was successful and we are awaiting a 785 * link up status. I have decided to let this timer run 786 * forever until some sort of error is signalled, reporting 787 * a message to the user at 10 second intervals. 788 */ 789 hp->sw_bmsr = happy_meal_tcvr_read(hp, tregs, MII_BMSR); 790 if (hp->sw_bmsr & BMSR_LSTATUS) { 791 /* Wheee, it's up, display the link mode in use and put 792 * the timer to sleep. 793 */ 794 display_link_mode(hp, tregs); 795 hp->timer_state = asleep; 796 restart_timer = 0; 797 } else { 798 if (hp->timer_ticks >= 10) { 799 netdev_notice(hp->dev, 800 "Auto negotiation successful, link still not completely up.\n"); 801 hp->timer_ticks = 0; 802 restart_timer = 1; 803 } else { 804 restart_timer = 1; 805 } 806 } 807 break; 808 809 case ltrywait: 810 /* Making the timeout here too long can make it take 811 * annoyingly long to attempt all of the link mode 812 * permutations, but then again this is essentially 813 * error recovery code for the most part. 814 */ 815 hp->sw_bmsr = happy_meal_tcvr_read(hp, tregs, MII_BMSR); 816 hp->sw_csconfig = happy_meal_tcvr_read(hp, tregs, DP83840_CSCONFIG); 817 if (hp->timer_ticks == 1) { 818 if (!is_lucent_phy(hp)) { 819 /* Re-enable transceiver, we'll re-enable the transceiver next 820 * tick, then check link state on the following tick. 821 */ 822 hp->sw_csconfig |= CSCONFIG_TCVDISAB; 823 happy_meal_tcvr_write(hp, tregs, 824 DP83840_CSCONFIG, hp->sw_csconfig); 825 } 826 restart_timer = 1; 827 break; 828 } 829 if (hp->timer_ticks == 2) { 830 if (!is_lucent_phy(hp)) { 831 hp->sw_csconfig &= ~(CSCONFIG_TCVDISAB); 832 happy_meal_tcvr_write(hp, tregs, 833 DP83840_CSCONFIG, hp->sw_csconfig); 834 } 835 restart_timer = 1; 836 break; 837 } 838 if (hp->sw_bmsr & BMSR_LSTATUS) { 839 /* Force mode selection success. */ 840 display_forced_link_mode(hp, tregs); 841 set_happy_link_modes(hp, tregs); /* XXX error? then what? */ 842 hp->timer_state = asleep; 843 restart_timer = 0; 844 } else { 845 if (hp->timer_ticks >= 4) { /* 6 seconds or so... */ 846 int ret; 847 848 ret = try_next_permutation(hp, tregs); 849 if (ret == -1) { 850 /* Aieee, tried them all, reset the 851 * chip and try all over again. 852 */ 853 854 /* Let the user know... */ 855 netdev_notice(hp->dev, 856 "Link down, cable problem?\n"); 857 858 happy_meal_begin_auto_negotiation(hp, tregs, NULL); 859 goto out; 860 } 861 if (!is_lucent_phy(hp)) { 862 hp->sw_csconfig = happy_meal_tcvr_read(hp, tregs, 863 DP83840_CSCONFIG); 864 hp->sw_csconfig |= CSCONFIG_TCVDISAB; 865 happy_meal_tcvr_write(hp, tregs, 866 DP83840_CSCONFIG, hp->sw_csconfig); 867 } 868 hp->timer_ticks = 0; 869 restart_timer = 1; 870 } else { 871 restart_timer = 1; 872 } 873 } 874 break; 875 876 case asleep: 877 default: 878 /* Can't happens.... */ 879 netdev_err(hp->dev, 880 "Aieee, link timer is asleep but we got one anyways!\n"); 881 restart_timer = 0; 882 hp->timer_ticks = 0; 883 hp->timer_state = asleep; /* foo on you */ 884 break; 885 } 886 887 if (restart_timer) { 888 hp->happy_timer.expires = jiffies + ((12 * HZ)/10); /* 1.2 sec. */ 889 add_timer(&hp->happy_timer); 890 } 891 892 out: 893 spin_unlock_irq(&hp->happy_lock); 894 } 895 896 #define TX_RESET_TRIES 32 897 #define RX_RESET_TRIES 32 898 899 /* hp->happy_lock must be held */ 900 static void happy_meal_tx_reset(struct happy_meal *hp, void __iomem *bregs) 901 { 902 int tries = TX_RESET_TRIES; 903 904 HMD("reset...\n"); 905 906 /* Would you like to try our SMCC Delux? */ 907 hme_write32(hp, bregs + BMAC_TXSWRESET, 0); 908 while ((hme_read32(hp, bregs + BMAC_TXSWRESET) & 1) && --tries) 909 udelay(20); 910 911 /* Lettuce, tomato, buggy hardware (no extra charge)? */ 912 if (!tries) 913 netdev_err(hp->dev, "Transceiver BigMac ATTACK!"); 914 915 /* Take care. */ 916 HMD("done\n"); 917 } 918 919 /* hp->happy_lock must be held */ 920 static void happy_meal_rx_reset(struct happy_meal *hp, void __iomem *bregs) 921 { 922 int tries = RX_RESET_TRIES; 923 924 HMD("reset...\n"); 925 926 /* We have a special on GNU/Viking hardware bugs today. */ 927 hme_write32(hp, bregs + BMAC_RXSWRESET, 0); 928 while ((hme_read32(hp, bregs + BMAC_RXSWRESET) & 1) && --tries) 929 udelay(20); 930 931 /* Will that be all? */ 932 if (!tries) 933 netdev_err(hp->dev, "Receiver BigMac ATTACK!\n"); 934 935 /* Don't forget your vik_1137125_wa. Have a nice day. */ 936 HMD("done\n"); 937 } 938 939 #define STOP_TRIES 16 940 941 /* hp->happy_lock must be held */ 942 static void happy_meal_stop(struct happy_meal *hp, void __iomem *gregs) 943 { 944 int tries = STOP_TRIES; 945 946 HMD("reset...\n"); 947 948 /* We're consolidating our STB products, it's your lucky day. */ 949 hme_write32(hp, gregs + GREG_SWRESET, GREG_RESET_ALL); 950 while (hme_read32(hp, gregs + GREG_SWRESET) && --tries) 951 udelay(20); 952 953 /* Come back next week when we are "Sun Microelectronics". */ 954 if (!tries) 955 netdev_err(hp->dev, "Fry guys.\n"); 956 957 /* Remember: "Different name, same old buggy as shit hardware." */ 958 HMD("done\n"); 959 } 960 961 /* hp->happy_lock must be held */ 962 static void happy_meal_get_counters(struct happy_meal *hp, void __iomem *bregs) 963 { 964 struct net_device_stats *stats = &hp->dev->stats; 965 966 stats->rx_crc_errors += hme_read32(hp, bregs + BMAC_RCRCECTR); 967 hme_write32(hp, bregs + BMAC_RCRCECTR, 0); 968 969 stats->rx_frame_errors += hme_read32(hp, bregs + BMAC_UNALECTR); 970 hme_write32(hp, bregs + BMAC_UNALECTR, 0); 971 972 stats->rx_length_errors += hme_read32(hp, bregs + BMAC_GLECTR); 973 hme_write32(hp, bregs + BMAC_GLECTR, 0); 974 975 stats->tx_aborted_errors += hme_read32(hp, bregs + BMAC_EXCTR); 976 977 stats->collisions += 978 (hme_read32(hp, bregs + BMAC_EXCTR) + 979 hme_read32(hp, bregs + BMAC_LTCTR)); 980 hme_write32(hp, bregs + BMAC_EXCTR, 0); 981 hme_write32(hp, bregs + BMAC_LTCTR, 0); 982 } 983 984 /* Only Sun can take such nice parts and fuck up the programming interface 985 * like this. Good job guys... 986 */ 987 #define TCVR_RESET_TRIES 16 /* It should reset quickly */ 988 #define TCVR_UNISOLATE_TRIES 32 /* Dis-isolation can take longer. */ 989 990 /* hp->happy_lock must be held */ 991 static int happy_meal_tcvr_reset(struct happy_meal *hp, void __iomem *tregs) 992 { 993 u32 tconfig; 994 int result, tries = TCVR_RESET_TRIES; 995 996 tconfig = hme_read32(hp, tregs + TCVR_CFG); 997 ASD("tcfg=%08x\n", tconfig); 998 if (hp->tcvr_type == external) { 999 hme_write32(hp, tregs + TCVR_CFG, tconfig & ~(TCV_CFG_PSELECT)); 1000 hp->tcvr_type = internal; 1001 hp->paddr = TCV_PADDR_ITX; 1002 happy_meal_tcvr_write(hp, tregs, MII_BMCR, 1003 (BMCR_LOOPBACK|BMCR_PDOWN|BMCR_ISOLATE)); 1004 result = happy_meal_tcvr_read(hp, tregs, MII_BMCR); 1005 if (result == TCVR_FAILURE) { 1006 ASD("phyread_fail\n"); 1007 return -1; 1008 } 1009 ASD("external: ISOLATE, phyread_ok, PSELECT\n"); 1010 hme_write32(hp, tregs + TCVR_CFG, tconfig | TCV_CFG_PSELECT); 1011 hp->tcvr_type = external; 1012 hp->paddr = TCV_PADDR_ETX; 1013 } else { 1014 if (tconfig & TCV_CFG_MDIO1) { 1015 hme_write32(hp, tregs + TCVR_CFG, (tconfig | TCV_CFG_PSELECT)); 1016 happy_meal_tcvr_write(hp, tregs, MII_BMCR, 1017 (BMCR_LOOPBACK|BMCR_PDOWN|BMCR_ISOLATE)); 1018 result = happy_meal_tcvr_read(hp, tregs, MII_BMCR); 1019 if (result == TCVR_FAILURE) { 1020 ASD("phyread_fail>\n"); 1021 return -1; 1022 } 1023 ASD("internal: PSELECT, ISOLATE, phyread_ok, ~PSELECT\n"); 1024 hme_write32(hp, tregs + TCVR_CFG, (tconfig & ~(TCV_CFG_PSELECT))); 1025 hp->tcvr_type = internal; 1026 hp->paddr = TCV_PADDR_ITX; 1027 } 1028 } 1029 1030 ASD("BMCR_RESET...\n"); 1031 happy_meal_tcvr_write(hp, tregs, MII_BMCR, BMCR_RESET); 1032 1033 while (--tries) { 1034 result = happy_meal_tcvr_read(hp, tregs, MII_BMCR); 1035 if (result == TCVR_FAILURE) 1036 return -1; 1037 hp->sw_bmcr = result; 1038 if (!(result & BMCR_RESET)) 1039 break; 1040 udelay(20); 1041 } 1042 if (!tries) { 1043 ASD("BMCR RESET FAILED!\n"); 1044 return -1; 1045 } 1046 ASD("RESET_OK\n"); 1047 1048 /* Get fresh copies of the PHY registers. */ 1049 hp->sw_bmsr = happy_meal_tcvr_read(hp, tregs, MII_BMSR); 1050 hp->sw_physid1 = happy_meal_tcvr_read(hp, tregs, MII_PHYSID1); 1051 hp->sw_physid2 = happy_meal_tcvr_read(hp, tregs, MII_PHYSID2); 1052 hp->sw_advertise = happy_meal_tcvr_read(hp, tregs, MII_ADVERTISE); 1053 1054 ASD("UNISOLATE...\n"); 1055 hp->sw_bmcr &= ~(BMCR_ISOLATE); 1056 happy_meal_tcvr_write(hp, tregs, MII_BMCR, hp->sw_bmcr); 1057 1058 tries = TCVR_UNISOLATE_TRIES; 1059 while (--tries) { 1060 result = happy_meal_tcvr_read(hp, tregs, MII_BMCR); 1061 if (result == TCVR_FAILURE) 1062 return -1; 1063 if (!(result & BMCR_ISOLATE)) 1064 break; 1065 udelay(20); 1066 } 1067 if (!tries) { 1068 ASD("UNISOLATE FAILED!\n"); 1069 return -1; 1070 } 1071 ASD("SUCCESS and CSCONFIG_DFBYPASS\n"); 1072 if (!is_lucent_phy(hp)) { 1073 result = happy_meal_tcvr_read(hp, tregs, 1074 DP83840_CSCONFIG); 1075 happy_meal_tcvr_write(hp, tregs, 1076 DP83840_CSCONFIG, (result | CSCONFIG_DFBYPASS)); 1077 } 1078 return 0; 1079 } 1080 1081 /* Figure out whether we have an internal or external transceiver. 1082 * 1083 * hp->happy_lock must be held 1084 */ 1085 static void happy_meal_transceiver_check(struct happy_meal *hp, void __iomem *tregs) 1086 { 1087 unsigned long tconfig = hme_read32(hp, tregs + TCVR_CFG); 1088 u32 reread = hme_read32(hp, tregs + TCVR_CFG); 1089 1090 ASD("tcfg=%08lx\n", tconfig); 1091 if (reread & TCV_CFG_MDIO1) { 1092 hme_write32(hp, tregs + TCVR_CFG, tconfig | TCV_CFG_PSELECT); 1093 hp->paddr = TCV_PADDR_ETX; 1094 hp->tcvr_type = external; 1095 ASD("not polling, external\n"); 1096 } else { 1097 if (reread & TCV_CFG_MDIO0) { 1098 hme_write32(hp, tregs + TCVR_CFG, 1099 tconfig & ~(TCV_CFG_PSELECT)); 1100 hp->paddr = TCV_PADDR_ITX; 1101 hp->tcvr_type = internal; 1102 ASD("not polling, internal\n"); 1103 } else { 1104 netdev_err(hp->dev, 1105 "Transceiver and a coke please."); 1106 hp->tcvr_type = none; /* Grrr... */ 1107 ASD("not polling, none\n"); 1108 } 1109 } 1110 } 1111 1112 /* The receive ring buffers are a bit tricky to get right. Here goes... 1113 * 1114 * The buffers we dma into must be 64 byte aligned. So we use a special 1115 * alloc_skb() routine for the happy meal to allocate 64 bytes more than 1116 * we really need. 1117 * 1118 * We use skb_reserve() to align the data block we get in the skb. We 1119 * also program the etxregs->cfg register to use an offset of 2. This 1120 * imperical constant plus the ethernet header size will always leave 1121 * us with a nicely aligned ip header once we pass things up to the 1122 * protocol layers. 1123 * 1124 * The numbers work out to: 1125 * 1126 * Max ethernet frame size 1518 1127 * Ethernet header size 14 1128 * Happy Meal base offset 2 1129 * 1130 * Say a skb data area is at 0xf001b010, and its size alloced is 1131 * (ETH_FRAME_LEN + 64 + 2) = (1514 + 64 + 2) = 1580 bytes. 1132 * 1133 * First our alloc_skb() routine aligns the data base to a 64 byte 1134 * boundary. We now have 0xf001b040 as our skb data address. We 1135 * plug this into the receive descriptor address. 1136 * 1137 * Next, we skb_reserve() 2 bytes to account for the Happy Meal offset. 1138 * So now the data we will end up looking at starts at 0xf001b042. When 1139 * the packet arrives, we will check out the size received and subtract 1140 * this from the skb->length. Then we just pass the packet up to the 1141 * protocols as is, and allocate a new skb to replace this slot we have 1142 * just received from. 1143 * 1144 * The ethernet layer will strip the ether header from the front of the 1145 * skb we just sent to it, this leaves us with the ip header sitting 1146 * nicely aligned at 0xf001b050. Also, for tcp and udp packets the 1147 * Happy Meal has even checksummed the tcp/udp data for us. The 16 1148 * bit checksum is obtained from the low bits of the receive descriptor 1149 * flags, thus: 1150 * 1151 * skb->csum = rxd->rx_flags & 0xffff; 1152 * skb->ip_summed = CHECKSUM_COMPLETE; 1153 * 1154 * before sending off the skb to the protocols, and we are good as gold. 1155 */ 1156 static void happy_meal_clean_rings(struct happy_meal *hp) 1157 { 1158 int i; 1159 1160 for (i = 0; i < RX_RING_SIZE; i++) { 1161 if (hp->rx_skbs[i] != NULL) { 1162 struct sk_buff *skb = hp->rx_skbs[i]; 1163 struct happy_meal_rxd *rxd; 1164 u32 dma_addr; 1165 1166 rxd = &hp->happy_block->happy_meal_rxd[i]; 1167 dma_addr = hme_read_desc32(hp, &rxd->rx_addr); 1168 dma_unmap_single(hp->dma_dev, dma_addr, 1169 RX_BUF_ALLOC_SIZE, DMA_FROM_DEVICE); 1170 dev_kfree_skb_any(skb); 1171 hp->rx_skbs[i] = NULL; 1172 } 1173 } 1174 1175 for (i = 0; i < TX_RING_SIZE; i++) { 1176 if (hp->tx_skbs[i] != NULL) { 1177 struct sk_buff *skb = hp->tx_skbs[i]; 1178 struct happy_meal_txd *txd; 1179 u32 dma_addr; 1180 int frag; 1181 1182 hp->tx_skbs[i] = NULL; 1183 1184 for (frag = 0; frag <= skb_shinfo(skb)->nr_frags; frag++) { 1185 txd = &hp->happy_block->happy_meal_txd[i]; 1186 dma_addr = hme_read_desc32(hp, &txd->tx_addr); 1187 if (!frag) 1188 dma_unmap_single(hp->dma_dev, dma_addr, 1189 (hme_read_desc32(hp, &txd->tx_flags) 1190 & TXFLAG_SIZE), 1191 DMA_TO_DEVICE); 1192 else 1193 dma_unmap_page(hp->dma_dev, dma_addr, 1194 (hme_read_desc32(hp, &txd->tx_flags) 1195 & TXFLAG_SIZE), 1196 DMA_TO_DEVICE); 1197 1198 if (frag != skb_shinfo(skb)->nr_frags) 1199 i++; 1200 } 1201 1202 dev_kfree_skb_any(skb); 1203 } 1204 } 1205 } 1206 1207 /* hp->happy_lock must be held */ 1208 static void happy_meal_init_rings(struct happy_meal *hp) 1209 { 1210 struct hmeal_init_block *hb = hp->happy_block; 1211 int i; 1212 1213 HMD("counters to zero\n"); 1214 hp->rx_new = hp->rx_old = hp->tx_new = hp->tx_old = 0; 1215 1216 /* Free any skippy bufs left around in the rings. */ 1217 happy_meal_clean_rings(hp); 1218 1219 /* Now get new skippy bufs for the receive ring. */ 1220 HMD("init rxring\n"); 1221 for (i = 0; i < RX_RING_SIZE; i++) { 1222 struct sk_buff *skb; 1223 u32 mapping; 1224 1225 skb = happy_meal_alloc_skb(RX_BUF_ALLOC_SIZE, GFP_ATOMIC); 1226 if (!skb) { 1227 hme_write_rxd(hp, &hb->happy_meal_rxd[i], 0, 0); 1228 continue; 1229 } 1230 hp->rx_skbs[i] = skb; 1231 1232 /* Because we reserve afterwards. */ 1233 skb_put(skb, (ETH_FRAME_LEN + RX_OFFSET + 4)); 1234 mapping = dma_map_single(hp->dma_dev, skb->data, RX_BUF_ALLOC_SIZE, 1235 DMA_FROM_DEVICE); 1236 if (dma_mapping_error(hp->dma_dev, mapping)) { 1237 dev_kfree_skb_any(skb); 1238 hme_write_rxd(hp, &hb->happy_meal_rxd[i], 0, 0); 1239 continue; 1240 } 1241 hme_write_rxd(hp, &hb->happy_meal_rxd[i], 1242 (RXFLAG_OWN | ((RX_BUF_ALLOC_SIZE - RX_OFFSET) << 16)), 1243 mapping); 1244 skb_reserve(skb, RX_OFFSET); 1245 } 1246 1247 HMD("init txring\n"); 1248 for (i = 0; i < TX_RING_SIZE; i++) 1249 hme_write_txd(hp, &hb->happy_meal_txd[i], 0, 0); 1250 1251 HMD("done\n"); 1252 } 1253 1254 /* hp->happy_lock must be held */ 1255 static int happy_meal_init(struct happy_meal *hp) 1256 { 1257 const unsigned char *e = &hp->dev->dev_addr[0]; 1258 void __iomem *gregs = hp->gregs; 1259 void __iomem *etxregs = hp->etxregs; 1260 void __iomem *erxregs = hp->erxregs; 1261 void __iomem *bregs = hp->bigmacregs; 1262 void __iomem *tregs = hp->tcvregs; 1263 const char *bursts = "64"; 1264 u32 regtmp, rxcfg; 1265 1266 /* If auto-negotiation timer is running, kill it. */ 1267 del_timer(&hp->happy_timer); 1268 1269 HMD("happy_flags[%08x]\n", hp->happy_flags); 1270 if (!(hp->happy_flags & HFLAG_INIT)) { 1271 HMD("set HFLAG_INIT\n"); 1272 hp->happy_flags |= HFLAG_INIT; 1273 happy_meal_get_counters(hp, bregs); 1274 } 1275 1276 /* Stop transmitter and receiver. */ 1277 HMD("to happy_meal_stop\n"); 1278 happy_meal_stop(hp, gregs); 1279 1280 /* Alloc and reset the tx/rx descriptor chains. */ 1281 HMD("to happy_meal_init_rings\n"); 1282 happy_meal_init_rings(hp); 1283 1284 /* See if we can enable the MIF frame on this card to speak to the DP83840. */ 1285 if (hp->happy_flags & HFLAG_FENABLE) { 1286 HMD("use frame old[%08x]\n", 1287 hme_read32(hp, tregs + TCVR_CFG)); 1288 hme_write32(hp, tregs + TCVR_CFG, 1289 hme_read32(hp, tregs + TCVR_CFG) & ~(TCV_CFG_BENABLE)); 1290 } else { 1291 HMD("use bitbang old[%08x]\n", 1292 hme_read32(hp, tregs + TCVR_CFG)); 1293 hme_write32(hp, tregs + TCVR_CFG, 1294 hme_read32(hp, tregs + TCVR_CFG) | TCV_CFG_BENABLE); 1295 } 1296 1297 /* Check the state of the transceiver. */ 1298 HMD("to happy_meal_transceiver_check\n"); 1299 happy_meal_transceiver_check(hp, tregs); 1300 1301 /* Put the Big Mac into a sane state. */ 1302 switch(hp->tcvr_type) { 1303 case none: 1304 /* Cannot operate if we don't know the transceiver type! */ 1305 HMD("AAIEEE no transceiver type, EAGAIN\n"); 1306 return -EAGAIN; 1307 1308 case internal: 1309 /* Using the MII buffers. */ 1310 HMD("internal, using MII\n"); 1311 hme_write32(hp, bregs + BMAC_XIFCFG, 0); 1312 break; 1313 1314 case external: 1315 /* Not using the MII, disable it. */ 1316 HMD("external, disable MII\n"); 1317 hme_write32(hp, bregs + BMAC_XIFCFG, BIGMAC_XCFG_MIIDISAB); 1318 break; 1319 } 1320 1321 if (happy_meal_tcvr_reset(hp, tregs)) 1322 return -EAGAIN; 1323 1324 /* Reset the Happy Meal Big Mac transceiver and the receiver. */ 1325 HMD("tx/rx reset\n"); 1326 happy_meal_tx_reset(hp, bregs); 1327 happy_meal_rx_reset(hp, bregs); 1328 1329 /* Set jam size and inter-packet gaps to reasonable defaults. */ 1330 hme_write32(hp, bregs + BMAC_JSIZE, DEFAULT_JAMSIZE); 1331 hme_write32(hp, bregs + BMAC_IGAP1, DEFAULT_IPG1); 1332 hme_write32(hp, bregs + BMAC_IGAP2, DEFAULT_IPG2); 1333 1334 /* Load up the MAC address and random seed. */ 1335 1336 /* The docs recommend to use the 10LSB of our MAC here. */ 1337 hme_write32(hp, bregs + BMAC_RSEED, ((e[5] | e[4]<<8)&0x3ff)); 1338 1339 hme_write32(hp, bregs + BMAC_MACADDR2, ((e[4] << 8) | e[5])); 1340 hme_write32(hp, bregs + BMAC_MACADDR1, ((e[2] << 8) | e[3])); 1341 hme_write32(hp, bregs + BMAC_MACADDR0, ((e[0] << 8) | e[1])); 1342 1343 if ((hp->dev->flags & IFF_ALLMULTI) || 1344 (netdev_mc_count(hp->dev) > 64)) { 1345 hme_write32(hp, bregs + BMAC_HTABLE0, 0xffff); 1346 hme_write32(hp, bregs + BMAC_HTABLE1, 0xffff); 1347 hme_write32(hp, bregs + BMAC_HTABLE2, 0xffff); 1348 hme_write32(hp, bregs + BMAC_HTABLE3, 0xffff); 1349 } else if ((hp->dev->flags & IFF_PROMISC) == 0) { 1350 u16 hash_table[4]; 1351 struct netdev_hw_addr *ha; 1352 u32 crc; 1353 1354 memset(hash_table, 0, sizeof(hash_table)); 1355 netdev_for_each_mc_addr(ha, hp->dev) { 1356 crc = ether_crc_le(6, ha->addr); 1357 crc >>= 26; 1358 hash_table[crc >> 4] |= 1 << (crc & 0xf); 1359 } 1360 hme_write32(hp, bregs + BMAC_HTABLE0, hash_table[0]); 1361 hme_write32(hp, bregs + BMAC_HTABLE1, hash_table[1]); 1362 hme_write32(hp, bregs + BMAC_HTABLE2, hash_table[2]); 1363 hme_write32(hp, bregs + BMAC_HTABLE3, hash_table[3]); 1364 } else { 1365 hme_write32(hp, bregs + BMAC_HTABLE3, 0); 1366 hme_write32(hp, bregs + BMAC_HTABLE2, 0); 1367 hme_write32(hp, bregs + BMAC_HTABLE1, 0); 1368 hme_write32(hp, bregs + BMAC_HTABLE0, 0); 1369 } 1370 1371 /* Set the RX and TX ring ptrs. */ 1372 HMD("ring ptrs rxr[%08x] txr[%08x]\n", 1373 ((__u32)hp->hblock_dvma + hblock_offset(happy_meal_rxd, 0)), 1374 ((__u32)hp->hblock_dvma + hblock_offset(happy_meal_txd, 0))); 1375 hme_write32(hp, erxregs + ERX_RING, 1376 ((__u32)hp->hblock_dvma + hblock_offset(happy_meal_rxd, 0))); 1377 hme_write32(hp, etxregs + ETX_RING, 1378 ((__u32)hp->hblock_dvma + hblock_offset(happy_meal_txd, 0))); 1379 1380 /* Parity issues in the ERX unit of some HME revisions can cause some 1381 * registers to not be written unless their parity is even. Detect such 1382 * lost writes and simply rewrite with a low bit set (which will be ignored 1383 * since the rxring needs to be 2K aligned). 1384 */ 1385 if (hme_read32(hp, erxregs + ERX_RING) != 1386 ((__u32)hp->hblock_dvma + hblock_offset(happy_meal_rxd, 0))) 1387 hme_write32(hp, erxregs + ERX_RING, 1388 ((__u32)hp->hblock_dvma + hblock_offset(happy_meal_rxd, 0)) 1389 | 0x4); 1390 1391 /* Set the supported burst sizes. */ 1392 #ifndef CONFIG_SPARC 1393 /* It is always PCI and can handle 64byte bursts. */ 1394 hme_write32(hp, gregs + GREG_CFG, GREG_CFG_BURST64); 1395 #else 1396 if ((hp->happy_bursts & DMA_BURST64) && 1397 ((hp->happy_flags & HFLAG_PCI) != 0 1398 #ifdef CONFIG_SBUS 1399 || sbus_can_burst64() 1400 #endif 1401 || 0)) { 1402 u32 gcfg = GREG_CFG_BURST64; 1403 1404 /* I have no idea if I should set the extended 1405 * transfer mode bit for Cheerio, so for now I 1406 * do not. -DaveM 1407 */ 1408 #ifdef CONFIG_SBUS 1409 if ((hp->happy_flags & HFLAG_PCI) == 0) { 1410 struct platform_device *op = hp->happy_dev; 1411 if (sbus_can_dma_64bit()) { 1412 sbus_set_sbus64(&op->dev, 1413 hp->happy_bursts); 1414 gcfg |= GREG_CFG_64BIT; 1415 } 1416 } 1417 #endif 1418 1419 bursts = "64"; 1420 hme_write32(hp, gregs + GREG_CFG, gcfg); 1421 } else if (hp->happy_bursts & DMA_BURST32) { 1422 bursts = "32"; 1423 hme_write32(hp, gregs + GREG_CFG, GREG_CFG_BURST32); 1424 } else if (hp->happy_bursts & DMA_BURST16) { 1425 bursts = "16"; 1426 hme_write32(hp, gregs + GREG_CFG, GREG_CFG_BURST16); 1427 } else { 1428 bursts = "XXX"; 1429 hme_write32(hp, gregs + GREG_CFG, 0); 1430 } 1431 #endif /* CONFIG_SPARC */ 1432 1433 HMD("old[%08x] bursts<%s>\n", 1434 hme_read32(hp, gregs + GREG_CFG), bursts); 1435 1436 /* Turn off interrupts we do not want to hear. */ 1437 hme_write32(hp, gregs + GREG_IMASK, 1438 (GREG_IMASK_GOTFRAME | GREG_IMASK_RCNTEXP | 1439 GREG_IMASK_SENTFRAME | GREG_IMASK_TXPERR)); 1440 1441 /* Set the transmit ring buffer size. */ 1442 HMD("tx rsize=%d oreg[%08x]\n", (int)TX_RING_SIZE, 1443 hme_read32(hp, etxregs + ETX_RSIZE)); 1444 hme_write32(hp, etxregs + ETX_RSIZE, (TX_RING_SIZE >> ETX_RSIZE_SHIFT) - 1); 1445 1446 /* Enable transmitter DVMA. */ 1447 HMD("tx dma enable old[%08x]\n", hme_read32(hp, etxregs + ETX_CFG)); 1448 hme_write32(hp, etxregs + ETX_CFG, 1449 hme_read32(hp, etxregs + ETX_CFG) | ETX_CFG_DMAENABLE); 1450 1451 /* This chip really rots, for the receiver sometimes when you 1452 * write to its control registers not all the bits get there 1453 * properly. I cannot think of a sane way to provide complete 1454 * coverage for this hardware bug yet. 1455 */ 1456 HMD("erx regs bug old[%08x]\n", 1457 hme_read32(hp, erxregs + ERX_CFG)); 1458 hme_write32(hp, erxregs + ERX_CFG, ERX_CFG_DEFAULT(RX_OFFSET)); 1459 regtmp = hme_read32(hp, erxregs + ERX_CFG); 1460 hme_write32(hp, erxregs + ERX_CFG, ERX_CFG_DEFAULT(RX_OFFSET)); 1461 if (hme_read32(hp, erxregs + ERX_CFG) != ERX_CFG_DEFAULT(RX_OFFSET)) { 1462 netdev_err(hp->dev, 1463 "Eieee, rx config register gets greasy fries.\n"); 1464 netdev_err(hp->dev, 1465 "Trying to set %08x, reread gives %08x\n", 1466 ERX_CFG_DEFAULT(RX_OFFSET), regtmp); 1467 /* XXX Should return failure here... */ 1468 } 1469 1470 /* Enable Big Mac hash table filter. */ 1471 HMD("enable hash rx_cfg_old[%08x]\n", 1472 hme_read32(hp, bregs + BMAC_RXCFG)); 1473 rxcfg = BIGMAC_RXCFG_HENABLE | BIGMAC_RXCFG_REJME; 1474 if (hp->dev->flags & IFF_PROMISC) 1475 rxcfg |= BIGMAC_RXCFG_PMISC; 1476 hme_write32(hp, bregs + BMAC_RXCFG, rxcfg); 1477 1478 /* Let the bits settle in the chip. */ 1479 udelay(10); 1480 1481 /* Ok, configure the Big Mac transmitter. */ 1482 HMD("BIGMAC init\n"); 1483 regtmp = 0; 1484 if (hp->happy_flags & HFLAG_FULL) 1485 regtmp |= BIGMAC_TXCFG_FULLDPLX; 1486 1487 /* Don't turn on the "don't give up" bit for now. It could cause hme 1488 * to deadlock with the PHY if a Jabber occurs. 1489 */ 1490 hme_write32(hp, bregs + BMAC_TXCFG, regtmp /*| BIGMAC_TXCFG_DGIVEUP*/); 1491 1492 /* Give up after 16 TX attempts. */ 1493 hme_write32(hp, bregs + BMAC_ALIMIT, 16); 1494 1495 /* Enable the output drivers no matter what. */ 1496 regtmp = BIGMAC_XCFG_ODENABLE; 1497 1498 /* If card can do lance mode, enable it. */ 1499 if (hp->happy_flags & HFLAG_LANCE) 1500 regtmp |= (DEFAULT_IPG0 << 5) | BIGMAC_XCFG_LANCE; 1501 1502 /* Disable the MII buffers if using external transceiver. */ 1503 if (hp->tcvr_type == external) 1504 regtmp |= BIGMAC_XCFG_MIIDISAB; 1505 1506 HMD("XIF config old[%08x]\n", hme_read32(hp, bregs + BMAC_XIFCFG)); 1507 hme_write32(hp, bregs + BMAC_XIFCFG, regtmp); 1508 1509 /* Start things up. */ 1510 HMD("tx old[%08x] and rx [%08x] ON!\n", 1511 hme_read32(hp, bregs + BMAC_TXCFG), 1512 hme_read32(hp, bregs + BMAC_RXCFG)); 1513 1514 /* Set larger TX/RX size to allow for 802.1q */ 1515 hme_write32(hp, bregs + BMAC_TXMAX, ETH_FRAME_LEN + 8); 1516 hme_write32(hp, bregs + BMAC_RXMAX, ETH_FRAME_LEN + 8); 1517 1518 hme_write32(hp, bregs + BMAC_TXCFG, 1519 hme_read32(hp, bregs + BMAC_TXCFG) | BIGMAC_TXCFG_ENABLE); 1520 hme_write32(hp, bregs + BMAC_RXCFG, 1521 hme_read32(hp, bregs + BMAC_RXCFG) | BIGMAC_RXCFG_ENABLE); 1522 1523 /* Get the autonegotiation started, and the watch timer ticking. */ 1524 happy_meal_begin_auto_negotiation(hp, tregs, NULL); 1525 1526 /* Success. */ 1527 return 0; 1528 } 1529 1530 /* hp->happy_lock must be held */ 1531 static void happy_meal_set_initial_advertisement(struct happy_meal *hp) 1532 { 1533 void __iomem *tregs = hp->tcvregs; 1534 void __iomem *bregs = hp->bigmacregs; 1535 void __iomem *gregs = hp->gregs; 1536 1537 happy_meal_stop(hp, gregs); 1538 if (hp->happy_flags & HFLAG_FENABLE) 1539 hme_write32(hp, tregs + TCVR_CFG, 1540 hme_read32(hp, tregs + TCVR_CFG) & ~(TCV_CFG_BENABLE)); 1541 else 1542 hme_write32(hp, tregs + TCVR_CFG, 1543 hme_read32(hp, tregs + TCVR_CFG) | TCV_CFG_BENABLE); 1544 happy_meal_transceiver_check(hp, tregs); 1545 switch(hp->tcvr_type) { 1546 case none: 1547 return; 1548 case internal: 1549 hme_write32(hp, bregs + BMAC_XIFCFG, 0); 1550 break; 1551 case external: 1552 hme_write32(hp, bregs + BMAC_XIFCFG, BIGMAC_XCFG_MIIDISAB); 1553 break; 1554 } 1555 if (happy_meal_tcvr_reset(hp, tregs)) 1556 return; 1557 1558 /* Latch PHY registers as of now. */ 1559 hp->sw_bmsr = happy_meal_tcvr_read(hp, tregs, MII_BMSR); 1560 hp->sw_advertise = happy_meal_tcvr_read(hp, tregs, MII_ADVERTISE); 1561 1562 /* Advertise everything we can support. */ 1563 if (hp->sw_bmsr & BMSR_10HALF) 1564 hp->sw_advertise |= (ADVERTISE_10HALF); 1565 else 1566 hp->sw_advertise &= ~(ADVERTISE_10HALF); 1567 1568 if (hp->sw_bmsr & BMSR_10FULL) 1569 hp->sw_advertise |= (ADVERTISE_10FULL); 1570 else 1571 hp->sw_advertise &= ~(ADVERTISE_10FULL); 1572 if (hp->sw_bmsr & BMSR_100HALF) 1573 hp->sw_advertise |= (ADVERTISE_100HALF); 1574 else 1575 hp->sw_advertise &= ~(ADVERTISE_100HALF); 1576 if (hp->sw_bmsr & BMSR_100FULL) 1577 hp->sw_advertise |= (ADVERTISE_100FULL); 1578 else 1579 hp->sw_advertise &= ~(ADVERTISE_100FULL); 1580 1581 /* Update the PHY advertisement register. */ 1582 happy_meal_tcvr_write(hp, tregs, MII_ADVERTISE, hp->sw_advertise); 1583 } 1584 1585 /* Once status is latched (by happy_meal_interrupt) it is cleared by 1586 * the hardware, so we cannot re-read it and get a correct value. 1587 * 1588 * hp->happy_lock must be held 1589 */ 1590 static int happy_meal_is_not_so_happy(struct happy_meal *hp, u32 status) 1591 { 1592 int reset = 0; 1593 1594 /* Only print messages for non-counter related interrupts. */ 1595 if (status & (GREG_STAT_STSTERR | GREG_STAT_TFIFO_UND | 1596 GREG_STAT_MAXPKTERR | GREG_STAT_RXERR | 1597 GREG_STAT_RXPERR | GREG_STAT_RXTERR | GREG_STAT_EOPERR | 1598 GREG_STAT_MIFIRQ | GREG_STAT_TXEACK | GREG_STAT_TXLERR | 1599 GREG_STAT_TXPERR | GREG_STAT_TXTERR | GREG_STAT_SLVERR | 1600 GREG_STAT_SLVPERR)) 1601 netdev_err(hp->dev, 1602 "Error interrupt for happy meal, status = %08x\n", 1603 status); 1604 1605 if (status & GREG_STAT_RFIFOVF) { 1606 /* Receive FIFO overflow is harmless and the hardware will take 1607 care of it, just some packets are lost. Who cares. */ 1608 netdev_dbg(hp->dev, "Happy Meal receive FIFO overflow.\n"); 1609 } 1610 1611 if (status & GREG_STAT_STSTERR) { 1612 /* BigMAC SQE link test failed. */ 1613 netdev_err(hp->dev, "Happy Meal BigMAC SQE test failed.\n"); 1614 reset = 1; 1615 } 1616 1617 if (status & GREG_STAT_TFIFO_UND) { 1618 /* Transmit FIFO underrun, again DMA error likely. */ 1619 netdev_err(hp->dev, 1620 "Happy Meal transmitter FIFO underrun, DMA error.\n"); 1621 reset = 1; 1622 } 1623 1624 if (status & GREG_STAT_MAXPKTERR) { 1625 /* Driver error, tried to transmit something larger 1626 * than ethernet max mtu. 1627 */ 1628 netdev_err(hp->dev, "Happy Meal MAX Packet size error.\n"); 1629 reset = 1; 1630 } 1631 1632 if (status & GREG_STAT_NORXD) { 1633 /* This is harmless, it just means the system is 1634 * quite loaded and the incoming packet rate was 1635 * faster than the interrupt handler could keep up 1636 * with. 1637 */ 1638 netdev_info(hp->dev, 1639 "Happy Meal out of receive descriptors, packet dropped.\n"); 1640 } 1641 1642 if (status & (GREG_STAT_RXERR|GREG_STAT_RXPERR|GREG_STAT_RXTERR)) { 1643 /* All sorts of DMA receive errors. */ 1644 netdev_err(hp->dev, "Happy Meal rx DMA errors [ %s%s%s]\n", 1645 status & GREG_STAT_RXERR ? "GenericError " : "", 1646 status & GREG_STAT_RXPERR ? "ParityError " : "", 1647 status & GREG_STAT_RXTERR ? "RxTagBotch " : ""); 1648 reset = 1; 1649 } 1650 1651 if (status & GREG_STAT_EOPERR) { 1652 /* Driver bug, didn't set EOP bit in tx descriptor given 1653 * to the happy meal. 1654 */ 1655 netdev_err(hp->dev, 1656 "EOP not set in happy meal transmit descriptor!\n"); 1657 reset = 1; 1658 } 1659 1660 if (status & GREG_STAT_MIFIRQ) { 1661 /* MIF signalled an interrupt, were we polling it? */ 1662 netdev_err(hp->dev, "Happy Meal MIF interrupt.\n"); 1663 } 1664 1665 if (status & 1666 (GREG_STAT_TXEACK|GREG_STAT_TXLERR|GREG_STAT_TXPERR|GREG_STAT_TXTERR)) { 1667 /* All sorts of transmit DMA errors. */ 1668 netdev_err(hp->dev, "Happy Meal tx DMA errors [ %s%s%s%s]\n", 1669 status & GREG_STAT_TXEACK ? "GenericError " : "", 1670 status & GREG_STAT_TXLERR ? "LateError " : "", 1671 status & GREG_STAT_TXPERR ? "ParityError " : "", 1672 status & GREG_STAT_TXTERR ? "TagBotch " : ""); 1673 reset = 1; 1674 } 1675 1676 if (status & (GREG_STAT_SLVERR|GREG_STAT_SLVPERR)) { 1677 /* Bus or parity error when cpu accessed happy meal registers 1678 * or it's internal FIFO's. Should never see this. 1679 */ 1680 netdev_err(hp->dev, 1681 "Happy Meal register access SBUS slave (%s) error.\n", 1682 (status & GREG_STAT_SLVPERR) ? "parity" : "generic"); 1683 reset = 1; 1684 } 1685 1686 if (reset) { 1687 netdev_notice(hp->dev, "Resetting...\n"); 1688 happy_meal_init(hp); 1689 return 1; 1690 } 1691 return 0; 1692 } 1693 1694 /* hp->happy_lock must be held */ 1695 static void happy_meal_tx(struct happy_meal *hp) 1696 { 1697 struct happy_meal_txd *txbase = &hp->happy_block->happy_meal_txd[0]; 1698 struct happy_meal_txd *this; 1699 struct net_device *dev = hp->dev; 1700 int elem; 1701 1702 elem = hp->tx_old; 1703 while (elem != hp->tx_new) { 1704 struct sk_buff *skb; 1705 u32 flags, dma_addr, dma_len; 1706 int frag; 1707 1708 netdev_vdbg(hp->dev, "TX[%d]\n", elem); 1709 this = &txbase[elem]; 1710 flags = hme_read_desc32(hp, &this->tx_flags); 1711 if (flags & TXFLAG_OWN) 1712 break; 1713 skb = hp->tx_skbs[elem]; 1714 if (skb_shinfo(skb)->nr_frags) { 1715 int last; 1716 1717 last = elem + skb_shinfo(skb)->nr_frags; 1718 last &= (TX_RING_SIZE - 1); 1719 flags = hme_read_desc32(hp, &txbase[last].tx_flags); 1720 if (flags & TXFLAG_OWN) 1721 break; 1722 } 1723 hp->tx_skbs[elem] = NULL; 1724 dev->stats.tx_bytes += skb->len; 1725 1726 for (frag = 0; frag <= skb_shinfo(skb)->nr_frags; frag++) { 1727 dma_addr = hme_read_desc32(hp, &this->tx_addr); 1728 dma_len = hme_read_desc32(hp, &this->tx_flags); 1729 1730 dma_len &= TXFLAG_SIZE; 1731 if (!frag) 1732 dma_unmap_single(hp->dma_dev, dma_addr, dma_len, DMA_TO_DEVICE); 1733 else 1734 dma_unmap_page(hp->dma_dev, dma_addr, dma_len, DMA_TO_DEVICE); 1735 1736 elem = NEXT_TX(elem); 1737 this = &txbase[elem]; 1738 } 1739 1740 dev_consume_skb_irq(skb); 1741 dev->stats.tx_packets++; 1742 } 1743 hp->tx_old = elem; 1744 1745 if (netif_queue_stopped(dev) && 1746 TX_BUFFS_AVAIL(hp) > (MAX_SKB_FRAGS + 1)) 1747 netif_wake_queue(dev); 1748 } 1749 1750 /* Originally I used to handle the allocation failure by just giving back just 1751 * that one ring buffer to the happy meal. Problem is that usually when that 1752 * condition is triggered, the happy meal expects you to do something reasonable 1753 * with all of the packets it has DMA'd in. So now I just drop the entire 1754 * ring when we cannot get a new skb and give them all back to the happy meal, 1755 * maybe things will be "happier" now. 1756 * 1757 * hp->happy_lock must be held 1758 */ 1759 static void happy_meal_rx(struct happy_meal *hp, struct net_device *dev) 1760 { 1761 struct happy_meal_rxd *rxbase = &hp->happy_block->happy_meal_rxd[0]; 1762 struct happy_meal_rxd *this; 1763 int elem = hp->rx_new, drops = 0; 1764 u32 flags; 1765 1766 this = &rxbase[elem]; 1767 while (!((flags = hme_read_desc32(hp, &this->rx_flags)) & RXFLAG_OWN)) { 1768 struct sk_buff *skb; 1769 int len = flags >> 16; 1770 u16 csum = flags & RXFLAG_CSUM; 1771 u32 dma_addr = hme_read_desc32(hp, &this->rx_addr); 1772 1773 /* Check for errors. */ 1774 if ((len < ETH_ZLEN) || (flags & RXFLAG_OVERFLOW)) { 1775 netdev_vdbg(dev, "RX[%d ERR(%08x)]", elem, flags); 1776 dev->stats.rx_errors++; 1777 if (len < ETH_ZLEN) 1778 dev->stats.rx_length_errors++; 1779 if (len & (RXFLAG_OVERFLOW >> 16)) { 1780 dev->stats.rx_over_errors++; 1781 dev->stats.rx_fifo_errors++; 1782 } 1783 1784 /* Return it to the Happy meal. */ 1785 drop_it: 1786 dev->stats.rx_dropped++; 1787 hme_write_rxd(hp, this, 1788 (RXFLAG_OWN|((RX_BUF_ALLOC_SIZE-RX_OFFSET)<<16)), 1789 dma_addr); 1790 goto next; 1791 } 1792 skb = hp->rx_skbs[elem]; 1793 if (len > RX_COPY_THRESHOLD) { 1794 struct sk_buff *new_skb; 1795 u32 mapping; 1796 1797 /* Now refill the entry, if we can. */ 1798 new_skb = happy_meal_alloc_skb(RX_BUF_ALLOC_SIZE, GFP_ATOMIC); 1799 if (new_skb == NULL) { 1800 drops++; 1801 goto drop_it; 1802 } 1803 skb_put(new_skb, (ETH_FRAME_LEN + RX_OFFSET + 4)); 1804 mapping = dma_map_single(hp->dma_dev, new_skb->data, 1805 RX_BUF_ALLOC_SIZE, 1806 DMA_FROM_DEVICE); 1807 if (unlikely(dma_mapping_error(hp->dma_dev, mapping))) { 1808 dev_kfree_skb_any(new_skb); 1809 drops++; 1810 goto drop_it; 1811 } 1812 1813 dma_unmap_single(hp->dma_dev, dma_addr, RX_BUF_ALLOC_SIZE, DMA_FROM_DEVICE); 1814 hp->rx_skbs[elem] = new_skb; 1815 hme_write_rxd(hp, this, 1816 (RXFLAG_OWN|((RX_BUF_ALLOC_SIZE-RX_OFFSET)<<16)), 1817 mapping); 1818 skb_reserve(new_skb, RX_OFFSET); 1819 1820 /* Trim the original skb for the netif. */ 1821 skb_trim(skb, len); 1822 } else { 1823 struct sk_buff *copy_skb = netdev_alloc_skb(dev, len + 2); 1824 1825 if (copy_skb == NULL) { 1826 drops++; 1827 goto drop_it; 1828 } 1829 1830 skb_reserve(copy_skb, 2); 1831 skb_put(copy_skb, len); 1832 dma_sync_single_for_cpu(hp->dma_dev, dma_addr, len + 2, DMA_FROM_DEVICE); 1833 skb_copy_from_linear_data(skb, copy_skb->data, len); 1834 dma_sync_single_for_device(hp->dma_dev, dma_addr, len + 2, DMA_FROM_DEVICE); 1835 /* Reuse original ring buffer. */ 1836 hme_write_rxd(hp, this, 1837 (RXFLAG_OWN|((RX_BUF_ALLOC_SIZE-RX_OFFSET)<<16)), 1838 dma_addr); 1839 1840 skb = copy_skb; 1841 } 1842 1843 /* This card is _fucking_ hot... */ 1844 skb->csum = csum_unfold(~(__force __sum16)htons(csum)); 1845 skb->ip_summed = CHECKSUM_COMPLETE; 1846 1847 netdev_vdbg(dev, "RX[%d len=%d csum=%4x]", elem, len, csum); 1848 skb->protocol = eth_type_trans(skb, dev); 1849 netif_rx(skb); 1850 1851 dev->stats.rx_packets++; 1852 dev->stats.rx_bytes += len; 1853 next: 1854 elem = NEXT_RX(elem); 1855 this = &rxbase[elem]; 1856 } 1857 hp->rx_new = elem; 1858 if (drops) 1859 netdev_info(hp->dev, "Memory squeeze, deferring packet.\n"); 1860 } 1861 1862 static irqreturn_t happy_meal_interrupt(int irq, void *dev_id) 1863 { 1864 struct net_device *dev = dev_id; 1865 struct happy_meal *hp = netdev_priv(dev); 1866 u32 happy_status = hme_read32(hp, hp->gregs + GREG_STAT); 1867 1868 HMD("status=%08x\n", happy_status); 1869 if (!happy_status) 1870 return IRQ_NONE; 1871 1872 spin_lock(&hp->happy_lock); 1873 1874 if (happy_status & GREG_STAT_ERRORS) { 1875 if (happy_meal_is_not_so_happy(hp, /* un- */ happy_status)) 1876 goto out; 1877 } 1878 1879 if (happy_status & GREG_STAT_TXALL) 1880 happy_meal_tx(hp); 1881 1882 if (happy_status & GREG_STAT_RXTOHOST) 1883 happy_meal_rx(hp, dev); 1884 1885 HMD("done\n"); 1886 out: 1887 spin_unlock(&hp->happy_lock); 1888 1889 return IRQ_HANDLED; 1890 } 1891 1892 static int happy_meal_open(struct net_device *dev) 1893 { 1894 struct happy_meal *hp = netdev_priv(dev); 1895 int res; 1896 1897 res = request_irq(hp->irq, happy_meal_interrupt, IRQF_SHARED, 1898 dev->name, dev); 1899 if (res) { 1900 netdev_err(dev, "Can't order irq %d to go.\n", hp->irq); 1901 return res; 1902 } 1903 1904 HMD("to happy_meal_init\n"); 1905 1906 spin_lock_irq(&hp->happy_lock); 1907 res = happy_meal_init(hp); 1908 spin_unlock_irq(&hp->happy_lock); 1909 1910 if (res) 1911 free_irq(hp->irq, dev); 1912 return res; 1913 } 1914 1915 static int happy_meal_close(struct net_device *dev) 1916 { 1917 struct happy_meal *hp = netdev_priv(dev); 1918 1919 spin_lock_irq(&hp->happy_lock); 1920 happy_meal_stop(hp, hp->gregs); 1921 happy_meal_clean_rings(hp); 1922 1923 /* If auto-negotiation timer is running, kill it. */ 1924 del_timer(&hp->happy_timer); 1925 1926 spin_unlock_irq(&hp->happy_lock); 1927 1928 free_irq(hp->irq, dev); 1929 1930 return 0; 1931 } 1932 1933 static void happy_meal_tx_timeout(struct net_device *dev, unsigned int txqueue) 1934 { 1935 struct happy_meal *hp = netdev_priv(dev); 1936 1937 netdev_err(dev, "transmit timed out, resetting\n"); 1938 tx_dump_log(); 1939 netdev_err(dev, "Happy Status %08x TX[%08x:%08x]\n", 1940 hme_read32(hp, hp->gregs + GREG_STAT), 1941 hme_read32(hp, hp->etxregs + ETX_CFG), 1942 hme_read32(hp, hp->bigmacregs + BMAC_TXCFG)); 1943 1944 spin_lock_irq(&hp->happy_lock); 1945 happy_meal_init(hp); 1946 spin_unlock_irq(&hp->happy_lock); 1947 1948 netif_wake_queue(dev); 1949 } 1950 1951 static void unmap_partial_tx_skb(struct happy_meal *hp, u32 first_mapping, 1952 u32 first_len, u32 first_entry, u32 entry) 1953 { 1954 struct happy_meal_txd *txbase = &hp->happy_block->happy_meal_txd[0]; 1955 1956 dma_unmap_single(hp->dma_dev, first_mapping, first_len, DMA_TO_DEVICE); 1957 1958 first_entry = NEXT_TX(first_entry); 1959 while (first_entry != entry) { 1960 struct happy_meal_txd *this = &txbase[first_entry]; 1961 u32 addr, len; 1962 1963 addr = hme_read_desc32(hp, &this->tx_addr); 1964 len = hme_read_desc32(hp, &this->tx_flags); 1965 len &= TXFLAG_SIZE; 1966 dma_unmap_page(hp->dma_dev, addr, len, DMA_TO_DEVICE); 1967 } 1968 } 1969 1970 static netdev_tx_t happy_meal_start_xmit(struct sk_buff *skb, 1971 struct net_device *dev) 1972 { 1973 struct happy_meal *hp = netdev_priv(dev); 1974 int entry; 1975 u32 tx_flags; 1976 1977 tx_flags = TXFLAG_OWN; 1978 if (skb->ip_summed == CHECKSUM_PARTIAL) { 1979 const u32 csum_start_off = skb_checksum_start_offset(skb); 1980 const u32 csum_stuff_off = csum_start_off + skb->csum_offset; 1981 1982 tx_flags = (TXFLAG_OWN | TXFLAG_CSENABLE | 1983 ((csum_start_off << 14) & TXFLAG_CSBUFBEGIN) | 1984 ((csum_stuff_off << 20) & TXFLAG_CSLOCATION)); 1985 } 1986 1987 spin_lock_irq(&hp->happy_lock); 1988 1989 if (TX_BUFFS_AVAIL(hp) <= (skb_shinfo(skb)->nr_frags + 1)) { 1990 netif_stop_queue(dev); 1991 spin_unlock_irq(&hp->happy_lock); 1992 netdev_err(dev, "BUG! Tx Ring full when queue awake!\n"); 1993 return NETDEV_TX_BUSY; 1994 } 1995 1996 entry = hp->tx_new; 1997 netdev_vdbg(dev, "SX<l[%d]e[%d]>\n", skb->len, entry); 1998 hp->tx_skbs[entry] = skb; 1999 2000 if (skb_shinfo(skb)->nr_frags == 0) { 2001 u32 mapping, len; 2002 2003 len = skb->len; 2004 mapping = dma_map_single(hp->dma_dev, skb->data, len, DMA_TO_DEVICE); 2005 if (unlikely(dma_mapping_error(hp->dma_dev, mapping))) 2006 goto out_dma_error; 2007 tx_flags |= (TXFLAG_SOP | TXFLAG_EOP); 2008 hme_write_txd(hp, &hp->happy_block->happy_meal_txd[entry], 2009 (tx_flags | (len & TXFLAG_SIZE)), 2010 mapping); 2011 entry = NEXT_TX(entry); 2012 } else { 2013 u32 first_len, first_mapping; 2014 int frag, first_entry = entry; 2015 2016 /* We must give this initial chunk to the device last. 2017 * Otherwise we could race with the device. 2018 */ 2019 first_len = skb_headlen(skb); 2020 first_mapping = dma_map_single(hp->dma_dev, skb->data, first_len, 2021 DMA_TO_DEVICE); 2022 if (unlikely(dma_mapping_error(hp->dma_dev, first_mapping))) 2023 goto out_dma_error; 2024 entry = NEXT_TX(entry); 2025 2026 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) { 2027 const skb_frag_t *this_frag = &skb_shinfo(skb)->frags[frag]; 2028 u32 len, mapping, this_txflags; 2029 2030 len = skb_frag_size(this_frag); 2031 mapping = skb_frag_dma_map(hp->dma_dev, this_frag, 2032 0, len, DMA_TO_DEVICE); 2033 if (unlikely(dma_mapping_error(hp->dma_dev, mapping))) { 2034 unmap_partial_tx_skb(hp, first_mapping, first_len, 2035 first_entry, entry); 2036 goto out_dma_error; 2037 } 2038 this_txflags = tx_flags; 2039 if (frag == skb_shinfo(skb)->nr_frags - 1) 2040 this_txflags |= TXFLAG_EOP; 2041 hme_write_txd(hp, &hp->happy_block->happy_meal_txd[entry], 2042 (this_txflags | (len & TXFLAG_SIZE)), 2043 mapping); 2044 entry = NEXT_TX(entry); 2045 } 2046 hme_write_txd(hp, &hp->happy_block->happy_meal_txd[first_entry], 2047 (tx_flags | TXFLAG_SOP | (first_len & TXFLAG_SIZE)), 2048 first_mapping); 2049 } 2050 2051 hp->tx_new = entry; 2052 2053 if (TX_BUFFS_AVAIL(hp) <= (MAX_SKB_FRAGS + 1)) 2054 netif_stop_queue(dev); 2055 2056 /* Get it going. */ 2057 hme_write32(hp, hp->etxregs + ETX_PENDING, ETX_TP_DMAWAKEUP); 2058 2059 spin_unlock_irq(&hp->happy_lock); 2060 2061 tx_add_log(hp, TXLOG_ACTION_TXMIT, 0); 2062 return NETDEV_TX_OK; 2063 2064 out_dma_error: 2065 hp->tx_skbs[hp->tx_new] = NULL; 2066 spin_unlock_irq(&hp->happy_lock); 2067 2068 dev_kfree_skb_any(skb); 2069 dev->stats.tx_dropped++; 2070 return NETDEV_TX_OK; 2071 } 2072 2073 static struct net_device_stats *happy_meal_get_stats(struct net_device *dev) 2074 { 2075 struct happy_meal *hp = netdev_priv(dev); 2076 2077 spin_lock_irq(&hp->happy_lock); 2078 happy_meal_get_counters(hp, hp->bigmacregs); 2079 spin_unlock_irq(&hp->happy_lock); 2080 2081 return &dev->stats; 2082 } 2083 2084 static void happy_meal_set_multicast(struct net_device *dev) 2085 { 2086 struct happy_meal *hp = netdev_priv(dev); 2087 void __iomem *bregs = hp->bigmacregs; 2088 struct netdev_hw_addr *ha; 2089 u32 crc; 2090 2091 spin_lock_irq(&hp->happy_lock); 2092 2093 if ((dev->flags & IFF_ALLMULTI) || (netdev_mc_count(dev) > 64)) { 2094 hme_write32(hp, bregs + BMAC_HTABLE0, 0xffff); 2095 hme_write32(hp, bregs + BMAC_HTABLE1, 0xffff); 2096 hme_write32(hp, bregs + BMAC_HTABLE2, 0xffff); 2097 hme_write32(hp, bregs + BMAC_HTABLE3, 0xffff); 2098 } else if (dev->flags & IFF_PROMISC) { 2099 hme_write32(hp, bregs + BMAC_RXCFG, 2100 hme_read32(hp, bregs + BMAC_RXCFG) | BIGMAC_RXCFG_PMISC); 2101 } else { 2102 u16 hash_table[4]; 2103 2104 memset(hash_table, 0, sizeof(hash_table)); 2105 netdev_for_each_mc_addr(ha, dev) { 2106 crc = ether_crc_le(6, ha->addr); 2107 crc >>= 26; 2108 hash_table[crc >> 4] |= 1 << (crc & 0xf); 2109 } 2110 hme_write32(hp, bregs + BMAC_HTABLE0, hash_table[0]); 2111 hme_write32(hp, bregs + BMAC_HTABLE1, hash_table[1]); 2112 hme_write32(hp, bregs + BMAC_HTABLE2, hash_table[2]); 2113 hme_write32(hp, bregs + BMAC_HTABLE3, hash_table[3]); 2114 } 2115 2116 spin_unlock_irq(&hp->happy_lock); 2117 } 2118 2119 /* Ethtool support... */ 2120 static int hme_get_link_ksettings(struct net_device *dev, 2121 struct ethtool_link_ksettings *cmd) 2122 { 2123 struct happy_meal *hp = netdev_priv(dev); 2124 u32 speed; 2125 u32 supported; 2126 2127 supported = 2128 (SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full | 2129 SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full | 2130 SUPPORTED_Autoneg | SUPPORTED_TP | SUPPORTED_MII); 2131 2132 /* XXX hardcoded stuff for now */ 2133 cmd->base.port = PORT_TP; /* XXX no MII support */ 2134 cmd->base.phy_address = 0; /* XXX fixed PHYAD */ 2135 2136 /* Record PHY settings. */ 2137 spin_lock_irq(&hp->happy_lock); 2138 hp->sw_bmcr = happy_meal_tcvr_read(hp, hp->tcvregs, MII_BMCR); 2139 hp->sw_lpa = happy_meal_tcvr_read(hp, hp->tcvregs, MII_LPA); 2140 spin_unlock_irq(&hp->happy_lock); 2141 2142 if (hp->sw_bmcr & BMCR_ANENABLE) { 2143 cmd->base.autoneg = AUTONEG_ENABLE; 2144 speed = ((hp->sw_lpa & (LPA_100HALF | LPA_100FULL)) ? 2145 SPEED_100 : SPEED_10); 2146 if (speed == SPEED_100) 2147 cmd->base.duplex = 2148 (hp->sw_lpa & (LPA_100FULL)) ? 2149 DUPLEX_FULL : DUPLEX_HALF; 2150 else 2151 cmd->base.duplex = 2152 (hp->sw_lpa & (LPA_10FULL)) ? 2153 DUPLEX_FULL : DUPLEX_HALF; 2154 } else { 2155 cmd->base.autoneg = AUTONEG_DISABLE; 2156 speed = (hp->sw_bmcr & BMCR_SPEED100) ? SPEED_100 : SPEED_10; 2157 cmd->base.duplex = 2158 (hp->sw_bmcr & BMCR_FULLDPLX) ? 2159 DUPLEX_FULL : DUPLEX_HALF; 2160 } 2161 cmd->base.speed = speed; 2162 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.supported, 2163 supported); 2164 2165 return 0; 2166 } 2167 2168 static int hme_set_link_ksettings(struct net_device *dev, 2169 const struct ethtool_link_ksettings *cmd) 2170 { 2171 struct happy_meal *hp = netdev_priv(dev); 2172 2173 /* Verify the settings we care about. */ 2174 if (cmd->base.autoneg != AUTONEG_ENABLE && 2175 cmd->base.autoneg != AUTONEG_DISABLE) 2176 return -EINVAL; 2177 if (cmd->base.autoneg == AUTONEG_DISABLE && 2178 ((cmd->base.speed != SPEED_100 && 2179 cmd->base.speed != SPEED_10) || 2180 (cmd->base.duplex != DUPLEX_HALF && 2181 cmd->base.duplex != DUPLEX_FULL))) 2182 return -EINVAL; 2183 2184 /* Ok, do it to it. */ 2185 spin_lock_irq(&hp->happy_lock); 2186 del_timer(&hp->happy_timer); 2187 happy_meal_begin_auto_negotiation(hp, hp->tcvregs, cmd); 2188 spin_unlock_irq(&hp->happy_lock); 2189 2190 return 0; 2191 } 2192 2193 static void hme_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info) 2194 { 2195 struct happy_meal *hp = netdev_priv(dev); 2196 2197 strscpy(info->driver, DRV_NAME, sizeof(info->driver)); 2198 if (hp->happy_flags & HFLAG_PCI) { 2199 struct pci_dev *pdev = hp->happy_dev; 2200 strscpy(info->bus_info, pci_name(pdev), sizeof(info->bus_info)); 2201 } 2202 #ifdef CONFIG_SBUS 2203 else { 2204 const struct linux_prom_registers *regs; 2205 struct platform_device *op = hp->happy_dev; 2206 regs = of_get_property(op->dev.of_node, "regs", NULL); 2207 if (regs) 2208 snprintf(info->bus_info, sizeof(info->bus_info), 2209 "SBUS:%d", 2210 regs->which_io); 2211 } 2212 #endif 2213 } 2214 2215 static u32 hme_get_link(struct net_device *dev) 2216 { 2217 struct happy_meal *hp = netdev_priv(dev); 2218 2219 spin_lock_irq(&hp->happy_lock); 2220 hp->sw_bmcr = happy_meal_tcvr_read(hp, hp->tcvregs, MII_BMCR); 2221 spin_unlock_irq(&hp->happy_lock); 2222 2223 return hp->sw_bmsr & BMSR_LSTATUS; 2224 } 2225 2226 static const struct ethtool_ops hme_ethtool_ops = { 2227 .get_drvinfo = hme_get_drvinfo, 2228 .get_link = hme_get_link, 2229 .get_link_ksettings = hme_get_link_ksettings, 2230 .set_link_ksettings = hme_set_link_ksettings, 2231 }; 2232 2233 #ifdef CONFIG_SBUS 2234 /* Given a happy meal sbus device, find it's quattro parent. 2235 * If none exist, allocate and return a new one. 2236 * 2237 * Return NULL on failure. 2238 */ 2239 static struct quattro *quattro_sbus_find(struct platform_device *child) 2240 { 2241 struct device *parent = child->dev.parent; 2242 struct platform_device *op; 2243 struct quattro *qp; 2244 2245 op = to_platform_device(parent); 2246 qp = platform_get_drvdata(op); 2247 if (qp) 2248 return qp; 2249 2250 qp = kzalloc(sizeof(*qp), GFP_KERNEL); 2251 if (!qp) 2252 return NULL; 2253 2254 qp->quattro_dev = child; 2255 qp->next = qfe_sbus_list; 2256 qfe_sbus_list = qp; 2257 2258 platform_set_drvdata(op, qp); 2259 return qp; 2260 } 2261 #endif /* CONFIG_SBUS */ 2262 2263 #ifdef CONFIG_PCI 2264 static struct quattro *quattro_pci_find(struct pci_dev *pdev) 2265 { 2266 int i; 2267 struct pci_dev *bdev = pdev->bus->self; 2268 struct quattro *qp; 2269 2270 if (!bdev) 2271 return ERR_PTR(-ENODEV); 2272 2273 for (qp = qfe_pci_list; qp != NULL; qp = qp->next) { 2274 struct pci_dev *qpdev = qp->quattro_dev; 2275 2276 if (qpdev == bdev) 2277 return qp; 2278 } 2279 2280 qp = kmalloc(sizeof(struct quattro), GFP_KERNEL); 2281 if (!qp) 2282 return ERR_PTR(-ENOMEM); 2283 2284 for (i = 0; i < 4; i++) 2285 qp->happy_meals[i] = NULL; 2286 2287 qp->quattro_dev = bdev; 2288 qp->next = qfe_pci_list; 2289 qfe_pci_list = qp; 2290 2291 /* No range tricks necessary on PCI. */ 2292 qp->nranges = 0; 2293 return qp; 2294 } 2295 #endif /* CONFIG_PCI */ 2296 2297 static const struct net_device_ops hme_netdev_ops = { 2298 .ndo_open = happy_meal_open, 2299 .ndo_stop = happy_meal_close, 2300 .ndo_start_xmit = happy_meal_start_xmit, 2301 .ndo_tx_timeout = happy_meal_tx_timeout, 2302 .ndo_get_stats = happy_meal_get_stats, 2303 .ndo_set_rx_mode = happy_meal_set_multicast, 2304 .ndo_set_mac_address = eth_mac_addr, 2305 .ndo_validate_addr = eth_validate_addr, 2306 }; 2307 2308 #ifdef CONFIG_PCI 2309 static int is_quattro_p(struct pci_dev *pdev) 2310 { 2311 struct pci_dev *busdev = pdev->bus->self; 2312 struct pci_dev *this_pdev; 2313 int n_hmes; 2314 2315 if (!busdev || busdev->vendor != PCI_VENDOR_ID_DEC || 2316 busdev->device != PCI_DEVICE_ID_DEC_21153) 2317 return 0; 2318 2319 n_hmes = 0; 2320 list_for_each_entry(this_pdev, &pdev->bus->devices, bus_list) { 2321 if (this_pdev->vendor == PCI_VENDOR_ID_SUN && 2322 this_pdev->device == PCI_DEVICE_ID_SUN_HAPPYMEAL) 2323 n_hmes++; 2324 } 2325 2326 if (n_hmes != 4) 2327 return 0; 2328 2329 return 1; 2330 } 2331 2332 /* Fetch MAC address from vital product data of PCI ROM. */ 2333 static int find_eth_addr_in_vpd(void __iomem *rom_base, int len, int index, unsigned char *dev_addr) 2334 { 2335 int this_offset; 2336 2337 for (this_offset = 0x20; this_offset < len; this_offset++) { 2338 void __iomem *p = rom_base + this_offset; 2339 2340 if (readb(p + 0) != 0x90 || 2341 readb(p + 1) != 0x00 || 2342 readb(p + 2) != 0x09 || 2343 readb(p + 3) != 0x4e || 2344 readb(p + 4) != 0x41 || 2345 readb(p + 5) != 0x06) 2346 continue; 2347 2348 this_offset += 6; 2349 p += 6; 2350 2351 if (index == 0) { 2352 for (int i = 0; i < 6; i++) 2353 dev_addr[i] = readb(p + i); 2354 return 1; 2355 } 2356 index--; 2357 } 2358 return 0; 2359 } 2360 2361 static void __maybe_unused get_hme_mac_nonsparc(struct pci_dev *pdev, 2362 unsigned char *dev_addr) 2363 { 2364 void __iomem *p; 2365 size_t size; 2366 2367 p = pci_map_rom(pdev, &size); 2368 if (p) { 2369 int index = 0; 2370 int found; 2371 2372 if (is_quattro_p(pdev)) 2373 index = PCI_SLOT(pdev->devfn); 2374 2375 found = readb(p) == 0x55 && 2376 readb(p + 1) == 0xaa && 2377 find_eth_addr_in_vpd(p, (64 * 1024), index, dev_addr); 2378 pci_unmap_rom(pdev, p); 2379 if (found) 2380 return; 2381 } 2382 2383 /* Sun MAC prefix then 3 random bytes. */ 2384 dev_addr[0] = 0x08; 2385 dev_addr[1] = 0x00; 2386 dev_addr[2] = 0x20; 2387 get_random_bytes(&dev_addr[3], 3); 2388 } 2389 #endif 2390 2391 static void happy_meal_addr_init(struct happy_meal *hp, 2392 struct device_node *dp, int qfe_slot) 2393 { 2394 int i; 2395 2396 for (i = 0; i < 6; i++) { 2397 if (macaddr[i] != 0) 2398 break; 2399 } 2400 2401 if (i < 6) { /* a mac address was given */ 2402 u8 addr[ETH_ALEN]; 2403 2404 for (i = 0; i < 6; i++) 2405 addr[i] = macaddr[i]; 2406 eth_hw_addr_set(hp->dev, addr); 2407 macaddr[5]++; 2408 } else { 2409 #ifdef CONFIG_SPARC 2410 const unsigned char *addr; 2411 int len; 2412 2413 /* If user did not specify a MAC address specifically, use 2414 * the Quattro local-mac-address property... 2415 */ 2416 if (qfe_slot != -1) { 2417 addr = of_get_property(dp, "local-mac-address", &len); 2418 if (addr && len == 6) { 2419 eth_hw_addr_set(hp->dev, addr); 2420 return; 2421 } 2422 } 2423 2424 eth_hw_addr_set(hp->dev, idprom->id_ethaddr); 2425 #else 2426 u8 addr[ETH_ALEN]; 2427 2428 get_hme_mac_nonsparc(hp->happy_dev, addr); 2429 eth_hw_addr_set(hp->dev, addr); 2430 #endif 2431 } 2432 } 2433 2434 static int happy_meal_common_probe(struct happy_meal *hp, 2435 struct device_node *dp) 2436 { 2437 struct net_device *dev = hp->dev; 2438 int err; 2439 2440 #ifdef CONFIG_SPARC 2441 hp->hm_revision = of_getintprop_default(dp, "hm-rev", hp->hm_revision); 2442 #endif 2443 2444 /* Now enable the feature flags we can. */ 2445 if (hp->hm_revision == 0x20 || hp->hm_revision == 0x21) 2446 hp->happy_flags |= HFLAG_20_21; 2447 else if (hp->hm_revision != 0xa0) 2448 hp->happy_flags |= HFLAG_NOT_A0; 2449 2450 hp->happy_block = dmam_alloc_coherent(hp->dma_dev, PAGE_SIZE, 2451 &hp->hblock_dvma, GFP_KERNEL); 2452 if (!hp->happy_block) 2453 return -ENOMEM; 2454 2455 /* Force check of the link first time we are brought up. */ 2456 hp->linkcheck = 0; 2457 2458 /* Force timer state to 'asleep' with count of zero. */ 2459 hp->timer_state = asleep; 2460 hp->timer_ticks = 0; 2461 2462 timer_setup(&hp->happy_timer, happy_meal_timer, 0); 2463 2464 dev->netdev_ops = &hme_netdev_ops; 2465 dev->watchdog_timeo = 5 * HZ; 2466 dev->ethtool_ops = &hme_ethtool_ops; 2467 2468 /* Happy Meal can do it all... */ 2469 dev->hw_features = NETIF_F_SG | NETIF_F_HW_CSUM; 2470 dev->features |= dev->hw_features | NETIF_F_RXCSUM; 2471 2472 2473 /* Grrr, Happy Meal comes up by default not advertising 2474 * full duplex 100baseT capabilities, fix this. 2475 */ 2476 spin_lock_irq(&hp->happy_lock); 2477 happy_meal_set_initial_advertisement(hp); 2478 spin_unlock_irq(&hp->happy_lock); 2479 2480 err = devm_register_netdev(hp->dma_dev, dev); 2481 if (err) 2482 dev_err(hp->dma_dev, "Cannot register net device, aborting.\n"); 2483 return err; 2484 } 2485 2486 #ifdef CONFIG_SBUS 2487 static int happy_meal_sbus_probe_one(struct platform_device *op, int is_qfe) 2488 { 2489 struct device_node *dp = op->dev.of_node, *sbus_dp; 2490 struct quattro *qp = NULL; 2491 struct happy_meal *hp; 2492 struct net_device *dev; 2493 int qfe_slot = -1; 2494 int err; 2495 2496 sbus_dp = op->dev.parent->of_node; 2497 2498 /* We can match PCI devices too, do not accept those here. */ 2499 if (!of_node_name_eq(sbus_dp, "sbus") && !of_node_name_eq(sbus_dp, "sbi")) 2500 return -ENODEV; 2501 2502 if (is_qfe) { 2503 qp = quattro_sbus_find(op); 2504 if (qp == NULL) 2505 return -ENODEV; 2506 for (qfe_slot = 0; qfe_slot < 4; qfe_slot++) 2507 if (qp->happy_meals[qfe_slot] == NULL) 2508 break; 2509 if (qfe_slot == 4) 2510 return -ENODEV; 2511 } 2512 2513 dev = devm_alloc_etherdev(&op->dev, sizeof(struct happy_meal)); 2514 if (!dev) 2515 return -ENOMEM; 2516 SET_NETDEV_DEV(dev, &op->dev); 2517 2518 hp = netdev_priv(dev); 2519 hp->dev = dev; 2520 hp->happy_dev = op; 2521 hp->dma_dev = &op->dev; 2522 happy_meal_addr_init(hp, dp, qfe_slot); 2523 2524 spin_lock_init(&hp->happy_lock); 2525 2526 if (qp != NULL) { 2527 hp->qfe_parent = qp; 2528 hp->qfe_ent = qfe_slot; 2529 qp->happy_meals[qfe_slot] = dev; 2530 } 2531 2532 hp->gregs = devm_platform_ioremap_resource(op, 0); 2533 if (IS_ERR(hp->gregs)) { 2534 dev_err(&op->dev, "Cannot map global registers.\n"); 2535 err = PTR_ERR(hp->gregs); 2536 goto err_out_clear_quattro; 2537 } 2538 2539 hp->etxregs = devm_platform_ioremap_resource(op, 1); 2540 if (IS_ERR(hp->etxregs)) { 2541 dev_err(&op->dev, "Cannot map MAC TX registers.\n"); 2542 err = PTR_ERR(hp->etxregs); 2543 goto err_out_clear_quattro; 2544 } 2545 2546 hp->erxregs = devm_platform_ioremap_resource(op, 2); 2547 if (IS_ERR(hp->erxregs)) { 2548 dev_err(&op->dev, "Cannot map MAC RX registers.\n"); 2549 err = PTR_ERR(hp->erxregs); 2550 goto err_out_clear_quattro; 2551 } 2552 2553 hp->bigmacregs = devm_platform_ioremap_resource(op, 3); 2554 if (IS_ERR(hp->bigmacregs)) { 2555 dev_err(&op->dev, "Cannot map BIGMAC registers.\n"); 2556 err = PTR_ERR(hp->bigmacregs); 2557 goto err_out_clear_quattro; 2558 } 2559 2560 hp->tcvregs = devm_platform_ioremap_resource(op, 4); 2561 if (IS_ERR(hp->tcvregs)) { 2562 dev_err(&op->dev, "Cannot map TCVR registers.\n"); 2563 err = PTR_ERR(hp->tcvregs); 2564 goto err_out_clear_quattro; 2565 } 2566 2567 hp->hm_revision = 0xa0; 2568 2569 if (qp != NULL) 2570 hp->happy_flags |= HFLAG_QUATTRO; 2571 2572 hp->irq = op->archdata.irqs[0]; 2573 2574 /* Get the supported DVMA burst sizes from our Happy SBUS. */ 2575 hp->happy_bursts = of_getintprop_default(sbus_dp, 2576 "burst-sizes", 0x00); 2577 2578 #ifdef CONFIG_PCI 2579 /* Hook up SBUS register/descriptor accessors. */ 2580 hp->read_desc32 = sbus_hme_read_desc32; 2581 hp->write_txd = sbus_hme_write_txd; 2582 hp->write_rxd = sbus_hme_write_rxd; 2583 hp->read32 = sbus_hme_read32; 2584 hp->write32 = sbus_hme_write32; 2585 #endif 2586 2587 err = happy_meal_common_probe(hp, dp); 2588 if (err) 2589 goto err_out_clear_quattro; 2590 2591 platform_set_drvdata(op, hp); 2592 2593 if (qfe_slot != -1) 2594 netdev_info(dev, 2595 "Quattro HME slot %d (SBUS) 10/100baseT Ethernet %pM\n", 2596 qfe_slot, dev->dev_addr); 2597 else 2598 netdev_info(dev, "HAPPY MEAL (SBUS) 10/100baseT Ethernet %pM\n", 2599 dev->dev_addr); 2600 2601 return 0; 2602 2603 err_out_clear_quattro: 2604 if (qp) 2605 qp->happy_meals[qfe_slot] = NULL; 2606 return err; 2607 } 2608 #endif 2609 2610 #ifdef CONFIG_PCI 2611 static int happy_meal_pci_probe(struct pci_dev *pdev, 2612 const struct pci_device_id *ent) 2613 { 2614 struct device_node *dp = NULL; 2615 struct quattro *qp = NULL; 2616 struct happy_meal *hp; 2617 struct net_device *dev; 2618 void __iomem *hpreg_base; 2619 struct resource *hpreg_res; 2620 char prom_name[64]; 2621 int qfe_slot = -1; 2622 int err = -ENODEV; 2623 2624 /* Now make sure pci_dev cookie is there. */ 2625 #ifdef CONFIG_SPARC 2626 dp = pci_device_to_OF_node(pdev); 2627 snprintf(prom_name, sizeof(prom_name), "%pOFn", dp); 2628 #else 2629 if (is_quattro_p(pdev)) 2630 strcpy(prom_name, "SUNW,qfe"); 2631 else 2632 strcpy(prom_name, "SUNW,hme"); 2633 #endif 2634 2635 err = pcim_enable_device(pdev); 2636 if (err) 2637 return err; 2638 pci_set_master(pdev); 2639 2640 if (!strcmp(prom_name, "SUNW,qfe") || !strcmp(prom_name, "qfe")) { 2641 qp = quattro_pci_find(pdev); 2642 if (IS_ERR(qp)) 2643 return PTR_ERR(qp); 2644 2645 for (qfe_slot = 0; qfe_slot < 4; qfe_slot++) 2646 if (!qp->happy_meals[qfe_slot]) 2647 break; 2648 2649 if (qfe_slot == 4) 2650 return -ENODEV; 2651 } 2652 2653 dev = devm_alloc_etherdev(&pdev->dev, sizeof(struct happy_meal)); 2654 if (!dev) 2655 return -ENOMEM; 2656 SET_NETDEV_DEV(dev, &pdev->dev); 2657 2658 hp = netdev_priv(dev); 2659 hp->dev = dev; 2660 hp->happy_dev = pdev; 2661 hp->dma_dev = &pdev->dev; 2662 2663 spin_lock_init(&hp->happy_lock); 2664 2665 if (qp != NULL) { 2666 hp->qfe_parent = qp; 2667 hp->qfe_ent = qfe_slot; 2668 qp->happy_meals[qfe_slot] = dev; 2669 } 2670 2671 err = -EINVAL; 2672 if ((pci_resource_flags(pdev, 0) & IORESOURCE_IO) != 0) { 2673 dev_err(&pdev->dev, 2674 "Cannot find proper PCI device base address.\n"); 2675 goto err_out_clear_quattro; 2676 } 2677 2678 hpreg_res = devm_request_mem_region(&pdev->dev, 2679 pci_resource_start(pdev, 0), 2680 pci_resource_len(pdev, 0), 2681 DRV_NAME); 2682 if (!hpreg_res) { 2683 err = -EBUSY; 2684 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting.\n"); 2685 goto err_out_clear_quattro; 2686 } 2687 2688 hpreg_base = pcim_iomap(pdev, 0, 0x8000); 2689 if (!hpreg_base) { 2690 err = -ENOMEM; 2691 dev_err(&pdev->dev, "Unable to remap card memory.\n"); 2692 goto err_out_clear_quattro; 2693 } 2694 2695 happy_meal_addr_init(hp, dp, qfe_slot); 2696 2697 /* Layout registers. */ 2698 hp->gregs = (hpreg_base + 0x0000UL); 2699 hp->etxregs = (hpreg_base + 0x2000UL); 2700 hp->erxregs = (hpreg_base + 0x4000UL); 2701 hp->bigmacregs = (hpreg_base + 0x6000UL); 2702 hp->tcvregs = (hpreg_base + 0x7000UL); 2703 2704 if (IS_ENABLED(CONFIG_SPARC)) 2705 hp->hm_revision = 0xc0 | (pdev->revision & 0x0f); 2706 else 2707 hp->hm_revision = 0x20; 2708 2709 if (qp != NULL) 2710 hp->happy_flags |= HFLAG_QUATTRO; 2711 2712 /* And of course, indicate this is PCI. */ 2713 hp->happy_flags |= HFLAG_PCI; 2714 2715 #ifdef CONFIG_SPARC 2716 /* Assume PCI happy meals can handle all burst sizes. */ 2717 hp->happy_bursts = DMA_BURSTBITS; 2718 #endif 2719 hp->irq = pdev->irq; 2720 2721 #ifdef CONFIG_SBUS 2722 /* Hook up PCI register/descriptor accessors. */ 2723 hp->read_desc32 = pci_hme_read_desc32; 2724 hp->write_txd = pci_hme_write_txd; 2725 hp->write_rxd = pci_hme_write_rxd; 2726 hp->read32 = pci_hme_read32; 2727 hp->write32 = pci_hme_write32; 2728 #endif 2729 2730 err = happy_meal_common_probe(hp, dp); 2731 if (err) 2732 goto err_out_clear_quattro; 2733 2734 pci_set_drvdata(pdev, hp); 2735 2736 if (!qfe_slot) { 2737 struct pci_dev *qpdev = qp->quattro_dev; 2738 2739 prom_name[0] = 0; 2740 if (!strncmp(dev->name, "eth", 3)) { 2741 int i = simple_strtoul(dev->name + 3, NULL, 10); 2742 sprintf(prom_name, "-%d", i + 3); 2743 } 2744 netdev_info(dev, 2745 "%s: Quattro HME (PCI/CheerIO) 10/100baseT Ethernet bridge %04x.%04x\n", 2746 prom_name, qpdev->vendor, qpdev->device); 2747 } 2748 2749 if (qfe_slot != -1) 2750 netdev_info(dev, 2751 "Quattro HME slot %d (PCI/CheerIO) 10/100baseT Ethernet %pM\n", 2752 qfe_slot, dev->dev_addr); 2753 else 2754 netdev_info(dev, 2755 "HAPPY MEAL (PCI/CheerIO) 10/100BaseT Ethernet %pM\n", 2756 dev->dev_addr); 2757 2758 return 0; 2759 2760 err_out_clear_quattro: 2761 if (qp != NULL) 2762 qp->happy_meals[qfe_slot] = NULL; 2763 return err; 2764 } 2765 2766 static const struct pci_device_id happymeal_pci_ids[] = { 2767 { PCI_DEVICE(PCI_VENDOR_ID_SUN, PCI_DEVICE_ID_SUN_HAPPYMEAL) }, 2768 { } /* Terminating entry */ 2769 }; 2770 2771 MODULE_DEVICE_TABLE(pci, happymeal_pci_ids); 2772 2773 static struct pci_driver hme_pci_driver = { 2774 .name = "hme", 2775 .id_table = happymeal_pci_ids, 2776 .probe = happy_meal_pci_probe, 2777 }; 2778 2779 static int __init happy_meal_pci_init(void) 2780 { 2781 return pci_register_driver(&hme_pci_driver); 2782 } 2783 2784 static void happy_meal_pci_exit(void) 2785 { 2786 pci_unregister_driver(&hme_pci_driver); 2787 2788 while (qfe_pci_list) { 2789 struct quattro *qfe = qfe_pci_list; 2790 struct quattro *next = qfe->next; 2791 2792 kfree(qfe); 2793 2794 qfe_pci_list = next; 2795 } 2796 } 2797 2798 #endif 2799 2800 #ifdef CONFIG_SBUS 2801 static const struct of_device_id hme_sbus_match[]; 2802 static int hme_sbus_probe(struct platform_device *op) 2803 { 2804 const struct of_device_id *match; 2805 struct device_node *dp = op->dev.of_node; 2806 const char *model = of_get_property(dp, "model", NULL); 2807 int is_qfe; 2808 2809 match = of_match_device(hme_sbus_match, &op->dev); 2810 if (!match) 2811 return -EINVAL; 2812 is_qfe = (match->data != NULL); 2813 2814 if (!is_qfe && model && !strcmp(model, "SUNW,sbus-qfe")) 2815 is_qfe = 1; 2816 2817 return happy_meal_sbus_probe_one(op, is_qfe); 2818 } 2819 2820 static const struct of_device_id hme_sbus_match[] = { 2821 { 2822 .name = "SUNW,hme", 2823 }, 2824 { 2825 .name = "SUNW,qfe", 2826 .data = (void *) 1, 2827 }, 2828 { 2829 .name = "qfe", 2830 .data = (void *) 1, 2831 }, 2832 {}, 2833 }; 2834 2835 MODULE_DEVICE_TABLE(of, hme_sbus_match); 2836 2837 static struct platform_driver hme_sbus_driver = { 2838 .driver = { 2839 .name = "hme", 2840 .of_match_table = hme_sbus_match, 2841 }, 2842 .probe = hme_sbus_probe, 2843 }; 2844 2845 static int __init happy_meal_sbus_init(void) 2846 { 2847 return platform_driver_register(&hme_sbus_driver); 2848 } 2849 2850 static void happy_meal_sbus_exit(void) 2851 { 2852 platform_driver_unregister(&hme_sbus_driver); 2853 2854 while (qfe_sbus_list) { 2855 struct quattro *qfe = qfe_sbus_list; 2856 struct quattro *next = qfe->next; 2857 2858 kfree(qfe); 2859 2860 qfe_sbus_list = next; 2861 } 2862 } 2863 #endif 2864 2865 static int __init happy_meal_probe(void) 2866 { 2867 int err = 0; 2868 2869 #ifdef CONFIG_SBUS 2870 err = happy_meal_sbus_init(); 2871 #endif 2872 #ifdef CONFIG_PCI 2873 if (!err) { 2874 err = happy_meal_pci_init(); 2875 #ifdef CONFIG_SBUS 2876 if (err) 2877 happy_meal_sbus_exit(); 2878 #endif 2879 } 2880 #endif 2881 2882 return err; 2883 } 2884 2885 2886 static void __exit happy_meal_exit(void) 2887 { 2888 #ifdef CONFIG_SBUS 2889 happy_meal_sbus_exit(); 2890 #endif 2891 #ifdef CONFIG_PCI 2892 happy_meal_pci_exit(); 2893 #endif 2894 } 2895 2896 module_init(happy_meal_probe); 2897 module_exit(happy_meal_exit); 2898