1e689cf4aSJeff Kirsher /* $Id: sungem.h,v 1.10.2.4 2002/03/11 08:54:48 davem Exp $ 2e689cf4aSJeff Kirsher * sungem.h: Definitions for Sun GEM ethernet driver. 3e689cf4aSJeff Kirsher * 4e689cf4aSJeff Kirsher * Copyright (C) 2000 David S. Miller (davem@redhat.com) 5e689cf4aSJeff Kirsher */ 6e689cf4aSJeff Kirsher 7e689cf4aSJeff Kirsher #ifndef _SUNGEM_H 8e689cf4aSJeff Kirsher #define _SUNGEM_H 9e689cf4aSJeff Kirsher 10e689cf4aSJeff Kirsher /* Global Registers */ 11e689cf4aSJeff Kirsher #define GREG_SEBSTATE 0x0000UL /* SEB State Register */ 12e689cf4aSJeff Kirsher #define GREG_CFG 0x0004UL /* Configuration Register */ 13e689cf4aSJeff Kirsher #define GREG_STAT 0x000CUL /* Status Register */ 14e689cf4aSJeff Kirsher #define GREG_IMASK 0x0010UL /* Interrupt Mask Register */ 15e689cf4aSJeff Kirsher #define GREG_IACK 0x0014UL /* Interrupt ACK Register */ 16e689cf4aSJeff Kirsher #define GREG_STAT2 0x001CUL /* Alias of GREG_STAT */ 17e689cf4aSJeff Kirsher #define GREG_PCIESTAT 0x1000UL /* PCI Error Status Register */ 18e689cf4aSJeff Kirsher #define GREG_PCIEMASK 0x1004UL /* PCI Error Mask Register */ 19e689cf4aSJeff Kirsher #define GREG_BIFCFG 0x1008UL /* BIF Configuration Register */ 20e689cf4aSJeff Kirsher #define GREG_BIFDIAG 0x100CUL /* BIF Diagnostics Register */ 21e689cf4aSJeff Kirsher #define GREG_SWRST 0x1010UL /* Software Reset Register */ 22e689cf4aSJeff Kirsher 23e689cf4aSJeff Kirsher /* Global SEB State Register */ 24e689cf4aSJeff Kirsher #define GREG_SEBSTATE_ARB 0x00000003 /* State of Arbiter */ 25e689cf4aSJeff Kirsher #define GREG_SEBSTATE_RXWON 0x00000004 /* RX won internal arbitration */ 26e689cf4aSJeff Kirsher 27e689cf4aSJeff Kirsher /* Global Configuration Register */ 28e689cf4aSJeff Kirsher #define GREG_CFG_IBURST 0x00000001 /* Infinite Burst */ 29e689cf4aSJeff Kirsher #define GREG_CFG_TXDMALIM 0x0000003e /* TX DMA grant limit */ 30e689cf4aSJeff Kirsher #define GREG_CFG_RXDMALIM 0x000007c0 /* RX DMA grant limit */ 31e689cf4aSJeff Kirsher #define GREG_CFG_RONPAULBIT 0x00000800 /* Use mem read multiple for PCI read 32e689cf4aSJeff Kirsher * after infinite burst (Apple) */ 33e689cf4aSJeff Kirsher #define GREG_CFG_ENBUG2FIX 0x00001000 /* Fix Rx hang after overflow */ 34e689cf4aSJeff Kirsher 35e689cf4aSJeff Kirsher /* Global Interrupt Status Register. 36e689cf4aSJeff Kirsher * 37e689cf4aSJeff Kirsher * Reading this register automatically clears bits 0 through 6. 38e689cf4aSJeff Kirsher * This auto-clearing does not occur when the alias at GREG_STAT2 39e689cf4aSJeff Kirsher * is read instead. The rest of the interrupt bits only clear when 40e689cf4aSJeff Kirsher * the secondary interrupt status register corresponding to that 41e689cf4aSJeff Kirsher * bit is read (ie. if GREG_STAT_PCS is set, it will be cleared by 42e689cf4aSJeff Kirsher * reading PCS_ISTAT). 43e689cf4aSJeff Kirsher */ 44e689cf4aSJeff Kirsher #define GREG_STAT_TXINTME 0x00000001 /* TX INTME frame transferred */ 45e689cf4aSJeff Kirsher #define GREG_STAT_TXALL 0x00000002 /* All TX frames transferred */ 46e689cf4aSJeff Kirsher #define GREG_STAT_TXDONE 0x00000004 /* One TX frame transferred */ 47e689cf4aSJeff Kirsher #define GREG_STAT_RXDONE 0x00000010 /* One RX frame arrived */ 48e689cf4aSJeff Kirsher #define GREG_STAT_RXNOBUF 0x00000020 /* No free RX buffers available */ 49e689cf4aSJeff Kirsher #define GREG_STAT_RXTAGERR 0x00000040 /* RX tag framing is corrupt */ 50e689cf4aSJeff Kirsher #define GREG_STAT_PCS 0x00002000 /* PCS signalled interrupt */ 51e689cf4aSJeff Kirsher #define GREG_STAT_TXMAC 0x00004000 /* TX MAC signalled interrupt */ 52e689cf4aSJeff Kirsher #define GREG_STAT_RXMAC 0x00008000 /* RX MAC signalled interrupt */ 53e689cf4aSJeff Kirsher #define GREG_STAT_MAC 0x00010000 /* MAC Control signalled irq */ 54e689cf4aSJeff Kirsher #define GREG_STAT_MIF 0x00020000 /* MIF signalled interrupt */ 55e689cf4aSJeff Kirsher #define GREG_STAT_PCIERR 0x00040000 /* PCI Error interrupt */ 56e689cf4aSJeff Kirsher #define GREG_STAT_TXNR 0xfff80000 /* == TXDMA_TXDONE reg val */ 57e689cf4aSJeff Kirsher #define GREG_STAT_TXNR_SHIFT 19 58e689cf4aSJeff Kirsher 59e689cf4aSJeff Kirsher #define GREG_STAT_ABNORMAL (GREG_STAT_RXNOBUF | GREG_STAT_RXTAGERR | \ 60e689cf4aSJeff Kirsher GREG_STAT_PCS | GREG_STAT_TXMAC | GREG_STAT_RXMAC | \ 61e689cf4aSJeff Kirsher GREG_STAT_MAC | GREG_STAT_MIF | GREG_STAT_PCIERR) 62e689cf4aSJeff Kirsher 63e689cf4aSJeff Kirsher #define GREG_STAT_NAPI (GREG_STAT_TXALL | GREG_STAT_TXINTME | \ 64e689cf4aSJeff Kirsher GREG_STAT_RXDONE | GREG_STAT_ABNORMAL) 65e689cf4aSJeff Kirsher 66e689cf4aSJeff Kirsher /* The layout of GREG_IMASK and GREG_IACK is identical to GREG_STAT. 67e689cf4aSJeff Kirsher * Bits set in GREG_IMASK will prevent that interrupt type from being 68e689cf4aSJeff Kirsher * signalled to the cpu. GREG_IACK can be used to clear specific top-level 69e689cf4aSJeff Kirsher * interrupt conditions in GREG_STAT, ie. it only works for bits 0 through 6. 70e689cf4aSJeff Kirsher * Setting the bit will clear that interrupt, clear bits will have no effect 71e689cf4aSJeff Kirsher * on GREG_STAT. 72e689cf4aSJeff Kirsher */ 73e689cf4aSJeff Kirsher 74e689cf4aSJeff Kirsher /* Global PCI Error Status Register */ 75e689cf4aSJeff Kirsher #define GREG_PCIESTAT_BADACK 0x00000001 /* No ACK64# during ABS64 cycle */ 76e689cf4aSJeff Kirsher #define GREG_PCIESTAT_DTRTO 0x00000002 /* Delayed transaction timeout */ 77e689cf4aSJeff Kirsher #define GREG_PCIESTAT_OTHER 0x00000004 /* Other PCI error, check cfg space */ 78e689cf4aSJeff Kirsher 79e689cf4aSJeff Kirsher /* The layout of the GREG_PCIEMASK is identical to that of GREG_PCIESTAT. 80e689cf4aSJeff Kirsher * Bits set in GREG_PCIEMASK will prevent that interrupt type from being 81e689cf4aSJeff Kirsher * signalled to the cpu. 82e689cf4aSJeff Kirsher */ 83e689cf4aSJeff Kirsher 84e689cf4aSJeff Kirsher /* Global BIF Configuration Register */ 85e689cf4aSJeff Kirsher #define GREG_BIFCFG_SLOWCLK 0x00000001 /* Set if PCI runs < 25Mhz */ 86e689cf4aSJeff Kirsher #define GREG_BIFCFG_B64DIS 0x00000002 /* Disable 64bit wide data cycle*/ 87e689cf4aSJeff Kirsher #define GREG_BIFCFG_M66EN 0x00000004 /* Set if on 66Mhz PCI segment */ 88e689cf4aSJeff Kirsher 89e689cf4aSJeff Kirsher /* Global BIF Diagnostics Register */ 90e689cf4aSJeff Kirsher #define GREG_BIFDIAG_BURSTSM 0x007f0000 /* PCI Burst state machine */ 91e689cf4aSJeff Kirsher #define GREG_BIFDIAG_BIFSM 0xff000000 /* BIF state machine */ 92e689cf4aSJeff Kirsher 93e689cf4aSJeff Kirsher /* Global Software Reset Register. 94e689cf4aSJeff Kirsher * 95e689cf4aSJeff Kirsher * This register is used to perform a global reset of the RX and TX portions 96e689cf4aSJeff Kirsher * of the GEM asic. Setting the RX or TX reset bit will start the reset. 97e689cf4aSJeff Kirsher * The driver _MUST_ poll these bits until they clear. One may not attempt 98e689cf4aSJeff Kirsher * to program any other part of GEM until the bits clear. 99e689cf4aSJeff Kirsher */ 100e689cf4aSJeff Kirsher #define GREG_SWRST_TXRST 0x00000001 /* TX Software Reset */ 101e689cf4aSJeff Kirsher #define GREG_SWRST_RXRST 0x00000002 /* RX Software Reset */ 102e689cf4aSJeff Kirsher #define GREG_SWRST_RSTOUT 0x00000004 /* Force RST# pin active */ 103e689cf4aSJeff Kirsher #define GREG_SWRST_CACHESIZE 0x00ff0000 /* RIO only: cache line size */ 104e689cf4aSJeff Kirsher #define GREG_SWRST_CACHE_SHIFT 16 105e689cf4aSJeff Kirsher 106e689cf4aSJeff Kirsher /* TX DMA Registers */ 107e689cf4aSJeff Kirsher #define TXDMA_KICK 0x2000UL /* TX Kick Register */ 108e689cf4aSJeff Kirsher #define TXDMA_CFG 0x2004UL /* TX Configuration Register */ 109e689cf4aSJeff Kirsher #define TXDMA_DBLOW 0x2008UL /* TX Desc. Base Low */ 110e689cf4aSJeff Kirsher #define TXDMA_DBHI 0x200CUL /* TX Desc. Base High */ 111e689cf4aSJeff Kirsher #define TXDMA_FWPTR 0x2014UL /* TX FIFO Write Pointer */ 112e689cf4aSJeff Kirsher #define TXDMA_FSWPTR 0x2018UL /* TX FIFO Shadow Write Pointer */ 113e689cf4aSJeff Kirsher #define TXDMA_FRPTR 0x201CUL /* TX FIFO Read Pointer */ 114e689cf4aSJeff Kirsher #define TXDMA_FSRPTR 0x2020UL /* TX FIFO Shadow Read Pointer */ 115e689cf4aSJeff Kirsher #define TXDMA_PCNT 0x2024UL /* TX FIFO Packet Counter */ 116e689cf4aSJeff Kirsher #define TXDMA_SMACHINE 0x2028UL /* TX State Machine Register */ 117e689cf4aSJeff Kirsher #define TXDMA_DPLOW 0x2030UL /* TX Data Pointer Low */ 118e689cf4aSJeff Kirsher #define TXDMA_DPHI 0x2034UL /* TX Data Pointer High */ 119e689cf4aSJeff Kirsher #define TXDMA_TXDONE 0x2100UL /* TX Completion Register */ 120e689cf4aSJeff Kirsher #define TXDMA_FADDR 0x2104UL /* TX FIFO Address */ 121e689cf4aSJeff Kirsher #define TXDMA_FTAG 0x2108UL /* TX FIFO Tag */ 122e689cf4aSJeff Kirsher #define TXDMA_DLOW 0x210CUL /* TX FIFO Data Low */ 123e689cf4aSJeff Kirsher #define TXDMA_DHIT1 0x2110UL /* TX FIFO Data HighT1 */ 124e689cf4aSJeff Kirsher #define TXDMA_DHIT0 0x2114UL /* TX FIFO Data HighT0 */ 125e689cf4aSJeff Kirsher #define TXDMA_FSZ 0x2118UL /* TX FIFO Size */ 126e689cf4aSJeff Kirsher 127e689cf4aSJeff Kirsher /* TX Kick Register. 128e689cf4aSJeff Kirsher * 129e689cf4aSJeff Kirsher * This 13-bit register is programmed by the driver to hold the descriptor 130e689cf4aSJeff Kirsher * entry index which follows the last valid transmit descriptor. 131e689cf4aSJeff Kirsher */ 132e689cf4aSJeff Kirsher 133e689cf4aSJeff Kirsher /* TX Completion Register. 134e689cf4aSJeff Kirsher * 135e689cf4aSJeff Kirsher * This 13-bit register is updated by GEM to hold to descriptor entry index 136e689cf4aSJeff Kirsher * which follows the last descriptor already processed by GEM. Note that 137e689cf4aSJeff Kirsher * this value is mirrored in GREG_STAT which eliminates the need to even 138e689cf4aSJeff Kirsher * access this register in the driver during interrupt processing. 139e689cf4aSJeff Kirsher */ 140e689cf4aSJeff Kirsher 141e689cf4aSJeff Kirsher /* TX Configuration Register. 142e689cf4aSJeff Kirsher * 143e689cf4aSJeff Kirsher * Note that TXDMA_CFG_FTHRESH, the TX FIFO Threshold, is an obsolete feature 144e689cf4aSJeff Kirsher * that was meant to be used with jumbo packets. It should be set to the 145e689cf4aSJeff Kirsher * maximum value of 0x4ff, else one risks getting TX MAC Underrun errors. 146e689cf4aSJeff Kirsher */ 147e689cf4aSJeff Kirsher #define TXDMA_CFG_ENABLE 0x00000001 /* Enable TX DMA channel */ 148e689cf4aSJeff Kirsher #define TXDMA_CFG_RINGSZ 0x0000001e /* TX descriptor ring size */ 149e689cf4aSJeff Kirsher #define TXDMA_CFG_RINGSZ_32 0x00000000 /* 32 TX descriptors */ 150e689cf4aSJeff Kirsher #define TXDMA_CFG_RINGSZ_64 0x00000002 /* 64 TX descriptors */ 151e689cf4aSJeff Kirsher #define TXDMA_CFG_RINGSZ_128 0x00000004 /* 128 TX descriptors */ 152e689cf4aSJeff Kirsher #define TXDMA_CFG_RINGSZ_256 0x00000006 /* 256 TX descriptors */ 153e689cf4aSJeff Kirsher #define TXDMA_CFG_RINGSZ_512 0x00000008 /* 512 TX descriptors */ 154e689cf4aSJeff Kirsher #define TXDMA_CFG_RINGSZ_1K 0x0000000a /* 1024 TX descriptors */ 155e689cf4aSJeff Kirsher #define TXDMA_CFG_RINGSZ_2K 0x0000000c /* 2048 TX descriptors */ 156e689cf4aSJeff Kirsher #define TXDMA_CFG_RINGSZ_4K 0x0000000e /* 4096 TX descriptors */ 157e689cf4aSJeff Kirsher #define TXDMA_CFG_RINGSZ_8K 0x00000010 /* 8192 TX descriptors */ 158e689cf4aSJeff Kirsher #define TXDMA_CFG_PIOSEL 0x00000020 /* Enable TX FIFO PIO from cpu */ 159e689cf4aSJeff Kirsher #define TXDMA_CFG_FTHRESH 0x001ffc00 /* TX FIFO Threshold, obsolete */ 160e689cf4aSJeff Kirsher #define TXDMA_CFG_PMODE 0x00200000 /* TXALL irq means TX FIFO empty*/ 161e689cf4aSJeff Kirsher 162e689cf4aSJeff Kirsher /* TX Descriptor Base Low/High. 163e689cf4aSJeff Kirsher * 164e689cf4aSJeff Kirsher * These two registers store the 53 most significant bits of the base address 165e689cf4aSJeff Kirsher * of the TX descriptor table. The 11 least significant bits are always 166e689cf4aSJeff Kirsher * zero. As a result, the TX descriptor table must be 2K aligned. 167e689cf4aSJeff Kirsher */ 168e689cf4aSJeff Kirsher 169e689cf4aSJeff Kirsher /* The rest of the TXDMA_* registers are for diagnostics and debug, I will document 170e689cf4aSJeff Kirsher * them later. -DaveM 171e689cf4aSJeff Kirsher */ 172e689cf4aSJeff Kirsher 173e689cf4aSJeff Kirsher /* WakeOnLan Registers */ 174e689cf4aSJeff Kirsher #define WOL_MATCH0 0x3000UL 175e689cf4aSJeff Kirsher #define WOL_MATCH1 0x3004UL 176e689cf4aSJeff Kirsher #define WOL_MATCH2 0x3008UL 177e689cf4aSJeff Kirsher #define WOL_MCOUNT 0x300CUL 178e689cf4aSJeff Kirsher #define WOL_WAKECSR 0x3010UL 179e689cf4aSJeff Kirsher 180e689cf4aSJeff Kirsher /* WOL Match count register 181e689cf4aSJeff Kirsher */ 182e689cf4aSJeff Kirsher #define WOL_MCOUNT_N 0x00000010 183e689cf4aSJeff Kirsher #define WOL_MCOUNT_M 0x00000000 /* 0 << 8 */ 184e689cf4aSJeff Kirsher 185e689cf4aSJeff Kirsher #define WOL_WAKECSR_ENABLE 0x00000001 186e689cf4aSJeff Kirsher #define WOL_WAKECSR_MII 0x00000002 187e689cf4aSJeff Kirsher #define WOL_WAKECSR_SEEN 0x00000004 188e689cf4aSJeff Kirsher #define WOL_WAKECSR_FILT_UCAST 0x00000008 189e689cf4aSJeff Kirsher #define WOL_WAKECSR_FILT_MCAST 0x00000010 190e689cf4aSJeff Kirsher #define WOL_WAKECSR_FILT_BCAST 0x00000020 191e689cf4aSJeff Kirsher #define WOL_WAKECSR_FILT_SEEN 0x00000040 192e689cf4aSJeff Kirsher 193e689cf4aSJeff Kirsher 194e689cf4aSJeff Kirsher /* Receive DMA Registers */ 195e689cf4aSJeff Kirsher #define RXDMA_CFG 0x4000UL /* RX Configuration Register */ 196e689cf4aSJeff Kirsher #define RXDMA_DBLOW 0x4004UL /* RX Descriptor Base Low */ 197e689cf4aSJeff Kirsher #define RXDMA_DBHI 0x4008UL /* RX Descriptor Base High */ 198e689cf4aSJeff Kirsher #define RXDMA_FWPTR 0x400CUL /* RX FIFO Write Pointer */ 199e689cf4aSJeff Kirsher #define RXDMA_FSWPTR 0x4010UL /* RX FIFO Shadow Write Pointer */ 200e689cf4aSJeff Kirsher #define RXDMA_FRPTR 0x4014UL /* RX FIFO Read Pointer */ 201e689cf4aSJeff Kirsher #define RXDMA_PCNT 0x4018UL /* RX FIFO Packet Counter */ 202e689cf4aSJeff Kirsher #define RXDMA_SMACHINE 0x401CUL /* RX State Machine Register */ 203e689cf4aSJeff Kirsher #define RXDMA_PTHRESH 0x4020UL /* Pause Thresholds */ 204e689cf4aSJeff Kirsher #define RXDMA_DPLOW 0x4024UL /* RX Data Pointer Low */ 205e689cf4aSJeff Kirsher #define RXDMA_DPHI 0x4028UL /* RX Data Pointer High */ 206e689cf4aSJeff Kirsher #define RXDMA_KICK 0x4100UL /* RX Kick Register */ 207e689cf4aSJeff Kirsher #define RXDMA_DONE 0x4104UL /* RX Completion Register */ 208e689cf4aSJeff Kirsher #define RXDMA_BLANK 0x4108UL /* RX Blanking Register */ 209e689cf4aSJeff Kirsher #define RXDMA_FADDR 0x410CUL /* RX FIFO Address */ 210e689cf4aSJeff Kirsher #define RXDMA_FTAG 0x4110UL /* RX FIFO Tag */ 211e689cf4aSJeff Kirsher #define RXDMA_DLOW 0x4114UL /* RX FIFO Data Low */ 212e689cf4aSJeff Kirsher #define RXDMA_DHIT1 0x4118UL /* RX FIFO Data HighT0 */ 213e689cf4aSJeff Kirsher #define RXDMA_DHIT0 0x411CUL /* RX FIFO Data HighT1 */ 214e689cf4aSJeff Kirsher #define RXDMA_FSZ 0x4120UL /* RX FIFO Size */ 215e689cf4aSJeff Kirsher 216e689cf4aSJeff Kirsher /* RX Configuration Register. */ 217e689cf4aSJeff Kirsher #define RXDMA_CFG_ENABLE 0x00000001 /* Enable RX DMA channel */ 218e689cf4aSJeff Kirsher #define RXDMA_CFG_RINGSZ 0x0000001e /* RX descriptor ring size */ 219e689cf4aSJeff Kirsher #define RXDMA_CFG_RINGSZ_32 0x00000000 /* - 32 entries */ 220e689cf4aSJeff Kirsher #define RXDMA_CFG_RINGSZ_64 0x00000002 /* - 64 entries */ 221e689cf4aSJeff Kirsher #define RXDMA_CFG_RINGSZ_128 0x00000004 /* - 128 entries */ 222e689cf4aSJeff Kirsher #define RXDMA_CFG_RINGSZ_256 0x00000006 /* - 256 entries */ 223e689cf4aSJeff Kirsher #define RXDMA_CFG_RINGSZ_512 0x00000008 /* - 512 entries */ 224e689cf4aSJeff Kirsher #define RXDMA_CFG_RINGSZ_1K 0x0000000a /* - 1024 entries */ 225e689cf4aSJeff Kirsher #define RXDMA_CFG_RINGSZ_2K 0x0000000c /* - 2048 entries */ 226e689cf4aSJeff Kirsher #define RXDMA_CFG_RINGSZ_4K 0x0000000e /* - 4096 entries */ 227e689cf4aSJeff Kirsher #define RXDMA_CFG_RINGSZ_8K 0x00000010 /* - 8192 entries */ 228e689cf4aSJeff Kirsher #define RXDMA_CFG_RINGSZ_BDISAB 0x00000020 /* Disable RX desc batching */ 229e689cf4aSJeff Kirsher #define RXDMA_CFG_FBOFF 0x00001c00 /* Offset of first data byte */ 230e689cf4aSJeff Kirsher #define RXDMA_CFG_CSUMOFF 0x000fe000 /* Skip bytes before csum calc */ 231e689cf4aSJeff Kirsher #define RXDMA_CFG_FTHRESH 0x07000000 /* RX FIFO dma start threshold */ 232e689cf4aSJeff Kirsher #define RXDMA_CFG_FTHRESH_64 0x00000000 /* - 64 bytes */ 233e689cf4aSJeff Kirsher #define RXDMA_CFG_FTHRESH_128 0x01000000 /* - 128 bytes */ 234e689cf4aSJeff Kirsher #define RXDMA_CFG_FTHRESH_256 0x02000000 /* - 256 bytes */ 235e689cf4aSJeff Kirsher #define RXDMA_CFG_FTHRESH_512 0x03000000 /* - 512 bytes */ 236e689cf4aSJeff Kirsher #define RXDMA_CFG_FTHRESH_1K 0x04000000 /* - 1024 bytes */ 237e689cf4aSJeff Kirsher #define RXDMA_CFG_FTHRESH_2K 0x05000000 /* - 2048 bytes */ 238e689cf4aSJeff Kirsher 239e689cf4aSJeff Kirsher /* RX Descriptor Base Low/High. 240e689cf4aSJeff Kirsher * 241e689cf4aSJeff Kirsher * These two registers store the 53 most significant bits of the base address 242e689cf4aSJeff Kirsher * of the RX descriptor table. The 11 least significant bits are always 243e689cf4aSJeff Kirsher * zero. As a result, the RX descriptor table must be 2K aligned. 244e689cf4aSJeff Kirsher */ 245e689cf4aSJeff Kirsher 246e689cf4aSJeff Kirsher /* RX PAUSE Thresholds. 247e689cf4aSJeff Kirsher * 248e689cf4aSJeff Kirsher * These values determine when XOFF and XON PAUSE frames are emitted by 249e689cf4aSJeff Kirsher * GEM. The thresholds measure RX FIFO occupancy in units of 64 bytes. 250e689cf4aSJeff Kirsher */ 251e689cf4aSJeff Kirsher #define RXDMA_PTHRESH_OFF 0x000001ff /* XOFF emitted w/FIFO > this */ 252e689cf4aSJeff Kirsher #define RXDMA_PTHRESH_ON 0x001ff000 /* XON emitted w/FIFO < this */ 253e689cf4aSJeff Kirsher 254e689cf4aSJeff Kirsher /* RX Kick Register. 255e689cf4aSJeff Kirsher * 256e689cf4aSJeff Kirsher * This 13-bit register is written by the host CPU and holds the last 257e689cf4aSJeff Kirsher * valid RX descriptor number plus one. This is, if 'N' is written to 258e689cf4aSJeff Kirsher * this register, it means that all RX descriptors up to but excluding 259e689cf4aSJeff Kirsher * 'N' are valid. 260e689cf4aSJeff Kirsher * 261e689cf4aSJeff Kirsher * The hardware requires that RX descriptors are posted in increments 262e689cf4aSJeff Kirsher * of 4. This means 'N' must be a multiple of four. For the best 263e689cf4aSJeff Kirsher * performance, the first new descriptor being posted should be (PCI) 264e689cf4aSJeff Kirsher * cache line aligned. 265e689cf4aSJeff Kirsher */ 266e689cf4aSJeff Kirsher 267e689cf4aSJeff Kirsher /* RX Completion Register. 268e689cf4aSJeff Kirsher * 269e689cf4aSJeff Kirsher * This 13-bit register is updated by GEM to indicate which RX descriptors 270e689cf4aSJeff Kirsher * have already been used for receive frames. All descriptors up to but 271e689cf4aSJeff Kirsher * excluding the value in this register are ready to be processed. GEM 272e689cf4aSJeff Kirsher * updates this register value after the RX FIFO empties completely into 273e689cf4aSJeff Kirsher * the RX descriptor's buffer, but before the RX_DONE bit is set in the 274e689cf4aSJeff Kirsher * interrupt status register. 275e689cf4aSJeff Kirsher */ 276e689cf4aSJeff Kirsher 277e689cf4aSJeff Kirsher /* RX Blanking Register. */ 278e689cf4aSJeff Kirsher #define RXDMA_BLANK_IPKTS 0x000001ff /* RX_DONE asserted after this 279e689cf4aSJeff Kirsher * many packets received since 280e689cf4aSJeff Kirsher * previous RX_DONE. 281e689cf4aSJeff Kirsher */ 282e689cf4aSJeff Kirsher #define RXDMA_BLANK_ITIME 0x000ff000 /* RX_DONE asserted after this 283e689cf4aSJeff Kirsher * many clocks (measured in 2048 284e689cf4aSJeff Kirsher * PCI clocks) were counted since 285e689cf4aSJeff Kirsher * the previous RX_DONE. 286e689cf4aSJeff Kirsher */ 287e689cf4aSJeff Kirsher 288e689cf4aSJeff Kirsher /* RX FIFO Size. 289e689cf4aSJeff Kirsher * 290e689cf4aSJeff Kirsher * This 11-bit read-only register indicates how large, in units of 64-bytes, 291e689cf4aSJeff Kirsher * the RX FIFO is. The driver uses this to properly configure the RX PAUSE 292e689cf4aSJeff Kirsher * thresholds. 293e689cf4aSJeff Kirsher */ 294e689cf4aSJeff Kirsher 295e689cf4aSJeff Kirsher /* The rest of the RXDMA_* registers are for diagnostics and debug, I will document 296e689cf4aSJeff Kirsher * them later. -DaveM 297e689cf4aSJeff Kirsher */ 298e689cf4aSJeff Kirsher 299e689cf4aSJeff Kirsher /* MAC Registers */ 300e689cf4aSJeff Kirsher #define MAC_TXRST 0x6000UL /* TX MAC Software Reset Command*/ 301e689cf4aSJeff Kirsher #define MAC_RXRST 0x6004UL /* RX MAC Software Reset Command*/ 302e689cf4aSJeff Kirsher #define MAC_SNDPAUSE 0x6008UL /* Send Pause Command Register */ 303e689cf4aSJeff Kirsher #define MAC_TXSTAT 0x6010UL /* TX MAC Status Register */ 304e689cf4aSJeff Kirsher #define MAC_RXSTAT 0x6014UL /* RX MAC Status Register */ 305e689cf4aSJeff Kirsher #define MAC_CSTAT 0x6018UL /* MAC Control Status Register */ 306e689cf4aSJeff Kirsher #define MAC_TXMASK 0x6020UL /* TX MAC Mask Register */ 307e689cf4aSJeff Kirsher #define MAC_RXMASK 0x6024UL /* RX MAC Mask Register */ 308e689cf4aSJeff Kirsher #define MAC_MCMASK 0x6028UL /* MAC Control Mask Register */ 309e689cf4aSJeff Kirsher #define MAC_TXCFG 0x6030UL /* TX MAC Configuration Register*/ 310e689cf4aSJeff Kirsher #define MAC_RXCFG 0x6034UL /* RX MAC Configuration Register*/ 311e689cf4aSJeff Kirsher #define MAC_MCCFG 0x6038UL /* MAC Control Config Register */ 312e689cf4aSJeff Kirsher #define MAC_XIFCFG 0x603CUL /* XIF Configuration Register */ 313e689cf4aSJeff Kirsher #define MAC_IPG0 0x6040UL /* InterPacketGap0 Register */ 314e689cf4aSJeff Kirsher #define MAC_IPG1 0x6044UL /* InterPacketGap1 Register */ 315e689cf4aSJeff Kirsher #define MAC_IPG2 0x6048UL /* InterPacketGap2 Register */ 316e689cf4aSJeff Kirsher #define MAC_STIME 0x604CUL /* SlotTime Register */ 317e689cf4aSJeff Kirsher #define MAC_MINFSZ 0x6050UL /* MinFrameSize Register */ 318e689cf4aSJeff Kirsher #define MAC_MAXFSZ 0x6054UL /* MaxFrameSize Register */ 319e689cf4aSJeff Kirsher #define MAC_PASIZE 0x6058UL /* PA Size Register */ 320e689cf4aSJeff Kirsher #define MAC_JAMSIZE 0x605CUL /* JamSize Register */ 321e689cf4aSJeff Kirsher #define MAC_ATTLIM 0x6060UL /* Attempt Limit Register */ 322e689cf4aSJeff Kirsher #define MAC_MCTYPE 0x6064UL /* MAC Control Type Register */ 323e689cf4aSJeff Kirsher #define MAC_ADDR0 0x6080UL /* MAC Address 0 Register */ 324e689cf4aSJeff Kirsher #define MAC_ADDR1 0x6084UL /* MAC Address 1 Register */ 325e689cf4aSJeff Kirsher #define MAC_ADDR2 0x6088UL /* MAC Address 2 Register */ 326e689cf4aSJeff Kirsher #define MAC_ADDR3 0x608CUL /* MAC Address 3 Register */ 327e689cf4aSJeff Kirsher #define MAC_ADDR4 0x6090UL /* MAC Address 4 Register */ 328e689cf4aSJeff Kirsher #define MAC_ADDR5 0x6094UL /* MAC Address 5 Register */ 329e689cf4aSJeff Kirsher #define MAC_ADDR6 0x6098UL /* MAC Address 6 Register */ 330e689cf4aSJeff Kirsher #define MAC_ADDR7 0x609CUL /* MAC Address 7 Register */ 331e689cf4aSJeff Kirsher #define MAC_ADDR8 0x60A0UL /* MAC Address 8 Register */ 332e689cf4aSJeff Kirsher #define MAC_AFILT0 0x60A4UL /* Address Filter 0 Register */ 333e689cf4aSJeff Kirsher #define MAC_AFILT1 0x60A8UL /* Address Filter 1 Register */ 334e689cf4aSJeff Kirsher #define MAC_AFILT2 0x60ACUL /* Address Filter 2 Register */ 335e689cf4aSJeff Kirsher #define MAC_AF21MSK 0x60B0UL /* Address Filter 2&1 Mask Reg */ 336e689cf4aSJeff Kirsher #define MAC_AF0MSK 0x60B4UL /* Address Filter 0 Mask Reg */ 337e689cf4aSJeff Kirsher #define MAC_HASH0 0x60C0UL /* Hash Table 0 Register */ 338e689cf4aSJeff Kirsher #define MAC_HASH1 0x60C4UL /* Hash Table 1 Register */ 339e689cf4aSJeff Kirsher #define MAC_HASH2 0x60C8UL /* Hash Table 2 Register */ 340e689cf4aSJeff Kirsher #define MAC_HASH3 0x60CCUL /* Hash Table 3 Register */ 341e689cf4aSJeff Kirsher #define MAC_HASH4 0x60D0UL /* Hash Table 4 Register */ 342e689cf4aSJeff Kirsher #define MAC_HASH5 0x60D4UL /* Hash Table 5 Register */ 343e689cf4aSJeff Kirsher #define MAC_HASH6 0x60D8UL /* Hash Table 6 Register */ 344e689cf4aSJeff Kirsher #define MAC_HASH7 0x60DCUL /* Hash Table 7 Register */ 345e689cf4aSJeff Kirsher #define MAC_HASH8 0x60E0UL /* Hash Table 8 Register */ 346e689cf4aSJeff Kirsher #define MAC_HASH9 0x60E4UL /* Hash Table 9 Register */ 347e689cf4aSJeff Kirsher #define MAC_HASH10 0x60E8UL /* Hash Table 10 Register */ 348e689cf4aSJeff Kirsher #define MAC_HASH11 0x60ECUL /* Hash Table 11 Register */ 349e689cf4aSJeff Kirsher #define MAC_HASH12 0x60F0UL /* Hash Table 12 Register */ 350e689cf4aSJeff Kirsher #define MAC_HASH13 0x60F4UL /* Hash Table 13 Register */ 351e689cf4aSJeff Kirsher #define MAC_HASH14 0x60F8UL /* Hash Table 14 Register */ 352e689cf4aSJeff Kirsher #define MAC_HASH15 0x60FCUL /* Hash Table 15 Register */ 353e689cf4aSJeff Kirsher #define MAC_NCOLL 0x6100UL /* Normal Collision Counter */ 354e689cf4aSJeff Kirsher #define MAC_FASUCC 0x6104UL /* First Attmpt. Succ Coll Ctr. */ 355e689cf4aSJeff Kirsher #define MAC_ECOLL 0x6108UL /* Excessive Collision Counter */ 356e689cf4aSJeff Kirsher #define MAC_LCOLL 0x610CUL /* Late Collision Counter */ 357e689cf4aSJeff Kirsher #define MAC_DTIMER 0x6110UL /* Defer Timer */ 358e689cf4aSJeff Kirsher #define MAC_PATMPS 0x6114UL /* Peak Attempts Register */ 359e689cf4aSJeff Kirsher #define MAC_RFCTR 0x6118UL /* Receive Frame Counter */ 360e689cf4aSJeff Kirsher #define MAC_LERR 0x611CUL /* Length Error Counter */ 361e689cf4aSJeff Kirsher #define MAC_AERR 0x6120UL /* Alignment Error Counter */ 362e689cf4aSJeff Kirsher #define MAC_FCSERR 0x6124UL /* FCS Error Counter */ 363e689cf4aSJeff Kirsher #define MAC_RXCVERR 0x6128UL /* RX code Violation Error Ctr */ 364e689cf4aSJeff Kirsher #define MAC_RANDSEED 0x6130UL /* Random Number Seed Register */ 365e689cf4aSJeff Kirsher #define MAC_SMACHINE 0x6134UL /* State Machine Register */ 366e689cf4aSJeff Kirsher 367e689cf4aSJeff Kirsher /* TX MAC Software Reset Command. */ 368e689cf4aSJeff Kirsher #define MAC_TXRST_CMD 0x00000001 /* Start sw reset, self-clears */ 369e689cf4aSJeff Kirsher 370e689cf4aSJeff Kirsher /* RX MAC Software Reset Command. */ 371e689cf4aSJeff Kirsher #define MAC_RXRST_CMD 0x00000001 /* Start sw reset, self-clears */ 372e689cf4aSJeff Kirsher 373e689cf4aSJeff Kirsher /* Send Pause Command. */ 374e689cf4aSJeff Kirsher #define MAC_SNDPAUSE_TS 0x0000ffff /* The pause_time operand used in 375e689cf4aSJeff Kirsher * Send_Pause and flow-control 376e689cf4aSJeff Kirsher * handshakes. 377e689cf4aSJeff Kirsher */ 378e689cf4aSJeff Kirsher #define MAC_SNDPAUSE_SP 0x00010000 /* Setting this bit instructs the MAC 379e689cf4aSJeff Kirsher * to send a Pause Flow Control 380e689cf4aSJeff Kirsher * frame onto the network. 381e689cf4aSJeff Kirsher */ 382e689cf4aSJeff Kirsher 383e689cf4aSJeff Kirsher /* TX MAC Status Register. */ 384e689cf4aSJeff Kirsher #define MAC_TXSTAT_XMIT 0x00000001 /* Frame Transmitted */ 385e689cf4aSJeff Kirsher #define MAC_TXSTAT_URUN 0x00000002 /* TX Underrun */ 386e689cf4aSJeff Kirsher #define MAC_TXSTAT_MPE 0x00000004 /* Max Packet Size Error */ 387e689cf4aSJeff Kirsher #define MAC_TXSTAT_NCE 0x00000008 /* Normal Collision Cntr Expire */ 388e689cf4aSJeff Kirsher #define MAC_TXSTAT_ECE 0x00000010 /* Excess Collision Cntr Expire */ 389e689cf4aSJeff Kirsher #define MAC_TXSTAT_LCE 0x00000020 /* Late Collision Cntr Expire */ 390e689cf4aSJeff Kirsher #define MAC_TXSTAT_FCE 0x00000040 /* First Collision Cntr Expire */ 391e689cf4aSJeff Kirsher #define MAC_TXSTAT_DTE 0x00000080 /* Defer Timer Expire */ 392e689cf4aSJeff Kirsher #define MAC_TXSTAT_PCE 0x00000100 /* Peak Attempts Cntr Expire */ 393e689cf4aSJeff Kirsher 394e689cf4aSJeff Kirsher /* RX MAC Status Register. */ 395e689cf4aSJeff Kirsher #define MAC_RXSTAT_RCV 0x00000001 /* Frame Received */ 396e689cf4aSJeff Kirsher #define MAC_RXSTAT_OFLW 0x00000002 /* Receive Overflow */ 397e689cf4aSJeff Kirsher #define MAC_RXSTAT_FCE 0x00000004 /* Frame Cntr Expire */ 398e689cf4aSJeff Kirsher #define MAC_RXSTAT_ACE 0x00000008 /* Align Error Cntr Expire */ 399e689cf4aSJeff Kirsher #define MAC_RXSTAT_CCE 0x00000010 /* CRC Error Cntr Expire */ 400e689cf4aSJeff Kirsher #define MAC_RXSTAT_LCE 0x00000020 /* Length Error Cntr Expire */ 401e689cf4aSJeff Kirsher #define MAC_RXSTAT_VCE 0x00000040 /* Code Violation Cntr Expire */ 402e689cf4aSJeff Kirsher 403e689cf4aSJeff Kirsher /* MAC Control Status Register. */ 404e689cf4aSJeff Kirsher #define MAC_CSTAT_PRCV 0x00000001 /* Pause Received */ 405e689cf4aSJeff Kirsher #define MAC_CSTAT_PS 0x00000002 /* Paused State */ 406e689cf4aSJeff Kirsher #define MAC_CSTAT_NPS 0x00000004 /* Not Paused State */ 407e689cf4aSJeff Kirsher #define MAC_CSTAT_PTR 0xffff0000 /* Pause Time Received */ 408e689cf4aSJeff Kirsher 409e689cf4aSJeff Kirsher /* The layout of the MAC_{TX,RX,C}MASK registers is identical to that 410e689cf4aSJeff Kirsher * of MAC_{TX,RX,C}STAT. Bits set in MAC_{TX,RX,C}MASK will prevent 411e689cf4aSJeff Kirsher * that interrupt type from being signalled to front end of GEM. For 412e689cf4aSJeff Kirsher * the interrupt to actually get sent to the cpu, it is necessary to 413e689cf4aSJeff Kirsher * properly set the appropriate GREG_IMASK_{TX,RX,}MAC bits as well. 414e689cf4aSJeff Kirsher */ 415e689cf4aSJeff Kirsher 416e689cf4aSJeff Kirsher /* TX MAC Configuration Register. 417e689cf4aSJeff Kirsher * 418e689cf4aSJeff Kirsher * NOTE: The TX MAC Enable bit must be cleared and polled until 419e689cf4aSJeff Kirsher * zero before any other bits in this register are changed. 420e689cf4aSJeff Kirsher * 421e689cf4aSJeff Kirsher * Also, enabling the Carrier Extension feature of GEM is 422e689cf4aSJeff Kirsher * a 3 step process 1) Set TX Carrier Extension 2) Set 423e689cf4aSJeff Kirsher * RX Carrier Extension 3) Set Slot Time to 0x200. This 424e689cf4aSJeff Kirsher * mode must be enabled when in half-duplex at 1Gbps, else 425e689cf4aSJeff Kirsher * it must be disabled. 426e689cf4aSJeff Kirsher */ 427e689cf4aSJeff Kirsher #define MAC_TXCFG_ENAB 0x00000001 /* TX MAC Enable */ 428e689cf4aSJeff Kirsher #define MAC_TXCFG_ICS 0x00000002 /* Ignore Carrier Sense */ 429e689cf4aSJeff Kirsher #define MAC_TXCFG_ICOLL 0x00000004 /* Ignore Collisions */ 430e689cf4aSJeff Kirsher #define MAC_TXCFG_EIPG0 0x00000008 /* Enable IPG0 */ 431e689cf4aSJeff Kirsher #define MAC_TXCFG_NGU 0x00000010 /* Never Give Up */ 432e689cf4aSJeff Kirsher #define MAC_TXCFG_NGUL 0x00000020 /* Never Give Up Limit */ 433e689cf4aSJeff Kirsher #define MAC_TXCFG_NBO 0x00000040 /* No Backoff */ 434e689cf4aSJeff Kirsher #define MAC_TXCFG_SD 0x00000080 /* Slow Down */ 435e689cf4aSJeff Kirsher #define MAC_TXCFG_NFCS 0x00000100 /* No FCS */ 436e689cf4aSJeff Kirsher #define MAC_TXCFG_TCE 0x00000200 /* TX Carrier Extension */ 437e689cf4aSJeff Kirsher 438e689cf4aSJeff Kirsher /* RX MAC Configuration Register. 439e689cf4aSJeff Kirsher * 440e689cf4aSJeff Kirsher * NOTE: The RX MAC Enable bit must be cleared and polled until 441e689cf4aSJeff Kirsher * zero before any other bits in this register are changed. 442e689cf4aSJeff Kirsher * 443e689cf4aSJeff Kirsher * Similar rules apply to the Hash Filter Enable bit when 444e689cf4aSJeff Kirsher * programming the hash table registers, and the Address Filter 445e689cf4aSJeff Kirsher * Enable bit when programming the address filter registers. 446e689cf4aSJeff Kirsher */ 447e689cf4aSJeff Kirsher #define MAC_RXCFG_ENAB 0x00000001 /* RX MAC Enable */ 448e689cf4aSJeff Kirsher #define MAC_RXCFG_SPAD 0x00000002 /* Strip Pad */ 449e689cf4aSJeff Kirsher #define MAC_RXCFG_SFCS 0x00000004 /* Strip FCS */ 450e689cf4aSJeff Kirsher #define MAC_RXCFG_PROM 0x00000008 /* Promiscuous Mode */ 451e689cf4aSJeff Kirsher #define MAC_RXCFG_PGRP 0x00000010 /* Promiscuous Group */ 452e689cf4aSJeff Kirsher #define MAC_RXCFG_HFE 0x00000020 /* Hash Filter Enable */ 453e689cf4aSJeff Kirsher #define MAC_RXCFG_AFE 0x00000040 /* Address Filter Enable */ 454e689cf4aSJeff Kirsher #define MAC_RXCFG_DDE 0x00000080 /* Disable Discard on Error */ 455e689cf4aSJeff Kirsher #define MAC_RXCFG_RCE 0x00000100 /* RX Carrier Extension */ 456e689cf4aSJeff Kirsher 457e689cf4aSJeff Kirsher /* MAC Control Config Register. */ 458e689cf4aSJeff Kirsher #define MAC_MCCFG_SPE 0x00000001 /* Send Pause Enable */ 459e689cf4aSJeff Kirsher #define MAC_MCCFG_RPE 0x00000002 /* Receive Pause Enable */ 460e689cf4aSJeff Kirsher #define MAC_MCCFG_PMC 0x00000004 /* Pass MAC Control */ 461e689cf4aSJeff Kirsher 462e689cf4aSJeff Kirsher /* XIF Configuration Register. 463e689cf4aSJeff Kirsher * 464e689cf4aSJeff Kirsher * NOTE: When leaving or entering loopback mode, a global hardware 465e689cf4aSJeff Kirsher * init of GEM should be performed. 466e689cf4aSJeff Kirsher */ 467e689cf4aSJeff Kirsher #define MAC_XIFCFG_OE 0x00000001 /* MII TX Output Driver Enable */ 468e689cf4aSJeff Kirsher #define MAC_XIFCFG_LBCK 0x00000002 /* Loopback TX to RX */ 469e689cf4aSJeff Kirsher #define MAC_XIFCFG_DISE 0x00000004 /* Disable RX path during TX */ 470e689cf4aSJeff Kirsher #define MAC_XIFCFG_GMII 0x00000008 /* Use GMII clocks + datapath */ 471e689cf4aSJeff Kirsher #define MAC_XIFCFG_MBOE 0x00000010 /* Controls MII_BUF_EN pin */ 472e689cf4aSJeff Kirsher #define MAC_XIFCFG_LLED 0x00000020 /* Force LINKLED# active (low) */ 473e689cf4aSJeff Kirsher #define MAC_XIFCFG_FLED 0x00000040 /* Force FDPLXLED# active (low) */ 474e689cf4aSJeff Kirsher 475e689cf4aSJeff Kirsher /* InterPacketGap0 Register. This 8-bit value is used as an extension 476e689cf4aSJeff Kirsher * to the InterPacketGap1 Register. Specifically it contributes to the 477e689cf4aSJeff Kirsher * timing of the RX-to-TX IPG. This value is ignored and presumed to 478e689cf4aSJeff Kirsher * be zero for TX-to-TX IPG calculations and/or when the Enable IPG0 bit 479e689cf4aSJeff Kirsher * is cleared in the TX MAC Configuration Register. 480e689cf4aSJeff Kirsher * 481e689cf4aSJeff Kirsher * This value in this register in terms of media byte time. 482e689cf4aSJeff Kirsher * 483e689cf4aSJeff Kirsher * Recommended value: 0x00 484e689cf4aSJeff Kirsher */ 485e689cf4aSJeff Kirsher 486e689cf4aSJeff Kirsher /* InterPacketGap1 Register. This 8-bit value defines the first 2/3 487e689cf4aSJeff Kirsher * portion of the Inter Packet Gap. 488e689cf4aSJeff Kirsher * 489e689cf4aSJeff Kirsher * This value in this register in terms of media byte time. 490e689cf4aSJeff Kirsher * 491e689cf4aSJeff Kirsher * Recommended value: 0x08 492e689cf4aSJeff Kirsher */ 493e689cf4aSJeff Kirsher 494e689cf4aSJeff Kirsher /* InterPacketGap2 Register. This 8-bit value defines the second 1/3 495e689cf4aSJeff Kirsher * portion of the Inter Packet Gap. 496e689cf4aSJeff Kirsher * 497e689cf4aSJeff Kirsher * This value in this register in terms of media byte time. 498e689cf4aSJeff Kirsher * 499e689cf4aSJeff Kirsher * Recommended value: 0x04 500e689cf4aSJeff Kirsher */ 501e689cf4aSJeff Kirsher 502e689cf4aSJeff Kirsher /* Slot Time Register. This 10-bit value specifies the slot time 503e689cf4aSJeff Kirsher * parameter in units of media byte time. It determines the physical 504e689cf4aSJeff Kirsher * span of the network. 505e689cf4aSJeff Kirsher * 506e689cf4aSJeff Kirsher * Recommended value: 0x40 507e689cf4aSJeff Kirsher */ 508e689cf4aSJeff Kirsher 509e689cf4aSJeff Kirsher /* Minimum Frame Size Register. This 10-bit register specifies the 510e689cf4aSJeff Kirsher * smallest sized frame the TXMAC will send onto the medium, and the 511e689cf4aSJeff Kirsher * RXMAC will receive from the medium. 512e689cf4aSJeff Kirsher * 513e689cf4aSJeff Kirsher * Recommended value: 0x40 514e689cf4aSJeff Kirsher */ 515e689cf4aSJeff Kirsher 516e689cf4aSJeff Kirsher /* Maximum Frame and Burst Size Register. 517e689cf4aSJeff Kirsher * 518e689cf4aSJeff Kirsher * This register specifies two things. First it specifies the maximum 519e689cf4aSJeff Kirsher * sized frame the TXMAC will send and the RXMAC will recognize as 520e689cf4aSJeff Kirsher * valid. Second, it specifies the maximum run length of a burst of 521e689cf4aSJeff Kirsher * packets sent in half-duplex gigabit modes. 522e689cf4aSJeff Kirsher * 523e689cf4aSJeff Kirsher * Recommended value: 0x200005ee 524e689cf4aSJeff Kirsher */ 525e689cf4aSJeff Kirsher #define MAC_MAXFSZ_MFS 0x00007fff /* Max Frame Size */ 526e689cf4aSJeff Kirsher #define MAC_MAXFSZ_MBS 0x7fff0000 /* Max Burst Size */ 527e689cf4aSJeff Kirsher 528e689cf4aSJeff Kirsher /* PA Size Register. This 10-bit register specifies the number of preamble 529e689cf4aSJeff Kirsher * bytes which will be transmitted at the beginning of each frame. A 530e689cf4aSJeff Kirsher * value of two or greater should be programmed here. 531e689cf4aSJeff Kirsher * 532e689cf4aSJeff Kirsher * Recommended value: 0x07 533e689cf4aSJeff Kirsher */ 534e689cf4aSJeff Kirsher 535e689cf4aSJeff Kirsher /* Jam Size Register. This 4-bit register specifies the duration of 536e689cf4aSJeff Kirsher * the jam in units of media byte time. 537e689cf4aSJeff Kirsher * 538e689cf4aSJeff Kirsher * Recommended value: 0x04 539e689cf4aSJeff Kirsher */ 540e689cf4aSJeff Kirsher 541e689cf4aSJeff Kirsher /* Attempts Limit Register. This 8-bit register specifies the number 542e689cf4aSJeff Kirsher * of attempts that the TXMAC will make to transmit a frame, before it 543e689cf4aSJeff Kirsher * resets its Attempts Counter. After reaching the Attempts Limit the 544e689cf4aSJeff Kirsher * TXMAC may or may not drop the frame, as determined by the NGU 545e689cf4aSJeff Kirsher * (Never Give Up) and NGUL (Never Give Up Limit) bits in the TXMAC 546e689cf4aSJeff Kirsher * Configuration Register. 547e689cf4aSJeff Kirsher * 548e689cf4aSJeff Kirsher * Recommended value: 0x10 549e689cf4aSJeff Kirsher */ 550e689cf4aSJeff Kirsher 551e689cf4aSJeff Kirsher /* MAX Control Type Register. This 16-bit register specifies the 552e689cf4aSJeff Kirsher * "type" field of a MAC Control frame. The TXMAC uses this field to 553e689cf4aSJeff Kirsher * encapsulate the MAC Control frame for transmission, and the RXMAC 554e689cf4aSJeff Kirsher * uses it for decoding valid MAC Control frames received from the 555e689cf4aSJeff Kirsher * network. 556e689cf4aSJeff Kirsher * 557e689cf4aSJeff Kirsher * Recommended value: 0x8808 558e689cf4aSJeff Kirsher */ 559e689cf4aSJeff Kirsher 560e689cf4aSJeff Kirsher /* MAC Address Registers. Each of these registers specify the 561e689cf4aSJeff Kirsher * ethernet MAC of the interface, 16-bits at a time. Register 562e689cf4aSJeff Kirsher * 0 specifies bits [47:32], register 1 bits [31:16], and register 563e689cf4aSJeff Kirsher * 2 bits [15:0]. 564e689cf4aSJeff Kirsher * 565e689cf4aSJeff Kirsher * Registers 3 through and including 5 specify an alternate 566e689cf4aSJeff Kirsher * MAC address for the interface. 567e689cf4aSJeff Kirsher * 568e689cf4aSJeff Kirsher * Registers 6 through and including 8 specify the MAC Control 569e689cf4aSJeff Kirsher * Address, which must be the reserved multicast address for MAC 570e689cf4aSJeff Kirsher * Control frames. 571e689cf4aSJeff Kirsher * 572e689cf4aSJeff Kirsher * Example: To program primary station address a:b:c:d:e:f into 573e689cf4aSJeff Kirsher * the chip. 574e689cf4aSJeff Kirsher * MAC_Address_2 = (a << 8) | b 575e689cf4aSJeff Kirsher * MAC_Address_1 = (c << 8) | d 576e689cf4aSJeff Kirsher * MAC_Address_0 = (e << 8) | f 577e689cf4aSJeff Kirsher */ 578e689cf4aSJeff Kirsher 579e689cf4aSJeff Kirsher /* Address Filter Registers. Registers 0 through 2 specify bit 580e689cf4aSJeff Kirsher * fields [47:32] through [15:0], respectively, of the address 581e689cf4aSJeff Kirsher * filter. The Address Filter 2&1 Mask Register denotes the 8-bit 582e689cf4aSJeff Kirsher * nibble mask for Address Filter Registers 2 and 1. The Address 583e689cf4aSJeff Kirsher * Filter 0 Mask Register denotes the 16-bit mask for the Address 584e689cf4aSJeff Kirsher * Filter Register 0. 585e689cf4aSJeff Kirsher */ 586e689cf4aSJeff Kirsher 587e689cf4aSJeff Kirsher /* Hash Table Registers. Registers 0 through 15 specify bit fields 588e689cf4aSJeff Kirsher * [255:240] through [15:0], respectively, of the hash table. 589e689cf4aSJeff Kirsher */ 590e689cf4aSJeff Kirsher 591e689cf4aSJeff Kirsher /* Statistics Registers. All of these registers are 16-bits and 592e689cf4aSJeff Kirsher * track occurrences of a specific event. GEM can be configured 593e689cf4aSJeff Kirsher * to interrupt the host cpu when any of these counters overflow. 594e689cf4aSJeff Kirsher * They should all be explicitly initialized to zero when the interface 595e689cf4aSJeff Kirsher * is brought up. 596e689cf4aSJeff Kirsher */ 597e689cf4aSJeff Kirsher 598e689cf4aSJeff Kirsher /* Random Number Seed Register. This 10-bit value is used as the 599e689cf4aSJeff Kirsher * RNG seed inside GEM for the CSMA/CD backoff algorithm. It is 600e689cf4aSJeff Kirsher * recommended to program this register to the 10 LSB of the 601e689cf4aSJeff Kirsher * interfaces MAC address. 602e689cf4aSJeff Kirsher */ 603e689cf4aSJeff Kirsher 604e689cf4aSJeff Kirsher /* Pause Timer, read-only. This 16-bit timer is used to time the pause 605e689cf4aSJeff Kirsher * interval as indicated by a received pause flow control frame. 606e689cf4aSJeff Kirsher * A non-zero value in this timer indicates that the MAC is currently in 607e689cf4aSJeff Kirsher * the paused state. 608e689cf4aSJeff Kirsher */ 609e689cf4aSJeff Kirsher 610e689cf4aSJeff Kirsher /* MIF Registers */ 611e689cf4aSJeff Kirsher #define MIF_BBCLK 0x6200UL /* MIF Bit-Bang Clock */ 612e689cf4aSJeff Kirsher #define MIF_BBDATA 0x6204UL /* MIF Bit-Band Data */ 613e689cf4aSJeff Kirsher #define MIF_BBOENAB 0x6208UL /* MIF Bit-Bang Output Enable */ 614e689cf4aSJeff Kirsher #define MIF_FRAME 0x620CUL /* MIF Frame/Output Register */ 615e689cf4aSJeff Kirsher #define MIF_CFG 0x6210UL /* MIF Configuration Register */ 616e689cf4aSJeff Kirsher #define MIF_MASK 0x6214UL /* MIF Mask Register */ 617e689cf4aSJeff Kirsher #define MIF_STATUS 0x6218UL /* MIF Status Register */ 618e689cf4aSJeff Kirsher #define MIF_SMACHINE 0x621CUL /* MIF State Machine Register */ 619e689cf4aSJeff Kirsher 620e689cf4aSJeff Kirsher /* MIF Bit-Bang Clock. This 1-bit register is used to generate the 621e689cf4aSJeff Kirsher * MDC clock waveform on the MII Management Interface when the MIF is 622e689cf4aSJeff Kirsher * programmed in the "Bit-Bang" mode. Writing a '1' after a '0' into 623e689cf4aSJeff Kirsher * this register will create a rising edge on the MDC, while writing 624e689cf4aSJeff Kirsher * a '0' after a '1' will create a falling edge. For every bit that 625e689cf4aSJeff Kirsher * is transferred on the management interface, both edges have to be 626e689cf4aSJeff Kirsher * generated. 627e689cf4aSJeff Kirsher */ 628e689cf4aSJeff Kirsher 629e689cf4aSJeff Kirsher /* MIF Bit-Bang Data. This 1-bit register is used to generate the 630e689cf4aSJeff Kirsher * outgoing data (MDO) on the MII Management Interface when the MIF 631e689cf4aSJeff Kirsher * is programmed in the "Bit-Bang" mode. The daa will be steered to the 632e689cf4aSJeff Kirsher * appropriate MDIO based on the state of the PHY_Select bit in the MIF 633e689cf4aSJeff Kirsher * Configuration Register. 634e689cf4aSJeff Kirsher */ 635e689cf4aSJeff Kirsher 636e689cf4aSJeff Kirsher /* MIF Big-Band Output Enable. THis 1-bit register is used to enable 637e689cf4aSJeff Kirsher * ('1') or disable ('0') the I-directional driver on the MII when the 638e689cf4aSJeff Kirsher * MIF is programmed in the "Bit-Bang" mode. The MDIO should be enabled 639e689cf4aSJeff Kirsher * when data bits are transferred from the MIF to the transceiver, and it 640e689cf4aSJeff Kirsher * should be disabled when the interface is idle or when data bits are 641e689cf4aSJeff Kirsher * transferred from the transceiver to the MIF (data portion of a read 642e689cf4aSJeff Kirsher * instruction). Only one MDIO will be enabled at a given time, depending 643e689cf4aSJeff Kirsher * on the state of the PHY_Select bit in the MIF Configuration Register. 644e689cf4aSJeff Kirsher */ 645e689cf4aSJeff Kirsher 646e689cf4aSJeff Kirsher /* MIF Configuration Register. This 15-bit register controls the operation 647e689cf4aSJeff Kirsher * of the MIF. 648e689cf4aSJeff Kirsher */ 649e689cf4aSJeff Kirsher #define MIF_CFG_PSELECT 0x00000001 /* Xcvr slct: 0=mdio0 1=mdio1 */ 650e689cf4aSJeff Kirsher #define MIF_CFG_POLL 0x00000002 /* Enable polling mechanism */ 651e689cf4aSJeff Kirsher #define MIF_CFG_BBMODE 0x00000004 /* 1=bit-bang 0=frame mode */ 652e689cf4aSJeff Kirsher #define MIF_CFG_PRADDR 0x000000f8 /* Xcvr poll register address */ 653e689cf4aSJeff Kirsher #define MIF_CFG_MDI0 0x00000100 /* MDIO_0 present or read-bit */ 654e689cf4aSJeff Kirsher #define MIF_CFG_MDI1 0x00000200 /* MDIO_1 present or read-bit */ 655e689cf4aSJeff Kirsher #define MIF_CFG_PPADDR 0x00007c00 /* Xcvr poll PHY address */ 656e689cf4aSJeff Kirsher 657e689cf4aSJeff Kirsher /* MIF Frame/Output Register. This 32-bit register allows the host to 658e689cf4aSJeff Kirsher * communicate with a transceiver in frame mode (as opposed to big-bang 659e689cf4aSJeff Kirsher * mode). Writes by the host specify an instrution. After being issued 660e689cf4aSJeff Kirsher * the host must poll this register for completion. Also, after 661e689cf4aSJeff Kirsher * completion this register holds the data returned by the transceiver 662e689cf4aSJeff Kirsher * if applicable. 663e689cf4aSJeff Kirsher */ 664e689cf4aSJeff Kirsher #define MIF_FRAME_ST 0xc0000000 /* STart of frame */ 665e689cf4aSJeff Kirsher #define MIF_FRAME_OP 0x30000000 /* OPcode */ 666e689cf4aSJeff Kirsher #define MIF_FRAME_PHYAD 0x0f800000 /* PHY ADdress */ 667e689cf4aSJeff Kirsher #define MIF_FRAME_REGAD 0x007c0000 /* REGister ADdress */ 668e689cf4aSJeff Kirsher #define MIF_FRAME_TAMSB 0x00020000 /* Turn Around MSB */ 669e689cf4aSJeff Kirsher #define MIF_FRAME_TALSB 0x00010000 /* Turn Around LSB */ 670e689cf4aSJeff Kirsher #define MIF_FRAME_DATA 0x0000ffff /* Instruction Payload */ 671e689cf4aSJeff Kirsher 672e689cf4aSJeff Kirsher /* MIF Status Register. This register reports status when the MIF is 673e689cf4aSJeff Kirsher * operating in the poll mode. The poll status field is auto-clearing 674e689cf4aSJeff Kirsher * on read. 675e689cf4aSJeff Kirsher */ 676e689cf4aSJeff Kirsher #define MIF_STATUS_DATA 0xffff0000 /* Live image of XCVR reg */ 677e689cf4aSJeff Kirsher #define MIF_STATUS_STAT 0x0000ffff /* Which bits have changed */ 678e689cf4aSJeff Kirsher 679e689cf4aSJeff Kirsher /* MIF Mask Register. This 16-bit register is used when in poll mode 680e689cf4aSJeff Kirsher * to say which bits of the polled register will cause an interrupt 681e689cf4aSJeff Kirsher * when changed. 682e689cf4aSJeff Kirsher */ 683e689cf4aSJeff Kirsher 684e689cf4aSJeff Kirsher /* PCS/Serialink Registers */ 685e689cf4aSJeff Kirsher #define PCS_MIICTRL 0x9000UL /* PCS MII Control Register */ 686e689cf4aSJeff Kirsher #define PCS_MIISTAT 0x9004UL /* PCS MII Status Register */ 687e689cf4aSJeff Kirsher #define PCS_MIIADV 0x9008UL /* PCS MII Advertisement Reg */ 688e689cf4aSJeff Kirsher #define PCS_MIILP 0x900CUL /* PCS MII Link Partner Ability */ 689e689cf4aSJeff Kirsher #define PCS_CFG 0x9010UL /* PCS Configuration Register */ 690e689cf4aSJeff Kirsher #define PCS_SMACHINE 0x9014UL /* PCS State Machine Register */ 691e689cf4aSJeff Kirsher #define PCS_ISTAT 0x9018UL /* PCS Interrupt Status Reg */ 692e689cf4aSJeff Kirsher #define PCS_DMODE 0x9050UL /* Datapath Mode Register */ 693e689cf4aSJeff Kirsher #define PCS_SCTRL 0x9054UL /* Serialink Control Register */ 694e689cf4aSJeff Kirsher #define PCS_SOS 0x9058UL /* Shared Output Select Reg */ 695e689cf4aSJeff Kirsher #define PCS_SSTATE 0x905CUL /* Serialink State Register */ 696e689cf4aSJeff Kirsher 697e689cf4aSJeff Kirsher /* PCD MII Control Register. */ 698e689cf4aSJeff Kirsher #define PCS_MIICTRL_SPD 0x00000040 /* Read as one, writes ignored */ 699e689cf4aSJeff Kirsher #define PCS_MIICTRL_CT 0x00000080 /* Force COL signal active */ 700e689cf4aSJeff Kirsher #define PCS_MIICTRL_DM 0x00000100 /* Duplex mode, forced low */ 701e689cf4aSJeff Kirsher #define PCS_MIICTRL_RAN 0x00000200 /* Restart auto-neg, self clear */ 702e689cf4aSJeff Kirsher #define PCS_MIICTRL_ISO 0x00000400 /* Read as zero, writes ignored */ 703e689cf4aSJeff Kirsher #define PCS_MIICTRL_PD 0x00000800 /* Read as zero, writes ignored */ 704e689cf4aSJeff Kirsher #define PCS_MIICTRL_ANE 0x00001000 /* Auto-neg enable */ 705e689cf4aSJeff Kirsher #define PCS_MIICTRL_SS 0x00002000 /* Read as zero, writes ignored */ 706e689cf4aSJeff Kirsher #define PCS_MIICTRL_WB 0x00004000 /* Wrapback, loopback at 10-bit 707e689cf4aSJeff Kirsher * input side of Serialink 708e689cf4aSJeff Kirsher */ 709e689cf4aSJeff Kirsher #define PCS_MIICTRL_RST 0x00008000 /* Resets PCS, self clearing */ 710e689cf4aSJeff Kirsher 711e689cf4aSJeff Kirsher /* PCS MII Status Register. */ 712e689cf4aSJeff Kirsher #define PCS_MIISTAT_EC 0x00000001 /* Ext Capability: Read as zero */ 713e689cf4aSJeff Kirsher #define PCS_MIISTAT_JD 0x00000002 /* Jabber Detect: Read as zero */ 714e689cf4aSJeff Kirsher #define PCS_MIISTAT_LS 0x00000004 /* Link Status: 1=up 0=down */ 715e689cf4aSJeff Kirsher #define PCS_MIISTAT_ANA 0x00000008 /* Auto-neg Ability, always 1 */ 716e689cf4aSJeff Kirsher #define PCS_MIISTAT_RF 0x00000010 /* Remote Fault */ 717e689cf4aSJeff Kirsher #define PCS_MIISTAT_ANC 0x00000020 /* Auto-neg complete */ 718e689cf4aSJeff Kirsher #define PCS_MIISTAT_ES 0x00000100 /* Extended Status, always 1 */ 719e689cf4aSJeff Kirsher 720e689cf4aSJeff Kirsher /* PCS MII Advertisement Register. */ 721e689cf4aSJeff Kirsher #define PCS_MIIADV_FD 0x00000020 /* Advertise Full Duplex */ 722e689cf4aSJeff Kirsher #define PCS_MIIADV_HD 0x00000040 /* Advertise Half Duplex */ 723e689cf4aSJeff Kirsher #define PCS_MIIADV_SP 0x00000080 /* Advertise Symmetric Pause */ 724e689cf4aSJeff Kirsher #define PCS_MIIADV_AP 0x00000100 /* Advertise Asymmetric Pause */ 725e689cf4aSJeff Kirsher #define PCS_MIIADV_RF 0x00003000 /* Remote Fault */ 726e689cf4aSJeff Kirsher #define PCS_MIIADV_ACK 0x00004000 /* Read-only */ 727e689cf4aSJeff Kirsher #define PCS_MIIADV_NP 0x00008000 /* Next-page, forced low */ 728e689cf4aSJeff Kirsher 729e689cf4aSJeff Kirsher /* PCS MII Link Partner Ability Register. This register is equivalent 730e689cf4aSJeff Kirsher * to the Link Partnet Ability Register of the standard MII register set. 731e689cf4aSJeff Kirsher * It's layout corresponds to the PCS MII Advertisement Register. 732e689cf4aSJeff Kirsher */ 733e689cf4aSJeff Kirsher 734e689cf4aSJeff Kirsher /* PCS Configuration Register. */ 735e689cf4aSJeff Kirsher #define PCS_CFG_ENABLE 0x00000001 /* Must be zero while changing 736e689cf4aSJeff Kirsher * PCS MII advertisement reg. 737e689cf4aSJeff Kirsher */ 738e689cf4aSJeff Kirsher #define PCS_CFG_SDO 0x00000002 /* Signal detect override */ 739e689cf4aSJeff Kirsher #define PCS_CFG_SDL 0x00000004 /* Signal detect active low */ 740e689cf4aSJeff Kirsher #define PCS_CFG_JS 0x00000018 /* Jitter-study: 741e689cf4aSJeff Kirsher * 0 = normal operation 742e689cf4aSJeff Kirsher * 1 = high-frequency test pattern 743e689cf4aSJeff Kirsher * 2 = low-frequency test pattern 744e689cf4aSJeff Kirsher * 3 = reserved 745e689cf4aSJeff Kirsher */ 746e689cf4aSJeff Kirsher #define PCS_CFG_TO 0x00000020 /* 10ms auto-neg timer override */ 747e689cf4aSJeff Kirsher 748e689cf4aSJeff Kirsher /* PCS Interrupt Status Register. This register is self-clearing 749e689cf4aSJeff Kirsher * when read. 750e689cf4aSJeff Kirsher */ 751e689cf4aSJeff Kirsher #define PCS_ISTAT_LSC 0x00000004 /* Link Status Change */ 752e689cf4aSJeff Kirsher 753e689cf4aSJeff Kirsher /* Datapath Mode Register. */ 754e689cf4aSJeff Kirsher #define PCS_DMODE_SM 0x00000001 /* 1 = use internal Serialink */ 755e689cf4aSJeff Kirsher #define PCS_DMODE_ESM 0x00000002 /* External SERDES mode */ 756e689cf4aSJeff Kirsher #define PCS_DMODE_MGM 0x00000004 /* MII/GMII mode */ 757e689cf4aSJeff Kirsher #define PCS_DMODE_GMOE 0x00000008 /* GMII Output Enable */ 758e689cf4aSJeff Kirsher 759e689cf4aSJeff Kirsher /* Serialink Control Register. 760e689cf4aSJeff Kirsher * 761e689cf4aSJeff Kirsher * NOTE: When in SERDES mode, the loopback bit has inverse logic. 762e689cf4aSJeff Kirsher */ 763e689cf4aSJeff Kirsher #define PCS_SCTRL_LOOP 0x00000001 /* Loopback enable */ 764e689cf4aSJeff Kirsher #define PCS_SCTRL_ESCD 0x00000002 /* Enable sync char detection */ 765e689cf4aSJeff Kirsher #define PCS_SCTRL_LOCK 0x00000004 /* Lock to reference clock */ 766e689cf4aSJeff Kirsher #define PCS_SCTRL_EMP 0x00000018 /* Output driver emphasis */ 767e689cf4aSJeff Kirsher #define PCS_SCTRL_STEST 0x000001c0 /* Self test patterns */ 768e689cf4aSJeff Kirsher #define PCS_SCTRL_PDWN 0x00000200 /* Software power-down */ 769e689cf4aSJeff Kirsher #define PCS_SCTRL_RXZ 0x00000c00 /* PLL input to Serialink */ 770e689cf4aSJeff Kirsher #define PCS_SCTRL_RXP 0x00003000 /* PLL input to Serialink */ 771e689cf4aSJeff Kirsher #define PCS_SCTRL_TXZ 0x0000c000 /* PLL input to Serialink */ 772e689cf4aSJeff Kirsher #define PCS_SCTRL_TXP 0x00030000 /* PLL input to Serialink */ 773e689cf4aSJeff Kirsher 774e689cf4aSJeff Kirsher /* Shared Output Select Register. For test and debug, allows multiplexing 775e689cf4aSJeff Kirsher * test outputs into the PROM address pins. Set to zero for normal 776e689cf4aSJeff Kirsher * operation. 777e689cf4aSJeff Kirsher */ 778e689cf4aSJeff Kirsher #define PCS_SOS_PADDR 0x00000003 /* PROM Address */ 779e689cf4aSJeff Kirsher 780e689cf4aSJeff Kirsher /* PROM Image Space */ 781e689cf4aSJeff Kirsher #define PROM_START 0x100000UL /* Expansion ROM run time access*/ 782e689cf4aSJeff Kirsher #define PROM_SIZE 0x0fffffUL /* Size of ROM */ 783e689cf4aSJeff Kirsher #define PROM_END 0x200000UL /* End of ROM */ 784e689cf4aSJeff Kirsher 785e689cf4aSJeff Kirsher /* MII definitions missing from mii.h */ 786e689cf4aSJeff Kirsher 787e689cf4aSJeff Kirsher #define BMCR_SPD2 0x0040 /* Gigabit enable? (bcm5411) */ 788e689cf4aSJeff Kirsher #define LPA_PAUSE 0x0400 789e689cf4aSJeff Kirsher 790e689cf4aSJeff Kirsher /* More PHY registers (specific to Broadcom models) */ 791e689cf4aSJeff Kirsher 792e689cf4aSJeff Kirsher /* MII BCM5201 MULTIPHY interrupt register */ 793e689cf4aSJeff Kirsher #define MII_BCM5201_INTERRUPT 0x1A 794e689cf4aSJeff Kirsher #define MII_BCM5201_INTERRUPT_INTENABLE 0x4000 795e689cf4aSJeff Kirsher 796e689cf4aSJeff Kirsher #define MII_BCM5201_AUXMODE2 0x1B 797e689cf4aSJeff Kirsher #define MII_BCM5201_AUXMODE2_LOWPOWER 0x0008 798e689cf4aSJeff Kirsher 799e689cf4aSJeff Kirsher #define MII_BCM5201_MULTIPHY 0x1E 800e689cf4aSJeff Kirsher 801e689cf4aSJeff Kirsher /* MII BCM5201 MULTIPHY register bits */ 802e689cf4aSJeff Kirsher #define MII_BCM5201_MULTIPHY_SERIALMODE 0x0002 803e689cf4aSJeff Kirsher #define MII_BCM5201_MULTIPHY_SUPERISOLATE 0x0008 804e689cf4aSJeff Kirsher 805e689cf4aSJeff Kirsher /* MII BCM5400 1000-BASET Control register */ 806e689cf4aSJeff Kirsher #define MII_BCM5400_GB_CONTROL 0x09 807e689cf4aSJeff Kirsher #define MII_BCM5400_GB_CONTROL_FULLDUPLEXCAP 0x0200 808e689cf4aSJeff Kirsher 809e689cf4aSJeff Kirsher /* MII BCM5400 AUXCONTROL register */ 810e689cf4aSJeff Kirsher #define MII_BCM5400_AUXCONTROL 0x18 811e689cf4aSJeff Kirsher #define MII_BCM5400_AUXCONTROL_PWR10BASET 0x0004 812e689cf4aSJeff Kirsher 813e689cf4aSJeff Kirsher /* MII BCM5400 AUXSTATUS register */ 814e689cf4aSJeff Kirsher #define MII_BCM5400_AUXSTATUS 0x19 815e689cf4aSJeff Kirsher #define MII_BCM5400_AUXSTATUS_LINKMODE_MASK 0x0700 816e689cf4aSJeff Kirsher #define MII_BCM5400_AUXSTATUS_LINKMODE_SHIFT 8 817e689cf4aSJeff Kirsher 818e689cf4aSJeff Kirsher /* When it can, GEM internally caches 4 aligned TX descriptors 819e689cf4aSJeff Kirsher * at a time, so that it can use full cacheline DMA reads. 820e689cf4aSJeff Kirsher * 821e689cf4aSJeff Kirsher * Note that unlike HME, there is no ownership bit in the descriptor 822e689cf4aSJeff Kirsher * control word. The same functionality is obtained via the TX-Kick 823e689cf4aSJeff Kirsher * and TX-Complete registers. As a result, GEM need not write back 824e689cf4aSJeff Kirsher * updated values to the TX descriptor ring, it only performs reads. 825e689cf4aSJeff Kirsher * 826e689cf4aSJeff Kirsher * Since TX descriptors are never modified by GEM, the driver can 827e689cf4aSJeff Kirsher * use the buffer DMA address as a place to keep track of allocated 828e689cf4aSJeff Kirsher * DMA mappings for a transmitted packet. 829e689cf4aSJeff Kirsher */ 830e689cf4aSJeff Kirsher struct gem_txd { 831e689cf4aSJeff Kirsher __le64 control_word; 832e689cf4aSJeff Kirsher __le64 buffer; 833e689cf4aSJeff Kirsher }; 834e689cf4aSJeff Kirsher 835e689cf4aSJeff Kirsher #define TXDCTRL_BUFSZ 0x0000000000007fffULL /* Buffer Size */ 836e689cf4aSJeff Kirsher #define TXDCTRL_CSTART 0x00000000001f8000ULL /* CSUM Start Offset */ 837e689cf4aSJeff Kirsher #define TXDCTRL_COFF 0x000000001fe00000ULL /* CSUM Stuff Offset */ 838e689cf4aSJeff Kirsher #define TXDCTRL_CENAB 0x0000000020000000ULL /* CSUM Enable */ 839e689cf4aSJeff Kirsher #define TXDCTRL_EOF 0x0000000040000000ULL /* End of Frame */ 840e689cf4aSJeff Kirsher #define TXDCTRL_SOF 0x0000000080000000ULL /* Start of Frame */ 841e689cf4aSJeff Kirsher #define TXDCTRL_INTME 0x0000000100000000ULL /* "Interrupt Me" */ 842e689cf4aSJeff Kirsher #define TXDCTRL_NOCRC 0x0000000200000000ULL /* No CRC Present */ 843e689cf4aSJeff Kirsher 844e689cf4aSJeff Kirsher /* GEM requires that RX descriptors are provided four at a time, 845e689cf4aSJeff Kirsher * aligned. Also, the RX ring may not wrap around. This means that 846e689cf4aSJeff Kirsher * there will be at least 4 unused descriptor entries in the middle 847e689cf4aSJeff Kirsher * of the RX ring at all times. 848e689cf4aSJeff Kirsher * 849e689cf4aSJeff Kirsher * Similar to HME, GEM assumes that it can write garbage bytes before 850e689cf4aSJeff Kirsher * the beginning of the buffer and right after the end in order to DMA 851e689cf4aSJeff Kirsher * whole cachelines. 852e689cf4aSJeff Kirsher * 853e689cf4aSJeff Kirsher * Unlike for TX, GEM does update the status word in the RX descriptors 854e689cf4aSJeff Kirsher * when packets arrive. Therefore an ownership bit does exist in the 855e689cf4aSJeff Kirsher * RX descriptors. It is advisory, GEM clears it but does not check 856e689cf4aSJeff Kirsher * it in any way. So when buffers are posted to the RX ring (via the 857e689cf4aSJeff Kirsher * RX Kick register) by the driver it must make sure the buffers are 858e689cf4aSJeff Kirsher * truly ready and that the ownership bits are set properly. 859e689cf4aSJeff Kirsher * 860e689cf4aSJeff Kirsher * Even though GEM modifies the RX descriptors, it guarantees that the 861e689cf4aSJeff Kirsher * buffer DMA address field will stay the same when it performs these 862e689cf4aSJeff Kirsher * updates. Therefore it can be used to keep track of DMA mappings 863e689cf4aSJeff Kirsher * by the host driver just as in the TX descriptor case above. 864e689cf4aSJeff Kirsher */ 865e689cf4aSJeff Kirsher struct gem_rxd { 866e689cf4aSJeff Kirsher __le64 status_word; 867e689cf4aSJeff Kirsher __le64 buffer; 868e689cf4aSJeff Kirsher }; 869e689cf4aSJeff Kirsher 870e689cf4aSJeff Kirsher #define RXDCTRL_TCPCSUM 0x000000000000ffffULL /* TCP Pseudo-CSUM */ 871e689cf4aSJeff Kirsher #define RXDCTRL_BUFSZ 0x000000007fff0000ULL /* Buffer Size */ 872e689cf4aSJeff Kirsher #define RXDCTRL_OWN 0x0000000080000000ULL /* GEM owns this entry */ 873e689cf4aSJeff Kirsher #define RXDCTRL_HASHVAL 0x0ffff00000000000ULL /* Hash Value */ 874e689cf4aSJeff Kirsher #define RXDCTRL_HPASS 0x1000000000000000ULL /* Passed Hash Filter */ 875e689cf4aSJeff Kirsher #define RXDCTRL_ALTMAC 0x2000000000000000ULL /* Matched ALT MAC */ 876e689cf4aSJeff Kirsher #define RXDCTRL_BAD 0x4000000000000000ULL /* Frame has bad CRC */ 877e689cf4aSJeff Kirsher 878e689cf4aSJeff Kirsher #define RXDCTRL_FRESH(gp) \ 879e689cf4aSJeff Kirsher ((((RX_BUF_ALLOC_SIZE(gp) - RX_OFFSET) << 16) & RXDCTRL_BUFSZ) | \ 880e689cf4aSJeff Kirsher RXDCTRL_OWN) 881e689cf4aSJeff Kirsher 882e689cf4aSJeff Kirsher #define TX_RING_SIZE 128 883e689cf4aSJeff Kirsher #define RX_RING_SIZE 128 884e689cf4aSJeff Kirsher 885e689cf4aSJeff Kirsher #if TX_RING_SIZE == 32 886e689cf4aSJeff Kirsher #define TXDMA_CFG_BASE TXDMA_CFG_RINGSZ_32 887e689cf4aSJeff Kirsher #elif TX_RING_SIZE == 64 888e689cf4aSJeff Kirsher #define TXDMA_CFG_BASE TXDMA_CFG_RINGSZ_64 889e689cf4aSJeff Kirsher #elif TX_RING_SIZE == 128 890e689cf4aSJeff Kirsher #define TXDMA_CFG_BASE TXDMA_CFG_RINGSZ_128 891e689cf4aSJeff Kirsher #elif TX_RING_SIZE == 256 892e689cf4aSJeff Kirsher #define TXDMA_CFG_BASE TXDMA_CFG_RINGSZ_256 893e689cf4aSJeff Kirsher #elif TX_RING_SIZE == 512 894e689cf4aSJeff Kirsher #define TXDMA_CFG_BASE TXDMA_CFG_RINGSZ_512 895e689cf4aSJeff Kirsher #elif TX_RING_SIZE == 1024 896e689cf4aSJeff Kirsher #define TXDMA_CFG_BASE TXDMA_CFG_RINGSZ_1K 897e689cf4aSJeff Kirsher #elif TX_RING_SIZE == 2048 898e689cf4aSJeff Kirsher #define TXDMA_CFG_BASE TXDMA_CFG_RINGSZ_2K 899e689cf4aSJeff Kirsher #elif TX_RING_SIZE == 4096 900e689cf4aSJeff Kirsher #define TXDMA_CFG_BASE TXDMA_CFG_RINGSZ_4K 901e689cf4aSJeff Kirsher #elif TX_RING_SIZE == 8192 902e689cf4aSJeff Kirsher #define TXDMA_CFG_BASE TXDMA_CFG_RINGSZ_8K 903e689cf4aSJeff Kirsher #else 904e689cf4aSJeff Kirsher #error TX_RING_SIZE value is illegal... 905e689cf4aSJeff Kirsher #endif 906e689cf4aSJeff Kirsher 907e689cf4aSJeff Kirsher #if RX_RING_SIZE == 32 908e689cf4aSJeff Kirsher #define RXDMA_CFG_BASE RXDMA_CFG_RINGSZ_32 909e689cf4aSJeff Kirsher #elif RX_RING_SIZE == 64 910e689cf4aSJeff Kirsher #define RXDMA_CFG_BASE RXDMA_CFG_RINGSZ_64 911e689cf4aSJeff Kirsher #elif RX_RING_SIZE == 128 912e689cf4aSJeff Kirsher #define RXDMA_CFG_BASE RXDMA_CFG_RINGSZ_128 913e689cf4aSJeff Kirsher #elif RX_RING_SIZE == 256 914e689cf4aSJeff Kirsher #define RXDMA_CFG_BASE RXDMA_CFG_RINGSZ_256 915e689cf4aSJeff Kirsher #elif RX_RING_SIZE == 512 916e689cf4aSJeff Kirsher #define RXDMA_CFG_BASE RXDMA_CFG_RINGSZ_512 917e689cf4aSJeff Kirsher #elif RX_RING_SIZE == 1024 918e689cf4aSJeff Kirsher #define RXDMA_CFG_BASE RXDMA_CFG_RINGSZ_1K 919e689cf4aSJeff Kirsher #elif RX_RING_SIZE == 2048 920e689cf4aSJeff Kirsher #define RXDMA_CFG_BASE RXDMA_CFG_RINGSZ_2K 921e689cf4aSJeff Kirsher #elif RX_RING_SIZE == 4096 922e689cf4aSJeff Kirsher #define RXDMA_CFG_BASE RXDMA_CFG_RINGSZ_4K 923e689cf4aSJeff Kirsher #elif RX_RING_SIZE == 8192 924e689cf4aSJeff Kirsher #define RXDMA_CFG_BASE RXDMA_CFG_RINGSZ_8K 925e689cf4aSJeff Kirsher #else 926e689cf4aSJeff Kirsher #error RX_RING_SIZE is illegal... 927e689cf4aSJeff Kirsher #endif 928e689cf4aSJeff Kirsher 929e689cf4aSJeff Kirsher #define NEXT_TX(N) (((N) + 1) & (TX_RING_SIZE - 1)) 930e689cf4aSJeff Kirsher #define NEXT_RX(N) (((N) + 1) & (RX_RING_SIZE - 1)) 931e689cf4aSJeff Kirsher 932e689cf4aSJeff Kirsher #define TX_BUFFS_AVAIL(GP) \ 933e689cf4aSJeff Kirsher (((GP)->tx_old <= (GP)->tx_new) ? \ 934e689cf4aSJeff Kirsher (GP)->tx_old + (TX_RING_SIZE - 1) - (GP)->tx_new : \ 935e689cf4aSJeff Kirsher (GP)->tx_old - (GP)->tx_new - 1) 936e689cf4aSJeff Kirsher 937e689cf4aSJeff Kirsher #define RX_OFFSET 2 938e689cf4aSJeff Kirsher #define RX_BUF_ALLOC_SIZE(gp) ((gp)->rx_buf_sz + 28 + RX_OFFSET + 64) 939e689cf4aSJeff Kirsher 940e689cf4aSJeff Kirsher #define RX_COPY_THRESHOLD 256 941e689cf4aSJeff Kirsher 942e689cf4aSJeff Kirsher #if TX_RING_SIZE < 128 943e689cf4aSJeff Kirsher #define INIT_BLOCK_TX_RING_SIZE 128 944e689cf4aSJeff Kirsher #else 945e689cf4aSJeff Kirsher #define INIT_BLOCK_TX_RING_SIZE TX_RING_SIZE 946e689cf4aSJeff Kirsher #endif 947e689cf4aSJeff Kirsher 948e689cf4aSJeff Kirsher #if RX_RING_SIZE < 128 949e689cf4aSJeff Kirsher #define INIT_BLOCK_RX_RING_SIZE 128 950e689cf4aSJeff Kirsher #else 951e689cf4aSJeff Kirsher #define INIT_BLOCK_RX_RING_SIZE RX_RING_SIZE 952e689cf4aSJeff Kirsher #endif 953e689cf4aSJeff Kirsher 954e689cf4aSJeff Kirsher struct gem_init_block { 955e689cf4aSJeff Kirsher struct gem_txd txd[INIT_BLOCK_TX_RING_SIZE]; 956e689cf4aSJeff Kirsher struct gem_rxd rxd[INIT_BLOCK_RX_RING_SIZE]; 957e689cf4aSJeff Kirsher }; 958e689cf4aSJeff Kirsher 959e689cf4aSJeff Kirsher enum gem_phy_type { 960e689cf4aSJeff Kirsher phy_mii_mdio0, 961e689cf4aSJeff Kirsher phy_mii_mdio1, 962e689cf4aSJeff Kirsher phy_serialink, 963e689cf4aSJeff Kirsher phy_serdes, 964e689cf4aSJeff Kirsher }; 965e689cf4aSJeff Kirsher 966e689cf4aSJeff Kirsher enum link_state { 967e689cf4aSJeff Kirsher link_down = 0, /* No link, will retry */ 968e689cf4aSJeff Kirsher link_aneg, /* Autoneg in progress */ 969e689cf4aSJeff Kirsher link_force_try, /* Try Forced link speed */ 970e689cf4aSJeff Kirsher link_force_ret, /* Forced mode worked, retrying autoneg */ 971e689cf4aSJeff Kirsher link_force_ok, /* Stay in forced mode */ 972e689cf4aSJeff Kirsher link_up /* Link is up */ 973e689cf4aSJeff Kirsher }; 974e689cf4aSJeff Kirsher 975e689cf4aSJeff Kirsher struct gem { 976e689cf4aSJeff Kirsher void __iomem *regs; 977e689cf4aSJeff Kirsher int rx_new, rx_old; 978e689cf4aSJeff Kirsher int tx_new, tx_old; 979e689cf4aSJeff Kirsher 980e689cf4aSJeff Kirsher unsigned int has_wol : 1; /* chip supports wake-on-lan */ 981e689cf4aSJeff Kirsher unsigned int asleep_wol : 1; /* was asleep with WOL enabled */ 982e689cf4aSJeff Kirsher 983e689cf4aSJeff Kirsher int cell_enabled; 984e689cf4aSJeff Kirsher u32 msg_enable; 985e689cf4aSJeff Kirsher u32 status; 986e689cf4aSJeff Kirsher 987e689cf4aSJeff Kirsher struct napi_struct napi; 988e689cf4aSJeff Kirsher 989e689cf4aSJeff Kirsher int tx_fifo_sz; 990e689cf4aSJeff Kirsher int rx_fifo_sz; 991e689cf4aSJeff Kirsher int rx_pause_off; 992e689cf4aSJeff Kirsher int rx_pause_on; 993e689cf4aSJeff Kirsher int rx_buf_sz; 994e689cf4aSJeff Kirsher u64 pause_entered; 995e689cf4aSJeff Kirsher u16 pause_last_time_recvd; 996e689cf4aSJeff Kirsher u32 mac_rx_cfg; 997e689cf4aSJeff Kirsher u32 swrst_base; 998e689cf4aSJeff Kirsher 999e689cf4aSJeff Kirsher int want_autoneg; 1000e689cf4aSJeff Kirsher int last_forced_speed; 1001e689cf4aSJeff Kirsher enum link_state lstate; 1002e689cf4aSJeff Kirsher struct timer_list link_timer; 1003e689cf4aSJeff Kirsher int timer_ticks; 1004e689cf4aSJeff Kirsher int wake_on_lan; 1005e689cf4aSJeff Kirsher struct work_struct reset_task; 1006e689cf4aSJeff Kirsher volatile int reset_task_pending; 1007e689cf4aSJeff Kirsher 1008e689cf4aSJeff Kirsher enum gem_phy_type phy_type; 1009e689cf4aSJeff Kirsher struct mii_phy phy_mii; 1010e689cf4aSJeff Kirsher int mii_phy_addr; 1011e689cf4aSJeff Kirsher 1012e689cf4aSJeff Kirsher struct gem_init_block *init_block; 1013e689cf4aSJeff Kirsher struct sk_buff *rx_skbs[RX_RING_SIZE]; 1014e689cf4aSJeff Kirsher struct sk_buff *tx_skbs[TX_RING_SIZE]; 1015e689cf4aSJeff Kirsher dma_addr_t gblock_dvma; 1016e689cf4aSJeff Kirsher 1017e689cf4aSJeff Kirsher struct pci_dev *pdev; 1018e689cf4aSJeff Kirsher struct net_device *dev; 1019e689cf4aSJeff Kirsher #if defined(CONFIG_PPC_PMAC) || defined(CONFIG_SPARC) 1020e689cf4aSJeff Kirsher struct device_node *of_node; 1021e689cf4aSJeff Kirsher #endif 1022e689cf4aSJeff Kirsher }; 1023e689cf4aSJeff Kirsher 1024e689cf4aSJeff Kirsher #define found_mii_phy(gp) ((gp->phy_type == phy_mii_mdio0 || gp->phy_type == phy_mii_mdio1) && \ 1025e689cf4aSJeff Kirsher gp->phy_mii.def && gp->phy_mii.def->ops) 1026e689cf4aSJeff Kirsher 1027e689cf4aSJeff Kirsher #endif /* _SUNGEM_H */ 1028