1 // SPDX-License-Identifier: GPL-2.0 2 /* $Id: sungem.c,v 1.44.2.22 2002/03/13 01:18:12 davem Exp $ 3 * sungem.c: Sun GEM ethernet driver. 4 * 5 * Copyright (C) 2000, 2001, 2002, 2003 David S. Miller (davem@redhat.com) 6 * 7 * Support for Apple GMAC and assorted PHYs, WOL, Power Management 8 * (C) 2001,2002,2003 Benjamin Herrenscmidt (benh@kernel.crashing.org) 9 * (C) 2004,2005 Benjamin Herrenscmidt, IBM Corp. 10 * 11 * NAPI and NETPOLL support 12 * (C) 2004 by Eric Lemoine (eric.lemoine@gmail.com) 13 * 14 */ 15 16 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 17 18 #include <linux/module.h> 19 #include <linux/kernel.h> 20 #include <linux/types.h> 21 #include <linux/fcntl.h> 22 #include <linux/interrupt.h> 23 #include <linux/ioport.h> 24 #include <linux/in.h> 25 #include <linux/sched.h> 26 #include <linux/string.h> 27 #include <linux/delay.h> 28 #include <linux/errno.h> 29 #include <linux/pci.h> 30 #include <linux/dma-mapping.h> 31 #include <linux/netdevice.h> 32 #include <linux/etherdevice.h> 33 #include <linux/skbuff.h> 34 #include <linux/mii.h> 35 #include <linux/ethtool.h> 36 #include <linux/crc32.h> 37 #include <linux/random.h> 38 #include <linux/workqueue.h> 39 #include <linux/if_vlan.h> 40 #include <linux/bitops.h> 41 #include <linux/mm.h> 42 #include <linux/gfp.h> 43 44 #include <asm/io.h> 45 #include <asm/byteorder.h> 46 #include <linux/uaccess.h> 47 #include <asm/irq.h> 48 49 #ifdef CONFIG_SPARC 50 #include <asm/idprom.h> 51 #include <asm/prom.h> 52 #endif 53 54 #ifdef CONFIG_PPC_PMAC 55 #include <asm/prom.h> 56 #include <asm/machdep.h> 57 #include <asm/pmac_feature.h> 58 #endif 59 60 #include <linux/sungem_phy.h> 61 #include "sungem.h" 62 63 #define STRIP_FCS 64 65 #define DEFAULT_MSG (NETIF_MSG_DRV | \ 66 NETIF_MSG_PROBE | \ 67 NETIF_MSG_LINK) 68 69 #define ADVERTISE_MASK (SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full | \ 70 SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full | \ 71 SUPPORTED_1000baseT_Half | SUPPORTED_1000baseT_Full | \ 72 SUPPORTED_Pause | SUPPORTED_Autoneg) 73 74 #define DRV_NAME "sungem" 75 #define DRV_VERSION "1.0" 76 #define DRV_AUTHOR "David S. Miller <davem@redhat.com>" 77 78 static char version[] = 79 DRV_NAME ".c:v" DRV_VERSION " " DRV_AUTHOR "\n"; 80 81 MODULE_AUTHOR(DRV_AUTHOR); 82 MODULE_DESCRIPTION("Sun GEM Gbit ethernet driver"); 83 MODULE_LICENSE("GPL"); 84 85 #define GEM_MODULE_NAME "gem" 86 87 static const struct pci_device_id gem_pci_tbl[] = { 88 { PCI_VENDOR_ID_SUN, PCI_DEVICE_ID_SUN_GEM, 89 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL }, 90 91 /* These models only differ from the original GEM in 92 * that their tx/rx fifos are of a different size and 93 * they only support 10/100 speeds. -DaveM 94 * 95 * Apple's GMAC does support gigabit on machines with 96 * the BCM54xx PHYs. -BenH 97 */ 98 { PCI_VENDOR_ID_SUN, PCI_DEVICE_ID_SUN_RIO_GEM, 99 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL }, 100 { PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_GMAC, 101 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL }, 102 { PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_GMACP, 103 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL }, 104 { PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_GMAC2, 105 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL }, 106 { PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_K2_GMAC, 107 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL }, 108 { PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_SH_SUNGEM, 109 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL }, 110 { PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_IPID2_GMAC, 111 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL }, 112 {0, } 113 }; 114 115 MODULE_DEVICE_TABLE(pci, gem_pci_tbl); 116 117 static u16 __sungem_phy_read(struct gem *gp, int phy_addr, int reg) 118 { 119 u32 cmd; 120 int limit = 10000; 121 122 cmd = (1 << 30); 123 cmd |= (2 << 28); 124 cmd |= (phy_addr << 23) & MIF_FRAME_PHYAD; 125 cmd |= (reg << 18) & MIF_FRAME_REGAD; 126 cmd |= (MIF_FRAME_TAMSB); 127 writel(cmd, gp->regs + MIF_FRAME); 128 129 while (--limit) { 130 cmd = readl(gp->regs + MIF_FRAME); 131 if (cmd & MIF_FRAME_TALSB) 132 break; 133 134 udelay(10); 135 } 136 137 if (!limit) 138 cmd = 0xffff; 139 140 return cmd & MIF_FRAME_DATA; 141 } 142 143 static inline int _sungem_phy_read(struct net_device *dev, int mii_id, int reg) 144 { 145 struct gem *gp = netdev_priv(dev); 146 return __sungem_phy_read(gp, mii_id, reg); 147 } 148 149 static inline u16 sungem_phy_read(struct gem *gp, int reg) 150 { 151 return __sungem_phy_read(gp, gp->mii_phy_addr, reg); 152 } 153 154 static void __sungem_phy_write(struct gem *gp, int phy_addr, int reg, u16 val) 155 { 156 u32 cmd; 157 int limit = 10000; 158 159 cmd = (1 << 30); 160 cmd |= (1 << 28); 161 cmd |= (phy_addr << 23) & MIF_FRAME_PHYAD; 162 cmd |= (reg << 18) & MIF_FRAME_REGAD; 163 cmd |= (MIF_FRAME_TAMSB); 164 cmd |= (val & MIF_FRAME_DATA); 165 writel(cmd, gp->regs + MIF_FRAME); 166 167 while (limit--) { 168 cmd = readl(gp->regs + MIF_FRAME); 169 if (cmd & MIF_FRAME_TALSB) 170 break; 171 172 udelay(10); 173 } 174 } 175 176 static inline void _sungem_phy_write(struct net_device *dev, int mii_id, int reg, int val) 177 { 178 struct gem *gp = netdev_priv(dev); 179 __sungem_phy_write(gp, mii_id, reg, val & 0xffff); 180 } 181 182 static inline void sungem_phy_write(struct gem *gp, int reg, u16 val) 183 { 184 __sungem_phy_write(gp, gp->mii_phy_addr, reg, val); 185 } 186 187 static inline void gem_enable_ints(struct gem *gp) 188 { 189 /* Enable all interrupts but TXDONE */ 190 writel(GREG_STAT_TXDONE, gp->regs + GREG_IMASK); 191 } 192 193 static inline void gem_disable_ints(struct gem *gp) 194 { 195 /* Disable all interrupts, including TXDONE */ 196 writel(GREG_STAT_NAPI | GREG_STAT_TXDONE, gp->regs + GREG_IMASK); 197 (void)readl(gp->regs + GREG_IMASK); /* write posting */ 198 } 199 200 static void gem_get_cell(struct gem *gp) 201 { 202 BUG_ON(gp->cell_enabled < 0); 203 gp->cell_enabled++; 204 #ifdef CONFIG_PPC_PMAC 205 if (gp->cell_enabled == 1) { 206 mb(); 207 pmac_call_feature(PMAC_FTR_GMAC_ENABLE, gp->of_node, 0, 1); 208 udelay(10); 209 } 210 #endif /* CONFIG_PPC_PMAC */ 211 } 212 213 /* Turn off the chip's clock */ 214 static void gem_put_cell(struct gem *gp) 215 { 216 BUG_ON(gp->cell_enabled <= 0); 217 gp->cell_enabled--; 218 #ifdef CONFIG_PPC_PMAC 219 if (gp->cell_enabled == 0) { 220 mb(); 221 pmac_call_feature(PMAC_FTR_GMAC_ENABLE, gp->of_node, 0, 0); 222 udelay(10); 223 } 224 #endif /* CONFIG_PPC_PMAC */ 225 } 226 227 static inline void gem_netif_stop(struct gem *gp) 228 { 229 netif_trans_update(gp->dev); /* prevent tx timeout */ 230 napi_disable(&gp->napi); 231 netif_tx_disable(gp->dev); 232 } 233 234 static inline void gem_netif_start(struct gem *gp) 235 { 236 /* NOTE: unconditional netif_wake_queue is only 237 * appropriate so long as all callers are assured to 238 * have free tx slots. 239 */ 240 netif_wake_queue(gp->dev); 241 napi_enable(&gp->napi); 242 } 243 244 static void gem_schedule_reset(struct gem *gp) 245 { 246 gp->reset_task_pending = 1; 247 schedule_work(&gp->reset_task); 248 } 249 250 static void gem_handle_mif_event(struct gem *gp, u32 reg_val, u32 changed_bits) 251 { 252 if (netif_msg_intr(gp)) 253 printk(KERN_DEBUG "%s: mif interrupt\n", gp->dev->name); 254 } 255 256 static int gem_pcs_interrupt(struct net_device *dev, struct gem *gp, u32 gem_status) 257 { 258 u32 pcs_istat = readl(gp->regs + PCS_ISTAT); 259 u32 pcs_miistat; 260 261 if (netif_msg_intr(gp)) 262 printk(KERN_DEBUG "%s: pcs interrupt, pcs_istat: 0x%x\n", 263 gp->dev->name, pcs_istat); 264 265 if (!(pcs_istat & PCS_ISTAT_LSC)) { 266 netdev_err(dev, "PCS irq but no link status change???\n"); 267 return 0; 268 } 269 270 /* The link status bit latches on zero, so you must 271 * read it twice in such a case to see a transition 272 * to the link being up. 273 */ 274 pcs_miistat = readl(gp->regs + PCS_MIISTAT); 275 if (!(pcs_miistat & PCS_MIISTAT_LS)) 276 pcs_miistat |= 277 (readl(gp->regs + PCS_MIISTAT) & 278 PCS_MIISTAT_LS); 279 280 if (pcs_miistat & PCS_MIISTAT_ANC) { 281 /* The remote-fault indication is only valid 282 * when autoneg has completed. 283 */ 284 if (pcs_miistat & PCS_MIISTAT_RF) 285 netdev_info(dev, "PCS AutoNEG complete, RemoteFault\n"); 286 else 287 netdev_info(dev, "PCS AutoNEG complete\n"); 288 } 289 290 if (pcs_miistat & PCS_MIISTAT_LS) { 291 netdev_info(dev, "PCS link is now up\n"); 292 netif_carrier_on(gp->dev); 293 } else { 294 netdev_info(dev, "PCS link is now down\n"); 295 netif_carrier_off(gp->dev); 296 /* If this happens and the link timer is not running, 297 * reset so we re-negotiate. 298 */ 299 if (!timer_pending(&gp->link_timer)) 300 return 1; 301 } 302 303 return 0; 304 } 305 306 static int gem_txmac_interrupt(struct net_device *dev, struct gem *gp, u32 gem_status) 307 { 308 u32 txmac_stat = readl(gp->regs + MAC_TXSTAT); 309 310 if (netif_msg_intr(gp)) 311 printk(KERN_DEBUG "%s: txmac interrupt, txmac_stat: 0x%x\n", 312 gp->dev->name, txmac_stat); 313 314 /* Defer timer expiration is quite normal, 315 * don't even log the event. 316 */ 317 if ((txmac_stat & MAC_TXSTAT_DTE) && 318 !(txmac_stat & ~MAC_TXSTAT_DTE)) 319 return 0; 320 321 if (txmac_stat & MAC_TXSTAT_URUN) { 322 netdev_err(dev, "TX MAC xmit underrun\n"); 323 dev->stats.tx_fifo_errors++; 324 } 325 326 if (txmac_stat & MAC_TXSTAT_MPE) { 327 netdev_err(dev, "TX MAC max packet size error\n"); 328 dev->stats.tx_errors++; 329 } 330 331 /* The rest are all cases of one of the 16-bit TX 332 * counters expiring. 333 */ 334 if (txmac_stat & MAC_TXSTAT_NCE) 335 dev->stats.collisions += 0x10000; 336 337 if (txmac_stat & MAC_TXSTAT_ECE) { 338 dev->stats.tx_aborted_errors += 0x10000; 339 dev->stats.collisions += 0x10000; 340 } 341 342 if (txmac_stat & MAC_TXSTAT_LCE) { 343 dev->stats.tx_aborted_errors += 0x10000; 344 dev->stats.collisions += 0x10000; 345 } 346 347 /* We do not keep track of MAC_TXSTAT_FCE and 348 * MAC_TXSTAT_PCE events. 349 */ 350 return 0; 351 } 352 353 /* When we get a RX fifo overflow, the RX unit in GEM is probably hung 354 * so we do the following. 355 * 356 * If any part of the reset goes wrong, we return 1 and that causes the 357 * whole chip to be reset. 358 */ 359 static int gem_rxmac_reset(struct gem *gp) 360 { 361 struct net_device *dev = gp->dev; 362 int limit, i; 363 u64 desc_dma; 364 u32 val; 365 366 /* First, reset & disable MAC RX. */ 367 writel(MAC_RXRST_CMD, gp->regs + MAC_RXRST); 368 for (limit = 0; limit < 5000; limit++) { 369 if (!(readl(gp->regs + MAC_RXRST) & MAC_RXRST_CMD)) 370 break; 371 udelay(10); 372 } 373 if (limit == 5000) { 374 netdev_err(dev, "RX MAC will not reset, resetting whole chip\n"); 375 return 1; 376 } 377 378 writel(gp->mac_rx_cfg & ~MAC_RXCFG_ENAB, 379 gp->regs + MAC_RXCFG); 380 for (limit = 0; limit < 5000; limit++) { 381 if (!(readl(gp->regs + MAC_RXCFG) & MAC_RXCFG_ENAB)) 382 break; 383 udelay(10); 384 } 385 if (limit == 5000) { 386 netdev_err(dev, "RX MAC will not disable, resetting whole chip\n"); 387 return 1; 388 } 389 390 /* Second, disable RX DMA. */ 391 writel(0, gp->regs + RXDMA_CFG); 392 for (limit = 0; limit < 5000; limit++) { 393 if (!(readl(gp->regs + RXDMA_CFG) & RXDMA_CFG_ENABLE)) 394 break; 395 udelay(10); 396 } 397 if (limit == 5000) { 398 netdev_err(dev, "RX DMA will not disable, resetting whole chip\n"); 399 return 1; 400 } 401 402 mdelay(5); 403 404 /* Execute RX reset command. */ 405 writel(gp->swrst_base | GREG_SWRST_RXRST, 406 gp->regs + GREG_SWRST); 407 for (limit = 0; limit < 5000; limit++) { 408 if (!(readl(gp->regs + GREG_SWRST) & GREG_SWRST_RXRST)) 409 break; 410 udelay(10); 411 } 412 if (limit == 5000) { 413 netdev_err(dev, "RX reset command will not execute, resetting whole chip\n"); 414 return 1; 415 } 416 417 /* Refresh the RX ring. */ 418 for (i = 0; i < RX_RING_SIZE; i++) { 419 struct gem_rxd *rxd = &gp->init_block->rxd[i]; 420 421 if (gp->rx_skbs[i] == NULL) { 422 netdev_err(dev, "Parts of RX ring empty, resetting whole chip\n"); 423 return 1; 424 } 425 426 rxd->status_word = cpu_to_le64(RXDCTRL_FRESH(gp)); 427 } 428 gp->rx_new = gp->rx_old = 0; 429 430 /* Now we must reprogram the rest of RX unit. */ 431 desc_dma = (u64) gp->gblock_dvma; 432 desc_dma += (INIT_BLOCK_TX_RING_SIZE * sizeof(struct gem_txd)); 433 writel(desc_dma >> 32, gp->regs + RXDMA_DBHI); 434 writel(desc_dma & 0xffffffff, gp->regs + RXDMA_DBLOW); 435 writel(RX_RING_SIZE - 4, gp->regs + RXDMA_KICK); 436 val = (RXDMA_CFG_BASE | (RX_OFFSET << 10) | 437 (ETH_HLEN << 13) | RXDMA_CFG_FTHRESH_128); 438 writel(val, gp->regs + RXDMA_CFG); 439 if (readl(gp->regs + GREG_BIFCFG) & GREG_BIFCFG_M66EN) 440 writel(((5 & RXDMA_BLANK_IPKTS) | 441 ((8 << 12) & RXDMA_BLANK_ITIME)), 442 gp->regs + RXDMA_BLANK); 443 else 444 writel(((5 & RXDMA_BLANK_IPKTS) | 445 ((4 << 12) & RXDMA_BLANK_ITIME)), 446 gp->regs + RXDMA_BLANK); 447 val = (((gp->rx_pause_off / 64) << 0) & RXDMA_PTHRESH_OFF); 448 val |= (((gp->rx_pause_on / 64) << 12) & RXDMA_PTHRESH_ON); 449 writel(val, gp->regs + RXDMA_PTHRESH); 450 val = readl(gp->regs + RXDMA_CFG); 451 writel(val | RXDMA_CFG_ENABLE, gp->regs + RXDMA_CFG); 452 writel(MAC_RXSTAT_RCV, gp->regs + MAC_RXMASK); 453 val = readl(gp->regs + MAC_RXCFG); 454 writel(val | MAC_RXCFG_ENAB, gp->regs + MAC_RXCFG); 455 456 return 0; 457 } 458 459 static int gem_rxmac_interrupt(struct net_device *dev, struct gem *gp, u32 gem_status) 460 { 461 u32 rxmac_stat = readl(gp->regs + MAC_RXSTAT); 462 int ret = 0; 463 464 if (netif_msg_intr(gp)) 465 printk(KERN_DEBUG "%s: rxmac interrupt, rxmac_stat: 0x%x\n", 466 gp->dev->name, rxmac_stat); 467 468 if (rxmac_stat & MAC_RXSTAT_OFLW) { 469 u32 smac = readl(gp->regs + MAC_SMACHINE); 470 471 netdev_err(dev, "RX MAC fifo overflow smac[%08x]\n", smac); 472 dev->stats.rx_over_errors++; 473 dev->stats.rx_fifo_errors++; 474 475 ret = gem_rxmac_reset(gp); 476 } 477 478 if (rxmac_stat & MAC_RXSTAT_ACE) 479 dev->stats.rx_frame_errors += 0x10000; 480 481 if (rxmac_stat & MAC_RXSTAT_CCE) 482 dev->stats.rx_crc_errors += 0x10000; 483 484 if (rxmac_stat & MAC_RXSTAT_LCE) 485 dev->stats.rx_length_errors += 0x10000; 486 487 /* We do not track MAC_RXSTAT_FCE and MAC_RXSTAT_VCE 488 * events. 489 */ 490 return ret; 491 } 492 493 static int gem_mac_interrupt(struct net_device *dev, struct gem *gp, u32 gem_status) 494 { 495 u32 mac_cstat = readl(gp->regs + MAC_CSTAT); 496 497 if (netif_msg_intr(gp)) 498 printk(KERN_DEBUG "%s: mac interrupt, mac_cstat: 0x%x\n", 499 gp->dev->name, mac_cstat); 500 501 /* This interrupt is just for pause frame and pause 502 * tracking. It is useful for diagnostics and debug 503 * but probably by default we will mask these events. 504 */ 505 if (mac_cstat & MAC_CSTAT_PS) 506 gp->pause_entered++; 507 508 if (mac_cstat & MAC_CSTAT_PRCV) 509 gp->pause_last_time_recvd = (mac_cstat >> 16); 510 511 return 0; 512 } 513 514 static int gem_mif_interrupt(struct net_device *dev, struct gem *gp, u32 gem_status) 515 { 516 u32 mif_status = readl(gp->regs + MIF_STATUS); 517 u32 reg_val, changed_bits; 518 519 reg_val = (mif_status & MIF_STATUS_DATA) >> 16; 520 changed_bits = (mif_status & MIF_STATUS_STAT); 521 522 gem_handle_mif_event(gp, reg_val, changed_bits); 523 524 return 0; 525 } 526 527 static int gem_pci_interrupt(struct net_device *dev, struct gem *gp, u32 gem_status) 528 { 529 u32 pci_estat = readl(gp->regs + GREG_PCIESTAT); 530 531 if (gp->pdev->vendor == PCI_VENDOR_ID_SUN && 532 gp->pdev->device == PCI_DEVICE_ID_SUN_GEM) { 533 netdev_err(dev, "PCI error [%04x]", pci_estat); 534 535 if (pci_estat & GREG_PCIESTAT_BADACK) 536 pr_cont(" <No ACK64# during ABS64 cycle>"); 537 if (pci_estat & GREG_PCIESTAT_DTRTO) 538 pr_cont(" <Delayed transaction timeout>"); 539 if (pci_estat & GREG_PCIESTAT_OTHER) 540 pr_cont(" <other>"); 541 pr_cont("\n"); 542 } else { 543 pci_estat |= GREG_PCIESTAT_OTHER; 544 netdev_err(dev, "PCI error\n"); 545 } 546 547 if (pci_estat & GREG_PCIESTAT_OTHER) { 548 int pci_errs; 549 550 /* Interrogate PCI config space for the 551 * true cause. 552 */ 553 pci_errs = pci_status_get_and_clear_errors(gp->pdev); 554 netdev_err(dev, "PCI status errors[%04x]\n", pci_errs); 555 if (pci_errs & PCI_STATUS_PARITY) 556 netdev_err(dev, "PCI parity error detected\n"); 557 if (pci_errs & PCI_STATUS_SIG_TARGET_ABORT) 558 netdev_err(dev, "PCI target abort\n"); 559 if (pci_errs & PCI_STATUS_REC_TARGET_ABORT) 560 netdev_err(dev, "PCI master acks target abort\n"); 561 if (pci_errs & PCI_STATUS_REC_MASTER_ABORT) 562 netdev_err(dev, "PCI master abort\n"); 563 if (pci_errs & PCI_STATUS_SIG_SYSTEM_ERROR) 564 netdev_err(dev, "PCI system error SERR#\n"); 565 if (pci_errs & PCI_STATUS_DETECTED_PARITY) 566 netdev_err(dev, "PCI parity error\n"); 567 } 568 569 /* For all PCI errors, we should reset the chip. */ 570 return 1; 571 } 572 573 /* All non-normal interrupt conditions get serviced here. 574 * Returns non-zero if we should just exit the interrupt 575 * handler right now (ie. if we reset the card which invalidates 576 * all of the other original irq status bits). 577 */ 578 static int gem_abnormal_irq(struct net_device *dev, struct gem *gp, u32 gem_status) 579 { 580 if (gem_status & GREG_STAT_RXNOBUF) { 581 /* Frame arrived, no free RX buffers available. */ 582 if (netif_msg_rx_err(gp)) 583 printk(KERN_DEBUG "%s: no buffer for rx frame\n", 584 gp->dev->name); 585 dev->stats.rx_dropped++; 586 } 587 588 if (gem_status & GREG_STAT_RXTAGERR) { 589 /* corrupt RX tag framing */ 590 if (netif_msg_rx_err(gp)) 591 printk(KERN_DEBUG "%s: corrupt rx tag framing\n", 592 gp->dev->name); 593 dev->stats.rx_errors++; 594 595 return 1; 596 } 597 598 if (gem_status & GREG_STAT_PCS) { 599 if (gem_pcs_interrupt(dev, gp, gem_status)) 600 return 1; 601 } 602 603 if (gem_status & GREG_STAT_TXMAC) { 604 if (gem_txmac_interrupt(dev, gp, gem_status)) 605 return 1; 606 } 607 608 if (gem_status & GREG_STAT_RXMAC) { 609 if (gem_rxmac_interrupt(dev, gp, gem_status)) 610 return 1; 611 } 612 613 if (gem_status & GREG_STAT_MAC) { 614 if (gem_mac_interrupt(dev, gp, gem_status)) 615 return 1; 616 } 617 618 if (gem_status & GREG_STAT_MIF) { 619 if (gem_mif_interrupt(dev, gp, gem_status)) 620 return 1; 621 } 622 623 if (gem_status & GREG_STAT_PCIERR) { 624 if (gem_pci_interrupt(dev, gp, gem_status)) 625 return 1; 626 } 627 628 return 0; 629 } 630 631 static __inline__ void gem_tx(struct net_device *dev, struct gem *gp, u32 gem_status) 632 { 633 int entry, limit; 634 635 entry = gp->tx_old; 636 limit = ((gem_status & GREG_STAT_TXNR) >> GREG_STAT_TXNR_SHIFT); 637 while (entry != limit) { 638 struct sk_buff *skb; 639 struct gem_txd *txd; 640 dma_addr_t dma_addr; 641 u32 dma_len; 642 int frag; 643 644 if (netif_msg_tx_done(gp)) 645 printk(KERN_DEBUG "%s: tx done, slot %d\n", 646 gp->dev->name, entry); 647 skb = gp->tx_skbs[entry]; 648 if (skb_shinfo(skb)->nr_frags) { 649 int last = entry + skb_shinfo(skb)->nr_frags; 650 int walk = entry; 651 int incomplete = 0; 652 653 last &= (TX_RING_SIZE - 1); 654 for (;;) { 655 walk = NEXT_TX(walk); 656 if (walk == limit) 657 incomplete = 1; 658 if (walk == last) 659 break; 660 } 661 if (incomplete) 662 break; 663 } 664 gp->tx_skbs[entry] = NULL; 665 dev->stats.tx_bytes += skb->len; 666 667 for (frag = 0; frag <= skb_shinfo(skb)->nr_frags; frag++) { 668 txd = &gp->init_block->txd[entry]; 669 670 dma_addr = le64_to_cpu(txd->buffer); 671 dma_len = le64_to_cpu(txd->control_word) & TXDCTRL_BUFSZ; 672 673 pci_unmap_page(gp->pdev, dma_addr, dma_len, PCI_DMA_TODEVICE); 674 entry = NEXT_TX(entry); 675 } 676 677 dev->stats.tx_packets++; 678 dev_consume_skb_any(skb); 679 } 680 gp->tx_old = entry; 681 682 /* Need to make the tx_old update visible to gem_start_xmit() 683 * before checking for netif_queue_stopped(). Without the 684 * memory barrier, there is a small possibility that gem_start_xmit() 685 * will miss it and cause the queue to be stopped forever. 686 */ 687 smp_mb(); 688 689 if (unlikely(netif_queue_stopped(dev) && 690 TX_BUFFS_AVAIL(gp) > (MAX_SKB_FRAGS + 1))) { 691 struct netdev_queue *txq = netdev_get_tx_queue(dev, 0); 692 693 __netif_tx_lock(txq, smp_processor_id()); 694 if (netif_queue_stopped(dev) && 695 TX_BUFFS_AVAIL(gp) > (MAX_SKB_FRAGS + 1)) 696 netif_wake_queue(dev); 697 __netif_tx_unlock(txq); 698 } 699 } 700 701 static __inline__ void gem_post_rxds(struct gem *gp, int limit) 702 { 703 int cluster_start, curr, count, kick; 704 705 cluster_start = curr = (gp->rx_new & ~(4 - 1)); 706 count = 0; 707 kick = -1; 708 dma_wmb(); 709 while (curr != limit) { 710 curr = NEXT_RX(curr); 711 if (++count == 4) { 712 struct gem_rxd *rxd = 713 &gp->init_block->rxd[cluster_start]; 714 for (;;) { 715 rxd->status_word = cpu_to_le64(RXDCTRL_FRESH(gp)); 716 rxd++; 717 cluster_start = NEXT_RX(cluster_start); 718 if (cluster_start == curr) 719 break; 720 } 721 kick = curr; 722 count = 0; 723 } 724 } 725 if (kick >= 0) { 726 mb(); 727 writel(kick, gp->regs + RXDMA_KICK); 728 } 729 } 730 731 #define ALIGNED_RX_SKB_ADDR(addr) \ 732 ((((unsigned long)(addr) + (64UL - 1UL)) & ~(64UL - 1UL)) - (unsigned long)(addr)) 733 static __inline__ struct sk_buff *gem_alloc_skb(struct net_device *dev, int size, 734 gfp_t gfp_flags) 735 { 736 struct sk_buff *skb = alloc_skb(size + 64, gfp_flags); 737 738 if (likely(skb)) { 739 unsigned long offset = ALIGNED_RX_SKB_ADDR(skb->data); 740 skb_reserve(skb, offset); 741 } 742 return skb; 743 } 744 745 static int gem_rx(struct gem *gp, int work_to_do) 746 { 747 struct net_device *dev = gp->dev; 748 int entry, drops, work_done = 0; 749 u32 done; 750 751 if (netif_msg_rx_status(gp)) 752 printk(KERN_DEBUG "%s: rx interrupt, done: %d, rx_new: %d\n", 753 gp->dev->name, readl(gp->regs + RXDMA_DONE), gp->rx_new); 754 755 entry = gp->rx_new; 756 drops = 0; 757 done = readl(gp->regs + RXDMA_DONE); 758 for (;;) { 759 struct gem_rxd *rxd = &gp->init_block->rxd[entry]; 760 struct sk_buff *skb; 761 u64 status = le64_to_cpu(rxd->status_word); 762 dma_addr_t dma_addr; 763 int len; 764 765 if ((status & RXDCTRL_OWN) != 0) 766 break; 767 768 if (work_done >= RX_RING_SIZE || work_done >= work_to_do) 769 break; 770 771 /* When writing back RX descriptor, GEM writes status 772 * then buffer address, possibly in separate transactions. 773 * If we don't wait for the chip to write both, we could 774 * post a new buffer to this descriptor then have GEM spam 775 * on the buffer address. We sync on the RX completion 776 * register to prevent this from happening. 777 */ 778 if (entry == done) { 779 done = readl(gp->regs + RXDMA_DONE); 780 if (entry == done) 781 break; 782 } 783 784 /* We can now account for the work we're about to do */ 785 work_done++; 786 787 skb = gp->rx_skbs[entry]; 788 789 len = (status & RXDCTRL_BUFSZ) >> 16; 790 if ((len < ETH_ZLEN) || (status & RXDCTRL_BAD)) { 791 dev->stats.rx_errors++; 792 if (len < ETH_ZLEN) 793 dev->stats.rx_length_errors++; 794 if (len & RXDCTRL_BAD) 795 dev->stats.rx_crc_errors++; 796 797 /* We'll just return it to GEM. */ 798 drop_it: 799 dev->stats.rx_dropped++; 800 goto next; 801 } 802 803 dma_addr = le64_to_cpu(rxd->buffer); 804 if (len > RX_COPY_THRESHOLD) { 805 struct sk_buff *new_skb; 806 807 new_skb = gem_alloc_skb(dev, RX_BUF_ALLOC_SIZE(gp), GFP_ATOMIC); 808 if (new_skb == NULL) { 809 drops++; 810 goto drop_it; 811 } 812 pci_unmap_page(gp->pdev, dma_addr, 813 RX_BUF_ALLOC_SIZE(gp), 814 PCI_DMA_FROMDEVICE); 815 gp->rx_skbs[entry] = new_skb; 816 skb_put(new_skb, (gp->rx_buf_sz + RX_OFFSET)); 817 rxd->buffer = cpu_to_le64(pci_map_page(gp->pdev, 818 virt_to_page(new_skb->data), 819 offset_in_page(new_skb->data), 820 RX_BUF_ALLOC_SIZE(gp), 821 PCI_DMA_FROMDEVICE)); 822 skb_reserve(new_skb, RX_OFFSET); 823 824 /* Trim the original skb for the netif. */ 825 skb_trim(skb, len); 826 } else { 827 struct sk_buff *copy_skb = netdev_alloc_skb(dev, len + 2); 828 829 if (copy_skb == NULL) { 830 drops++; 831 goto drop_it; 832 } 833 834 skb_reserve(copy_skb, 2); 835 skb_put(copy_skb, len); 836 pci_dma_sync_single_for_cpu(gp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE); 837 skb_copy_from_linear_data(skb, copy_skb->data, len); 838 pci_dma_sync_single_for_device(gp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE); 839 840 /* We'll reuse the original ring buffer. */ 841 skb = copy_skb; 842 } 843 844 if (likely(dev->features & NETIF_F_RXCSUM)) { 845 __sum16 csum; 846 847 csum = (__force __sum16)htons((status & RXDCTRL_TCPCSUM) ^ 0xffff); 848 skb->csum = csum_unfold(csum); 849 skb->ip_summed = CHECKSUM_COMPLETE; 850 } 851 skb->protocol = eth_type_trans(skb, gp->dev); 852 853 napi_gro_receive(&gp->napi, skb); 854 855 dev->stats.rx_packets++; 856 dev->stats.rx_bytes += len; 857 858 next: 859 entry = NEXT_RX(entry); 860 } 861 862 gem_post_rxds(gp, entry); 863 864 gp->rx_new = entry; 865 866 if (drops) 867 netdev_info(gp->dev, "Memory squeeze, deferring packet\n"); 868 869 return work_done; 870 } 871 872 static int gem_poll(struct napi_struct *napi, int budget) 873 { 874 struct gem *gp = container_of(napi, struct gem, napi); 875 struct net_device *dev = gp->dev; 876 int work_done; 877 878 work_done = 0; 879 do { 880 /* Handle anomalies */ 881 if (unlikely(gp->status & GREG_STAT_ABNORMAL)) { 882 struct netdev_queue *txq = netdev_get_tx_queue(dev, 0); 883 int reset; 884 885 /* We run the abnormal interrupt handling code with 886 * the Tx lock. It only resets the Rx portion of the 887 * chip, but we need to guard it against DMA being 888 * restarted by the link poll timer 889 */ 890 __netif_tx_lock(txq, smp_processor_id()); 891 reset = gem_abnormal_irq(dev, gp, gp->status); 892 __netif_tx_unlock(txq); 893 if (reset) { 894 gem_schedule_reset(gp); 895 napi_complete(napi); 896 return work_done; 897 } 898 } 899 900 /* Run TX completion thread */ 901 gem_tx(dev, gp, gp->status); 902 903 /* Run RX thread. We don't use any locking here, 904 * code willing to do bad things - like cleaning the 905 * rx ring - must call napi_disable(), which 906 * schedule_timeout()'s if polling is already disabled. 907 */ 908 work_done += gem_rx(gp, budget - work_done); 909 910 if (work_done >= budget) 911 return work_done; 912 913 gp->status = readl(gp->regs + GREG_STAT); 914 } while (gp->status & GREG_STAT_NAPI); 915 916 napi_complete_done(napi, work_done); 917 gem_enable_ints(gp); 918 919 return work_done; 920 } 921 922 static irqreturn_t gem_interrupt(int irq, void *dev_id) 923 { 924 struct net_device *dev = dev_id; 925 struct gem *gp = netdev_priv(dev); 926 927 if (napi_schedule_prep(&gp->napi)) { 928 u32 gem_status = readl(gp->regs + GREG_STAT); 929 930 if (unlikely(gem_status == 0)) { 931 napi_enable(&gp->napi); 932 return IRQ_NONE; 933 } 934 if (netif_msg_intr(gp)) 935 printk(KERN_DEBUG "%s: gem_interrupt() gem_status: 0x%x\n", 936 gp->dev->name, gem_status); 937 938 gp->status = gem_status; 939 gem_disable_ints(gp); 940 __napi_schedule(&gp->napi); 941 } 942 943 /* If polling was disabled at the time we received that 944 * interrupt, we may return IRQ_HANDLED here while we 945 * should return IRQ_NONE. No big deal... 946 */ 947 return IRQ_HANDLED; 948 } 949 950 #ifdef CONFIG_NET_POLL_CONTROLLER 951 static void gem_poll_controller(struct net_device *dev) 952 { 953 struct gem *gp = netdev_priv(dev); 954 955 disable_irq(gp->pdev->irq); 956 gem_interrupt(gp->pdev->irq, dev); 957 enable_irq(gp->pdev->irq); 958 } 959 #endif 960 961 static void gem_tx_timeout(struct net_device *dev, unsigned int txqueue) 962 { 963 struct gem *gp = netdev_priv(dev); 964 965 netdev_err(dev, "transmit timed out, resetting\n"); 966 967 netdev_err(dev, "TX_STATE[%08x:%08x:%08x]\n", 968 readl(gp->regs + TXDMA_CFG), 969 readl(gp->regs + MAC_TXSTAT), 970 readl(gp->regs + MAC_TXCFG)); 971 netdev_err(dev, "RX_STATE[%08x:%08x:%08x]\n", 972 readl(gp->regs + RXDMA_CFG), 973 readl(gp->regs + MAC_RXSTAT), 974 readl(gp->regs + MAC_RXCFG)); 975 976 gem_schedule_reset(gp); 977 } 978 979 static __inline__ int gem_intme(int entry) 980 { 981 /* Algorithm: IRQ every 1/2 of descriptors. */ 982 if (!(entry & ((TX_RING_SIZE>>1)-1))) 983 return 1; 984 985 return 0; 986 } 987 988 static netdev_tx_t gem_start_xmit(struct sk_buff *skb, 989 struct net_device *dev) 990 { 991 struct gem *gp = netdev_priv(dev); 992 int entry; 993 u64 ctrl; 994 995 ctrl = 0; 996 if (skb->ip_summed == CHECKSUM_PARTIAL) { 997 const u64 csum_start_off = skb_checksum_start_offset(skb); 998 const u64 csum_stuff_off = csum_start_off + skb->csum_offset; 999 1000 ctrl = (TXDCTRL_CENAB | 1001 (csum_start_off << 15) | 1002 (csum_stuff_off << 21)); 1003 } 1004 1005 if (unlikely(TX_BUFFS_AVAIL(gp) <= (skb_shinfo(skb)->nr_frags + 1))) { 1006 /* This is a hard error, log it. */ 1007 if (!netif_queue_stopped(dev)) { 1008 netif_stop_queue(dev); 1009 netdev_err(dev, "BUG! Tx Ring full when queue awake!\n"); 1010 } 1011 return NETDEV_TX_BUSY; 1012 } 1013 1014 entry = gp->tx_new; 1015 gp->tx_skbs[entry] = skb; 1016 1017 if (skb_shinfo(skb)->nr_frags == 0) { 1018 struct gem_txd *txd = &gp->init_block->txd[entry]; 1019 dma_addr_t mapping; 1020 u32 len; 1021 1022 len = skb->len; 1023 mapping = pci_map_page(gp->pdev, 1024 virt_to_page(skb->data), 1025 offset_in_page(skb->data), 1026 len, PCI_DMA_TODEVICE); 1027 ctrl |= TXDCTRL_SOF | TXDCTRL_EOF | len; 1028 if (gem_intme(entry)) 1029 ctrl |= TXDCTRL_INTME; 1030 txd->buffer = cpu_to_le64(mapping); 1031 dma_wmb(); 1032 txd->control_word = cpu_to_le64(ctrl); 1033 entry = NEXT_TX(entry); 1034 } else { 1035 struct gem_txd *txd; 1036 u32 first_len; 1037 u64 intme; 1038 dma_addr_t first_mapping; 1039 int frag, first_entry = entry; 1040 1041 intme = 0; 1042 if (gem_intme(entry)) 1043 intme |= TXDCTRL_INTME; 1044 1045 /* We must give this initial chunk to the device last. 1046 * Otherwise we could race with the device. 1047 */ 1048 first_len = skb_headlen(skb); 1049 first_mapping = pci_map_page(gp->pdev, virt_to_page(skb->data), 1050 offset_in_page(skb->data), 1051 first_len, PCI_DMA_TODEVICE); 1052 entry = NEXT_TX(entry); 1053 1054 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) { 1055 const skb_frag_t *this_frag = &skb_shinfo(skb)->frags[frag]; 1056 u32 len; 1057 dma_addr_t mapping; 1058 u64 this_ctrl; 1059 1060 len = skb_frag_size(this_frag); 1061 mapping = skb_frag_dma_map(&gp->pdev->dev, this_frag, 1062 0, len, DMA_TO_DEVICE); 1063 this_ctrl = ctrl; 1064 if (frag == skb_shinfo(skb)->nr_frags - 1) 1065 this_ctrl |= TXDCTRL_EOF; 1066 1067 txd = &gp->init_block->txd[entry]; 1068 txd->buffer = cpu_to_le64(mapping); 1069 dma_wmb(); 1070 txd->control_word = cpu_to_le64(this_ctrl | len); 1071 1072 if (gem_intme(entry)) 1073 intme |= TXDCTRL_INTME; 1074 1075 entry = NEXT_TX(entry); 1076 } 1077 txd = &gp->init_block->txd[first_entry]; 1078 txd->buffer = cpu_to_le64(first_mapping); 1079 dma_wmb(); 1080 txd->control_word = 1081 cpu_to_le64(ctrl | TXDCTRL_SOF | intme | first_len); 1082 } 1083 1084 gp->tx_new = entry; 1085 if (unlikely(TX_BUFFS_AVAIL(gp) <= (MAX_SKB_FRAGS + 1))) { 1086 netif_stop_queue(dev); 1087 1088 /* netif_stop_queue() must be done before checking 1089 * checking tx index in TX_BUFFS_AVAIL() below, because 1090 * in gem_tx(), we update tx_old before checking for 1091 * netif_queue_stopped(). 1092 */ 1093 smp_mb(); 1094 if (TX_BUFFS_AVAIL(gp) > (MAX_SKB_FRAGS + 1)) 1095 netif_wake_queue(dev); 1096 } 1097 if (netif_msg_tx_queued(gp)) 1098 printk(KERN_DEBUG "%s: tx queued, slot %d, skblen %d\n", 1099 dev->name, entry, skb->len); 1100 mb(); 1101 writel(gp->tx_new, gp->regs + TXDMA_KICK); 1102 1103 return NETDEV_TX_OK; 1104 } 1105 1106 static void gem_pcs_reset(struct gem *gp) 1107 { 1108 int limit; 1109 u32 val; 1110 1111 /* Reset PCS unit. */ 1112 val = readl(gp->regs + PCS_MIICTRL); 1113 val |= PCS_MIICTRL_RST; 1114 writel(val, gp->regs + PCS_MIICTRL); 1115 1116 limit = 32; 1117 while (readl(gp->regs + PCS_MIICTRL) & PCS_MIICTRL_RST) { 1118 udelay(100); 1119 if (limit-- <= 0) 1120 break; 1121 } 1122 if (limit < 0) 1123 netdev_warn(gp->dev, "PCS reset bit would not clear\n"); 1124 } 1125 1126 static void gem_pcs_reinit_adv(struct gem *gp) 1127 { 1128 u32 val; 1129 1130 /* Make sure PCS is disabled while changing advertisement 1131 * configuration. 1132 */ 1133 val = readl(gp->regs + PCS_CFG); 1134 val &= ~(PCS_CFG_ENABLE | PCS_CFG_TO); 1135 writel(val, gp->regs + PCS_CFG); 1136 1137 /* Advertise all capabilities except asymmetric 1138 * pause. 1139 */ 1140 val = readl(gp->regs + PCS_MIIADV); 1141 val |= (PCS_MIIADV_FD | PCS_MIIADV_HD | 1142 PCS_MIIADV_SP | PCS_MIIADV_AP); 1143 writel(val, gp->regs + PCS_MIIADV); 1144 1145 /* Enable and restart auto-negotiation, disable wrapback/loopback, 1146 * and re-enable PCS. 1147 */ 1148 val = readl(gp->regs + PCS_MIICTRL); 1149 val |= (PCS_MIICTRL_RAN | PCS_MIICTRL_ANE); 1150 val &= ~PCS_MIICTRL_WB; 1151 writel(val, gp->regs + PCS_MIICTRL); 1152 1153 val = readl(gp->regs + PCS_CFG); 1154 val |= PCS_CFG_ENABLE; 1155 writel(val, gp->regs + PCS_CFG); 1156 1157 /* Make sure serialink loopback is off. The meaning 1158 * of this bit is logically inverted based upon whether 1159 * you are in Serialink or SERDES mode. 1160 */ 1161 val = readl(gp->regs + PCS_SCTRL); 1162 if (gp->phy_type == phy_serialink) 1163 val &= ~PCS_SCTRL_LOOP; 1164 else 1165 val |= PCS_SCTRL_LOOP; 1166 writel(val, gp->regs + PCS_SCTRL); 1167 } 1168 1169 #define STOP_TRIES 32 1170 1171 static void gem_reset(struct gem *gp) 1172 { 1173 int limit; 1174 u32 val; 1175 1176 /* Make sure we won't get any more interrupts */ 1177 writel(0xffffffff, gp->regs + GREG_IMASK); 1178 1179 /* Reset the chip */ 1180 writel(gp->swrst_base | GREG_SWRST_TXRST | GREG_SWRST_RXRST, 1181 gp->regs + GREG_SWRST); 1182 1183 limit = STOP_TRIES; 1184 1185 do { 1186 udelay(20); 1187 val = readl(gp->regs + GREG_SWRST); 1188 if (limit-- <= 0) 1189 break; 1190 } while (val & (GREG_SWRST_TXRST | GREG_SWRST_RXRST)); 1191 1192 if (limit < 0) 1193 netdev_err(gp->dev, "SW reset is ghetto\n"); 1194 1195 if (gp->phy_type == phy_serialink || gp->phy_type == phy_serdes) 1196 gem_pcs_reinit_adv(gp); 1197 } 1198 1199 static void gem_start_dma(struct gem *gp) 1200 { 1201 u32 val; 1202 1203 /* We are ready to rock, turn everything on. */ 1204 val = readl(gp->regs + TXDMA_CFG); 1205 writel(val | TXDMA_CFG_ENABLE, gp->regs + TXDMA_CFG); 1206 val = readl(gp->regs + RXDMA_CFG); 1207 writel(val | RXDMA_CFG_ENABLE, gp->regs + RXDMA_CFG); 1208 val = readl(gp->regs + MAC_TXCFG); 1209 writel(val | MAC_TXCFG_ENAB, gp->regs + MAC_TXCFG); 1210 val = readl(gp->regs + MAC_RXCFG); 1211 writel(val | MAC_RXCFG_ENAB, gp->regs + MAC_RXCFG); 1212 1213 (void) readl(gp->regs + MAC_RXCFG); 1214 udelay(100); 1215 1216 gem_enable_ints(gp); 1217 1218 writel(RX_RING_SIZE - 4, gp->regs + RXDMA_KICK); 1219 } 1220 1221 /* DMA won't be actually stopped before about 4ms tho ... 1222 */ 1223 static void gem_stop_dma(struct gem *gp) 1224 { 1225 u32 val; 1226 1227 /* We are done rocking, turn everything off. */ 1228 val = readl(gp->regs + TXDMA_CFG); 1229 writel(val & ~TXDMA_CFG_ENABLE, gp->regs + TXDMA_CFG); 1230 val = readl(gp->regs + RXDMA_CFG); 1231 writel(val & ~RXDMA_CFG_ENABLE, gp->regs + RXDMA_CFG); 1232 val = readl(gp->regs + MAC_TXCFG); 1233 writel(val & ~MAC_TXCFG_ENAB, gp->regs + MAC_TXCFG); 1234 val = readl(gp->regs + MAC_RXCFG); 1235 writel(val & ~MAC_RXCFG_ENAB, gp->regs + MAC_RXCFG); 1236 1237 (void) readl(gp->regs + MAC_RXCFG); 1238 1239 /* Need to wait a bit ... done by the caller */ 1240 } 1241 1242 1243 // XXX dbl check what that function should do when called on PCS PHY 1244 static void gem_begin_auto_negotiation(struct gem *gp, 1245 const struct ethtool_link_ksettings *ep) 1246 { 1247 u32 advertise, features; 1248 int autoneg; 1249 int speed; 1250 int duplex; 1251 u32 advertising; 1252 1253 if (ep) 1254 ethtool_convert_link_mode_to_legacy_u32( 1255 &advertising, ep->link_modes.advertising); 1256 1257 if (gp->phy_type != phy_mii_mdio0 && 1258 gp->phy_type != phy_mii_mdio1) 1259 goto non_mii; 1260 1261 /* Setup advertise */ 1262 if (found_mii_phy(gp)) 1263 features = gp->phy_mii.def->features; 1264 else 1265 features = 0; 1266 1267 advertise = features & ADVERTISE_MASK; 1268 if (gp->phy_mii.advertising != 0) 1269 advertise &= gp->phy_mii.advertising; 1270 1271 autoneg = gp->want_autoneg; 1272 speed = gp->phy_mii.speed; 1273 duplex = gp->phy_mii.duplex; 1274 1275 /* Setup link parameters */ 1276 if (!ep) 1277 goto start_aneg; 1278 if (ep->base.autoneg == AUTONEG_ENABLE) { 1279 advertise = advertising; 1280 autoneg = 1; 1281 } else { 1282 autoneg = 0; 1283 speed = ep->base.speed; 1284 duplex = ep->base.duplex; 1285 } 1286 1287 start_aneg: 1288 /* Sanitize settings based on PHY capabilities */ 1289 if ((features & SUPPORTED_Autoneg) == 0) 1290 autoneg = 0; 1291 if (speed == SPEED_1000 && 1292 !(features & (SUPPORTED_1000baseT_Half | SUPPORTED_1000baseT_Full))) 1293 speed = SPEED_100; 1294 if (speed == SPEED_100 && 1295 !(features & (SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full))) 1296 speed = SPEED_10; 1297 if (duplex == DUPLEX_FULL && 1298 !(features & (SUPPORTED_1000baseT_Full | 1299 SUPPORTED_100baseT_Full | 1300 SUPPORTED_10baseT_Full))) 1301 duplex = DUPLEX_HALF; 1302 if (speed == 0) 1303 speed = SPEED_10; 1304 1305 /* If we are asleep, we don't try to actually setup the PHY, we 1306 * just store the settings 1307 */ 1308 if (!netif_device_present(gp->dev)) { 1309 gp->phy_mii.autoneg = gp->want_autoneg = autoneg; 1310 gp->phy_mii.speed = speed; 1311 gp->phy_mii.duplex = duplex; 1312 return; 1313 } 1314 1315 /* Configure PHY & start aneg */ 1316 gp->want_autoneg = autoneg; 1317 if (autoneg) { 1318 if (found_mii_phy(gp)) 1319 gp->phy_mii.def->ops->setup_aneg(&gp->phy_mii, advertise); 1320 gp->lstate = link_aneg; 1321 } else { 1322 if (found_mii_phy(gp)) 1323 gp->phy_mii.def->ops->setup_forced(&gp->phy_mii, speed, duplex); 1324 gp->lstate = link_force_ok; 1325 } 1326 1327 non_mii: 1328 gp->timer_ticks = 0; 1329 mod_timer(&gp->link_timer, jiffies + ((12 * HZ) / 10)); 1330 } 1331 1332 /* A link-up condition has occurred, initialize and enable the 1333 * rest of the chip. 1334 */ 1335 static int gem_set_link_modes(struct gem *gp) 1336 { 1337 struct netdev_queue *txq = netdev_get_tx_queue(gp->dev, 0); 1338 int full_duplex, speed, pause; 1339 u32 val; 1340 1341 full_duplex = 0; 1342 speed = SPEED_10; 1343 pause = 0; 1344 1345 if (found_mii_phy(gp)) { 1346 if (gp->phy_mii.def->ops->read_link(&gp->phy_mii)) 1347 return 1; 1348 full_duplex = (gp->phy_mii.duplex == DUPLEX_FULL); 1349 speed = gp->phy_mii.speed; 1350 pause = gp->phy_mii.pause; 1351 } else if (gp->phy_type == phy_serialink || 1352 gp->phy_type == phy_serdes) { 1353 u32 pcs_lpa = readl(gp->regs + PCS_MIILP); 1354 1355 if ((pcs_lpa & PCS_MIIADV_FD) || gp->phy_type == phy_serdes) 1356 full_duplex = 1; 1357 speed = SPEED_1000; 1358 } 1359 1360 netif_info(gp, link, gp->dev, "Link is up at %d Mbps, %s-duplex\n", 1361 speed, (full_duplex ? "full" : "half")); 1362 1363 1364 /* We take the tx queue lock to avoid collisions between 1365 * this code, the tx path and the NAPI-driven error path 1366 */ 1367 __netif_tx_lock(txq, smp_processor_id()); 1368 1369 val = (MAC_TXCFG_EIPG0 | MAC_TXCFG_NGU); 1370 if (full_duplex) { 1371 val |= (MAC_TXCFG_ICS | MAC_TXCFG_ICOLL); 1372 } else { 1373 /* MAC_TXCFG_NBO must be zero. */ 1374 } 1375 writel(val, gp->regs + MAC_TXCFG); 1376 1377 val = (MAC_XIFCFG_OE | MAC_XIFCFG_LLED); 1378 if (!full_duplex && 1379 (gp->phy_type == phy_mii_mdio0 || 1380 gp->phy_type == phy_mii_mdio1)) { 1381 val |= MAC_XIFCFG_DISE; 1382 } else if (full_duplex) { 1383 val |= MAC_XIFCFG_FLED; 1384 } 1385 1386 if (speed == SPEED_1000) 1387 val |= (MAC_XIFCFG_GMII); 1388 1389 writel(val, gp->regs + MAC_XIFCFG); 1390 1391 /* If gigabit and half-duplex, enable carrier extension 1392 * mode. Else, disable it. 1393 */ 1394 if (speed == SPEED_1000 && !full_duplex) { 1395 val = readl(gp->regs + MAC_TXCFG); 1396 writel(val | MAC_TXCFG_TCE, gp->regs + MAC_TXCFG); 1397 1398 val = readl(gp->regs + MAC_RXCFG); 1399 writel(val | MAC_RXCFG_RCE, gp->regs + MAC_RXCFG); 1400 } else { 1401 val = readl(gp->regs + MAC_TXCFG); 1402 writel(val & ~MAC_TXCFG_TCE, gp->regs + MAC_TXCFG); 1403 1404 val = readl(gp->regs + MAC_RXCFG); 1405 writel(val & ~MAC_RXCFG_RCE, gp->regs + MAC_RXCFG); 1406 } 1407 1408 if (gp->phy_type == phy_serialink || 1409 gp->phy_type == phy_serdes) { 1410 u32 pcs_lpa = readl(gp->regs + PCS_MIILP); 1411 1412 if (pcs_lpa & (PCS_MIIADV_SP | PCS_MIIADV_AP)) 1413 pause = 1; 1414 } 1415 1416 if (!full_duplex) 1417 writel(512, gp->regs + MAC_STIME); 1418 else 1419 writel(64, gp->regs + MAC_STIME); 1420 val = readl(gp->regs + MAC_MCCFG); 1421 if (pause) 1422 val |= (MAC_MCCFG_SPE | MAC_MCCFG_RPE); 1423 else 1424 val &= ~(MAC_MCCFG_SPE | MAC_MCCFG_RPE); 1425 writel(val, gp->regs + MAC_MCCFG); 1426 1427 gem_start_dma(gp); 1428 1429 __netif_tx_unlock(txq); 1430 1431 if (netif_msg_link(gp)) { 1432 if (pause) { 1433 netdev_info(gp->dev, 1434 "Pause is enabled (rxfifo: %d off: %d on: %d)\n", 1435 gp->rx_fifo_sz, 1436 gp->rx_pause_off, 1437 gp->rx_pause_on); 1438 } else { 1439 netdev_info(gp->dev, "Pause is disabled\n"); 1440 } 1441 } 1442 1443 return 0; 1444 } 1445 1446 static int gem_mdio_link_not_up(struct gem *gp) 1447 { 1448 switch (gp->lstate) { 1449 case link_force_ret: 1450 netif_info(gp, link, gp->dev, 1451 "Autoneg failed again, keeping forced mode\n"); 1452 gp->phy_mii.def->ops->setup_forced(&gp->phy_mii, 1453 gp->last_forced_speed, DUPLEX_HALF); 1454 gp->timer_ticks = 5; 1455 gp->lstate = link_force_ok; 1456 return 0; 1457 case link_aneg: 1458 /* We try forced modes after a failed aneg only on PHYs that don't 1459 * have "magic_aneg" bit set, which means they internally do the 1460 * while forced-mode thingy. On these, we just restart aneg 1461 */ 1462 if (gp->phy_mii.def->magic_aneg) 1463 return 1; 1464 netif_info(gp, link, gp->dev, "switching to forced 100bt\n"); 1465 /* Try forced modes. */ 1466 gp->phy_mii.def->ops->setup_forced(&gp->phy_mii, SPEED_100, 1467 DUPLEX_HALF); 1468 gp->timer_ticks = 5; 1469 gp->lstate = link_force_try; 1470 return 0; 1471 case link_force_try: 1472 /* Downgrade from 100 to 10 Mbps if necessary. 1473 * If already at 10Mbps, warn user about the 1474 * situation every 10 ticks. 1475 */ 1476 if (gp->phy_mii.speed == SPEED_100) { 1477 gp->phy_mii.def->ops->setup_forced(&gp->phy_mii, SPEED_10, 1478 DUPLEX_HALF); 1479 gp->timer_ticks = 5; 1480 netif_info(gp, link, gp->dev, 1481 "switching to forced 10bt\n"); 1482 return 0; 1483 } else 1484 return 1; 1485 default: 1486 return 0; 1487 } 1488 } 1489 1490 static void gem_link_timer(struct timer_list *t) 1491 { 1492 struct gem *gp = from_timer(gp, t, link_timer); 1493 struct net_device *dev = gp->dev; 1494 int restart_aneg = 0; 1495 1496 /* There's no point doing anything if we're going to be reset */ 1497 if (gp->reset_task_pending) 1498 return; 1499 1500 if (gp->phy_type == phy_serialink || 1501 gp->phy_type == phy_serdes) { 1502 u32 val = readl(gp->regs + PCS_MIISTAT); 1503 1504 if (!(val & PCS_MIISTAT_LS)) 1505 val = readl(gp->regs + PCS_MIISTAT); 1506 1507 if ((val & PCS_MIISTAT_LS) != 0) { 1508 if (gp->lstate == link_up) 1509 goto restart; 1510 1511 gp->lstate = link_up; 1512 netif_carrier_on(dev); 1513 (void)gem_set_link_modes(gp); 1514 } 1515 goto restart; 1516 } 1517 if (found_mii_phy(gp) && gp->phy_mii.def->ops->poll_link(&gp->phy_mii)) { 1518 /* Ok, here we got a link. If we had it due to a forced 1519 * fallback, and we were configured for autoneg, we do 1520 * retry a short autoneg pass. If you know your hub is 1521 * broken, use ethtool ;) 1522 */ 1523 if (gp->lstate == link_force_try && gp->want_autoneg) { 1524 gp->lstate = link_force_ret; 1525 gp->last_forced_speed = gp->phy_mii.speed; 1526 gp->timer_ticks = 5; 1527 if (netif_msg_link(gp)) 1528 netdev_info(dev, 1529 "Got link after fallback, retrying autoneg once...\n"); 1530 gp->phy_mii.def->ops->setup_aneg(&gp->phy_mii, gp->phy_mii.advertising); 1531 } else if (gp->lstate != link_up) { 1532 gp->lstate = link_up; 1533 netif_carrier_on(dev); 1534 if (gem_set_link_modes(gp)) 1535 restart_aneg = 1; 1536 } 1537 } else { 1538 /* If the link was previously up, we restart the 1539 * whole process 1540 */ 1541 if (gp->lstate == link_up) { 1542 gp->lstate = link_down; 1543 netif_info(gp, link, dev, "Link down\n"); 1544 netif_carrier_off(dev); 1545 gem_schedule_reset(gp); 1546 /* The reset task will restart the timer */ 1547 return; 1548 } else if (++gp->timer_ticks > 10) { 1549 if (found_mii_phy(gp)) 1550 restart_aneg = gem_mdio_link_not_up(gp); 1551 else 1552 restart_aneg = 1; 1553 } 1554 } 1555 if (restart_aneg) { 1556 gem_begin_auto_negotiation(gp, NULL); 1557 return; 1558 } 1559 restart: 1560 mod_timer(&gp->link_timer, jiffies + ((12 * HZ) / 10)); 1561 } 1562 1563 static void gem_clean_rings(struct gem *gp) 1564 { 1565 struct gem_init_block *gb = gp->init_block; 1566 struct sk_buff *skb; 1567 int i; 1568 dma_addr_t dma_addr; 1569 1570 for (i = 0; i < RX_RING_SIZE; i++) { 1571 struct gem_rxd *rxd; 1572 1573 rxd = &gb->rxd[i]; 1574 if (gp->rx_skbs[i] != NULL) { 1575 skb = gp->rx_skbs[i]; 1576 dma_addr = le64_to_cpu(rxd->buffer); 1577 pci_unmap_page(gp->pdev, dma_addr, 1578 RX_BUF_ALLOC_SIZE(gp), 1579 PCI_DMA_FROMDEVICE); 1580 dev_kfree_skb_any(skb); 1581 gp->rx_skbs[i] = NULL; 1582 } 1583 rxd->status_word = 0; 1584 dma_wmb(); 1585 rxd->buffer = 0; 1586 } 1587 1588 for (i = 0; i < TX_RING_SIZE; i++) { 1589 if (gp->tx_skbs[i] != NULL) { 1590 struct gem_txd *txd; 1591 int frag; 1592 1593 skb = gp->tx_skbs[i]; 1594 gp->tx_skbs[i] = NULL; 1595 1596 for (frag = 0; frag <= skb_shinfo(skb)->nr_frags; frag++) { 1597 int ent = i & (TX_RING_SIZE - 1); 1598 1599 txd = &gb->txd[ent]; 1600 dma_addr = le64_to_cpu(txd->buffer); 1601 pci_unmap_page(gp->pdev, dma_addr, 1602 le64_to_cpu(txd->control_word) & 1603 TXDCTRL_BUFSZ, PCI_DMA_TODEVICE); 1604 1605 if (frag != skb_shinfo(skb)->nr_frags) 1606 i++; 1607 } 1608 dev_kfree_skb_any(skb); 1609 } 1610 } 1611 } 1612 1613 static void gem_init_rings(struct gem *gp) 1614 { 1615 struct gem_init_block *gb = gp->init_block; 1616 struct net_device *dev = gp->dev; 1617 int i; 1618 dma_addr_t dma_addr; 1619 1620 gp->rx_new = gp->rx_old = gp->tx_new = gp->tx_old = 0; 1621 1622 gem_clean_rings(gp); 1623 1624 gp->rx_buf_sz = max(dev->mtu + ETH_HLEN + VLAN_HLEN, 1625 (unsigned)VLAN_ETH_FRAME_LEN); 1626 1627 for (i = 0; i < RX_RING_SIZE; i++) { 1628 struct sk_buff *skb; 1629 struct gem_rxd *rxd = &gb->rxd[i]; 1630 1631 skb = gem_alloc_skb(dev, RX_BUF_ALLOC_SIZE(gp), GFP_KERNEL); 1632 if (!skb) { 1633 rxd->buffer = 0; 1634 rxd->status_word = 0; 1635 continue; 1636 } 1637 1638 gp->rx_skbs[i] = skb; 1639 skb_put(skb, (gp->rx_buf_sz + RX_OFFSET)); 1640 dma_addr = pci_map_page(gp->pdev, 1641 virt_to_page(skb->data), 1642 offset_in_page(skb->data), 1643 RX_BUF_ALLOC_SIZE(gp), 1644 PCI_DMA_FROMDEVICE); 1645 rxd->buffer = cpu_to_le64(dma_addr); 1646 dma_wmb(); 1647 rxd->status_word = cpu_to_le64(RXDCTRL_FRESH(gp)); 1648 skb_reserve(skb, RX_OFFSET); 1649 } 1650 1651 for (i = 0; i < TX_RING_SIZE; i++) { 1652 struct gem_txd *txd = &gb->txd[i]; 1653 1654 txd->control_word = 0; 1655 dma_wmb(); 1656 txd->buffer = 0; 1657 } 1658 wmb(); 1659 } 1660 1661 /* Init PHY interface and start link poll state machine */ 1662 static void gem_init_phy(struct gem *gp) 1663 { 1664 u32 mifcfg; 1665 1666 /* Revert MIF CFG setting done on stop_phy */ 1667 mifcfg = readl(gp->regs + MIF_CFG); 1668 mifcfg &= ~MIF_CFG_BBMODE; 1669 writel(mifcfg, gp->regs + MIF_CFG); 1670 1671 if (gp->pdev->vendor == PCI_VENDOR_ID_APPLE) { 1672 int i; 1673 1674 /* Those delay sucks, the HW seem to love them though, I'll 1675 * serisouly consider breaking some locks here to be able 1676 * to schedule instead 1677 */ 1678 for (i = 0; i < 3; i++) { 1679 #ifdef CONFIG_PPC_PMAC 1680 pmac_call_feature(PMAC_FTR_GMAC_PHY_RESET, gp->of_node, 0, 0); 1681 msleep(20); 1682 #endif 1683 /* Some PHYs used by apple have problem getting back to us, 1684 * we do an additional reset here 1685 */ 1686 sungem_phy_write(gp, MII_BMCR, BMCR_RESET); 1687 msleep(20); 1688 if (sungem_phy_read(gp, MII_BMCR) != 0xffff) 1689 break; 1690 if (i == 2) 1691 netdev_warn(gp->dev, "GMAC PHY not responding !\n"); 1692 } 1693 } 1694 1695 if (gp->pdev->vendor == PCI_VENDOR_ID_SUN && 1696 gp->pdev->device == PCI_DEVICE_ID_SUN_GEM) { 1697 u32 val; 1698 1699 /* Init datapath mode register. */ 1700 if (gp->phy_type == phy_mii_mdio0 || 1701 gp->phy_type == phy_mii_mdio1) { 1702 val = PCS_DMODE_MGM; 1703 } else if (gp->phy_type == phy_serialink) { 1704 val = PCS_DMODE_SM | PCS_DMODE_GMOE; 1705 } else { 1706 val = PCS_DMODE_ESM; 1707 } 1708 1709 writel(val, gp->regs + PCS_DMODE); 1710 } 1711 1712 if (gp->phy_type == phy_mii_mdio0 || 1713 gp->phy_type == phy_mii_mdio1) { 1714 /* Reset and detect MII PHY */ 1715 sungem_phy_probe(&gp->phy_mii, gp->mii_phy_addr); 1716 1717 /* Init PHY */ 1718 if (gp->phy_mii.def && gp->phy_mii.def->ops->init) 1719 gp->phy_mii.def->ops->init(&gp->phy_mii); 1720 } else { 1721 gem_pcs_reset(gp); 1722 gem_pcs_reinit_adv(gp); 1723 } 1724 1725 /* Default aneg parameters */ 1726 gp->timer_ticks = 0; 1727 gp->lstate = link_down; 1728 netif_carrier_off(gp->dev); 1729 1730 /* Print things out */ 1731 if (gp->phy_type == phy_mii_mdio0 || 1732 gp->phy_type == phy_mii_mdio1) 1733 netdev_info(gp->dev, "Found %s PHY\n", 1734 gp->phy_mii.def ? gp->phy_mii.def->name : "no"); 1735 1736 gem_begin_auto_negotiation(gp, NULL); 1737 } 1738 1739 static void gem_init_dma(struct gem *gp) 1740 { 1741 u64 desc_dma = (u64) gp->gblock_dvma; 1742 u32 val; 1743 1744 val = (TXDMA_CFG_BASE | (0x7ff << 10) | TXDMA_CFG_PMODE); 1745 writel(val, gp->regs + TXDMA_CFG); 1746 1747 writel(desc_dma >> 32, gp->regs + TXDMA_DBHI); 1748 writel(desc_dma & 0xffffffff, gp->regs + TXDMA_DBLOW); 1749 desc_dma += (INIT_BLOCK_TX_RING_SIZE * sizeof(struct gem_txd)); 1750 1751 writel(0, gp->regs + TXDMA_KICK); 1752 1753 val = (RXDMA_CFG_BASE | (RX_OFFSET << 10) | 1754 (ETH_HLEN << 13) | RXDMA_CFG_FTHRESH_128); 1755 writel(val, gp->regs + RXDMA_CFG); 1756 1757 writel(desc_dma >> 32, gp->regs + RXDMA_DBHI); 1758 writel(desc_dma & 0xffffffff, gp->regs + RXDMA_DBLOW); 1759 1760 writel(RX_RING_SIZE - 4, gp->regs + RXDMA_KICK); 1761 1762 val = (((gp->rx_pause_off / 64) << 0) & RXDMA_PTHRESH_OFF); 1763 val |= (((gp->rx_pause_on / 64) << 12) & RXDMA_PTHRESH_ON); 1764 writel(val, gp->regs + RXDMA_PTHRESH); 1765 1766 if (readl(gp->regs + GREG_BIFCFG) & GREG_BIFCFG_M66EN) 1767 writel(((5 & RXDMA_BLANK_IPKTS) | 1768 ((8 << 12) & RXDMA_BLANK_ITIME)), 1769 gp->regs + RXDMA_BLANK); 1770 else 1771 writel(((5 & RXDMA_BLANK_IPKTS) | 1772 ((4 << 12) & RXDMA_BLANK_ITIME)), 1773 gp->regs + RXDMA_BLANK); 1774 } 1775 1776 static u32 gem_setup_multicast(struct gem *gp) 1777 { 1778 u32 rxcfg = 0; 1779 int i; 1780 1781 if ((gp->dev->flags & IFF_ALLMULTI) || 1782 (netdev_mc_count(gp->dev) > 256)) { 1783 for (i=0; i<16; i++) 1784 writel(0xffff, gp->regs + MAC_HASH0 + (i << 2)); 1785 rxcfg |= MAC_RXCFG_HFE; 1786 } else if (gp->dev->flags & IFF_PROMISC) { 1787 rxcfg |= MAC_RXCFG_PROM; 1788 } else { 1789 u16 hash_table[16]; 1790 u32 crc; 1791 struct netdev_hw_addr *ha; 1792 int i; 1793 1794 memset(hash_table, 0, sizeof(hash_table)); 1795 netdev_for_each_mc_addr(ha, gp->dev) { 1796 crc = ether_crc_le(6, ha->addr); 1797 crc >>= 24; 1798 hash_table[crc >> 4] |= 1 << (15 - (crc & 0xf)); 1799 } 1800 for (i=0; i<16; i++) 1801 writel(hash_table[i], gp->regs + MAC_HASH0 + (i << 2)); 1802 rxcfg |= MAC_RXCFG_HFE; 1803 } 1804 1805 return rxcfg; 1806 } 1807 1808 static void gem_init_mac(struct gem *gp) 1809 { 1810 unsigned char *e = &gp->dev->dev_addr[0]; 1811 1812 writel(0x1bf0, gp->regs + MAC_SNDPAUSE); 1813 1814 writel(0x00, gp->regs + MAC_IPG0); 1815 writel(0x08, gp->regs + MAC_IPG1); 1816 writel(0x04, gp->regs + MAC_IPG2); 1817 writel(0x40, gp->regs + MAC_STIME); 1818 writel(0x40, gp->regs + MAC_MINFSZ); 1819 1820 /* Ethernet payload + header + FCS + optional VLAN tag. */ 1821 writel(0x20000000 | (gp->rx_buf_sz + 4), gp->regs + MAC_MAXFSZ); 1822 1823 writel(0x07, gp->regs + MAC_PASIZE); 1824 writel(0x04, gp->regs + MAC_JAMSIZE); 1825 writel(0x10, gp->regs + MAC_ATTLIM); 1826 writel(0x8808, gp->regs + MAC_MCTYPE); 1827 1828 writel((e[5] | (e[4] << 8)) & 0x3ff, gp->regs + MAC_RANDSEED); 1829 1830 writel((e[4] << 8) | e[5], gp->regs + MAC_ADDR0); 1831 writel((e[2] << 8) | e[3], gp->regs + MAC_ADDR1); 1832 writel((e[0] << 8) | e[1], gp->regs + MAC_ADDR2); 1833 1834 writel(0, gp->regs + MAC_ADDR3); 1835 writel(0, gp->regs + MAC_ADDR4); 1836 writel(0, gp->regs + MAC_ADDR5); 1837 1838 writel(0x0001, gp->regs + MAC_ADDR6); 1839 writel(0xc200, gp->regs + MAC_ADDR7); 1840 writel(0x0180, gp->regs + MAC_ADDR8); 1841 1842 writel(0, gp->regs + MAC_AFILT0); 1843 writel(0, gp->regs + MAC_AFILT1); 1844 writel(0, gp->regs + MAC_AFILT2); 1845 writel(0, gp->regs + MAC_AF21MSK); 1846 writel(0, gp->regs + MAC_AF0MSK); 1847 1848 gp->mac_rx_cfg = gem_setup_multicast(gp); 1849 #ifdef STRIP_FCS 1850 gp->mac_rx_cfg |= MAC_RXCFG_SFCS; 1851 #endif 1852 writel(0, gp->regs + MAC_NCOLL); 1853 writel(0, gp->regs + MAC_FASUCC); 1854 writel(0, gp->regs + MAC_ECOLL); 1855 writel(0, gp->regs + MAC_LCOLL); 1856 writel(0, gp->regs + MAC_DTIMER); 1857 writel(0, gp->regs + MAC_PATMPS); 1858 writel(0, gp->regs + MAC_RFCTR); 1859 writel(0, gp->regs + MAC_LERR); 1860 writel(0, gp->regs + MAC_AERR); 1861 writel(0, gp->regs + MAC_FCSERR); 1862 writel(0, gp->regs + MAC_RXCVERR); 1863 1864 /* Clear RX/TX/MAC/XIF config, we will set these up and enable 1865 * them once a link is established. 1866 */ 1867 writel(0, gp->regs + MAC_TXCFG); 1868 writel(gp->mac_rx_cfg, gp->regs + MAC_RXCFG); 1869 writel(0, gp->regs + MAC_MCCFG); 1870 writel(0, gp->regs + MAC_XIFCFG); 1871 1872 /* Setup MAC interrupts. We want to get all of the interesting 1873 * counter expiration events, but we do not want to hear about 1874 * normal rx/tx as the DMA engine tells us that. 1875 */ 1876 writel(MAC_TXSTAT_XMIT, gp->regs + MAC_TXMASK); 1877 writel(MAC_RXSTAT_RCV, gp->regs + MAC_RXMASK); 1878 1879 /* Don't enable even the PAUSE interrupts for now, we 1880 * make no use of those events other than to record them. 1881 */ 1882 writel(0xffffffff, gp->regs + MAC_MCMASK); 1883 1884 /* Don't enable GEM's WOL in normal operations 1885 */ 1886 if (gp->has_wol) 1887 writel(0, gp->regs + WOL_WAKECSR); 1888 } 1889 1890 static void gem_init_pause_thresholds(struct gem *gp) 1891 { 1892 u32 cfg; 1893 1894 /* Calculate pause thresholds. Setting the OFF threshold to the 1895 * full RX fifo size effectively disables PAUSE generation which 1896 * is what we do for 10/100 only GEMs which have FIFOs too small 1897 * to make real gains from PAUSE. 1898 */ 1899 if (gp->rx_fifo_sz <= (2 * 1024)) { 1900 gp->rx_pause_off = gp->rx_pause_on = gp->rx_fifo_sz; 1901 } else { 1902 int max_frame = (gp->rx_buf_sz + 4 + 64) & ~63; 1903 int off = (gp->rx_fifo_sz - (max_frame * 2)); 1904 int on = off - max_frame; 1905 1906 gp->rx_pause_off = off; 1907 gp->rx_pause_on = on; 1908 } 1909 1910 1911 /* Configure the chip "burst" DMA mode & enable some 1912 * HW bug fixes on Apple version 1913 */ 1914 cfg = 0; 1915 if (gp->pdev->vendor == PCI_VENDOR_ID_APPLE) 1916 cfg |= GREG_CFG_RONPAULBIT | GREG_CFG_ENBUG2FIX; 1917 #if !defined(CONFIG_SPARC64) && !defined(CONFIG_ALPHA) 1918 cfg |= GREG_CFG_IBURST; 1919 #endif 1920 cfg |= ((31 << 1) & GREG_CFG_TXDMALIM); 1921 cfg |= ((31 << 6) & GREG_CFG_RXDMALIM); 1922 writel(cfg, gp->regs + GREG_CFG); 1923 1924 /* If Infinite Burst didn't stick, then use different 1925 * thresholds (and Apple bug fixes don't exist) 1926 */ 1927 if (!(readl(gp->regs + GREG_CFG) & GREG_CFG_IBURST)) { 1928 cfg = ((2 << 1) & GREG_CFG_TXDMALIM); 1929 cfg |= ((8 << 6) & GREG_CFG_RXDMALIM); 1930 writel(cfg, gp->regs + GREG_CFG); 1931 } 1932 } 1933 1934 static int gem_check_invariants(struct gem *gp) 1935 { 1936 struct pci_dev *pdev = gp->pdev; 1937 u32 mif_cfg; 1938 1939 /* On Apple's sungem, we can't rely on registers as the chip 1940 * was been powered down by the firmware. The PHY is looked 1941 * up later on. 1942 */ 1943 if (pdev->vendor == PCI_VENDOR_ID_APPLE) { 1944 gp->phy_type = phy_mii_mdio0; 1945 gp->tx_fifo_sz = readl(gp->regs + TXDMA_FSZ) * 64; 1946 gp->rx_fifo_sz = readl(gp->regs + RXDMA_FSZ) * 64; 1947 gp->swrst_base = 0; 1948 1949 mif_cfg = readl(gp->regs + MIF_CFG); 1950 mif_cfg &= ~(MIF_CFG_PSELECT|MIF_CFG_POLL|MIF_CFG_BBMODE|MIF_CFG_MDI1); 1951 mif_cfg |= MIF_CFG_MDI0; 1952 writel(mif_cfg, gp->regs + MIF_CFG); 1953 writel(PCS_DMODE_MGM, gp->regs + PCS_DMODE); 1954 writel(MAC_XIFCFG_OE, gp->regs + MAC_XIFCFG); 1955 1956 /* We hard-code the PHY address so we can properly bring it out of 1957 * reset later on, we can't really probe it at this point, though 1958 * that isn't an issue. 1959 */ 1960 if (gp->pdev->device == PCI_DEVICE_ID_APPLE_K2_GMAC) 1961 gp->mii_phy_addr = 1; 1962 else 1963 gp->mii_phy_addr = 0; 1964 1965 return 0; 1966 } 1967 1968 mif_cfg = readl(gp->regs + MIF_CFG); 1969 1970 if (pdev->vendor == PCI_VENDOR_ID_SUN && 1971 pdev->device == PCI_DEVICE_ID_SUN_RIO_GEM) { 1972 /* One of the MII PHYs _must_ be present 1973 * as this chip has no gigabit PHY. 1974 */ 1975 if ((mif_cfg & (MIF_CFG_MDI0 | MIF_CFG_MDI1)) == 0) { 1976 pr_err("RIO GEM lacks MII phy, mif_cfg[%08x]\n", 1977 mif_cfg); 1978 return -1; 1979 } 1980 } 1981 1982 /* Determine initial PHY interface type guess. MDIO1 is the 1983 * external PHY and thus takes precedence over MDIO0. 1984 */ 1985 1986 if (mif_cfg & MIF_CFG_MDI1) { 1987 gp->phy_type = phy_mii_mdio1; 1988 mif_cfg |= MIF_CFG_PSELECT; 1989 writel(mif_cfg, gp->regs + MIF_CFG); 1990 } else if (mif_cfg & MIF_CFG_MDI0) { 1991 gp->phy_type = phy_mii_mdio0; 1992 mif_cfg &= ~MIF_CFG_PSELECT; 1993 writel(mif_cfg, gp->regs + MIF_CFG); 1994 } else { 1995 #ifdef CONFIG_SPARC 1996 const char *p; 1997 1998 p = of_get_property(gp->of_node, "shared-pins", NULL); 1999 if (p && !strcmp(p, "serdes")) 2000 gp->phy_type = phy_serdes; 2001 else 2002 #endif 2003 gp->phy_type = phy_serialink; 2004 } 2005 if (gp->phy_type == phy_mii_mdio1 || 2006 gp->phy_type == phy_mii_mdio0) { 2007 int i; 2008 2009 for (i = 0; i < 32; i++) { 2010 gp->mii_phy_addr = i; 2011 if (sungem_phy_read(gp, MII_BMCR) != 0xffff) 2012 break; 2013 } 2014 if (i == 32) { 2015 if (pdev->device != PCI_DEVICE_ID_SUN_GEM) { 2016 pr_err("RIO MII phy will not respond\n"); 2017 return -1; 2018 } 2019 gp->phy_type = phy_serdes; 2020 } 2021 } 2022 2023 /* Fetch the FIFO configurations now too. */ 2024 gp->tx_fifo_sz = readl(gp->regs + TXDMA_FSZ) * 64; 2025 gp->rx_fifo_sz = readl(gp->regs + RXDMA_FSZ) * 64; 2026 2027 if (pdev->vendor == PCI_VENDOR_ID_SUN) { 2028 if (pdev->device == PCI_DEVICE_ID_SUN_GEM) { 2029 if (gp->tx_fifo_sz != (9 * 1024) || 2030 gp->rx_fifo_sz != (20 * 1024)) { 2031 pr_err("GEM has bogus fifo sizes tx(%d) rx(%d)\n", 2032 gp->tx_fifo_sz, gp->rx_fifo_sz); 2033 return -1; 2034 } 2035 gp->swrst_base = 0; 2036 } else { 2037 if (gp->tx_fifo_sz != (2 * 1024) || 2038 gp->rx_fifo_sz != (2 * 1024)) { 2039 pr_err("RIO GEM has bogus fifo sizes tx(%d) rx(%d)\n", 2040 gp->tx_fifo_sz, gp->rx_fifo_sz); 2041 return -1; 2042 } 2043 gp->swrst_base = (64 / 4) << GREG_SWRST_CACHE_SHIFT; 2044 } 2045 } 2046 2047 return 0; 2048 } 2049 2050 static void gem_reinit_chip(struct gem *gp) 2051 { 2052 /* Reset the chip */ 2053 gem_reset(gp); 2054 2055 /* Make sure ints are disabled */ 2056 gem_disable_ints(gp); 2057 2058 /* Allocate & setup ring buffers */ 2059 gem_init_rings(gp); 2060 2061 /* Configure pause thresholds */ 2062 gem_init_pause_thresholds(gp); 2063 2064 /* Init DMA & MAC engines */ 2065 gem_init_dma(gp); 2066 gem_init_mac(gp); 2067 } 2068 2069 2070 static void gem_stop_phy(struct gem *gp, int wol) 2071 { 2072 u32 mifcfg; 2073 2074 /* Let the chip settle down a bit, it seems that helps 2075 * for sleep mode on some models 2076 */ 2077 msleep(10); 2078 2079 /* Make sure we aren't polling PHY status change. We 2080 * don't currently use that feature though 2081 */ 2082 mifcfg = readl(gp->regs + MIF_CFG); 2083 mifcfg &= ~MIF_CFG_POLL; 2084 writel(mifcfg, gp->regs + MIF_CFG); 2085 2086 if (wol && gp->has_wol) { 2087 unsigned char *e = &gp->dev->dev_addr[0]; 2088 u32 csr; 2089 2090 /* Setup wake-on-lan for MAGIC packet */ 2091 writel(MAC_RXCFG_HFE | MAC_RXCFG_SFCS | MAC_RXCFG_ENAB, 2092 gp->regs + MAC_RXCFG); 2093 writel((e[4] << 8) | e[5], gp->regs + WOL_MATCH0); 2094 writel((e[2] << 8) | e[3], gp->regs + WOL_MATCH1); 2095 writel((e[0] << 8) | e[1], gp->regs + WOL_MATCH2); 2096 2097 writel(WOL_MCOUNT_N | WOL_MCOUNT_M, gp->regs + WOL_MCOUNT); 2098 csr = WOL_WAKECSR_ENABLE; 2099 if ((readl(gp->regs + MAC_XIFCFG) & MAC_XIFCFG_GMII) == 0) 2100 csr |= WOL_WAKECSR_MII; 2101 writel(csr, gp->regs + WOL_WAKECSR); 2102 } else { 2103 writel(0, gp->regs + MAC_RXCFG); 2104 (void)readl(gp->regs + MAC_RXCFG); 2105 /* Machine sleep will die in strange ways if we 2106 * dont wait a bit here, looks like the chip takes 2107 * some time to really shut down 2108 */ 2109 msleep(10); 2110 } 2111 2112 writel(0, gp->regs + MAC_TXCFG); 2113 writel(0, gp->regs + MAC_XIFCFG); 2114 writel(0, gp->regs + TXDMA_CFG); 2115 writel(0, gp->regs + RXDMA_CFG); 2116 2117 if (!wol) { 2118 gem_reset(gp); 2119 writel(MAC_TXRST_CMD, gp->regs + MAC_TXRST); 2120 writel(MAC_RXRST_CMD, gp->regs + MAC_RXRST); 2121 2122 if (found_mii_phy(gp) && gp->phy_mii.def->ops->suspend) 2123 gp->phy_mii.def->ops->suspend(&gp->phy_mii); 2124 2125 /* According to Apple, we must set the MDIO pins to this begnign 2126 * state or we may 1) eat more current, 2) damage some PHYs 2127 */ 2128 writel(mifcfg | MIF_CFG_BBMODE, gp->regs + MIF_CFG); 2129 writel(0, gp->regs + MIF_BBCLK); 2130 writel(0, gp->regs + MIF_BBDATA); 2131 writel(0, gp->regs + MIF_BBOENAB); 2132 writel(MAC_XIFCFG_GMII | MAC_XIFCFG_LBCK, gp->regs + MAC_XIFCFG); 2133 (void) readl(gp->regs + MAC_XIFCFG); 2134 } 2135 } 2136 2137 static int gem_do_start(struct net_device *dev) 2138 { 2139 struct gem *gp = netdev_priv(dev); 2140 int rc; 2141 2142 pci_set_master(gp->pdev); 2143 2144 /* Init & setup chip hardware */ 2145 gem_reinit_chip(gp); 2146 2147 /* An interrupt might come in handy */ 2148 rc = request_irq(gp->pdev->irq, gem_interrupt, 2149 IRQF_SHARED, dev->name, (void *)dev); 2150 if (rc) { 2151 netdev_err(dev, "failed to request irq !\n"); 2152 2153 gem_reset(gp); 2154 gem_clean_rings(gp); 2155 gem_put_cell(gp); 2156 return rc; 2157 } 2158 2159 /* Mark us as attached again if we come from resume(), this has 2160 * no effect if we weren't detached and needs to be done now. 2161 */ 2162 netif_device_attach(dev); 2163 2164 /* Restart NAPI & queues */ 2165 gem_netif_start(gp); 2166 2167 /* Detect & init PHY, start autoneg etc... this will 2168 * eventually result in starting DMA operations when 2169 * the link is up 2170 */ 2171 gem_init_phy(gp); 2172 2173 return 0; 2174 } 2175 2176 static void gem_do_stop(struct net_device *dev, int wol) 2177 { 2178 struct gem *gp = netdev_priv(dev); 2179 2180 /* Stop NAPI and stop tx queue */ 2181 gem_netif_stop(gp); 2182 2183 /* Make sure ints are disabled. We don't care about 2184 * synchronizing as NAPI is disabled, thus a stray 2185 * interrupt will do nothing bad (our irq handler 2186 * just schedules NAPI) 2187 */ 2188 gem_disable_ints(gp); 2189 2190 /* Stop the link timer */ 2191 del_timer_sync(&gp->link_timer); 2192 2193 /* We cannot cancel the reset task while holding the 2194 * rtnl lock, we'd get an A->B / B->A deadlock stituation 2195 * if we did. This is not an issue however as the reset 2196 * task is synchronized vs. us (rtnl_lock) and will do 2197 * nothing if the device is down or suspended. We do 2198 * still clear reset_task_pending to avoid a spurrious 2199 * reset later on in case we do resume before it gets 2200 * scheduled. 2201 */ 2202 gp->reset_task_pending = 0; 2203 2204 /* If we are going to sleep with WOL */ 2205 gem_stop_dma(gp); 2206 msleep(10); 2207 if (!wol) 2208 gem_reset(gp); 2209 msleep(10); 2210 2211 /* Get rid of rings */ 2212 gem_clean_rings(gp); 2213 2214 /* No irq needed anymore */ 2215 free_irq(gp->pdev->irq, (void *) dev); 2216 2217 /* Shut the PHY down eventually and setup WOL */ 2218 gem_stop_phy(gp, wol); 2219 } 2220 2221 static void gem_reset_task(struct work_struct *work) 2222 { 2223 struct gem *gp = container_of(work, struct gem, reset_task); 2224 2225 /* Lock out the network stack (essentially shield ourselves 2226 * against a racing open, close, control call, or suspend 2227 */ 2228 rtnl_lock(); 2229 2230 /* Skip the reset task if suspended or closed, or if it's 2231 * been cancelled by gem_do_stop (see comment there) 2232 */ 2233 if (!netif_device_present(gp->dev) || 2234 !netif_running(gp->dev) || 2235 !gp->reset_task_pending) { 2236 rtnl_unlock(); 2237 return; 2238 } 2239 2240 /* Stop the link timer */ 2241 del_timer_sync(&gp->link_timer); 2242 2243 /* Stop NAPI and tx */ 2244 gem_netif_stop(gp); 2245 2246 /* Reset the chip & rings */ 2247 gem_reinit_chip(gp); 2248 if (gp->lstate == link_up) 2249 gem_set_link_modes(gp); 2250 2251 /* Restart NAPI and Tx */ 2252 gem_netif_start(gp); 2253 2254 /* We are back ! */ 2255 gp->reset_task_pending = 0; 2256 2257 /* If the link is not up, restart autoneg, else restart the 2258 * polling timer 2259 */ 2260 if (gp->lstate != link_up) 2261 gem_begin_auto_negotiation(gp, NULL); 2262 else 2263 mod_timer(&gp->link_timer, jiffies + ((12 * HZ) / 10)); 2264 2265 rtnl_unlock(); 2266 } 2267 2268 static int gem_open(struct net_device *dev) 2269 { 2270 struct gem *gp = netdev_priv(dev); 2271 int rc; 2272 2273 /* We allow open while suspended, we just do nothing, 2274 * the chip will be initialized in resume() 2275 */ 2276 if (netif_device_present(dev)) { 2277 /* Enable the cell */ 2278 gem_get_cell(gp); 2279 2280 /* Make sure PCI access and bus master are enabled */ 2281 rc = pci_enable_device(gp->pdev); 2282 if (rc) { 2283 netdev_err(dev, "Failed to enable chip on PCI bus !\n"); 2284 2285 /* Put cell and forget it for now, it will be considered 2286 *as still asleep, a new sleep cycle may bring it back 2287 */ 2288 gem_put_cell(gp); 2289 return -ENXIO; 2290 } 2291 return gem_do_start(dev); 2292 } 2293 2294 return 0; 2295 } 2296 2297 static int gem_close(struct net_device *dev) 2298 { 2299 struct gem *gp = netdev_priv(dev); 2300 2301 if (netif_device_present(dev)) { 2302 gem_do_stop(dev, 0); 2303 2304 /* Make sure bus master is disabled */ 2305 pci_disable_device(gp->pdev); 2306 2307 /* Cell not needed neither if no WOL */ 2308 if (!gp->asleep_wol) 2309 gem_put_cell(gp); 2310 } 2311 return 0; 2312 } 2313 2314 static int __maybe_unused gem_suspend(struct device *dev_d) 2315 { 2316 struct net_device *dev = dev_get_drvdata(dev_d); 2317 struct gem *gp = netdev_priv(dev); 2318 2319 /* Lock the network stack first to avoid racing with open/close, 2320 * reset task and setting calls 2321 */ 2322 rtnl_lock(); 2323 2324 /* Not running, mark ourselves non-present, no need for 2325 * a lock here 2326 */ 2327 if (!netif_running(dev)) { 2328 netif_device_detach(dev); 2329 rtnl_unlock(); 2330 return 0; 2331 } 2332 netdev_info(dev, "suspending, WakeOnLan %s\n", 2333 (gp->wake_on_lan && netif_running(dev)) ? 2334 "enabled" : "disabled"); 2335 2336 /* Tell the network stack we're gone. gem_do_stop() below will 2337 * synchronize with TX, stop NAPI etc... 2338 */ 2339 netif_device_detach(dev); 2340 2341 /* Switch off chip, remember WOL setting */ 2342 gp->asleep_wol = !!gp->wake_on_lan; 2343 gem_do_stop(dev, gp->asleep_wol); 2344 2345 /* Cell not needed neither if no WOL */ 2346 if (!gp->asleep_wol) 2347 gem_put_cell(gp); 2348 2349 /* Unlock the network stack */ 2350 rtnl_unlock(); 2351 2352 return 0; 2353 } 2354 2355 static int __maybe_unused gem_resume(struct device *dev_d) 2356 { 2357 struct net_device *dev = dev_get_drvdata(dev_d); 2358 struct gem *gp = netdev_priv(dev); 2359 2360 /* See locking comment in gem_suspend */ 2361 rtnl_lock(); 2362 2363 /* Not running, mark ourselves present, no need for 2364 * a lock here 2365 */ 2366 if (!netif_running(dev)) { 2367 netif_device_attach(dev); 2368 rtnl_unlock(); 2369 return 0; 2370 } 2371 2372 /* Enable the cell */ 2373 gem_get_cell(gp); 2374 2375 /* Restart chip. If that fails there isn't much we can do, we 2376 * leave things stopped. 2377 */ 2378 gem_do_start(dev); 2379 2380 /* If we had WOL enabled, the cell clock was never turned off during 2381 * sleep, so we end up beeing unbalanced. Fix that here 2382 */ 2383 if (gp->asleep_wol) 2384 gem_put_cell(gp); 2385 2386 /* Unlock the network stack */ 2387 rtnl_unlock(); 2388 2389 return 0; 2390 } 2391 2392 static struct net_device_stats *gem_get_stats(struct net_device *dev) 2393 { 2394 struct gem *gp = netdev_priv(dev); 2395 2396 /* I have seen this being called while the PM was in progress, 2397 * so we shield against this. Let's also not poke at registers 2398 * while the reset task is going on. 2399 * 2400 * TODO: Move stats collection elsewhere (link timer ?) and 2401 * make this a nop to avoid all those synchro issues 2402 */ 2403 if (!netif_device_present(dev) || !netif_running(dev)) 2404 goto bail; 2405 2406 /* Better safe than sorry... */ 2407 if (WARN_ON(!gp->cell_enabled)) 2408 goto bail; 2409 2410 dev->stats.rx_crc_errors += readl(gp->regs + MAC_FCSERR); 2411 writel(0, gp->regs + MAC_FCSERR); 2412 2413 dev->stats.rx_frame_errors += readl(gp->regs + MAC_AERR); 2414 writel(0, gp->regs + MAC_AERR); 2415 2416 dev->stats.rx_length_errors += readl(gp->regs + MAC_LERR); 2417 writel(0, gp->regs + MAC_LERR); 2418 2419 dev->stats.tx_aborted_errors += readl(gp->regs + MAC_ECOLL); 2420 dev->stats.collisions += 2421 (readl(gp->regs + MAC_ECOLL) + readl(gp->regs + MAC_LCOLL)); 2422 writel(0, gp->regs + MAC_ECOLL); 2423 writel(0, gp->regs + MAC_LCOLL); 2424 bail: 2425 return &dev->stats; 2426 } 2427 2428 static int gem_set_mac_address(struct net_device *dev, void *addr) 2429 { 2430 struct sockaddr *macaddr = (struct sockaddr *) addr; 2431 struct gem *gp = netdev_priv(dev); 2432 unsigned char *e = &dev->dev_addr[0]; 2433 2434 if (!is_valid_ether_addr(macaddr->sa_data)) 2435 return -EADDRNOTAVAIL; 2436 2437 memcpy(dev->dev_addr, macaddr->sa_data, dev->addr_len); 2438 2439 /* We'll just catch it later when the device is up'd or resumed */ 2440 if (!netif_running(dev) || !netif_device_present(dev)) 2441 return 0; 2442 2443 /* Better safe than sorry... */ 2444 if (WARN_ON(!gp->cell_enabled)) 2445 return 0; 2446 2447 writel((e[4] << 8) | e[5], gp->regs + MAC_ADDR0); 2448 writel((e[2] << 8) | e[3], gp->regs + MAC_ADDR1); 2449 writel((e[0] << 8) | e[1], gp->regs + MAC_ADDR2); 2450 2451 return 0; 2452 } 2453 2454 static void gem_set_multicast(struct net_device *dev) 2455 { 2456 struct gem *gp = netdev_priv(dev); 2457 u32 rxcfg, rxcfg_new; 2458 int limit = 10000; 2459 2460 if (!netif_running(dev) || !netif_device_present(dev)) 2461 return; 2462 2463 /* Better safe than sorry... */ 2464 if (gp->reset_task_pending || WARN_ON(!gp->cell_enabled)) 2465 return; 2466 2467 rxcfg = readl(gp->regs + MAC_RXCFG); 2468 rxcfg_new = gem_setup_multicast(gp); 2469 #ifdef STRIP_FCS 2470 rxcfg_new |= MAC_RXCFG_SFCS; 2471 #endif 2472 gp->mac_rx_cfg = rxcfg_new; 2473 2474 writel(rxcfg & ~MAC_RXCFG_ENAB, gp->regs + MAC_RXCFG); 2475 while (readl(gp->regs + MAC_RXCFG) & MAC_RXCFG_ENAB) { 2476 if (!limit--) 2477 break; 2478 udelay(10); 2479 } 2480 2481 rxcfg &= ~(MAC_RXCFG_PROM | MAC_RXCFG_HFE); 2482 rxcfg |= rxcfg_new; 2483 2484 writel(rxcfg, gp->regs + MAC_RXCFG); 2485 } 2486 2487 /* Jumbo-grams don't seem to work :-( */ 2488 #define GEM_MIN_MTU ETH_MIN_MTU 2489 #if 1 2490 #define GEM_MAX_MTU ETH_DATA_LEN 2491 #else 2492 #define GEM_MAX_MTU 9000 2493 #endif 2494 2495 static int gem_change_mtu(struct net_device *dev, int new_mtu) 2496 { 2497 struct gem *gp = netdev_priv(dev); 2498 2499 dev->mtu = new_mtu; 2500 2501 /* We'll just catch it later when the device is up'd or resumed */ 2502 if (!netif_running(dev) || !netif_device_present(dev)) 2503 return 0; 2504 2505 /* Better safe than sorry... */ 2506 if (WARN_ON(!gp->cell_enabled)) 2507 return 0; 2508 2509 gem_netif_stop(gp); 2510 gem_reinit_chip(gp); 2511 if (gp->lstate == link_up) 2512 gem_set_link_modes(gp); 2513 gem_netif_start(gp); 2514 2515 return 0; 2516 } 2517 2518 static void gem_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info) 2519 { 2520 struct gem *gp = netdev_priv(dev); 2521 2522 strlcpy(info->driver, DRV_NAME, sizeof(info->driver)); 2523 strlcpy(info->version, DRV_VERSION, sizeof(info->version)); 2524 strlcpy(info->bus_info, pci_name(gp->pdev), sizeof(info->bus_info)); 2525 } 2526 2527 static int gem_get_link_ksettings(struct net_device *dev, 2528 struct ethtool_link_ksettings *cmd) 2529 { 2530 struct gem *gp = netdev_priv(dev); 2531 u32 supported, advertising; 2532 2533 if (gp->phy_type == phy_mii_mdio0 || 2534 gp->phy_type == phy_mii_mdio1) { 2535 if (gp->phy_mii.def) 2536 supported = gp->phy_mii.def->features; 2537 else 2538 supported = (SUPPORTED_10baseT_Half | 2539 SUPPORTED_10baseT_Full); 2540 2541 /* XXX hardcoded stuff for now */ 2542 cmd->base.port = PORT_MII; 2543 cmd->base.phy_address = 0; /* XXX fixed PHYAD */ 2544 2545 /* Return current PHY settings */ 2546 cmd->base.autoneg = gp->want_autoneg; 2547 cmd->base.speed = gp->phy_mii.speed; 2548 cmd->base.duplex = gp->phy_mii.duplex; 2549 advertising = gp->phy_mii.advertising; 2550 2551 /* If we started with a forced mode, we don't have a default 2552 * advertise set, we need to return something sensible so 2553 * userland can re-enable autoneg properly. 2554 */ 2555 if (advertising == 0) 2556 advertising = supported; 2557 } else { // XXX PCS ? 2558 supported = 2559 (SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full | 2560 SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full | 2561 SUPPORTED_Autoneg); 2562 advertising = supported; 2563 cmd->base.speed = 0; 2564 cmd->base.duplex = 0; 2565 cmd->base.port = 0; 2566 cmd->base.phy_address = 0; 2567 cmd->base.autoneg = 0; 2568 2569 /* serdes means usually a Fibre connector, with most fixed */ 2570 if (gp->phy_type == phy_serdes) { 2571 cmd->base.port = PORT_FIBRE; 2572 supported = (SUPPORTED_1000baseT_Half | 2573 SUPPORTED_1000baseT_Full | 2574 SUPPORTED_FIBRE | SUPPORTED_Autoneg | 2575 SUPPORTED_Pause | SUPPORTED_Asym_Pause); 2576 advertising = supported; 2577 if (gp->lstate == link_up) 2578 cmd->base.speed = SPEED_1000; 2579 cmd->base.duplex = DUPLEX_FULL; 2580 cmd->base.autoneg = 1; 2581 } 2582 } 2583 2584 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.supported, 2585 supported); 2586 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.advertising, 2587 advertising); 2588 2589 return 0; 2590 } 2591 2592 static int gem_set_link_ksettings(struct net_device *dev, 2593 const struct ethtool_link_ksettings *cmd) 2594 { 2595 struct gem *gp = netdev_priv(dev); 2596 u32 speed = cmd->base.speed; 2597 u32 advertising; 2598 2599 ethtool_convert_link_mode_to_legacy_u32(&advertising, 2600 cmd->link_modes.advertising); 2601 2602 /* Verify the settings we care about. */ 2603 if (cmd->base.autoneg != AUTONEG_ENABLE && 2604 cmd->base.autoneg != AUTONEG_DISABLE) 2605 return -EINVAL; 2606 2607 if (cmd->base.autoneg == AUTONEG_ENABLE && 2608 advertising == 0) 2609 return -EINVAL; 2610 2611 if (cmd->base.autoneg == AUTONEG_DISABLE && 2612 ((speed != SPEED_1000 && 2613 speed != SPEED_100 && 2614 speed != SPEED_10) || 2615 (cmd->base.duplex != DUPLEX_HALF && 2616 cmd->base.duplex != DUPLEX_FULL))) 2617 return -EINVAL; 2618 2619 /* Apply settings and restart link process. */ 2620 if (netif_device_present(gp->dev)) { 2621 del_timer_sync(&gp->link_timer); 2622 gem_begin_auto_negotiation(gp, cmd); 2623 } 2624 2625 return 0; 2626 } 2627 2628 static int gem_nway_reset(struct net_device *dev) 2629 { 2630 struct gem *gp = netdev_priv(dev); 2631 2632 if (!gp->want_autoneg) 2633 return -EINVAL; 2634 2635 /* Restart link process */ 2636 if (netif_device_present(gp->dev)) { 2637 del_timer_sync(&gp->link_timer); 2638 gem_begin_auto_negotiation(gp, NULL); 2639 } 2640 2641 return 0; 2642 } 2643 2644 static u32 gem_get_msglevel(struct net_device *dev) 2645 { 2646 struct gem *gp = netdev_priv(dev); 2647 return gp->msg_enable; 2648 } 2649 2650 static void gem_set_msglevel(struct net_device *dev, u32 value) 2651 { 2652 struct gem *gp = netdev_priv(dev); 2653 gp->msg_enable = value; 2654 } 2655 2656 2657 /* Add more when I understand how to program the chip */ 2658 /* like WAKE_UCAST | WAKE_MCAST | WAKE_BCAST */ 2659 2660 #define WOL_SUPPORTED_MASK (WAKE_MAGIC) 2661 2662 static void gem_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 2663 { 2664 struct gem *gp = netdev_priv(dev); 2665 2666 /* Add more when I understand how to program the chip */ 2667 if (gp->has_wol) { 2668 wol->supported = WOL_SUPPORTED_MASK; 2669 wol->wolopts = gp->wake_on_lan; 2670 } else { 2671 wol->supported = 0; 2672 wol->wolopts = 0; 2673 } 2674 } 2675 2676 static int gem_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 2677 { 2678 struct gem *gp = netdev_priv(dev); 2679 2680 if (!gp->has_wol) 2681 return -EOPNOTSUPP; 2682 gp->wake_on_lan = wol->wolopts & WOL_SUPPORTED_MASK; 2683 return 0; 2684 } 2685 2686 static const struct ethtool_ops gem_ethtool_ops = { 2687 .get_drvinfo = gem_get_drvinfo, 2688 .get_link = ethtool_op_get_link, 2689 .nway_reset = gem_nway_reset, 2690 .get_msglevel = gem_get_msglevel, 2691 .set_msglevel = gem_set_msglevel, 2692 .get_wol = gem_get_wol, 2693 .set_wol = gem_set_wol, 2694 .get_link_ksettings = gem_get_link_ksettings, 2695 .set_link_ksettings = gem_set_link_ksettings, 2696 }; 2697 2698 static int gem_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) 2699 { 2700 struct gem *gp = netdev_priv(dev); 2701 struct mii_ioctl_data *data = if_mii(ifr); 2702 int rc = -EOPNOTSUPP; 2703 2704 /* For SIOCGMIIREG and SIOCSMIIREG the core checks for us that 2705 * netif_device_present() is true and holds rtnl_lock for us 2706 * so we have nothing to worry about 2707 */ 2708 2709 switch (cmd) { 2710 case SIOCGMIIPHY: /* Get address of MII PHY in use. */ 2711 data->phy_id = gp->mii_phy_addr; 2712 /* Fallthrough... */ 2713 2714 case SIOCGMIIREG: /* Read MII PHY register. */ 2715 data->val_out = __sungem_phy_read(gp, data->phy_id & 0x1f, 2716 data->reg_num & 0x1f); 2717 rc = 0; 2718 break; 2719 2720 case SIOCSMIIREG: /* Write MII PHY register. */ 2721 __sungem_phy_write(gp, data->phy_id & 0x1f, data->reg_num & 0x1f, 2722 data->val_in); 2723 rc = 0; 2724 break; 2725 } 2726 return rc; 2727 } 2728 2729 #if (!defined(CONFIG_SPARC) && !defined(CONFIG_PPC_PMAC)) 2730 /* Fetch MAC address from vital product data of PCI ROM. */ 2731 static int find_eth_addr_in_vpd(void __iomem *rom_base, int len, unsigned char *dev_addr) 2732 { 2733 int this_offset; 2734 2735 for (this_offset = 0x20; this_offset < len; this_offset++) { 2736 void __iomem *p = rom_base + this_offset; 2737 int i; 2738 2739 if (readb(p + 0) != 0x90 || 2740 readb(p + 1) != 0x00 || 2741 readb(p + 2) != 0x09 || 2742 readb(p + 3) != 0x4e || 2743 readb(p + 4) != 0x41 || 2744 readb(p + 5) != 0x06) 2745 continue; 2746 2747 this_offset += 6; 2748 p += 6; 2749 2750 for (i = 0; i < 6; i++) 2751 dev_addr[i] = readb(p + i); 2752 return 1; 2753 } 2754 return 0; 2755 } 2756 2757 static void get_gem_mac_nonobp(struct pci_dev *pdev, unsigned char *dev_addr) 2758 { 2759 size_t size; 2760 void __iomem *p = pci_map_rom(pdev, &size); 2761 2762 if (p) { 2763 int found; 2764 2765 found = readb(p) == 0x55 && 2766 readb(p + 1) == 0xaa && 2767 find_eth_addr_in_vpd(p, (64 * 1024), dev_addr); 2768 pci_unmap_rom(pdev, p); 2769 if (found) 2770 return; 2771 } 2772 2773 /* Sun MAC prefix then 3 random bytes. */ 2774 dev_addr[0] = 0x08; 2775 dev_addr[1] = 0x00; 2776 dev_addr[2] = 0x20; 2777 get_random_bytes(dev_addr + 3, 3); 2778 } 2779 #endif /* not Sparc and not PPC */ 2780 2781 static int gem_get_device_address(struct gem *gp) 2782 { 2783 #if defined(CONFIG_SPARC) || defined(CONFIG_PPC_PMAC) 2784 struct net_device *dev = gp->dev; 2785 const unsigned char *addr; 2786 2787 addr = of_get_property(gp->of_node, "local-mac-address", NULL); 2788 if (addr == NULL) { 2789 #ifdef CONFIG_SPARC 2790 addr = idprom->id_ethaddr; 2791 #else 2792 printk("\n"); 2793 pr_err("%s: can't get mac-address\n", dev->name); 2794 return -1; 2795 #endif 2796 } 2797 memcpy(dev->dev_addr, addr, ETH_ALEN); 2798 #else 2799 get_gem_mac_nonobp(gp->pdev, gp->dev->dev_addr); 2800 #endif 2801 return 0; 2802 } 2803 2804 static void gem_remove_one(struct pci_dev *pdev) 2805 { 2806 struct net_device *dev = pci_get_drvdata(pdev); 2807 2808 if (dev) { 2809 struct gem *gp = netdev_priv(dev); 2810 2811 unregister_netdev(dev); 2812 2813 /* Ensure reset task is truly gone */ 2814 cancel_work_sync(&gp->reset_task); 2815 2816 /* Free resources */ 2817 pci_free_consistent(pdev, 2818 sizeof(struct gem_init_block), 2819 gp->init_block, 2820 gp->gblock_dvma); 2821 iounmap(gp->regs); 2822 pci_release_regions(pdev); 2823 free_netdev(dev); 2824 } 2825 } 2826 2827 static const struct net_device_ops gem_netdev_ops = { 2828 .ndo_open = gem_open, 2829 .ndo_stop = gem_close, 2830 .ndo_start_xmit = gem_start_xmit, 2831 .ndo_get_stats = gem_get_stats, 2832 .ndo_set_rx_mode = gem_set_multicast, 2833 .ndo_do_ioctl = gem_ioctl, 2834 .ndo_tx_timeout = gem_tx_timeout, 2835 .ndo_change_mtu = gem_change_mtu, 2836 .ndo_validate_addr = eth_validate_addr, 2837 .ndo_set_mac_address = gem_set_mac_address, 2838 #ifdef CONFIG_NET_POLL_CONTROLLER 2839 .ndo_poll_controller = gem_poll_controller, 2840 #endif 2841 }; 2842 2843 static int gem_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) 2844 { 2845 unsigned long gemreg_base, gemreg_len; 2846 struct net_device *dev; 2847 struct gem *gp; 2848 int err, pci_using_dac; 2849 2850 printk_once(KERN_INFO "%s", version); 2851 2852 /* Apple gmac note: during probe, the chip is powered up by 2853 * the arch code to allow the code below to work (and to let 2854 * the chip be probed on the config space. It won't stay powered 2855 * up until the interface is brought up however, so we can't rely 2856 * on register configuration done at this point. 2857 */ 2858 err = pci_enable_device(pdev); 2859 if (err) { 2860 pr_err("Cannot enable MMIO operation, aborting\n"); 2861 return err; 2862 } 2863 pci_set_master(pdev); 2864 2865 /* Configure DMA attributes. */ 2866 2867 /* All of the GEM documentation states that 64-bit DMA addressing 2868 * is fully supported and should work just fine. However the 2869 * front end for RIO based GEMs is different and only supports 2870 * 32-bit addressing. 2871 * 2872 * For now we assume the various PPC GEMs are 32-bit only as well. 2873 */ 2874 if (pdev->vendor == PCI_VENDOR_ID_SUN && 2875 pdev->device == PCI_DEVICE_ID_SUN_GEM && 2876 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) { 2877 pci_using_dac = 1; 2878 } else { 2879 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); 2880 if (err) { 2881 pr_err("No usable DMA configuration, aborting\n"); 2882 goto err_disable_device; 2883 } 2884 pci_using_dac = 0; 2885 } 2886 2887 gemreg_base = pci_resource_start(pdev, 0); 2888 gemreg_len = pci_resource_len(pdev, 0); 2889 2890 if ((pci_resource_flags(pdev, 0) & IORESOURCE_IO) != 0) { 2891 pr_err("Cannot find proper PCI device base address, aborting\n"); 2892 err = -ENODEV; 2893 goto err_disable_device; 2894 } 2895 2896 dev = alloc_etherdev(sizeof(*gp)); 2897 if (!dev) { 2898 err = -ENOMEM; 2899 goto err_disable_device; 2900 } 2901 SET_NETDEV_DEV(dev, &pdev->dev); 2902 2903 gp = netdev_priv(dev); 2904 2905 err = pci_request_regions(pdev, DRV_NAME); 2906 if (err) { 2907 pr_err("Cannot obtain PCI resources, aborting\n"); 2908 goto err_out_free_netdev; 2909 } 2910 2911 gp->pdev = pdev; 2912 gp->dev = dev; 2913 2914 gp->msg_enable = DEFAULT_MSG; 2915 2916 timer_setup(&gp->link_timer, gem_link_timer, 0); 2917 2918 INIT_WORK(&gp->reset_task, gem_reset_task); 2919 2920 gp->lstate = link_down; 2921 gp->timer_ticks = 0; 2922 netif_carrier_off(dev); 2923 2924 gp->regs = ioremap(gemreg_base, gemreg_len); 2925 if (!gp->regs) { 2926 pr_err("Cannot map device registers, aborting\n"); 2927 err = -EIO; 2928 goto err_out_free_res; 2929 } 2930 2931 /* On Apple, we want a reference to the Open Firmware device-tree 2932 * node. We use it for clock control. 2933 */ 2934 #if defined(CONFIG_PPC_PMAC) || defined(CONFIG_SPARC) 2935 gp->of_node = pci_device_to_OF_node(pdev); 2936 #endif 2937 2938 /* Only Apple version supports WOL afaik */ 2939 if (pdev->vendor == PCI_VENDOR_ID_APPLE) 2940 gp->has_wol = 1; 2941 2942 /* Make sure cell is enabled */ 2943 gem_get_cell(gp); 2944 2945 /* Make sure everything is stopped and in init state */ 2946 gem_reset(gp); 2947 2948 /* Fill up the mii_phy structure (even if we won't use it) */ 2949 gp->phy_mii.dev = dev; 2950 gp->phy_mii.mdio_read = _sungem_phy_read; 2951 gp->phy_mii.mdio_write = _sungem_phy_write; 2952 #ifdef CONFIG_PPC_PMAC 2953 gp->phy_mii.platform_data = gp->of_node; 2954 #endif 2955 /* By default, we start with autoneg */ 2956 gp->want_autoneg = 1; 2957 2958 /* Check fifo sizes, PHY type, etc... */ 2959 if (gem_check_invariants(gp)) { 2960 err = -ENODEV; 2961 goto err_out_iounmap; 2962 } 2963 2964 /* It is guaranteed that the returned buffer will be at least 2965 * PAGE_SIZE aligned. 2966 */ 2967 gp->init_block = (struct gem_init_block *) 2968 pci_alloc_consistent(pdev, sizeof(struct gem_init_block), 2969 &gp->gblock_dvma); 2970 if (!gp->init_block) { 2971 pr_err("Cannot allocate init block, aborting\n"); 2972 err = -ENOMEM; 2973 goto err_out_iounmap; 2974 } 2975 2976 err = gem_get_device_address(gp); 2977 if (err) 2978 goto err_out_free_consistent; 2979 2980 dev->netdev_ops = &gem_netdev_ops; 2981 netif_napi_add(dev, &gp->napi, gem_poll, 64); 2982 dev->ethtool_ops = &gem_ethtool_ops; 2983 dev->watchdog_timeo = 5 * HZ; 2984 dev->dma = 0; 2985 2986 /* Set that now, in case PM kicks in now */ 2987 pci_set_drvdata(pdev, dev); 2988 2989 /* We can do scatter/gather and HW checksum */ 2990 dev->hw_features = NETIF_F_SG | NETIF_F_HW_CSUM | NETIF_F_RXCSUM; 2991 dev->features = dev->hw_features; 2992 if (pci_using_dac) 2993 dev->features |= NETIF_F_HIGHDMA; 2994 2995 /* MTU range: 68 - 1500 (Jumbo mode is broken) */ 2996 dev->min_mtu = GEM_MIN_MTU; 2997 dev->max_mtu = GEM_MAX_MTU; 2998 2999 /* Register with kernel */ 3000 if (register_netdev(dev)) { 3001 pr_err("Cannot register net device, aborting\n"); 3002 err = -ENOMEM; 3003 goto err_out_free_consistent; 3004 } 3005 3006 /* Undo the get_cell with appropriate locking (we could use 3007 * ndo_init/uninit but that would be even more clumsy imho) 3008 */ 3009 rtnl_lock(); 3010 gem_put_cell(gp); 3011 rtnl_unlock(); 3012 3013 netdev_info(dev, "Sun GEM (PCI) 10/100/1000BaseT Ethernet %pM\n", 3014 dev->dev_addr); 3015 return 0; 3016 3017 err_out_free_consistent: 3018 gem_remove_one(pdev); 3019 err_out_iounmap: 3020 gem_put_cell(gp); 3021 iounmap(gp->regs); 3022 3023 err_out_free_res: 3024 pci_release_regions(pdev); 3025 3026 err_out_free_netdev: 3027 free_netdev(dev); 3028 err_disable_device: 3029 pci_disable_device(pdev); 3030 return err; 3031 3032 } 3033 3034 static SIMPLE_DEV_PM_OPS(gem_pm_ops, gem_suspend, gem_resume); 3035 3036 static struct pci_driver gem_driver = { 3037 .name = GEM_MODULE_NAME, 3038 .id_table = gem_pci_tbl, 3039 .probe = gem_init_one, 3040 .remove = gem_remove_one, 3041 .driver.pm = &gem_pm_ops, 3042 }; 3043 3044 module_pci_driver(gem_driver); 3045