1 /* sunbmac.c: Driver for Sparc BigMAC 100baseT ethernet adapters. 2 * 3 * Copyright (C) 1997, 1998, 1999, 2003, 2008 David S. Miller (davem@davemloft.net) 4 */ 5 6 #include <linux/module.h> 7 8 #include <linux/kernel.h> 9 #include <linux/types.h> 10 #include <linux/fcntl.h> 11 #include <linux/interrupt.h> 12 #include <linux/ioport.h> 13 #include <linux/in.h> 14 #include <linux/string.h> 15 #include <linux/delay.h> 16 #include <linux/init.h> 17 #include <linux/crc32.h> 18 #include <linux/errno.h> 19 #include <linux/ethtool.h> 20 #include <linux/mii.h> 21 #include <linux/netdevice.h> 22 #include <linux/etherdevice.h> 23 #include <linux/skbuff.h> 24 #include <linux/bitops.h> 25 #include <linux/dma-mapping.h> 26 #include <linux/of.h> 27 #include <linux/of_device.h> 28 #include <linux/gfp.h> 29 30 #include <asm/auxio.h> 31 #include <asm/byteorder.h> 32 #include <asm/dma.h> 33 #include <asm/idprom.h> 34 #include <asm/io.h> 35 #include <asm/openprom.h> 36 #include <asm/oplib.h> 37 #include <asm/pgtable.h> 38 #include <asm/system.h> 39 40 #include "sunbmac.h" 41 42 #define DRV_NAME "sunbmac" 43 #define DRV_VERSION "2.1" 44 #define DRV_RELDATE "August 26, 2008" 45 #define DRV_AUTHOR "David S. Miller (davem@davemloft.net)" 46 47 static char version[] = 48 DRV_NAME ".c:v" DRV_VERSION " " DRV_RELDATE " " DRV_AUTHOR "\n"; 49 50 MODULE_VERSION(DRV_VERSION); 51 MODULE_AUTHOR(DRV_AUTHOR); 52 MODULE_DESCRIPTION("Sun BigMAC 100baseT ethernet driver"); 53 MODULE_LICENSE("GPL"); 54 55 #undef DEBUG_PROBE 56 #undef DEBUG_TX 57 #undef DEBUG_IRQ 58 59 #ifdef DEBUG_PROBE 60 #define DP(x) printk x 61 #else 62 #define DP(x) 63 #endif 64 65 #ifdef DEBUG_TX 66 #define DTX(x) printk x 67 #else 68 #define DTX(x) 69 #endif 70 71 #ifdef DEBUG_IRQ 72 #define DIRQ(x) printk x 73 #else 74 #define DIRQ(x) 75 #endif 76 77 #define DEFAULT_JAMSIZE 4 /* Toe jam */ 78 79 #define QEC_RESET_TRIES 200 80 81 static int qec_global_reset(void __iomem *gregs) 82 { 83 int tries = QEC_RESET_TRIES; 84 85 sbus_writel(GLOB_CTRL_RESET, gregs + GLOB_CTRL); 86 while (--tries) { 87 if (sbus_readl(gregs + GLOB_CTRL) & GLOB_CTRL_RESET) { 88 udelay(20); 89 continue; 90 } 91 break; 92 } 93 if (tries) 94 return 0; 95 printk(KERN_ERR "BigMAC: Cannot reset the QEC.\n"); 96 return -1; 97 } 98 99 static void qec_init(struct bigmac *bp) 100 { 101 struct platform_device *qec_op = bp->qec_op; 102 void __iomem *gregs = bp->gregs; 103 u8 bsizes = bp->bigmac_bursts; 104 u32 regval; 105 106 /* 64byte bursts do not work at the moment, do 107 * not even try to enable them. -DaveM 108 */ 109 if (bsizes & DMA_BURST32) 110 regval = GLOB_CTRL_B32; 111 else 112 regval = GLOB_CTRL_B16; 113 sbus_writel(regval | GLOB_CTRL_BMODE, gregs + GLOB_CTRL); 114 sbus_writel(GLOB_PSIZE_2048, gregs + GLOB_PSIZE); 115 116 /* All of memsize is given to bigmac. */ 117 sbus_writel(resource_size(&qec_op->resource[1]), 118 gregs + GLOB_MSIZE); 119 120 /* Half to the transmitter, half to the receiver. */ 121 sbus_writel(resource_size(&qec_op->resource[1]) >> 1, 122 gregs + GLOB_TSIZE); 123 sbus_writel(resource_size(&qec_op->resource[1]) >> 1, 124 gregs + GLOB_RSIZE); 125 } 126 127 #define TX_RESET_TRIES 32 128 #define RX_RESET_TRIES 32 129 130 static void bigmac_tx_reset(void __iomem *bregs) 131 { 132 int tries = TX_RESET_TRIES; 133 134 sbus_writel(0, bregs + BMAC_TXCFG); 135 136 /* The fifo threshold bit is read-only and does 137 * not clear. -DaveM 138 */ 139 while ((sbus_readl(bregs + BMAC_TXCFG) & ~(BIGMAC_TXCFG_FIFO)) != 0 && 140 --tries != 0) 141 udelay(20); 142 143 if (!tries) { 144 printk(KERN_ERR "BIGMAC: Transmitter will not reset.\n"); 145 printk(KERN_ERR "BIGMAC: tx_cfg is %08x\n", 146 sbus_readl(bregs + BMAC_TXCFG)); 147 } 148 } 149 150 static void bigmac_rx_reset(void __iomem *bregs) 151 { 152 int tries = RX_RESET_TRIES; 153 154 sbus_writel(0, bregs + BMAC_RXCFG); 155 while (sbus_readl(bregs + BMAC_RXCFG) && --tries) 156 udelay(20); 157 158 if (!tries) { 159 printk(KERN_ERR "BIGMAC: Receiver will not reset.\n"); 160 printk(KERN_ERR "BIGMAC: rx_cfg is %08x\n", 161 sbus_readl(bregs + BMAC_RXCFG)); 162 } 163 } 164 165 /* Reset the transmitter and receiver. */ 166 static void bigmac_stop(struct bigmac *bp) 167 { 168 bigmac_tx_reset(bp->bregs); 169 bigmac_rx_reset(bp->bregs); 170 } 171 172 static void bigmac_get_counters(struct bigmac *bp, void __iomem *bregs) 173 { 174 struct net_device_stats *stats = &bp->enet_stats; 175 176 stats->rx_crc_errors += sbus_readl(bregs + BMAC_RCRCECTR); 177 sbus_writel(0, bregs + BMAC_RCRCECTR); 178 179 stats->rx_frame_errors += sbus_readl(bregs + BMAC_UNALECTR); 180 sbus_writel(0, bregs + BMAC_UNALECTR); 181 182 stats->rx_length_errors += sbus_readl(bregs + BMAC_GLECTR); 183 sbus_writel(0, bregs + BMAC_GLECTR); 184 185 stats->tx_aborted_errors += sbus_readl(bregs + BMAC_EXCTR); 186 187 stats->collisions += 188 (sbus_readl(bregs + BMAC_EXCTR) + 189 sbus_readl(bregs + BMAC_LTCTR)); 190 sbus_writel(0, bregs + BMAC_EXCTR); 191 sbus_writel(0, bregs + BMAC_LTCTR); 192 } 193 194 static void bigmac_clean_rings(struct bigmac *bp) 195 { 196 int i; 197 198 for (i = 0; i < RX_RING_SIZE; i++) { 199 if (bp->rx_skbs[i] != NULL) { 200 dev_kfree_skb_any(bp->rx_skbs[i]); 201 bp->rx_skbs[i] = NULL; 202 } 203 } 204 205 for (i = 0; i < TX_RING_SIZE; i++) { 206 if (bp->tx_skbs[i] != NULL) { 207 dev_kfree_skb_any(bp->tx_skbs[i]); 208 bp->tx_skbs[i] = NULL; 209 } 210 } 211 } 212 213 static void bigmac_init_rings(struct bigmac *bp, int from_irq) 214 { 215 struct bmac_init_block *bb = bp->bmac_block; 216 struct net_device *dev = bp->dev; 217 int i; 218 gfp_t gfp_flags = GFP_KERNEL; 219 220 if (from_irq || in_interrupt()) 221 gfp_flags = GFP_ATOMIC; 222 223 bp->rx_new = bp->rx_old = bp->tx_new = bp->tx_old = 0; 224 225 /* Free any skippy bufs left around in the rings. */ 226 bigmac_clean_rings(bp); 227 228 /* Now get new skbufs for the receive ring. */ 229 for (i = 0; i < RX_RING_SIZE; i++) { 230 struct sk_buff *skb; 231 232 skb = big_mac_alloc_skb(RX_BUF_ALLOC_SIZE, gfp_flags); 233 if (!skb) 234 continue; 235 236 bp->rx_skbs[i] = skb; 237 skb->dev = dev; 238 239 /* Because we reserve afterwards. */ 240 skb_put(skb, ETH_FRAME_LEN); 241 skb_reserve(skb, 34); 242 243 bb->be_rxd[i].rx_addr = 244 dma_map_single(&bp->bigmac_op->dev, 245 skb->data, 246 RX_BUF_ALLOC_SIZE - 34, 247 DMA_FROM_DEVICE); 248 bb->be_rxd[i].rx_flags = 249 (RXD_OWN | ((RX_BUF_ALLOC_SIZE - 34) & RXD_LENGTH)); 250 } 251 252 for (i = 0; i < TX_RING_SIZE; i++) 253 bb->be_txd[i].tx_flags = bb->be_txd[i].tx_addr = 0; 254 } 255 256 #define MGMT_CLKON (MGMT_PAL_INT_MDIO|MGMT_PAL_EXT_MDIO|MGMT_PAL_OENAB|MGMT_PAL_DCLOCK) 257 #define MGMT_CLKOFF (MGMT_PAL_INT_MDIO|MGMT_PAL_EXT_MDIO|MGMT_PAL_OENAB) 258 259 static void idle_transceiver(void __iomem *tregs) 260 { 261 int i = 20; 262 263 while (i--) { 264 sbus_writel(MGMT_CLKOFF, tregs + TCVR_MPAL); 265 sbus_readl(tregs + TCVR_MPAL); 266 sbus_writel(MGMT_CLKON, tregs + TCVR_MPAL); 267 sbus_readl(tregs + TCVR_MPAL); 268 } 269 } 270 271 static void write_tcvr_bit(struct bigmac *bp, void __iomem *tregs, int bit) 272 { 273 if (bp->tcvr_type == internal) { 274 bit = (bit & 1) << 3; 275 sbus_writel(bit | (MGMT_PAL_OENAB | MGMT_PAL_EXT_MDIO), 276 tregs + TCVR_MPAL); 277 sbus_readl(tregs + TCVR_MPAL); 278 sbus_writel(bit | MGMT_PAL_OENAB | MGMT_PAL_EXT_MDIO | MGMT_PAL_DCLOCK, 279 tregs + TCVR_MPAL); 280 sbus_readl(tregs + TCVR_MPAL); 281 } else if (bp->tcvr_type == external) { 282 bit = (bit & 1) << 2; 283 sbus_writel(bit | MGMT_PAL_INT_MDIO | MGMT_PAL_OENAB, 284 tregs + TCVR_MPAL); 285 sbus_readl(tregs + TCVR_MPAL); 286 sbus_writel(bit | MGMT_PAL_INT_MDIO | MGMT_PAL_OENAB | MGMT_PAL_DCLOCK, 287 tregs + TCVR_MPAL); 288 sbus_readl(tregs + TCVR_MPAL); 289 } else { 290 printk(KERN_ERR "write_tcvr_bit: No transceiver type known!\n"); 291 } 292 } 293 294 static int read_tcvr_bit(struct bigmac *bp, void __iomem *tregs) 295 { 296 int retval = 0; 297 298 if (bp->tcvr_type == internal) { 299 sbus_writel(MGMT_PAL_EXT_MDIO, tregs + TCVR_MPAL); 300 sbus_readl(tregs + TCVR_MPAL); 301 sbus_writel(MGMT_PAL_EXT_MDIO | MGMT_PAL_DCLOCK, 302 tregs + TCVR_MPAL); 303 sbus_readl(tregs + TCVR_MPAL); 304 retval = (sbus_readl(tregs + TCVR_MPAL) & MGMT_PAL_INT_MDIO) >> 3; 305 } else if (bp->tcvr_type == external) { 306 sbus_writel(MGMT_PAL_INT_MDIO, tregs + TCVR_MPAL); 307 sbus_readl(tregs + TCVR_MPAL); 308 sbus_writel(MGMT_PAL_INT_MDIO | MGMT_PAL_DCLOCK, tregs + TCVR_MPAL); 309 sbus_readl(tregs + TCVR_MPAL); 310 retval = (sbus_readl(tregs + TCVR_MPAL) & MGMT_PAL_EXT_MDIO) >> 2; 311 } else { 312 printk(KERN_ERR "read_tcvr_bit: No transceiver type known!\n"); 313 } 314 return retval; 315 } 316 317 static int read_tcvr_bit2(struct bigmac *bp, void __iomem *tregs) 318 { 319 int retval = 0; 320 321 if (bp->tcvr_type == internal) { 322 sbus_writel(MGMT_PAL_EXT_MDIO, tregs + TCVR_MPAL); 323 sbus_readl(tregs + TCVR_MPAL); 324 retval = (sbus_readl(tregs + TCVR_MPAL) & MGMT_PAL_INT_MDIO) >> 3; 325 sbus_writel(MGMT_PAL_EXT_MDIO | MGMT_PAL_DCLOCK, tregs + TCVR_MPAL); 326 sbus_readl(tregs + TCVR_MPAL); 327 } else if (bp->tcvr_type == external) { 328 sbus_writel(MGMT_PAL_INT_MDIO, tregs + TCVR_MPAL); 329 sbus_readl(tregs + TCVR_MPAL); 330 retval = (sbus_readl(tregs + TCVR_MPAL) & MGMT_PAL_EXT_MDIO) >> 2; 331 sbus_writel(MGMT_PAL_INT_MDIO | MGMT_PAL_DCLOCK, tregs + TCVR_MPAL); 332 sbus_readl(tregs + TCVR_MPAL); 333 } else { 334 printk(KERN_ERR "read_tcvr_bit2: No transceiver type known!\n"); 335 } 336 return retval; 337 } 338 339 static void put_tcvr_byte(struct bigmac *bp, 340 void __iomem *tregs, 341 unsigned int byte) 342 { 343 int shift = 4; 344 345 do { 346 write_tcvr_bit(bp, tregs, ((byte >> shift) & 1)); 347 shift -= 1; 348 } while (shift >= 0); 349 } 350 351 static void bigmac_tcvr_write(struct bigmac *bp, void __iomem *tregs, 352 int reg, unsigned short val) 353 { 354 int shift; 355 356 reg &= 0xff; 357 val &= 0xffff; 358 switch(bp->tcvr_type) { 359 case internal: 360 case external: 361 break; 362 363 default: 364 printk(KERN_ERR "bigmac_tcvr_read: Whoops, no known transceiver type.\n"); 365 return; 366 } 367 368 idle_transceiver(tregs); 369 write_tcvr_bit(bp, tregs, 0); 370 write_tcvr_bit(bp, tregs, 1); 371 write_tcvr_bit(bp, tregs, 0); 372 write_tcvr_bit(bp, tregs, 1); 373 374 put_tcvr_byte(bp, tregs, 375 ((bp->tcvr_type == internal) ? 376 BIGMAC_PHY_INTERNAL : BIGMAC_PHY_EXTERNAL)); 377 378 put_tcvr_byte(bp, tregs, reg); 379 380 write_tcvr_bit(bp, tregs, 1); 381 write_tcvr_bit(bp, tregs, 0); 382 383 shift = 15; 384 do { 385 write_tcvr_bit(bp, tregs, (val >> shift) & 1); 386 shift -= 1; 387 } while (shift >= 0); 388 } 389 390 static unsigned short bigmac_tcvr_read(struct bigmac *bp, 391 void __iomem *tregs, 392 int reg) 393 { 394 unsigned short retval = 0; 395 396 reg &= 0xff; 397 switch(bp->tcvr_type) { 398 case internal: 399 case external: 400 break; 401 402 default: 403 printk(KERN_ERR "bigmac_tcvr_read: Whoops, no known transceiver type.\n"); 404 return 0xffff; 405 } 406 407 idle_transceiver(tregs); 408 write_tcvr_bit(bp, tregs, 0); 409 write_tcvr_bit(bp, tregs, 1); 410 write_tcvr_bit(bp, tregs, 1); 411 write_tcvr_bit(bp, tregs, 0); 412 413 put_tcvr_byte(bp, tregs, 414 ((bp->tcvr_type == internal) ? 415 BIGMAC_PHY_INTERNAL : BIGMAC_PHY_EXTERNAL)); 416 417 put_tcvr_byte(bp, tregs, reg); 418 419 if (bp->tcvr_type == external) { 420 int shift = 15; 421 422 (void) read_tcvr_bit2(bp, tregs); 423 (void) read_tcvr_bit2(bp, tregs); 424 425 do { 426 int tmp; 427 428 tmp = read_tcvr_bit2(bp, tregs); 429 retval |= ((tmp & 1) << shift); 430 shift -= 1; 431 } while (shift >= 0); 432 433 (void) read_tcvr_bit2(bp, tregs); 434 (void) read_tcvr_bit2(bp, tregs); 435 (void) read_tcvr_bit2(bp, tregs); 436 } else { 437 int shift = 15; 438 439 (void) read_tcvr_bit(bp, tregs); 440 (void) read_tcvr_bit(bp, tregs); 441 442 do { 443 int tmp; 444 445 tmp = read_tcvr_bit(bp, tregs); 446 retval |= ((tmp & 1) << shift); 447 shift -= 1; 448 } while (shift >= 0); 449 450 (void) read_tcvr_bit(bp, tregs); 451 (void) read_tcvr_bit(bp, tregs); 452 (void) read_tcvr_bit(bp, tregs); 453 } 454 return retval; 455 } 456 457 static void bigmac_tcvr_init(struct bigmac *bp) 458 { 459 void __iomem *tregs = bp->tregs; 460 u32 mpal; 461 462 idle_transceiver(tregs); 463 sbus_writel(MGMT_PAL_INT_MDIO | MGMT_PAL_EXT_MDIO | MGMT_PAL_DCLOCK, 464 tregs + TCVR_MPAL); 465 sbus_readl(tregs + TCVR_MPAL); 466 467 /* Only the bit for the present transceiver (internal or 468 * external) will stick, set them both and see what stays. 469 */ 470 sbus_writel(MGMT_PAL_INT_MDIO | MGMT_PAL_EXT_MDIO, tregs + TCVR_MPAL); 471 sbus_readl(tregs + TCVR_MPAL); 472 udelay(20); 473 474 mpal = sbus_readl(tregs + TCVR_MPAL); 475 if (mpal & MGMT_PAL_EXT_MDIO) { 476 bp->tcvr_type = external; 477 sbus_writel(~(TCVR_PAL_EXTLBACK | TCVR_PAL_MSENSE | TCVR_PAL_LTENABLE), 478 tregs + TCVR_TPAL); 479 sbus_readl(tregs + TCVR_TPAL); 480 } else if (mpal & MGMT_PAL_INT_MDIO) { 481 bp->tcvr_type = internal; 482 sbus_writel(~(TCVR_PAL_SERIAL | TCVR_PAL_EXTLBACK | 483 TCVR_PAL_MSENSE | TCVR_PAL_LTENABLE), 484 tregs + TCVR_TPAL); 485 sbus_readl(tregs + TCVR_TPAL); 486 } else { 487 printk(KERN_ERR "BIGMAC: AIEEE, neither internal nor " 488 "external MDIO available!\n"); 489 printk(KERN_ERR "BIGMAC: mgmt_pal[%08x] tcvr_pal[%08x]\n", 490 sbus_readl(tregs + TCVR_MPAL), 491 sbus_readl(tregs + TCVR_TPAL)); 492 } 493 } 494 495 static int bigmac_init_hw(struct bigmac *, int); 496 497 static int try_next_permutation(struct bigmac *bp, void __iomem *tregs) 498 { 499 if (bp->sw_bmcr & BMCR_SPEED100) { 500 int timeout; 501 502 /* Reset the PHY. */ 503 bp->sw_bmcr = (BMCR_ISOLATE | BMCR_PDOWN | BMCR_LOOPBACK); 504 bigmac_tcvr_write(bp, tregs, MII_BMCR, bp->sw_bmcr); 505 bp->sw_bmcr = (BMCR_RESET); 506 bigmac_tcvr_write(bp, tregs, MII_BMCR, bp->sw_bmcr); 507 508 timeout = 64; 509 while (--timeout) { 510 bp->sw_bmcr = bigmac_tcvr_read(bp, tregs, MII_BMCR); 511 if ((bp->sw_bmcr & BMCR_RESET) == 0) 512 break; 513 udelay(20); 514 } 515 if (timeout == 0) 516 printk(KERN_ERR "%s: PHY reset failed.\n", bp->dev->name); 517 518 bp->sw_bmcr = bigmac_tcvr_read(bp, tregs, MII_BMCR); 519 520 /* Now we try 10baseT. */ 521 bp->sw_bmcr &= ~(BMCR_SPEED100); 522 bigmac_tcvr_write(bp, tregs, MII_BMCR, bp->sw_bmcr); 523 return 0; 524 } 525 526 /* We've tried them all. */ 527 return -1; 528 } 529 530 static void bigmac_timer(unsigned long data) 531 { 532 struct bigmac *bp = (struct bigmac *) data; 533 void __iomem *tregs = bp->tregs; 534 int restart_timer = 0; 535 536 bp->timer_ticks++; 537 if (bp->timer_state == ltrywait) { 538 bp->sw_bmsr = bigmac_tcvr_read(bp, tregs, MII_BMSR); 539 bp->sw_bmcr = bigmac_tcvr_read(bp, tregs, MII_BMCR); 540 if (bp->sw_bmsr & BMSR_LSTATUS) { 541 printk(KERN_INFO "%s: Link is now up at %s.\n", 542 bp->dev->name, 543 (bp->sw_bmcr & BMCR_SPEED100) ? 544 "100baseT" : "10baseT"); 545 bp->timer_state = asleep; 546 restart_timer = 0; 547 } else { 548 if (bp->timer_ticks >= 4) { 549 int ret; 550 551 ret = try_next_permutation(bp, tregs); 552 if (ret == -1) { 553 printk(KERN_ERR "%s: Link down, cable problem?\n", 554 bp->dev->name); 555 ret = bigmac_init_hw(bp, 0); 556 if (ret) { 557 printk(KERN_ERR "%s: Error, cannot re-init the " 558 "BigMAC.\n", bp->dev->name); 559 } 560 return; 561 } 562 bp->timer_ticks = 0; 563 restart_timer = 1; 564 } else { 565 restart_timer = 1; 566 } 567 } 568 } else { 569 /* Can't happens.... */ 570 printk(KERN_ERR "%s: Aieee, link timer is asleep but we got one anyways!\n", 571 bp->dev->name); 572 restart_timer = 0; 573 bp->timer_ticks = 0; 574 bp->timer_state = asleep; /* foo on you */ 575 } 576 577 if (restart_timer != 0) { 578 bp->bigmac_timer.expires = jiffies + ((12 * HZ)/10); /* 1.2 sec. */ 579 add_timer(&bp->bigmac_timer); 580 } 581 } 582 583 /* Well, really we just force the chip into 100baseT then 584 * 10baseT, each time checking for a link status. 585 */ 586 static void bigmac_begin_auto_negotiation(struct bigmac *bp) 587 { 588 void __iomem *tregs = bp->tregs; 589 int timeout; 590 591 /* Grab new software copies of PHY registers. */ 592 bp->sw_bmsr = bigmac_tcvr_read(bp, tregs, MII_BMSR); 593 bp->sw_bmcr = bigmac_tcvr_read(bp, tregs, MII_BMCR); 594 595 /* Reset the PHY. */ 596 bp->sw_bmcr = (BMCR_ISOLATE | BMCR_PDOWN | BMCR_LOOPBACK); 597 bigmac_tcvr_write(bp, tregs, MII_BMCR, bp->sw_bmcr); 598 bp->sw_bmcr = (BMCR_RESET); 599 bigmac_tcvr_write(bp, tregs, MII_BMCR, bp->sw_bmcr); 600 601 timeout = 64; 602 while (--timeout) { 603 bp->sw_bmcr = bigmac_tcvr_read(bp, tregs, MII_BMCR); 604 if ((bp->sw_bmcr & BMCR_RESET) == 0) 605 break; 606 udelay(20); 607 } 608 if (timeout == 0) 609 printk(KERN_ERR "%s: PHY reset failed.\n", bp->dev->name); 610 611 bp->sw_bmcr = bigmac_tcvr_read(bp, tregs, MII_BMCR); 612 613 /* First we try 100baseT. */ 614 bp->sw_bmcr |= BMCR_SPEED100; 615 bigmac_tcvr_write(bp, tregs, MII_BMCR, bp->sw_bmcr); 616 617 bp->timer_state = ltrywait; 618 bp->timer_ticks = 0; 619 bp->bigmac_timer.expires = jiffies + (12 * HZ) / 10; 620 bp->bigmac_timer.data = (unsigned long) bp; 621 bp->bigmac_timer.function = bigmac_timer; 622 add_timer(&bp->bigmac_timer); 623 } 624 625 static int bigmac_init_hw(struct bigmac *bp, int from_irq) 626 { 627 void __iomem *gregs = bp->gregs; 628 void __iomem *cregs = bp->creg; 629 void __iomem *bregs = bp->bregs; 630 unsigned char *e = &bp->dev->dev_addr[0]; 631 632 /* Latch current counters into statistics. */ 633 bigmac_get_counters(bp, bregs); 634 635 /* Reset QEC. */ 636 qec_global_reset(gregs); 637 638 /* Init QEC. */ 639 qec_init(bp); 640 641 /* Alloc and reset the tx/rx descriptor chains. */ 642 bigmac_init_rings(bp, from_irq); 643 644 /* Initialize the PHY. */ 645 bigmac_tcvr_init(bp); 646 647 /* Stop transmitter and receiver. */ 648 bigmac_stop(bp); 649 650 /* Set hardware ethernet address. */ 651 sbus_writel(((e[4] << 8) | e[5]), bregs + BMAC_MACADDR2); 652 sbus_writel(((e[2] << 8) | e[3]), bregs + BMAC_MACADDR1); 653 sbus_writel(((e[0] << 8) | e[1]), bregs + BMAC_MACADDR0); 654 655 /* Clear the hash table until mc upload occurs. */ 656 sbus_writel(0, bregs + BMAC_HTABLE3); 657 sbus_writel(0, bregs + BMAC_HTABLE2); 658 sbus_writel(0, bregs + BMAC_HTABLE1); 659 sbus_writel(0, bregs + BMAC_HTABLE0); 660 661 /* Enable Big Mac hash table filter. */ 662 sbus_writel(BIGMAC_RXCFG_HENABLE | BIGMAC_RXCFG_FIFO, 663 bregs + BMAC_RXCFG); 664 udelay(20); 665 666 /* Ok, configure the Big Mac transmitter. */ 667 sbus_writel(BIGMAC_TXCFG_FIFO, bregs + BMAC_TXCFG); 668 669 /* The HME docs recommend to use the 10LSB of our MAC here. */ 670 sbus_writel(((e[5] | e[4] << 8) & 0x3ff), 671 bregs + BMAC_RSEED); 672 673 /* Enable the output drivers no matter what. */ 674 sbus_writel(BIGMAC_XCFG_ODENABLE | BIGMAC_XCFG_RESV, 675 bregs + BMAC_XIFCFG); 676 677 /* Tell the QEC where the ring descriptors are. */ 678 sbus_writel(bp->bblock_dvma + bib_offset(be_rxd, 0), 679 cregs + CREG_RXDS); 680 sbus_writel(bp->bblock_dvma + bib_offset(be_txd, 0), 681 cregs + CREG_TXDS); 682 683 /* Setup the FIFO pointers into QEC local memory. */ 684 sbus_writel(0, cregs + CREG_RXRBUFPTR); 685 sbus_writel(0, cregs + CREG_RXWBUFPTR); 686 sbus_writel(sbus_readl(gregs + GLOB_RSIZE), 687 cregs + CREG_TXRBUFPTR); 688 sbus_writel(sbus_readl(gregs + GLOB_RSIZE), 689 cregs + CREG_TXWBUFPTR); 690 691 /* Tell bigmac what interrupts we don't want to hear about. */ 692 sbus_writel(BIGMAC_IMASK_GOTFRAME | BIGMAC_IMASK_SENTFRAME, 693 bregs + BMAC_IMASK); 694 695 /* Enable the various other irq's. */ 696 sbus_writel(0, cregs + CREG_RIMASK); 697 sbus_writel(0, cregs + CREG_TIMASK); 698 sbus_writel(0, cregs + CREG_QMASK); 699 sbus_writel(0, cregs + CREG_BMASK); 700 701 /* Set jam size to a reasonable default. */ 702 sbus_writel(DEFAULT_JAMSIZE, bregs + BMAC_JSIZE); 703 704 /* Clear collision counter. */ 705 sbus_writel(0, cregs + CREG_CCNT); 706 707 /* Enable transmitter and receiver. */ 708 sbus_writel(sbus_readl(bregs + BMAC_TXCFG) | BIGMAC_TXCFG_ENABLE, 709 bregs + BMAC_TXCFG); 710 sbus_writel(sbus_readl(bregs + BMAC_RXCFG) | BIGMAC_RXCFG_ENABLE, 711 bregs + BMAC_RXCFG); 712 713 /* Ok, start detecting link speed/duplex. */ 714 bigmac_begin_auto_negotiation(bp); 715 716 /* Success. */ 717 return 0; 718 } 719 720 /* Error interrupts get sent here. */ 721 static void bigmac_is_medium_rare(struct bigmac *bp, u32 qec_status, u32 bmac_status) 722 { 723 printk(KERN_ERR "bigmac_is_medium_rare: "); 724 if (qec_status & (GLOB_STAT_ER | GLOB_STAT_BM)) { 725 if (qec_status & GLOB_STAT_ER) 726 printk("QEC_ERROR, "); 727 if (qec_status & GLOB_STAT_BM) 728 printk("QEC_BMAC_ERROR, "); 729 } 730 if (bmac_status & CREG_STAT_ERRORS) { 731 if (bmac_status & CREG_STAT_BERROR) 732 printk("BMAC_ERROR, "); 733 if (bmac_status & CREG_STAT_TXDERROR) 734 printk("TXD_ERROR, "); 735 if (bmac_status & CREG_STAT_TXLERR) 736 printk("TX_LATE_ERROR, "); 737 if (bmac_status & CREG_STAT_TXPERR) 738 printk("TX_PARITY_ERROR, "); 739 if (bmac_status & CREG_STAT_TXSERR) 740 printk("TX_SBUS_ERROR, "); 741 742 if (bmac_status & CREG_STAT_RXDROP) 743 printk("RX_DROP_ERROR, "); 744 745 if (bmac_status & CREG_STAT_RXSMALL) 746 printk("RX_SMALL_ERROR, "); 747 if (bmac_status & CREG_STAT_RXLERR) 748 printk("RX_LATE_ERROR, "); 749 if (bmac_status & CREG_STAT_RXPERR) 750 printk("RX_PARITY_ERROR, "); 751 if (bmac_status & CREG_STAT_RXSERR) 752 printk("RX_SBUS_ERROR, "); 753 } 754 755 printk(" RESET\n"); 756 bigmac_init_hw(bp, 1); 757 } 758 759 /* BigMAC transmit complete service routines. */ 760 static void bigmac_tx(struct bigmac *bp) 761 { 762 struct be_txd *txbase = &bp->bmac_block->be_txd[0]; 763 struct net_device *dev = bp->dev; 764 int elem; 765 766 spin_lock(&bp->lock); 767 768 elem = bp->tx_old; 769 DTX(("bigmac_tx: tx_old[%d] ", elem)); 770 while (elem != bp->tx_new) { 771 struct sk_buff *skb; 772 struct be_txd *this = &txbase[elem]; 773 774 DTX(("this(%p) [flags(%08x)addr(%08x)]", 775 this, this->tx_flags, this->tx_addr)); 776 777 if (this->tx_flags & TXD_OWN) 778 break; 779 skb = bp->tx_skbs[elem]; 780 bp->enet_stats.tx_packets++; 781 bp->enet_stats.tx_bytes += skb->len; 782 dma_unmap_single(&bp->bigmac_op->dev, 783 this->tx_addr, skb->len, 784 DMA_TO_DEVICE); 785 786 DTX(("skb(%p) ", skb)); 787 bp->tx_skbs[elem] = NULL; 788 dev_kfree_skb_irq(skb); 789 790 elem = NEXT_TX(elem); 791 } 792 DTX((" DONE, tx_old=%d\n", elem)); 793 bp->tx_old = elem; 794 795 if (netif_queue_stopped(dev) && 796 TX_BUFFS_AVAIL(bp) > 0) 797 netif_wake_queue(bp->dev); 798 799 spin_unlock(&bp->lock); 800 } 801 802 /* BigMAC receive complete service routines. */ 803 static void bigmac_rx(struct bigmac *bp) 804 { 805 struct be_rxd *rxbase = &bp->bmac_block->be_rxd[0]; 806 struct be_rxd *this; 807 int elem = bp->rx_new, drops = 0; 808 u32 flags; 809 810 this = &rxbase[elem]; 811 while (!((flags = this->rx_flags) & RXD_OWN)) { 812 struct sk_buff *skb; 813 int len = (flags & RXD_LENGTH); /* FCS not included */ 814 815 /* Check for errors. */ 816 if (len < ETH_ZLEN) { 817 bp->enet_stats.rx_errors++; 818 bp->enet_stats.rx_length_errors++; 819 820 drop_it: 821 /* Return it to the BigMAC. */ 822 bp->enet_stats.rx_dropped++; 823 this->rx_flags = 824 (RXD_OWN | ((RX_BUF_ALLOC_SIZE - 34) & RXD_LENGTH)); 825 goto next; 826 } 827 skb = bp->rx_skbs[elem]; 828 if (len > RX_COPY_THRESHOLD) { 829 struct sk_buff *new_skb; 830 831 /* Now refill the entry, if we can. */ 832 new_skb = big_mac_alloc_skb(RX_BUF_ALLOC_SIZE, GFP_ATOMIC); 833 if (new_skb == NULL) { 834 drops++; 835 goto drop_it; 836 } 837 dma_unmap_single(&bp->bigmac_op->dev, 838 this->rx_addr, 839 RX_BUF_ALLOC_SIZE - 34, 840 DMA_FROM_DEVICE); 841 bp->rx_skbs[elem] = new_skb; 842 new_skb->dev = bp->dev; 843 skb_put(new_skb, ETH_FRAME_LEN); 844 skb_reserve(new_skb, 34); 845 this->rx_addr = 846 dma_map_single(&bp->bigmac_op->dev, 847 new_skb->data, 848 RX_BUF_ALLOC_SIZE - 34, 849 DMA_FROM_DEVICE); 850 this->rx_flags = 851 (RXD_OWN | ((RX_BUF_ALLOC_SIZE - 34) & RXD_LENGTH)); 852 853 /* Trim the original skb for the netif. */ 854 skb_trim(skb, len); 855 } else { 856 struct sk_buff *copy_skb = dev_alloc_skb(len + 2); 857 858 if (copy_skb == NULL) { 859 drops++; 860 goto drop_it; 861 } 862 skb_reserve(copy_skb, 2); 863 skb_put(copy_skb, len); 864 dma_sync_single_for_cpu(&bp->bigmac_op->dev, 865 this->rx_addr, len, 866 DMA_FROM_DEVICE); 867 skb_copy_to_linear_data(copy_skb, (unsigned char *)skb->data, len); 868 dma_sync_single_for_device(&bp->bigmac_op->dev, 869 this->rx_addr, len, 870 DMA_FROM_DEVICE); 871 872 /* Reuse original ring buffer. */ 873 this->rx_flags = 874 (RXD_OWN | ((RX_BUF_ALLOC_SIZE - 34) & RXD_LENGTH)); 875 876 skb = copy_skb; 877 } 878 879 /* No checksums done by the BigMAC ;-( */ 880 skb->protocol = eth_type_trans(skb, bp->dev); 881 netif_rx(skb); 882 bp->enet_stats.rx_packets++; 883 bp->enet_stats.rx_bytes += len; 884 next: 885 elem = NEXT_RX(elem); 886 this = &rxbase[elem]; 887 } 888 bp->rx_new = elem; 889 if (drops) 890 printk(KERN_NOTICE "%s: Memory squeeze, deferring packet.\n", bp->dev->name); 891 } 892 893 static irqreturn_t bigmac_interrupt(int irq, void *dev_id) 894 { 895 struct bigmac *bp = (struct bigmac *) dev_id; 896 u32 qec_status, bmac_status; 897 898 DIRQ(("bigmac_interrupt: ")); 899 900 /* Latch status registers now. */ 901 bmac_status = sbus_readl(bp->creg + CREG_STAT); 902 qec_status = sbus_readl(bp->gregs + GLOB_STAT); 903 904 DIRQ(("qec_status=%08x bmac_status=%08x\n", qec_status, bmac_status)); 905 if ((qec_status & (GLOB_STAT_ER | GLOB_STAT_BM)) || 906 (bmac_status & CREG_STAT_ERRORS)) 907 bigmac_is_medium_rare(bp, qec_status, bmac_status); 908 909 if (bmac_status & CREG_STAT_TXIRQ) 910 bigmac_tx(bp); 911 912 if (bmac_status & CREG_STAT_RXIRQ) 913 bigmac_rx(bp); 914 915 return IRQ_HANDLED; 916 } 917 918 static int bigmac_open(struct net_device *dev) 919 { 920 struct bigmac *bp = netdev_priv(dev); 921 int ret; 922 923 ret = request_irq(dev->irq, bigmac_interrupt, IRQF_SHARED, dev->name, bp); 924 if (ret) { 925 printk(KERN_ERR "BIGMAC: Can't order irq %d to go.\n", dev->irq); 926 return ret; 927 } 928 init_timer(&bp->bigmac_timer); 929 ret = bigmac_init_hw(bp, 0); 930 if (ret) 931 free_irq(dev->irq, bp); 932 return ret; 933 } 934 935 static int bigmac_close(struct net_device *dev) 936 { 937 struct bigmac *bp = netdev_priv(dev); 938 939 del_timer(&bp->bigmac_timer); 940 bp->timer_state = asleep; 941 bp->timer_ticks = 0; 942 943 bigmac_stop(bp); 944 bigmac_clean_rings(bp); 945 free_irq(dev->irq, bp); 946 return 0; 947 } 948 949 static void bigmac_tx_timeout(struct net_device *dev) 950 { 951 struct bigmac *bp = netdev_priv(dev); 952 953 bigmac_init_hw(bp, 0); 954 netif_wake_queue(dev); 955 } 956 957 /* Put a packet on the wire. */ 958 static int bigmac_start_xmit(struct sk_buff *skb, struct net_device *dev) 959 { 960 struct bigmac *bp = netdev_priv(dev); 961 int len, entry; 962 u32 mapping; 963 964 len = skb->len; 965 mapping = dma_map_single(&bp->bigmac_op->dev, skb->data, 966 len, DMA_TO_DEVICE); 967 968 /* Avoid a race... */ 969 spin_lock_irq(&bp->lock); 970 entry = bp->tx_new; 971 DTX(("bigmac_start_xmit: len(%d) entry(%d)\n", len, entry)); 972 bp->bmac_block->be_txd[entry].tx_flags = TXD_UPDATE; 973 bp->tx_skbs[entry] = skb; 974 bp->bmac_block->be_txd[entry].tx_addr = mapping; 975 bp->bmac_block->be_txd[entry].tx_flags = 976 (TXD_OWN | TXD_SOP | TXD_EOP | (len & TXD_LENGTH)); 977 bp->tx_new = NEXT_TX(entry); 978 if (TX_BUFFS_AVAIL(bp) <= 0) 979 netif_stop_queue(dev); 980 spin_unlock_irq(&bp->lock); 981 982 /* Get it going. */ 983 sbus_writel(CREG_CTRL_TWAKEUP, bp->creg + CREG_CTRL); 984 985 986 return NETDEV_TX_OK; 987 } 988 989 static struct net_device_stats *bigmac_get_stats(struct net_device *dev) 990 { 991 struct bigmac *bp = netdev_priv(dev); 992 993 bigmac_get_counters(bp, bp->bregs); 994 return &bp->enet_stats; 995 } 996 997 static void bigmac_set_multicast(struct net_device *dev) 998 { 999 struct bigmac *bp = netdev_priv(dev); 1000 void __iomem *bregs = bp->bregs; 1001 struct netdev_hw_addr *ha; 1002 int i; 1003 u32 tmp, crc; 1004 1005 /* Disable the receiver. The bit self-clears when 1006 * the operation is complete. 1007 */ 1008 tmp = sbus_readl(bregs + BMAC_RXCFG); 1009 tmp &= ~(BIGMAC_RXCFG_ENABLE); 1010 sbus_writel(tmp, bregs + BMAC_RXCFG); 1011 while ((sbus_readl(bregs + BMAC_RXCFG) & BIGMAC_RXCFG_ENABLE) != 0) 1012 udelay(20); 1013 1014 if ((dev->flags & IFF_ALLMULTI) || (netdev_mc_count(dev) > 64)) { 1015 sbus_writel(0xffff, bregs + BMAC_HTABLE0); 1016 sbus_writel(0xffff, bregs + BMAC_HTABLE1); 1017 sbus_writel(0xffff, bregs + BMAC_HTABLE2); 1018 sbus_writel(0xffff, bregs + BMAC_HTABLE3); 1019 } else if (dev->flags & IFF_PROMISC) { 1020 tmp = sbus_readl(bregs + BMAC_RXCFG); 1021 tmp |= BIGMAC_RXCFG_PMISC; 1022 sbus_writel(tmp, bregs + BMAC_RXCFG); 1023 } else { 1024 u16 hash_table[4]; 1025 1026 for (i = 0; i < 4; i++) 1027 hash_table[i] = 0; 1028 1029 netdev_for_each_mc_addr(ha, dev) { 1030 crc = ether_crc_le(6, ha->addr); 1031 crc >>= 26; 1032 hash_table[crc >> 4] |= 1 << (crc & 0xf); 1033 } 1034 sbus_writel(hash_table[0], bregs + BMAC_HTABLE0); 1035 sbus_writel(hash_table[1], bregs + BMAC_HTABLE1); 1036 sbus_writel(hash_table[2], bregs + BMAC_HTABLE2); 1037 sbus_writel(hash_table[3], bregs + BMAC_HTABLE3); 1038 } 1039 1040 /* Re-enable the receiver. */ 1041 tmp = sbus_readl(bregs + BMAC_RXCFG); 1042 tmp |= BIGMAC_RXCFG_ENABLE; 1043 sbus_writel(tmp, bregs + BMAC_RXCFG); 1044 } 1045 1046 /* Ethtool support... */ 1047 static void bigmac_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info) 1048 { 1049 strcpy(info->driver, "sunbmac"); 1050 strcpy(info->version, "2.0"); 1051 } 1052 1053 static u32 bigmac_get_link(struct net_device *dev) 1054 { 1055 struct bigmac *bp = netdev_priv(dev); 1056 1057 spin_lock_irq(&bp->lock); 1058 bp->sw_bmsr = bigmac_tcvr_read(bp, bp->tregs, MII_BMSR); 1059 spin_unlock_irq(&bp->lock); 1060 1061 return (bp->sw_bmsr & BMSR_LSTATUS); 1062 } 1063 1064 static const struct ethtool_ops bigmac_ethtool_ops = { 1065 .get_drvinfo = bigmac_get_drvinfo, 1066 .get_link = bigmac_get_link, 1067 }; 1068 1069 static const struct net_device_ops bigmac_ops = { 1070 .ndo_open = bigmac_open, 1071 .ndo_stop = bigmac_close, 1072 .ndo_start_xmit = bigmac_start_xmit, 1073 .ndo_get_stats = bigmac_get_stats, 1074 .ndo_set_rx_mode = bigmac_set_multicast, 1075 .ndo_tx_timeout = bigmac_tx_timeout, 1076 .ndo_change_mtu = eth_change_mtu, 1077 .ndo_set_mac_address = eth_mac_addr, 1078 .ndo_validate_addr = eth_validate_addr, 1079 }; 1080 1081 static int __devinit bigmac_ether_init(struct platform_device *op, 1082 struct platform_device *qec_op) 1083 { 1084 static int version_printed; 1085 struct net_device *dev; 1086 u8 bsizes, bsizes_more; 1087 struct bigmac *bp; 1088 int i; 1089 1090 /* Get a new device struct for this interface. */ 1091 dev = alloc_etherdev(sizeof(struct bigmac)); 1092 if (!dev) 1093 return -ENOMEM; 1094 1095 if (version_printed++ == 0) 1096 printk(KERN_INFO "%s", version); 1097 1098 for (i = 0; i < 6; i++) 1099 dev->dev_addr[i] = idprom->id_ethaddr[i]; 1100 1101 /* Setup softc, with backpointers to QEC and BigMAC SBUS device structs. */ 1102 bp = netdev_priv(dev); 1103 bp->qec_op = qec_op; 1104 bp->bigmac_op = op; 1105 1106 SET_NETDEV_DEV(dev, &op->dev); 1107 1108 spin_lock_init(&bp->lock); 1109 1110 /* Map in QEC global control registers. */ 1111 bp->gregs = of_ioremap(&qec_op->resource[0], 0, 1112 GLOB_REG_SIZE, "BigMAC QEC GLobal Regs"); 1113 if (!bp->gregs) { 1114 printk(KERN_ERR "BIGMAC: Cannot map QEC global registers.\n"); 1115 goto fail_and_cleanup; 1116 } 1117 1118 /* Make sure QEC is in BigMAC mode. */ 1119 if ((sbus_readl(bp->gregs + GLOB_CTRL) & 0xf0000000) != GLOB_CTRL_BMODE) { 1120 printk(KERN_ERR "BigMAC: AIEEE, QEC is not in BigMAC mode!\n"); 1121 goto fail_and_cleanup; 1122 } 1123 1124 /* Reset the QEC. */ 1125 if (qec_global_reset(bp->gregs)) 1126 goto fail_and_cleanup; 1127 1128 /* Get supported SBUS burst sizes. */ 1129 bsizes = of_getintprop_default(qec_op->dev.of_node, "burst-sizes", 0xff); 1130 bsizes_more = of_getintprop_default(qec_op->dev.of_node, "burst-sizes", 0xff); 1131 1132 bsizes &= 0xff; 1133 if (bsizes_more != 0xff) 1134 bsizes &= bsizes_more; 1135 if (bsizes == 0xff || (bsizes & DMA_BURST16) == 0 || 1136 (bsizes & DMA_BURST32) == 0) 1137 bsizes = (DMA_BURST32 - 1); 1138 bp->bigmac_bursts = bsizes; 1139 1140 /* Perform QEC initialization. */ 1141 qec_init(bp); 1142 1143 /* Map in the BigMAC channel registers. */ 1144 bp->creg = of_ioremap(&op->resource[0], 0, 1145 CREG_REG_SIZE, "BigMAC QEC Channel Regs"); 1146 if (!bp->creg) { 1147 printk(KERN_ERR "BIGMAC: Cannot map QEC channel registers.\n"); 1148 goto fail_and_cleanup; 1149 } 1150 1151 /* Map in the BigMAC control registers. */ 1152 bp->bregs = of_ioremap(&op->resource[1], 0, 1153 BMAC_REG_SIZE, "BigMAC Primary Regs"); 1154 if (!bp->bregs) { 1155 printk(KERN_ERR "BIGMAC: Cannot map BigMAC primary registers.\n"); 1156 goto fail_and_cleanup; 1157 } 1158 1159 /* Map in the BigMAC transceiver registers, this is how you poke at 1160 * the BigMAC's PHY. 1161 */ 1162 bp->tregs = of_ioremap(&op->resource[2], 0, 1163 TCVR_REG_SIZE, "BigMAC Transceiver Regs"); 1164 if (!bp->tregs) { 1165 printk(KERN_ERR "BIGMAC: Cannot map BigMAC transceiver registers.\n"); 1166 goto fail_and_cleanup; 1167 } 1168 1169 /* Stop the BigMAC. */ 1170 bigmac_stop(bp); 1171 1172 /* Allocate transmit/receive descriptor DVMA block. */ 1173 bp->bmac_block = dma_alloc_coherent(&bp->bigmac_op->dev, 1174 PAGE_SIZE, 1175 &bp->bblock_dvma, GFP_ATOMIC); 1176 if (bp->bmac_block == NULL || bp->bblock_dvma == 0) { 1177 printk(KERN_ERR "BIGMAC: Cannot allocate consistent DMA.\n"); 1178 goto fail_and_cleanup; 1179 } 1180 1181 /* Get the board revision of this BigMAC. */ 1182 bp->board_rev = of_getintprop_default(bp->bigmac_op->dev.of_node, 1183 "board-version", 1); 1184 1185 /* Init auto-negotiation timer state. */ 1186 init_timer(&bp->bigmac_timer); 1187 bp->timer_state = asleep; 1188 bp->timer_ticks = 0; 1189 1190 /* Backlink to generic net device struct. */ 1191 bp->dev = dev; 1192 1193 /* Set links to our BigMAC open and close routines. */ 1194 dev->ethtool_ops = &bigmac_ethtool_ops; 1195 dev->netdev_ops = &bigmac_ops; 1196 dev->watchdog_timeo = 5*HZ; 1197 1198 /* Finish net device registration. */ 1199 dev->irq = bp->bigmac_op->archdata.irqs[0]; 1200 dev->dma = 0; 1201 1202 if (register_netdev(dev)) { 1203 printk(KERN_ERR "BIGMAC: Cannot register device.\n"); 1204 goto fail_and_cleanup; 1205 } 1206 1207 dev_set_drvdata(&bp->bigmac_op->dev, bp); 1208 1209 printk(KERN_INFO "%s: BigMAC 100baseT Ethernet %pM\n", 1210 dev->name, dev->dev_addr); 1211 1212 return 0; 1213 1214 fail_and_cleanup: 1215 /* Something went wrong, undo whatever we did so far. */ 1216 /* Free register mappings if any. */ 1217 if (bp->gregs) 1218 of_iounmap(&qec_op->resource[0], bp->gregs, GLOB_REG_SIZE); 1219 if (bp->creg) 1220 of_iounmap(&op->resource[0], bp->creg, CREG_REG_SIZE); 1221 if (bp->bregs) 1222 of_iounmap(&op->resource[1], bp->bregs, BMAC_REG_SIZE); 1223 if (bp->tregs) 1224 of_iounmap(&op->resource[2], bp->tregs, TCVR_REG_SIZE); 1225 1226 if (bp->bmac_block) 1227 dma_free_coherent(&bp->bigmac_op->dev, 1228 PAGE_SIZE, 1229 bp->bmac_block, 1230 bp->bblock_dvma); 1231 1232 /* This also frees the co-located private data */ 1233 free_netdev(dev); 1234 return -ENODEV; 1235 } 1236 1237 /* QEC can be the parent of either QuadEthernet or a BigMAC. We want 1238 * the latter. 1239 */ 1240 static int __devinit bigmac_sbus_probe(struct platform_device *op) 1241 { 1242 struct device *parent = op->dev.parent; 1243 struct platform_device *qec_op; 1244 1245 qec_op = to_platform_device(parent); 1246 1247 return bigmac_ether_init(op, qec_op); 1248 } 1249 1250 static int __devexit bigmac_sbus_remove(struct platform_device *op) 1251 { 1252 struct bigmac *bp = dev_get_drvdata(&op->dev); 1253 struct device *parent = op->dev.parent; 1254 struct net_device *net_dev = bp->dev; 1255 struct platform_device *qec_op; 1256 1257 qec_op = to_platform_device(parent); 1258 1259 unregister_netdev(net_dev); 1260 1261 of_iounmap(&qec_op->resource[0], bp->gregs, GLOB_REG_SIZE); 1262 of_iounmap(&op->resource[0], bp->creg, CREG_REG_SIZE); 1263 of_iounmap(&op->resource[1], bp->bregs, BMAC_REG_SIZE); 1264 of_iounmap(&op->resource[2], bp->tregs, TCVR_REG_SIZE); 1265 dma_free_coherent(&op->dev, 1266 PAGE_SIZE, 1267 bp->bmac_block, 1268 bp->bblock_dvma); 1269 1270 free_netdev(net_dev); 1271 1272 dev_set_drvdata(&op->dev, NULL); 1273 1274 return 0; 1275 } 1276 1277 static const struct of_device_id bigmac_sbus_match[] = { 1278 { 1279 .name = "be", 1280 }, 1281 {}, 1282 }; 1283 1284 MODULE_DEVICE_TABLE(of, bigmac_sbus_match); 1285 1286 static struct platform_driver bigmac_sbus_driver = { 1287 .driver = { 1288 .name = "sunbmac", 1289 .owner = THIS_MODULE, 1290 .of_match_table = bigmac_sbus_match, 1291 }, 1292 .probe = bigmac_sbus_probe, 1293 .remove = __devexit_p(bigmac_sbus_remove), 1294 }; 1295 1296 static int __init bigmac_init(void) 1297 { 1298 return platform_driver_register(&bigmac_sbus_driver); 1299 } 1300 1301 static void __exit bigmac_exit(void) 1302 { 1303 platform_driver_unregister(&bigmac_sbus_driver); 1304 } 1305 1306 module_init(bigmac_init); 1307 module_exit(bigmac_exit); 1308