1 /* sunbmac.c: Driver for Sparc BigMAC 100baseT ethernet adapters. 2 * 3 * Copyright (C) 1997, 1998, 1999, 2003, 2008 David S. Miller (davem@davemloft.net) 4 */ 5 6 #include <linux/module.h> 7 8 #include <linux/kernel.h> 9 #include <linux/types.h> 10 #include <linux/fcntl.h> 11 #include <linux/interrupt.h> 12 #include <linux/ioport.h> 13 #include <linux/in.h> 14 #include <linux/string.h> 15 #include <linux/delay.h> 16 #include <linux/init.h> 17 #include <linux/crc32.h> 18 #include <linux/errno.h> 19 #include <linux/ethtool.h> 20 #include <linux/mii.h> 21 #include <linux/netdevice.h> 22 #include <linux/etherdevice.h> 23 #include <linux/skbuff.h> 24 #include <linux/bitops.h> 25 #include <linux/dma-mapping.h> 26 #include <linux/of.h> 27 #include <linux/of_device.h> 28 #include <linux/gfp.h> 29 30 #include <asm/auxio.h> 31 #include <asm/byteorder.h> 32 #include <asm/dma.h> 33 #include <asm/idprom.h> 34 #include <asm/io.h> 35 #include <asm/openprom.h> 36 #include <asm/oplib.h> 37 #include <asm/pgtable.h> 38 39 #include "sunbmac.h" 40 41 #define DRV_NAME "sunbmac" 42 #define DRV_VERSION "2.1" 43 #define DRV_RELDATE "August 26, 2008" 44 #define DRV_AUTHOR "David S. Miller (davem@davemloft.net)" 45 46 static char version[] = 47 DRV_NAME ".c:v" DRV_VERSION " " DRV_RELDATE " " DRV_AUTHOR "\n"; 48 49 MODULE_VERSION(DRV_VERSION); 50 MODULE_AUTHOR(DRV_AUTHOR); 51 MODULE_DESCRIPTION("Sun BigMAC 100baseT ethernet driver"); 52 MODULE_LICENSE("GPL"); 53 54 #undef DEBUG_PROBE 55 #undef DEBUG_TX 56 #undef DEBUG_IRQ 57 58 #ifdef DEBUG_PROBE 59 #define DP(x) printk x 60 #else 61 #define DP(x) 62 #endif 63 64 #ifdef DEBUG_TX 65 #define DTX(x) printk x 66 #else 67 #define DTX(x) 68 #endif 69 70 #ifdef DEBUG_IRQ 71 #define DIRQ(x) printk x 72 #else 73 #define DIRQ(x) 74 #endif 75 76 #define DEFAULT_JAMSIZE 4 /* Toe jam */ 77 78 #define QEC_RESET_TRIES 200 79 80 static int qec_global_reset(void __iomem *gregs) 81 { 82 int tries = QEC_RESET_TRIES; 83 84 sbus_writel(GLOB_CTRL_RESET, gregs + GLOB_CTRL); 85 while (--tries) { 86 if (sbus_readl(gregs + GLOB_CTRL) & GLOB_CTRL_RESET) { 87 udelay(20); 88 continue; 89 } 90 break; 91 } 92 if (tries) 93 return 0; 94 printk(KERN_ERR "BigMAC: Cannot reset the QEC.\n"); 95 return -1; 96 } 97 98 static void qec_init(struct bigmac *bp) 99 { 100 struct platform_device *qec_op = bp->qec_op; 101 void __iomem *gregs = bp->gregs; 102 u8 bsizes = bp->bigmac_bursts; 103 u32 regval; 104 105 /* 64byte bursts do not work at the moment, do 106 * not even try to enable them. -DaveM 107 */ 108 if (bsizes & DMA_BURST32) 109 regval = GLOB_CTRL_B32; 110 else 111 regval = GLOB_CTRL_B16; 112 sbus_writel(regval | GLOB_CTRL_BMODE, gregs + GLOB_CTRL); 113 sbus_writel(GLOB_PSIZE_2048, gregs + GLOB_PSIZE); 114 115 /* All of memsize is given to bigmac. */ 116 sbus_writel(resource_size(&qec_op->resource[1]), 117 gregs + GLOB_MSIZE); 118 119 /* Half to the transmitter, half to the receiver. */ 120 sbus_writel(resource_size(&qec_op->resource[1]) >> 1, 121 gregs + GLOB_TSIZE); 122 sbus_writel(resource_size(&qec_op->resource[1]) >> 1, 123 gregs + GLOB_RSIZE); 124 } 125 126 #define TX_RESET_TRIES 32 127 #define RX_RESET_TRIES 32 128 129 static void bigmac_tx_reset(void __iomem *bregs) 130 { 131 int tries = TX_RESET_TRIES; 132 133 sbus_writel(0, bregs + BMAC_TXCFG); 134 135 /* The fifo threshold bit is read-only and does 136 * not clear. -DaveM 137 */ 138 while ((sbus_readl(bregs + BMAC_TXCFG) & ~(BIGMAC_TXCFG_FIFO)) != 0 && 139 --tries != 0) 140 udelay(20); 141 142 if (!tries) { 143 printk(KERN_ERR "BIGMAC: Transmitter will not reset.\n"); 144 printk(KERN_ERR "BIGMAC: tx_cfg is %08x\n", 145 sbus_readl(bregs + BMAC_TXCFG)); 146 } 147 } 148 149 static void bigmac_rx_reset(void __iomem *bregs) 150 { 151 int tries = RX_RESET_TRIES; 152 153 sbus_writel(0, bregs + BMAC_RXCFG); 154 while (sbus_readl(bregs + BMAC_RXCFG) && --tries) 155 udelay(20); 156 157 if (!tries) { 158 printk(KERN_ERR "BIGMAC: Receiver will not reset.\n"); 159 printk(KERN_ERR "BIGMAC: rx_cfg is %08x\n", 160 sbus_readl(bregs + BMAC_RXCFG)); 161 } 162 } 163 164 /* Reset the transmitter and receiver. */ 165 static void bigmac_stop(struct bigmac *bp) 166 { 167 bigmac_tx_reset(bp->bregs); 168 bigmac_rx_reset(bp->bregs); 169 } 170 171 static void bigmac_get_counters(struct bigmac *bp, void __iomem *bregs) 172 { 173 struct net_device_stats *stats = &bp->enet_stats; 174 175 stats->rx_crc_errors += sbus_readl(bregs + BMAC_RCRCECTR); 176 sbus_writel(0, bregs + BMAC_RCRCECTR); 177 178 stats->rx_frame_errors += sbus_readl(bregs + BMAC_UNALECTR); 179 sbus_writel(0, bregs + BMAC_UNALECTR); 180 181 stats->rx_length_errors += sbus_readl(bregs + BMAC_GLECTR); 182 sbus_writel(0, bregs + BMAC_GLECTR); 183 184 stats->tx_aborted_errors += sbus_readl(bregs + BMAC_EXCTR); 185 186 stats->collisions += 187 (sbus_readl(bregs + BMAC_EXCTR) + 188 sbus_readl(bregs + BMAC_LTCTR)); 189 sbus_writel(0, bregs + BMAC_EXCTR); 190 sbus_writel(0, bregs + BMAC_LTCTR); 191 } 192 193 static void bigmac_clean_rings(struct bigmac *bp) 194 { 195 int i; 196 197 for (i = 0; i < RX_RING_SIZE; i++) { 198 if (bp->rx_skbs[i] != NULL) { 199 dev_kfree_skb_any(bp->rx_skbs[i]); 200 bp->rx_skbs[i] = NULL; 201 } 202 } 203 204 for (i = 0; i < TX_RING_SIZE; i++) { 205 if (bp->tx_skbs[i] != NULL) { 206 dev_kfree_skb_any(bp->tx_skbs[i]); 207 bp->tx_skbs[i] = NULL; 208 } 209 } 210 } 211 212 static void bigmac_init_rings(struct bigmac *bp, int from_irq) 213 { 214 struct bmac_init_block *bb = bp->bmac_block; 215 struct net_device *dev = bp->dev; 216 int i; 217 gfp_t gfp_flags = GFP_KERNEL; 218 219 if (from_irq || in_interrupt()) 220 gfp_flags = GFP_ATOMIC; 221 222 bp->rx_new = bp->rx_old = bp->tx_new = bp->tx_old = 0; 223 224 /* Free any skippy bufs left around in the rings. */ 225 bigmac_clean_rings(bp); 226 227 /* Now get new skbufs for the receive ring. */ 228 for (i = 0; i < RX_RING_SIZE; i++) { 229 struct sk_buff *skb; 230 231 skb = big_mac_alloc_skb(RX_BUF_ALLOC_SIZE, gfp_flags); 232 if (!skb) 233 continue; 234 235 bp->rx_skbs[i] = skb; 236 237 /* Because we reserve afterwards. */ 238 skb_put(skb, ETH_FRAME_LEN); 239 skb_reserve(skb, 34); 240 241 bb->be_rxd[i].rx_addr = 242 dma_map_single(&bp->bigmac_op->dev, 243 skb->data, 244 RX_BUF_ALLOC_SIZE - 34, 245 DMA_FROM_DEVICE); 246 bb->be_rxd[i].rx_flags = 247 (RXD_OWN | ((RX_BUF_ALLOC_SIZE - 34) & RXD_LENGTH)); 248 } 249 250 for (i = 0; i < TX_RING_SIZE; i++) 251 bb->be_txd[i].tx_flags = bb->be_txd[i].tx_addr = 0; 252 } 253 254 #define MGMT_CLKON (MGMT_PAL_INT_MDIO|MGMT_PAL_EXT_MDIO|MGMT_PAL_OENAB|MGMT_PAL_DCLOCK) 255 #define MGMT_CLKOFF (MGMT_PAL_INT_MDIO|MGMT_PAL_EXT_MDIO|MGMT_PAL_OENAB) 256 257 static void idle_transceiver(void __iomem *tregs) 258 { 259 int i = 20; 260 261 while (i--) { 262 sbus_writel(MGMT_CLKOFF, tregs + TCVR_MPAL); 263 sbus_readl(tregs + TCVR_MPAL); 264 sbus_writel(MGMT_CLKON, tregs + TCVR_MPAL); 265 sbus_readl(tregs + TCVR_MPAL); 266 } 267 } 268 269 static void write_tcvr_bit(struct bigmac *bp, void __iomem *tregs, int bit) 270 { 271 if (bp->tcvr_type == internal) { 272 bit = (bit & 1) << 3; 273 sbus_writel(bit | (MGMT_PAL_OENAB | MGMT_PAL_EXT_MDIO), 274 tregs + TCVR_MPAL); 275 sbus_readl(tregs + TCVR_MPAL); 276 sbus_writel(bit | MGMT_PAL_OENAB | MGMT_PAL_EXT_MDIO | MGMT_PAL_DCLOCK, 277 tregs + TCVR_MPAL); 278 sbus_readl(tregs + TCVR_MPAL); 279 } else if (bp->tcvr_type == external) { 280 bit = (bit & 1) << 2; 281 sbus_writel(bit | MGMT_PAL_INT_MDIO | MGMT_PAL_OENAB, 282 tregs + TCVR_MPAL); 283 sbus_readl(tregs + TCVR_MPAL); 284 sbus_writel(bit | MGMT_PAL_INT_MDIO | MGMT_PAL_OENAB | MGMT_PAL_DCLOCK, 285 tregs + TCVR_MPAL); 286 sbus_readl(tregs + TCVR_MPAL); 287 } else { 288 printk(KERN_ERR "write_tcvr_bit: No transceiver type known!\n"); 289 } 290 } 291 292 static int read_tcvr_bit(struct bigmac *bp, void __iomem *tregs) 293 { 294 int retval = 0; 295 296 if (bp->tcvr_type == internal) { 297 sbus_writel(MGMT_PAL_EXT_MDIO, tregs + TCVR_MPAL); 298 sbus_readl(tregs + TCVR_MPAL); 299 sbus_writel(MGMT_PAL_EXT_MDIO | MGMT_PAL_DCLOCK, 300 tregs + TCVR_MPAL); 301 sbus_readl(tregs + TCVR_MPAL); 302 retval = (sbus_readl(tregs + TCVR_MPAL) & MGMT_PAL_INT_MDIO) >> 3; 303 } else if (bp->tcvr_type == external) { 304 sbus_writel(MGMT_PAL_INT_MDIO, tregs + TCVR_MPAL); 305 sbus_readl(tregs + TCVR_MPAL); 306 sbus_writel(MGMT_PAL_INT_MDIO | MGMT_PAL_DCLOCK, tregs + TCVR_MPAL); 307 sbus_readl(tregs + TCVR_MPAL); 308 retval = (sbus_readl(tregs + TCVR_MPAL) & MGMT_PAL_EXT_MDIO) >> 2; 309 } else { 310 printk(KERN_ERR "read_tcvr_bit: No transceiver type known!\n"); 311 } 312 return retval; 313 } 314 315 static int read_tcvr_bit2(struct bigmac *bp, void __iomem *tregs) 316 { 317 int retval = 0; 318 319 if (bp->tcvr_type == internal) { 320 sbus_writel(MGMT_PAL_EXT_MDIO, tregs + TCVR_MPAL); 321 sbus_readl(tregs + TCVR_MPAL); 322 retval = (sbus_readl(tregs + TCVR_MPAL) & MGMT_PAL_INT_MDIO) >> 3; 323 sbus_writel(MGMT_PAL_EXT_MDIO | MGMT_PAL_DCLOCK, tregs + TCVR_MPAL); 324 sbus_readl(tregs + TCVR_MPAL); 325 } else if (bp->tcvr_type == external) { 326 sbus_writel(MGMT_PAL_INT_MDIO, tregs + TCVR_MPAL); 327 sbus_readl(tregs + TCVR_MPAL); 328 retval = (sbus_readl(tregs + TCVR_MPAL) & MGMT_PAL_EXT_MDIO) >> 2; 329 sbus_writel(MGMT_PAL_INT_MDIO | MGMT_PAL_DCLOCK, tregs + TCVR_MPAL); 330 sbus_readl(tregs + TCVR_MPAL); 331 } else { 332 printk(KERN_ERR "read_tcvr_bit2: No transceiver type known!\n"); 333 } 334 return retval; 335 } 336 337 static void put_tcvr_byte(struct bigmac *bp, 338 void __iomem *tregs, 339 unsigned int byte) 340 { 341 int shift = 4; 342 343 do { 344 write_tcvr_bit(bp, tregs, ((byte >> shift) & 1)); 345 shift -= 1; 346 } while (shift >= 0); 347 } 348 349 static void bigmac_tcvr_write(struct bigmac *bp, void __iomem *tregs, 350 int reg, unsigned short val) 351 { 352 int shift; 353 354 reg &= 0xff; 355 val &= 0xffff; 356 switch(bp->tcvr_type) { 357 case internal: 358 case external: 359 break; 360 361 default: 362 printk(KERN_ERR "bigmac_tcvr_read: Whoops, no known transceiver type.\n"); 363 return; 364 } 365 366 idle_transceiver(tregs); 367 write_tcvr_bit(bp, tregs, 0); 368 write_tcvr_bit(bp, tregs, 1); 369 write_tcvr_bit(bp, tregs, 0); 370 write_tcvr_bit(bp, tregs, 1); 371 372 put_tcvr_byte(bp, tregs, 373 ((bp->tcvr_type == internal) ? 374 BIGMAC_PHY_INTERNAL : BIGMAC_PHY_EXTERNAL)); 375 376 put_tcvr_byte(bp, tregs, reg); 377 378 write_tcvr_bit(bp, tregs, 1); 379 write_tcvr_bit(bp, tregs, 0); 380 381 shift = 15; 382 do { 383 write_tcvr_bit(bp, tregs, (val >> shift) & 1); 384 shift -= 1; 385 } while (shift >= 0); 386 } 387 388 static unsigned short bigmac_tcvr_read(struct bigmac *bp, 389 void __iomem *tregs, 390 int reg) 391 { 392 unsigned short retval = 0; 393 394 reg &= 0xff; 395 switch(bp->tcvr_type) { 396 case internal: 397 case external: 398 break; 399 400 default: 401 printk(KERN_ERR "bigmac_tcvr_read: Whoops, no known transceiver type.\n"); 402 return 0xffff; 403 } 404 405 idle_transceiver(tregs); 406 write_tcvr_bit(bp, tregs, 0); 407 write_tcvr_bit(bp, tregs, 1); 408 write_tcvr_bit(bp, tregs, 1); 409 write_tcvr_bit(bp, tregs, 0); 410 411 put_tcvr_byte(bp, tregs, 412 ((bp->tcvr_type == internal) ? 413 BIGMAC_PHY_INTERNAL : BIGMAC_PHY_EXTERNAL)); 414 415 put_tcvr_byte(bp, tregs, reg); 416 417 if (bp->tcvr_type == external) { 418 int shift = 15; 419 420 (void) read_tcvr_bit2(bp, tregs); 421 (void) read_tcvr_bit2(bp, tregs); 422 423 do { 424 int tmp; 425 426 tmp = read_tcvr_bit2(bp, tregs); 427 retval |= ((tmp & 1) << shift); 428 shift -= 1; 429 } while (shift >= 0); 430 431 (void) read_tcvr_bit2(bp, tregs); 432 (void) read_tcvr_bit2(bp, tregs); 433 (void) read_tcvr_bit2(bp, tregs); 434 } else { 435 int shift = 15; 436 437 (void) read_tcvr_bit(bp, tregs); 438 (void) read_tcvr_bit(bp, tregs); 439 440 do { 441 int tmp; 442 443 tmp = read_tcvr_bit(bp, tregs); 444 retval |= ((tmp & 1) << shift); 445 shift -= 1; 446 } while (shift >= 0); 447 448 (void) read_tcvr_bit(bp, tregs); 449 (void) read_tcvr_bit(bp, tregs); 450 (void) read_tcvr_bit(bp, tregs); 451 } 452 return retval; 453 } 454 455 static void bigmac_tcvr_init(struct bigmac *bp) 456 { 457 void __iomem *tregs = bp->tregs; 458 u32 mpal; 459 460 idle_transceiver(tregs); 461 sbus_writel(MGMT_PAL_INT_MDIO | MGMT_PAL_EXT_MDIO | MGMT_PAL_DCLOCK, 462 tregs + TCVR_MPAL); 463 sbus_readl(tregs + TCVR_MPAL); 464 465 /* Only the bit for the present transceiver (internal or 466 * external) will stick, set them both and see what stays. 467 */ 468 sbus_writel(MGMT_PAL_INT_MDIO | MGMT_PAL_EXT_MDIO, tregs + TCVR_MPAL); 469 sbus_readl(tregs + TCVR_MPAL); 470 udelay(20); 471 472 mpal = sbus_readl(tregs + TCVR_MPAL); 473 if (mpal & MGMT_PAL_EXT_MDIO) { 474 bp->tcvr_type = external; 475 sbus_writel(~(TCVR_PAL_EXTLBACK | TCVR_PAL_MSENSE | TCVR_PAL_LTENABLE), 476 tregs + TCVR_TPAL); 477 sbus_readl(tregs + TCVR_TPAL); 478 } else if (mpal & MGMT_PAL_INT_MDIO) { 479 bp->tcvr_type = internal; 480 sbus_writel(~(TCVR_PAL_SERIAL | TCVR_PAL_EXTLBACK | 481 TCVR_PAL_MSENSE | TCVR_PAL_LTENABLE), 482 tregs + TCVR_TPAL); 483 sbus_readl(tregs + TCVR_TPAL); 484 } else { 485 printk(KERN_ERR "BIGMAC: AIEEE, neither internal nor " 486 "external MDIO available!\n"); 487 printk(KERN_ERR "BIGMAC: mgmt_pal[%08x] tcvr_pal[%08x]\n", 488 sbus_readl(tregs + TCVR_MPAL), 489 sbus_readl(tregs + TCVR_TPAL)); 490 } 491 } 492 493 static int bigmac_init_hw(struct bigmac *, int); 494 495 static int try_next_permutation(struct bigmac *bp, void __iomem *tregs) 496 { 497 if (bp->sw_bmcr & BMCR_SPEED100) { 498 int timeout; 499 500 /* Reset the PHY. */ 501 bp->sw_bmcr = (BMCR_ISOLATE | BMCR_PDOWN | BMCR_LOOPBACK); 502 bigmac_tcvr_write(bp, tregs, MII_BMCR, bp->sw_bmcr); 503 bp->sw_bmcr = (BMCR_RESET); 504 bigmac_tcvr_write(bp, tregs, MII_BMCR, bp->sw_bmcr); 505 506 timeout = 64; 507 while (--timeout) { 508 bp->sw_bmcr = bigmac_tcvr_read(bp, tregs, MII_BMCR); 509 if ((bp->sw_bmcr & BMCR_RESET) == 0) 510 break; 511 udelay(20); 512 } 513 if (timeout == 0) 514 printk(KERN_ERR "%s: PHY reset failed.\n", bp->dev->name); 515 516 bp->sw_bmcr = bigmac_tcvr_read(bp, tregs, MII_BMCR); 517 518 /* Now we try 10baseT. */ 519 bp->sw_bmcr &= ~(BMCR_SPEED100); 520 bigmac_tcvr_write(bp, tregs, MII_BMCR, bp->sw_bmcr); 521 return 0; 522 } 523 524 /* We've tried them all. */ 525 return -1; 526 } 527 528 static void bigmac_timer(unsigned long data) 529 { 530 struct bigmac *bp = (struct bigmac *) data; 531 void __iomem *tregs = bp->tregs; 532 int restart_timer = 0; 533 534 bp->timer_ticks++; 535 if (bp->timer_state == ltrywait) { 536 bp->sw_bmsr = bigmac_tcvr_read(bp, tregs, MII_BMSR); 537 bp->sw_bmcr = bigmac_tcvr_read(bp, tregs, MII_BMCR); 538 if (bp->sw_bmsr & BMSR_LSTATUS) { 539 printk(KERN_INFO "%s: Link is now up at %s.\n", 540 bp->dev->name, 541 (bp->sw_bmcr & BMCR_SPEED100) ? 542 "100baseT" : "10baseT"); 543 bp->timer_state = asleep; 544 restart_timer = 0; 545 } else { 546 if (bp->timer_ticks >= 4) { 547 int ret; 548 549 ret = try_next_permutation(bp, tregs); 550 if (ret == -1) { 551 printk(KERN_ERR "%s: Link down, cable problem?\n", 552 bp->dev->name); 553 ret = bigmac_init_hw(bp, 0); 554 if (ret) { 555 printk(KERN_ERR "%s: Error, cannot re-init the " 556 "BigMAC.\n", bp->dev->name); 557 } 558 return; 559 } 560 bp->timer_ticks = 0; 561 restart_timer = 1; 562 } else { 563 restart_timer = 1; 564 } 565 } 566 } else { 567 /* Can't happens.... */ 568 printk(KERN_ERR "%s: Aieee, link timer is asleep but we got one anyways!\n", 569 bp->dev->name); 570 restart_timer = 0; 571 bp->timer_ticks = 0; 572 bp->timer_state = asleep; /* foo on you */ 573 } 574 575 if (restart_timer != 0) { 576 bp->bigmac_timer.expires = jiffies + ((12 * HZ)/10); /* 1.2 sec. */ 577 add_timer(&bp->bigmac_timer); 578 } 579 } 580 581 /* Well, really we just force the chip into 100baseT then 582 * 10baseT, each time checking for a link status. 583 */ 584 static void bigmac_begin_auto_negotiation(struct bigmac *bp) 585 { 586 void __iomem *tregs = bp->tregs; 587 int timeout; 588 589 /* Grab new software copies of PHY registers. */ 590 bp->sw_bmsr = bigmac_tcvr_read(bp, tregs, MII_BMSR); 591 bp->sw_bmcr = bigmac_tcvr_read(bp, tregs, MII_BMCR); 592 593 /* Reset the PHY. */ 594 bp->sw_bmcr = (BMCR_ISOLATE | BMCR_PDOWN | BMCR_LOOPBACK); 595 bigmac_tcvr_write(bp, tregs, MII_BMCR, bp->sw_bmcr); 596 bp->sw_bmcr = (BMCR_RESET); 597 bigmac_tcvr_write(bp, tregs, MII_BMCR, bp->sw_bmcr); 598 599 timeout = 64; 600 while (--timeout) { 601 bp->sw_bmcr = bigmac_tcvr_read(bp, tregs, MII_BMCR); 602 if ((bp->sw_bmcr & BMCR_RESET) == 0) 603 break; 604 udelay(20); 605 } 606 if (timeout == 0) 607 printk(KERN_ERR "%s: PHY reset failed.\n", bp->dev->name); 608 609 bp->sw_bmcr = bigmac_tcvr_read(bp, tregs, MII_BMCR); 610 611 /* First we try 100baseT. */ 612 bp->sw_bmcr |= BMCR_SPEED100; 613 bigmac_tcvr_write(bp, tregs, MII_BMCR, bp->sw_bmcr); 614 615 bp->timer_state = ltrywait; 616 bp->timer_ticks = 0; 617 bp->bigmac_timer.expires = jiffies + (12 * HZ) / 10; 618 bp->bigmac_timer.data = (unsigned long) bp; 619 bp->bigmac_timer.function = bigmac_timer; 620 add_timer(&bp->bigmac_timer); 621 } 622 623 static int bigmac_init_hw(struct bigmac *bp, int from_irq) 624 { 625 void __iomem *gregs = bp->gregs; 626 void __iomem *cregs = bp->creg; 627 void __iomem *bregs = bp->bregs; 628 unsigned char *e = &bp->dev->dev_addr[0]; 629 630 /* Latch current counters into statistics. */ 631 bigmac_get_counters(bp, bregs); 632 633 /* Reset QEC. */ 634 qec_global_reset(gregs); 635 636 /* Init QEC. */ 637 qec_init(bp); 638 639 /* Alloc and reset the tx/rx descriptor chains. */ 640 bigmac_init_rings(bp, from_irq); 641 642 /* Initialize the PHY. */ 643 bigmac_tcvr_init(bp); 644 645 /* Stop transmitter and receiver. */ 646 bigmac_stop(bp); 647 648 /* Set hardware ethernet address. */ 649 sbus_writel(((e[4] << 8) | e[5]), bregs + BMAC_MACADDR2); 650 sbus_writel(((e[2] << 8) | e[3]), bregs + BMAC_MACADDR1); 651 sbus_writel(((e[0] << 8) | e[1]), bregs + BMAC_MACADDR0); 652 653 /* Clear the hash table until mc upload occurs. */ 654 sbus_writel(0, bregs + BMAC_HTABLE3); 655 sbus_writel(0, bregs + BMAC_HTABLE2); 656 sbus_writel(0, bregs + BMAC_HTABLE1); 657 sbus_writel(0, bregs + BMAC_HTABLE0); 658 659 /* Enable Big Mac hash table filter. */ 660 sbus_writel(BIGMAC_RXCFG_HENABLE | BIGMAC_RXCFG_FIFO, 661 bregs + BMAC_RXCFG); 662 udelay(20); 663 664 /* Ok, configure the Big Mac transmitter. */ 665 sbus_writel(BIGMAC_TXCFG_FIFO, bregs + BMAC_TXCFG); 666 667 /* The HME docs recommend to use the 10LSB of our MAC here. */ 668 sbus_writel(((e[5] | e[4] << 8) & 0x3ff), 669 bregs + BMAC_RSEED); 670 671 /* Enable the output drivers no matter what. */ 672 sbus_writel(BIGMAC_XCFG_ODENABLE | BIGMAC_XCFG_RESV, 673 bregs + BMAC_XIFCFG); 674 675 /* Tell the QEC where the ring descriptors are. */ 676 sbus_writel(bp->bblock_dvma + bib_offset(be_rxd, 0), 677 cregs + CREG_RXDS); 678 sbus_writel(bp->bblock_dvma + bib_offset(be_txd, 0), 679 cregs + CREG_TXDS); 680 681 /* Setup the FIFO pointers into QEC local memory. */ 682 sbus_writel(0, cregs + CREG_RXRBUFPTR); 683 sbus_writel(0, cregs + CREG_RXWBUFPTR); 684 sbus_writel(sbus_readl(gregs + GLOB_RSIZE), 685 cregs + CREG_TXRBUFPTR); 686 sbus_writel(sbus_readl(gregs + GLOB_RSIZE), 687 cregs + CREG_TXWBUFPTR); 688 689 /* Tell bigmac what interrupts we don't want to hear about. */ 690 sbus_writel(BIGMAC_IMASK_GOTFRAME | BIGMAC_IMASK_SENTFRAME, 691 bregs + BMAC_IMASK); 692 693 /* Enable the various other irq's. */ 694 sbus_writel(0, cregs + CREG_RIMASK); 695 sbus_writel(0, cregs + CREG_TIMASK); 696 sbus_writel(0, cregs + CREG_QMASK); 697 sbus_writel(0, cregs + CREG_BMASK); 698 699 /* Set jam size to a reasonable default. */ 700 sbus_writel(DEFAULT_JAMSIZE, bregs + BMAC_JSIZE); 701 702 /* Clear collision counter. */ 703 sbus_writel(0, cregs + CREG_CCNT); 704 705 /* Enable transmitter and receiver. */ 706 sbus_writel(sbus_readl(bregs + BMAC_TXCFG) | BIGMAC_TXCFG_ENABLE, 707 bregs + BMAC_TXCFG); 708 sbus_writel(sbus_readl(bregs + BMAC_RXCFG) | BIGMAC_RXCFG_ENABLE, 709 bregs + BMAC_RXCFG); 710 711 /* Ok, start detecting link speed/duplex. */ 712 bigmac_begin_auto_negotiation(bp); 713 714 /* Success. */ 715 return 0; 716 } 717 718 /* Error interrupts get sent here. */ 719 static void bigmac_is_medium_rare(struct bigmac *bp, u32 qec_status, u32 bmac_status) 720 { 721 printk(KERN_ERR "bigmac_is_medium_rare: "); 722 if (qec_status & (GLOB_STAT_ER | GLOB_STAT_BM)) { 723 if (qec_status & GLOB_STAT_ER) 724 printk("QEC_ERROR, "); 725 if (qec_status & GLOB_STAT_BM) 726 printk("QEC_BMAC_ERROR, "); 727 } 728 if (bmac_status & CREG_STAT_ERRORS) { 729 if (bmac_status & CREG_STAT_BERROR) 730 printk("BMAC_ERROR, "); 731 if (bmac_status & CREG_STAT_TXDERROR) 732 printk("TXD_ERROR, "); 733 if (bmac_status & CREG_STAT_TXLERR) 734 printk("TX_LATE_ERROR, "); 735 if (bmac_status & CREG_STAT_TXPERR) 736 printk("TX_PARITY_ERROR, "); 737 if (bmac_status & CREG_STAT_TXSERR) 738 printk("TX_SBUS_ERROR, "); 739 740 if (bmac_status & CREG_STAT_RXDROP) 741 printk("RX_DROP_ERROR, "); 742 743 if (bmac_status & CREG_STAT_RXSMALL) 744 printk("RX_SMALL_ERROR, "); 745 if (bmac_status & CREG_STAT_RXLERR) 746 printk("RX_LATE_ERROR, "); 747 if (bmac_status & CREG_STAT_RXPERR) 748 printk("RX_PARITY_ERROR, "); 749 if (bmac_status & CREG_STAT_RXSERR) 750 printk("RX_SBUS_ERROR, "); 751 } 752 753 printk(" RESET\n"); 754 bigmac_init_hw(bp, 1); 755 } 756 757 /* BigMAC transmit complete service routines. */ 758 static void bigmac_tx(struct bigmac *bp) 759 { 760 struct be_txd *txbase = &bp->bmac_block->be_txd[0]; 761 struct net_device *dev = bp->dev; 762 int elem; 763 764 spin_lock(&bp->lock); 765 766 elem = bp->tx_old; 767 DTX(("bigmac_tx: tx_old[%d] ", elem)); 768 while (elem != bp->tx_new) { 769 struct sk_buff *skb; 770 struct be_txd *this = &txbase[elem]; 771 772 DTX(("this(%p) [flags(%08x)addr(%08x)]", 773 this, this->tx_flags, this->tx_addr)); 774 775 if (this->tx_flags & TXD_OWN) 776 break; 777 skb = bp->tx_skbs[elem]; 778 bp->enet_stats.tx_packets++; 779 bp->enet_stats.tx_bytes += skb->len; 780 dma_unmap_single(&bp->bigmac_op->dev, 781 this->tx_addr, skb->len, 782 DMA_TO_DEVICE); 783 784 DTX(("skb(%p) ", skb)); 785 bp->tx_skbs[elem] = NULL; 786 dev_kfree_skb_irq(skb); 787 788 elem = NEXT_TX(elem); 789 } 790 DTX((" DONE, tx_old=%d\n", elem)); 791 bp->tx_old = elem; 792 793 if (netif_queue_stopped(dev) && 794 TX_BUFFS_AVAIL(bp) > 0) 795 netif_wake_queue(bp->dev); 796 797 spin_unlock(&bp->lock); 798 } 799 800 /* BigMAC receive complete service routines. */ 801 static void bigmac_rx(struct bigmac *bp) 802 { 803 struct be_rxd *rxbase = &bp->bmac_block->be_rxd[0]; 804 struct be_rxd *this; 805 int elem = bp->rx_new, drops = 0; 806 u32 flags; 807 808 this = &rxbase[elem]; 809 while (!((flags = this->rx_flags) & RXD_OWN)) { 810 struct sk_buff *skb; 811 int len = (flags & RXD_LENGTH); /* FCS not included */ 812 813 /* Check for errors. */ 814 if (len < ETH_ZLEN) { 815 bp->enet_stats.rx_errors++; 816 bp->enet_stats.rx_length_errors++; 817 818 drop_it: 819 /* Return it to the BigMAC. */ 820 bp->enet_stats.rx_dropped++; 821 this->rx_flags = 822 (RXD_OWN | ((RX_BUF_ALLOC_SIZE - 34) & RXD_LENGTH)); 823 goto next; 824 } 825 skb = bp->rx_skbs[elem]; 826 if (len > RX_COPY_THRESHOLD) { 827 struct sk_buff *new_skb; 828 829 /* Now refill the entry, if we can. */ 830 new_skb = big_mac_alloc_skb(RX_BUF_ALLOC_SIZE, GFP_ATOMIC); 831 if (new_skb == NULL) { 832 drops++; 833 goto drop_it; 834 } 835 dma_unmap_single(&bp->bigmac_op->dev, 836 this->rx_addr, 837 RX_BUF_ALLOC_SIZE - 34, 838 DMA_FROM_DEVICE); 839 bp->rx_skbs[elem] = new_skb; 840 skb_put(new_skb, ETH_FRAME_LEN); 841 skb_reserve(new_skb, 34); 842 this->rx_addr = 843 dma_map_single(&bp->bigmac_op->dev, 844 new_skb->data, 845 RX_BUF_ALLOC_SIZE - 34, 846 DMA_FROM_DEVICE); 847 this->rx_flags = 848 (RXD_OWN | ((RX_BUF_ALLOC_SIZE - 34) & RXD_LENGTH)); 849 850 /* Trim the original skb for the netif. */ 851 skb_trim(skb, len); 852 } else { 853 struct sk_buff *copy_skb = netdev_alloc_skb(bp->dev, len + 2); 854 855 if (copy_skb == NULL) { 856 drops++; 857 goto drop_it; 858 } 859 skb_reserve(copy_skb, 2); 860 skb_put(copy_skb, len); 861 dma_sync_single_for_cpu(&bp->bigmac_op->dev, 862 this->rx_addr, len, 863 DMA_FROM_DEVICE); 864 skb_copy_to_linear_data(copy_skb, (unsigned char *)skb->data, len); 865 dma_sync_single_for_device(&bp->bigmac_op->dev, 866 this->rx_addr, len, 867 DMA_FROM_DEVICE); 868 869 /* Reuse original ring buffer. */ 870 this->rx_flags = 871 (RXD_OWN | ((RX_BUF_ALLOC_SIZE - 34) & RXD_LENGTH)); 872 873 skb = copy_skb; 874 } 875 876 /* No checksums done by the BigMAC ;-( */ 877 skb->protocol = eth_type_trans(skb, bp->dev); 878 netif_rx(skb); 879 bp->enet_stats.rx_packets++; 880 bp->enet_stats.rx_bytes += len; 881 next: 882 elem = NEXT_RX(elem); 883 this = &rxbase[elem]; 884 } 885 bp->rx_new = elem; 886 if (drops) 887 printk(KERN_NOTICE "%s: Memory squeeze, deferring packet.\n", bp->dev->name); 888 } 889 890 static irqreturn_t bigmac_interrupt(int irq, void *dev_id) 891 { 892 struct bigmac *bp = (struct bigmac *) dev_id; 893 u32 qec_status, bmac_status; 894 895 DIRQ(("bigmac_interrupt: ")); 896 897 /* Latch status registers now. */ 898 bmac_status = sbus_readl(bp->creg + CREG_STAT); 899 qec_status = sbus_readl(bp->gregs + GLOB_STAT); 900 901 DIRQ(("qec_status=%08x bmac_status=%08x\n", qec_status, bmac_status)); 902 if ((qec_status & (GLOB_STAT_ER | GLOB_STAT_BM)) || 903 (bmac_status & CREG_STAT_ERRORS)) 904 bigmac_is_medium_rare(bp, qec_status, bmac_status); 905 906 if (bmac_status & CREG_STAT_TXIRQ) 907 bigmac_tx(bp); 908 909 if (bmac_status & CREG_STAT_RXIRQ) 910 bigmac_rx(bp); 911 912 return IRQ_HANDLED; 913 } 914 915 static int bigmac_open(struct net_device *dev) 916 { 917 struct bigmac *bp = netdev_priv(dev); 918 int ret; 919 920 ret = request_irq(dev->irq, bigmac_interrupt, IRQF_SHARED, dev->name, bp); 921 if (ret) { 922 printk(KERN_ERR "BIGMAC: Can't order irq %d to go.\n", dev->irq); 923 return ret; 924 } 925 init_timer(&bp->bigmac_timer); 926 ret = bigmac_init_hw(bp, 0); 927 if (ret) 928 free_irq(dev->irq, bp); 929 return ret; 930 } 931 932 static int bigmac_close(struct net_device *dev) 933 { 934 struct bigmac *bp = netdev_priv(dev); 935 936 del_timer(&bp->bigmac_timer); 937 bp->timer_state = asleep; 938 bp->timer_ticks = 0; 939 940 bigmac_stop(bp); 941 bigmac_clean_rings(bp); 942 free_irq(dev->irq, bp); 943 return 0; 944 } 945 946 static void bigmac_tx_timeout(struct net_device *dev) 947 { 948 struct bigmac *bp = netdev_priv(dev); 949 950 bigmac_init_hw(bp, 0); 951 netif_wake_queue(dev); 952 } 953 954 /* Put a packet on the wire. */ 955 static int bigmac_start_xmit(struct sk_buff *skb, struct net_device *dev) 956 { 957 struct bigmac *bp = netdev_priv(dev); 958 int len, entry; 959 u32 mapping; 960 961 len = skb->len; 962 mapping = dma_map_single(&bp->bigmac_op->dev, skb->data, 963 len, DMA_TO_DEVICE); 964 965 /* Avoid a race... */ 966 spin_lock_irq(&bp->lock); 967 entry = bp->tx_new; 968 DTX(("bigmac_start_xmit: len(%d) entry(%d)\n", len, entry)); 969 bp->bmac_block->be_txd[entry].tx_flags = TXD_UPDATE; 970 bp->tx_skbs[entry] = skb; 971 bp->bmac_block->be_txd[entry].tx_addr = mapping; 972 bp->bmac_block->be_txd[entry].tx_flags = 973 (TXD_OWN | TXD_SOP | TXD_EOP | (len & TXD_LENGTH)); 974 bp->tx_new = NEXT_TX(entry); 975 if (TX_BUFFS_AVAIL(bp) <= 0) 976 netif_stop_queue(dev); 977 spin_unlock_irq(&bp->lock); 978 979 /* Get it going. */ 980 sbus_writel(CREG_CTRL_TWAKEUP, bp->creg + CREG_CTRL); 981 982 983 return NETDEV_TX_OK; 984 } 985 986 static struct net_device_stats *bigmac_get_stats(struct net_device *dev) 987 { 988 struct bigmac *bp = netdev_priv(dev); 989 990 bigmac_get_counters(bp, bp->bregs); 991 return &bp->enet_stats; 992 } 993 994 static void bigmac_set_multicast(struct net_device *dev) 995 { 996 struct bigmac *bp = netdev_priv(dev); 997 void __iomem *bregs = bp->bregs; 998 struct netdev_hw_addr *ha; 999 int i; 1000 u32 tmp, crc; 1001 1002 /* Disable the receiver. The bit self-clears when 1003 * the operation is complete. 1004 */ 1005 tmp = sbus_readl(bregs + BMAC_RXCFG); 1006 tmp &= ~(BIGMAC_RXCFG_ENABLE); 1007 sbus_writel(tmp, bregs + BMAC_RXCFG); 1008 while ((sbus_readl(bregs + BMAC_RXCFG) & BIGMAC_RXCFG_ENABLE) != 0) 1009 udelay(20); 1010 1011 if ((dev->flags & IFF_ALLMULTI) || (netdev_mc_count(dev) > 64)) { 1012 sbus_writel(0xffff, bregs + BMAC_HTABLE0); 1013 sbus_writel(0xffff, bregs + BMAC_HTABLE1); 1014 sbus_writel(0xffff, bregs + BMAC_HTABLE2); 1015 sbus_writel(0xffff, bregs + BMAC_HTABLE3); 1016 } else if (dev->flags & IFF_PROMISC) { 1017 tmp = sbus_readl(bregs + BMAC_RXCFG); 1018 tmp |= BIGMAC_RXCFG_PMISC; 1019 sbus_writel(tmp, bregs + BMAC_RXCFG); 1020 } else { 1021 u16 hash_table[4]; 1022 1023 for (i = 0; i < 4; i++) 1024 hash_table[i] = 0; 1025 1026 netdev_for_each_mc_addr(ha, dev) { 1027 crc = ether_crc_le(6, ha->addr); 1028 crc >>= 26; 1029 hash_table[crc >> 4] |= 1 << (crc & 0xf); 1030 } 1031 sbus_writel(hash_table[0], bregs + BMAC_HTABLE0); 1032 sbus_writel(hash_table[1], bregs + BMAC_HTABLE1); 1033 sbus_writel(hash_table[2], bregs + BMAC_HTABLE2); 1034 sbus_writel(hash_table[3], bregs + BMAC_HTABLE3); 1035 } 1036 1037 /* Re-enable the receiver. */ 1038 tmp = sbus_readl(bregs + BMAC_RXCFG); 1039 tmp |= BIGMAC_RXCFG_ENABLE; 1040 sbus_writel(tmp, bregs + BMAC_RXCFG); 1041 } 1042 1043 /* Ethtool support... */ 1044 static void bigmac_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info) 1045 { 1046 strcpy(info->driver, "sunbmac"); 1047 strcpy(info->version, "2.0"); 1048 } 1049 1050 static u32 bigmac_get_link(struct net_device *dev) 1051 { 1052 struct bigmac *bp = netdev_priv(dev); 1053 1054 spin_lock_irq(&bp->lock); 1055 bp->sw_bmsr = bigmac_tcvr_read(bp, bp->tregs, MII_BMSR); 1056 spin_unlock_irq(&bp->lock); 1057 1058 return (bp->sw_bmsr & BMSR_LSTATUS); 1059 } 1060 1061 static const struct ethtool_ops bigmac_ethtool_ops = { 1062 .get_drvinfo = bigmac_get_drvinfo, 1063 .get_link = bigmac_get_link, 1064 }; 1065 1066 static const struct net_device_ops bigmac_ops = { 1067 .ndo_open = bigmac_open, 1068 .ndo_stop = bigmac_close, 1069 .ndo_start_xmit = bigmac_start_xmit, 1070 .ndo_get_stats = bigmac_get_stats, 1071 .ndo_set_rx_mode = bigmac_set_multicast, 1072 .ndo_tx_timeout = bigmac_tx_timeout, 1073 .ndo_change_mtu = eth_change_mtu, 1074 .ndo_set_mac_address = eth_mac_addr, 1075 .ndo_validate_addr = eth_validate_addr, 1076 }; 1077 1078 static int __devinit bigmac_ether_init(struct platform_device *op, 1079 struct platform_device *qec_op) 1080 { 1081 static int version_printed; 1082 struct net_device *dev; 1083 u8 bsizes, bsizes_more; 1084 struct bigmac *bp; 1085 int i; 1086 1087 /* Get a new device struct for this interface. */ 1088 dev = alloc_etherdev(sizeof(struct bigmac)); 1089 if (!dev) 1090 return -ENOMEM; 1091 1092 if (version_printed++ == 0) 1093 printk(KERN_INFO "%s", version); 1094 1095 for (i = 0; i < 6; i++) 1096 dev->dev_addr[i] = idprom->id_ethaddr[i]; 1097 1098 /* Setup softc, with backpointers to QEC and BigMAC SBUS device structs. */ 1099 bp = netdev_priv(dev); 1100 bp->qec_op = qec_op; 1101 bp->bigmac_op = op; 1102 1103 SET_NETDEV_DEV(dev, &op->dev); 1104 1105 spin_lock_init(&bp->lock); 1106 1107 /* Map in QEC global control registers. */ 1108 bp->gregs = of_ioremap(&qec_op->resource[0], 0, 1109 GLOB_REG_SIZE, "BigMAC QEC GLobal Regs"); 1110 if (!bp->gregs) { 1111 printk(KERN_ERR "BIGMAC: Cannot map QEC global registers.\n"); 1112 goto fail_and_cleanup; 1113 } 1114 1115 /* Make sure QEC is in BigMAC mode. */ 1116 if ((sbus_readl(bp->gregs + GLOB_CTRL) & 0xf0000000) != GLOB_CTRL_BMODE) { 1117 printk(KERN_ERR "BigMAC: AIEEE, QEC is not in BigMAC mode!\n"); 1118 goto fail_and_cleanup; 1119 } 1120 1121 /* Reset the QEC. */ 1122 if (qec_global_reset(bp->gregs)) 1123 goto fail_and_cleanup; 1124 1125 /* Get supported SBUS burst sizes. */ 1126 bsizes = of_getintprop_default(qec_op->dev.of_node, "burst-sizes", 0xff); 1127 bsizes_more = of_getintprop_default(qec_op->dev.of_node, "burst-sizes", 0xff); 1128 1129 bsizes &= 0xff; 1130 if (bsizes_more != 0xff) 1131 bsizes &= bsizes_more; 1132 if (bsizes == 0xff || (bsizes & DMA_BURST16) == 0 || 1133 (bsizes & DMA_BURST32) == 0) 1134 bsizes = (DMA_BURST32 - 1); 1135 bp->bigmac_bursts = bsizes; 1136 1137 /* Perform QEC initialization. */ 1138 qec_init(bp); 1139 1140 /* Map in the BigMAC channel registers. */ 1141 bp->creg = of_ioremap(&op->resource[0], 0, 1142 CREG_REG_SIZE, "BigMAC QEC Channel Regs"); 1143 if (!bp->creg) { 1144 printk(KERN_ERR "BIGMAC: Cannot map QEC channel registers.\n"); 1145 goto fail_and_cleanup; 1146 } 1147 1148 /* Map in the BigMAC control registers. */ 1149 bp->bregs = of_ioremap(&op->resource[1], 0, 1150 BMAC_REG_SIZE, "BigMAC Primary Regs"); 1151 if (!bp->bregs) { 1152 printk(KERN_ERR "BIGMAC: Cannot map BigMAC primary registers.\n"); 1153 goto fail_and_cleanup; 1154 } 1155 1156 /* Map in the BigMAC transceiver registers, this is how you poke at 1157 * the BigMAC's PHY. 1158 */ 1159 bp->tregs = of_ioremap(&op->resource[2], 0, 1160 TCVR_REG_SIZE, "BigMAC Transceiver Regs"); 1161 if (!bp->tregs) { 1162 printk(KERN_ERR "BIGMAC: Cannot map BigMAC transceiver registers.\n"); 1163 goto fail_and_cleanup; 1164 } 1165 1166 /* Stop the BigMAC. */ 1167 bigmac_stop(bp); 1168 1169 /* Allocate transmit/receive descriptor DVMA block. */ 1170 bp->bmac_block = dma_alloc_coherent(&bp->bigmac_op->dev, 1171 PAGE_SIZE, 1172 &bp->bblock_dvma, GFP_ATOMIC); 1173 if (bp->bmac_block == NULL || bp->bblock_dvma == 0) { 1174 printk(KERN_ERR "BIGMAC: Cannot allocate consistent DMA.\n"); 1175 goto fail_and_cleanup; 1176 } 1177 1178 /* Get the board revision of this BigMAC. */ 1179 bp->board_rev = of_getintprop_default(bp->bigmac_op->dev.of_node, 1180 "board-version", 1); 1181 1182 /* Init auto-negotiation timer state. */ 1183 init_timer(&bp->bigmac_timer); 1184 bp->timer_state = asleep; 1185 bp->timer_ticks = 0; 1186 1187 /* Backlink to generic net device struct. */ 1188 bp->dev = dev; 1189 1190 /* Set links to our BigMAC open and close routines. */ 1191 dev->ethtool_ops = &bigmac_ethtool_ops; 1192 dev->netdev_ops = &bigmac_ops; 1193 dev->watchdog_timeo = 5*HZ; 1194 1195 /* Finish net device registration. */ 1196 dev->irq = bp->bigmac_op->archdata.irqs[0]; 1197 dev->dma = 0; 1198 1199 if (register_netdev(dev)) { 1200 printk(KERN_ERR "BIGMAC: Cannot register device.\n"); 1201 goto fail_and_cleanup; 1202 } 1203 1204 dev_set_drvdata(&bp->bigmac_op->dev, bp); 1205 1206 printk(KERN_INFO "%s: BigMAC 100baseT Ethernet %pM\n", 1207 dev->name, dev->dev_addr); 1208 1209 return 0; 1210 1211 fail_and_cleanup: 1212 /* Something went wrong, undo whatever we did so far. */ 1213 /* Free register mappings if any. */ 1214 if (bp->gregs) 1215 of_iounmap(&qec_op->resource[0], bp->gregs, GLOB_REG_SIZE); 1216 if (bp->creg) 1217 of_iounmap(&op->resource[0], bp->creg, CREG_REG_SIZE); 1218 if (bp->bregs) 1219 of_iounmap(&op->resource[1], bp->bregs, BMAC_REG_SIZE); 1220 if (bp->tregs) 1221 of_iounmap(&op->resource[2], bp->tregs, TCVR_REG_SIZE); 1222 1223 if (bp->bmac_block) 1224 dma_free_coherent(&bp->bigmac_op->dev, 1225 PAGE_SIZE, 1226 bp->bmac_block, 1227 bp->bblock_dvma); 1228 1229 /* This also frees the co-located private data */ 1230 free_netdev(dev); 1231 return -ENODEV; 1232 } 1233 1234 /* QEC can be the parent of either QuadEthernet or a BigMAC. We want 1235 * the latter. 1236 */ 1237 static int __devinit bigmac_sbus_probe(struct platform_device *op) 1238 { 1239 struct device *parent = op->dev.parent; 1240 struct platform_device *qec_op; 1241 1242 qec_op = to_platform_device(parent); 1243 1244 return bigmac_ether_init(op, qec_op); 1245 } 1246 1247 static int __devexit bigmac_sbus_remove(struct platform_device *op) 1248 { 1249 struct bigmac *bp = dev_get_drvdata(&op->dev); 1250 struct device *parent = op->dev.parent; 1251 struct net_device *net_dev = bp->dev; 1252 struct platform_device *qec_op; 1253 1254 qec_op = to_platform_device(parent); 1255 1256 unregister_netdev(net_dev); 1257 1258 of_iounmap(&qec_op->resource[0], bp->gregs, GLOB_REG_SIZE); 1259 of_iounmap(&op->resource[0], bp->creg, CREG_REG_SIZE); 1260 of_iounmap(&op->resource[1], bp->bregs, BMAC_REG_SIZE); 1261 of_iounmap(&op->resource[2], bp->tregs, TCVR_REG_SIZE); 1262 dma_free_coherent(&op->dev, 1263 PAGE_SIZE, 1264 bp->bmac_block, 1265 bp->bblock_dvma); 1266 1267 free_netdev(net_dev); 1268 1269 dev_set_drvdata(&op->dev, NULL); 1270 1271 return 0; 1272 } 1273 1274 static const struct of_device_id bigmac_sbus_match[] = { 1275 { 1276 .name = "be", 1277 }, 1278 {}, 1279 }; 1280 1281 MODULE_DEVICE_TABLE(of, bigmac_sbus_match); 1282 1283 static struct platform_driver bigmac_sbus_driver = { 1284 .driver = { 1285 .name = "sunbmac", 1286 .owner = THIS_MODULE, 1287 .of_match_table = bigmac_sbus_match, 1288 }, 1289 .probe = bigmac_sbus_probe, 1290 .remove = __devexit_p(bigmac_sbus_remove), 1291 }; 1292 1293 module_platform_driver(bigmac_sbus_driver); 1294