1 /* niu.c: Neptune ethernet driver. 2 * 3 * Copyright (C) 2007, 2008 David S. Miller (davem@davemloft.net) 4 */ 5 6 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 7 8 #include <linux/module.h> 9 #include <linux/init.h> 10 #include <linux/interrupt.h> 11 #include <linux/pci.h> 12 #include <linux/dma-mapping.h> 13 #include <linux/netdevice.h> 14 #include <linux/ethtool.h> 15 #include <linux/etherdevice.h> 16 #include <linux/platform_device.h> 17 #include <linux/delay.h> 18 #include <linux/bitops.h> 19 #include <linux/mii.h> 20 #include <linux/if.h> 21 #include <linux/if_ether.h> 22 #include <linux/if_vlan.h> 23 #include <linux/ip.h> 24 #include <linux/in.h> 25 #include <linux/ipv6.h> 26 #include <linux/log2.h> 27 #include <linux/jiffies.h> 28 #include <linux/crc32.h> 29 #include <linux/list.h> 30 #include <linux/slab.h> 31 32 #include <linux/io.h> 33 #include <linux/of_device.h> 34 35 #include "niu.h" 36 37 #define DRV_MODULE_NAME "niu" 38 #define DRV_MODULE_VERSION "1.1" 39 #define DRV_MODULE_RELDATE "Apr 22, 2010" 40 41 static char version[] = 42 DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n"; 43 44 MODULE_AUTHOR("David S. Miller (davem@davemloft.net)"); 45 MODULE_DESCRIPTION("NIU ethernet driver"); 46 MODULE_LICENSE("GPL"); 47 MODULE_VERSION(DRV_MODULE_VERSION); 48 49 #ifndef readq 50 static u64 readq(void __iomem *reg) 51 { 52 return ((u64) readl(reg)) | (((u64) readl(reg + 4UL)) << 32); 53 } 54 55 static void writeq(u64 val, void __iomem *reg) 56 { 57 writel(val & 0xffffffff, reg); 58 writel(val >> 32, reg + 0x4UL); 59 } 60 #endif 61 62 static const struct pci_device_id niu_pci_tbl[] = { 63 {PCI_DEVICE(PCI_VENDOR_ID_SUN, 0xabcd)}, 64 {} 65 }; 66 67 MODULE_DEVICE_TABLE(pci, niu_pci_tbl); 68 69 #define NIU_TX_TIMEOUT (5 * HZ) 70 71 #define nr64(reg) readq(np->regs + (reg)) 72 #define nw64(reg, val) writeq((val), np->regs + (reg)) 73 74 #define nr64_mac(reg) readq(np->mac_regs + (reg)) 75 #define nw64_mac(reg, val) writeq((val), np->mac_regs + (reg)) 76 77 #define nr64_ipp(reg) readq(np->regs + np->ipp_off + (reg)) 78 #define nw64_ipp(reg, val) writeq((val), np->regs + np->ipp_off + (reg)) 79 80 #define nr64_pcs(reg) readq(np->regs + np->pcs_off + (reg)) 81 #define nw64_pcs(reg, val) writeq((val), np->regs + np->pcs_off + (reg)) 82 83 #define nr64_xpcs(reg) readq(np->regs + np->xpcs_off + (reg)) 84 #define nw64_xpcs(reg, val) writeq((val), np->regs + np->xpcs_off + (reg)) 85 86 #define NIU_MSG_DEFAULT (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK) 87 88 static int niu_debug; 89 static int debug = -1; 90 module_param(debug, int, 0); 91 MODULE_PARM_DESC(debug, "NIU debug level"); 92 93 #define niu_lock_parent(np, flags) \ 94 spin_lock_irqsave(&np->parent->lock, flags) 95 #define niu_unlock_parent(np, flags) \ 96 spin_unlock_irqrestore(&np->parent->lock, flags) 97 98 static int serdes_init_10g_serdes(struct niu *np); 99 100 static int __niu_wait_bits_clear_mac(struct niu *np, unsigned long reg, 101 u64 bits, int limit, int delay) 102 { 103 while (--limit >= 0) { 104 u64 val = nr64_mac(reg); 105 106 if (!(val & bits)) 107 break; 108 udelay(delay); 109 } 110 if (limit < 0) 111 return -ENODEV; 112 return 0; 113 } 114 115 static int __niu_set_and_wait_clear_mac(struct niu *np, unsigned long reg, 116 u64 bits, int limit, int delay, 117 const char *reg_name) 118 { 119 int err; 120 121 nw64_mac(reg, bits); 122 err = __niu_wait_bits_clear_mac(np, reg, bits, limit, delay); 123 if (err) 124 netdev_err(np->dev, "bits (%llx) of register %s would not clear, val[%llx]\n", 125 (unsigned long long)bits, reg_name, 126 (unsigned long long)nr64_mac(reg)); 127 return err; 128 } 129 130 #define niu_set_and_wait_clear_mac(NP, REG, BITS, LIMIT, DELAY, REG_NAME) \ 131 ({ BUILD_BUG_ON(LIMIT <= 0 || DELAY < 0); \ 132 __niu_set_and_wait_clear_mac(NP, REG, BITS, LIMIT, DELAY, REG_NAME); \ 133 }) 134 135 static int __niu_wait_bits_clear_ipp(struct niu *np, unsigned long reg, 136 u64 bits, int limit, int delay) 137 { 138 while (--limit >= 0) { 139 u64 val = nr64_ipp(reg); 140 141 if (!(val & bits)) 142 break; 143 udelay(delay); 144 } 145 if (limit < 0) 146 return -ENODEV; 147 return 0; 148 } 149 150 static int __niu_set_and_wait_clear_ipp(struct niu *np, unsigned long reg, 151 u64 bits, int limit, int delay, 152 const char *reg_name) 153 { 154 int err; 155 u64 val; 156 157 val = nr64_ipp(reg); 158 val |= bits; 159 nw64_ipp(reg, val); 160 161 err = __niu_wait_bits_clear_ipp(np, reg, bits, limit, delay); 162 if (err) 163 netdev_err(np->dev, "bits (%llx) of register %s would not clear, val[%llx]\n", 164 (unsigned long long)bits, reg_name, 165 (unsigned long long)nr64_ipp(reg)); 166 return err; 167 } 168 169 #define niu_set_and_wait_clear_ipp(NP, REG, BITS, LIMIT, DELAY, REG_NAME) \ 170 ({ BUILD_BUG_ON(LIMIT <= 0 || DELAY < 0); \ 171 __niu_set_and_wait_clear_ipp(NP, REG, BITS, LIMIT, DELAY, REG_NAME); \ 172 }) 173 174 static int __niu_wait_bits_clear(struct niu *np, unsigned long reg, 175 u64 bits, int limit, int delay) 176 { 177 while (--limit >= 0) { 178 u64 val = nr64(reg); 179 180 if (!(val & bits)) 181 break; 182 udelay(delay); 183 } 184 if (limit < 0) 185 return -ENODEV; 186 return 0; 187 } 188 189 #define niu_wait_bits_clear(NP, REG, BITS, LIMIT, DELAY) \ 190 ({ BUILD_BUG_ON(LIMIT <= 0 || DELAY < 0); \ 191 __niu_wait_bits_clear(NP, REG, BITS, LIMIT, DELAY); \ 192 }) 193 194 static int __niu_set_and_wait_clear(struct niu *np, unsigned long reg, 195 u64 bits, int limit, int delay, 196 const char *reg_name) 197 { 198 int err; 199 200 nw64(reg, bits); 201 err = __niu_wait_bits_clear(np, reg, bits, limit, delay); 202 if (err) 203 netdev_err(np->dev, "bits (%llx) of register %s would not clear, val[%llx]\n", 204 (unsigned long long)bits, reg_name, 205 (unsigned long long)nr64(reg)); 206 return err; 207 } 208 209 #define niu_set_and_wait_clear(NP, REG, BITS, LIMIT, DELAY, REG_NAME) \ 210 ({ BUILD_BUG_ON(LIMIT <= 0 || DELAY < 0); \ 211 __niu_set_and_wait_clear(NP, REG, BITS, LIMIT, DELAY, REG_NAME); \ 212 }) 213 214 static void niu_ldg_rearm(struct niu *np, struct niu_ldg *lp, int on) 215 { 216 u64 val = (u64) lp->timer; 217 218 if (on) 219 val |= LDG_IMGMT_ARM; 220 221 nw64(LDG_IMGMT(lp->ldg_num), val); 222 } 223 224 static int niu_ldn_irq_enable(struct niu *np, int ldn, int on) 225 { 226 unsigned long mask_reg, bits; 227 u64 val; 228 229 if (ldn < 0 || ldn > LDN_MAX) 230 return -EINVAL; 231 232 if (ldn < 64) { 233 mask_reg = LD_IM0(ldn); 234 bits = LD_IM0_MASK; 235 } else { 236 mask_reg = LD_IM1(ldn - 64); 237 bits = LD_IM1_MASK; 238 } 239 240 val = nr64(mask_reg); 241 if (on) 242 val &= ~bits; 243 else 244 val |= bits; 245 nw64(mask_reg, val); 246 247 return 0; 248 } 249 250 static int niu_enable_ldn_in_ldg(struct niu *np, struct niu_ldg *lp, int on) 251 { 252 struct niu_parent *parent = np->parent; 253 int i; 254 255 for (i = 0; i <= LDN_MAX; i++) { 256 int err; 257 258 if (parent->ldg_map[i] != lp->ldg_num) 259 continue; 260 261 err = niu_ldn_irq_enable(np, i, on); 262 if (err) 263 return err; 264 } 265 return 0; 266 } 267 268 static int niu_enable_interrupts(struct niu *np, int on) 269 { 270 int i; 271 272 for (i = 0; i < np->num_ldg; i++) { 273 struct niu_ldg *lp = &np->ldg[i]; 274 int err; 275 276 err = niu_enable_ldn_in_ldg(np, lp, on); 277 if (err) 278 return err; 279 } 280 for (i = 0; i < np->num_ldg; i++) 281 niu_ldg_rearm(np, &np->ldg[i], on); 282 283 return 0; 284 } 285 286 static u32 phy_encode(u32 type, int port) 287 { 288 return type << (port * 2); 289 } 290 291 static u32 phy_decode(u32 val, int port) 292 { 293 return (val >> (port * 2)) & PORT_TYPE_MASK; 294 } 295 296 static int mdio_wait(struct niu *np) 297 { 298 int limit = 1000; 299 u64 val; 300 301 while (--limit > 0) { 302 val = nr64(MIF_FRAME_OUTPUT); 303 if ((val >> MIF_FRAME_OUTPUT_TA_SHIFT) & 0x1) 304 return val & MIF_FRAME_OUTPUT_DATA; 305 306 udelay(10); 307 } 308 309 return -ENODEV; 310 } 311 312 static int mdio_read(struct niu *np, int port, int dev, int reg) 313 { 314 int err; 315 316 nw64(MIF_FRAME_OUTPUT, MDIO_ADDR_OP(port, dev, reg)); 317 err = mdio_wait(np); 318 if (err < 0) 319 return err; 320 321 nw64(MIF_FRAME_OUTPUT, MDIO_READ_OP(port, dev)); 322 return mdio_wait(np); 323 } 324 325 static int mdio_write(struct niu *np, int port, int dev, int reg, int data) 326 { 327 int err; 328 329 nw64(MIF_FRAME_OUTPUT, MDIO_ADDR_OP(port, dev, reg)); 330 err = mdio_wait(np); 331 if (err < 0) 332 return err; 333 334 nw64(MIF_FRAME_OUTPUT, MDIO_WRITE_OP(port, dev, data)); 335 err = mdio_wait(np); 336 if (err < 0) 337 return err; 338 339 return 0; 340 } 341 342 static int mii_read(struct niu *np, int port, int reg) 343 { 344 nw64(MIF_FRAME_OUTPUT, MII_READ_OP(port, reg)); 345 return mdio_wait(np); 346 } 347 348 static int mii_write(struct niu *np, int port, int reg, int data) 349 { 350 int err; 351 352 nw64(MIF_FRAME_OUTPUT, MII_WRITE_OP(port, reg, data)); 353 err = mdio_wait(np); 354 if (err < 0) 355 return err; 356 357 return 0; 358 } 359 360 static int esr2_set_tx_cfg(struct niu *np, unsigned long channel, u32 val) 361 { 362 int err; 363 364 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR, 365 ESR2_TI_PLL_TX_CFG_L(channel), 366 val & 0xffff); 367 if (!err) 368 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR, 369 ESR2_TI_PLL_TX_CFG_H(channel), 370 val >> 16); 371 return err; 372 } 373 374 static int esr2_set_rx_cfg(struct niu *np, unsigned long channel, u32 val) 375 { 376 int err; 377 378 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR, 379 ESR2_TI_PLL_RX_CFG_L(channel), 380 val & 0xffff); 381 if (!err) 382 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR, 383 ESR2_TI_PLL_RX_CFG_H(channel), 384 val >> 16); 385 return err; 386 } 387 388 /* Mode is always 10G fiber. */ 389 static int serdes_init_niu_10g_fiber(struct niu *np) 390 { 391 struct niu_link_config *lp = &np->link_config; 392 u32 tx_cfg, rx_cfg; 393 unsigned long i; 394 395 tx_cfg = (PLL_TX_CFG_ENTX | PLL_TX_CFG_SWING_1375MV); 396 rx_cfg = (PLL_RX_CFG_ENRX | PLL_RX_CFG_TERM_0P8VDDT | 397 PLL_RX_CFG_ALIGN_ENA | PLL_RX_CFG_LOS_LTHRESH | 398 PLL_RX_CFG_EQ_LP_ADAPTIVE); 399 400 if (lp->loopback_mode == LOOPBACK_PHY) { 401 u16 test_cfg = PLL_TEST_CFG_LOOPBACK_CML_DIS; 402 403 mdio_write(np, np->port, NIU_ESR2_DEV_ADDR, 404 ESR2_TI_PLL_TEST_CFG_L, test_cfg); 405 406 tx_cfg |= PLL_TX_CFG_ENTEST; 407 rx_cfg |= PLL_RX_CFG_ENTEST; 408 } 409 410 /* Initialize all 4 lanes of the SERDES. */ 411 for (i = 0; i < 4; i++) { 412 int err = esr2_set_tx_cfg(np, i, tx_cfg); 413 if (err) 414 return err; 415 } 416 417 for (i = 0; i < 4; i++) { 418 int err = esr2_set_rx_cfg(np, i, rx_cfg); 419 if (err) 420 return err; 421 } 422 423 return 0; 424 } 425 426 static int serdes_init_niu_1g_serdes(struct niu *np) 427 { 428 struct niu_link_config *lp = &np->link_config; 429 u16 pll_cfg, pll_sts; 430 int max_retry = 100; 431 u64 uninitialized_var(sig), mask, val; 432 u32 tx_cfg, rx_cfg; 433 unsigned long i; 434 int err; 435 436 tx_cfg = (PLL_TX_CFG_ENTX | PLL_TX_CFG_SWING_1375MV | 437 PLL_TX_CFG_RATE_HALF); 438 rx_cfg = (PLL_RX_CFG_ENRX | PLL_RX_CFG_TERM_0P8VDDT | 439 PLL_RX_CFG_ALIGN_ENA | PLL_RX_CFG_LOS_LTHRESH | 440 PLL_RX_CFG_RATE_HALF); 441 442 if (np->port == 0) 443 rx_cfg |= PLL_RX_CFG_EQ_LP_ADAPTIVE; 444 445 if (lp->loopback_mode == LOOPBACK_PHY) { 446 u16 test_cfg = PLL_TEST_CFG_LOOPBACK_CML_DIS; 447 448 mdio_write(np, np->port, NIU_ESR2_DEV_ADDR, 449 ESR2_TI_PLL_TEST_CFG_L, test_cfg); 450 451 tx_cfg |= PLL_TX_CFG_ENTEST; 452 rx_cfg |= PLL_RX_CFG_ENTEST; 453 } 454 455 /* Initialize PLL for 1G */ 456 pll_cfg = (PLL_CFG_ENPLL | PLL_CFG_MPY_8X); 457 458 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR, 459 ESR2_TI_PLL_CFG_L, pll_cfg); 460 if (err) { 461 netdev_err(np->dev, "NIU Port %d %s() mdio write to ESR2_TI_PLL_CFG_L failed\n", 462 np->port, __func__); 463 return err; 464 } 465 466 pll_sts = PLL_CFG_ENPLL; 467 468 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR, 469 ESR2_TI_PLL_STS_L, pll_sts); 470 if (err) { 471 netdev_err(np->dev, "NIU Port %d %s() mdio write to ESR2_TI_PLL_STS_L failed\n", 472 np->port, __func__); 473 return err; 474 } 475 476 udelay(200); 477 478 /* Initialize all 4 lanes of the SERDES. */ 479 for (i = 0; i < 4; i++) { 480 err = esr2_set_tx_cfg(np, i, tx_cfg); 481 if (err) 482 return err; 483 } 484 485 for (i = 0; i < 4; i++) { 486 err = esr2_set_rx_cfg(np, i, rx_cfg); 487 if (err) 488 return err; 489 } 490 491 switch (np->port) { 492 case 0: 493 val = (ESR_INT_SRDY0_P0 | ESR_INT_DET0_P0); 494 mask = val; 495 break; 496 497 case 1: 498 val = (ESR_INT_SRDY0_P1 | ESR_INT_DET0_P1); 499 mask = val; 500 break; 501 502 default: 503 return -EINVAL; 504 } 505 506 while (max_retry--) { 507 sig = nr64(ESR_INT_SIGNALS); 508 if ((sig & mask) == val) 509 break; 510 511 mdelay(500); 512 } 513 514 if ((sig & mask) != val) { 515 netdev_err(np->dev, "Port %u signal bits [%08x] are not [%08x]\n", 516 np->port, (int)(sig & mask), (int)val); 517 return -ENODEV; 518 } 519 520 return 0; 521 } 522 523 static int serdes_init_niu_10g_serdes(struct niu *np) 524 { 525 struct niu_link_config *lp = &np->link_config; 526 u32 tx_cfg, rx_cfg, pll_cfg, pll_sts; 527 int max_retry = 100; 528 u64 uninitialized_var(sig), mask, val; 529 unsigned long i; 530 int err; 531 532 tx_cfg = (PLL_TX_CFG_ENTX | PLL_TX_CFG_SWING_1375MV); 533 rx_cfg = (PLL_RX_CFG_ENRX | PLL_RX_CFG_TERM_0P8VDDT | 534 PLL_RX_CFG_ALIGN_ENA | PLL_RX_CFG_LOS_LTHRESH | 535 PLL_RX_CFG_EQ_LP_ADAPTIVE); 536 537 if (lp->loopback_mode == LOOPBACK_PHY) { 538 u16 test_cfg = PLL_TEST_CFG_LOOPBACK_CML_DIS; 539 540 mdio_write(np, np->port, NIU_ESR2_DEV_ADDR, 541 ESR2_TI_PLL_TEST_CFG_L, test_cfg); 542 543 tx_cfg |= PLL_TX_CFG_ENTEST; 544 rx_cfg |= PLL_RX_CFG_ENTEST; 545 } 546 547 /* Initialize PLL for 10G */ 548 pll_cfg = (PLL_CFG_ENPLL | PLL_CFG_MPY_10X); 549 550 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR, 551 ESR2_TI_PLL_CFG_L, pll_cfg & 0xffff); 552 if (err) { 553 netdev_err(np->dev, "NIU Port %d %s() mdio write to ESR2_TI_PLL_CFG_L failed\n", 554 np->port, __func__); 555 return err; 556 } 557 558 pll_sts = PLL_CFG_ENPLL; 559 560 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR, 561 ESR2_TI_PLL_STS_L, pll_sts & 0xffff); 562 if (err) { 563 netdev_err(np->dev, "NIU Port %d %s() mdio write to ESR2_TI_PLL_STS_L failed\n", 564 np->port, __func__); 565 return err; 566 } 567 568 udelay(200); 569 570 /* Initialize all 4 lanes of the SERDES. */ 571 for (i = 0; i < 4; i++) { 572 err = esr2_set_tx_cfg(np, i, tx_cfg); 573 if (err) 574 return err; 575 } 576 577 for (i = 0; i < 4; i++) { 578 err = esr2_set_rx_cfg(np, i, rx_cfg); 579 if (err) 580 return err; 581 } 582 583 /* check if serdes is ready */ 584 585 switch (np->port) { 586 case 0: 587 mask = ESR_INT_SIGNALS_P0_BITS; 588 val = (ESR_INT_SRDY0_P0 | 589 ESR_INT_DET0_P0 | 590 ESR_INT_XSRDY_P0 | 591 ESR_INT_XDP_P0_CH3 | 592 ESR_INT_XDP_P0_CH2 | 593 ESR_INT_XDP_P0_CH1 | 594 ESR_INT_XDP_P0_CH0); 595 break; 596 597 case 1: 598 mask = ESR_INT_SIGNALS_P1_BITS; 599 val = (ESR_INT_SRDY0_P1 | 600 ESR_INT_DET0_P1 | 601 ESR_INT_XSRDY_P1 | 602 ESR_INT_XDP_P1_CH3 | 603 ESR_INT_XDP_P1_CH2 | 604 ESR_INT_XDP_P1_CH1 | 605 ESR_INT_XDP_P1_CH0); 606 break; 607 608 default: 609 return -EINVAL; 610 } 611 612 while (max_retry--) { 613 sig = nr64(ESR_INT_SIGNALS); 614 if ((sig & mask) == val) 615 break; 616 617 mdelay(500); 618 } 619 620 if ((sig & mask) != val) { 621 pr_info("NIU Port %u signal bits [%08x] are not [%08x] for 10G...trying 1G\n", 622 np->port, (int)(sig & mask), (int)val); 623 624 /* 10G failed, try initializing at 1G */ 625 err = serdes_init_niu_1g_serdes(np); 626 if (!err) { 627 np->flags &= ~NIU_FLAGS_10G; 628 np->mac_xcvr = MAC_XCVR_PCS; 629 } else { 630 netdev_err(np->dev, "Port %u 10G/1G SERDES Link Failed\n", 631 np->port); 632 return -ENODEV; 633 } 634 } 635 return 0; 636 } 637 638 static int esr_read_rxtx_ctrl(struct niu *np, unsigned long chan, u32 *val) 639 { 640 int err; 641 642 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR, ESR_RXTX_CTRL_L(chan)); 643 if (err >= 0) { 644 *val = (err & 0xffff); 645 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR, 646 ESR_RXTX_CTRL_H(chan)); 647 if (err >= 0) 648 *val |= ((err & 0xffff) << 16); 649 err = 0; 650 } 651 return err; 652 } 653 654 static int esr_read_glue0(struct niu *np, unsigned long chan, u32 *val) 655 { 656 int err; 657 658 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR, 659 ESR_GLUE_CTRL0_L(chan)); 660 if (err >= 0) { 661 *val = (err & 0xffff); 662 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR, 663 ESR_GLUE_CTRL0_H(chan)); 664 if (err >= 0) { 665 *val |= ((err & 0xffff) << 16); 666 err = 0; 667 } 668 } 669 return err; 670 } 671 672 static int esr_read_reset(struct niu *np, u32 *val) 673 { 674 int err; 675 676 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR, 677 ESR_RXTX_RESET_CTRL_L); 678 if (err >= 0) { 679 *val = (err & 0xffff); 680 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR, 681 ESR_RXTX_RESET_CTRL_H); 682 if (err >= 0) { 683 *val |= ((err & 0xffff) << 16); 684 err = 0; 685 } 686 } 687 return err; 688 } 689 690 static int esr_write_rxtx_ctrl(struct niu *np, unsigned long chan, u32 val) 691 { 692 int err; 693 694 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR, 695 ESR_RXTX_CTRL_L(chan), val & 0xffff); 696 if (!err) 697 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR, 698 ESR_RXTX_CTRL_H(chan), (val >> 16)); 699 return err; 700 } 701 702 static int esr_write_glue0(struct niu *np, unsigned long chan, u32 val) 703 { 704 int err; 705 706 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR, 707 ESR_GLUE_CTRL0_L(chan), val & 0xffff); 708 if (!err) 709 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR, 710 ESR_GLUE_CTRL0_H(chan), (val >> 16)); 711 return err; 712 } 713 714 static int esr_reset(struct niu *np) 715 { 716 u32 uninitialized_var(reset); 717 int err; 718 719 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR, 720 ESR_RXTX_RESET_CTRL_L, 0x0000); 721 if (err) 722 return err; 723 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR, 724 ESR_RXTX_RESET_CTRL_H, 0xffff); 725 if (err) 726 return err; 727 udelay(200); 728 729 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR, 730 ESR_RXTX_RESET_CTRL_L, 0xffff); 731 if (err) 732 return err; 733 udelay(200); 734 735 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR, 736 ESR_RXTX_RESET_CTRL_H, 0x0000); 737 if (err) 738 return err; 739 udelay(200); 740 741 err = esr_read_reset(np, &reset); 742 if (err) 743 return err; 744 if (reset != 0) { 745 netdev_err(np->dev, "Port %u ESR_RESET did not clear [%08x]\n", 746 np->port, reset); 747 return -ENODEV; 748 } 749 750 return 0; 751 } 752 753 static int serdes_init_10g(struct niu *np) 754 { 755 struct niu_link_config *lp = &np->link_config; 756 unsigned long ctrl_reg, test_cfg_reg, i; 757 u64 ctrl_val, test_cfg_val, sig, mask, val; 758 int err; 759 760 switch (np->port) { 761 case 0: 762 ctrl_reg = ENET_SERDES_0_CTRL_CFG; 763 test_cfg_reg = ENET_SERDES_0_TEST_CFG; 764 break; 765 case 1: 766 ctrl_reg = ENET_SERDES_1_CTRL_CFG; 767 test_cfg_reg = ENET_SERDES_1_TEST_CFG; 768 break; 769 770 default: 771 return -EINVAL; 772 } 773 ctrl_val = (ENET_SERDES_CTRL_SDET_0 | 774 ENET_SERDES_CTRL_SDET_1 | 775 ENET_SERDES_CTRL_SDET_2 | 776 ENET_SERDES_CTRL_SDET_3 | 777 (0x5 << ENET_SERDES_CTRL_EMPH_0_SHIFT) | 778 (0x5 << ENET_SERDES_CTRL_EMPH_1_SHIFT) | 779 (0x5 << ENET_SERDES_CTRL_EMPH_2_SHIFT) | 780 (0x5 << ENET_SERDES_CTRL_EMPH_3_SHIFT) | 781 (0x1 << ENET_SERDES_CTRL_LADJ_0_SHIFT) | 782 (0x1 << ENET_SERDES_CTRL_LADJ_1_SHIFT) | 783 (0x1 << ENET_SERDES_CTRL_LADJ_2_SHIFT) | 784 (0x1 << ENET_SERDES_CTRL_LADJ_3_SHIFT)); 785 test_cfg_val = 0; 786 787 if (lp->loopback_mode == LOOPBACK_PHY) { 788 test_cfg_val |= ((ENET_TEST_MD_PAD_LOOPBACK << 789 ENET_SERDES_TEST_MD_0_SHIFT) | 790 (ENET_TEST_MD_PAD_LOOPBACK << 791 ENET_SERDES_TEST_MD_1_SHIFT) | 792 (ENET_TEST_MD_PAD_LOOPBACK << 793 ENET_SERDES_TEST_MD_2_SHIFT) | 794 (ENET_TEST_MD_PAD_LOOPBACK << 795 ENET_SERDES_TEST_MD_3_SHIFT)); 796 } 797 798 nw64(ctrl_reg, ctrl_val); 799 nw64(test_cfg_reg, test_cfg_val); 800 801 /* Initialize all 4 lanes of the SERDES. */ 802 for (i = 0; i < 4; i++) { 803 u32 rxtx_ctrl, glue0; 804 805 err = esr_read_rxtx_ctrl(np, i, &rxtx_ctrl); 806 if (err) 807 return err; 808 err = esr_read_glue0(np, i, &glue0); 809 if (err) 810 return err; 811 812 rxtx_ctrl &= ~(ESR_RXTX_CTRL_VMUXLO); 813 rxtx_ctrl |= (ESR_RXTX_CTRL_ENSTRETCH | 814 (2 << ESR_RXTX_CTRL_VMUXLO_SHIFT)); 815 816 glue0 &= ~(ESR_GLUE_CTRL0_SRATE | 817 ESR_GLUE_CTRL0_THCNT | 818 ESR_GLUE_CTRL0_BLTIME); 819 glue0 |= (ESR_GLUE_CTRL0_RXLOSENAB | 820 (0xf << ESR_GLUE_CTRL0_SRATE_SHIFT) | 821 (0xff << ESR_GLUE_CTRL0_THCNT_SHIFT) | 822 (BLTIME_300_CYCLES << 823 ESR_GLUE_CTRL0_BLTIME_SHIFT)); 824 825 err = esr_write_rxtx_ctrl(np, i, rxtx_ctrl); 826 if (err) 827 return err; 828 err = esr_write_glue0(np, i, glue0); 829 if (err) 830 return err; 831 } 832 833 err = esr_reset(np); 834 if (err) 835 return err; 836 837 sig = nr64(ESR_INT_SIGNALS); 838 switch (np->port) { 839 case 0: 840 mask = ESR_INT_SIGNALS_P0_BITS; 841 val = (ESR_INT_SRDY0_P0 | 842 ESR_INT_DET0_P0 | 843 ESR_INT_XSRDY_P0 | 844 ESR_INT_XDP_P0_CH3 | 845 ESR_INT_XDP_P0_CH2 | 846 ESR_INT_XDP_P0_CH1 | 847 ESR_INT_XDP_P0_CH0); 848 break; 849 850 case 1: 851 mask = ESR_INT_SIGNALS_P1_BITS; 852 val = (ESR_INT_SRDY0_P1 | 853 ESR_INT_DET0_P1 | 854 ESR_INT_XSRDY_P1 | 855 ESR_INT_XDP_P1_CH3 | 856 ESR_INT_XDP_P1_CH2 | 857 ESR_INT_XDP_P1_CH1 | 858 ESR_INT_XDP_P1_CH0); 859 break; 860 861 default: 862 return -EINVAL; 863 } 864 865 if ((sig & mask) != val) { 866 if (np->flags & NIU_FLAGS_HOTPLUG_PHY) { 867 np->flags &= ~NIU_FLAGS_HOTPLUG_PHY_PRESENT; 868 return 0; 869 } 870 netdev_err(np->dev, "Port %u signal bits [%08x] are not [%08x]\n", 871 np->port, (int)(sig & mask), (int)val); 872 return -ENODEV; 873 } 874 if (np->flags & NIU_FLAGS_HOTPLUG_PHY) 875 np->flags |= NIU_FLAGS_HOTPLUG_PHY_PRESENT; 876 return 0; 877 } 878 879 static int serdes_init_1g(struct niu *np) 880 { 881 u64 val; 882 883 val = nr64(ENET_SERDES_1_PLL_CFG); 884 val &= ~ENET_SERDES_PLL_FBDIV2; 885 switch (np->port) { 886 case 0: 887 val |= ENET_SERDES_PLL_HRATE0; 888 break; 889 case 1: 890 val |= ENET_SERDES_PLL_HRATE1; 891 break; 892 case 2: 893 val |= ENET_SERDES_PLL_HRATE2; 894 break; 895 case 3: 896 val |= ENET_SERDES_PLL_HRATE3; 897 break; 898 default: 899 return -EINVAL; 900 } 901 nw64(ENET_SERDES_1_PLL_CFG, val); 902 903 return 0; 904 } 905 906 static int serdes_init_1g_serdes(struct niu *np) 907 { 908 struct niu_link_config *lp = &np->link_config; 909 unsigned long ctrl_reg, test_cfg_reg, pll_cfg, i; 910 u64 ctrl_val, test_cfg_val, sig, mask, val; 911 int err; 912 u64 reset_val, val_rd; 913 914 val = ENET_SERDES_PLL_HRATE0 | ENET_SERDES_PLL_HRATE1 | 915 ENET_SERDES_PLL_HRATE2 | ENET_SERDES_PLL_HRATE3 | 916 ENET_SERDES_PLL_FBDIV0; 917 switch (np->port) { 918 case 0: 919 reset_val = ENET_SERDES_RESET_0; 920 ctrl_reg = ENET_SERDES_0_CTRL_CFG; 921 test_cfg_reg = ENET_SERDES_0_TEST_CFG; 922 pll_cfg = ENET_SERDES_0_PLL_CFG; 923 break; 924 case 1: 925 reset_val = ENET_SERDES_RESET_1; 926 ctrl_reg = ENET_SERDES_1_CTRL_CFG; 927 test_cfg_reg = ENET_SERDES_1_TEST_CFG; 928 pll_cfg = ENET_SERDES_1_PLL_CFG; 929 break; 930 931 default: 932 return -EINVAL; 933 } 934 ctrl_val = (ENET_SERDES_CTRL_SDET_0 | 935 ENET_SERDES_CTRL_SDET_1 | 936 ENET_SERDES_CTRL_SDET_2 | 937 ENET_SERDES_CTRL_SDET_3 | 938 (0x5 << ENET_SERDES_CTRL_EMPH_0_SHIFT) | 939 (0x5 << ENET_SERDES_CTRL_EMPH_1_SHIFT) | 940 (0x5 << ENET_SERDES_CTRL_EMPH_2_SHIFT) | 941 (0x5 << ENET_SERDES_CTRL_EMPH_3_SHIFT) | 942 (0x1 << ENET_SERDES_CTRL_LADJ_0_SHIFT) | 943 (0x1 << ENET_SERDES_CTRL_LADJ_1_SHIFT) | 944 (0x1 << ENET_SERDES_CTRL_LADJ_2_SHIFT) | 945 (0x1 << ENET_SERDES_CTRL_LADJ_3_SHIFT)); 946 test_cfg_val = 0; 947 948 if (lp->loopback_mode == LOOPBACK_PHY) { 949 test_cfg_val |= ((ENET_TEST_MD_PAD_LOOPBACK << 950 ENET_SERDES_TEST_MD_0_SHIFT) | 951 (ENET_TEST_MD_PAD_LOOPBACK << 952 ENET_SERDES_TEST_MD_1_SHIFT) | 953 (ENET_TEST_MD_PAD_LOOPBACK << 954 ENET_SERDES_TEST_MD_2_SHIFT) | 955 (ENET_TEST_MD_PAD_LOOPBACK << 956 ENET_SERDES_TEST_MD_3_SHIFT)); 957 } 958 959 nw64(ENET_SERDES_RESET, reset_val); 960 mdelay(20); 961 val_rd = nr64(ENET_SERDES_RESET); 962 val_rd &= ~reset_val; 963 nw64(pll_cfg, val); 964 nw64(ctrl_reg, ctrl_val); 965 nw64(test_cfg_reg, test_cfg_val); 966 nw64(ENET_SERDES_RESET, val_rd); 967 mdelay(2000); 968 969 /* Initialize all 4 lanes of the SERDES. */ 970 for (i = 0; i < 4; i++) { 971 u32 rxtx_ctrl, glue0; 972 973 err = esr_read_rxtx_ctrl(np, i, &rxtx_ctrl); 974 if (err) 975 return err; 976 err = esr_read_glue0(np, i, &glue0); 977 if (err) 978 return err; 979 980 rxtx_ctrl &= ~(ESR_RXTX_CTRL_VMUXLO); 981 rxtx_ctrl |= (ESR_RXTX_CTRL_ENSTRETCH | 982 (2 << ESR_RXTX_CTRL_VMUXLO_SHIFT)); 983 984 glue0 &= ~(ESR_GLUE_CTRL0_SRATE | 985 ESR_GLUE_CTRL0_THCNT | 986 ESR_GLUE_CTRL0_BLTIME); 987 glue0 |= (ESR_GLUE_CTRL0_RXLOSENAB | 988 (0xf << ESR_GLUE_CTRL0_SRATE_SHIFT) | 989 (0xff << ESR_GLUE_CTRL0_THCNT_SHIFT) | 990 (BLTIME_300_CYCLES << 991 ESR_GLUE_CTRL0_BLTIME_SHIFT)); 992 993 err = esr_write_rxtx_ctrl(np, i, rxtx_ctrl); 994 if (err) 995 return err; 996 err = esr_write_glue0(np, i, glue0); 997 if (err) 998 return err; 999 } 1000 1001 1002 sig = nr64(ESR_INT_SIGNALS); 1003 switch (np->port) { 1004 case 0: 1005 val = (ESR_INT_SRDY0_P0 | ESR_INT_DET0_P0); 1006 mask = val; 1007 break; 1008 1009 case 1: 1010 val = (ESR_INT_SRDY0_P1 | ESR_INT_DET0_P1); 1011 mask = val; 1012 break; 1013 1014 default: 1015 return -EINVAL; 1016 } 1017 1018 if ((sig & mask) != val) { 1019 netdev_err(np->dev, "Port %u signal bits [%08x] are not [%08x]\n", 1020 np->port, (int)(sig & mask), (int)val); 1021 return -ENODEV; 1022 } 1023 1024 return 0; 1025 } 1026 1027 static int link_status_1g_serdes(struct niu *np, int *link_up_p) 1028 { 1029 struct niu_link_config *lp = &np->link_config; 1030 int link_up; 1031 u64 val; 1032 u16 current_speed; 1033 unsigned long flags; 1034 u8 current_duplex; 1035 1036 link_up = 0; 1037 current_speed = SPEED_INVALID; 1038 current_duplex = DUPLEX_INVALID; 1039 1040 spin_lock_irqsave(&np->lock, flags); 1041 1042 val = nr64_pcs(PCS_MII_STAT); 1043 1044 if (val & PCS_MII_STAT_LINK_STATUS) { 1045 link_up = 1; 1046 current_speed = SPEED_1000; 1047 current_duplex = DUPLEX_FULL; 1048 } 1049 1050 lp->active_speed = current_speed; 1051 lp->active_duplex = current_duplex; 1052 spin_unlock_irqrestore(&np->lock, flags); 1053 1054 *link_up_p = link_up; 1055 return 0; 1056 } 1057 1058 static int link_status_10g_serdes(struct niu *np, int *link_up_p) 1059 { 1060 unsigned long flags; 1061 struct niu_link_config *lp = &np->link_config; 1062 int link_up = 0; 1063 int link_ok = 1; 1064 u64 val, val2; 1065 u16 current_speed; 1066 u8 current_duplex; 1067 1068 if (!(np->flags & NIU_FLAGS_10G)) 1069 return link_status_1g_serdes(np, link_up_p); 1070 1071 current_speed = SPEED_INVALID; 1072 current_duplex = DUPLEX_INVALID; 1073 spin_lock_irqsave(&np->lock, flags); 1074 1075 val = nr64_xpcs(XPCS_STATUS(0)); 1076 val2 = nr64_mac(XMAC_INTER2); 1077 if (val2 & 0x01000000) 1078 link_ok = 0; 1079 1080 if ((val & 0x1000ULL) && link_ok) { 1081 link_up = 1; 1082 current_speed = SPEED_10000; 1083 current_duplex = DUPLEX_FULL; 1084 } 1085 lp->active_speed = current_speed; 1086 lp->active_duplex = current_duplex; 1087 spin_unlock_irqrestore(&np->lock, flags); 1088 *link_up_p = link_up; 1089 return 0; 1090 } 1091 1092 static int link_status_mii(struct niu *np, int *link_up_p) 1093 { 1094 struct niu_link_config *lp = &np->link_config; 1095 int err; 1096 int bmsr, advert, ctrl1000, stat1000, lpa, bmcr, estatus; 1097 int supported, advertising, active_speed, active_duplex; 1098 1099 err = mii_read(np, np->phy_addr, MII_BMCR); 1100 if (unlikely(err < 0)) 1101 return err; 1102 bmcr = err; 1103 1104 err = mii_read(np, np->phy_addr, MII_BMSR); 1105 if (unlikely(err < 0)) 1106 return err; 1107 bmsr = err; 1108 1109 err = mii_read(np, np->phy_addr, MII_ADVERTISE); 1110 if (unlikely(err < 0)) 1111 return err; 1112 advert = err; 1113 1114 err = mii_read(np, np->phy_addr, MII_LPA); 1115 if (unlikely(err < 0)) 1116 return err; 1117 lpa = err; 1118 1119 if (likely(bmsr & BMSR_ESTATEN)) { 1120 err = mii_read(np, np->phy_addr, MII_ESTATUS); 1121 if (unlikely(err < 0)) 1122 return err; 1123 estatus = err; 1124 1125 err = mii_read(np, np->phy_addr, MII_CTRL1000); 1126 if (unlikely(err < 0)) 1127 return err; 1128 ctrl1000 = err; 1129 1130 err = mii_read(np, np->phy_addr, MII_STAT1000); 1131 if (unlikely(err < 0)) 1132 return err; 1133 stat1000 = err; 1134 } else 1135 estatus = ctrl1000 = stat1000 = 0; 1136 1137 supported = 0; 1138 if (bmsr & BMSR_ANEGCAPABLE) 1139 supported |= SUPPORTED_Autoneg; 1140 if (bmsr & BMSR_10HALF) 1141 supported |= SUPPORTED_10baseT_Half; 1142 if (bmsr & BMSR_10FULL) 1143 supported |= SUPPORTED_10baseT_Full; 1144 if (bmsr & BMSR_100HALF) 1145 supported |= SUPPORTED_100baseT_Half; 1146 if (bmsr & BMSR_100FULL) 1147 supported |= SUPPORTED_100baseT_Full; 1148 if (estatus & ESTATUS_1000_THALF) 1149 supported |= SUPPORTED_1000baseT_Half; 1150 if (estatus & ESTATUS_1000_TFULL) 1151 supported |= SUPPORTED_1000baseT_Full; 1152 lp->supported = supported; 1153 1154 advertising = mii_adv_to_ethtool_adv_t(advert); 1155 advertising |= mii_ctrl1000_to_ethtool_adv_t(ctrl1000); 1156 1157 if (bmcr & BMCR_ANENABLE) { 1158 int neg, neg1000; 1159 1160 lp->active_autoneg = 1; 1161 advertising |= ADVERTISED_Autoneg; 1162 1163 neg = advert & lpa; 1164 neg1000 = (ctrl1000 << 2) & stat1000; 1165 1166 if (neg1000 & (LPA_1000FULL | LPA_1000HALF)) 1167 active_speed = SPEED_1000; 1168 else if (neg & LPA_100) 1169 active_speed = SPEED_100; 1170 else if (neg & (LPA_10HALF | LPA_10FULL)) 1171 active_speed = SPEED_10; 1172 else 1173 active_speed = SPEED_INVALID; 1174 1175 if ((neg1000 & LPA_1000FULL) || (neg & LPA_DUPLEX)) 1176 active_duplex = DUPLEX_FULL; 1177 else if (active_speed != SPEED_INVALID) 1178 active_duplex = DUPLEX_HALF; 1179 else 1180 active_duplex = DUPLEX_INVALID; 1181 } else { 1182 lp->active_autoneg = 0; 1183 1184 if ((bmcr & BMCR_SPEED1000) && !(bmcr & BMCR_SPEED100)) 1185 active_speed = SPEED_1000; 1186 else if (bmcr & BMCR_SPEED100) 1187 active_speed = SPEED_100; 1188 else 1189 active_speed = SPEED_10; 1190 1191 if (bmcr & BMCR_FULLDPLX) 1192 active_duplex = DUPLEX_FULL; 1193 else 1194 active_duplex = DUPLEX_HALF; 1195 } 1196 1197 lp->active_advertising = advertising; 1198 lp->active_speed = active_speed; 1199 lp->active_duplex = active_duplex; 1200 *link_up_p = !!(bmsr & BMSR_LSTATUS); 1201 1202 return 0; 1203 } 1204 1205 static int link_status_1g_rgmii(struct niu *np, int *link_up_p) 1206 { 1207 struct niu_link_config *lp = &np->link_config; 1208 u16 current_speed, bmsr; 1209 unsigned long flags; 1210 u8 current_duplex; 1211 int err, link_up; 1212 1213 link_up = 0; 1214 current_speed = SPEED_INVALID; 1215 current_duplex = DUPLEX_INVALID; 1216 1217 spin_lock_irqsave(&np->lock, flags); 1218 1219 err = -EINVAL; 1220 1221 err = mii_read(np, np->phy_addr, MII_BMSR); 1222 if (err < 0) 1223 goto out; 1224 1225 bmsr = err; 1226 if (bmsr & BMSR_LSTATUS) { 1227 u16 adv, lpa; 1228 1229 err = mii_read(np, np->phy_addr, MII_ADVERTISE); 1230 if (err < 0) 1231 goto out; 1232 adv = err; 1233 1234 err = mii_read(np, np->phy_addr, MII_LPA); 1235 if (err < 0) 1236 goto out; 1237 lpa = err; 1238 1239 err = mii_read(np, np->phy_addr, MII_ESTATUS); 1240 if (err < 0) 1241 goto out; 1242 link_up = 1; 1243 current_speed = SPEED_1000; 1244 current_duplex = DUPLEX_FULL; 1245 1246 } 1247 lp->active_speed = current_speed; 1248 lp->active_duplex = current_duplex; 1249 err = 0; 1250 1251 out: 1252 spin_unlock_irqrestore(&np->lock, flags); 1253 1254 *link_up_p = link_up; 1255 return err; 1256 } 1257 1258 static int link_status_1g(struct niu *np, int *link_up_p) 1259 { 1260 struct niu_link_config *lp = &np->link_config; 1261 unsigned long flags; 1262 int err; 1263 1264 spin_lock_irqsave(&np->lock, flags); 1265 1266 err = link_status_mii(np, link_up_p); 1267 lp->supported |= SUPPORTED_TP; 1268 lp->active_advertising |= ADVERTISED_TP; 1269 1270 spin_unlock_irqrestore(&np->lock, flags); 1271 return err; 1272 } 1273 1274 static int bcm8704_reset(struct niu *np) 1275 { 1276 int err, limit; 1277 1278 err = mdio_read(np, np->phy_addr, 1279 BCM8704_PHYXS_DEV_ADDR, MII_BMCR); 1280 if (err < 0 || err == 0xffff) 1281 return err; 1282 err |= BMCR_RESET; 1283 err = mdio_write(np, np->phy_addr, BCM8704_PHYXS_DEV_ADDR, 1284 MII_BMCR, err); 1285 if (err) 1286 return err; 1287 1288 limit = 1000; 1289 while (--limit >= 0) { 1290 err = mdio_read(np, np->phy_addr, 1291 BCM8704_PHYXS_DEV_ADDR, MII_BMCR); 1292 if (err < 0) 1293 return err; 1294 if (!(err & BMCR_RESET)) 1295 break; 1296 } 1297 if (limit < 0) { 1298 netdev_err(np->dev, "Port %u PHY will not reset (bmcr=%04x)\n", 1299 np->port, (err & 0xffff)); 1300 return -ENODEV; 1301 } 1302 return 0; 1303 } 1304 1305 /* When written, certain PHY registers need to be read back twice 1306 * in order for the bits to settle properly. 1307 */ 1308 static int bcm8704_user_dev3_readback(struct niu *np, int reg) 1309 { 1310 int err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR, reg); 1311 if (err < 0) 1312 return err; 1313 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR, reg); 1314 if (err < 0) 1315 return err; 1316 return 0; 1317 } 1318 1319 static int bcm8706_init_user_dev3(struct niu *np) 1320 { 1321 int err; 1322 1323 1324 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR, 1325 BCM8704_USER_OPT_DIGITAL_CTRL); 1326 if (err < 0) 1327 return err; 1328 err &= ~USER_ODIG_CTRL_GPIOS; 1329 err |= (0x3 << USER_ODIG_CTRL_GPIOS_SHIFT); 1330 err |= USER_ODIG_CTRL_RESV2; 1331 err = mdio_write(np, np->phy_addr, BCM8704_USER_DEV3_ADDR, 1332 BCM8704_USER_OPT_DIGITAL_CTRL, err); 1333 if (err) 1334 return err; 1335 1336 mdelay(1000); 1337 1338 return 0; 1339 } 1340 1341 static int bcm8704_init_user_dev3(struct niu *np) 1342 { 1343 int err; 1344 1345 err = mdio_write(np, np->phy_addr, 1346 BCM8704_USER_DEV3_ADDR, BCM8704_USER_CONTROL, 1347 (USER_CONTROL_OPTXRST_LVL | 1348 USER_CONTROL_OPBIASFLT_LVL | 1349 USER_CONTROL_OBTMPFLT_LVL | 1350 USER_CONTROL_OPPRFLT_LVL | 1351 USER_CONTROL_OPTXFLT_LVL | 1352 USER_CONTROL_OPRXLOS_LVL | 1353 USER_CONTROL_OPRXFLT_LVL | 1354 USER_CONTROL_OPTXON_LVL | 1355 (0x3f << USER_CONTROL_RES1_SHIFT))); 1356 if (err) 1357 return err; 1358 1359 err = mdio_write(np, np->phy_addr, 1360 BCM8704_USER_DEV3_ADDR, BCM8704_USER_PMD_TX_CONTROL, 1361 (USER_PMD_TX_CTL_XFP_CLKEN | 1362 (1 << USER_PMD_TX_CTL_TX_DAC_TXD_SH) | 1363 (2 << USER_PMD_TX_CTL_TX_DAC_TXCK_SH) | 1364 USER_PMD_TX_CTL_TSCK_LPWREN)); 1365 if (err) 1366 return err; 1367 1368 err = bcm8704_user_dev3_readback(np, BCM8704_USER_CONTROL); 1369 if (err) 1370 return err; 1371 err = bcm8704_user_dev3_readback(np, BCM8704_USER_PMD_TX_CONTROL); 1372 if (err) 1373 return err; 1374 1375 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR, 1376 BCM8704_USER_OPT_DIGITAL_CTRL); 1377 if (err < 0) 1378 return err; 1379 err &= ~USER_ODIG_CTRL_GPIOS; 1380 err |= (0x3 << USER_ODIG_CTRL_GPIOS_SHIFT); 1381 err = mdio_write(np, np->phy_addr, BCM8704_USER_DEV3_ADDR, 1382 BCM8704_USER_OPT_DIGITAL_CTRL, err); 1383 if (err) 1384 return err; 1385 1386 mdelay(1000); 1387 1388 return 0; 1389 } 1390 1391 static int mrvl88x2011_act_led(struct niu *np, int val) 1392 { 1393 int err; 1394 1395 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV2_ADDR, 1396 MRVL88X2011_LED_8_TO_11_CTL); 1397 if (err < 0) 1398 return err; 1399 1400 err &= ~MRVL88X2011_LED(MRVL88X2011_LED_ACT,MRVL88X2011_LED_CTL_MASK); 1401 err |= MRVL88X2011_LED(MRVL88X2011_LED_ACT,val); 1402 1403 return mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV2_ADDR, 1404 MRVL88X2011_LED_8_TO_11_CTL, err); 1405 } 1406 1407 static int mrvl88x2011_led_blink_rate(struct niu *np, int rate) 1408 { 1409 int err; 1410 1411 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV2_ADDR, 1412 MRVL88X2011_LED_BLINK_CTL); 1413 if (err >= 0) { 1414 err &= ~MRVL88X2011_LED_BLKRATE_MASK; 1415 err |= (rate << 4); 1416 1417 err = mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV2_ADDR, 1418 MRVL88X2011_LED_BLINK_CTL, err); 1419 } 1420 1421 return err; 1422 } 1423 1424 static int xcvr_init_10g_mrvl88x2011(struct niu *np) 1425 { 1426 int err; 1427 1428 /* Set LED functions */ 1429 err = mrvl88x2011_led_blink_rate(np, MRVL88X2011_LED_BLKRATE_134MS); 1430 if (err) 1431 return err; 1432 1433 /* led activity */ 1434 err = mrvl88x2011_act_led(np, MRVL88X2011_LED_CTL_OFF); 1435 if (err) 1436 return err; 1437 1438 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV3_ADDR, 1439 MRVL88X2011_GENERAL_CTL); 1440 if (err < 0) 1441 return err; 1442 1443 err |= MRVL88X2011_ENA_XFPREFCLK; 1444 1445 err = mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV3_ADDR, 1446 MRVL88X2011_GENERAL_CTL, err); 1447 if (err < 0) 1448 return err; 1449 1450 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR, 1451 MRVL88X2011_PMA_PMD_CTL_1); 1452 if (err < 0) 1453 return err; 1454 1455 if (np->link_config.loopback_mode == LOOPBACK_MAC) 1456 err |= MRVL88X2011_LOOPBACK; 1457 else 1458 err &= ~MRVL88X2011_LOOPBACK; 1459 1460 err = mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR, 1461 MRVL88X2011_PMA_PMD_CTL_1, err); 1462 if (err < 0) 1463 return err; 1464 1465 /* Enable PMD */ 1466 return mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR, 1467 MRVL88X2011_10G_PMD_TX_DIS, MRVL88X2011_ENA_PMDTX); 1468 } 1469 1470 1471 static int xcvr_diag_bcm870x(struct niu *np) 1472 { 1473 u16 analog_stat0, tx_alarm_status; 1474 int err = 0; 1475 1476 #if 1 1477 err = mdio_read(np, np->phy_addr, BCM8704_PMA_PMD_DEV_ADDR, 1478 MII_STAT1000); 1479 if (err < 0) 1480 return err; 1481 pr_info("Port %u PMA_PMD(MII_STAT1000) [%04x]\n", np->port, err); 1482 1483 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR, 0x20); 1484 if (err < 0) 1485 return err; 1486 pr_info("Port %u USER_DEV3(0x20) [%04x]\n", np->port, err); 1487 1488 err = mdio_read(np, np->phy_addr, BCM8704_PHYXS_DEV_ADDR, 1489 MII_NWAYTEST); 1490 if (err < 0) 1491 return err; 1492 pr_info("Port %u PHYXS(MII_NWAYTEST) [%04x]\n", np->port, err); 1493 #endif 1494 1495 /* XXX dig this out it might not be so useful XXX */ 1496 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR, 1497 BCM8704_USER_ANALOG_STATUS0); 1498 if (err < 0) 1499 return err; 1500 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR, 1501 BCM8704_USER_ANALOG_STATUS0); 1502 if (err < 0) 1503 return err; 1504 analog_stat0 = err; 1505 1506 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR, 1507 BCM8704_USER_TX_ALARM_STATUS); 1508 if (err < 0) 1509 return err; 1510 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR, 1511 BCM8704_USER_TX_ALARM_STATUS); 1512 if (err < 0) 1513 return err; 1514 tx_alarm_status = err; 1515 1516 if (analog_stat0 != 0x03fc) { 1517 if ((analog_stat0 == 0x43bc) && (tx_alarm_status != 0)) { 1518 pr_info("Port %u cable not connected or bad cable\n", 1519 np->port); 1520 } else if (analog_stat0 == 0x639c) { 1521 pr_info("Port %u optical module is bad or missing\n", 1522 np->port); 1523 } 1524 } 1525 1526 return 0; 1527 } 1528 1529 static int xcvr_10g_set_lb_bcm870x(struct niu *np) 1530 { 1531 struct niu_link_config *lp = &np->link_config; 1532 int err; 1533 1534 err = mdio_read(np, np->phy_addr, BCM8704_PCS_DEV_ADDR, 1535 MII_BMCR); 1536 if (err < 0) 1537 return err; 1538 1539 err &= ~BMCR_LOOPBACK; 1540 1541 if (lp->loopback_mode == LOOPBACK_MAC) 1542 err |= BMCR_LOOPBACK; 1543 1544 err = mdio_write(np, np->phy_addr, BCM8704_PCS_DEV_ADDR, 1545 MII_BMCR, err); 1546 if (err) 1547 return err; 1548 1549 return 0; 1550 } 1551 1552 static int xcvr_init_10g_bcm8706(struct niu *np) 1553 { 1554 int err = 0; 1555 u64 val; 1556 1557 if ((np->flags & NIU_FLAGS_HOTPLUG_PHY) && 1558 (np->flags & NIU_FLAGS_HOTPLUG_PHY_PRESENT) == 0) 1559 return err; 1560 1561 val = nr64_mac(XMAC_CONFIG); 1562 val &= ~XMAC_CONFIG_LED_POLARITY; 1563 val |= XMAC_CONFIG_FORCE_LED_ON; 1564 nw64_mac(XMAC_CONFIG, val); 1565 1566 val = nr64(MIF_CONFIG); 1567 val |= MIF_CONFIG_INDIRECT_MODE; 1568 nw64(MIF_CONFIG, val); 1569 1570 err = bcm8704_reset(np); 1571 if (err) 1572 return err; 1573 1574 err = xcvr_10g_set_lb_bcm870x(np); 1575 if (err) 1576 return err; 1577 1578 err = bcm8706_init_user_dev3(np); 1579 if (err) 1580 return err; 1581 1582 err = xcvr_diag_bcm870x(np); 1583 if (err) 1584 return err; 1585 1586 return 0; 1587 } 1588 1589 static int xcvr_init_10g_bcm8704(struct niu *np) 1590 { 1591 int err; 1592 1593 err = bcm8704_reset(np); 1594 if (err) 1595 return err; 1596 1597 err = bcm8704_init_user_dev3(np); 1598 if (err) 1599 return err; 1600 1601 err = xcvr_10g_set_lb_bcm870x(np); 1602 if (err) 1603 return err; 1604 1605 err = xcvr_diag_bcm870x(np); 1606 if (err) 1607 return err; 1608 1609 return 0; 1610 } 1611 1612 static int xcvr_init_10g(struct niu *np) 1613 { 1614 int phy_id, err; 1615 u64 val; 1616 1617 val = nr64_mac(XMAC_CONFIG); 1618 val &= ~XMAC_CONFIG_LED_POLARITY; 1619 val |= XMAC_CONFIG_FORCE_LED_ON; 1620 nw64_mac(XMAC_CONFIG, val); 1621 1622 /* XXX shared resource, lock parent XXX */ 1623 val = nr64(MIF_CONFIG); 1624 val |= MIF_CONFIG_INDIRECT_MODE; 1625 nw64(MIF_CONFIG, val); 1626 1627 phy_id = phy_decode(np->parent->port_phy, np->port); 1628 phy_id = np->parent->phy_probe_info.phy_id[phy_id][np->port]; 1629 1630 /* handle different phy types */ 1631 switch (phy_id & NIU_PHY_ID_MASK) { 1632 case NIU_PHY_ID_MRVL88X2011: 1633 err = xcvr_init_10g_mrvl88x2011(np); 1634 break; 1635 1636 default: /* bcom 8704 */ 1637 err = xcvr_init_10g_bcm8704(np); 1638 break; 1639 } 1640 1641 return err; 1642 } 1643 1644 static int mii_reset(struct niu *np) 1645 { 1646 int limit, err; 1647 1648 err = mii_write(np, np->phy_addr, MII_BMCR, BMCR_RESET); 1649 if (err) 1650 return err; 1651 1652 limit = 1000; 1653 while (--limit >= 0) { 1654 udelay(500); 1655 err = mii_read(np, np->phy_addr, MII_BMCR); 1656 if (err < 0) 1657 return err; 1658 if (!(err & BMCR_RESET)) 1659 break; 1660 } 1661 if (limit < 0) { 1662 netdev_err(np->dev, "Port %u MII would not reset, bmcr[%04x]\n", 1663 np->port, err); 1664 return -ENODEV; 1665 } 1666 1667 return 0; 1668 } 1669 1670 static int xcvr_init_1g_rgmii(struct niu *np) 1671 { 1672 int err; 1673 u64 val; 1674 u16 bmcr, bmsr, estat; 1675 1676 val = nr64(MIF_CONFIG); 1677 val &= ~MIF_CONFIG_INDIRECT_MODE; 1678 nw64(MIF_CONFIG, val); 1679 1680 err = mii_reset(np); 1681 if (err) 1682 return err; 1683 1684 err = mii_read(np, np->phy_addr, MII_BMSR); 1685 if (err < 0) 1686 return err; 1687 bmsr = err; 1688 1689 estat = 0; 1690 if (bmsr & BMSR_ESTATEN) { 1691 err = mii_read(np, np->phy_addr, MII_ESTATUS); 1692 if (err < 0) 1693 return err; 1694 estat = err; 1695 } 1696 1697 bmcr = 0; 1698 err = mii_write(np, np->phy_addr, MII_BMCR, bmcr); 1699 if (err) 1700 return err; 1701 1702 if (bmsr & BMSR_ESTATEN) { 1703 u16 ctrl1000 = 0; 1704 1705 if (estat & ESTATUS_1000_TFULL) 1706 ctrl1000 |= ADVERTISE_1000FULL; 1707 err = mii_write(np, np->phy_addr, MII_CTRL1000, ctrl1000); 1708 if (err) 1709 return err; 1710 } 1711 1712 bmcr = (BMCR_SPEED1000 | BMCR_FULLDPLX); 1713 1714 err = mii_write(np, np->phy_addr, MII_BMCR, bmcr); 1715 if (err) 1716 return err; 1717 1718 err = mii_read(np, np->phy_addr, MII_BMCR); 1719 if (err < 0) 1720 return err; 1721 bmcr = mii_read(np, np->phy_addr, MII_BMCR); 1722 1723 err = mii_read(np, np->phy_addr, MII_BMSR); 1724 if (err < 0) 1725 return err; 1726 1727 return 0; 1728 } 1729 1730 static int mii_init_common(struct niu *np) 1731 { 1732 struct niu_link_config *lp = &np->link_config; 1733 u16 bmcr, bmsr, adv, estat; 1734 int err; 1735 1736 err = mii_reset(np); 1737 if (err) 1738 return err; 1739 1740 err = mii_read(np, np->phy_addr, MII_BMSR); 1741 if (err < 0) 1742 return err; 1743 bmsr = err; 1744 1745 estat = 0; 1746 if (bmsr & BMSR_ESTATEN) { 1747 err = mii_read(np, np->phy_addr, MII_ESTATUS); 1748 if (err < 0) 1749 return err; 1750 estat = err; 1751 } 1752 1753 bmcr = 0; 1754 err = mii_write(np, np->phy_addr, MII_BMCR, bmcr); 1755 if (err) 1756 return err; 1757 1758 if (lp->loopback_mode == LOOPBACK_MAC) { 1759 bmcr |= BMCR_LOOPBACK; 1760 if (lp->active_speed == SPEED_1000) 1761 bmcr |= BMCR_SPEED1000; 1762 if (lp->active_duplex == DUPLEX_FULL) 1763 bmcr |= BMCR_FULLDPLX; 1764 } 1765 1766 if (lp->loopback_mode == LOOPBACK_PHY) { 1767 u16 aux; 1768 1769 aux = (BCM5464R_AUX_CTL_EXT_LB | 1770 BCM5464R_AUX_CTL_WRITE_1); 1771 err = mii_write(np, np->phy_addr, BCM5464R_AUX_CTL, aux); 1772 if (err) 1773 return err; 1774 } 1775 1776 if (lp->autoneg) { 1777 u16 ctrl1000; 1778 1779 adv = ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP; 1780 if ((bmsr & BMSR_10HALF) && 1781 (lp->advertising & ADVERTISED_10baseT_Half)) 1782 adv |= ADVERTISE_10HALF; 1783 if ((bmsr & BMSR_10FULL) && 1784 (lp->advertising & ADVERTISED_10baseT_Full)) 1785 adv |= ADVERTISE_10FULL; 1786 if ((bmsr & BMSR_100HALF) && 1787 (lp->advertising & ADVERTISED_100baseT_Half)) 1788 adv |= ADVERTISE_100HALF; 1789 if ((bmsr & BMSR_100FULL) && 1790 (lp->advertising & ADVERTISED_100baseT_Full)) 1791 adv |= ADVERTISE_100FULL; 1792 err = mii_write(np, np->phy_addr, MII_ADVERTISE, adv); 1793 if (err) 1794 return err; 1795 1796 if (likely(bmsr & BMSR_ESTATEN)) { 1797 ctrl1000 = 0; 1798 if ((estat & ESTATUS_1000_THALF) && 1799 (lp->advertising & ADVERTISED_1000baseT_Half)) 1800 ctrl1000 |= ADVERTISE_1000HALF; 1801 if ((estat & ESTATUS_1000_TFULL) && 1802 (lp->advertising & ADVERTISED_1000baseT_Full)) 1803 ctrl1000 |= ADVERTISE_1000FULL; 1804 err = mii_write(np, np->phy_addr, 1805 MII_CTRL1000, ctrl1000); 1806 if (err) 1807 return err; 1808 } 1809 1810 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART); 1811 } else { 1812 /* !lp->autoneg */ 1813 int fulldpx; 1814 1815 if (lp->duplex == DUPLEX_FULL) { 1816 bmcr |= BMCR_FULLDPLX; 1817 fulldpx = 1; 1818 } else if (lp->duplex == DUPLEX_HALF) 1819 fulldpx = 0; 1820 else 1821 return -EINVAL; 1822 1823 if (lp->speed == SPEED_1000) { 1824 /* if X-full requested while not supported, or 1825 X-half requested while not supported... */ 1826 if ((fulldpx && !(estat & ESTATUS_1000_TFULL)) || 1827 (!fulldpx && !(estat & ESTATUS_1000_THALF))) 1828 return -EINVAL; 1829 bmcr |= BMCR_SPEED1000; 1830 } else if (lp->speed == SPEED_100) { 1831 if ((fulldpx && !(bmsr & BMSR_100FULL)) || 1832 (!fulldpx && !(bmsr & BMSR_100HALF))) 1833 return -EINVAL; 1834 bmcr |= BMCR_SPEED100; 1835 } else if (lp->speed == SPEED_10) { 1836 if ((fulldpx && !(bmsr & BMSR_10FULL)) || 1837 (!fulldpx && !(bmsr & BMSR_10HALF))) 1838 return -EINVAL; 1839 } else 1840 return -EINVAL; 1841 } 1842 1843 err = mii_write(np, np->phy_addr, MII_BMCR, bmcr); 1844 if (err) 1845 return err; 1846 1847 #if 0 1848 err = mii_read(np, np->phy_addr, MII_BMCR); 1849 if (err < 0) 1850 return err; 1851 bmcr = err; 1852 1853 err = mii_read(np, np->phy_addr, MII_BMSR); 1854 if (err < 0) 1855 return err; 1856 bmsr = err; 1857 1858 pr_info("Port %u after MII init bmcr[%04x] bmsr[%04x]\n", 1859 np->port, bmcr, bmsr); 1860 #endif 1861 1862 return 0; 1863 } 1864 1865 static int xcvr_init_1g(struct niu *np) 1866 { 1867 u64 val; 1868 1869 /* XXX shared resource, lock parent XXX */ 1870 val = nr64(MIF_CONFIG); 1871 val &= ~MIF_CONFIG_INDIRECT_MODE; 1872 nw64(MIF_CONFIG, val); 1873 1874 return mii_init_common(np); 1875 } 1876 1877 static int niu_xcvr_init(struct niu *np) 1878 { 1879 const struct niu_phy_ops *ops = np->phy_ops; 1880 int err; 1881 1882 err = 0; 1883 if (ops->xcvr_init) 1884 err = ops->xcvr_init(np); 1885 1886 return err; 1887 } 1888 1889 static int niu_serdes_init(struct niu *np) 1890 { 1891 const struct niu_phy_ops *ops = np->phy_ops; 1892 int err; 1893 1894 err = 0; 1895 if (ops->serdes_init) 1896 err = ops->serdes_init(np); 1897 1898 return err; 1899 } 1900 1901 static void niu_init_xif(struct niu *); 1902 static void niu_handle_led(struct niu *, int status); 1903 1904 static int niu_link_status_common(struct niu *np, int link_up) 1905 { 1906 struct niu_link_config *lp = &np->link_config; 1907 struct net_device *dev = np->dev; 1908 unsigned long flags; 1909 1910 if (!netif_carrier_ok(dev) && link_up) { 1911 netif_info(np, link, dev, "Link is up at %s, %s duplex\n", 1912 lp->active_speed == SPEED_10000 ? "10Gb/sec" : 1913 lp->active_speed == SPEED_1000 ? "1Gb/sec" : 1914 lp->active_speed == SPEED_100 ? "100Mbit/sec" : 1915 "10Mbit/sec", 1916 lp->active_duplex == DUPLEX_FULL ? "full" : "half"); 1917 1918 spin_lock_irqsave(&np->lock, flags); 1919 niu_init_xif(np); 1920 niu_handle_led(np, 1); 1921 spin_unlock_irqrestore(&np->lock, flags); 1922 1923 netif_carrier_on(dev); 1924 } else if (netif_carrier_ok(dev) && !link_up) { 1925 netif_warn(np, link, dev, "Link is down\n"); 1926 spin_lock_irqsave(&np->lock, flags); 1927 niu_handle_led(np, 0); 1928 spin_unlock_irqrestore(&np->lock, flags); 1929 netif_carrier_off(dev); 1930 } 1931 1932 return 0; 1933 } 1934 1935 static int link_status_10g_mrvl(struct niu *np, int *link_up_p) 1936 { 1937 int err, link_up, pma_status, pcs_status; 1938 1939 link_up = 0; 1940 1941 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR, 1942 MRVL88X2011_10G_PMD_STATUS_2); 1943 if (err < 0) 1944 goto out; 1945 1946 /* Check PMA/PMD Register: 1.0001.2 == 1 */ 1947 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR, 1948 MRVL88X2011_PMA_PMD_STATUS_1); 1949 if (err < 0) 1950 goto out; 1951 1952 pma_status = ((err & MRVL88X2011_LNK_STATUS_OK) ? 1 : 0); 1953 1954 /* Check PMC Register : 3.0001.2 == 1: read twice */ 1955 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV3_ADDR, 1956 MRVL88X2011_PMA_PMD_STATUS_1); 1957 if (err < 0) 1958 goto out; 1959 1960 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV3_ADDR, 1961 MRVL88X2011_PMA_PMD_STATUS_1); 1962 if (err < 0) 1963 goto out; 1964 1965 pcs_status = ((err & MRVL88X2011_LNK_STATUS_OK) ? 1 : 0); 1966 1967 /* Check XGXS Register : 4.0018.[0-3,12] */ 1968 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV4_ADDR, 1969 MRVL88X2011_10G_XGXS_LANE_STAT); 1970 if (err < 0) 1971 goto out; 1972 1973 if (err == (PHYXS_XGXS_LANE_STAT_ALINGED | PHYXS_XGXS_LANE_STAT_LANE3 | 1974 PHYXS_XGXS_LANE_STAT_LANE2 | PHYXS_XGXS_LANE_STAT_LANE1 | 1975 PHYXS_XGXS_LANE_STAT_LANE0 | PHYXS_XGXS_LANE_STAT_MAGIC | 1976 0x800)) 1977 link_up = (pma_status && pcs_status) ? 1 : 0; 1978 1979 np->link_config.active_speed = SPEED_10000; 1980 np->link_config.active_duplex = DUPLEX_FULL; 1981 err = 0; 1982 out: 1983 mrvl88x2011_act_led(np, (link_up ? 1984 MRVL88X2011_LED_CTL_PCS_ACT : 1985 MRVL88X2011_LED_CTL_OFF)); 1986 1987 *link_up_p = link_up; 1988 return err; 1989 } 1990 1991 static int link_status_10g_bcm8706(struct niu *np, int *link_up_p) 1992 { 1993 int err, link_up; 1994 link_up = 0; 1995 1996 err = mdio_read(np, np->phy_addr, BCM8704_PMA_PMD_DEV_ADDR, 1997 BCM8704_PMD_RCV_SIGDET); 1998 if (err < 0 || err == 0xffff) 1999 goto out; 2000 if (!(err & PMD_RCV_SIGDET_GLOBAL)) { 2001 err = 0; 2002 goto out; 2003 } 2004 2005 err = mdio_read(np, np->phy_addr, BCM8704_PCS_DEV_ADDR, 2006 BCM8704_PCS_10G_R_STATUS); 2007 if (err < 0) 2008 goto out; 2009 2010 if (!(err & PCS_10G_R_STATUS_BLK_LOCK)) { 2011 err = 0; 2012 goto out; 2013 } 2014 2015 err = mdio_read(np, np->phy_addr, BCM8704_PHYXS_DEV_ADDR, 2016 BCM8704_PHYXS_XGXS_LANE_STAT); 2017 if (err < 0) 2018 goto out; 2019 if (err != (PHYXS_XGXS_LANE_STAT_ALINGED | 2020 PHYXS_XGXS_LANE_STAT_MAGIC | 2021 PHYXS_XGXS_LANE_STAT_PATTEST | 2022 PHYXS_XGXS_LANE_STAT_LANE3 | 2023 PHYXS_XGXS_LANE_STAT_LANE2 | 2024 PHYXS_XGXS_LANE_STAT_LANE1 | 2025 PHYXS_XGXS_LANE_STAT_LANE0)) { 2026 err = 0; 2027 np->link_config.active_speed = SPEED_INVALID; 2028 np->link_config.active_duplex = DUPLEX_INVALID; 2029 goto out; 2030 } 2031 2032 link_up = 1; 2033 np->link_config.active_speed = SPEED_10000; 2034 np->link_config.active_duplex = DUPLEX_FULL; 2035 err = 0; 2036 2037 out: 2038 *link_up_p = link_up; 2039 return err; 2040 } 2041 2042 static int link_status_10g_bcom(struct niu *np, int *link_up_p) 2043 { 2044 int err, link_up; 2045 2046 link_up = 0; 2047 2048 err = mdio_read(np, np->phy_addr, BCM8704_PMA_PMD_DEV_ADDR, 2049 BCM8704_PMD_RCV_SIGDET); 2050 if (err < 0) 2051 goto out; 2052 if (!(err & PMD_RCV_SIGDET_GLOBAL)) { 2053 err = 0; 2054 goto out; 2055 } 2056 2057 err = mdio_read(np, np->phy_addr, BCM8704_PCS_DEV_ADDR, 2058 BCM8704_PCS_10G_R_STATUS); 2059 if (err < 0) 2060 goto out; 2061 if (!(err & PCS_10G_R_STATUS_BLK_LOCK)) { 2062 err = 0; 2063 goto out; 2064 } 2065 2066 err = mdio_read(np, np->phy_addr, BCM8704_PHYXS_DEV_ADDR, 2067 BCM8704_PHYXS_XGXS_LANE_STAT); 2068 if (err < 0) 2069 goto out; 2070 2071 if (err != (PHYXS_XGXS_LANE_STAT_ALINGED | 2072 PHYXS_XGXS_LANE_STAT_MAGIC | 2073 PHYXS_XGXS_LANE_STAT_LANE3 | 2074 PHYXS_XGXS_LANE_STAT_LANE2 | 2075 PHYXS_XGXS_LANE_STAT_LANE1 | 2076 PHYXS_XGXS_LANE_STAT_LANE0)) { 2077 err = 0; 2078 goto out; 2079 } 2080 2081 link_up = 1; 2082 np->link_config.active_speed = SPEED_10000; 2083 np->link_config.active_duplex = DUPLEX_FULL; 2084 err = 0; 2085 2086 out: 2087 *link_up_p = link_up; 2088 return err; 2089 } 2090 2091 static int link_status_10g(struct niu *np, int *link_up_p) 2092 { 2093 unsigned long flags; 2094 int err = -EINVAL; 2095 2096 spin_lock_irqsave(&np->lock, flags); 2097 2098 if (np->link_config.loopback_mode == LOOPBACK_DISABLED) { 2099 int phy_id; 2100 2101 phy_id = phy_decode(np->parent->port_phy, np->port); 2102 phy_id = np->parent->phy_probe_info.phy_id[phy_id][np->port]; 2103 2104 /* handle different phy types */ 2105 switch (phy_id & NIU_PHY_ID_MASK) { 2106 case NIU_PHY_ID_MRVL88X2011: 2107 err = link_status_10g_mrvl(np, link_up_p); 2108 break; 2109 2110 default: /* bcom 8704 */ 2111 err = link_status_10g_bcom(np, link_up_p); 2112 break; 2113 } 2114 } 2115 2116 spin_unlock_irqrestore(&np->lock, flags); 2117 2118 return err; 2119 } 2120 2121 static int niu_10g_phy_present(struct niu *np) 2122 { 2123 u64 sig, mask, val; 2124 2125 sig = nr64(ESR_INT_SIGNALS); 2126 switch (np->port) { 2127 case 0: 2128 mask = ESR_INT_SIGNALS_P0_BITS; 2129 val = (ESR_INT_SRDY0_P0 | 2130 ESR_INT_DET0_P0 | 2131 ESR_INT_XSRDY_P0 | 2132 ESR_INT_XDP_P0_CH3 | 2133 ESR_INT_XDP_P0_CH2 | 2134 ESR_INT_XDP_P0_CH1 | 2135 ESR_INT_XDP_P0_CH0); 2136 break; 2137 2138 case 1: 2139 mask = ESR_INT_SIGNALS_P1_BITS; 2140 val = (ESR_INT_SRDY0_P1 | 2141 ESR_INT_DET0_P1 | 2142 ESR_INT_XSRDY_P1 | 2143 ESR_INT_XDP_P1_CH3 | 2144 ESR_INT_XDP_P1_CH2 | 2145 ESR_INT_XDP_P1_CH1 | 2146 ESR_INT_XDP_P1_CH0); 2147 break; 2148 2149 default: 2150 return 0; 2151 } 2152 2153 if ((sig & mask) != val) 2154 return 0; 2155 return 1; 2156 } 2157 2158 static int link_status_10g_hotplug(struct niu *np, int *link_up_p) 2159 { 2160 unsigned long flags; 2161 int err = 0; 2162 int phy_present; 2163 int phy_present_prev; 2164 2165 spin_lock_irqsave(&np->lock, flags); 2166 2167 if (np->link_config.loopback_mode == LOOPBACK_DISABLED) { 2168 phy_present_prev = (np->flags & NIU_FLAGS_HOTPLUG_PHY_PRESENT) ? 2169 1 : 0; 2170 phy_present = niu_10g_phy_present(np); 2171 if (phy_present != phy_present_prev) { 2172 /* state change */ 2173 if (phy_present) { 2174 /* A NEM was just plugged in */ 2175 np->flags |= NIU_FLAGS_HOTPLUG_PHY_PRESENT; 2176 if (np->phy_ops->xcvr_init) 2177 err = np->phy_ops->xcvr_init(np); 2178 if (err) { 2179 err = mdio_read(np, np->phy_addr, 2180 BCM8704_PHYXS_DEV_ADDR, MII_BMCR); 2181 if (err == 0xffff) { 2182 /* No mdio, back-to-back XAUI */ 2183 goto out; 2184 } 2185 /* debounce */ 2186 np->flags &= ~NIU_FLAGS_HOTPLUG_PHY_PRESENT; 2187 } 2188 } else { 2189 np->flags &= ~NIU_FLAGS_HOTPLUG_PHY_PRESENT; 2190 *link_up_p = 0; 2191 netif_warn(np, link, np->dev, 2192 "Hotplug PHY Removed\n"); 2193 } 2194 } 2195 out: 2196 if (np->flags & NIU_FLAGS_HOTPLUG_PHY_PRESENT) { 2197 err = link_status_10g_bcm8706(np, link_up_p); 2198 if (err == 0xffff) { 2199 /* No mdio, back-to-back XAUI: it is C10NEM */ 2200 *link_up_p = 1; 2201 np->link_config.active_speed = SPEED_10000; 2202 np->link_config.active_duplex = DUPLEX_FULL; 2203 } 2204 } 2205 } 2206 2207 spin_unlock_irqrestore(&np->lock, flags); 2208 2209 return 0; 2210 } 2211 2212 static int niu_link_status(struct niu *np, int *link_up_p) 2213 { 2214 const struct niu_phy_ops *ops = np->phy_ops; 2215 int err; 2216 2217 err = 0; 2218 if (ops->link_status) 2219 err = ops->link_status(np, link_up_p); 2220 2221 return err; 2222 } 2223 2224 static void niu_timer(unsigned long __opaque) 2225 { 2226 struct niu *np = (struct niu *) __opaque; 2227 unsigned long off; 2228 int err, link_up; 2229 2230 err = niu_link_status(np, &link_up); 2231 if (!err) 2232 niu_link_status_common(np, link_up); 2233 2234 if (netif_carrier_ok(np->dev)) 2235 off = 5 * HZ; 2236 else 2237 off = 1 * HZ; 2238 np->timer.expires = jiffies + off; 2239 2240 add_timer(&np->timer); 2241 } 2242 2243 static const struct niu_phy_ops phy_ops_10g_serdes = { 2244 .serdes_init = serdes_init_10g_serdes, 2245 .link_status = link_status_10g_serdes, 2246 }; 2247 2248 static const struct niu_phy_ops phy_ops_10g_serdes_niu = { 2249 .serdes_init = serdes_init_niu_10g_serdes, 2250 .link_status = link_status_10g_serdes, 2251 }; 2252 2253 static const struct niu_phy_ops phy_ops_1g_serdes_niu = { 2254 .serdes_init = serdes_init_niu_1g_serdes, 2255 .link_status = link_status_1g_serdes, 2256 }; 2257 2258 static const struct niu_phy_ops phy_ops_1g_rgmii = { 2259 .xcvr_init = xcvr_init_1g_rgmii, 2260 .link_status = link_status_1g_rgmii, 2261 }; 2262 2263 static const struct niu_phy_ops phy_ops_10g_fiber_niu = { 2264 .serdes_init = serdes_init_niu_10g_fiber, 2265 .xcvr_init = xcvr_init_10g, 2266 .link_status = link_status_10g, 2267 }; 2268 2269 static const struct niu_phy_ops phy_ops_10g_fiber = { 2270 .serdes_init = serdes_init_10g, 2271 .xcvr_init = xcvr_init_10g, 2272 .link_status = link_status_10g, 2273 }; 2274 2275 static const struct niu_phy_ops phy_ops_10g_fiber_hotplug = { 2276 .serdes_init = serdes_init_10g, 2277 .xcvr_init = xcvr_init_10g_bcm8706, 2278 .link_status = link_status_10g_hotplug, 2279 }; 2280 2281 static const struct niu_phy_ops phy_ops_niu_10g_hotplug = { 2282 .serdes_init = serdes_init_niu_10g_fiber, 2283 .xcvr_init = xcvr_init_10g_bcm8706, 2284 .link_status = link_status_10g_hotplug, 2285 }; 2286 2287 static const struct niu_phy_ops phy_ops_10g_copper = { 2288 .serdes_init = serdes_init_10g, 2289 .link_status = link_status_10g, /* XXX */ 2290 }; 2291 2292 static const struct niu_phy_ops phy_ops_1g_fiber = { 2293 .serdes_init = serdes_init_1g, 2294 .xcvr_init = xcvr_init_1g, 2295 .link_status = link_status_1g, 2296 }; 2297 2298 static const struct niu_phy_ops phy_ops_1g_copper = { 2299 .xcvr_init = xcvr_init_1g, 2300 .link_status = link_status_1g, 2301 }; 2302 2303 struct niu_phy_template { 2304 const struct niu_phy_ops *ops; 2305 u32 phy_addr_base; 2306 }; 2307 2308 static const struct niu_phy_template phy_template_niu_10g_fiber = { 2309 .ops = &phy_ops_10g_fiber_niu, 2310 .phy_addr_base = 16, 2311 }; 2312 2313 static const struct niu_phy_template phy_template_niu_10g_serdes = { 2314 .ops = &phy_ops_10g_serdes_niu, 2315 .phy_addr_base = 0, 2316 }; 2317 2318 static const struct niu_phy_template phy_template_niu_1g_serdes = { 2319 .ops = &phy_ops_1g_serdes_niu, 2320 .phy_addr_base = 0, 2321 }; 2322 2323 static const struct niu_phy_template phy_template_10g_fiber = { 2324 .ops = &phy_ops_10g_fiber, 2325 .phy_addr_base = 8, 2326 }; 2327 2328 static const struct niu_phy_template phy_template_10g_fiber_hotplug = { 2329 .ops = &phy_ops_10g_fiber_hotplug, 2330 .phy_addr_base = 8, 2331 }; 2332 2333 static const struct niu_phy_template phy_template_niu_10g_hotplug = { 2334 .ops = &phy_ops_niu_10g_hotplug, 2335 .phy_addr_base = 8, 2336 }; 2337 2338 static const struct niu_phy_template phy_template_10g_copper = { 2339 .ops = &phy_ops_10g_copper, 2340 .phy_addr_base = 10, 2341 }; 2342 2343 static const struct niu_phy_template phy_template_1g_fiber = { 2344 .ops = &phy_ops_1g_fiber, 2345 .phy_addr_base = 0, 2346 }; 2347 2348 static const struct niu_phy_template phy_template_1g_copper = { 2349 .ops = &phy_ops_1g_copper, 2350 .phy_addr_base = 0, 2351 }; 2352 2353 static const struct niu_phy_template phy_template_1g_rgmii = { 2354 .ops = &phy_ops_1g_rgmii, 2355 .phy_addr_base = 0, 2356 }; 2357 2358 static const struct niu_phy_template phy_template_10g_serdes = { 2359 .ops = &phy_ops_10g_serdes, 2360 .phy_addr_base = 0, 2361 }; 2362 2363 static int niu_atca_port_num[4] = { 2364 0, 0, 11, 10 2365 }; 2366 2367 static int serdes_init_10g_serdes(struct niu *np) 2368 { 2369 struct niu_link_config *lp = &np->link_config; 2370 unsigned long ctrl_reg, test_cfg_reg, pll_cfg, i; 2371 u64 ctrl_val, test_cfg_val, sig, mask, val; 2372 2373 switch (np->port) { 2374 case 0: 2375 ctrl_reg = ENET_SERDES_0_CTRL_CFG; 2376 test_cfg_reg = ENET_SERDES_0_TEST_CFG; 2377 pll_cfg = ENET_SERDES_0_PLL_CFG; 2378 break; 2379 case 1: 2380 ctrl_reg = ENET_SERDES_1_CTRL_CFG; 2381 test_cfg_reg = ENET_SERDES_1_TEST_CFG; 2382 pll_cfg = ENET_SERDES_1_PLL_CFG; 2383 break; 2384 2385 default: 2386 return -EINVAL; 2387 } 2388 ctrl_val = (ENET_SERDES_CTRL_SDET_0 | 2389 ENET_SERDES_CTRL_SDET_1 | 2390 ENET_SERDES_CTRL_SDET_2 | 2391 ENET_SERDES_CTRL_SDET_3 | 2392 (0x5 << ENET_SERDES_CTRL_EMPH_0_SHIFT) | 2393 (0x5 << ENET_SERDES_CTRL_EMPH_1_SHIFT) | 2394 (0x5 << ENET_SERDES_CTRL_EMPH_2_SHIFT) | 2395 (0x5 << ENET_SERDES_CTRL_EMPH_3_SHIFT) | 2396 (0x1 << ENET_SERDES_CTRL_LADJ_0_SHIFT) | 2397 (0x1 << ENET_SERDES_CTRL_LADJ_1_SHIFT) | 2398 (0x1 << ENET_SERDES_CTRL_LADJ_2_SHIFT) | 2399 (0x1 << ENET_SERDES_CTRL_LADJ_3_SHIFT)); 2400 test_cfg_val = 0; 2401 2402 if (lp->loopback_mode == LOOPBACK_PHY) { 2403 test_cfg_val |= ((ENET_TEST_MD_PAD_LOOPBACK << 2404 ENET_SERDES_TEST_MD_0_SHIFT) | 2405 (ENET_TEST_MD_PAD_LOOPBACK << 2406 ENET_SERDES_TEST_MD_1_SHIFT) | 2407 (ENET_TEST_MD_PAD_LOOPBACK << 2408 ENET_SERDES_TEST_MD_2_SHIFT) | 2409 (ENET_TEST_MD_PAD_LOOPBACK << 2410 ENET_SERDES_TEST_MD_3_SHIFT)); 2411 } 2412 2413 esr_reset(np); 2414 nw64(pll_cfg, ENET_SERDES_PLL_FBDIV2); 2415 nw64(ctrl_reg, ctrl_val); 2416 nw64(test_cfg_reg, test_cfg_val); 2417 2418 /* Initialize all 4 lanes of the SERDES. */ 2419 for (i = 0; i < 4; i++) { 2420 u32 rxtx_ctrl, glue0; 2421 int err; 2422 2423 err = esr_read_rxtx_ctrl(np, i, &rxtx_ctrl); 2424 if (err) 2425 return err; 2426 err = esr_read_glue0(np, i, &glue0); 2427 if (err) 2428 return err; 2429 2430 rxtx_ctrl &= ~(ESR_RXTX_CTRL_VMUXLO); 2431 rxtx_ctrl |= (ESR_RXTX_CTRL_ENSTRETCH | 2432 (2 << ESR_RXTX_CTRL_VMUXLO_SHIFT)); 2433 2434 glue0 &= ~(ESR_GLUE_CTRL0_SRATE | 2435 ESR_GLUE_CTRL0_THCNT | 2436 ESR_GLUE_CTRL0_BLTIME); 2437 glue0 |= (ESR_GLUE_CTRL0_RXLOSENAB | 2438 (0xf << ESR_GLUE_CTRL0_SRATE_SHIFT) | 2439 (0xff << ESR_GLUE_CTRL0_THCNT_SHIFT) | 2440 (BLTIME_300_CYCLES << 2441 ESR_GLUE_CTRL0_BLTIME_SHIFT)); 2442 2443 err = esr_write_rxtx_ctrl(np, i, rxtx_ctrl); 2444 if (err) 2445 return err; 2446 err = esr_write_glue0(np, i, glue0); 2447 if (err) 2448 return err; 2449 } 2450 2451 2452 sig = nr64(ESR_INT_SIGNALS); 2453 switch (np->port) { 2454 case 0: 2455 mask = ESR_INT_SIGNALS_P0_BITS; 2456 val = (ESR_INT_SRDY0_P0 | 2457 ESR_INT_DET0_P0 | 2458 ESR_INT_XSRDY_P0 | 2459 ESR_INT_XDP_P0_CH3 | 2460 ESR_INT_XDP_P0_CH2 | 2461 ESR_INT_XDP_P0_CH1 | 2462 ESR_INT_XDP_P0_CH0); 2463 break; 2464 2465 case 1: 2466 mask = ESR_INT_SIGNALS_P1_BITS; 2467 val = (ESR_INT_SRDY0_P1 | 2468 ESR_INT_DET0_P1 | 2469 ESR_INT_XSRDY_P1 | 2470 ESR_INT_XDP_P1_CH3 | 2471 ESR_INT_XDP_P1_CH2 | 2472 ESR_INT_XDP_P1_CH1 | 2473 ESR_INT_XDP_P1_CH0); 2474 break; 2475 2476 default: 2477 return -EINVAL; 2478 } 2479 2480 if ((sig & mask) != val) { 2481 int err; 2482 err = serdes_init_1g_serdes(np); 2483 if (!err) { 2484 np->flags &= ~NIU_FLAGS_10G; 2485 np->mac_xcvr = MAC_XCVR_PCS; 2486 } else { 2487 netdev_err(np->dev, "Port %u 10G/1G SERDES Link Failed\n", 2488 np->port); 2489 return -ENODEV; 2490 } 2491 } 2492 2493 return 0; 2494 } 2495 2496 static int niu_determine_phy_disposition(struct niu *np) 2497 { 2498 struct niu_parent *parent = np->parent; 2499 u8 plat_type = parent->plat_type; 2500 const struct niu_phy_template *tp; 2501 u32 phy_addr_off = 0; 2502 2503 if (plat_type == PLAT_TYPE_NIU) { 2504 switch (np->flags & 2505 (NIU_FLAGS_10G | 2506 NIU_FLAGS_FIBER | 2507 NIU_FLAGS_XCVR_SERDES)) { 2508 case NIU_FLAGS_10G | NIU_FLAGS_XCVR_SERDES: 2509 /* 10G Serdes */ 2510 tp = &phy_template_niu_10g_serdes; 2511 break; 2512 case NIU_FLAGS_XCVR_SERDES: 2513 /* 1G Serdes */ 2514 tp = &phy_template_niu_1g_serdes; 2515 break; 2516 case NIU_FLAGS_10G | NIU_FLAGS_FIBER: 2517 /* 10G Fiber */ 2518 default: 2519 if (np->flags & NIU_FLAGS_HOTPLUG_PHY) { 2520 tp = &phy_template_niu_10g_hotplug; 2521 if (np->port == 0) 2522 phy_addr_off = 8; 2523 if (np->port == 1) 2524 phy_addr_off = 12; 2525 } else { 2526 tp = &phy_template_niu_10g_fiber; 2527 phy_addr_off += np->port; 2528 } 2529 break; 2530 } 2531 } else { 2532 switch (np->flags & 2533 (NIU_FLAGS_10G | 2534 NIU_FLAGS_FIBER | 2535 NIU_FLAGS_XCVR_SERDES)) { 2536 case 0: 2537 /* 1G copper */ 2538 tp = &phy_template_1g_copper; 2539 if (plat_type == PLAT_TYPE_VF_P0) 2540 phy_addr_off = 10; 2541 else if (plat_type == PLAT_TYPE_VF_P1) 2542 phy_addr_off = 26; 2543 2544 phy_addr_off += (np->port ^ 0x3); 2545 break; 2546 2547 case NIU_FLAGS_10G: 2548 /* 10G copper */ 2549 tp = &phy_template_10g_copper; 2550 break; 2551 2552 case NIU_FLAGS_FIBER: 2553 /* 1G fiber */ 2554 tp = &phy_template_1g_fiber; 2555 break; 2556 2557 case NIU_FLAGS_10G | NIU_FLAGS_FIBER: 2558 /* 10G fiber */ 2559 tp = &phy_template_10g_fiber; 2560 if (plat_type == PLAT_TYPE_VF_P0 || 2561 plat_type == PLAT_TYPE_VF_P1) 2562 phy_addr_off = 8; 2563 phy_addr_off += np->port; 2564 if (np->flags & NIU_FLAGS_HOTPLUG_PHY) { 2565 tp = &phy_template_10g_fiber_hotplug; 2566 if (np->port == 0) 2567 phy_addr_off = 8; 2568 if (np->port == 1) 2569 phy_addr_off = 12; 2570 } 2571 break; 2572 2573 case NIU_FLAGS_10G | NIU_FLAGS_XCVR_SERDES: 2574 case NIU_FLAGS_XCVR_SERDES | NIU_FLAGS_FIBER: 2575 case NIU_FLAGS_XCVR_SERDES: 2576 switch(np->port) { 2577 case 0: 2578 case 1: 2579 tp = &phy_template_10g_serdes; 2580 break; 2581 case 2: 2582 case 3: 2583 tp = &phy_template_1g_rgmii; 2584 break; 2585 default: 2586 return -EINVAL; 2587 } 2588 phy_addr_off = niu_atca_port_num[np->port]; 2589 break; 2590 2591 default: 2592 return -EINVAL; 2593 } 2594 } 2595 2596 np->phy_ops = tp->ops; 2597 np->phy_addr = tp->phy_addr_base + phy_addr_off; 2598 2599 return 0; 2600 } 2601 2602 static int niu_init_link(struct niu *np) 2603 { 2604 struct niu_parent *parent = np->parent; 2605 int err, ignore; 2606 2607 if (parent->plat_type == PLAT_TYPE_NIU) { 2608 err = niu_xcvr_init(np); 2609 if (err) 2610 return err; 2611 msleep(200); 2612 } 2613 err = niu_serdes_init(np); 2614 if (err && !(np->flags & NIU_FLAGS_HOTPLUG_PHY)) 2615 return err; 2616 msleep(200); 2617 err = niu_xcvr_init(np); 2618 if (!err || (np->flags & NIU_FLAGS_HOTPLUG_PHY)) 2619 niu_link_status(np, &ignore); 2620 return 0; 2621 } 2622 2623 static void niu_set_primary_mac(struct niu *np, unsigned char *addr) 2624 { 2625 u16 reg0 = addr[4] << 8 | addr[5]; 2626 u16 reg1 = addr[2] << 8 | addr[3]; 2627 u16 reg2 = addr[0] << 8 | addr[1]; 2628 2629 if (np->flags & NIU_FLAGS_XMAC) { 2630 nw64_mac(XMAC_ADDR0, reg0); 2631 nw64_mac(XMAC_ADDR1, reg1); 2632 nw64_mac(XMAC_ADDR2, reg2); 2633 } else { 2634 nw64_mac(BMAC_ADDR0, reg0); 2635 nw64_mac(BMAC_ADDR1, reg1); 2636 nw64_mac(BMAC_ADDR2, reg2); 2637 } 2638 } 2639 2640 static int niu_num_alt_addr(struct niu *np) 2641 { 2642 if (np->flags & NIU_FLAGS_XMAC) 2643 return XMAC_NUM_ALT_ADDR; 2644 else 2645 return BMAC_NUM_ALT_ADDR; 2646 } 2647 2648 static int niu_set_alt_mac(struct niu *np, int index, unsigned char *addr) 2649 { 2650 u16 reg0 = addr[4] << 8 | addr[5]; 2651 u16 reg1 = addr[2] << 8 | addr[3]; 2652 u16 reg2 = addr[0] << 8 | addr[1]; 2653 2654 if (index >= niu_num_alt_addr(np)) 2655 return -EINVAL; 2656 2657 if (np->flags & NIU_FLAGS_XMAC) { 2658 nw64_mac(XMAC_ALT_ADDR0(index), reg0); 2659 nw64_mac(XMAC_ALT_ADDR1(index), reg1); 2660 nw64_mac(XMAC_ALT_ADDR2(index), reg2); 2661 } else { 2662 nw64_mac(BMAC_ALT_ADDR0(index), reg0); 2663 nw64_mac(BMAC_ALT_ADDR1(index), reg1); 2664 nw64_mac(BMAC_ALT_ADDR2(index), reg2); 2665 } 2666 2667 return 0; 2668 } 2669 2670 static int niu_enable_alt_mac(struct niu *np, int index, int on) 2671 { 2672 unsigned long reg; 2673 u64 val, mask; 2674 2675 if (index >= niu_num_alt_addr(np)) 2676 return -EINVAL; 2677 2678 if (np->flags & NIU_FLAGS_XMAC) { 2679 reg = XMAC_ADDR_CMPEN; 2680 mask = 1 << index; 2681 } else { 2682 reg = BMAC_ADDR_CMPEN; 2683 mask = 1 << (index + 1); 2684 } 2685 2686 val = nr64_mac(reg); 2687 if (on) 2688 val |= mask; 2689 else 2690 val &= ~mask; 2691 nw64_mac(reg, val); 2692 2693 return 0; 2694 } 2695 2696 static void __set_rdc_table_num_hw(struct niu *np, unsigned long reg, 2697 int num, int mac_pref) 2698 { 2699 u64 val = nr64_mac(reg); 2700 val &= ~(HOST_INFO_MACRDCTBLN | HOST_INFO_MPR); 2701 val |= num; 2702 if (mac_pref) 2703 val |= HOST_INFO_MPR; 2704 nw64_mac(reg, val); 2705 } 2706 2707 static int __set_rdc_table_num(struct niu *np, 2708 int xmac_index, int bmac_index, 2709 int rdc_table_num, int mac_pref) 2710 { 2711 unsigned long reg; 2712 2713 if (rdc_table_num & ~HOST_INFO_MACRDCTBLN) 2714 return -EINVAL; 2715 if (np->flags & NIU_FLAGS_XMAC) 2716 reg = XMAC_HOST_INFO(xmac_index); 2717 else 2718 reg = BMAC_HOST_INFO(bmac_index); 2719 __set_rdc_table_num_hw(np, reg, rdc_table_num, mac_pref); 2720 return 0; 2721 } 2722 2723 static int niu_set_primary_mac_rdc_table(struct niu *np, int table_num, 2724 int mac_pref) 2725 { 2726 return __set_rdc_table_num(np, 17, 0, table_num, mac_pref); 2727 } 2728 2729 static int niu_set_multicast_mac_rdc_table(struct niu *np, int table_num, 2730 int mac_pref) 2731 { 2732 return __set_rdc_table_num(np, 16, 8, table_num, mac_pref); 2733 } 2734 2735 static int niu_set_alt_mac_rdc_table(struct niu *np, int idx, 2736 int table_num, int mac_pref) 2737 { 2738 if (idx >= niu_num_alt_addr(np)) 2739 return -EINVAL; 2740 return __set_rdc_table_num(np, idx, idx + 1, table_num, mac_pref); 2741 } 2742 2743 static u64 vlan_entry_set_parity(u64 reg_val) 2744 { 2745 u64 port01_mask; 2746 u64 port23_mask; 2747 2748 port01_mask = 0x00ff; 2749 port23_mask = 0xff00; 2750 2751 if (hweight64(reg_val & port01_mask) & 1) 2752 reg_val |= ENET_VLAN_TBL_PARITY0; 2753 else 2754 reg_val &= ~ENET_VLAN_TBL_PARITY0; 2755 2756 if (hweight64(reg_val & port23_mask) & 1) 2757 reg_val |= ENET_VLAN_TBL_PARITY1; 2758 else 2759 reg_val &= ~ENET_VLAN_TBL_PARITY1; 2760 2761 return reg_val; 2762 } 2763 2764 static void vlan_tbl_write(struct niu *np, unsigned long index, 2765 int port, int vpr, int rdc_table) 2766 { 2767 u64 reg_val = nr64(ENET_VLAN_TBL(index)); 2768 2769 reg_val &= ~((ENET_VLAN_TBL_VPR | 2770 ENET_VLAN_TBL_VLANRDCTBLN) << 2771 ENET_VLAN_TBL_SHIFT(port)); 2772 if (vpr) 2773 reg_val |= (ENET_VLAN_TBL_VPR << 2774 ENET_VLAN_TBL_SHIFT(port)); 2775 reg_val |= (rdc_table << ENET_VLAN_TBL_SHIFT(port)); 2776 2777 reg_val = vlan_entry_set_parity(reg_val); 2778 2779 nw64(ENET_VLAN_TBL(index), reg_val); 2780 } 2781 2782 static void vlan_tbl_clear(struct niu *np) 2783 { 2784 int i; 2785 2786 for (i = 0; i < ENET_VLAN_TBL_NUM_ENTRIES; i++) 2787 nw64(ENET_VLAN_TBL(i), 0); 2788 } 2789 2790 static int tcam_wait_bit(struct niu *np, u64 bit) 2791 { 2792 int limit = 1000; 2793 2794 while (--limit > 0) { 2795 if (nr64(TCAM_CTL) & bit) 2796 break; 2797 udelay(1); 2798 } 2799 if (limit <= 0) 2800 return -ENODEV; 2801 2802 return 0; 2803 } 2804 2805 static int tcam_flush(struct niu *np, int index) 2806 { 2807 nw64(TCAM_KEY_0, 0x00); 2808 nw64(TCAM_KEY_MASK_0, 0xff); 2809 nw64(TCAM_CTL, (TCAM_CTL_RWC_TCAM_WRITE | index)); 2810 2811 return tcam_wait_bit(np, TCAM_CTL_STAT); 2812 } 2813 2814 #if 0 2815 static int tcam_read(struct niu *np, int index, 2816 u64 *key, u64 *mask) 2817 { 2818 int err; 2819 2820 nw64(TCAM_CTL, (TCAM_CTL_RWC_TCAM_READ | index)); 2821 err = tcam_wait_bit(np, TCAM_CTL_STAT); 2822 if (!err) { 2823 key[0] = nr64(TCAM_KEY_0); 2824 key[1] = nr64(TCAM_KEY_1); 2825 key[2] = nr64(TCAM_KEY_2); 2826 key[3] = nr64(TCAM_KEY_3); 2827 mask[0] = nr64(TCAM_KEY_MASK_0); 2828 mask[1] = nr64(TCAM_KEY_MASK_1); 2829 mask[2] = nr64(TCAM_KEY_MASK_2); 2830 mask[3] = nr64(TCAM_KEY_MASK_3); 2831 } 2832 return err; 2833 } 2834 #endif 2835 2836 static int tcam_write(struct niu *np, int index, 2837 u64 *key, u64 *mask) 2838 { 2839 nw64(TCAM_KEY_0, key[0]); 2840 nw64(TCAM_KEY_1, key[1]); 2841 nw64(TCAM_KEY_2, key[2]); 2842 nw64(TCAM_KEY_3, key[3]); 2843 nw64(TCAM_KEY_MASK_0, mask[0]); 2844 nw64(TCAM_KEY_MASK_1, mask[1]); 2845 nw64(TCAM_KEY_MASK_2, mask[2]); 2846 nw64(TCAM_KEY_MASK_3, mask[3]); 2847 nw64(TCAM_CTL, (TCAM_CTL_RWC_TCAM_WRITE | index)); 2848 2849 return tcam_wait_bit(np, TCAM_CTL_STAT); 2850 } 2851 2852 #if 0 2853 static int tcam_assoc_read(struct niu *np, int index, u64 *data) 2854 { 2855 int err; 2856 2857 nw64(TCAM_CTL, (TCAM_CTL_RWC_RAM_READ | index)); 2858 err = tcam_wait_bit(np, TCAM_CTL_STAT); 2859 if (!err) 2860 *data = nr64(TCAM_KEY_1); 2861 2862 return err; 2863 } 2864 #endif 2865 2866 static int tcam_assoc_write(struct niu *np, int index, u64 assoc_data) 2867 { 2868 nw64(TCAM_KEY_1, assoc_data); 2869 nw64(TCAM_CTL, (TCAM_CTL_RWC_RAM_WRITE | index)); 2870 2871 return tcam_wait_bit(np, TCAM_CTL_STAT); 2872 } 2873 2874 static void tcam_enable(struct niu *np, int on) 2875 { 2876 u64 val = nr64(FFLP_CFG_1); 2877 2878 if (on) 2879 val &= ~FFLP_CFG_1_TCAM_DIS; 2880 else 2881 val |= FFLP_CFG_1_TCAM_DIS; 2882 nw64(FFLP_CFG_1, val); 2883 } 2884 2885 static void tcam_set_lat_and_ratio(struct niu *np, u64 latency, u64 ratio) 2886 { 2887 u64 val = nr64(FFLP_CFG_1); 2888 2889 val &= ~(FFLP_CFG_1_FFLPINITDONE | 2890 FFLP_CFG_1_CAMLAT | 2891 FFLP_CFG_1_CAMRATIO); 2892 val |= (latency << FFLP_CFG_1_CAMLAT_SHIFT); 2893 val |= (ratio << FFLP_CFG_1_CAMRATIO_SHIFT); 2894 nw64(FFLP_CFG_1, val); 2895 2896 val = nr64(FFLP_CFG_1); 2897 val |= FFLP_CFG_1_FFLPINITDONE; 2898 nw64(FFLP_CFG_1, val); 2899 } 2900 2901 static int tcam_user_eth_class_enable(struct niu *np, unsigned long class, 2902 int on) 2903 { 2904 unsigned long reg; 2905 u64 val; 2906 2907 if (class < CLASS_CODE_ETHERTYPE1 || 2908 class > CLASS_CODE_ETHERTYPE2) 2909 return -EINVAL; 2910 2911 reg = L2_CLS(class - CLASS_CODE_ETHERTYPE1); 2912 val = nr64(reg); 2913 if (on) 2914 val |= L2_CLS_VLD; 2915 else 2916 val &= ~L2_CLS_VLD; 2917 nw64(reg, val); 2918 2919 return 0; 2920 } 2921 2922 #if 0 2923 static int tcam_user_eth_class_set(struct niu *np, unsigned long class, 2924 u64 ether_type) 2925 { 2926 unsigned long reg; 2927 u64 val; 2928 2929 if (class < CLASS_CODE_ETHERTYPE1 || 2930 class > CLASS_CODE_ETHERTYPE2 || 2931 (ether_type & ~(u64)0xffff) != 0) 2932 return -EINVAL; 2933 2934 reg = L2_CLS(class - CLASS_CODE_ETHERTYPE1); 2935 val = nr64(reg); 2936 val &= ~L2_CLS_ETYPE; 2937 val |= (ether_type << L2_CLS_ETYPE_SHIFT); 2938 nw64(reg, val); 2939 2940 return 0; 2941 } 2942 #endif 2943 2944 static int tcam_user_ip_class_enable(struct niu *np, unsigned long class, 2945 int on) 2946 { 2947 unsigned long reg; 2948 u64 val; 2949 2950 if (class < CLASS_CODE_USER_PROG1 || 2951 class > CLASS_CODE_USER_PROG4) 2952 return -EINVAL; 2953 2954 reg = L3_CLS(class - CLASS_CODE_USER_PROG1); 2955 val = nr64(reg); 2956 if (on) 2957 val |= L3_CLS_VALID; 2958 else 2959 val &= ~L3_CLS_VALID; 2960 nw64(reg, val); 2961 2962 return 0; 2963 } 2964 2965 static int tcam_user_ip_class_set(struct niu *np, unsigned long class, 2966 int ipv6, u64 protocol_id, 2967 u64 tos_mask, u64 tos_val) 2968 { 2969 unsigned long reg; 2970 u64 val; 2971 2972 if (class < CLASS_CODE_USER_PROG1 || 2973 class > CLASS_CODE_USER_PROG4 || 2974 (protocol_id & ~(u64)0xff) != 0 || 2975 (tos_mask & ~(u64)0xff) != 0 || 2976 (tos_val & ~(u64)0xff) != 0) 2977 return -EINVAL; 2978 2979 reg = L3_CLS(class - CLASS_CODE_USER_PROG1); 2980 val = nr64(reg); 2981 val &= ~(L3_CLS_IPVER | L3_CLS_PID | 2982 L3_CLS_TOSMASK | L3_CLS_TOS); 2983 if (ipv6) 2984 val |= L3_CLS_IPVER; 2985 val |= (protocol_id << L3_CLS_PID_SHIFT); 2986 val |= (tos_mask << L3_CLS_TOSMASK_SHIFT); 2987 val |= (tos_val << L3_CLS_TOS_SHIFT); 2988 nw64(reg, val); 2989 2990 return 0; 2991 } 2992 2993 static int tcam_early_init(struct niu *np) 2994 { 2995 unsigned long i; 2996 int err; 2997 2998 tcam_enable(np, 0); 2999 tcam_set_lat_and_ratio(np, 3000 DEFAULT_TCAM_LATENCY, 3001 DEFAULT_TCAM_ACCESS_RATIO); 3002 for (i = CLASS_CODE_ETHERTYPE1; i <= CLASS_CODE_ETHERTYPE2; i++) { 3003 err = tcam_user_eth_class_enable(np, i, 0); 3004 if (err) 3005 return err; 3006 } 3007 for (i = CLASS_CODE_USER_PROG1; i <= CLASS_CODE_USER_PROG4; i++) { 3008 err = tcam_user_ip_class_enable(np, i, 0); 3009 if (err) 3010 return err; 3011 } 3012 3013 return 0; 3014 } 3015 3016 static int tcam_flush_all(struct niu *np) 3017 { 3018 unsigned long i; 3019 3020 for (i = 0; i < np->parent->tcam_num_entries; i++) { 3021 int err = tcam_flush(np, i); 3022 if (err) 3023 return err; 3024 } 3025 return 0; 3026 } 3027 3028 static u64 hash_addr_regval(unsigned long index, unsigned long num_entries) 3029 { 3030 return (u64)index | (num_entries == 1 ? HASH_TBL_ADDR_AUTOINC : 0); 3031 } 3032 3033 #if 0 3034 static int hash_read(struct niu *np, unsigned long partition, 3035 unsigned long index, unsigned long num_entries, 3036 u64 *data) 3037 { 3038 u64 val = hash_addr_regval(index, num_entries); 3039 unsigned long i; 3040 3041 if (partition >= FCRAM_NUM_PARTITIONS || 3042 index + num_entries > FCRAM_SIZE) 3043 return -EINVAL; 3044 3045 nw64(HASH_TBL_ADDR(partition), val); 3046 for (i = 0; i < num_entries; i++) 3047 data[i] = nr64(HASH_TBL_DATA(partition)); 3048 3049 return 0; 3050 } 3051 #endif 3052 3053 static int hash_write(struct niu *np, unsigned long partition, 3054 unsigned long index, unsigned long num_entries, 3055 u64 *data) 3056 { 3057 u64 val = hash_addr_regval(index, num_entries); 3058 unsigned long i; 3059 3060 if (partition >= FCRAM_NUM_PARTITIONS || 3061 index + (num_entries * 8) > FCRAM_SIZE) 3062 return -EINVAL; 3063 3064 nw64(HASH_TBL_ADDR(partition), val); 3065 for (i = 0; i < num_entries; i++) 3066 nw64(HASH_TBL_DATA(partition), data[i]); 3067 3068 return 0; 3069 } 3070 3071 static void fflp_reset(struct niu *np) 3072 { 3073 u64 val; 3074 3075 nw64(FFLP_CFG_1, FFLP_CFG_1_PIO_FIO_RST); 3076 udelay(10); 3077 nw64(FFLP_CFG_1, 0); 3078 3079 val = FFLP_CFG_1_FCRAMOUTDR_NORMAL | FFLP_CFG_1_FFLPINITDONE; 3080 nw64(FFLP_CFG_1, val); 3081 } 3082 3083 static void fflp_set_timings(struct niu *np) 3084 { 3085 u64 val = nr64(FFLP_CFG_1); 3086 3087 val &= ~FFLP_CFG_1_FFLPINITDONE; 3088 val |= (DEFAULT_FCRAMRATIO << FFLP_CFG_1_FCRAMRATIO_SHIFT); 3089 nw64(FFLP_CFG_1, val); 3090 3091 val = nr64(FFLP_CFG_1); 3092 val |= FFLP_CFG_1_FFLPINITDONE; 3093 nw64(FFLP_CFG_1, val); 3094 3095 val = nr64(FCRAM_REF_TMR); 3096 val &= ~(FCRAM_REF_TMR_MAX | FCRAM_REF_TMR_MIN); 3097 val |= (DEFAULT_FCRAM_REFRESH_MAX << FCRAM_REF_TMR_MAX_SHIFT); 3098 val |= (DEFAULT_FCRAM_REFRESH_MIN << FCRAM_REF_TMR_MIN_SHIFT); 3099 nw64(FCRAM_REF_TMR, val); 3100 } 3101 3102 static int fflp_set_partition(struct niu *np, u64 partition, 3103 u64 mask, u64 base, int enable) 3104 { 3105 unsigned long reg; 3106 u64 val; 3107 3108 if (partition >= FCRAM_NUM_PARTITIONS || 3109 (mask & ~(u64)0x1f) != 0 || 3110 (base & ~(u64)0x1f) != 0) 3111 return -EINVAL; 3112 3113 reg = FLW_PRT_SEL(partition); 3114 3115 val = nr64(reg); 3116 val &= ~(FLW_PRT_SEL_EXT | FLW_PRT_SEL_MASK | FLW_PRT_SEL_BASE); 3117 val |= (mask << FLW_PRT_SEL_MASK_SHIFT); 3118 val |= (base << FLW_PRT_SEL_BASE_SHIFT); 3119 if (enable) 3120 val |= FLW_PRT_SEL_EXT; 3121 nw64(reg, val); 3122 3123 return 0; 3124 } 3125 3126 static int fflp_disable_all_partitions(struct niu *np) 3127 { 3128 unsigned long i; 3129 3130 for (i = 0; i < FCRAM_NUM_PARTITIONS; i++) { 3131 int err = fflp_set_partition(np, 0, 0, 0, 0); 3132 if (err) 3133 return err; 3134 } 3135 return 0; 3136 } 3137 3138 static void fflp_llcsnap_enable(struct niu *np, int on) 3139 { 3140 u64 val = nr64(FFLP_CFG_1); 3141 3142 if (on) 3143 val |= FFLP_CFG_1_LLCSNAP; 3144 else 3145 val &= ~FFLP_CFG_1_LLCSNAP; 3146 nw64(FFLP_CFG_1, val); 3147 } 3148 3149 static void fflp_errors_enable(struct niu *np, int on) 3150 { 3151 u64 val = nr64(FFLP_CFG_1); 3152 3153 if (on) 3154 val &= ~FFLP_CFG_1_ERRORDIS; 3155 else 3156 val |= FFLP_CFG_1_ERRORDIS; 3157 nw64(FFLP_CFG_1, val); 3158 } 3159 3160 static int fflp_hash_clear(struct niu *np) 3161 { 3162 struct fcram_hash_ipv4 ent; 3163 unsigned long i; 3164 3165 /* IPV4 hash entry with valid bit clear, rest is don't care. */ 3166 memset(&ent, 0, sizeof(ent)); 3167 ent.header = HASH_HEADER_EXT; 3168 3169 for (i = 0; i < FCRAM_SIZE; i += sizeof(ent)) { 3170 int err = hash_write(np, 0, i, 1, (u64 *) &ent); 3171 if (err) 3172 return err; 3173 } 3174 return 0; 3175 } 3176 3177 static int fflp_early_init(struct niu *np) 3178 { 3179 struct niu_parent *parent; 3180 unsigned long flags; 3181 int err; 3182 3183 niu_lock_parent(np, flags); 3184 3185 parent = np->parent; 3186 err = 0; 3187 if (!(parent->flags & PARENT_FLGS_CLS_HWINIT)) { 3188 if (np->parent->plat_type != PLAT_TYPE_NIU) { 3189 fflp_reset(np); 3190 fflp_set_timings(np); 3191 err = fflp_disable_all_partitions(np); 3192 if (err) { 3193 netif_printk(np, probe, KERN_DEBUG, np->dev, 3194 "fflp_disable_all_partitions failed, err=%d\n", 3195 err); 3196 goto out; 3197 } 3198 } 3199 3200 err = tcam_early_init(np); 3201 if (err) { 3202 netif_printk(np, probe, KERN_DEBUG, np->dev, 3203 "tcam_early_init failed, err=%d\n", err); 3204 goto out; 3205 } 3206 fflp_llcsnap_enable(np, 1); 3207 fflp_errors_enable(np, 0); 3208 nw64(H1POLY, 0); 3209 nw64(H2POLY, 0); 3210 3211 err = tcam_flush_all(np); 3212 if (err) { 3213 netif_printk(np, probe, KERN_DEBUG, np->dev, 3214 "tcam_flush_all failed, err=%d\n", err); 3215 goto out; 3216 } 3217 if (np->parent->plat_type != PLAT_TYPE_NIU) { 3218 err = fflp_hash_clear(np); 3219 if (err) { 3220 netif_printk(np, probe, KERN_DEBUG, np->dev, 3221 "fflp_hash_clear failed, err=%d\n", 3222 err); 3223 goto out; 3224 } 3225 } 3226 3227 vlan_tbl_clear(np); 3228 3229 parent->flags |= PARENT_FLGS_CLS_HWINIT; 3230 } 3231 out: 3232 niu_unlock_parent(np, flags); 3233 return err; 3234 } 3235 3236 static int niu_set_flow_key(struct niu *np, unsigned long class_code, u64 key) 3237 { 3238 if (class_code < CLASS_CODE_USER_PROG1 || 3239 class_code > CLASS_CODE_SCTP_IPV6) 3240 return -EINVAL; 3241 3242 nw64(FLOW_KEY(class_code - CLASS_CODE_USER_PROG1), key); 3243 return 0; 3244 } 3245 3246 static int niu_set_tcam_key(struct niu *np, unsigned long class_code, u64 key) 3247 { 3248 if (class_code < CLASS_CODE_USER_PROG1 || 3249 class_code > CLASS_CODE_SCTP_IPV6) 3250 return -EINVAL; 3251 3252 nw64(TCAM_KEY(class_code - CLASS_CODE_USER_PROG1), key); 3253 return 0; 3254 } 3255 3256 /* Entries for the ports are interleaved in the TCAM */ 3257 static u16 tcam_get_index(struct niu *np, u16 idx) 3258 { 3259 /* One entry reserved for IP fragment rule */ 3260 if (idx >= (np->clas.tcam_sz - 1)) 3261 idx = 0; 3262 return np->clas.tcam_top + ((idx+1) * np->parent->num_ports); 3263 } 3264 3265 static u16 tcam_get_size(struct niu *np) 3266 { 3267 /* One entry reserved for IP fragment rule */ 3268 return np->clas.tcam_sz - 1; 3269 } 3270 3271 static u16 tcam_get_valid_entry_cnt(struct niu *np) 3272 { 3273 /* One entry reserved for IP fragment rule */ 3274 return np->clas.tcam_valid_entries - 1; 3275 } 3276 3277 static void niu_rx_skb_append(struct sk_buff *skb, struct page *page, 3278 u32 offset, u32 size, u32 truesize) 3279 { 3280 skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags, page, offset, size); 3281 3282 skb->len += size; 3283 skb->data_len += size; 3284 skb->truesize += truesize; 3285 } 3286 3287 static unsigned int niu_hash_rxaddr(struct rx_ring_info *rp, u64 a) 3288 { 3289 a >>= PAGE_SHIFT; 3290 a ^= (a >> ilog2(MAX_RBR_RING_SIZE)); 3291 3292 return a & (MAX_RBR_RING_SIZE - 1); 3293 } 3294 3295 static struct page *niu_find_rxpage(struct rx_ring_info *rp, u64 addr, 3296 struct page ***link) 3297 { 3298 unsigned int h = niu_hash_rxaddr(rp, addr); 3299 struct page *p, **pp; 3300 3301 addr &= PAGE_MASK; 3302 pp = &rp->rxhash[h]; 3303 for (; (p = *pp) != NULL; pp = (struct page **) &p->mapping) { 3304 if (p->index == addr) { 3305 *link = pp; 3306 goto found; 3307 } 3308 } 3309 BUG(); 3310 3311 found: 3312 return p; 3313 } 3314 3315 static void niu_hash_page(struct rx_ring_info *rp, struct page *page, u64 base) 3316 { 3317 unsigned int h = niu_hash_rxaddr(rp, base); 3318 3319 page->index = base; 3320 page->mapping = (struct address_space *) rp->rxhash[h]; 3321 rp->rxhash[h] = page; 3322 } 3323 3324 static int niu_rbr_add_page(struct niu *np, struct rx_ring_info *rp, 3325 gfp_t mask, int start_index) 3326 { 3327 struct page *page; 3328 u64 addr; 3329 int i; 3330 3331 page = alloc_page(mask); 3332 if (!page) 3333 return -ENOMEM; 3334 3335 addr = np->ops->map_page(np->device, page, 0, 3336 PAGE_SIZE, DMA_FROM_DEVICE); 3337 if (!addr) { 3338 __free_page(page); 3339 return -ENOMEM; 3340 } 3341 3342 niu_hash_page(rp, page, addr); 3343 if (rp->rbr_blocks_per_page > 1) 3344 atomic_add(rp->rbr_blocks_per_page - 1, 3345 &compound_head(page)->_count); 3346 3347 for (i = 0; i < rp->rbr_blocks_per_page; i++) { 3348 __le32 *rbr = &rp->rbr[start_index + i]; 3349 3350 *rbr = cpu_to_le32(addr >> RBR_DESCR_ADDR_SHIFT); 3351 addr += rp->rbr_block_size; 3352 } 3353 3354 return 0; 3355 } 3356 3357 static void niu_rbr_refill(struct niu *np, struct rx_ring_info *rp, gfp_t mask) 3358 { 3359 int index = rp->rbr_index; 3360 3361 rp->rbr_pending++; 3362 if ((rp->rbr_pending % rp->rbr_blocks_per_page) == 0) { 3363 int err = niu_rbr_add_page(np, rp, mask, index); 3364 3365 if (unlikely(err)) { 3366 rp->rbr_pending--; 3367 return; 3368 } 3369 3370 rp->rbr_index += rp->rbr_blocks_per_page; 3371 BUG_ON(rp->rbr_index > rp->rbr_table_size); 3372 if (rp->rbr_index == rp->rbr_table_size) 3373 rp->rbr_index = 0; 3374 3375 if (rp->rbr_pending >= rp->rbr_kick_thresh) { 3376 nw64(RBR_KICK(rp->rx_channel), rp->rbr_pending); 3377 rp->rbr_pending = 0; 3378 } 3379 } 3380 } 3381 3382 static int niu_rx_pkt_ignore(struct niu *np, struct rx_ring_info *rp) 3383 { 3384 unsigned int index = rp->rcr_index; 3385 int num_rcr = 0; 3386 3387 rp->rx_dropped++; 3388 while (1) { 3389 struct page *page, **link; 3390 u64 addr, val; 3391 u32 rcr_size; 3392 3393 num_rcr++; 3394 3395 val = le64_to_cpup(&rp->rcr[index]); 3396 addr = (val & RCR_ENTRY_PKT_BUF_ADDR) << 3397 RCR_ENTRY_PKT_BUF_ADDR_SHIFT; 3398 page = niu_find_rxpage(rp, addr, &link); 3399 3400 rcr_size = rp->rbr_sizes[(val & RCR_ENTRY_PKTBUFSZ) >> 3401 RCR_ENTRY_PKTBUFSZ_SHIFT]; 3402 if ((page->index + PAGE_SIZE) - rcr_size == addr) { 3403 *link = (struct page *) page->mapping; 3404 np->ops->unmap_page(np->device, page->index, 3405 PAGE_SIZE, DMA_FROM_DEVICE); 3406 page->index = 0; 3407 page->mapping = NULL; 3408 __free_page(page); 3409 rp->rbr_refill_pending++; 3410 } 3411 3412 index = NEXT_RCR(rp, index); 3413 if (!(val & RCR_ENTRY_MULTI)) 3414 break; 3415 3416 } 3417 rp->rcr_index = index; 3418 3419 return num_rcr; 3420 } 3421 3422 static int niu_process_rx_pkt(struct napi_struct *napi, struct niu *np, 3423 struct rx_ring_info *rp) 3424 { 3425 unsigned int index = rp->rcr_index; 3426 struct rx_pkt_hdr1 *rh; 3427 struct sk_buff *skb; 3428 int len, num_rcr; 3429 3430 skb = netdev_alloc_skb(np->dev, RX_SKB_ALLOC_SIZE); 3431 if (unlikely(!skb)) 3432 return niu_rx_pkt_ignore(np, rp); 3433 3434 num_rcr = 0; 3435 while (1) { 3436 struct page *page, **link; 3437 u32 rcr_size, append_size; 3438 u64 addr, val, off; 3439 3440 num_rcr++; 3441 3442 val = le64_to_cpup(&rp->rcr[index]); 3443 3444 len = (val & RCR_ENTRY_L2_LEN) >> 3445 RCR_ENTRY_L2_LEN_SHIFT; 3446 len -= ETH_FCS_LEN; 3447 3448 addr = (val & RCR_ENTRY_PKT_BUF_ADDR) << 3449 RCR_ENTRY_PKT_BUF_ADDR_SHIFT; 3450 page = niu_find_rxpage(rp, addr, &link); 3451 3452 rcr_size = rp->rbr_sizes[(val & RCR_ENTRY_PKTBUFSZ) >> 3453 RCR_ENTRY_PKTBUFSZ_SHIFT]; 3454 3455 off = addr & ~PAGE_MASK; 3456 append_size = rcr_size; 3457 if (num_rcr == 1) { 3458 int ptype; 3459 3460 ptype = (val >> RCR_ENTRY_PKT_TYPE_SHIFT); 3461 if ((ptype == RCR_PKT_TYPE_TCP || 3462 ptype == RCR_PKT_TYPE_UDP) && 3463 !(val & (RCR_ENTRY_NOPORT | 3464 RCR_ENTRY_ERROR))) 3465 skb->ip_summed = CHECKSUM_UNNECESSARY; 3466 else 3467 skb_checksum_none_assert(skb); 3468 } else if (!(val & RCR_ENTRY_MULTI)) 3469 append_size = len - skb->len; 3470 3471 niu_rx_skb_append(skb, page, off, append_size, rcr_size); 3472 if ((page->index + rp->rbr_block_size) - rcr_size == addr) { 3473 *link = (struct page *) page->mapping; 3474 np->ops->unmap_page(np->device, page->index, 3475 PAGE_SIZE, DMA_FROM_DEVICE); 3476 page->index = 0; 3477 page->mapping = NULL; 3478 rp->rbr_refill_pending++; 3479 } else 3480 get_page(page); 3481 3482 index = NEXT_RCR(rp, index); 3483 if (!(val & RCR_ENTRY_MULTI)) 3484 break; 3485 3486 } 3487 rp->rcr_index = index; 3488 3489 len += sizeof(*rh); 3490 len = min_t(int, len, sizeof(*rh) + VLAN_ETH_HLEN); 3491 __pskb_pull_tail(skb, len); 3492 3493 rh = (struct rx_pkt_hdr1 *) skb->data; 3494 if (np->dev->features & NETIF_F_RXHASH) 3495 skb_set_hash(skb, 3496 ((u32)rh->hashval2_0 << 24 | 3497 (u32)rh->hashval2_1 << 16 | 3498 (u32)rh->hashval1_1 << 8 | 3499 (u32)rh->hashval1_2 << 0), 3500 PKT_HASH_TYPE_L3); 3501 skb_pull(skb, sizeof(*rh)); 3502 3503 rp->rx_packets++; 3504 rp->rx_bytes += skb->len; 3505 3506 skb->protocol = eth_type_trans(skb, np->dev); 3507 skb_record_rx_queue(skb, rp->rx_channel); 3508 napi_gro_receive(napi, skb); 3509 3510 return num_rcr; 3511 } 3512 3513 static int niu_rbr_fill(struct niu *np, struct rx_ring_info *rp, gfp_t mask) 3514 { 3515 int blocks_per_page = rp->rbr_blocks_per_page; 3516 int err, index = rp->rbr_index; 3517 3518 err = 0; 3519 while (index < (rp->rbr_table_size - blocks_per_page)) { 3520 err = niu_rbr_add_page(np, rp, mask, index); 3521 if (unlikely(err)) 3522 break; 3523 3524 index += blocks_per_page; 3525 } 3526 3527 rp->rbr_index = index; 3528 return err; 3529 } 3530 3531 static void niu_rbr_free(struct niu *np, struct rx_ring_info *rp) 3532 { 3533 int i; 3534 3535 for (i = 0; i < MAX_RBR_RING_SIZE; i++) { 3536 struct page *page; 3537 3538 page = rp->rxhash[i]; 3539 while (page) { 3540 struct page *next = (struct page *) page->mapping; 3541 u64 base = page->index; 3542 3543 np->ops->unmap_page(np->device, base, PAGE_SIZE, 3544 DMA_FROM_DEVICE); 3545 page->index = 0; 3546 page->mapping = NULL; 3547 3548 __free_page(page); 3549 3550 page = next; 3551 } 3552 } 3553 3554 for (i = 0; i < rp->rbr_table_size; i++) 3555 rp->rbr[i] = cpu_to_le32(0); 3556 rp->rbr_index = 0; 3557 } 3558 3559 static int release_tx_packet(struct niu *np, struct tx_ring_info *rp, int idx) 3560 { 3561 struct tx_buff_info *tb = &rp->tx_buffs[idx]; 3562 struct sk_buff *skb = tb->skb; 3563 struct tx_pkt_hdr *tp; 3564 u64 tx_flags; 3565 int i, len; 3566 3567 tp = (struct tx_pkt_hdr *) skb->data; 3568 tx_flags = le64_to_cpup(&tp->flags); 3569 3570 rp->tx_packets++; 3571 rp->tx_bytes += (((tx_flags & TXHDR_LEN) >> TXHDR_LEN_SHIFT) - 3572 ((tx_flags & TXHDR_PAD) / 2)); 3573 3574 len = skb_headlen(skb); 3575 np->ops->unmap_single(np->device, tb->mapping, 3576 len, DMA_TO_DEVICE); 3577 3578 if (le64_to_cpu(rp->descr[idx]) & TX_DESC_MARK) 3579 rp->mark_pending--; 3580 3581 tb->skb = NULL; 3582 do { 3583 idx = NEXT_TX(rp, idx); 3584 len -= MAX_TX_DESC_LEN; 3585 } while (len > 0); 3586 3587 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { 3588 tb = &rp->tx_buffs[idx]; 3589 BUG_ON(tb->skb != NULL); 3590 np->ops->unmap_page(np->device, tb->mapping, 3591 skb_frag_size(&skb_shinfo(skb)->frags[i]), 3592 DMA_TO_DEVICE); 3593 idx = NEXT_TX(rp, idx); 3594 } 3595 3596 dev_kfree_skb(skb); 3597 3598 return idx; 3599 } 3600 3601 #define NIU_TX_WAKEUP_THRESH(rp) ((rp)->pending / 4) 3602 3603 static void niu_tx_work(struct niu *np, struct tx_ring_info *rp) 3604 { 3605 struct netdev_queue *txq; 3606 u16 pkt_cnt, tmp; 3607 int cons, index; 3608 u64 cs; 3609 3610 index = (rp - np->tx_rings); 3611 txq = netdev_get_tx_queue(np->dev, index); 3612 3613 cs = rp->tx_cs; 3614 if (unlikely(!(cs & (TX_CS_MK | TX_CS_MMK)))) 3615 goto out; 3616 3617 tmp = pkt_cnt = (cs & TX_CS_PKT_CNT) >> TX_CS_PKT_CNT_SHIFT; 3618 pkt_cnt = (pkt_cnt - rp->last_pkt_cnt) & 3619 (TX_CS_PKT_CNT >> TX_CS_PKT_CNT_SHIFT); 3620 3621 rp->last_pkt_cnt = tmp; 3622 3623 cons = rp->cons; 3624 3625 netif_printk(np, tx_done, KERN_DEBUG, np->dev, 3626 "%s() pkt_cnt[%u] cons[%d]\n", __func__, pkt_cnt, cons); 3627 3628 while (pkt_cnt--) 3629 cons = release_tx_packet(np, rp, cons); 3630 3631 rp->cons = cons; 3632 smp_mb(); 3633 3634 out: 3635 if (unlikely(netif_tx_queue_stopped(txq) && 3636 (niu_tx_avail(rp) > NIU_TX_WAKEUP_THRESH(rp)))) { 3637 __netif_tx_lock(txq, smp_processor_id()); 3638 if (netif_tx_queue_stopped(txq) && 3639 (niu_tx_avail(rp) > NIU_TX_WAKEUP_THRESH(rp))) 3640 netif_tx_wake_queue(txq); 3641 __netif_tx_unlock(txq); 3642 } 3643 } 3644 3645 static inline void niu_sync_rx_discard_stats(struct niu *np, 3646 struct rx_ring_info *rp, 3647 const int limit) 3648 { 3649 /* This elaborate scheme is needed for reading the RX discard 3650 * counters, as they are only 16-bit and can overflow quickly, 3651 * and because the overflow indication bit is not usable as 3652 * the counter value does not wrap, but remains at max value 3653 * 0xFFFF. 3654 * 3655 * In theory and in practice counters can be lost in between 3656 * reading nr64() and clearing the counter nw64(). For this 3657 * reason, the number of counter clearings nw64() is 3658 * limited/reduced though the limit parameter. 3659 */ 3660 int rx_channel = rp->rx_channel; 3661 u32 misc, wred; 3662 3663 /* RXMISC (Receive Miscellaneous Discard Count), covers the 3664 * following discard events: IPP (Input Port Process), 3665 * FFLP/TCAM, Full RCR (Receive Completion Ring) RBR (Receive 3666 * Block Ring) prefetch buffer is empty. 3667 */ 3668 misc = nr64(RXMISC(rx_channel)); 3669 if (unlikely((misc & RXMISC_COUNT) > limit)) { 3670 nw64(RXMISC(rx_channel), 0); 3671 rp->rx_errors += misc & RXMISC_COUNT; 3672 3673 if (unlikely(misc & RXMISC_OFLOW)) 3674 dev_err(np->device, "rx-%d: Counter overflow RXMISC discard\n", 3675 rx_channel); 3676 3677 netif_printk(np, rx_err, KERN_DEBUG, np->dev, 3678 "rx-%d: MISC drop=%u over=%u\n", 3679 rx_channel, misc, misc-limit); 3680 } 3681 3682 /* WRED (Weighted Random Early Discard) by hardware */ 3683 wred = nr64(RED_DIS_CNT(rx_channel)); 3684 if (unlikely((wred & RED_DIS_CNT_COUNT) > limit)) { 3685 nw64(RED_DIS_CNT(rx_channel), 0); 3686 rp->rx_dropped += wred & RED_DIS_CNT_COUNT; 3687 3688 if (unlikely(wred & RED_DIS_CNT_OFLOW)) 3689 dev_err(np->device, "rx-%d: Counter overflow WRED discard\n", rx_channel); 3690 3691 netif_printk(np, rx_err, KERN_DEBUG, np->dev, 3692 "rx-%d: WRED drop=%u over=%u\n", 3693 rx_channel, wred, wred-limit); 3694 } 3695 } 3696 3697 static int niu_rx_work(struct napi_struct *napi, struct niu *np, 3698 struct rx_ring_info *rp, int budget) 3699 { 3700 int qlen, rcr_done = 0, work_done = 0; 3701 struct rxdma_mailbox *mbox = rp->mbox; 3702 u64 stat; 3703 3704 #if 1 3705 stat = nr64(RX_DMA_CTL_STAT(rp->rx_channel)); 3706 qlen = nr64(RCRSTAT_A(rp->rx_channel)) & RCRSTAT_A_QLEN; 3707 #else 3708 stat = le64_to_cpup(&mbox->rx_dma_ctl_stat); 3709 qlen = (le64_to_cpup(&mbox->rcrstat_a) & RCRSTAT_A_QLEN); 3710 #endif 3711 mbox->rx_dma_ctl_stat = 0; 3712 mbox->rcrstat_a = 0; 3713 3714 netif_printk(np, rx_status, KERN_DEBUG, np->dev, 3715 "%s(chan[%d]), stat[%llx] qlen=%d\n", 3716 __func__, rp->rx_channel, (unsigned long long)stat, qlen); 3717 3718 rcr_done = work_done = 0; 3719 qlen = min(qlen, budget); 3720 while (work_done < qlen) { 3721 rcr_done += niu_process_rx_pkt(napi, np, rp); 3722 work_done++; 3723 } 3724 3725 if (rp->rbr_refill_pending >= rp->rbr_kick_thresh) { 3726 unsigned int i; 3727 3728 for (i = 0; i < rp->rbr_refill_pending; i++) 3729 niu_rbr_refill(np, rp, GFP_ATOMIC); 3730 rp->rbr_refill_pending = 0; 3731 } 3732 3733 stat = (RX_DMA_CTL_STAT_MEX | 3734 ((u64)work_done << RX_DMA_CTL_STAT_PKTREAD_SHIFT) | 3735 ((u64)rcr_done << RX_DMA_CTL_STAT_PTRREAD_SHIFT)); 3736 3737 nw64(RX_DMA_CTL_STAT(rp->rx_channel), stat); 3738 3739 /* Only sync discards stats when qlen indicate potential for drops */ 3740 if (qlen > 10) 3741 niu_sync_rx_discard_stats(np, rp, 0x7FFF); 3742 3743 return work_done; 3744 } 3745 3746 static int niu_poll_core(struct niu *np, struct niu_ldg *lp, int budget) 3747 { 3748 u64 v0 = lp->v0; 3749 u32 tx_vec = (v0 >> 32); 3750 u32 rx_vec = (v0 & 0xffffffff); 3751 int i, work_done = 0; 3752 3753 netif_printk(np, intr, KERN_DEBUG, np->dev, 3754 "%s() v0[%016llx]\n", __func__, (unsigned long long)v0); 3755 3756 for (i = 0; i < np->num_tx_rings; i++) { 3757 struct tx_ring_info *rp = &np->tx_rings[i]; 3758 if (tx_vec & (1 << rp->tx_channel)) 3759 niu_tx_work(np, rp); 3760 nw64(LD_IM0(LDN_TXDMA(rp->tx_channel)), 0); 3761 } 3762 3763 for (i = 0; i < np->num_rx_rings; i++) { 3764 struct rx_ring_info *rp = &np->rx_rings[i]; 3765 3766 if (rx_vec & (1 << rp->rx_channel)) { 3767 int this_work_done; 3768 3769 this_work_done = niu_rx_work(&lp->napi, np, rp, 3770 budget); 3771 3772 budget -= this_work_done; 3773 work_done += this_work_done; 3774 } 3775 nw64(LD_IM0(LDN_RXDMA(rp->rx_channel)), 0); 3776 } 3777 3778 return work_done; 3779 } 3780 3781 static int niu_poll(struct napi_struct *napi, int budget) 3782 { 3783 struct niu_ldg *lp = container_of(napi, struct niu_ldg, napi); 3784 struct niu *np = lp->np; 3785 int work_done; 3786 3787 work_done = niu_poll_core(np, lp, budget); 3788 3789 if (work_done < budget) { 3790 napi_complete(napi); 3791 niu_ldg_rearm(np, lp, 1); 3792 } 3793 return work_done; 3794 } 3795 3796 static void niu_log_rxchan_errors(struct niu *np, struct rx_ring_info *rp, 3797 u64 stat) 3798 { 3799 netdev_err(np->dev, "RX channel %u errors ( ", rp->rx_channel); 3800 3801 if (stat & RX_DMA_CTL_STAT_RBR_TMOUT) 3802 pr_cont("RBR_TMOUT "); 3803 if (stat & RX_DMA_CTL_STAT_RSP_CNT_ERR) 3804 pr_cont("RSP_CNT "); 3805 if (stat & RX_DMA_CTL_STAT_BYTE_EN_BUS) 3806 pr_cont("BYTE_EN_BUS "); 3807 if (stat & RX_DMA_CTL_STAT_RSP_DAT_ERR) 3808 pr_cont("RSP_DAT "); 3809 if (stat & RX_DMA_CTL_STAT_RCR_ACK_ERR) 3810 pr_cont("RCR_ACK "); 3811 if (stat & RX_DMA_CTL_STAT_RCR_SHA_PAR) 3812 pr_cont("RCR_SHA_PAR "); 3813 if (stat & RX_DMA_CTL_STAT_RBR_PRE_PAR) 3814 pr_cont("RBR_PRE_PAR "); 3815 if (stat & RX_DMA_CTL_STAT_CONFIG_ERR) 3816 pr_cont("CONFIG "); 3817 if (stat & RX_DMA_CTL_STAT_RCRINCON) 3818 pr_cont("RCRINCON "); 3819 if (stat & RX_DMA_CTL_STAT_RCRFULL) 3820 pr_cont("RCRFULL "); 3821 if (stat & RX_DMA_CTL_STAT_RBRFULL) 3822 pr_cont("RBRFULL "); 3823 if (stat & RX_DMA_CTL_STAT_RBRLOGPAGE) 3824 pr_cont("RBRLOGPAGE "); 3825 if (stat & RX_DMA_CTL_STAT_CFIGLOGPAGE) 3826 pr_cont("CFIGLOGPAGE "); 3827 if (stat & RX_DMA_CTL_STAT_DC_FIFO_ERR) 3828 pr_cont("DC_FIDO "); 3829 3830 pr_cont(")\n"); 3831 } 3832 3833 static int niu_rx_error(struct niu *np, struct rx_ring_info *rp) 3834 { 3835 u64 stat = nr64(RX_DMA_CTL_STAT(rp->rx_channel)); 3836 int err = 0; 3837 3838 3839 if (stat & (RX_DMA_CTL_STAT_CHAN_FATAL | 3840 RX_DMA_CTL_STAT_PORT_FATAL)) 3841 err = -EINVAL; 3842 3843 if (err) { 3844 netdev_err(np->dev, "RX channel %u error, stat[%llx]\n", 3845 rp->rx_channel, 3846 (unsigned long long) stat); 3847 3848 niu_log_rxchan_errors(np, rp, stat); 3849 } 3850 3851 nw64(RX_DMA_CTL_STAT(rp->rx_channel), 3852 stat & RX_DMA_CTL_WRITE_CLEAR_ERRS); 3853 3854 return err; 3855 } 3856 3857 static void niu_log_txchan_errors(struct niu *np, struct tx_ring_info *rp, 3858 u64 cs) 3859 { 3860 netdev_err(np->dev, "TX channel %u errors ( ", rp->tx_channel); 3861 3862 if (cs & TX_CS_MBOX_ERR) 3863 pr_cont("MBOX "); 3864 if (cs & TX_CS_PKT_SIZE_ERR) 3865 pr_cont("PKT_SIZE "); 3866 if (cs & TX_CS_TX_RING_OFLOW) 3867 pr_cont("TX_RING_OFLOW "); 3868 if (cs & TX_CS_PREF_BUF_PAR_ERR) 3869 pr_cont("PREF_BUF_PAR "); 3870 if (cs & TX_CS_NACK_PREF) 3871 pr_cont("NACK_PREF "); 3872 if (cs & TX_CS_NACK_PKT_RD) 3873 pr_cont("NACK_PKT_RD "); 3874 if (cs & TX_CS_CONF_PART_ERR) 3875 pr_cont("CONF_PART "); 3876 if (cs & TX_CS_PKT_PRT_ERR) 3877 pr_cont("PKT_PTR "); 3878 3879 pr_cont(")\n"); 3880 } 3881 3882 static int niu_tx_error(struct niu *np, struct tx_ring_info *rp) 3883 { 3884 u64 cs, logh, logl; 3885 3886 cs = nr64(TX_CS(rp->tx_channel)); 3887 logh = nr64(TX_RNG_ERR_LOGH(rp->tx_channel)); 3888 logl = nr64(TX_RNG_ERR_LOGL(rp->tx_channel)); 3889 3890 netdev_err(np->dev, "TX channel %u error, cs[%llx] logh[%llx] logl[%llx]\n", 3891 rp->tx_channel, 3892 (unsigned long long)cs, 3893 (unsigned long long)logh, 3894 (unsigned long long)logl); 3895 3896 niu_log_txchan_errors(np, rp, cs); 3897 3898 return -ENODEV; 3899 } 3900 3901 static int niu_mif_interrupt(struct niu *np) 3902 { 3903 u64 mif_status = nr64(MIF_STATUS); 3904 int phy_mdint = 0; 3905 3906 if (np->flags & NIU_FLAGS_XMAC) { 3907 u64 xrxmac_stat = nr64_mac(XRXMAC_STATUS); 3908 3909 if (xrxmac_stat & XRXMAC_STATUS_PHY_MDINT) 3910 phy_mdint = 1; 3911 } 3912 3913 netdev_err(np->dev, "MIF interrupt, stat[%llx] phy_mdint(%d)\n", 3914 (unsigned long long)mif_status, phy_mdint); 3915 3916 return -ENODEV; 3917 } 3918 3919 static void niu_xmac_interrupt(struct niu *np) 3920 { 3921 struct niu_xmac_stats *mp = &np->mac_stats.xmac; 3922 u64 val; 3923 3924 val = nr64_mac(XTXMAC_STATUS); 3925 if (val & XTXMAC_STATUS_FRAME_CNT_EXP) 3926 mp->tx_frames += TXMAC_FRM_CNT_COUNT; 3927 if (val & XTXMAC_STATUS_BYTE_CNT_EXP) 3928 mp->tx_bytes += TXMAC_BYTE_CNT_COUNT; 3929 if (val & XTXMAC_STATUS_TXFIFO_XFR_ERR) 3930 mp->tx_fifo_errors++; 3931 if (val & XTXMAC_STATUS_TXMAC_OFLOW) 3932 mp->tx_overflow_errors++; 3933 if (val & XTXMAC_STATUS_MAX_PSIZE_ERR) 3934 mp->tx_max_pkt_size_errors++; 3935 if (val & XTXMAC_STATUS_TXMAC_UFLOW) 3936 mp->tx_underflow_errors++; 3937 3938 val = nr64_mac(XRXMAC_STATUS); 3939 if (val & XRXMAC_STATUS_LCL_FLT_STATUS) 3940 mp->rx_local_faults++; 3941 if (val & XRXMAC_STATUS_RFLT_DET) 3942 mp->rx_remote_faults++; 3943 if (val & XRXMAC_STATUS_LFLT_CNT_EXP) 3944 mp->rx_link_faults += LINK_FAULT_CNT_COUNT; 3945 if (val & XRXMAC_STATUS_ALIGNERR_CNT_EXP) 3946 mp->rx_align_errors += RXMAC_ALIGN_ERR_CNT_COUNT; 3947 if (val & XRXMAC_STATUS_RXFRAG_CNT_EXP) 3948 mp->rx_frags += RXMAC_FRAG_CNT_COUNT; 3949 if (val & XRXMAC_STATUS_RXMULTF_CNT_EXP) 3950 mp->rx_mcasts += RXMAC_MC_FRM_CNT_COUNT; 3951 if (val & XRXMAC_STATUS_RXBCAST_CNT_EXP) 3952 mp->rx_bcasts += RXMAC_BC_FRM_CNT_COUNT; 3953 if (val & XRXMAC_STATUS_RXBCAST_CNT_EXP) 3954 mp->rx_bcasts += RXMAC_BC_FRM_CNT_COUNT; 3955 if (val & XRXMAC_STATUS_RXHIST1_CNT_EXP) 3956 mp->rx_hist_cnt1 += RXMAC_HIST_CNT1_COUNT; 3957 if (val & XRXMAC_STATUS_RXHIST2_CNT_EXP) 3958 mp->rx_hist_cnt2 += RXMAC_HIST_CNT2_COUNT; 3959 if (val & XRXMAC_STATUS_RXHIST3_CNT_EXP) 3960 mp->rx_hist_cnt3 += RXMAC_HIST_CNT3_COUNT; 3961 if (val & XRXMAC_STATUS_RXHIST4_CNT_EXP) 3962 mp->rx_hist_cnt4 += RXMAC_HIST_CNT4_COUNT; 3963 if (val & XRXMAC_STATUS_RXHIST5_CNT_EXP) 3964 mp->rx_hist_cnt5 += RXMAC_HIST_CNT5_COUNT; 3965 if (val & XRXMAC_STATUS_RXHIST6_CNT_EXP) 3966 mp->rx_hist_cnt6 += RXMAC_HIST_CNT6_COUNT; 3967 if (val & XRXMAC_STATUS_RXHIST7_CNT_EXP) 3968 mp->rx_hist_cnt7 += RXMAC_HIST_CNT7_COUNT; 3969 if (val & XRXMAC_STATUS_RXOCTET_CNT_EXP) 3970 mp->rx_octets += RXMAC_BT_CNT_COUNT; 3971 if (val & XRXMAC_STATUS_CVIOLERR_CNT_EXP) 3972 mp->rx_code_violations += RXMAC_CD_VIO_CNT_COUNT; 3973 if (val & XRXMAC_STATUS_LENERR_CNT_EXP) 3974 mp->rx_len_errors += RXMAC_MPSZER_CNT_COUNT; 3975 if (val & XRXMAC_STATUS_CRCERR_CNT_EXP) 3976 mp->rx_crc_errors += RXMAC_CRC_ER_CNT_COUNT; 3977 if (val & XRXMAC_STATUS_RXUFLOW) 3978 mp->rx_underflows++; 3979 if (val & XRXMAC_STATUS_RXOFLOW) 3980 mp->rx_overflows++; 3981 3982 val = nr64_mac(XMAC_FC_STAT); 3983 if (val & XMAC_FC_STAT_TX_MAC_NPAUSE) 3984 mp->pause_off_state++; 3985 if (val & XMAC_FC_STAT_TX_MAC_PAUSE) 3986 mp->pause_on_state++; 3987 if (val & XMAC_FC_STAT_RX_MAC_RPAUSE) 3988 mp->pause_received++; 3989 } 3990 3991 static void niu_bmac_interrupt(struct niu *np) 3992 { 3993 struct niu_bmac_stats *mp = &np->mac_stats.bmac; 3994 u64 val; 3995 3996 val = nr64_mac(BTXMAC_STATUS); 3997 if (val & BTXMAC_STATUS_UNDERRUN) 3998 mp->tx_underflow_errors++; 3999 if (val & BTXMAC_STATUS_MAX_PKT_ERR) 4000 mp->tx_max_pkt_size_errors++; 4001 if (val & BTXMAC_STATUS_BYTE_CNT_EXP) 4002 mp->tx_bytes += BTXMAC_BYTE_CNT_COUNT; 4003 if (val & BTXMAC_STATUS_FRAME_CNT_EXP) 4004 mp->tx_frames += BTXMAC_FRM_CNT_COUNT; 4005 4006 val = nr64_mac(BRXMAC_STATUS); 4007 if (val & BRXMAC_STATUS_OVERFLOW) 4008 mp->rx_overflows++; 4009 if (val & BRXMAC_STATUS_FRAME_CNT_EXP) 4010 mp->rx_frames += BRXMAC_FRAME_CNT_COUNT; 4011 if (val & BRXMAC_STATUS_ALIGN_ERR_EXP) 4012 mp->rx_align_errors += BRXMAC_ALIGN_ERR_CNT_COUNT; 4013 if (val & BRXMAC_STATUS_CRC_ERR_EXP) 4014 mp->rx_crc_errors += BRXMAC_ALIGN_ERR_CNT_COUNT; 4015 if (val & BRXMAC_STATUS_LEN_ERR_EXP) 4016 mp->rx_len_errors += BRXMAC_CODE_VIOL_ERR_CNT_COUNT; 4017 4018 val = nr64_mac(BMAC_CTRL_STATUS); 4019 if (val & BMAC_CTRL_STATUS_NOPAUSE) 4020 mp->pause_off_state++; 4021 if (val & BMAC_CTRL_STATUS_PAUSE) 4022 mp->pause_on_state++; 4023 if (val & BMAC_CTRL_STATUS_PAUSE_RECV) 4024 mp->pause_received++; 4025 } 4026 4027 static int niu_mac_interrupt(struct niu *np) 4028 { 4029 if (np->flags & NIU_FLAGS_XMAC) 4030 niu_xmac_interrupt(np); 4031 else 4032 niu_bmac_interrupt(np); 4033 4034 return 0; 4035 } 4036 4037 static void niu_log_device_error(struct niu *np, u64 stat) 4038 { 4039 netdev_err(np->dev, "Core device errors ( "); 4040 4041 if (stat & SYS_ERR_MASK_META2) 4042 pr_cont("META2 "); 4043 if (stat & SYS_ERR_MASK_META1) 4044 pr_cont("META1 "); 4045 if (stat & SYS_ERR_MASK_PEU) 4046 pr_cont("PEU "); 4047 if (stat & SYS_ERR_MASK_TXC) 4048 pr_cont("TXC "); 4049 if (stat & SYS_ERR_MASK_RDMC) 4050 pr_cont("RDMC "); 4051 if (stat & SYS_ERR_MASK_TDMC) 4052 pr_cont("TDMC "); 4053 if (stat & SYS_ERR_MASK_ZCP) 4054 pr_cont("ZCP "); 4055 if (stat & SYS_ERR_MASK_FFLP) 4056 pr_cont("FFLP "); 4057 if (stat & SYS_ERR_MASK_IPP) 4058 pr_cont("IPP "); 4059 if (stat & SYS_ERR_MASK_MAC) 4060 pr_cont("MAC "); 4061 if (stat & SYS_ERR_MASK_SMX) 4062 pr_cont("SMX "); 4063 4064 pr_cont(")\n"); 4065 } 4066 4067 static int niu_device_error(struct niu *np) 4068 { 4069 u64 stat = nr64(SYS_ERR_STAT); 4070 4071 netdev_err(np->dev, "Core device error, stat[%llx]\n", 4072 (unsigned long long)stat); 4073 4074 niu_log_device_error(np, stat); 4075 4076 return -ENODEV; 4077 } 4078 4079 static int niu_slowpath_interrupt(struct niu *np, struct niu_ldg *lp, 4080 u64 v0, u64 v1, u64 v2) 4081 { 4082 4083 int i, err = 0; 4084 4085 lp->v0 = v0; 4086 lp->v1 = v1; 4087 lp->v2 = v2; 4088 4089 if (v1 & 0x00000000ffffffffULL) { 4090 u32 rx_vec = (v1 & 0xffffffff); 4091 4092 for (i = 0; i < np->num_rx_rings; i++) { 4093 struct rx_ring_info *rp = &np->rx_rings[i]; 4094 4095 if (rx_vec & (1 << rp->rx_channel)) { 4096 int r = niu_rx_error(np, rp); 4097 if (r) { 4098 err = r; 4099 } else { 4100 if (!v0) 4101 nw64(RX_DMA_CTL_STAT(rp->rx_channel), 4102 RX_DMA_CTL_STAT_MEX); 4103 } 4104 } 4105 } 4106 } 4107 if (v1 & 0x7fffffff00000000ULL) { 4108 u32 tx_vec = (v1 >> 32) & 0x7fffffff; 4109 4110 for (i = 0; i < np->num_tx_rings; i++) { 4111 struct tx_ring_info *rp = &np->tx_rings[i]; 4112 4113 if (tx_vec & (1 << rp->tx_channel)) { 4114 int r = niu_tx_error(np, rp); 4115 if (r) 4116 err = r; 4117 } 4118 } 4119 } 4120 if ((v0 | v1) & 0x8000000000000000ULL) { 4121 int r = niu_mif_interrupt(np); 4122 if (r) 4123 err = r; 4124 } 4125 if (v2) { 4126 if (v2 & 0x01ef) { 4127 int r = niu_mac_interrupt(np); 4128 if (r) 4129 err = r; 4130 } 4131 if (v2 & 0x0210) { 4132 int r = niu_device_error(np); 4133 if (r) 4134 err = r; 4135 } 4136 } 4137 4138 if (err) 4139 niu_enable_interrupts(np, 0); 4140 4141 return err; 4142 } 4143 4144 static void niu_rxchan_intr(struct niu *np, struct rx_ring_info *rp, 4145 int ldn) 4146 { 4147 struct rxdma_mailbox *mbox = rp->mbox; 4148 u64 stat_write, stat = le64_to_cpup(&mbox->rx_dma_ctl_stat); 4149 4150 stat_write = (RX_DMA_CTL_STAT_RCRTHRES | 4151 RX_DMA_CTL_STAT_RCRTO); 4152 nw64(RX_DMA_CTL_STAT(rp->rx_channel), stat_write); 4153 4154 netif_printk(np, intr, KERN_DEBUG, np->dev, 4155 "%s() stat[%llx]\n", __func__, (unsigned long long)stat); 4156 } 4157 4158 static void niu_txchan_intr(struct niu *np, struct tx_ring_info *rp, 4159 int ldn) 4160 { 4161 rp->tx_cs = nr64(TX_CS(rp->tx_channel)); 4162 4163 netif_printk(np, intr, KERN_DEBUG, np->dev, 4164 "%s() cs[%llx]\n", __func__, (unsigned long long)rp->tx_cs); 4165 } 4166 4167 static void __niu_fastpath_interrupt(struct niu *np, int ldg, u64 v0) 4168 { 4169 struct niu_parent *parent = np->parent; 4170 u32 rx_vec, tx_vec; 4171 int i; 4172 4173 tx_vec = (v0 >> 32); 4174 rx_vec = (v0 & 0xffffffff); 4175 4176 for (i = 0; i < np->num_rx_rings; i++) { 4177 struct rx_ring_info *rp = &np->rx_rings[i]; 4178 int ldn = LDN_RXDMA(rp->rx_channel); 4179 4180 if (parent->ldg_map[ldn] != ldg) 4181 continue; 4182 4183 nw64(LD_IM0(ldn), LD_IM0_MASK); 4184 if (rx_vec & (1 << rp->rx_channel)) 4185 niu_rxchan_intr(np, rp, ldn); 4186 } 4187 4188 for (i = 0; i < np->num_tx_rings; i++) { 4189 struct tx_ring_info *rp = &np->tx_rings[i]; 4190 int ldn = LDN_TXDMA(rp->tx_channel); 4191 4192 if (parent->ldg_map[ldn] != ldg) 4193 continue; 4194 4195 nw64(LD_IM0(ldn), LD_IM0_MASK); 4196 if (tx_vec & (1 << rp->tx_channel)) 4197 niu_txchan_intr(np, rp, ldn); 4198 } 4199 } 4200 4201 static void niu_schedule_napi(struct niu *np, struct niu_ldg *lp, 4202 u64 v0, u64 v1, u64 v2) 4203 { 4204 if (likely(napi_schedule_prep(&lp->napi))) { 4205 lp->v0 = v0; 4206 lp->v1 = v1; 4207 lp->v2 = v2; 4208 __niu_fastpath_interrupt(np, lp->ldg_num, v0); 4209 __napi_schedule(&lp->napi); 4210 } 4211 } 4212 4213 static irqreturn_t niu_interrupt(int irq, void *dev_id) 4214 { 4215 struct niu_ldg *lp = dev_id; 4216 struct niu *np = lp->np; 4217 int ldg = lp->ldg_num; 4218 unsigned long flags; 4219 u64 v0, v1, v2; 4220 4221 if (netif_msg_intr(np)) 4222 printk(KERN_DEBUG KBUILD_MODNAME ": " "%s() ldg[%p](%d)", 4223 __func__, lp, ldg); 4224 4225 spin_lock_irqsave(&np->lock, flags); 4226 4227 v0 = nr64(LDSV0(ldg)); 4228 v1 = nr64(LDSV1(ldg)); 4229 v2 = nr64(LDSV2(ldg)); 4230 4231 if (netif_msg_intr(np)) 4232 pr_cont(" v0[%llx] v1[%llx] v2[%llx]\n", 4233 (unsigned long long) v0, 4234 (unsigned long long) v1, 4235 (unsigned long long) v2); 4236 4237 if (unlikely(!v0 && !v1 && !v2)) { 4238 spin_unlock_irqrestore(&np->lock, flags); 4239 return IRQ_NONE; 4240 } 4241 4242 if (unlikely((v0 & ((u64)1 << LDN_MIF)) || v1 || v2)) { 4243 int err = niu_slowpath_interrupt(np, lp, v0, v1, v2); 4244 if (err) 4245 goto out; 4246 } 4247 if (likely(v0 & ~((u64)1 << LDN_MIF))) 4248 niu_schedule_napi(np, lp, v0, v1, v2); 4249 else 4250 niu_ldg_rearm(np, lp, 1); 4251 out: 4252 spin_unlock_irqrestore(&np->lock, flags); 4253 4254 return IRQ_HANDLED; 4255 } 4256 4257 static void niu_free_rx_ring_info(struct niu *np, struct rx_ring_info *rp) 4258 { 4259 if (rp->mbox) { 4260 np->ops->free_coherent(np->device, 4261 sizeof(struct rxdma_mailbox), 4262 rp->mbox, rp->mbox_dma); 4263 rp->mbox = NULL; 4264 } 4265 if (rp->rcr) { 4266 np->ops->free_coherent(np->device, 4267 MAX_RCR_RING_SIZE * sizeof(__le64), 4268 rp->rcr, rp->rcr_dma); 4269 rp->rcr = NULL; 4270 rp->rcr_table_size = 0; 4271 rp->rcr_index = 0; 4272 } 4273 if (rp->rbr) { 4274 niu_rbr_free(np, rp); 4275 4276 np->ops->free_coherent(np->device, 4277 MAX_RBR_RING_SIZE * sizeof(__le32), 4278 rp->rbr, rp->rbr_dma); 4279 rp->rbr = NULL; 4280 rp->rbr_table_size = 0; 4281 rp->rbr_index = 0; 4282 } 4283 kfree(rp->rxhash); 4284 rp->rxhash = NULL; 4285 } 4286 4287 static void niu_free_tx_ring_info(struct niu *np, struct tx_ring_info *rp) 4288 { 4289 if (rp->mbox) { 4290 np->ops->free_coherent(np->device, 4291 sizeof(struct txdma_mailbox), 4292 rp->mbox, rp->mbox_dma); 4293 rp->mbox = NULL; 4294 } 4295 if (rp->descr) { 4296 int i; 4297 4298 for (i = 0; i < MAX_TX_RING_SIZE; i++) { 4299 if (rp->tx_buffs[i].skb) 4300 (void) release_tx_packet(np, rp, i); 4301 } 4302 4303 np->ops->free_coherent(np->device, 4304 MAX_TX_RING_SIZE * sizeof(__le64), 4305 rp->descr, rp->descr_dma); 4306 rp->descr = NULL; 4307 rp->pending = 0; 4308 rp->prod = 0; 4309 rp->cons = 0; 4310 rp->wrap_bit = 0; 4311 } 4312 } 4313 4314 static void niu_free_channels(struct niu *np) 4315 { 4316 int i; 4317 4318 if (np->rx_rings) { 4319 for (i = 0; i < np->num_rx_rings; i++) { 4320 struct rx_ring_info *rp = &np->rx_rings[i]; 4321 4322 niu_free_rx_ring_info(np, rp); 4323 } 4324 kfree(np->rx_rings); 4325 np->rx_rings = NULL; 4326 np->num_rx_rings = 0; 4327 } 4328 4329 if (np->tx_rings) { 4330 for (i = 0; i < np->num_tx_rings; i++) { 4331 struct tx_ring_info *rp = &np->tx_rings[i]; 4332 4333 niu_free_tx_ring_info(np, rp); 4334 } 4335 kfree(np->tx_rings); 4336 np->tx_rings = NULL; 4337 np->num_tx_rings = 0; 4338 } 4339 } 4340 4341 static int niu_alloc_rx_ring_info(struct niu *np, 4342 struct rx_ring_info *rp) 4343 { 4344 BUILD_BUG_ON(sizeof(struct rxdma_mailbox) != 64); 4345 4346 rp->rxhash = kcalloc(MAX_RBR_RING_SIZE, sizeof(struct page *), 4347 GFP_KERNEL); 4348 if (!rp->rxhash) 4349 return -ENOMEM; 4350 4351 rp->mbox = np->ops->alloc_coherent(np->device, 4352 sizeof(struct rxdma_mailbox), 4353 &rp->mbox_dma, GFP_KERNEL); 4354 if (!rp->mbox) 4355 return -ENOMEM; 4356 if ((unsigned long)rp->mbox & (64UL - 1)) { 4357 netdev_err(np->dev, "Coherent alloc gives misaligned RXDMA mailbox %p\n", 4358 rp->mbox); 4359 return -EINVAL; 4360 } 4361 4362 rp->rcr = np->ops->alloc_coherent(np->device, 4363 MAX_RCR_RING_SIZE * sizeof(__le64), 4364 &rp->rcr_dma, GFP_KERNEL); 4365 if (!rp->rcr) 4366 return -ENOMEM; 4367 if ((unsigned long)rp->rcr & (64UL - 1)) { 4368 netdev_err(np->dev, "Coherent alloc gives misaligned RXDMA RCR table %p\n", 4369 rp->rcr); 4370 return -EINVAL; 4371 } 4372 rp->rcr_table_size = MAX_RCR_RING_SIZE; 4373 rp->rcr_index = 0; 4374 4375 rp->rbr = np->ops->alloc_coherent(np->device, 4376 MAX_RBR_RING_SIZE * sizeof(__le32), 4377 &rp->rbr_dma, GFP_KERNEL); 4378 if (!rp->rbr) 4379 return -ENOMEM; 4380 if ((unsigned long)rp->rbr & (64UL - 1)) { 4381 netdev_err(np->dev, "Coherent alloc gives misaligned RXDMA RBR table %p\n", 4382 rp->rbr); 4383 return -EINVAL; 4384 } 4385 rp->rbr_table_size = MAX_RBR_RING_SIZE; 4386 rp->rbr_index = 0; 4387 rp->rbr_pending = 0; 4388 4389 return 0; 4390 } 4391 4392 static void niu_set_max_burst(struct niu *np, struct tx_ring_info *rp) 4393 { 4394 int mtu = np->dev->mtu; 4395 4396 /* These values are recommended by the HW designers for fair 4397 * utilization of DRR amongst the rings. 4398 */ 4399 rp->max_burst = mtu + 32; 4400 if (rp->max_burst > 4096) 4401 rp->max_burst = 4096; 4402 } 4403 4404 static int niu_alloc_tx_ring_info(struct niu *np, 4405 struct tx_ring_info *rp) 4406 { 4407 BUILD_BUG_ON(sizeof(struct txdma_mailbox) != 64); 4408 4409 rp->mbox = np->ops->alloc_coherent(np->device, 4410 sizeof(struct txdma_mailbox), 4411 &rp->mbox_dma, GFP_KERNEL); 4412 if (!rp->mbox) 4413 return -ENOMEM; 4414 if ((unsigned long)rp->mbox & (64UL - 1)) { 4415 netdev_err(np->dev, "Coherent alloc gives misaligned TXDMA mailbox %p\n", 4416 rp->mbox); 4417 return -EINVAL; 4418 } 4419 4420 rp->descr = np->ops->alloc_coherent(np->device, 4421 MAX_TX_RING_SIZE * sizeof(__le64), 4422 &rp->descr_dma, GFP_KERNEL); 4423 if (!rp->descr) 4424 return -ENOMEM; 4425 if ((unsigned long)rp->descr & (64UL - 1)) { 4426 netdev_err(np->dev, "Coherent alloc gives misaligned TXDMA descr table %p\n", 4427 rp->descr); 4428 return -EINVAL; 4429 } 4430 4431 rp->pending = MAX_TX_RING_SIZE; 4432 rp->prod = 0; 4433 rp->cons = 0; 4434 rp->wrap_bit = 0; 4435 4436 /* XXX make these configurable... XXX */ 4437 rp->mark_freq = rp->pending / 4; 4438 4439 niu_set_max_burst(np, rp); 4440 4441 return 0; 4442 } 4443 4444 static void niu_size_rbr(struct niu *np, struct rx_ring_info *rp) 4445 { 4446 u16 bss; 4447 4448 bss = min(PAGE_SHIFT, 15); 4449 4450 rp->rbr_block_size = 1 << bss; 4451 rp->rbr_blocks_per_page = 1 << (PAGE_SHIFT-bss); 4452 4453 rp->rbr_sizes[0] = 256; 4454 rp->rbr_sizes[1] = 1024; 4455 if (np->dev->mtu > ETH_DATA_LEN) { 4456 switch (PAGE_SIZE) { 4457 case 4 * 1024: 4458 rp->rbr_sizes[2] = 4096; 4459 break; 4460 4461 default: 4462 rp->rbr_sizes[2] = 8192; 4463 break; 4464 } 4465 } else { 4466 rp->rbr_sizes[2] = 2048; 4467 } 4468 rp->rbr_sizes[3] = rp->rbr_block_size; 4469 } 4470 4471 static int niu_alloc_channels(struct niu *np) 4472 { 4473 struct niu_parent *parent = np->parent; 4474 int first_rx_channel, first_tx_channel; 4475 int num_rx_rings, num_tx_rings; 4476 struct rx_ring_info *rx_rings; 4477 struct tx_ring_info *tx_rings; 4478 int i, port, err; 4479 4480 port = np->port; 4481 first_rx_channel = first_tx_channel = 0; 4482 for (i = 0; i < port; i++) { 4483 first_rx_channel += parent->rxchan_per_port[i]; 4484 first_tx_channel += parent->txchan_per_port[i]; 4485 } 4486 4487 num_rx_rings = parent->rxchan_per_port[port]; 4488 num_tx_rings = parent->txchan_per_port[port]; 4489 4490 rx_rings = kcalloc(num_rx_rings, sizeof(struct rx_ring_info), 4491 GFP_KERNEL); 4492 err = -ENOMEM; 4493 if (!rx_rings) 4494 goto out_err; 4495 4496 np->num_rx_rings = num_rx_rings; 4497 smp_wmb(); 4498 np->rx_rings = rx_rings; 4499 4500 netif_set_real_num_rx_queues(np->dev, num_rx_rings); 4501 4502 for (i = 0; i < np->num_rx_rings; i++) { 4503 struct rx_ring_info *rp = &np->rx_rings[i]; 4504 4505 rp->np = np; 4506 rp->rx_channel = first_rx_channel + i; 4507 4508 err = niu_alloc_rx_ring_info(np, rp); 4509 if (err) 4510 goto out_err; 4511 4512 niu_size_rbr(np, rp); 4513 4514 /* XXX better defaults, configurable, etc... XXX */ 4515 rp->nonsyn_window = 64; 4516 rp->nonsyn_threshold = rp->rcr_table_size - 64; 4517 rp->syn_window = 64; 4518 rp->syn_threshold = rp->rcr_table_size - 64; 4519 rp->rcr_pkt_threshold = 16; 4520 rp->rcr_timeout = 8; 4521 rp->rbr_kick_thresh = RBR_REFILL_MIN; 4522 if (rp->rbr_kick_thresh < rp->rbr_blocks_per_page) 4523 rp->rbr_kick_thresh = rp->rbr_blocks_per_page; 4524 4525 err = niu_rbr_fill(np, rp, GFP_KERNEL); 4526 if (err) 4527 return err; 4528 } 4529 4530 tx_rings = kcalloc(num_tx_rings, sizeof(struct tx_ring_info), 4531 GFP_KERNEL); 4532 err = -ENOMEM; 4533 if (!tx_rings) 4534 goto out_err; 4535 4536 np->num_tx_rings = num_tx_rings; 4537 smp_wmb(); 4538 np->tx_rings = tx_rings; 4539 4540 netif_set_real_num_tx_queues(np->dev, num_tx_rings); 4541 4542 for (i = 0; i < np->num_tx_rings; i++) { 4543 struct tx_ring_info *rp = &np->tx_rings[i]; 4544 4545 rp->np = np; 4546 rp->tx_channel = first_tx_channel + i; 4547 4548 err = niu_alloc_tx_ring_info(np, rp); 4549 if (err) 4550 goto out_err; 4551 } 4552 4553 return 0; 4554 4555 out_err: 4556 niu_free_channels(np); 4557 return err; 4558 } 4559 4560 static int niu_tx_cs_sng_poll(struct niu *np, int channel) 4561 { 4562 int limit = 1000; 4563 4564 while (--limit > 0) { 4565 u64 val = nr64(TX_CS(channel)); 4566 if (val & TX_CS_SNG_STATE) 4567 return 0; 4568 } 4569 return -ENODEV; 4570 } 4571 4572 static int niu_tx_channel_stop(struct niu *np, int channel) 4573 { 4574 u64 val = nr64(TX_CS(channel)); 4575 4576 val |= TX_CS_STOP_N_GO; 4577 nw64(TX_CS(channel), val); 4578 4579 return niu_tx_cs_sng_poll(np, channel); 4580 } 4581 4582 static int niu_tx_cs_reset_poll(struct niu *np, int channel) 4583 { 4584 int limit = 1000; 4585 4586 while (--limit > 0) { 4587 u64 val = nr64(TX_CS(channel)); 4588 if (!(val & TX_CS_RST)) 4589 return 0; 4590 } 4591 return -ENODEV; 4592 } 4593 4594 static int niu_tx_channel_reset(struct niu *np, int channel) 4595 { 4596 u64 val = nr64(TX_CS(channel)); 4597 int err; 4598 4599 val |= TX_CS_RST; 4600 nw64(TX_CS(channel), val); 4601 4602 err = niu_tx_cs_reset_poll(np, channel); 4603 if (!err) 4604 nw64(TX_RING_KICK(channel), 0); 4605 4606 return err; 4607 } 4608 4609 static int niu_tx_channel_lpage_init(struct niu *np, int channel) 4610 { 4611 u64 val; 4612 4613 nw64(TX_LOG_MASK1(channel), 0); 4614 nw64(TX_LOG_VAL1(channel), 0); 4615 nw64(TX_LOG_MASK2(channel), 0); 4616 nw64(TX_LOG_VAL2(channel), 0); 4617 nw64(TX_LOG_PAGE_RELO1(channel), 0); 4618 nw64(TX_LOG_PAGE_RELO2(channel), 0); 4619 nw64(TX_LOG_PAGE_HDL(channel), 0); 4620 4621 val = (u64)np->port << TX_LOG_PAGE_VLD_FUNC_SHIFT; 4622 val |= (TX_LOG_PAGE_VLD_PAGE0 | TX_LOG_PAGE_VLD_PAGE1); 4623 nw64(TX_LOG_PAGE_VLD(channel), val); 4624 4625 /* XXX TXDMA 32bit mode? XXX */ 4626 4627 return 0; 4628 } 4629 4630 static void niu_txc_enable_port(struct niu *np, int on) 4631 { 4632 unsigned long flags; 4633 u64 val, mask; 4634 4635 niu_lock_parent(np, flags); 4636 val = nr64(TXC_CONTROL); 4637 mask = (u64)1 << np->port; 4638 if (on) { 4639 val |= TXC_CONTROL_ENABLE | mask; 4640 } else { 4641 val &= ~mask; 4642 if ((val & ~TXC_CONTROL_ENABLE) == 0) 4643 val &= ~TXC_CONTROL_ENABLE; 4644 } 4645 nw64(TXC_CONTROL, val); 4646 niu_unlock_parent(np, flags); 4647 } 4648 4649 static void niu_txc_set_imask(struct niu *np, u64 imask) 4650 { 4651 unsigned long flags; 4652 u64 val; 4653 4654 niu_lock_parent(np, flags); 4655 val = nr64(TXC_INT_MASK); 4656 val &= ~TXC_INT_MASK_VAL(np->port); 4657 val |= (imask << TXC_INT_MASK_VAL_SHIFT(np->port)); 4658 niu_unlock_parent(np, flags); 4659 } 4660 4661 static void niu_txc_port_dma_enable(struct niu *np, int on) 4662 { 4663 u64 val = 0; 4664 4665 if (on) { 4666 int i; 4667 4668 for (i = 0; i < np->num_tx_rings; i++) 4669 val |= (1 << np->tx_rings[i].tx_channel); 4670 } 4671 nw64(TXC_PORT_DMA(np->port), val); 4672 } 4673 4674 static int niu_init_one_tx_channel(struct niu *np, struct tx_ring_info *rp) 4675 { 4676 int err, channel = rp->tx_channel; 4677 u64 val, ring_len; 4678 4679 err = niu_tx_channel_stop(np, channel); 4680 if (err) 4681 return err; 4682 4683 err = niu_tx_channel_reset(np, channel); 4684 if (err) 4685 return err; 4686 4687 err = niu_tx_channel_lpage_init(np, channel); 4688 if (err) 4689 return err; 4690 4691 nw64(TXC_DMA_MAX(channel), rp->max_burst); 4692 nw64(TX_ENT_MSK(channel), 0); 4693 4694 if (rp->descr_dma & ~(TX_RNG_CFIG_STADDR_BASE | 4695 TX_RNG_CFIG_STADDR)) { 4696 netdev_err(np->dev, "TX ring channel %d DMA addr (%llx) is not aligned\n", 4697 channel, (unsigned long long)rp->descr_dma); 4698 return -EINVAL; 4699 } 4700 4701 /* The length field in TX_RNG_CFIG is measured in 64-byte 4702 * blocks. rp->pending is the number of TX descriptors in 4703 * our ring, 8 bytes each, thus we divide by 8 bytes more 4704 * to get the proper value the chip wants. 4705 */ 4706 ring_len = (rp->pending / 8); 4707 4708 val = ((ring_len << TX_RNG_CFIG_LEN_SHIFT) | 4709 rp->descr_dma); 4710 nw64(TX_RNG_CFIG(channel), val); 4711 4712 if (((rp->mbox_dma >> 32) & ~TXDMA_MBH_MBADDR) || 4713 ((u32)rp->mbox_dma & ~TXDMA_MBL_MBADDR)) { 4714 netdev_err(np->dev, "TX ring channel %d MBOX addr (%llx) has invalid bits\n", 4715 channel, (unsigned long long)rp->mbox_dma); 4716 return -EINVAL; 4717 } 4718 nw64(TXDMA_MBH(channel), rp->mbox_dma >> 32); 4719 nw64(TXDMA_MBL(channel), rp->mbox_dma & TXDMA_MBL_MBADDR); 4720 4721 nw64(TX_CS(channel), 0); 4722 4723 rp->last_pkt_cnt = 0; 4724 4725 return 0; 4726 } 4727 4728 static void niu_init_rdc_groups(struct niu *np) 4729 { 4730 struct niu_rdc_tables *tp = &np->parent->rdc_group_cfg[np->port]; 4731 int i, first_table_num = tp->first_table_num; 4732 4733 for (i = 0; i < tp->num_tables; i++) { 4734 struct rdc_table *tbl = &tp->tables[i]; 4735 int this_table = first_table_num + i; 4736 int slot; 4737 4738 for (slot = 0; slot < NIU_RDC_TABLE_SLOTS; slot++) 4739 nw64(RDC_TBL(this_table, slot), 4740 tbl->rxdma_channel[slot]); 4741 } 4742 4743 nw64(DEF_RDC(np->port), np->parent->rdc_default[np->port]); 4744 } 4745 4746 static void niu_init_drr_weight(struct niu *np) 4747 { 4748 int type = phy_decode(np->parent->port_phy, np->port); 4749 u64 val; 4750 4751 switch (type) { 4752 case PORT_TYPE_10G: 4753 val = PT_DRR_WEIGHT_DEFAULT_10G; 4754 break; 4755 4756 case PORT_TYPE_1G: 4757 default: 4758 val = PT_DRR_WEIGHT_DEFAULT_1G; 4759 break; 4760 } 4761 nw64(PT_DRR_WT(np->port), val); 4762 } 4763 4764 static int niu_init_hostinfo(struct niu *np) 4765 { 4766 struct niu_parent *parent = np->parent; 4767 struct niu_rdc_tables *tp = &parent->rdc_group_cfg[np->port]; 4768 int i, err, num_alt = niu_num_alt_addr(np); 4769 int first_rdc_table = tp->first_table_num; 4770 4771 err = niu_set_primary_mac_rdc_table(np, first_rdc_table, 1); 4772 if (err) 4773 return err; 4774 4775 err = niu_set_multicast_mac_rdc_table(np, first_rdc_table, 1); 4776 if (err) 4777 return err; 4778 4779 for (i = 0; i < num_alt; i++) { 4780 err = niu_set_alt_mac_rdc_table(np, i, first_rdc_table, 1); 4781 if (err) 4782 return err; 4783 } 4784 4785 return 0; 4786 } 4787 4788 static int niu_rx_channel_reset(struct niu *np, int channel) 4789 { 4790 return niu_set_and_wait_clear(np, RXDMA_CFIG1(channel), 4791 RXDMA_CFIG1_RST, 1000, 10, 4792 "RXDMA_CFIG1"); 4793 } 4794 4795 static int niu_rx_channel_lpage_init(struct niu *np, int channel) 4796 { 4797 u64 val; 4798 4799 nw64(RX_LOG_MASK1(channel), 0); 4800 nw64(RX_LOG_VAL1(channel), 0); 4801 nw64(RX_LOG_MASK2(channel), 0); 4802 nw64(RX_LOG_VAL2(channel), 0); 4803 nw64(RX_LOG_PAGE_RELO1(channel), 0); 4804 nw64(RX_LOG_PAGE_RELO2(channel), 0); 4805 nw64(RX_LOG_PAGE_HDL(channel), 0); 4806 4807 val = (u64)np->port << RX_LOG_PAGE_VLD_FUNC_SHIFT; 4808 val |= (RX_LOG_PAGE_VLD_PAGE0 | RX_LOG_PAGE_VLD_PAGE1); 4809 nw64(RX_LOG_PAGE_VLD(channel), val); 4810 4811 return 0; 4812 } 4813 4814 static void niu_rx_channel_wred_init(struct niu *np, struct rx_ring_info *rp) 4815 { 4816 u64 val; 4817 4818 val = (((u64)rp->nonsyn_window << RDC_RED_PARA_WIN_SHIFT) | 4819 ((u64)rp->nonsyn_threshold << RDC_RED_PARA_THRE_SHIFT) | 4820 ((u64)rp->syn_window << RDC_RED_PARA_WIN_SYN_SHIFT) | 4821 ((u64)rp->syn_threshold << RDC_RED_PARA_THRE_SYN_SHIFT)); 4822 nw64(RDC_RED_PARA(rp->rx_channel), val); 4823 } 4824 4825 static int niu_compute_rbr_cfig_b(struct rx_ring_info *rp, u64 *ret) 4826 { 4827 u64 val = 0; 4828 4829 *ret = 0; 4830 switch (rp->rbr_block_size) { 4831 case 4 * 1024: 4832 val |= (RBR_BLKSIZE_4K << RBR_CFIG_B_BLKSIZE_SHIFT); 4833 break; 4834 case 8 * 1024: 4835 val |= (RBR_BLKSIZE_8K << RBR_CFIG_B_BLKSIZE_SHIFT); 4836 break; 4837 case 16 * 1024: 4838 val |= (RBR_BLKSIZE_16K << RBR_CFIG_B_BLKSIZE_SHIFT); 4839 break; 4840 case 32 * 1024: 4841 val |= (RBR_BLKSIZE_32K << RBR_CFIG_B_BLKSIZE_SHIFT); 4842 break; 4843 default: 4844 return -EINVAL; 4845 } 4846 val |= RBR_CFIG_B_VLD2; 4847 switch (rp->rbr_sizes[2]) { 4848 case 2 * 1024: 4849 val |= (RBR_BUFSZ2_2K << RBR_CFIG_B_BUFSZ2_SHIFT); 4850 break; 4851 case 4 * 1024: 4852 val |= (RBR_BUFSZ2_4K << RBR_CFIG_B_BUFSZ2_SHIFT); 4853 break; 4854 case 8 * 1024: 4855 val |= (RBR_BUFSZ2_8K << RBR_CFIG_B_BUFSZ2_SHIFT); 4856 break; 4857 case 16 * 1024: 4858 val |= (RBR_BUFSZ2_16K << RBR_CFIG_B_BUFSZ2_SHIFT); 4859 break; 4860 4861 default: 4862 return -EINVAL; 4863 } 4864 val |= RBR_CFIG_B_VLD1; 4865 switch (rp->rbr_sizes[1]) { 4866 case 1 * 1024: 4867 val |= (RBR_BUFSZ1_1K << RBR_CFIG_B_BUFSZ1_SHIFT); 4868 break; 4869 case 2 * 1024: 4870 val |= (RBR_BUFSZ1_2K << RBR_CFIG_B_BUFSZ1_SHIFT); 4871 break; 4872 case 4 * 1024: 4873 val |= (RBR_BUFSZ1_4K << RBR_CFIG_B_BUFSZ1_SHIFT); 4874 break; 4875 case 8 * 1024: 4876 val |= (RBR_BUFSZ1_8K << RBR_CFIG_B_BUFSZ1_SHIFT); 4877 break; 4878 4879 default: 4880 return -EINVAL; 4881 } 4882 val |= RBR_CFIG_B_VLD0; 4883 switch (rp->rbr_sizes[0]) { 4884 case 256: 4885 val |= (RBR_BUFSZ0_256 << RBR_CFIG_B_BUFSZ0_SHIFT); 4886 break; 4887 case 512: 4888 val |= (RBR_BUFSZ0_512 << RBR_CFIG_B_BUFSZ0_SHIFT); 4889 break; 4890 case 1 * 1024: 4891 val |= (RBR_BUFSZ0_1K << RBR_CFIG_B_BUFSZ0_SHIFT); 4892 break; 4893 case 2 * 1024: 4894 val |= (RBR_BUFSZ0_2K << RBR_CFIG_B_BUFSZ0_SHIFT); 4895 break; 4896 4897 default: 4898 return -EINVAL; 4899 } 4900 4901 *ret = val; 4902 return 0; 4903 } 4904 4905 static int niu_enable_rx_channel(struct niu *np, int channel, int on) 4906 { 4907 u64 val = nr64(RXDMA_CFIG1(channel)); 4908 int limit; 4909 4910 if (on) 4911 val |= RXDMA_CFIG1_EN; 4912 else 4913 val &= ~RXDMA_CFIG1_EN; 4914 nw64(RXDMA_CFIG1(channel), val); 4915 4916 limit = 1000; 4917 while (--limit > 0) { 4918 if (nr64(RXDMA_CFIG1(channel)) & RXDMA_CFIG1_QST) 4919 break; 4920 udelay(10); 4921 } 4922 if (limit <= 0) 4923 return -ENODEV; 4924 return 0; 4925 } 4926 4927 static int niu_init_one_rx_channel(struct niu *np, struct rx_ring_info *rp) 4928 { 4929 int err, channel = rp->rx_channel; 4930 u64 val; 4931 4932 err = niu_rx_channel_reset(np, channel); 4933 if (err) 4934 return err; 4935 4936 err = niu_rx_channel_lpage_init(np, channel); 4937 if (err) 4938 return err; 4939 4940 niu_rx_channel_wred_init(np, rp); 4941 4942 nw64(RX_DMA_ENT_MSK(channel), RX_DMA_ENT_MSK_RBR_EMPTY); 4943 nw64(RX_DMA_CTL_STAT(channel), 4944 (RX_DMA_CTL_STAT_MEX | 4945 RX_DMA_CTL_STAT_RCRTHRES | 4946 RX_DMA_CTL_STAT_RCRTO | 4947 RX_DMA_CTL_STAT_RBR_EMPTY)); 4948 nw64(RXDMA_CFIG1(channel), rp->mbox_dma >> 32); 4949 nw64(RXDMA_CFIG2(channel), 4950 ((rp->mbox_dma & RXDMA_CFIG2_MBADDR_L) | 4951 RXDMA_CFIG2_FULL_HDR)); 4952 nw64(RBR_CFIG_A(channel), 4953 ((u64)rp->rbr_table_size << RBR_CFIG_A_LEN_SHIFT) | 4954 (rp->rbr_dma & (RBR_CFIG_A_STADDR_BASE | RBR_CFIG_A_STADDR))); 4955 err = niu_compute_rbr_cfig_b(rp, &val); 4956 if (err) 4957 return err; 4958 nw64(RBR_CFIG_B(channel), val); 4959 nw64(RCRCFIG_A(channel), 4960 ((u64)rp->rcr_table_size << RCRCFIG_A_LEN_SHIFT) | 4961 (rp->rcr_dma & (RCRCFIG_A_STADDR_BASE | RCRCFIG_A_STADDR))); 4962 nw64(RCRCFIG_B(channel), 4963 ((u64)rp->rcr_pkt_threshold << RCRCFIG_B_PTHRES_SHIFT) | 4964 RCRCFIG_B_ENTOUT | 4965 ((u64)rp->rcr_timeout << RCRCFIG_B_TIMEOUT_SHIFT)); 4966 4967 err = niu_enable_rx_channel(np, channel, 1); 4968 if (err) 4969 return err; 4970 4971 nw64(RBR_KICK(channel), rp->rbr_index); 4972 4973 val = nr64(RX_DMA_CTL_STAT(channel)); 4974 val |= RX_DMA_CTL_STAT_RBR_EMPTY; 4975 nw64(RX_DMA_CTL_STAT(channel), val); 4976 4977 return 0; 4978 } 4979 4980 static int niu_init_rx_channels(struct niu *np) 4981 { 4982 unsigned long flags; 4983 u64 seed = jiffies_64; 4984 int err, i; 4985 4986 niu_lock_parent(np, flags); 4987 nw64(RX_DMA_CK_DIV, np->parent->rxdma_clock_divider); 4988 nw64(RED_RAN_INIT, RED_RAN_INIT_OPMODE | (seed & RED_RAN_INIT_VAL)); 4989 niu_unlock_parent(np, flags); 4990 4991 /* XXX RXDMA 32bit mode? XXX */ 4992 4993 niu_init_rdc_groups(np); 4994 niu_init_drr_weight(np); 4995 4996 err = niu_init_hostinfo(np); 4997 if (err) 4998 return err; 4999 5000 for (i = 0; i < np->num_rx_rings; i++) { 5001 struct rx_ring_info *rp = &np->rx_rings[i]; 5002 5003 err = niu_init_one_rx_channel(np, rp); 5004 if (err) 5005 return err; 5006 } 5007 5008 return 0; 5009 } 5010 5011 static int niu_set_ip_frag_rule(struct niu *np) 5012 { 5013 struct niu_parent *parent = np->parent; 5014 struct niu_classifier *cp = &np->clas; 5015 struct niu_tcam_entry *tp; 5016 int index, err; 5017 5018 index = cp->tcam_top; 5019 tp = &parent->tcam[index]; 5020 5021 /* Note that the noport bit is the same in both ipv4 and 5022 * ipv6 format TCAM entries. 5023 */ 5024 memset(tp, 0, sizeof(*tp)); 5025 tp->key[1] = TCAM_V4KEY1_NOPORT; 5026 tp->key_mask[1] = TCAM_V4KEY1_NOPORT; 5027 tp->assoc_data = (TCAM_ASSOCDATA_TRES_USE_OFFSET | 5028 ((u64)0 << TCAM_ASSOCDATA_OFFSET_SHIFT)); 5029 err = tcam_write(np, index, tp->key, tp->key_mask); 5030 if (err) 5031 return err; 5032 err = tcam_assoc_write(np, index, tp->assoc_data); 5033 if (err) 5034 return err; 5035 tp->valid = 1; 5036 cp->tcam_valid_entries++; 5037 5038 return 0; 5039 } 5040 5041 static int niu_init_classifier_hw(struct niu *np) 5042 { 5043 struct niu_parent *parent = np->parent; 5044 struct niu_classifier *cp = &np->clas; 5045 int i, err; 5046 5047 nw64(H1POLY, cp->h1_init); 5048 nw64(H2POLY, cp->h2_init); 5049 5050 err = niu_init_hostinfo(np); 5051 if (err) 5052 return err; 5053 5054 for (i = 0; i < ENET_VLAN_TBL_NUM_ENTRIES; i++) { 5055 struct niu_vlan_rdc *vp = &cp->vlan_mappings[i]; 5056 5057 vlan_tbl_write(np, i, np->port, 5058 vp->vlan_pref, vp->rdc_num); 5059 } 5060 5061 for (i = 0; i < cp->num_alt_mac_mappings; i++) { 5062 struct niu_altmac_rdc *ap = &cp->alt_mac_mappings[i]; 5063 5064 err = niu_set_alt_mac_rdc_table(np, ap->alt_mac_num, 5065 ap->rdc_num, ap->mac_pref); 5066 if (err) 5067 return err; 5068 } 5069 5070 for (i = CLASS_CODE_USER_PROG1; i <= CLASS_CODE_SCTP_IPV6; i++) { 5071 int index = i - CLASS_CODE_USER_PROG1; 5072 5073 err = niu_set_tcam_key(np, i, parent->tcam_key[index]); 5074 if (err) 5075 return err; 5076 err = niu_set_flow_key(np, i, parent->flow_key[index]); 5077 if (err) 5078 return err; 5079 } 5080 5081 err = niu_set_ip_frag_rule(np); 5082 if (err) 5083 return err; 5084 5085 tcam_enable(np, 1); 5086 5087 return 0; 5088 } 5089 5090 static int niu_zcp_write(struct niu *np, int index, u64 *data) 5091 { 5092 nw64(ZCP_RAM_DATA0, data[0]); 5093 nw64(ZCP_RAM_DATA1, data[1]); 5094 nw64(ZCP_RAM_DATA2, data[2]); 5095 nw64(ZCP_RAM_DATA3, data[3]); 5096 nw64(ZCP_RAM_DATA4, data[4]); 5097 nw64(ZCP_RAM_BE, ZCP_RAM_BE_VAL); 5098 nw64(ZCP_RAM_ACC, 5099 (ZCP_RAM_ACC_WRITE | 5100 (0 << ZCP_RAM_ACC_ZFCID_SHIFT) | 5101 (ZCP_RAM_SEL_CFIFO(np->port) << ZCP_RAM_ACC_RAM_SEL_SHIFT))); 5102 5103 return niu_wait_bits_clear(np, ZCP_RAM_ACC, ZCP_RAM_ACC_BUSY, 5104 1000, 100); 5105 } 5106 5107 static int niu_zcp_read(struct niu *np, int index, u64 *data) 5108 { 5109 int err; 5110 5111 err = niu_wait_bits_clear(np, ZCP_RAM_ACC, ZCP_RAM_ACC_BUSY, 5112 1000, 100); 5113 if (err) { 5114 netdev_err(np->dev, "ZCP read busy won't clear, ZCP_RAM_ACC[%llx]\n", 5115 (unsigned long long)nr64(ZCP_RAM_ACC)); 5116 return err; 5117 } 5118 5119 nw64(ZCP_RAM_ACC, 5120 (ZCP_RAM_ACC_READ | 5121 (0 << ZCP_RAM_ACC_ZFCID_SHIFT) | 5122 (ZCP_RAM_SEL_CFIFO(np->port) << ZCP_RAM_ACC_RAM_SEL_SHIFT))); 5123 5124 err = niu_wait_bits_clear(np, ZCP_RAM_ACC, ZCP_RAM_ACC_BUSY, 5125 1000, 100); 5126 if (err) { 5127 netdev_err(np->dev, "ZCP read busy2 won't clear, ZCP_RAM_ACC[%llx]\n", 5128 (unsigned long long)nr64(ZCP_RAM_ACC)); 5129 return err; 5130 } 5131 5132 data[0] = nr64(ZCP_RAM_DATA0); 5133 data[1] = nr64(ZCP_RAM_DATA1); 5134 data[2] = nr64(ZCP_RAM_DATA2); 5135 data[3] = nr64(ZCP_RAM_DATA3); 5136 data[4] = nr64(ZCP_RAM_DATA4); 5137 5138 return 0; 5139 } 5140 5141 static void niu_zcp_cfifo_reset(struct niu *np) 5142 { 5143 u64 val = nr64(RESET_CFIFO); 5144 5145 val |= RESET_CFIFO_RST(np->port); 5146 nw64(RESET_CFIFO, val); 5147 udelay(10); 5148 5149 val &= ~RESET_CFIFO_RST(np->port); 5150 nw64(RESET_CFIFO, val); 5151 } 5152 5153 static int niu_init_zcp(struct niu *np) 5154 { 5155 u64 data[5], rbuf[5]; 5156 int i, max, err; 5157 5158 if (np->parent->plat_type != PLAT_TYPE_NIU) { 5159 if (np->port == 0 || np->port == 1) 5160 max = ATLAS_P0_P1_CFIFO_ENTRIES; 5161 else 5162 max = ATLAS_P2_P3_CFIFO_ENTRIES; 5163 } else 5164 max = NIU_CFIFO_ENTRIES; 5165 5166 data[0] = 0; 5167 data[1] = 0; 5168 data[2] = 0; 5169 data[3] = 0; 5170 data[4] = 0; 5171 5172 for (i = 0; i < max; i++) { 5173 err = niu_zcp_write(np, i, data); 5174 if (err) 5175 return err; 5176 err = niu_zcp_read(np, i, rbuf); 5177 if (err) 5178 return err; 5179 } 5180 5181 niu_zcp_cfifo_reset(np); 5182 nw64(CFIFO_ECC(np->port), 0); 5183 nw64(ZCP_INT_STAT, ZCP_INT_STAT_ALL); 5184 (void) nr64(ZCP_INT_STAT); 5185 nw64(ZCP_INT_MASK, ZCP_INT_MASK_ALL); 5186 5187 return 0; 5188 } 5189 5190 static void niu_ipp_write(struct niu *np, int index, u64 *data) 5191 { 5192 u64 val = nr64_ipp(IPP_CFIG); 5193 5194 nw64_ipp(IPP_CFIG, val | IPP_CFIG_DFIFO_PIO_W); 5195 nw64_ipp(IPP_DFIFO_WR_PTR, index); 5196 nw64_ipp(IPP_DFIFO_WR0, data[0]); 5197 nw64_ipp(IPP_DFIFO_WR1, data[1]); 5198 nw64_ipp(IPP_DFIFO_WR2, data[2]); 5199 nw64_ipp(IPP_DFIFO_WR3, data[3]); 5200 nw64_ipp(IPP_DFIFO_WR4, data[4]); 5201 nw64_ipp(IPP_CFIG, val & ~IPP_CFIG_DFIFO_PIO_W); 5202 } 5203 5204 static void niu_ipp_read(struct niu *np, int index, u64 *data) 5205 { 5206 nw64_ipp(IPP_DFIFO_RD_PTR, index); 5207 data[0] = nr64_ipp(IPP_DFIFO_RD0); 5208 data[1] = nr64_ipp(IPP_DFIFO_RD1); 5209 data[2] = nr64_ipp(IPP_DFIFO_RD2); 5210 data[3] = nr64_ipp(IPP_DFIFO_RD3); 5211 data[4] = nr64_ipp(IPP_DFIFO_RD4); 5212 } 5213 5214 static int niu_ipp_reset(struct niu *np) 5215 { 5216 return niu_set_and_wait_clear_ipp(np, IPP_CFIG, IPP_CFIG_SOFT_RST, 5217 1000, 100, "IPP_CFIG"); 5218 } 5219 5220 static int niu_init_ipp(struct niu *np) 5221 { 5222 u64 data[5], rbuf[5], val; 5223 int i, max, err; 5224 5225 if (np->parent->plat_type != PLAT_TYPE_NIU) { 5226 if (np->port == 0 || np->port == 1) 5227 max = ATLAS_P0_P1_DFIFO_ENTRIES; 5228 else 5229 max = ATLAS_P2_P3_DFIFO_ENTRIES; 5230 } else 5231 max = NIU_DFIFO_ENTRIES; 5232 5233 data[0] = 0; 5234 data[1] = 0; 5235 data[2] = 0; 5236 data[3] = 0; 5237 data[4] = 0; 5238 5239 for (i = 0; i < max; i++) { 5240 niu_ipp_write(np, i, data); 5241 niu_ipp_read(np, i, rbuf); 5242 } 5243 5244 (void) nr64_ipp(IPP_INT_STAT); 5245 (void) nr64_ipp(IPP_INT_STAT); 5246 5247 err = niu_ipp_reset(np); 5248 if (err) 5249 return err; 5250 5251 (void) nr64_ipp(IPP_PKT_DIS); 5252 (void) nr64_ipp(IPP_BAD_CS_CNT); 5253 (void) nr64_ipp(IPP_ECC); 5254 5255 (void) nr64_ipp(IPP_INT_STAT); 5256 5257 nw64_ipp(IPP_MSK, ~IPP_MSK_ALL); 5258 5259 val = nr64_ipp(IPP_CFIG); 5260 val &= ~IPP_CFIG_IP_MAX_PKT; 5261 val |= (IPP_CFIG_IPP_ENABLE | 5262 IPP_CFIG_DFIFO_ECC_EN | 5263 IPP_CFIG_DROP_BAD_CRC | 5264 IPP_CFIG_CKSUM_EN | 5265 (0x1ffff << IPP_CFIG_IP_MAX_PKT_SHIFT)); 5266 nw64_ipp(IPP_CFIG, val); 5267 5268 return 0; 5269 } 5270 5271 static void niu_handle_led(struct niu *np, int status) 5272 { 5273 u64 val; 5274 val = nr64_mac(XMAC_CONFIG); 5275 5276 if ((np->flags & NIU_FLAGS_10G) != 0 && 5277 (np->flags & NIU_FLAGS_FIBER) != 0) { 5278 if (status) { 5279 val |= XMAC_CONFIG_LED_POLARITY; 5280 val &= ~XMAC_CONFIG_FORCE_LED_ON; 5281 } else { 5282 val |= XMAC_CONFIG_FORCE_LED_ON; 5283 val &= ~XMAC_CONFIG_LED_POLARITY; 5284 } 5285 } 5286 5287 nw64_mac(XMAC_CONFIG, val); 5288 } 5289 5290 static void niu_init_xif_xmac(struct niu *np) 5291 { 5292 struct niu_link_config *lp = &np->link_config; 5293 u64 val; 5294 5295 if (np->flags & NIU_FLAGS_XCVR_SERDES) { 5296 val = nr64(MIF_CONFIG); 5297 val |= MIF_CONFIG_ATCA_GE; 5298 nw64(MIF_CONFIG, val); 5299 } 5300 5301 val = nr64_mac(XMAC_CONFIG); 5302 val &= ~XMAC_CONFIG_SEL_POR_CLK_SRC; 5303 5304 val |= XMAC_CONFIG_TX_OUTPUT_EN; 5305 5306 if (lp->loopback_mode == LOOPBACK_MAC) { 5307 val &= ~XMAC_CONFIG_SEL_POR_CLK_SRC; 5308 val |= XMAC_CONFIG_LOOPBACK; 5309 } else { 5310 val &= ~XMAC_CONFIG_LOOPBACK; 5311 } 5312 5313 if (np->flags & NIU_FLAGS_10G) { 5314 val &= ~XMAC_CONFIG_LFS_DISABLE; 5315 } else { 5316 val |= XMAC_CONFIG_LFS_DISABLE; 5317 if (!(np->flags & NIU_FLAGS_FIBER) && 5318 !(np->flags & NIU_FLAGS_XCVR_SERDES)) 5319 val |= XMAC_CONFIG_1G_PCS_BYPASS; 5320 else 5321 val &= ~XMAC_CONFIG_1G_PCS_BYPASS; 5322 } 5323 5324 val &= ~XMAC_CONFIG_10G_XPCS_BYPASS; 5325 5326 if (lp->active_speed == SPEED_100) 5327 val |= XMAC_CONFIG_SEL_CLK_25MHZ; 5328 else 5329 val &= ~XMAC_CONFIG_SEL_CLK_25MHZ; 5330 5331 nw64_mac(XMAC_CONFIG, val); 5332 5333 val = nr64_mac(XMAC_CONFIG); 5334 val &= ~XMAC_CONFIG_MODE_MASK; 5335 if (np->flags & NIU_FLAGS_10G) { 5336 val |= XMAC_CONFIG_MODE_XGMII; 5337 } else { 5338 if (lp->active_speed == SPEED_1000) 5339 val |= XMAC_CONFIG_MODE_GMII; 5340 else 5341 val |= XMAC_CONFIG_MODE_MII; 5342 } 5343 5344 nw64_mac(XMAC_CONFIG, val); 5345 } 5346 5347 static void niu_init_xif_bmac(struct niu *np) 5348 { 5349 struct niu_link_config *lp = &np->link_config; 5350 u64 val; 5351 5352 val = BMAC_XIF_CONFIG_TX_OUTPUT_EN; 5353 5354 if (lp->loopback_mode == LOOPBACK_MAC) 5355 val |= BMAC_XIF_CONFIG_MII_LOOPBACK; 5356 else 5357 val &= ~BMAC_XIF_CONFIG_MII_LOOPBACK; 5358 5359 if (lp->active_speed == SPEED_1000) 5360 val |= BMAC_XIF_CONFIG_GMII_MODE; 5361 else 5362 val &= ~BMAC_XIF_CONFIG_GMII_MODE; 5363 5364 val &= ~(BMAC_XIF_CONFIG_LINK_LED | 5365 BMAC_XIF_CONFIG_LED_POLARITY); 5366 5367 if (!(np->flags & NIU_FLAGS_10G) && 5368 !(np->flags & NIU_FLAGS_FIBER) && 5369 lp->active_speed == SPEED_100) 5370 val |= BMAC_XIF_CONFIG_25MHZ_CLOCK; 5371 else 5372 val &= ~BMAC_XIF_CONFIG_25MHZ_CLOCK; 5373 5374 nw64_mac(BMAC_XIF_CONFIG, val); 5375 } 5376 5377 static void niu_init_xif(struct niu *np) 5378 { 5379 if (np->flags & NIU_FLAGS_XMAC) 5380 niu_init_xif_xmac(np); 5381 else 5382 niu_init_xif_bmac(np); 5383 } 5384 5385 static void niu_pcs_mii_reset(struct niu *np) 5386 { 5387 int limit = 1000; 5388 u64 val = nr64_pcs(PCS_MII_CTL); 5389 val |= PCS_MII_CTL_RST; 5390 nw64_pcs(PCS_MII_CTL, val); 5391 while ((--limit >= 0) && (val & PCS_MII_CTL_RST)) { 5392 udelay(100); 5393 val = nr64_pcs(PCS_MII_CTL); 5394 } 5395 } 5396 5397 static void niu_xpcs_reset(struct niu *np) 5398 { 5399 int limit = 1000; 5400 u64 val = nr64_xpcs(XPCS_CONTROL1); 5401 val |= XPCS_CONTROL1_RESET; 5402 nw64_xpcs(XPCS_CONTROL1, val); 5403 while ((--limit >= 0) && (val & XPCS_CONTROL1_RESET)) { 5404 udelay(100); 5405 val = nr64_xpcs(XPCS_CONTROL1); 5406 } 5407 } 5408 5409 static int niu_init_pcs(struct niu *np) 5410 { 5411 struct niu_link_config *lp = &np->link_config; 5412 u64 val; 5413 5414 switch (np->flags & (NIU_FLAGS_10G | 5415 NIU_FLAGS_FIBER | 5416 NIU_FLAGS_XCVR_SERDES)) { 5417 case NIU_FLAGS_FIBER: 5418 /* 1G fiber */ 5419 nw64_pcs(PCS_CONF, PCS_CONF_MASK | PCS_CONF_ENABLE); 5420 nw64_pcs(PCS_DPATH_MODE, 0); 5421 niu_pcs_mii_reset(np); 5422 break; 5423 5424 case NIU_FLAGS_10G: 5425 case NIU_FLAGS_10G | NIU_FLAGS_FIBER: 5426 case NIU_FLAGS_10G | NIU_FLAGS_XCVR_SERDES: 5427 /* 10G SERDES */ 5428 if (!(np->flags & NIU_FLAGS_XMAC)) 5429 return -EINVAL; 5430 5431 /* 10G copper or fiber */ 5432 val = nr64_mac(XMAC_CONFIG); 5433 val &= ~XMAC_CONFIG_10G_XPCS_BYPASS; 5434 nw64_mac(XMAC_CONFIG, val); 5435 5436 niu_xpcs_reset(np); 5437 5438 val = nr64_xpcs(XPCS_CONTROL1); 5439 if (lp->loopback_mode == LOOPBACK_PHY) 5440 val |= XPCS_CONTROL1_LOOPBACK; 5441 else 5442 val &= ~XPCS_CONTROL1_LOOPBACK; 5443 nw64_xpcs(XPCS_CONTROL1, val); 5444 5445 nw64_xpcs(XPCS_DESKEW_ERR_CNT, 0); 5446 (void) nr64_xpcs(XPCS_SYMERR_CNT01); 5447 (void) nr64_xpcs(XPCS_SYMERR_CNT23); 5448 break; 5449 5450 5451 case NIU_FLAGS_XCVR_SERDES: 5452 /* 1G SERDES */ 5453 niu_pcs_mii_reset(np); 5454 nw64_pcs(PCS_CONF, PCS_CONF_MASK | PCS_CONF_ENABLE); 5455 nw64_pcs(PCS_DPATH_MODE, 0); 5456 break; 5457 5458 case 0: 5459 /* 1G copper */ 5460 case NIU_FLAGS_XCVR_SERDES | NIU_FLAGS_FIBER: 5461 /* 1G RGMII FIBER */ 5462 nw64_pcs(PCS_DPATH_MODE, PCS_DPATH_MODE_MII); 5463 niu_pcs_mii_reset(np); 5464 break; 5465 5466 default: 5467 return -EINVAL; 5468 } 5469 5470 return 0; 5471 } 5472 5473 static int niu_reset_tx_xmac(struct niu *np) 5474 { 5475 return niu_set_and_wait_clear_mac(np, XTXMAC_SW_RST, 5476 (XTXMAC_SW_RST_REG_RS | 5477 XTXMAC_SW_RST_SOFT_RST), 5478 1000, 100, "XTXMAC_SW_RST"); 5479 } 5480 5481 static int niu_reset_tx_bmac(struct niu *np) 5482 { 5483 int limit; 5484 5485 nw64_mac(BTXMAC_SW_RST, BTXMAC_SW_RST_RESET); 5486 limit = 1000; 5487 while (--limit >= 0) { 5488 if (!(nr64_mac(BTXMAC_SW_RST) & BTXMAC_SW_RST_RESET)) 5489 break; 5490 udelay(100); 5491 } 5492 if (limit < 0) { 5493 dev_err(np->device, "Port %u TX BMAC would not reset, BTXMAC_SW_RST[%llx]\n", 5494 np->port, 5495 (unsigned long long) nr64_mac(BTXMAC_SW_RST)); 5496 return -ENODEV; 5497 } 5498 5499 return 0; 5500 } 5501 5502 static int niu_reset_tx_mac(struct niu *np) 5503 { 5504 if (np->flags & NIU_FLAGS_XMAC) 5505 return niu_reset_tx_xmac(np); 5506 else 5507 return niu_reset_tx_bmac(np); 5508 } 5509 5510 static void niu_init_tx_xmac(struct niu *np, u64 min, u64 max) 5511 { 5512 u64 val; 5513 5514 val = nr64_mac(XMAC_MIN); 5515 val &= ~(XMAC_MIN_TX_MIN_PKT_SIZE | 5516 XMAC_MIN_RX_MIN_PKT_SIZE); 5517 val |= (min << XMAC_MIN_RX_MIN_PKT_SIZE_SHFT); 5518 val |= (min << XMAC_MIN_TX_MIN_PKT_SIZE_SHFT); 5519 nw64_mac(XMAC_MIN, val); 5520 5521 nw64_mac(XMAC_MAX, max); 5522 5523 nw64_mac(XTXMAC_STAT_MSK, ~(u64)0); 5524 5525 val = nr64_mac(XMAC_IPG); 5526 if (np->flags & NIU_FLAGS_10G) { 5527 val &= ~XMAC_IPG_IPG_XGMII; 5528 val |= (IPG_12_15_XGMII << XMAC_IPG_IPG_XGMII_SHIFT); 5529 } else { 5530 val &= ~XMAC_IPG_IPG_MII_GMII; 5531 val |= (IPG_12_MII_GMII << XMAC_IPG_IPG_MII_GMII_SHIFT); 5532 } 5533 nw64_mac(XMAC_IPG, val); 5534 5535 val = nr64_mac(XMAC_CONFIG); 5536 val &= ~(XMAC_CONFIG_ALWAYS_NO_CRC | 5537 XMAC_CONFIG_STRETCH_MODE | 5538 XMAC_CONFIG_VAR_MIN_IPG_EN | 5539 XMAC_CONFIG_TX_ENABLE); 5540 nw64_mac(XMAC_CONFIG, val); 5541 5542 nw64_mac(TXMAC_FRM_CNT, 0); 5543 nw64_mac(TXMAC_BYTE_CNT, 0); 5544 } 5545 5546 static void niu_init_tx_bmac(struct niu *np, u64 min, u64 max) 5547 { 5548 u64 val; 5549 5550 nw64_mac(BMAC_MIN_FRAME, min); 5551 nw64_mac(BMAC_MAX_FRAME, max); 5552 5553 nw64_mac(BTXMAC_STATUS_MASK, ~(u64)0); 5554 nw64_mac(BMAC_CTRL_TYPE, 0x8808); 5555 nw64_mac(BMAC_PREAMBLE_SIZE, 7); 5556 5557 val = nr64_mac(BTXMAC_CONFIG); 5558 val &= ~(BTXMAC_CONFIG_FCS_DISABLE | 5559 BTXMAC_CONFIG_ENABLE); 5560 nw64_mac(BTXMAC_CONFIG, val); 5561 } 5562 5563 static void niu_init_tx_mac(struct niu *np) 5564 { 5565 u64 min, max; 5566 5567 min = 64; 5568 if (np->dev->mtu > ETH_DATA_LEN) 5569 max = 9216; 5570 else 5571 max = 1522; 5572 5573 /* The XMAC_MIN register only accepts values for TX min which 5574 * have the low 3 bits cleared. 5575 */ 5576 BUG_ON(min & 0x7); 5577 5578 if (np->flags & NIU_FLAGS_XMAC) 5579 niu_init_tx_xmac(np, min, max); 5580 else 5581 niu_init_tx_bmac(np, min, max); 5582 } 5583 5584 static int niu_reset_rx_xmac(struct niu *np) 5585 { 5586 int limit; 5587 5588 nw64_mac(XRXMAC_SW_RST, 5589 XRXMAC_SW_RST_REG_RS | XRXMAC_SW_RST_SOFT_RST); 5590 limit = 1000; 5591 while (--limit >= 0) { 5592 if (!(nr64_mac(XRXMAC_SW_RST) & (XRXMAC_SW_RST_REG_RS | 5593 XRXMAC_SW_RST_SOFT_RST))) 5594 break; 5595 udelay(100); 5596 } 5597 if (limit < 0) { 5598 dev_err(np->device, "Port %u RX XMAC would not reset, XRXMAC_SW_RST[%llx]\n", 5599 np->port, 5600 (unsigned long long) nr64_mac(XRXMAC_SW_RST)); 5601 return -ENODEV; 5602 } 5603 5604 return 0; 5605 } 5606 5607 static int niu_reset_rx_bmac(struct niu *np) 5608 { 5609 int limit; 5610 5611 nw64_mac(BRXMAC_SW_RST, BRXMAC_SW_RST_RESET); 5612 limit = 1000; 5613 while (--limit >= 0) { 5614 if (!(nr64_mac(BRXMAC_SW_RST) & BRXMAC_SW_RST_RESET)) 5615 break; 5616 udelay(100); 5617 } 5618 if (limit < 0) { 5619 dev_err(np->device, "Port %u RX BMAC would not reset, BRXMAC_SW_RST[%llx]\n", 5620 np->port, 5621 (unsigned long long) nr64_mac(BRXMAC_SW_RST)); 5622 return -ENODEV; 5623 } 5624 5625 return 0; 5626 } 5627 5628 static int niu_reset_rx_mac(struct niu *np) 5629 { 5630 if (np->flags & NIU_FLAGS_XMAC) 5631 return niu_reset_rx_xmac(np); 5632 else 5633 return niu_reset_rx_bmac(np); 5634 } 5635 5636 static void niu_init_rx_xmac(struct niu *np) 5637 { 5638 struct niu_parent *parent = np->parent; 5639 struct niu_rdc_tables *tp = &parent->rdc_group_cfg[np->port]; 5640 int first_rdc_table = tp->first_table_num; 5641 unsigned long i; 5642 u64 val; 5643 5644 nw64_mac(XMAC_ADD_FILT0, 0); 5645 nw64_mac(XMAC_ADD_FILT1, 0); 5646 nw64_mac(XMAC_ADD_FILT2, 0); 5647 nw64_mac(XMAC_ADD_FILT12_MASK, 0); 5648 nw64_mac(XMAC_ADD_FILT00_MASK, 0); 5649 for (i = 0; i < MAC_NUM_HASH; i++) 5650 nw64_mac(XMAC_HASH_TBL(i), 0); 5651 nw64_mac(XRXMAC_STAT_MSK, ~(u64)0); 5652 niu_set_primary_mac_rdc_table(np, first_rdc_table, 1); 5653 niu_set_multicast_mac_rdc_table(np, first_rdc_table, 1); 5654 5655 val = nr64_mac(XMAC_CONFIG); 5656 val &= ~(XMAC_CONFIG_RX_MAC_ENABLE | 5657 XMAC_CONFIG_PROMISCUOUS | 5658 XMAC_CONFIG_PROMISC_GROUP | 5659 XMAC_CONFIG_ERR_CHK_DIS | 5660 XMAC_CONFIG_RX_CRC_CHK_DIS | 5661 XMAC_CONFIG_RESERVED_MULTICAST | 5662 XMAC_CONFIG_RX_CODEV_CHK_DIS | 5663 XMAC_CONFIG_ADDR_FILTER_EN | 5664 XMAC_CONFIG_RCV_PAUSE_ENABLE | 5665 XMAC_CONFIG_STRIP_CRC | 5666 XMAC_CONFIG_PASS_FLOW_CTRL | 5667 XMAC_CONFIG_MAC2IPP_PKT_CNT_EN); 5668 val |= (XMAC_CONFIG_HASH_FILTER_EN); 5669 nw64_mac(XMAC_CONFIG, val); 5670 5671 nw64_mac(RXMAC_BT_CNT, 0); 5672 nw64_mac(RXMAC_BC_FRM_CNT, 0); 5673 nw64_mac(RXMAC_MC_FRM_CNT, 0); 5674 nw64_mac(RXMAC_FRAG_CNT, 0); 5675 nw64_mac(RXMAC_HIST_CNT1, 0); 5676 nw64_mac(RXMAC_HIST_CNT2, 0); 5677 nw64_mac(RXMAC_HIST_CNT3, 0); 5678 nw64_mac(RXMAC_HIST_CNT4, 0); 5679 nw64_mac(RXMAC_HIST_CNT5, 0); 5680 nw64_mac(RXMAC_HIST_CNT6, 0); 5681 nw64_mac(RXMAC_HIST_CNT7, 0); 5682 nw64_mac(RXMAC_MPSZER_CNT, 0); 5683 nw64_mac(RXMAC_CRC_ER_CNT, 0); 5684 nw64_mac(RXMAC_CD_VIO_CNT, 0); 5685 nw64_mac(LINK_FAULT_CNT, 0); 5686 } 5687 5688 static void niu_init_rx_bmac(struct niu *np) 5689 { 5690 struct niu_parent *parent = np->parent; 5691 struct niu_rdc_tables *tp = &parent->rdc_group_cfg[np->port]; 5692 int first_rdc_table = tp->first_table_num; 5693 unsigned long i; 5694 u64 val; 5695 5696 nw64_mac(BMAC_ADD_FILT0, 0); 5697 nw64_mac(BMAC_ADD_FILT1, 0); 5698 nw64_mac(BMAC_ADD_FILT2, 0); 5699 nw64_mac(BMAC_ADD_FILT12_MASK, 0); 5700 nw64_mac(BMAC_ADD_FILT00_MASK, 0); 5701 for (i = 0; i < MAC_NUM_HASH; i++) 5702 nw64_mac(BMAC_HASH_TBL(i), 0); 5703 niu_set_primary_mac_rdc_table(np, first_rdc_table, 1); 5704 niu_set_multicast_mac_rdc_table(np, first_rdc_table, 1); 5705 nw64_mac(BRXMAC_STATUS_MASK, ~(u64)0); 5706 5707 val = nr64_mac(BRXMAC_CONFIG); 5708 val &= ~(BRXMAC_CONFIG_ENABLE | 5709 BRXMAC_CONFIG_STRIP_PAD | 5710 BRXMAC_CONFIG_STRIP_FCS | 5711 BRXMAC_CONFIG_PROMISC | 5712 BRXMAC_CONFIG_PROMISC_GRP | 5713 BRXMAC_CONFIG_ADDR_FILT_EN | 5714 BRXMAC_CONFIG_DISCARD_DIS); 5715 val |= (BRXMAC_CONFIG_HASH_FILT_EN); 5716 nw64_mac(BRXMAC_CONFIG, val); 5717 5718 val = nr64_mac(BMAC_ADDR_CMPEN); 5719 val |= BMAC_ADDR_CMPEN_EN0; 5720 nw64_mac(BMAC_ADDR_CMPEN, val); 5721 } 5722 5723 static void niu_init_rx_mac(struct niu *np) 5724 { 5725 niu_set_primary_mac(np, np->dev->dev_addr); 5726 5727 if (np->flags & NIU_FLAGS_XMAC) 5728 niu_init_rx_xmac(np); 5729 else 5730 niu_init_rx_bmac(np); 5731 } 5732 5733 static void niu_enable_tx_xmac(struct niu *np, int on) 5734 { 5735 u64 val = nr64_mac(XMAC_CONFIG); 5736 5737 if (on) 5738 val |= XMAC_CONFIG_TX_ENABLE; 5739 else 5740 val &= ~XMAC_CONFIG_TX_ENABLE; 5741 nw64_mac(XMAC_CONFIG, val); 5742 } 5743 5744 static void niu_enable_tx_bmac(struct niu *np, int on) 5745 { 5746 u64 val = nr64_mac(BTXMAC_CONFIG); 5747 5748 if (on) 5749 val |= BTXMAC_CONFIG_ENABLE; 5750 else 5751 val &= ~BTXMAC_CONFIG_ENABLE; 5752 nw64_mac(BTXMAC_CONFIG, val); 5753 } 5754 5755 static void niu_enable_tx_mac(struct niu *np, int on) 5756 { 5757 if (np->flags & NIU_FLAGS_XMAC) 5758 niu_enable_tx_xmac(np, on); 5759 else 5760 niu_enable_tx_bmac(np, on); 5761 } 5762 5763 static void niu_enable_rx_xmac(struct niu *np, int on) 5764 { 5765 u64 val = nr64_mac(XMAC_CONFIG); 5766 5767 val &= ~(XMAC_CONFIG_HASH_FILTER_EN | 5768 XMAC_CONFIG_PROMISCUOUS); 5769 5770 if (np->flags & NIU_FLAGS_MCAST) 5771 val |= XMAC_CONFIG_HASH_FILTER_EN; 5772 if (np->flags & NIU_FLAGS_PROMISC) 5773 val |= XMAC_CONFIG_PROMISCUOUS; 5774 5775 if (on) 5776 val |= XMAC_CONFIG_RX_MAC_ENABLE; 5777 else 5778 val &= ~XMAC_CONFIG_RX_MAC_ENABLE; 5779 nw64_mac(XMAC_CONFIG, val); 5780 } 5781 5782 static void niu_enable_rx_bmac(struct niu *np, int on) 5783 { 5784 u64 val = nr64_mac(BRXMAC_CONFIG); 5785 5786 val &= ~(BRXMAC_CONFIG_HASH_FILT_EN | 5787 BRXMAC_CONFIG_PROMISC); 5788 5789 if (np->flags & NIU_FLAGS_MCAST) 5790 val |= BRXMAC_CONFIG_HASH_FILT_EN; 5791 if (np->flags & NIU_FLAGS_PROMISC) 5792 val |= BRXMAC_CONFIG_PROMISC; 5793 5794 if (on) 5795 val |= BRXMAC_CONFIG_ENABLE; 5796 else 5797 val &= ~BRXMAC_CONFIG_ENABLE; 5798 nw64_mac(BRXMAC_CONFIG, val); 5799 } 5800 5801 static void niu_enable_rx_mac(struct niu *np, int on) 5802 { 5803 if (np->flags & NIU_FLAGS_XMAC) 5804 niu_enable_rx_xmac(np, on); 5805 else 5806 niu_enable_rx_bmac(np, on); 5807 } 5808 5809 static int niu_init_mac(struct niu *np) 5810 { 5811 int err; 5812 5813 niu_init_xif(np); 5814 err = niu_init_pcs(np); 5815 if (err) 5816 return err; 5817 5818 err = niu_reset_tx_mac(np); 5819 if (err) 5820 return err; 5821 niu_init_tx_mac(np); 5822 err = niu_reset_rx_mac(np); 5823 if (err) 5824 return err; 5825 niu_init_rx_mac(np); 5826 5827 /* This looks hookey but the RX MAC reset we just did will 5828 * undo some of the state we setup in niu_init_tx_mac() so we 5829 * have to call it again. In particular, the RX MAC reset will 5830 * set the XMAC_MAX register back to it's default value. 5831 */ 5832 niu_init_tx_mac(np); 5833 niu_enable_tx_mac(np, 1); 5834 5835 niu_enable_rx_mac(np, 1); 5836 5837 return 0; 5838 } 5839 5840 static void niu_stop_one_tx_channel(struct niu *np, struct tx_ring_info *rp) 5841 { 5842 (void) niu_tx_channel_stop(np, rp->tx_channel); 5843 } 5844 5845 static void niu_stop_tx_channels(struct niu *np) 5846 { 5847 int i; 5848 5849 for (i = 0; i < np->num_tx_rings; i++) { 5850 struct tx_ring_info *rp = &np->tx_rings[i]; 5851 5852 niu_stop_one_tx_channel(np, rp); 5853 } 5854 } 5855 5856 static void niu_reset_one_tx_channel(struct niu *np, struct tx_ring_info *rp) 5857 { 5858 (void) niu_tx_channel_reset(np, rp->tx_channel); 5859 } 5860 5861 static void niu_reset_tx_channels(struct niu *np) 5862 { 5863 int i; 5864 5865 for (i = 0; i < np->num_tx_rings; i++) { 5866 struct tx_ring_info *rp = &np->tx_rings[i]; 5867 5868 niu_reset_one_tx_channel(np, rp); 5869 } 5870 } 5871 5872 static void niu_stop_one_rx_channel(struct niu *np, struct rx_ring_info *rp) 5873 { 5874 (void) niu_enable_rx_channel(np, rp->rx_channel, 0); 5875 } 5876 5877 static void niu_stop_rx_channels(struct niu *np) 5878 { 5879 int i; 5880 5881 for (i = 0; i < np->num_rx_rings; i++) { 5882 struct rx_ring_info *rp = &np->rx_rings[i]; 5883 5884 niu_stop_one_rx_channel(np, rp); 5885 } 5886 } 5887 5888 static void niu_reset_one_rx_channel(struct niu *np, struct rx_ring_info *rp) 5889 { 5890 int channel = rp->rx_channel; 5891 5892 (void) niu_rx_channel_reset(np, channel); 5893 nw64(RX_DMA_ENT_MSK(channel), RX_DMA_ENT_MSK_ALL); 5894 nw64(RX_DMA_CTL_STAT(channel), 0); 5895 (void) niu_enable_rx_channel(np, channel, 0); 5896 } 5897 5898 static void niu_reset_rx_channels(struct niu *np) 5899 { 5900 int i; 5901 5902 for (i = 0; i < np->num_rx_rings; i++) { 5903 struct rx_ring_info *rp = &np->rx_rings[i]; 5904 5905 niu_reset_one_rx_channel(np, rp); 5906 } 5907 } 5908 5909 static void niu_disable_ipp(struct niu *np) 5910 { 5911 u64 rd, wr, val; 5912 int limit; 5913 5914 rd = nr64_ipp(IPP_DFIFO_RD_PTR); 5915 wr = nr64_ipp(IPP_DFIFO_WR_PTR); 5916 limit = 100; 5917 while (--limit >= 0 && (rd != wr)) { 5918 rd = nr64_ipp(IPP_DFIFO_RD_PTR); 5919 wr = nr64_ipp(IPP_DFIFO_WR_PTR); 5920 } 5921 if (limit < 0 && 5922 (rd != 0 && wr != 1)) { 5923 netdev_err(np->dev, "IPP would not quiesce, rd_ptr[%llx] wr_ptr[%llx]\n", 5924 (unsigned long long)nr64_ipp(IPP_DFIFO_RD_PTR), 5925 (unsigned long long)nr64_ipp(IPP_DFIFO_WR_PTR)); 5926 } 5927 5928 val = nr64_ipp(IPP_CFIG); 5929 val &= ~(IPP_CFIG_IPP_ENABLE | 5930 IPP_CFIG_DFIFO_ECC_EN | 5931 IPP_CFIG_DROP_BAD_CRC | 5932 IPP_CFIG_CKSUM_EN); 5933 nw64_ipp(IPP_CFIG, val); 5934 5935 (void) niu_ipp_reset(np); 5936 } 5937 5938 static int niu_init_hw(struct niu *np) 5939 { 5940 int i, err; 5941 5942 netif_printk(np, ifup, KERN_DEBUG, np->dev, "Initialize TXC\n"); 5943 niu_txc_enable_port(np, 1); 5944 niu_txc_port_dma_enable(np, 1); 5945 niu_txc_set_imask(np, 0); 5946 5947 netif_printk(np, ifup, KERN_DEBUG, np->dev, "Initialize TX channels\n"); 5948 for (i = 0; i < np->num_tx_rings; i++) { 5949 struct tx_ring_info *rp = &np->tx_rings[i]; 5950 5951 err = niu_init_one_tx_channel(np, rp); 5952 if (err) 5953 return err; 5954 } 5955 5956 netif_printk(np, ifup, KERN_DEBUG, np->dev, "Initialize RX channels\n"); 5957 err = niu_init_rx_channels(np); 5958 if (err) 5959 goto out_uninit_tx_channels; 5960 5961 netif_printk(np, ifup, KERN_DEBUG, np->dev, "Initialize classifier\n"); 5962 err = niu_init_classifier_hw(np); 5963 if (err) 5964 goto out_uninit_rx_channels; 5965 5966 netif_printk(np, ifup, KERN_DEBUG, np->dev, "Initialize ZCP\n"); 5967 err = niu_init_zcp(np); 5968 if (err) 5969 goto out_uninit_rx_channels; 5970 5971 netif_printk(np, ifup, KERN_DEBUG, np->dev, "Initialize IPP\n"); 5972 err = niu_init_ipp(np); 5973 if (err) 5974 goto out_uninit_rx_channels; 5975 5976 netif_printk(np, ifup, KERN_DEBUG, np->dev, "Initialize MAC\n"); 5977 err = niu_init_mac(np); 5978 if (err) 5979 goto out_uninit_ipp; 5980 5981 return 0; 5982 5983 out_uninit_ipp: 5984 netif_printk(np, ifup, KERN_DEBUG, np->dev, "Uninit IPP\n"); 5985 niu_disable_ipp(np); 5986 5987 out_uninit_rx_channels: 5988 netif_printk(np, ifup, KERN_DEBUG, np->dev, "Uninit RX channels\n"); 5989 niu_stop_rx_channels(np); 5990 niu_reset_rx_channels(np); 5991 5992 out_uninit_tx_channels: 5993 netif_printk(np, ifup, KERN_DEBUG, np->dev, "Uninit TX channels\n"); 5994 niu_stop_tx_channels(np); 5995 niu_reset_tx_channels(np); 5996 5997 return err; 5998 } 5999 6000 static void niu_stop_hw(struct niu *np) 6001 { 6002 netif_printk(np, ifdown, KERN_DEBUG, np->dev, "Disable interrupts\n"); 6003 niu_enable_interrupts(np, 0); 6004 6005 netif_printk(np, ifdown, KERN_DEBUG, np->dev, "Disable RX MAC\n"); 6006 niu_enable_rx_mac(np, 0); 6007 6008 netif_printk(np, ifdown, KERN_DEBUG, np->dev, "Disable IPP\n"); 6009 niu_disable_ipp(np); 6010 6011 netif_printk(np, ifdown, KERN_DEBUG, np->dev, "Stop TX channels\n"); 6012 niu_stop_tx_channels(np); 6013 6014 netif_printk(np, ifdown, KERN_DEBUG, np->dev, "Stop RX channels\n"); 6015 niu_stop_rx_channels(np); 6016 6017 netif_printk(np, ifdown, KERN_DEBUG, np->dev, "Reset TX channels\n"); 6018 niu_reset_tx_channels(np); 6019 6020 netif_printk(np, ifdown, KERN_DEBUG, np->dev, "Reset RX channels\n"); 6021 niu_reset_rx_channels(np); 6022 } 6023 6024 static void niu_set_irq_name(struct niu *np) 6025 { 6026 int port = np->port; 6027 int i, j = 1; 6028 6029 sprintf(np->irq_name[0], "%s:MAC", np->dev->name); 6030 6031 if (port == 0) { 6032 sprintf(np->irq_name[1], "%s:MIF", np->dev->name); 6033 sprintf(np->irq_name[2], "%s:SYSERR", np->dev->name); 6034 j = 3; 6035 } 6036 6037 for (i = 0; i < np->num_ldg - j; i++) { 6038 if (i < np->num_rx_rings) 6039 sprintf(np->irq_name[i+j], "%s-rx-%d", 6040 np->dev->name, i); 6041 else if (i < np->num_tx_rings + np->num_rx_rings) 6042 sprintf(np->irq_name[i+j], "%s-tx-%d", np->dev->name, 6043 i - np->num_rx_rings); 6044 } 6045 } 6046 6047 static int niu_request_irq(struct niu *np) 6048 { 6049 int i, j, err; 6050 6051 niu_set_irq_name(np); 6052 6053 err = 0; 6054 for (i = 0; i < np->num_ldg; i++) { 6055 struct niu_ldg *lp = &np->ldg[i]; 6056 6057 err = request_irq(lp->irq, niu_interrupt, IRQF_SHARED, 6058 np->irq_name[i], lp); 6059 if (err) 6060 goto out_free_irqs; 6061 6062 } 6063 6064 return 0; 6065 6066 out_free_irqs: 6067 for (j = 0; j < i; j++) { 6068 struct niu_ldg *lp = &np->ldg[j]; 6069 6070 free_irq(lp->irq, lp); 6071 } 6072 return err; 6073 } 6074 6075 static void niu_free_irq(struct niu *np) 6076 { 6077 int i; 6078 6079 for (i = 0; i < np->num_ldg; i++) { 6080 struct niu_ldg *lp = &np->ldg[i]; 6081 6082 free_irq(lp->irq, lp); 6083 } 6084 } 6085 6086 static void niu_enable_napi(struct niu *np) 6087 { 6088 int i; 6089 6090 for (i = 0; i < np->num_ldg; i++) 6091 napi_enable(&np->ldg[i].napi); 6092 } 6093 6094 static void niu_disable_napi(struct niu *np) 6095 { 6096 int i; 6097 6098 for (i = 0; i < np->num_ldg; i++) 6099 napi_disable(&np->ldg[i].napi); 6100 } 6101 6102 static int niu_open(struct net_device *dev) 6103 { 6104 struct niu *np = netdev_priv(dev); 6105 int err; 6106 6107 netif_carrier_off(dev); 6108 6109 err = niu_alloc_channels(np); 6110 if (err) 6111 goto out_err; 6112 6113 err = niu_enable_interrupts(np, 0); 6114 if (err) 6115 goto out_free_channels; 6116 6117 err = niu_request_irq(np); 6118 if (err) 6119 goto out_free_channels; 6120 6121 niu_enable_napi(np); 6122 6123 spin_lock_irq(&np->lock); 6124 6125 err = niu_init_hw(np); 6126 if (!err) { 6127 init_timer(&np->timer); 6128 np->timer.expires = jiffies + HZ; 6129 np->timer.data = (unsigned long) np; 6130 np->timer.function = niu_timer; 6131 6132 err = niu_enable_interrupts(np, 1); 6133 if (err) 6134 niu_stop_hw(np); 6135 } 6136 6137 spin_unlock_irq(&np->lock); 6138 6139 if (err) { 6140 niu_disable_napi(np); 6141 goto out_free_irq; 6142 } 6143 6144 netif_tx_start_all_queues(dev); 6145 6146 if (np->link_config.loopback_mode != LOOPBACK_DISABLED) 6147 netif_carrier_on(dev); 6148 6149 add_timer(&np->timer); 6150 6151 return 0; 6152 6153 out_free_irq: 6154 niu_free_irq(np); 6155 6156 out_free_channels: 6157 niu_free_channels(np); 6158 6159 out_err: 6160 return err; 6161 } 6162 6163 static void niu_full_shutdown(struct niu *np, struct net_device *dev) 6164 { 6165 cancel_work_sync(&np->reset_task); 6166 6167 niu_disable_napi(np); 6168 netif_tx_stop_all_queues(dev); 6169 6170 del_timer_sync(&np->timer); 6171 6172 spin_lock_irq(&np->lock); 6173 6174 niu_stop_hw(np); 6175 6176 spin_unlock_irq(&np->lock); 6177 } 6178 6179 static int niu_close(struct net_device *dev) 6180 { 6181 struct niu *np = netdev_priv(dev); 6182 6183 niu_full_shutdown(np, dev); 6184 6185 niu_free_irq(np); 6186 6187 niu_free_channels(np); 6188 6189 niu_handle_led(np, 0); 6190 6191 return 0; 6192 } 6193 6194 static void niu_sync_xmac_stats(struct niu *np) 6195 { 6196 struct niu_xmac_stats *mp = &np->mac_stats.xmac; 6197 6198 mp->tx_frames += nr64_mac(TXMAC_FRM_CNT); 6199 mp->tx_bytes += nr64_mac(TXMAC_BYTE_CNT); 6200 6201 mp->rx_link_faults += nr64_mac(LINK_FAULT_CNT); 6202 mp->rx_align_errors += nr64_mac(RXMAC_ALIGN_ERR_CNT); 6203 mp->rx_frags += nr64_mac(RXMAC_FRAG_CNT); 6204 mp->rx_mcasts += nr64_mac(RXMAC_MC_FRM_CNT); 6205 mp->rx_bcasts += nr64_mac(RXMAC_BC_FRM_CNT); 6206 mp->rx_hist_cnt1 += nr64_mac(RXMAC_HIST_CNT1); 6207 mp->rx_hist_cnt2 += nr64_mac(RXMAC_HIST_CNT2); 6208 mp->rx_hist_cnt3 += nr64_mac(RXMAC_HIST_CNT3); 6209 mp->rx_hist_cnt4 += nr64_mac(RXMAC_HIST_CNT4); 6210 mp->rx_hist_cnt5 += nr64_mac(RXMAC_HIST_CNT5); 6211 mp->rx_hist_cnt6 += nr64_mac(RXMAC_HIST_CNT6); 6212 mp->rx_hist_cnt7 += nr64_mac(RXMAC_HIST_CNT7); 6213 mp->rx_octets += nr64_mac(RXMAC_BT_CNT); 6214 mp->rx_code_violations += nr64_mac(RXMAC_CD_VIO_CNT); 6215 mp->rx_len_errors += nr64_mac(RXMAC_MPSZER_CNT); 6216 mp->rx_crc_errors += nr64_mac(RXMAC_CRC_ER_CNT); 6217 } 6218 6219 static void niu_sync_bmac_stats(struct niu *np) 6220 { 6221 struct niu_bmac_stats *mp = &np->mac_stats.bmac; 6222 6223 mp->tx_bytes += nr64_mac(BTXMAC_BYTE_CNT); 6224 mp->tx_frames += nr64_mac(BTXMAC_FRM_CNT); 6225 6226 mp->rx_frames += nr64_mac(BRXMAC_FRAME_CNT); 6227 mp->rx_align_errors += nr64_mac(BRXMAC_ALIGN_ERR_CNT); 6228 mp->rx_crc_errors += nr64_mac(BRXMAC_ALIGN_ERR_CNT); 6229 mp->rx_len_errors += nr64_mac(BRXMAC_CODE_VIOL_ERR_CNT); 6230 } 6231 6232 static void niu_sync_mac_stats(struct niu *np) 6233 { 6234 if (np->flags & NIU_FLAGS_XMAC) 6235 niu_sync_xmac_stats(np); 6236 else 6237 niu_sync_bmac_stats(np); 6238 } 6239 6240 static void niu_get_rx_stats(struct niu *np, 6241 struct rtnl_link_stats64 *stats) 6242 { 6243 u64 pkts, dropped, errors, bytes; 6244 struct rx_ring_info *rx_rings; 6245 int i; 6246 6247 pkts = dropped = errors = bytes = 0; 6248 6249 rx_rings = ACCESS_ONCE(np->rx_rings); 6250 if (!rx_rings) 6251 goto no_rings; 6252 6253 for (i = 0; i < np->num_rx_rings; i++) { 6254 struct rx_ring_info *rp = &rx_rings[i]; 6255 6256 niu_sync_rx_discard_stats(np, rp, 0); 6257 6258 pkts += rp->rx_packets; 6259 bytes += rp->rx_bytes; 6260 dropped += rp->rx_dropped; 6261 errors += rp->rx_errors; 6262 } 6263 6264 no_rings: 6265 stats->rx_packets = pkts; 6266 stats->rx_bytes = bytes; 6267 stats->rx_dropped = dropped; 6268 stats->rx_errors = errors; 6269 } 6270 6271 static void niu_get_tx_stats(struct niu *np, 6272 struct rtnl_link_stats64 *stats) 6273 { 6274 u64 pkts, errors, bytes; 6275 struct tx_ring_info *tx_rings; 6276 int i; 6277 6278 pkts = errors = bytes = 0; 6279 6280 tx_rings = ACCESS_ONCE(np->tx_rings); 6281 if (!tx_rings) 6282 goto no_rings; 6283 6284 for (i = 0; i < np->num_tx_rings; i++) { 6285 struct tx_ring_info *rp = &tx_rings[i]; 6286 6287 pkts += rp->tx_packets; 6288 bytes += rp->tx_bytes; 6289 errors += rp->tx_errors; 6290 } 6291 6292 no_rings: 6293 stats->tx_packets = pkts; 6294 stats->tx_bytes = bytes; 6295 stats->tx_errors = errors; 6296 } 6297 6298 static struct rtnl_link_stats64 *niu_get_stats(struct net_device *dev, 6299 struct rtnl_link_stats64 *stats) 6300 { 6301 struct niu *np = netdev_priv(dev); 6302 6303 if (netif_running(dev)) { 6304 niu_get_rx_stats(np, stats); 6305 niu_get_tx_stats(np, stats); 6306 } 6307 6308 return stats; 6309 } 6310 6311 static void niu_load_hash_xmac(struct niu *np, u16 *hash) 6312 { 6313 int i; 6314 6315 for (i = 0; i < 16; i++) 6316 nw64_mac(XMAC_HASH_TBL(i), hash[i]); 6317 } 6318 6319 static void niu_load_hash_bmac(struct niu *np, u16 *hash) 6320 { 6321 int i; 6322 6323 for (i = 0; i < 16; i++) 6324 nw64_mac(BMAC_HASH_TBL(i), hash[i]); 6325 } 6326 6327 static void niu_load_hash(struct niu *np, u16 *hash) 6328 { 6329 if (np->flags & NIU_FLAGS_XMAC) 6330 niu_load_hash_xmac(np, hash); 6331 else 6332 niu_load_hash_bmac(np, hash); 6333 } 6334 6335 static void niu_set_rx_mode(struct net_device *dev) 6336 { 6337 struct niu *np = netdev_priv(dev); 6338 int i, alt_cnt, err; 6339 struct netdev_hw_addr *ha; 6340 unsigned long flags; 6341 u16 hash[16] = { 0, }; 6342 6343 spin_lock_irqsave(&np->lock, flags); 6344 niu_enable_rx_mac(np, 0); 6345 6346 np->flags &= ~(NIU_FLAGS_MCAST | NIU_FLAGS_PROMISC); 6347 if (dev->flags & IFF_PROMISC) 6348 np->flags |= NIU_FLAGS_PROMISC; 6349 if ((dev->flags & IFF_ALLMULTI) || (!netdev_mc_empty(dev))) 6350 np->flags |= NIU_FLAGS_MCAST; 6351 6352 alt_cnt = netdev_uc_count(dev); 6353 if (alt_cnt > niu_num_alt_addr(np)) { 6354 alt_cnt = 0; 6355 np->flags |= NIU_FLAGS_PROMISC; 6356 } 6357 6358 if (alt_cnt) { 6359 int index = 0; 6360 6361 netdev_for_each_uc_addr(ha, dev) { 6362 err = niu_set_alt_mac(np, index, ha->addr); 6363 if (err) 6364 netdev_warn(dev, "Error %d adding alt mac %d\n", 6365 err, index); 6366 err = niu_enable_alt_mac(np, index, 1); 6367 if (err) 6368 netdev_warn(dev, "Error %d enabling alt mac %d\n", 6369 err, index); 6370 6371 index++; 6372 } 6373 } else { 6374 int alt_start; 6375 if (np->flags & NIU_FLAGS_XMAC) 6376 alt_start = 0; 6377 else 6378 alt_start = 1; 6379 for (i = alt_start; i < niu_num_alt_addr(np); i++) { 6380 err = niu_enable_alt_mac(np, i, 0); 6381 if (err) 6382 netdev_warn(dev, "Error %d disabling alt mac %d\n", 6383 err, i); 6384 } 6385 } 6386 if (dev->flags & IFF_ALLMULTI) { 6387 for (i = 0; i < 16; i++) 6388 hash[i] = 0xffff; 6389 } else if (!netdev_mc_empty(dev)) { 6390 netdev_for_each_mc_addr(ha, dev) { 6391 u32 crc = ether_crc_le(ETH_ALEN, ha->addr); 6392 6393 crc >>= 24; 6394 hash[crc >> 4] |= (1 << (15 - (crc & 0xf))); 6395 } 6396 } 6397 6398 if (np->flags & NIU_FLAGS_MCAST) 6399 niu_load_hash(np, hash); 6400 6401 niu_enable_rx_mac(np, 1); 6402 spin_unlock_irqrestore(&np->lock, flags); 6403 } 6404 6405 static int niu_set_mac_addr(struct net_device *dev, void *p) 6406 { 6407 struct niu *np = netdev_priv(dev); 6408 struct sockaddr *addr = p; 6409 unsigned long flags; 6410 6411 if (!is_valid_ether_addr(addr->sa_data)) 6412 return -EADDRNOTAVAIL; 6413 6414 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN); 6415 6416 if (!netif_running(dev)) 6417 return 0; 6418 6419 spin_lock_irqsave(&np->lock, flags); 6420 niu_enable_rx_mac(np, 0); 6421 niu_set_primary_mac(np, dev->dev_addr); 6422 niu_enable_rx_mac(np, 1); 6423 spin_unlock_irqrestore(&np->lock, flags); 6424 6425 return 0; 6426 } 6427 6428 static int niu_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) 6429 { 6430 return -EOPNOTSUPP; 6431 } 6432 6433 static void niu_netif_stop(struct niu *np) 6434 { 6435 np->dev->trans_start = jiffies; /* prevent tx timeout */ 6436 6437 niu_disable_napi(np); 6438 6439 netif_tx_disable(np->dev); 6440 } 6441 6442 static void niu_netif_start(struct niu *np) 6443 { 6444 /* NOTE: unconditional netif_wake_queue is only appropriate 6445 * so long as all callers are assured to have free tx slots 6446 * (such as after niu_init_hw). 6447 */ 6448 netif_tx_wake_all_queues(np->dev); 6449 6450 niu_enable_napi(np); 6451 6452 niu_enable_interrupts(np, 1); 6453 } 6454 6455 static void niu_reset_buffers(struct niu *np) 6456 { 6457 int i, j, k, err; 6458 6459 if (np->rx_rings) { 6460 for (i = 0; i < np->num_rx_rings; i++) { 6461 struct rx_ring_info *rp = &np->rx_rings[i]; 6462 6463 for (j = 0, k = 0; j < MAX_RBR_RING_SIZE; j++) { 6464 struct page *page; 6465 6466 page = rp->rxhash[j]; 6467 while (page) { 6468 struct page *next = 6469 (struct page *) page->mapping; 6470 u64 base = page->index; 6471 base = base >> RBR_DESCR_ADDR_SHIFT; 6472 rp->rbr[k++] = cpu_to_le32(base); 6473 page = next; 6474 } 6475 } 6476 for (; k < MAX_RBR_RING_SIZE; k++) { 6477 err = niu_rbr_add_page(np, rp, GFP_ATOMIC, k); 6478 if (unlikely(err)) 6479 break; 6480 } 6481 6482 rp->rbr_index = rp->rbr_table_size - 1; 6483 rp->rcr_index = 0; 6484 rp->rbr_pending = 0; 6485 rp->rbr_refill_pending = 0; 6486 } 6487 } 6488 if (np->tx_rings) { 6489 for (i = 0; i < np->num_tx_rings; i++) { 6490 struct tx_ring_info *rp = &np->tx_rings[i]; 6491 6492 for (j = 0; j < MAX_TX_RING_SIZE; j++) { 6493 if (rp->tx_buffs[j].skb) 6494 (void) release_tx_packet(np, rp, j); 6495 } 6496 6497 rp->pending = MAX_TX_RING_SIZE; 6498 rp->prod = 0; 6499 rp->cons = 0; 6500 rp->wrap_bit = 0; 6501 } 6502 } 6503 } 6504 6505 static void niu_reset_task(struct work_struct *work) 6506 { 6507 struct niu *np = container_of(work, struct niu, reset_task); 6508 unsigned long flags; 6509 int err; 6510 6511 spin_lock_irqsave(&np->lock, flags); 6512 if (!netif_running(np->dev)) { 6513 spin_unlock_irqrestore(&np->lock, flags); 6514 return; 6515 } 6516 6517 spin_unlock_irqrestore(&np->lock, flags); 6518 6519 del_timer_sync(&np->timer); 6520 6521 niu_netif_stop(np); 6522 6523 spin_lock_irqsave(&np->lock, flags); 6524 6525 niu_stop_hw(np); 6526 6527 spin_unlock_irqrestore(&np->lock, flags); 6528 6529 niu_reset_buffers(np); 6530 6531 spin_lock_irqsave(&np->lock, flags); 6532 6533 err = niu_init_hw(np); 6534 if (!err) { 6535 np->timer.expires = jiffies + HZ; 6536 add_timer(&np->timer); 6537 niu_netif_start(np); 6538 } 6539 6540 spin_unlock_irqrestore(&np->lock, flags); 6541 } 6542 6543 static void niu_tx_timeout(struct net_device *dev) 6544 { 6545 struct niu *np = netdev_priv(dev); 6546 6547 dev_err(np->device, "%s: Transmit timed out, resetting\n", 6548 dev->name); 6549 6550 schedule_work(&np->reset_task); 6551 } 6552 6553 static void niu_set_txd(struct tx_ring_info *rp, int index, 6554 u64 mapping, u64 len, u64 mark, 6555 u64 n_frags) 6556 { 6557 __le64 *desc = &rp->descr[index]; 6558 6559 *desc = cpu_to_le64(mark | 6560 (n_frags << TX_DESC_NUM_PTR_SHIFT) | 6561 (len << TX_DESC_TR_LEN_SHIFT) | 6562 (mapping & TX_DESC_SAD)); 6563 } 6564 6565 static u64 niu_compute_tx_flags(struct sk_buff *skb, struct ethhdr *ehdr, 6566 u64 pad_bytes, u64 len) 6567 { 6568 u16 eth_proto, eth_proto_inner; 6569 u64 csum_bits, l3off, ihl, ret; 6570 u8 ip_proto; 6571 int ipv6; 6572 6573 eth_proto = be16_to_cpu(ehdr->h_proto); 6574 eth_proto_inner = eth_proto; 6575 if (eth_proto == ETH_P_8021Q) { 6576 struct vlan_ethhdr *vp = (struct vlan_ethhdr *) ehdr; 6577 __be16 val = vp->h_vlan_encapsulated_proto; 6578 6579 eth_proto_inner = be16_to_cpu(val); 6580 } 6581 6582 ipv6 = ihl = 0; 6583 switch (skb->protocol) { 6584 case cpu_to_be16(ETH_P_IP): 6585 ip_proto = ip_hdr(skb)->protocol; 6586 ihl = ip_hdr(skb)->ihl; 6587 break; 6588 case cpu_to_be16(ETH_P_IPV6): 6589 ip_proto = ipv6_hdr(skb)->nexthdr; 6590 ihl = (40 >> 2); 6591 ipv6 = 1; 6592 break; 6593 default: 6594 ip_proto = ihl = 0; 6595 break; 6596 } 6597 6598 csum_bits = TXHDR_CSUM_NONE; 6599 if (skb->ip_summed == CHECKSUM_PARTIAL) { 6600 u64 start, stuff; 6601 6602 csum_bits = (ip_proto == IPPROTO_TCP ? 6603 TXHDR_CSUM_TCP : 6604 (ip_proto == IPPROTO_UDP ? 6605 TXHDR_CSUM_UDP : TXHDR_CSUM_SCTP)); 6606 6607 start = skb_checksum_start_offset(skb) - 6608 (pad_bytes + sizeof(struct tx_pkt_hdr)); 6609 stuff = start + skb->csum_offset; 6610 6611 csum_bits |= (start / 2) << TXHDR_L4START_SHIFT; 6612 csum_bits |= (stuff / 2) << TXHDR_L4STUFF_SHIFT; 6613 } 6614 6615 l3off = skb_network_offset(skb) - 6616 (pad_bytes + sizeof(struct tx_pkt_hdr)); 6617 6618 ret = (((pad_bytes / 2) << TXHDR_PAD_SHIFT) | 6619 (len << TXHDR_LEN_SHIFT) | 6620 ((l3off / 2) << TXHDR_L3START_SHIFT) | 6621 (ihl << TXHDR_IHL_SHIFT) | 6622 ((eth_proto_inner < ETH_P_802_3_MIN) ? TXHDR_LLC : 0) | 6623 ((eth_proto == ETH_P_8021Q) ? TXHDR_VLAN : 0) | 6624 (ipv6 ? TXHDR_IP_VER : 0) | 6625 csum_bits); 6626 6627 return ret; 6628 } 6629 6630 static netdev_tx_t niu_start_xmit(struct sk_buff *skb, 6631 struct net_device *dev) 6632 { 6633 struct niu *np = netdev_priv(dev); 6634 unsigned long align, headroom; 6635 struct netdev_queue *txq; 6636 struct tx_ring_info *rp; 6637 struct tx_pkt_hdr *tp; 6638 unsigned int len, nfg; 6639 struct ethhdr *ehdr; 6640 int prod, i, tlen; 6641 u64 mapping, mrk; 6642 6643 i = skb_get_queue_mapping(skb); 6644 rp = &np->tx_rings[i]; 6645 txq = netdev_get_tx_queue(dev, i); 6646 6647 if (niu_tx_avail(rp) <= (skb_shinfo(skb)->nr_frags + 1)) { 6648 netif_tx_stop_queue(txq); 6649 dev_err(np->device, "%s: BUG! Tx ring full when queue awake!\n", dev->name); 6650 rp->tx_errors++; 6651 return NETDEV_TX_BUSY; 6652 } 6653 6654 if (eth_skb_pad(skb)) 6655 goto out; 6656 6657 len = sizeof(struct tx_pkt_hdr) + 15; 6658 if (skb_headroom(skb) < len) { 6659 struct sk_buff *skb_new; 6660 6661 skb_new = skb_realloc_headroom(skb, len); 6662 if (!skb_new) { 6663 rp->tx_errors++; 6664 goto out_drop; 6665 } 6666 kfree_skb(skb); 6667 skb = skb_new; 6668 } else 6669 skb_orphan(skb); 6670 6671 align = ((unsigned long) skb->data & (16 - 1)); 6672 headroom = align + sizeof(struct tx_pkt_hdr); 6673 6674 ehdr = (struct ethhdr *) skb->data; 6675 tp = (struct tx_pkt_hdr *) skb_push(skb, headroom); 6676 6677 len = skb->len - sizeof(struct tx_pkt_hdr); 6678 tp->flags = cpu_to_le64(niu_compute_tx_flags(skb, ehdr, align, len)); 6679 tp->resv = 0; 6680 6681 len = skb_headlen(skb); 6682 mapping = np->ops->map_single(np->device, skb->data, 6683 len, DMA_TO_DEVICE); 6684 6685 prod = rp->prod; 6686 6687 rp->tx_buffs[prod].skb = skb; 6688 rp->tx_buffs[prod].mapping = mapping; 6689 6690 mrk = TX_DESC_SOP; 6691 if (++rp->mark_counter == rp->mark_freq) { 6692 rp->mark_counter = 0; 6693 mrk |= TX_DESC_MARK; 6694 rp->mark_pending++; 6695 } 6696 6697 tlen = len; 6698 nfg = skb_shinfo(skb)->nr_frags; 6699 while (tlen > 0) { 6700 tlen -= MAX_TX_DESC_LEN; 6701 nfg++; 6702 } 6703 6704 while (len > 0) { 6705 unsigned int this_len = len; 6706 6707 if (this_len > MAX_TX_DESC_LEN) 6708 this_len = MAX_TX_DESC_LEN; 6709 6710 niu_set_txd(rp, prod, mapping, this_len, mrk, nfg); 6711 mrk = nfg = 0; 6712 6713 prod = NEXT_TX(rp, prod); 6714 mapping += this_len; 6715 len -= this_len; 6716 } 6717 6718 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { 6719 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 6720 6721 len = skb_frag_size(frag); 6722 mapping = np->ops->map_page(np->device, skb_frag_page(frag), 6723 frag->page_offset, len, 6724 DMA_TO_DEVICE); 6725 6726 rp->tx_buffs[prod].skb = NULL; 6727 rp->tx_buffs[prod].mapping = mapping; 6728 6729 niu_set_txd(rp, prod, mapping, len, 0, 0); 6730 6731 prod = NEXT_TX(rp, prod); 6732 } 6733 6734 if (prod < rp->prod) 6735 rp->wrap_bit ^= TX_RING_KICK_WRAP; 6736 rp->prod = prod; 6737 6738 nw64(TX_RING_KICK(rp->tx_channel), rp->wrap_bit | (prod << 3)); 6739 6740 if (unlikely(niu_tx_avail(rp) <= (MAX_SKB_FRAGS + 1))) { 6741 netif_tx_stop_queue(txq); 6742 if (niu_tx_avail(rp) > NIU_TX_WAKEUP_THRESH(rp)) 6743 netif_tx_wake_queue(txq); 6744 } 6745 6746 out: 6747 return NETDEV_TX_OK; 6748 6749 out_drop: 6750 rp->tx_errors++; 6751 kfree_skb(skb); 6752 goto out; 6753 } 6754 6755 static int niu_change_mtu(struct net_device *dev, int new_mtu) 6756 { 6757 struct niu *np = netdev_priv(dev); 6758 int err, orig_jumbo, new_jumbo; 6759 6760 if (new_mtu < 68 || new_mtu > NIU_MAX_MTU) 6761 return -EINVAL; 6762 6763 orig_jumbo = (dev->mtu > ETH_DATA_LEN); 6764 new_jumbo = (new_mtu > ETH_DATA_LEN); 6765 6766 dev->mtu = new_mtu; 6767 6768 if (!netif_running(dev) || 6769 (orig_jumbo == new_jumbo)) 6770 return 0; 6771 6772 niu_full_shutdown(np, dev); 6773 6774 niu_free_channels(np); 6775 6776 niu_enable_napi(np); 6777 6778 err = niu_alloc_channels(np); 6779 if (err) 6780 return err; 6781 6782 spin_lock_irq(&np->lock); 6783 6784 err = niu_init_hw(np); 6785 if (!err) { 6786 init_timer(&np->timer); 6787 np->timer.expires = jiffies + HZ; 6788 np->timer.data = (unsigned long) np; 6789 np->timer.function = niu_timer; 6790 6791 err = niu_enable_interrupts(np, 1); 6792 if (err) 6793 niu_stop_hw(np); 6794 } 6795 6796 spin_unlock_irq(&np->lock); 6797 6798 if (!err) { 6799 netif_tx_start_all_queues(dev); 6800 if (np->link_config.loopback_mode != LOOPBACK_DISABLED) 6801 netif_carrier_on(dev); 6802 6803 add_timer(&np->timer); 6804 } 6805 6806 return err; 6807 } 6808 6809 static void niu_get_drvinfo(struct net_device *dev, 6810 struct ethtool_drvinfo *info) 6811 { 6812 struct niu *np = netdev_priv(dev); 6813 struct niu_vpd *vpd = &np->vpd; 6814 6815 strlcpy(info->driver, DRV_MODULE_NAME, sizeof(info->driver)); 6816 strlcpy(info->version, DRV_MODULE_VERSION, sizeof(info->version)); 6817 snprintf(info->fw_version, sizeof(info->fw_version), "%d.%d", 6818 vpd->fcode_major, vpd->fcode_minor); 6819 if (np->parent->plat_type != PLAT_TYPE_NIU) 6820 strlcpy(info->bus_info, pci_name(np->pdev), 6821 sizeof(info->bus_info)); 6822 } 6823 6824 static int niu_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) 6825 { 6826 struct niu *np = netdev_priv(dev); 6827 struct niu_link_config *lp; 6828 6829 lp = &np->link_config; 6830 6831 memset(cmd, 0, sizeof(*cmd)); 6832 cmd->phy_address = np->phy_addr; 6833 cmd->supported = lp->supported; 6834 cmd->advertising = lp->active_advertising; 6835 cmd->autoneg = lp->active_autoneg; 6836 ethtool_cmd_speed_set(cmd, lp->active_speed); 6837 cmd->duplex = lp->active_duplex; 6838 cmd->port = (np->flags & NIU_FLAGS_FIBER) ? PORT_FIBRE : PORT_TP; 6839 cmd->transceiver = (np->flags & NIU_FLAGS_XCVR_SERDES) ? 6840 XCVR_EXTERNAL : XCVR_INTERNAL; 6841 6842 return 0; 6843 } 6844 6845 static int niu_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) 6846 { 6847 struct niu *np = netdev_priv(dev); 6848 struct niu_link_config *lp = &np->link_config; 6849 6850 lp->advertising = cmd->advertising; 6851 lp->speed = ethtool_cmd_speed(cmd); 6852 lp->duplex = cmd->duplex; 6853 lp->autoneg = cmd->autoneg; 6854 return niu_init_link(np); 6855 } 6856 6857 static u32 niu_get_msglevel(struct net_device *dev) 6858 { 6859 struct niu *np = netdev_priv(dev); 6860 return np->msg_enable; 6861 } 6862 6863 static void niu_set_msglevel(struct net_device *dev, u32 value) 6864 { 6865 struct niu *np = netdev_priv(dev); 6866 np->msg_enable = value; 6867 } 6868 6869 static int niu_nway_reset(struct net_device *dev) 6870 { 6871 struct niu *np = netdev_priv(dev); 6872 6873 if (np->link_config.autoneg) 6874 return niu_init_link(np); 6875 6876 return 0; 6877 } 6878 6879 static int niu_get_eeprom_len(struct net_device *dev) 6880 { 6881 struct niu *np = netdev_priv(dev); 6882 6883 return np->eeprom_len; 6884 } 6885 6886 static int niu_get_eeprom(struct net_device *dev, 6887 struct ethtool_eeprom *eeprom, u8 *data) 6888 { 6889 struct niu *np = netdev_priv(dev); 6890 u32 offset, len, val; 6891 6892 offset = eeprom->offset; 6893 len = eeprom->len; 6894 6895 if (offset + len < offset) 6896 return -EINVAL; 6897 if (offset >= np->eeprom_len) 6898 return -EINVAL; 6899 if (offset + len > np->eeprom_len) 6900 len = eeprom->len = np->eeprom_len - offset; 6901 6902 if (offset & 3) { 6903 u32 b_offset, b_count; 6904 6905 b_offset = offset & 3; 6906 b_count = 4 - b_offset; 6907 if (b_count > len) 6908 b_count = len; 6909 6910 val = nr64(ESPC_NCR((offset - b_offset) / 4)); 6911 memcpy(data, ((char *)&val) + b_offset, b_count); 6912 data += b_count; 6913 len -= b_count; 6914 offset += b_count; 6915 } 6916 while (len >= 4) { 6917 val = nr64(ESPC_NCR(offset / 4)); 6918 memcpy(data, &val, 4); 6919 data += 4; 6920 len -= 4; 6921 offset += 4; 6922 } 6923 if (len) { 6924 val = nr64(ESPC_NCR(offset / 4)); 6925 memcpy(data, &val, len); 6926 } 6927 return 0; 6928 } 6929 6930 static void niu_ethflow_to_l3proto(int flow_type, u8 *pid) 6931 { 6932 switch (flow_type) { 6933 case TCP_V4_FLOW: 6934 case TCP_V6_FLOW: 6935 *pid = IPPROTO_TCP; 6936 break; 6937 case UDP_V4_FLOW: 6938 case UDP_V6_FLOW: 6939 *pid = IPPROTO_UDP; 6940 break; 6941 case SCTP_V4_FLOW: 6942 case SCTP_V6_FLOW: 6943 *pid = IPPROTO_SCTP; 6944 break; 6945 case AH_V4_FLOW: 6946 case AH_V6_FLOW: 6947 *pid = IPPROTO_AH; 6948 break; 6949 case ESP_V4_FLOW: 6950 case ESP_V6_FLOW: 6951 *pid = IPPROTO_ESP; 6952 break; 6953 default: 6954 *pid = 0; 6955 break; 6956 } 6957 } 6958 6959 static int niu_class_to_ethflow(u64 class, int *flow_type) 6960 { 6961 switch (class) { 6962 case CLASS_CODE_TCP_IPV4: 6963 *flow_type = TCP_V4_FLOW; 6964 break; 6965 case CLASS_CODE_UDP_IPV4: 6966 *flow_type = UDP_V4_FLOW; 6967 break; 6968 case CLASS_CODE_AH_ESP_IPV4: 6969 *flow_type = AH_V4_FLOW; 6970 break; 6971 case CLASS_CODE_SCTP_IPV4: 6972 *flow_type = SCTP_V4_FLOW; 6973 break; 6974 case CLASS_CODE_TCP_IPV6: 6975 *flow_type = TCP_V6_FLOW; 6976 break; 6977 case CLASS_CODE_UDP_IPV6: 6978 *flow_type = UDP_V6_FLOW; 6979 break; 6980 case CLASS_CODE_AH_ESP_IPV6: 6981 *flow_type = AH_V6_FLOW; 6982 break; 6983 case CLASS_CODE_SCTP_IPV6: 6984 *flow_type = SCTP_V6_FLOW; 6985 break; 6986 case CLASS_CODE_USER_PROG1: 6987 case CLASS_CODE_USER_PROG2: 6988 case CLASS_CODE_USER_PROG3: 6989 case CLASS_CODE_USER_PROG4: 6990 *flow_type = IP_USER_FLOW; 6991 break; 6992 default: 6993 return 0; 6994 } 6995 6996 return 1; 6997 } 6998 6999 static int niu_ethflow_to_class(int flow_type, u64 *class) 7000 { 7001 switch (flow_type) { 7002 case TCP_V4_FLOW: 7003 *class = CLASS_CODE_TCP_IPV4; 7004 break; 7005 case UDP_V4_FLOW: 7006 *class = CLASS_CODE_UDP_IPV4; 7007 break; 7008 case AH_ESP_V4_FLOW: 7009 case AH_V4_FLOW: 7010 case ESP_V4_FLOW: 7011 *class = CLASS_CODE_AH_ESP_IPV4; 7012 break; 7013 case SCTP_V4_FLOW: 7014 *class = CLASS_CODE_SCTP_IPV4; 7015 break; 7016 case TCP_V6_FLOW: 7017 *class = CLASS_CODE_TCP_IPV6; 7018 break; 7019 case UDP_V6_FLOW: 7020 *class = CLASS_CODE_UDP_IPV6; 7021 break; 7022 case AH_ESP_V6_FLOW: 7023 case AH_V6_FLOW: 7024 case ESP_V6_FLOW: 7025 *class = CLASS_CODE_AH_ESP_IPV6; 7026 break; 7027 case SCTP_V6_FLOW: 7028 *class = CLASS_CODE_SCTP_IPV6; 7029 break; 7030 default: 7031 return 0; 7032 } 7033 7034 return 1; 7035 } 7036 7037 static u64 niu_flowkey_to_ethflow(u64 flow_key) 7038 { 7039 u64 ethflow = 0; 7040 7041 if (flow_key & FLOW_KEY_L2DA) 7042 ethflow |= RXH_L2DA; 7043 if (flow_key & FLOW_KEY_VLAN) 7044 ethflow |= RXH_VLAN; 7045 if (flow_key & FLOW_KEY_IPSA) 7046 ethflow |= RXH_IP_SRC; 7047 if (flow_key & FLOW_KEY_IPDA) 7048 ethflow |= RXH_IP_DST; 7049 if (flow_key & FLOW_KEY_PROTO) 7050 ethflow |= RXH_L3_PROTO; 7051 if (flow_key & (FLOW_KEY_L4_BYTE12 << FLOW_KEY_L4_0_SHIFT)) 7052 ethflow |= RXH_L4_B_0_1; 7053 if (flow_key & (FLOW_KEY_L4_BYTE12 << FLOW_KEY_L4_1_SHIFT)) 7054 ethflow |= RXH_L4_B_2_3; 7055 7056 return ethflow; 7057 7058 } 7059 7060 static int niu_ethflow_to_flowkey(u64 ethflow, u64 *flow_key) 7061 { 7062 u64 key = 0; 7063 7064 if (ethflow & RXH_L2DA) 7065 key |= FLOW_KEY_L2DA; 7066 if (ethflow & RXH_VLAN) 7067 key |= FLOW_KEY_VLAN; 7068 if (ethflow & RXH_IP_SRC) 7069 key |= FLOW_KEY_IPSA; 7070 if (ethflow & RXH_IP_DST) 7071 key |= FLOW_KEY_IPDA; 7072 if (ethflow & RXH_L3_PROTO) 7073 key |= FLOW_KEY_PROTO; 7074 if (ethflow & RXH_L4_B_0_1) 7075 key |= (FLOW_KEY_L4_BYTE12 << FLOW_KEY_L4_0_SHIFT); 7076 if (ethflow & RXH_L4_B_2_3) 7077 key |= (FLOW_KEY_L4_BYTE12 << FLOW_KEY_L4_1_SHIFT); 7078 7079 *flow_key = key; 7080 7081 return 1; 7082 7083 } 7084 7085 static int niu_get_hash_opts(struct niu *np, struct ethtool_rxnfc *nfc) 7086 { 7087 u64 class; 7088 7089 nfc->data = 0; 7090 7091 if (!niu_ethflow_to_class(nfc->flow_type, &class)) 7092 return -EINVAL; 7093 7094 if (np->parent->tcam_key[class - CLASS_CODE_USER_PROG1] & 7095 TCAM_KEY_DISC) 7096 nfc->data = RXH_DISCARD; 7097 else 7098 nfc->data = niu_flowkey_to_ethflow(np->parent->flow_key[class - 7099 CLASS_CODE_USER_PROG1]); 7100 return 0; 7101 } 7102 7103 static void niu_get_ip4fs_from_tcam_key(struct niu_tcam_entry *tp, 7104 struct ethtool_rx_flow_spec *fsp) 7105 { 7106 u32 tmp; 7107 u16 prt; 7108 7109 tmp = (tp->key[3] & TCAM_V4KEY3_SADDR) >> TCAM_V4KEY3_SADDR_SHIFT; 7110 fsp->h_u.tcp_ip4_spec.ip4src = cpu_to_be32(tmp); 7111 7112 tmp = (tp->key[3] & TCAM_V4KEY3_DADDR) >> TCAM_V4KEY3_DADDR_SHIFT; 7113 fsp->h_u.tcp_ip4_spec.ip4dst = cpu_to_be32(tmp); 7114 7115 tmp = (tp->key_mask[3] & TCAM_V4KEY3_SADDR) >> TCAM_V4KEY3_SADDR_SHIFT; 7116 fsp->m_u.tcp_ip4_spec.ip4src = cpu_to_be32(tmp); 7117 7118 tmp = (tp->key_mask[3] & TCAM_V4KEY3_DADDR) >> TCAM_V4KEY3_DADDR_SHIFT; 7119 fsp->m_u.tcp_ip4_spec.ip4dst = cpu_to_be32(tmp); 7120 7121 fsp->h_u.tcp_ip4_spec.tos = (tp->key[2] & TCAM_V4KEY2_TOS) >> 7122 TCAM_V4KEY2_TOS_SHIFT; 7123 fsp->m_u.tcp_ip4_spec.tos = (tp->key_mask[2] & TCAM_V4KEY2_TOS) >> 7124 TCAM_V4KEY2_TOS_SHIFT; 7125 7126 switch (fsp->flow_type) { 7127 case TCP_V4_FLOW: 7128 case UDP_V4_FLOW: 7129 case SCTP_V4_FLOW: 7130 prt = ((tp->key[2] & TCAM_V4KEY2_PORT_SPI) >> 7131 TCAM_V4KEY2_PORT_SPI_SHIFT) >> 16; 7132 fsp->h_u.tcp_ip4_spec.psrc = cpu_to_be16(prt); 7133 7134 prt = ((tp->key[2] & TCAM_V4KEY2_PORT_SPI) >> 7135 TCAM_V4KEY2_PORT_SPI_SHIFT) & 0xffff; 7136 fsp->h_u.tcp_ip4_spec.pdst = cpu_to_be16(prt); 7137 7138 prt = ((tp->key_mask[2] & TCAM_V4KEY2_PORT_SPI) >> 7139 TCAM_V4KEY2_PORT_SPI_SHIFT) >> 16; 7140 fsp->m_u.tcp_ip4_spec.psrc = cpu_to_be16(prt); 7141 7142 prt = ((tp->key_mask[2] & TCAM_V4KEY2_PORT_SPI) >> 7143 TCAM_V4KEY2_PORT_SPI_SHIFT) & 0xffff; 7144 fsp->m_u.tcp_ip4_spec.pdst = cpu_to_be16(prt); 7145 break; 7146 case AH_V4_FLOW: 7147 case ESP_V4_FLOW: 7148 tmp = (tp->key[2] & TCAM_V4KEY2_PORT_SPI) >> 7149 TCAM_V4KEY2_PORT_SPI_SHIFT; 7150 fsp->h_u.ah_ip4_spec.spi = cpu_to_be32(tmp); 7151 7152 tmp = (tp->key_mask[2] & TCAM_V4KEY2_PORT_SPI) >> 7153 TCAM_V4KEY2_PORT_SPI_SHIFT; 7154 fsp->m_u.ah_ip4_spec.spi = cpu_to_be32(tmp); 7155 break; 7156 case IP_USER_FLOW: 7157 tmp = (tp->key[2] & TCAM_V4KEY2_PORT_SPI) >> 7158 TCAM_V4KEY2_PORT_SPI_SHIFT; 7159 fsp->h_u.usr_ip4_spec.l4_4_bytes = cpu_to_be32(tmp); 7160 7161 tmp = (tp->key_mask[2] & TCAM_V4KEY2_PORT_SPI) >> 7162 TCAM_V4KEY2_PORT_SPI_SHIFT; 7163 fsp->m_u.usr_ip4_spec.l4_4_bytes = cpu_to_be32(tmp); 7164 7165 fsp->h_u.usr_ip4_spec.proto = 7166 (tp->key[2] & TCAM_V4KEY2_PROTO) >> 7167 TCAM_V4KEY2_PROTO_SHIFT; 7168 fsp->m_u.usr_ip4_spec.proto = 7169 (tp->key_mask[2] & TCAM_V4KEY2_PROTO) >> 7170 TCAM_V4KEY2_PROTO_SHIFT; 7171 7172 fsp->h_u.usr_ip4_spec.ip_ver = ETH_RX_NFC_IP4; 7173 break; 7174 default: 7175 break; 7176 } 7177 } 7178 7179 static int niu_get_ethtool_tcam_entry(struct niu *np, 7180 struct ethtool_rxnfc *nfc) 7181 { 7182 struct niu_parent *parent = np->parent; 7183 struct niu_tcam_entry *tp; 7184 struct ethtool_rx_flow_spec *fsp = &nfc->fs; 7185 u16 idx; 7186 u64 class; 7187 int ret = 0; 7188 7189 idx = tcam_get_index(np, (u16)nfc->fs.location); 7190 7191 tp = &parent->tcam[idx]; 7192 if (!tp->valid) { 7193 netdev_info(np->dev, "niu%d: entry [%d] invalid for idx[%d]\n", 7194 parent->index, (u16)nfc->fs.location, idx); 7195 return -EINVAL; 7196 } 7197 7198 /* fill the flow spec entry */ 7199 class = (tp->key[0] & TCAM_V4KEY0_CLASS_CODE) >> 7200 TCAM_V4KEY0_CLASS_CODE_SHIFT; 7201 ret = niu_class_to_ethflow(class, &fsp->flow_type); 7202 7203 if (ret < 0) { 7204 netdev_info(np->dev, "niu%d: niu_class_to_ethflow failed\n", 7205 parent->index); 7206 ret = -EINVAL; 7207 goto out; 7208 } 7209 7210 if (fsp->flow_type == AH_V4_FLOW || fsp->flow_type == AH_V6_FLOW) { 7211 u32 proto = (tp->key[2] & TCAM_V4KEY2_PROTO) >> 7212 TCAM_V4KEY2_PROTO_SHIFT; 7213 if (proto == IPPROTO_ESP) { 7214 if (fsp->flow_type == AH_V4_FLOW) 7215 fsp->flow_type = ESP_V4_FLOW; 7216 else 7217 fsp->flow_type = ESP_V6_FLOW; 7218 } 7219 } 7220 7221 switch (fsp->flow_type) { 7222 case TCP_V4_FLOW: 7223 case UDP_V4_FLOW: 7224 case SCTP_V4_FLOW: 7225 case AH_V4_FLOW: 7226 case ESP_V4_FLOW: 7227 niu_get_ip4fs_from_tcam_key(tp, fsp); 7228 break; 7229 case TCP_V6_FLOW: 7230 case UDP_V6_FLOW: 7231 case SCTP_V6_FLOW: 7232 case AH_V6_FLOW: 7233 case ESP_V6_FLOW: 7234 /* Not yet implemented */ 7235 ret = -EINVAL; 7236 break; 7237 case IP_USER_FLOW: 7238 niu_get_ip4fs_from_tcam_key(tp, fsp); 7239 break; 7240 default: 7241 ret = -EINVAL; 7242 break; 7243 } 7244 7245 if (ret < 0) 7246 goto out; 7247 7248 if (tp->assoc_data & TCAM_ASSOCDATA_DISC) 7249 fsp->ring_cookie = RX_CLS_FLOW_DISC; 7250 else 7251 fsp->ring_cookie = (tp->assoc_data & TCAM_ASSOCDATA_OFFSET) >> 7252 TCAM_ASSOCDATA_OFFSET_SHIFT; 7253 7254 /* put the tcam size here */ 7255 nfc->data = tcam_get_size(np); 7256 out: 7257 return ret; 7258 } 7259 7260 static int niu_get_ethtool_tcam_all(struct niu *np, 7261 struct ethtool_rxnfc *nfc, 7262 u32 *rule_locs) 7263 { 7264 struct niu_parent *parent = np->parent; 7265 struct niu_tcam_entry *tp; 7266 int i, idx, cnt; 7267 unsigned long flags; 7268 int ret = 0; 7269 7270 /* put the tcam size here */ 7271 nfc->data = tcam_get_size(np); 7272 7273 niu_lock_parent(np, flags); 7274 for (cnt = 0, i = 0; i < nfc->data; i++) { 7275 idx = tcam_get_index(np, i); 7276 tp = &parent->tcam[idx]; 7277 if (!tp->valid) 7278 continue; 7279 if (cnt == nfc->rule_cnt) { 7280 ret = -EMSGSIZE; 7281 break; 7282 } 7283 rule_locs[cnt] = i; 7284 cnt++; 7285 } 7286 niu_unlock_parent(np, flags); 7287 7288 nfc->rule_cnt = cnt; 7289 7290 return ret; 7291 } 7292 7293 static int niu_get_nfc(struct net_device *dev, struct ethtool_rxnfc *cmd, 7294 u32 *rule_locs) 7295 { 7296 struct niu *np = netdev_priv(dev); 7297 int ret = 0; 7298 7299 switch (cmd->cmd) { 7300 case ETHTOOL_GRXFH: 7301 ret = niu_get_hash_opts(np, cmd); 7302 break; 7303 case ETHTOOL_GRXRINGS: 7304 cmd->data = np->num_rx_rings; 7305 break; 7306 case ETHTOOL_GRXCLSRLCNT: 7307 cmd->rule_cnt = tcam_get_valid_entry_cnt(np); 7308 break; 7309 case ETHTOOL_GRXCLSRULE: 7310 ret = niu_get_ethtool_tcam_entry(np, cmd); 7311 break; 7312 case ETHTOOL_GRXCLSRLALL: 7313 ret = niu_get_ethtool_tcam_all(np, cmd, rule_locs); 7314 break; 7315 default: 7316 ret = -EINVAL; 7317 break; 7318 } 7319 7320 return ret; 7321 } 7322 7323 static int niu_set_hash_opts(struct niu *np, struct ethtool_rxnfc *nfc) 7324 { 7325 u64 class; 7326 u64 flow_key = 0; 7327 unsigned long flags; 7328 7329 if (!niu_ethflow_to_class(nfc->flow_type, &class)) 7330 return -EINVAL; 7331 7332 if (class < CLASS_CODE_USER_PROG1 || 7333 class > CLASS_CODE_SCTP_IPV6) 7334 return -EINVAL; 7335 7336 if (nfc->data & RXH_DISCARD) { 7337 niu_lock_parent(np, flags); 7338 flow_key = np->parent->tcam_key[class - 7339 CLASS_CODE_USER_PROG1]; 7340 flow_key |= TCAM_KEY_DISC; 7341 nw64(TCAM_KEY(class - CLASS_CODE_USER_PROG1), flow_key); 7342 np->parent->tcam_key[class - CLASS_CODE_USER_PROG1] = flow_key; 7343 niu_unlock_parent(np, flags); 7344 return 0; 7345 } else { 7346 /* Discard was set before, but is not set now */ 7347 if (np->parent->tcam_key[class - CLASS_CODE_USER_PROG1] & 7348 TCAM_KEY_DISC) { 7349 niu_lock_parent(np, flags); 7350 flow_key = np->parent->tcam_key[class - 7351 CLASS_CODE_USER_PROG1]; 7352 flow_key &= ~TCAM_KEY_DISC; 7353 nw64(TCAM_KEY(class - CLASS_CODE_USER_PROG1), 7354 flow_key); 7355 np->parent->tcam_key[class - CLASS_CODE_USER_PROG1] = 7356 flow_key; 7357 niu_unlock_parent(np, flags); 7358 } 7359 } 7360 7361 if (!niu_ethflow_to_flowkey(nfc->data, &flow_key)) 7362 return -EINVAL; 7363 7364 niu_lock_parent(np, flags); 7365 nw64(FLOW_KEY(class - CLASS_CODE_USER_PROG1), flow_key); 7366 np->parent->flow_key[class - CLASS_CODE_USER_PROG1] = flow_key; 7367 niu_unlock_parent(np, flags); 7368 7369 return 0; 7370 } 7371 7372 static void niu_get_tcamkey_from_ip4fs(struct ethtool_rx_flow_spec *fsp, 7373 struct niu_tcam_entry *tp, 7374 int l2_rdc_tab, u64 class) 7375 { 7376 u8 pid = 0; 7377 u32 sip, dip, sipm, dipm, spi, spim; 7378 u16 sport, dport, spm, dpm; 7379 7380 sip = be32_to_cpu(fsp->h_u.tcp_ip4_spec.ip4src); 7381 sipm = be32_to_cpu(fsp->m_u.tcp_ip4_spec.ip4src); 7382 dip = be32_to_cpu(fsp->h_u.tcp_ip4_spec.ip4dst); 7383 dipm = be32_to_cpu(fsp->m_u.tcp_ip4_spec.ip4dst); 7384 7385 tp->key[0] = class << TCAM_V4KEY0_CLASS_CODE_SHIFT; 7386 tp->key_mask[0] = TCAM_V4KEY0_CLASS_CODE; 7387 tp->key[1] = (u64)l2_rdc_tab << TCAM_V4KEY1_L2RDCNUM_SHIFT; 7388 tp->key_mask[1] = TCAM_V4KEY1_L2RDCNUM; 7389 7390 tp->key[3] = (u64)sip << TCAM_V4KEY3_SADDR_SHIFT; 7391 tp->key[3] |= dip; 7392 7393 tp->key_mask[3] = (u64)sipm << TCAM_V4KEY3_SADDR_SHIFT; 7394 tp->key_mask[3] |= dipm; 7395 7396 tp->key[2] |= ((u64)fsp->h_u.tcp_ip4_spec.tos << 7397 TCAM_V4KEY2_TOS_SHIFT); 7398 tp->key_mask[2] |= ((u64)fsp->m_u.tcp_ip4_spec.tos << 7399 TCAM_V4KEY2_TOS_SHIFT); 7400 switch (fsp->flow_type) { 7401 case TCP_V4_FLOW: 7402 case UDP_V4_FLOW: 7403 case SCTP_V4_FLOW: 7404 sport = be16_to_cpu(fsp->h_u.tcp_ip4_spec.psrc); 7405 spm = be16_to_cpu(fsp->m_u.tcp_ip4_spec.psrc); 7406 dport = be16_to_cpu(fsp->h_u.tcp_ip4_spec.pdst); 7407 dpm = be16_to_cpu(fsp->m_u.tcp_ip4_spec.pdst); 7408 7409 tp->key[2] |= (((u64)sport << 16) | dport); 7410 tp->key_mask[2] |= (((u64)spm << 16) | dpm); 7411 niu_ethflow_to_l3proto(fsp->flow_type, &pid); 7412 break; 7413 case AH_V4_FLOW: 7414 case ESP_V4_FLOW: 7415 spi = be32_to_cpu(fsp->h_u.ah_ip4_spec.spi); 7416 spim = be32_to_cpu(fsp->m_u.ah_ip4_spec.spi); 7417 7418 tp->key[2] |= spi; 7419 tp->key_mask[2] |= spim; 7420 niu_ethflow_to_l3proto(fsp->flow_type, &pid); 7421 break; 7422 case IP_USER_FLOW: 7423 spi = be32_to_cpu(fsp->h_u.usr_ip4_spec.l4_4_bytes); 7424 spim = be32_to_cpu(fsp->m_u.usr_ip4_spec.l4_4_bytes); 7425 7426 tp->key[2] |= spi; 7427 tp->key_mask[2] |= spim; 7428 pid = fsp->h_u.usr_ip4_spec.proto; 7429 break; 7430 default: 7431 break; 7432 } 7433 7434 tp->key[2] |= ((u64)pid << TCAM_V4KEY2_PROTO_SHIFT); 7435 if (pid) { 7436 tp->key_mask[2] |= TCAM_V4KEY2_PROTO; 7437 } 7438 } 7439 7440 static int niu_add_ethtool_tcam_entry(struct niu *np, 7441 struct ethtool_rxnfc *nfc) 7442 { 7443 struct niu_parent *parent = np->parent; 7444 struct niu_tcam_entry *tp; 7445 struct ethtool_rx_flow_spec *fsp = &nfc->fs; 7446 struct niu_rdc_tables *rdc_table = &parent->rdc_group_cfg[np->port]; 7447 int l2_rdc_table = rdc_table->first_table_num; 7448 u16 idx; 7449 u64 class; 7450 unsigned long flags; 7451 int err, ret; 7452 7453 ret = 0; 7454 7455 idx = nfc->fs.location; 7456 if (idx >= tcam_get_size(np)) 7457 return -EINVAL; 7458 7459 if (fsp->flow_type == IP_USER_FLOW) { 7460 int i; 7461 int add_usr_cls = 0; 7462 struct ethtool_usrip4_spec *uspec = &fsp->h_u.usr_ip4_spec; 7463 struct ethtool_usrip4_spec *umask = &fsp->m_u.usr_ip4_spec; 7464 7465 if (uspec->ip_ver != ETH_RX_NFC_IP4) 7466 return -EINVAL; 7467 7468 niu_lock_parent(np, flags); 7469 7470 for (i = 0; i < NIU_L3_PROG_CLS; i++) { 7471 if (parent->l3_cls[i]) { 7472 if (uspec->proto == parent->l3_cls_pid[i]) { 7473 class = parent->l3_cls[i]; 7474 parent->l3_cls_refcnt[i]++; 7475 add_usr_cls = 1; 7476 break; 7477 } 7478 } else { 7479 /* Program new user IP class */ 7480 switch (i) { 7481 case 0: 7482 class = CLASS_CODE_USER_PROG1; 7483 break; 7484 case 1: 7485 class = CLASS_CODE_USER_PROG2; 7486 break; 7487 case 2: 7488 class = CLASS_CODE_USER_PROG3; 7489 break; 7490 case 3: 7491 class = CLASS_CODE_USER_PROG4; 7492 break; 7493 default: 7494 break; 7495 } 7496 ret = tcam_user_ip_class_set(np, class, 0, 7497 uspec->proto, 7498 uspec->tos, 7499 umask->tos); 7500 if (ret) 7501 goto out; 7502 7503 ret = tcam_user_ip_class_enable(np, class, 1); 7504 if (ret) 7505 goto out; 7506 parent->l3_cls[i] = class; 7507 parent->l3_cls_pid[i] = uspec->proto; 7508 parent->l3_cls_refcnt[i]++; 7509 add_usr_cls = 1; 7510 break; 7511 } 7512 } 7513 if (!add_usr_cls) { 7514 netdev_info(np->dev, "niu%d: %s(): Could not find/insert class for pid %d\n", 7515 parent->index, __func__, uspec->proto); 7516 ret = -EINVAL; 7517 goto out; 7518 } 7519 niu_unlock_parent(np, flags); 7520 } else { 7521 if (!niu_ethflow_to_class(fsp->flow_type, &class)) { 7522 return -EINVAL; 7523 } 7524 } 7525 7526 niu_lock_parent(np, flags); 7527 7528 idx = tcam_get_index(np, idx); 7529 tp = &parent->tcam[idx]; 7530 7531 memset(tp, 0, sizeof(*tp)); 7532 7533 /* fill in the tcam key and mask */ 7534 switch (fsp->flow_type) { 7535 case TCP_V4_FLOW: 7536 case UDP_V4_FLOW: 7537 case SCTP_V4_FLOW: 7538 case AH_V4_FLOW: 7539 case ESP_V4_FLOW: 7540 niu_get_tcamkey_from_ip4fs(fsp, tp, l2_rdc_table, class); 7541 break; 7542 case TCP_V6_FLOW: 7543 case UDP_V6_FLOW: 7544 case SCTP_V6_FLOW: 7545 case AH_V6_FLOW: 7546 case ESP_V6_FLOW: 7547 /* Not yet implemented */ 7548 netdev_info(np->dev, "niu%d: In %s(): flow %d for IPv6 not implemented\n", 7549 parent->index, __func__, fsp->flow_type); 7550 ret = -EINVAL; 7551 goto out; 7552 case IP_USER_FLOW: 7553 niu_get_tcamkey_from_ip4fs(fsp, tp, l2_rdc_table, class); 7554 break; 7555 default: 7556 netdev_info(np->dev, "niu%d: In %s(): Unknown flow type %d\n", 7557 parent->index, __func__, fsp->flow_type); 7558 ret = -EINVAL; 7559 goto out; 7560 } 7561 7562 /* fill in the assoc data */ 7563 if (fsp->ring_cookie == RX_CLS_FLOW_DISC) { 7564 tp->assoc_data = TCAM_ASSOCDATA_DISC; 7565 } else { 7566 if (fsp->ring_cookie >= np->num_rx_rings) { 7567 netdev_info(np->dev, "niu%d: In %s(): Invalid RX ring %lld\n", 7568 parent->index, __func__, 7569 (long long)fsp->ring_cookie); 7570 ret = -EINVAL; 7571 goto out; 7572 } 7573 tp->assoc_data = (TCAM_ASSOCDATA_TRES_USE_OFFSET | 7574 (fsp->ring_cookie << 7575 TCAM_ASSOCDATA_OFFSET_SHIFT)); 7576 } 7577 7578 err = tcam_write(np, idx, tp->key, tp->key_mask); 7579 if (err) { 7580 ret = -EINVAL; 7581 goto out; 7582 } 7583 err = tcam_assoc_write(np, idx, tp->assoc_data); 7584 if (err) { 7585 ret = -EINVAL; 7586 goto out; 7587 } 7588 7589 /* validate the entry */ 7590 tp->valid = 1; 7591 np->clas.tcam_valid_entries++; 7592 out: 7593 niu_unlock_parent(np, flags); 7594 7595 return ret; 7596 } 7597 7598 static int niu_del_ethtool_tcam_entry(struct niu *np, u32 loc) 7599 { 7600 struct niu_parent *parent = np->parent; 7601 struct niu_tcam_entry *tp; 7602 u16 idx; 7603 unsigned long flags; 7604 u64 class; 7605 int ret = 0; 7606 7607 if (loc >= tcam_get_size(np)) 7608 return -EINVAL; 7609 7610 niu_lock_parent(np, flags); 7611 7612 idx = tcam_get_index(np, loc); 7613 tp = &parent->tcam[idx]; 7614 7615 /* if the entry is of a user defined class, then update*/ 7616 class = (tp->key[0] & TCAM_V4KEY0_CLASS_CODE) >> 7617 TCAM_V4KEY0_CLASS_CODE_SHIFT; 7618 7619 if (class >= CLASS_CODE_USER_PROG1 && class <= CLASS_CODE_USER_PROG4) { 7620 int i; 7621 for (i = 0; i < NIU_L3_PROG_CLS; i++) { 7622 if (parent->l3_cls[i] == class) { 7623 parent->l3_cls_refcnt[i]--; 7624 if (!parent->l3_cls_refcnt[i]) { 7625 /* disable class */ 7626 ret = tcam_user_ip_class_enable(np, 7627 class, 7628 0); 7629 if (ret) 7630 goto out; 7631 parent->l3_cls[i] = 0; 7632 parent->l3_cls_pid[i] = 0; 7633 } 7634 break; 7635 } 7636 } 7637 if (i == NIU_L3_PROG_CLS) { 7638 netdev_info(np->dev, "niu%d: In %s(): Usr class 0x%llx not found\n", 7639 parent->index, __func__, 7640 (unsigned long long)class); 7641 ret = -EINVAL; 7642 goto out; 7643 } 7644 } 7645 7646 ret = tcam_flush(np, idx); 7647 if (ret) 7648 goto out; 7649 7650 /* invalidate the entry */ 7651 tp->valid = 0; 7652 np->clas.tcam_valid_entries--; 7653 out: 7654 niu_unlock_parent(np, flags); 7655 7656 return ret; 7657 } 7658 7659 static int niu_set_nfc(struct net_device *dev, struct ethtool_rxnfc *cmd) 7660 { 7661 struct niu *np = netdev_priv(dev); 7662 int ret = 0; 7663 7664 switch (cmd->cmd) { 7665 case ETHTOOL_SRXFH: 7666 ret = niu_set_hash_opts(np, cmd); 7667 break; 7668 case ETHTOOL_SRXCLSRLINS: 7669 ret = niu_add_ethtool_tcam_entry(np, cmd); 7670 break; 7671 case ETHTOOL_SRXCLSRLDEL: 7672 ret = niu_del_ethtool_tcam_entry(np, cmd->fs.location); 7673 break; 7674 default: 7675 ret = -EINVAL; 7676 break; 7677 } 7678 7679 return ret; 7680 } 7681 7682 static const struct { 7683 const char string[ETH_GSTRING_LEN]; 7684 } niu_xmac_stat_keys[] = { 7685 { "tx_frames" }, 7686 { "tx_bytes" }, 7687 { "tx_fifo_errors" }, 7688 { "tx_overflow_errors" }, 7689 { "tx_max_pkt_size_errors" }, 7690 { "tx_underflow_errors" }, 7691 { "rx_local_faults" }, 7692 { "rx_remote_faults" }, 7693 { "rx_link_faults" }, 7694 { "rx_align_errors" }, 7695 { "rx_frags" }, 7696 { "rx_mcasts" }, 7697 { "rx_bcasts" }, 7698 { "rx_hist_cnt1" }, 7699 { "rx_hist_cnt2" }, 7700 { "rx_hist_cnt3" }, 7701 { "rx_hist_cnt4" }, 7702 { "rx_hist_cnt5" }, 7703 { "rx_hist_cnt6" }, 7704 { "rx_hist_cnt7" }, 7705 { "rx_octets" }, 7706 { "rx_code_violations" }, 7707 { "rx_len_errors" }, 7708 { "rx_crc_errors" }, 7709 { "rx_underflows" }, 7710 { "rx_overflows" }, 7711 { "pause_off_state" }, 7712 { "pause_on_state" }, 7713 { "pause_received" }, 7714 }; 7715 7716 #define NUM_XMAC_STAT_KEYS ARRAY_SIZE(niu_xmac_stat_keys) 7717 7718 static const struct { 7719 const char string[ETH_GSTRING_LEN]; 7720 } niu_bmac_stat_keys[] = { 7721 { "tx_underflow_errors" }, 7722 { "tx_max_pkt_size_errors" }, 7723 { "tx_bytes" }, 7724 { "tx_frames" }, 7725 { "rx_overflows" }, 7726 { "rx_frames" }, 7727 { "rx_align_errors" }, 7728 { "rx_crc_errors" }, 7729 { "rx_len_errors" }, 7730 { "pause_off_state" }, 7731 { "pause_on_state" }, 7732 { "pause_received" }, 7733 }; 7734 7735 #define NUM_BMAC_STAT_KEYS ARRAY_SIZE(niu_bmac_stat_keys) 7736 7737 static const struct { 7738 const char string[ETH_GSTRING_LEN]; 7739 } niu_rxchan_stat_keys[] = { 7740 { "rx_channel" }, 7741 { "rx_packets" }, 7742 { "rx_bytes" }, 7743 { "rx_dropped" }, 7744 { "rx_errors" }, 7745 }; 7746 7747 #define NUM_RXCHAN_STAT_KEYS ARRAY_SIZE(niu_rxchan_stat_keys) 7748 7749 static const struct { 7750 const char string[ETH_GSTRING_LEN]; 7751 } niu_txchan_stat_keys[] = { 7752 { "tx_channel" }, 7753 { "tx_packets" }, 7754 { "tx_bytes" }, 7755 { "tx_errors" }, 7756 }; 7757 7758 #define NUM_TXCHAN_STAT_KEYS ARRAY_SIZE(niu_txchan_stat_keys) 7759 7760 static void niu_get_strings(struct net_device *dev, u32 stringset, u8 *data) 7761 { 7762 struct niu *np = netdev_priv(dev); 7763 int i; 7764 7765 if (stringset != ETH_SS_STATS) 7766 return; 7767 7768 if (np->flags & NIU_FLAGS_XMAC) { 7769 memcpy(data, niu_xmac_stat_keys, 7770 sizeof(niu_xmac_stat_keys)); 7771 data += sizeof(niu_xmac_stat_keys); 7772 } else { 7773 memcpy(data, niu_bmac_stat_keys, 7774 sizeof(niu_bmac_stat_keys)); 7775 data += sizeof(niu_bmac_stat_keys); 7776 } 7777 for (i = 0; i < np->num_rx_rings; i++) { 7778 memcpy(data, niu_rxchan_stat_keys, 7779 sizeof(niu_rxchan_stat_keys)); 7780 data += sizeof(niu_rxchan_stat_keys); 7781 } 7782 for (i = 0; i < np->num_tx_rings; i++) { 7783 memcpy(data, niu_txchan_stat_keys, 7784 sizeof(niu_txchan_stat_keys)); 7785 data += sizeof(niu_txchan_stat_keys); 7786 } 7787 } 7788 7789 static int niu_get_sset_count(struct net_device *dev, int stringset) 7790 { 7791 struct niu *np = netdev_priv(dev); 7792 7793 if (stringset != ETH_SS_STATS) 7794 return -EINVAL; 7795 7796 return (np->flags & NIU_FLAGS_XMAC ? 7797 NUM_XMAC_STAT_KEYS : 7798 NUM_BMAC_STAT_KEYS) + 7799 (np->num_rx_rings * NUM_RXCHAN_STAT_KEYS) + 7800 (np->num_tx_rings * NUM_TXCHAN_STAT_KEYS); 7801 } 7802 7803 static void niu_get_ethtool_stats(struct net_device *dev, 7804 struct ethtool_stats *stats, u64 *data) 7805 { 7806 struct niu *np = netdev_priv(dev); 7807 int i; 7808 7809 niu_sync_mac_stats(np); 7810 if (np->flags & NIU_FLAGS_XMAC) { 7811 memcpy(data, &np->mac_stats.xmac, 7812 sizeof(struct niu_xmac_stats)); 7813 data += (sizeof(struct niu_xmac_stats) / sizeof(u64)); 7814 } else { 7815 memcpy(data, &np->mac_stats.bmac, 7816 sizeof(struct niu_bmac_stats)); 7817 data += (sizeof(struct niu_bmac_stats) / sizeof(u64)); 7818 } 7819 for (i = 0; i < np->num_rx_rings; i++) { 7820 struct rx_ring_info *rp = &np->rx_rings[i]; 7821 7822 niu_sync_rx_discard_stats(np, rp, 0); 7823 7824 data[0] = rp->rx_channel; 7825 data[1] = rp->rx_packets; 7826 data[2] = rp->rx_bytes; 7827 data[3] = rp->rx_dropped; 7828 data[4] = rp->rx_errors; 7829 data += 5; 7830 } 7831 for (i = 0; i < np->num_tx_rings; i++) { 7832 struct tx_ring_info *rp = &np->tx_rings[i]; 7833 7834 data[0] = rp->tx_channel; 7835 data[1] = rp->tx_packets; 7836 data[2] = rp->tx_bytes; 7837 data[3] = rp->tx_errors; 7838 data += 4; 7839 } 7840 } 7841 7842 static u64 niu_led_state_save(struct niu *np) 7843 { 7844 if (np->flags & NIU_FLAGS_XMAC) 7845 return nr64_mac(XMAC_CONFIG); 7846 else 7847 return nr64_mac(BMAC_XIF_CONFIG); 7848 } 7849 7850 static void niu_led_state_restore(struct niu *np, u64 val) 7851 { 7852 if (np->flags & NIU_FLAGS_XMAC) 7853 nw64_mac(XMAC_CONFIG, val); 7854 else 7855 nw64_mac(BMAC_XIF_CONFIG, val); 7856 } 7857 7858 static void niu_force_led(struct niu *np, int on) 7859 { 7860 u64 val, reg, bit; 7861 7862 if (np->flags & NIU_FLAGS_XMAC) { 7863 reg = XMAC_CONFIG; 7864 bit = XMAC_CONFIG_FORCE_LED_ON; 7865 } else { 7866 reg = BMAC_XIF_CONFIG; 7867 bit = BMAC_XIF_CONFIG_LINK_LED; 7868 } 7869 7870 val = nr64_mac(reg); 7871 if (on) 7872 val |= bit; 7873 else 7874 val &= ~bit; 7875 nw64_mac(reg, val); 7876 } 7877 7878 static int niu_set_phys_id(struct net_device *dev, 7879 enum ethtool_phys_id_state state) 7880 7881 { 7882 struct niu *np = netdev_priv(dev); 7883 7884 if (!netif_running(dev)) 7885 return -EAGAIN; 7886 7887 switch (state) { 7888 case ETHTOOL_ID_ACTIVE: 7889 np->orig_led_state = niu_led_state_save(np); 7890 return 1; /* cycle on/off once per second */ 7891 7892 case ETHTOOL_ID_ON: 7893 niu_force_led(np, 1); 7894 break; 7895 7896 case ETHTOOL_ID_OFF: 7897 niu_force_led(np, 0); 7898 break; 7899 7900 case ETHTOOL_ID_INACTIVE: 7901 niu_led_state_restore(np, np->orig_led_state); 7902 } 7903 7904 return 0; 7905 } 7906 7907 static const struct ethtool_ops niu_ethtool_ops = { 7908 .get_drvinfo = niu_get_drvinfo, 7909 .get_link = ethtool_op_get_link, 7910 .get_msglevel = niu_get_msglevel, 7911 .set_msglevel = niu_set_msglevel, 7912 .nway_reset = niu_nway_reset, 7913 .get_eeprom_len = niu_get_eeprom_len, 7914 .get_eeprom = niu_get_eeprom, 7915 .get_settings = niu_get_settings, 7916 .set_settings = niu_set_settings, 7917 .get_strings = niu_get_strings, 7918 .get_sset_count = niu_get_sset_count, 7919 .get_ethtool_stats = niu_get_ethtool_stats, 7920 .set_phys_id = niu_set_phys_id, 7921 .get_rxnfc = niu_get_nfc, 7922 .set_rxnfc = niu_set_nfc, 7923 }; 7924 7925 static int niu_ldg_assign_ldn(struct niu *np, struct niu_parent *parent, 7926 int ldg, int ldn) 7927 { 7928 if (ldg < NIU_LDG_MIN || ldg > NIU_LDG_MAX) 7929 return -EINVAL; 7930 if (ldn < 0 || ldn > LDN_MAX) 7931 return -EINVAL; 7932 7933 parent->ldg_map[ldn] = ldg; 7934 7935 if (np->parent->plat_type == PLAT_TYPE_NIU) { 7936 /* On N2 NIU, the ldn-->ldg assignments are setup and fixed by 7937 * the firmware, and we're not supposed to change them. 7938 * Validate the mapping, because if it's wrong we probably 7939 * won't get any interrupts and that's painful to debug. 7940 */ 7941 if (nr64(LDG_NUM(ldn)) != ldg) { 7942 dev_err(np->device, "Port %u, mis-matched LDG assignment for ldn %d, should be %d is %llu\n", 7943 np->port, ldn, ldg, 7944 (unsigned long long) nr64(LDG_NUM(ldn))); 7945 return -EINVAL; 7946 } 7947 } else 7948 nw64(LDG_NUM(ldn), ldg); 7949 7950 return 0; 7951 } 7952 7953 static int niu_set_ldg_timer_res(struct niu *np, int res) 7954 { 7955 if (res < 0 || res > LDG_TIMER_RES_VAL) 7956 return -EINVAL; 7957 7958 7959 nw64(LDG_TIMER_RES, res); 7960 7961 return 0; 7962 } 7963 7964 static int niu_set_ldg_sid(struct niu *np, int ldg, int func, int vector) 7965 { 7966 if ((ldg < NIU_LDG_MIN || ldg > NIU_LDG_MAX) || 7967 (func < 0 || func > 3) || 7968 (vector < 0 || vector > 0x1f)) 7969 return -EINVAL; 7970 7971 nw64(SID(ldg), (func << SID_FUNC_SHIFT) | vector); 7972 7973 return 0; 7974 } 7975 7976 static int niu_pci_eeprom_read(struct niu *np, u32 addr) 7977 { 7978 u64 frame, frame_base = (ESPC_PIO_STAT_READ_START | 7979 (addr << ESPC_PIO_STAT_ADDR_SHIFT)); 7980 int limit; 7981 7982 if (addr > (ESPC_PIO_STAT_ADDR >> ESPC_PIO_STAT_ADDR_SHIFT)) 7983 return -EINVAL; 7984 7985 frame = frame_base; 7986 nw64(ESPC_PIO_STAT, frame); 7987 limit = 64; 7988 do { 7989 udelay(5); 7990 frame = nr64(ESPC_PIO_STAT); 7991 if (frame & ESPC_PIO_STAT_READ_END) 7992 break; 7993 } while (limit--); 7994 if (!(frame & ESPC_PIO_STAT_READ_END)) { 7995 dev_err(np->device, "EEPROM read timeout frame[%llx]\n", 7996 (unsigned long long) frame); 7997 return -ENODEV; 7998 } 7999 8000 frame = frame_base; 8001 nw64(ESPC_PIO_STAT, frame); 8002 limit = 64; 8003 do { 8004 udelay(5); 8005 frame = nr64(ESPC_PIO_STAT); 8006 if (frame & ESPC_PIO_STAT_READ_END) 8007 break; 8008 } while (limit--); 8009 if (!(frame & ESPC_PIO_STAT_READ_END)) { 8010 dev_err(np->device, "EEPROM read timeout frame[%llx]\n", 8011 (unsigned long long) frame); 8012 return -ENODEV; 8013 } 8014 8015 frame = nr64(ESPC_PIO_STAT); 8016 return (frame & ESPC_PIO_STAT_DATA) >> ESPC_PIO_STAT_DATA_SHIFT; 8017 } 8018 8019 static int niu_pci_eeprom_read16(struct niu *np, u32 off) 8020 { 8021 int err = niu_pci_eeprom_read(np, off); 8022 u16 val; 8023 8024 if (err < 0) 8025 return err; 8026 val = (err << 8); 8027 err = niu_pci_eeprom_read(np, off + 1); 8028 if (err < 0) 8029 return err; 8030 val |= (err & 0xff); 8031 8032 return val; 8033 } 8034 8035 static int niu_pci_eeprom_read16_swp(struct niu *np, u32 off) 8036 { 8037 int err = niu_pci_eeprom_read(np, off); 8038 u16 val; 8039 8040 if (err < 0) 8041 return err; 8042 8043 val = (err & 0xff); 8044 err = niu_pci_eeprom_read(np, off + 1); 8045 if (err < 0) 8046 return err; 8047 8048 val |= (err & 0xff) << 8; 8049 8050 return val; 8051 } 8052 8053 static int niu_pci_vpd_get_propname(struct niu *np, u32 off, char *namebuf, 8054 int namebuf_len) 8055 { 8056 int i; 8057 8058 for (i = 0; i < namebuf_len; i++) { 8059 int err = niu_pci_eeprom_read(np, off + i); 8060 if (err < 0) 8061 return err; 8062 *namebuf++ = err; 8063 if (!err) 8064 break; 8065 } 8066 if (i >= namebuf_len) 8067 return -EINVAL; 8068 8069 return i + 1; 8070 } 8071 8072 static void niu_vpd_parse_version(struct niu *np) 8073 { 8074 struct niu_vpd *vpd = &np->vpd; 8075 int len = strlen(vpd->version) + 1; 8076 const char *s = vpd->version; 8077 int i; 8078 8079 for (i = 0; i < len - 5; i++) { 8080 if (!strncmp(s + i, "FCode ", 6)) 8081 break; 8082 } 8083 if (i >= len - 5) 8084 return; 8085 8086 s += i + 5; 8087 sscanf(s, "%d.%d", &vpd->fcode_major, &vpd->fcode_minor); 8088 8089 netif_printk(np, probe, KERN_DEBUG, np->dev, 8090 "VPD_SCAN: FCODE major(%d) minor(%d)\n", 8091 vpd->fcode_major, vpd->fcode_minor); 8092 if (vpd->fcode_major > NIU_VPD_MIN_MAJOR || 8093 (vpd->fcode_major == NIU_VPD_MIN_MAJOR && 8094 vpd->fcode_minor >= NIU_VPD_MIN_MINOR)) 8095 np->flags |= NIU_FLAGS_VPD_VALID; 8096 } 8097 8098 /* ESPC_PIO_EN_ENABLE must be set */ 8099 static int niu_pci_vpd_scan_props(struct niu *np, u32 start, u32 end) 8100 { 8101 unsigned int found_mask = 0; 8102 #define FOUND_MASK_MODEL 0x00000001 8103 #define FOUND_MASK_BMODEL 0x00000002 8104 #define FOUND_MASK_VERS 0x00000004 8105 #define FOUND_MASK_MAC 0x00000008 8106 #define FOUND_MASK_NMAC 0x00000010 8107 #define FOUND_MASK_PHY 0x00000020 8108 #define FOUND_MASK_ALL 0x0000003f 8109 8110 netif_printk(np, probe, KERN_DEBUG, np->dev, 8111 "VPD_SCAN: start[%x] end[%x]\n", start, end); 8112 while (start < end) { 8113 int len, err, prop_len; 8114 char namebuf[64]; 8115 u8 *prop_buf; 8116 int max_len; 8117 8118 if (found_mask == FOUND_MASK_ALL) { 8119 niu_vpd_parse_version(np); 8120 return 1; 8121 } 8122 8123 err = niu_pci_eeprom_read(np, start + 2); 8124 if (err < 0) 8125 return err; 8126 len = err; 8127 start += 3; 8128 8129 prop_len = niu_pci_eeprom_read(np, start + 4); 8130 err = niu_pci_vpd_get_propname(np, start + 5, namebuf, 64); 8131 if (err < 0) 8132 return err; 8133 8134 prop_buf = NULL; 8135 max_len = 0; 8136 if (!strcmp(namebuf, "model")) { 8137 prop_buf = np->vpd.model; 8138 max_len = NIU_VPD_MODEL_MAX; 8139 found_mask |= FOUND_MASK_MODEL; 8140 } else if (!strcmp(namebuf, "board-model")) { 8141 prop_buf = np->vpd.board_model; 8142 max_len = NIU_VPD_BD_MODEL_MAX; 8143 found_mask |= FOUND_MASK_BMODEL; 8144 } else if (!strcmp(namebuf, "version")) { 8145 prop_buf = np->vpd.version; 8146 max_len = NIU_VPD_VERSION_MAX; 8147 found_mask |= FOUND_MASK_VERS; 8148 } else if (!strcmp(namebuf, "local-mac-address")) { 8149 prop_buf = np->vpd.local_mac; 8150 max_len = ETH_ALEN; 8151 found_mask |= FOUND_MASK_MAC; 8152 } else if (!strcmp(namebuf, "num-mac-addresses")) { 8153 prop_buf = &np->vpd.mac_num; 8154 max_len = 1; 8155 found_mask |= FOUND_MASK_NMAC; 8156 } else if (!strcmp(namebuf, "phy-type")) { 8157 prop_buf = np->vpd.phy_type; 8158 max_len = NIU_VPD_PHY_TYPE_MAX; 8159 found_mask |= FOUND_MASK_PHY; 8160 } 8161 8162 if (max_len && prop_len > max_len) { 8163 dev_err(np->device, "Property '%s' length (%d) is too long\n", namebuf, prop_len); 8164 return -EINVAL; 8165 } 8166 8167 if (prop_buf) { 8168 u32 off = start + 5 + err; 8169 int i; 8170 8171 netif_printk(np, probe, KERN_DEBUG, np->dev, 8172 "VPD_SCAN: Reading in property [%s] len[%d]\n", 8173 namebuf, prop_len); 8174 for (i = 0; i < prop_len; i++) 8175 *prop_buf++ = niu_pci_eeprom_read(np, off + i); 8176 } 8177 8178 start += len; 8179 } 8180 8181 return 0; 8182 } 8183 8184 /* ESPC_PIO_EN_ENABLE must be set */ 8185 static void niu_pci_vpd_fetch(struct niu *np, u32 start) 8186 { 8187 u32 offset; 8188 int err; 8189 8190 err = niu_pci_eeprom_read16_swp(np, start + 1); 8191 if (err < 0) 8192 return; 8193 8194 offset = err + 3; 8195 8196 while (start + offset < ESPC_EEPROM_SIZE) { 8197 u32 here = start + offset; 8198 u32 end; 8199 8200 err = niu_pci_eeprom_read(np, here); 8201 if (err != 0x90) 8202 return; 8203 8204 err = niu_pci_eeprom_read16_swp(np, here + 1); 8205 if (err < 0) 8206 return; 8207 8208 here = start + offset + 3; 8209 end = start + offset + err; 8210 8211 offset += err; 8212 8213 err = niu_pci_vpd_scan_props(np, here, end); 8214 if (err < 0 || err == 1) 8215 return; 8216 } 8217 } 8218 8219 /* ESPC_PIO_EN_ENABLE must be set */ 8220 static u32 niu_pci_vpd_offset(struct niu *np) 8221 { 8222 u32 start = 0, end = ESPC_EEPROM_SIZE, ret; 8223 int err; 8224 8225 while (start < end) { 8226 ret = start; 8227 8228 /* ROM header signature? */ 8229 err = niu_pci_eeprom_read16(np, start + 0); 8230 if (err != 0x55aa) 8231 return 0; 8232 8233 /* Apply offset to PCI data structure. */ 8234 err = niu_pci_eeprom_read16(np, start + 23); 8235 if (err < 0) 8236 return 0; 8237 start += err; 8238 8239 /* Check for "PCIR" signature. */ 8240 err = niu_pci_eeprom_read16(np, start + 0); 8241 if (err != 0x5043) 8242 return 0; 8243 err = niu_pci_eeprom_read16(np, start + 2); 8244 if (err != 0x4952) 8245 return 0; 8246 8247 /* Check for OBP image type. */ 8248 err = niu_pci_eeprom_read(np, start + 20); 8249 if (err < 0) 8250 return 0; 8251 if (err != 0x01) { 8252 err = niu_pci_eeprom_read(np, ret + 2); 8253 if (err < 0) 8254 return 0; 8255 8256 start = ret + (err * 512); 8257 continue; 8258 } 8259 8260 err = niu_pci_eeprom_read16_swp(np, start + 8); 8261 if (err < 0) 8262 return err; 8263 ret += err; 8264 8265 err = niu_pci_eeprom_read(np, ret + 0); 8266 if (err != 0x82) 8267 return 0; 8268 8269 return ret; 8270 } 8271 8272 return 0; 8273 } 8274 8275 static int niu_phy_type_prop_decode(struct niu *np, const char *phy_prop) 8276 { 8277 if (!strcmp(phy_prop, "mif")) { 8278 /* 1G copper, MII */ 8279 np->flags &= ~(NIU_FLAGS_FIBER | 8280 NIU_FLAGS_10G); 8281 np->mac_xcvr = MAC_XCVR_MII; 8282 } else if (!strcmp(phy_prop, "xgf")) { 8283 /* 10G fiber, XPCS */ 8284 np->flags |= (NIU_FLAGS_10G | 8285 NIU_FLAGS_FIBER); 8286 np->mac_xcvr = MAC_XCVR_XPCS; 8287 } else if (!strcmp(phy_prop, "pcs")) { 8288 /* 1G fiber, PCS */ 8289 np->flags &= ~NIU_FLAGS_10G; 8290 np->flags |= NIU_FLAGS_FIBER; 8291 np->mac_xcvr = MAC_XCVR_PCS; 8292 } else if (!strcmp(phy_prop, "xgc")) { 8293 /* 10G copper, XPCS */ 8294 np->flags |= NIU_FLAGS_10G; 8295 np->flags &= ~NIU_FLAGS_FIBER; 8296 np->mac_xcvr = MAC_XCVR_XPCS; 8297 } else if (!strcmp(phy_prop, "xgsd") || !strcmp(phy_prop, "gsd")) { 8298 /* 10G Serdes or 1G Serdes, default to 10G */ 8299 np->flags |= NIU_FLAGS_10G; 8300 np->flags &= ~NIU_FLAGS_FIBER; 8301 np->flags |= NIU_FLAGS_XCVR_SERDES; 8302 np->mac_xcvr = MAC_XCVR_XPCS; 8303 } else { 8304 return -EINVAL; 8305 } 8306 return 0; 8307 } 8308 8309 static int niu_pci_vpd_get_nports(struct niu *np) 8310 { 8311 int ports = 0; 8312 8313 if ((!strcmp(np->vpd.model, NIU_QGC_LP_MDL_STR)) || 8314 (!strcmp(np->vpd.model, NIU_QGC_PEM_MDL_STR)) || 8315 (!strcmp(np->vpd.model, NIU_MARAMBA_MDL_STR)) || 8316 (!strcmp(np->vpd.model, NIU_KIMI_MDL_STR)) || 8317 (!strcmp(np->vpd.model, NIU_ALONSO_MDL_STR))) { 8318 ports = 4; 8319 } else if ((!strcmp(np->vpd.model, NIU_2XGF_LP_MDL_STR)) || 8320 (!strcmp(np->vpd.model, NIU_2XGF_PEM_MDL_STR)) || 8321 (!strcmp(np->vpd.model, NIU_FOXXY_MDL_STR)) || 8322 (!strcmp(np->vpd.model, NIU_2XGF_MRVL_MDL_STR))) { 8323 ports = 2; 8324 } 8325 8326 return ports; 8327 } 8328 8329 static void niu_pci_vpd_validate(struct niu *np) 8330 { 8331 struct net_device *dev = np->dev; 8332 struct niu_vpd *vpd = &np->vpd; 8333 u8 val8; 8334 8335 if (!is_valid_ether_addr(&vpd->local_mac[0])) { 8336 dev_err(np->device, "VPD MAC invalid, falling back to SPROM\n"); 8337 8338 np->flags &= ~NIU_FLAGS_VPD_VALID; 8339 return; 8340 } 8341 8342 if (!strcmp(np->vpd.model, NIU_ALONSO_MDL_STR) || 8343 !strcmp(np->vpd.model, NIU_KIMI_MDL_STR)) { 8344 np->flags |= NIU_FLAGS_10G; 8345 np->flags &= ~NIU_FLAGS_FIBER; 8346 np->flags |= NIU_FLAGS_XCVR_SERDES; 8347 np->mac_xcvr = MAC_XCVR_PCS; 8348 if (np->port > 1) { 8349 np->flags |= NIU_FLAGS_FIBER; 8350 np->flags &= ~NIU_FLAGS_10G; 8351 } 8352 if (np->flags & NIU_FLAGS_10G) 8353 np->mac_xcvr = MAC_XCVR_XPCS; 8354 } else if (!strcmp(np->vpd.model, NIU_FOXXY_MDL_STR)) { 8355 np->flags |= (NIU_FLAGS_10G | NIU_FLAGS_FIBER | 8356 NIU_FLAGS_HOTPLUG_PHY); 8357 } else if (niu_phy_type_prop_decode(np, np->vpd.phy_type)) { 8358 dev_err(np->device, "Illegal phy string [%s]\n", 8359 np->vpd.phy_type); 8360 dev_err(np->device, "Falling back to SPROM\n"); 8361 np->flags &= ~NIU_FLAGS_VPD_VALID; 8362 return; 8363 } 8364 8365 memcpy(dev->dev_addr, vpd->local_mac, ETH_ALEN); 8366 8367 val8 = dev->dev_addr[5]; 8368 dev->dev_addr[5] += np->port; 8369 if (dev->dev_addr[5] < val8) 8370 dev->dev_addr[4]++; 8371 } 8372 8373 static int niu_pci_probe_sprom(struct niu *np) 8374 { 8375 struct net_device *dev = np->dev; 8376 int len, i; 8377 u64 val, sum; 8378 u8 val8; 8379 8380 val = (nr64(ESPC_VER_IMGSZ) & ESPC_VER_IMGSZ_IMGSZ); 8381 val >>= ESPC_VER_IMGSZ_IMGSZ_SHIFT; 8382 len = val / 4; 8383 8384 np->eeprom_len = len; 8385 8386 netif_printk(np, probe, KERN_DEBUG, np->dev, 8387 "SPROM: Image size %llu\n", (unsigned long long)val); 8388 8389 sum = 0; 8390 for (i = 0; i < len; i++) { 8391 val = nr64(ESPC_NCR(i)); 8392 sum += (val >> 0) & 0xff; 8393 sum += (val >> 8) & 0xff; 8394 sum += (val >> 16) & 0xff; 8395 sum += (val >> 24) & 0xff; 8396 } 8397 netif_printk(np, probe, KERN_DEBUG, np->dev, 8398 "SPROM: Checksum %x\n", (int)(sum & 0xff)); 8399 if ((sum & 0xff) != 0xab) { 8400 dev_err(np->device, "Bad SPROM checksum (%x, should be 0xab)\n", (int)(sum & 0xff)); 8401 return -EINVAL; 8402 } 8403 8404 val = nr64(ESPC_PHY_TYPE); 8405 switch (np->port) { 8406 case 0: 8407 val8 = (val & ESPC_PHY_TYPE_PORT0) >> 8408 ESPC_PHY_TYPE_PORT0_SHIFT; 8409 break; 8410 case 1: 8411 val8 = (val & ESPC_PHY_TYPE_PORT1) >> 8412 ESPC_PHY_TYPE_PORT1_SHIFT; 8413 break; 8414 case 2: 8415 val8 = (val & ESPC_PHY_TYPE_PORT2) >> 8416 ESPC_PHY_TYPE_PORT2_SHIFT; 8417 break; 8418 case 3: 8419 val8 = (val & ESPC_PHY_TYPE_PORT3) >> 8420 ESPC_PHY_TYPE_PORT3_SHIFT; 8421 break; 8422 default: 8423 dev_err(np->device, "Bogus port number %u\n", 8424 np->port); 8425 return -EINVAL; 8426 } 8427 netif_printk(np, probe, KERN_DEBUG, np->dev, 8428 "SPROM: PHY type %x\n", val8); 8429 8430 switch (val8) { 8431 case ESPC_PHY_TYPE_1G_COPPER: 8432 /* 1G copper, MII */ 8433 np->flags &= ~(NIU_FLAGS_FIBER | 8434 NIU_FLAGS_10G); 8435 np->mac_xcvr = MAC_XCVR_MII; 8436 break; 8437 8438 case ESPC_PHY_TYPE_1G_FIBER: 8439 /* 1G fiber, PCS */ 8440 np->flags &= ~NIU_FLAGS_10G; 8441 np->flags |= NIU_FLAGS_FIBER; 8442 np->mac_xcvr = MAC_XCVR_PCS; 8443 break; 8444 8445 case ESPC_PHY_TYPE_10G_COPPER: 8446 /* 10G copper, XPCS */ 8447 np->flags |= NIU_FLAGS_10G; 8448 np->flags &= ~NIU_FLAGS_FIBER; 8449 np->mac_xcvr = MAC_XCVR_XPCS; 8450 break; 8451 8452 case ESPC_PHY_TYPE_10G_FIBER: 8453 /* 10G fiber, XPCS */ 8454 np->flags |= (NIU_FLAGS_10G | 8455 NIU_FLAGS_FIBER); 8456 np->mac_xcvr = MAC_XCVR_XPCS; 8457 break; 8458 8459 default: 8460 dev_err(np->device, "Bogus SPROM phy type %u\n", val8); 8461 return -EINVAL; 8462 } 8463 8464 val = nr64(ESPC_MAC_ADDR0); 8465 netif_printk(np, probe, KERN_DEBUG, np->dev, 8466 "SPROM: MAC_ADDR0[%08llx]\n", (unsigned long long)val); 8467 dev->dev_addr[0] = (val >> 0) & 0xff; 8468 dev->dev_addr[1] = (val >> 8) & 0xff; 8469 dev->dev_addr[2] = (val >> 16) & 0xff; 8470 dev->dev_addr[3] = (val >> 24) & 0xff; 8471 8472 val = nr64(ESPC_MAC_ADDR1); 8473 netif_printk(np, probe, KERN_DEBUG, np->dev, 8474 "SPROM: MAC_ADDR1[%08llx]\n", (unsigned long long)val); 8475 dev->dev_addr[4] = (val >> 0) & 0xff; 8476 dev->dev_addr[5] = (val >> 8) & 0xff; 8477 8478 if (!is_valid_ether_addr(&dev->dev_addr[0])) { 8479 dev_err(np->device, "SPROM MAC address invalid [ %pM ]\n", 8480 dev->dev_addr); 8481 return -EINVAL; 8482 } 8483 8484 val8 = dev->dev_addr[5]; 8485 dev->dev_addr[5] += np->port; 8486 if (dev->dev_addr[5] < val8) 8487 dev->dev_addr[4]++; 8488 8489 val = nr64(ESPC_MOD_STR_LEN); 8490 netif_printk(np, probe, KERN_DEBUG, np->dev, 8491 "SPROM: MOD_STR_LEN[%llu]\n", (unsigned long long)val); 8492 if (val >= 8 * 4) 8493 return -EINVAL; 8494 8495 for (i = 0; i < val; i += 4) { 8496 u64 tmp = nr64(ESPC_NCR(5 + (i / 4))); 8497 8498 np->vpd.model[i + 3] = (tmp >> 0) & 0xff; 8499 np->vpd.model[i + 2] = (tmp >> 8) & 0xff; 8500 np->vpd.model[i + 1] = (tmp >> 16) & 0xff; 8501 np->vpd.model[i + 0] = (tmp >> 24) & 0xff; 8502 } 8503 np->vpd.model[val] = '\0'; 8504 8505 val = nr64(ESPC_BD_MOD_STR_LEN); 8506 netif_printk(np, probe, KERN_DEBUG, np->dev, 8507 "SPROM: BD_MOD_STR_LEN[%llu]\n", (unsigned long long)val); 8508 if (val >= 4 * 4) 8509 return -EINVAL; 8510 8511 for (i = 0; i < val; i += 4) { 8512 u64 tmp = nr64(ESPC_NCR(14 + (i / 4))); 8513 8514 np->vpd.board_model[i + 3] = (tmp >> 0) & 0xff; 8515 np->vpd.board_model[i + 2] = (tmp >> 8) & 0xff; 8516 np->vpd.board_model[i + 1] = (tmp >> 16) & 0xff; 8517 np->vpd.board_model[i + 0] = (tmp >> 24) & 0xff; 8518 } 8519 np->vpd.board_model[val] = '\0'; 8520 8521 np->vpd.mac_num = 8522 nr64(ESPC_NUM_PORTS_MACS) & ESPC_NUM_PORTS_MACS_VAL; 8523 netif_printk(np, probe, KERN_DEBUG, np->dev, 8524 "SPROM: NUM_PORTS_MACS[%d]\n", np->vpd.mac_num); 8525 8526 return 0; 8527 } 8528 8529 static int niu_get_and_validate_port(struct niu *np) 8530 { 8531 struct niu_parent *parent = np->parent; 8532 8533 if (np->port <= 1) 8534 np->flags |= NIU_FLAGS_XMAC; 8535 8536 if (!parent->num_ports) { 8537 if (parent->plat_type == PLAT_TYPE_NIU) { 8538 parent->num_ports = 2; 8539 } else { 8540 parent->num_ports = niu_pci_vpd_get_nports(np); 8541 if (!parent->num_ports) { 8542 /* Fall back to SPROM as last resort. 8543 * This will fail on most cards. 8544 */ 8545 parent->num_ports = nr64(ESPC_NUM_PORTS_MACS) & 8546 ESPC_NUM_PORTS_MACS_VAL; 8547 8548 /* All of the current probing methods fail on 8549 * Maramba on-board parts. 8550 */ 8551 if (!parent->num_ports) 8552 parent->num_ports = 4; 8553 } 8554 } 8555 } 8556 8557 if (np->port >= parent->num_ports) 8558 return -ENODEV; 8559 8560 return 0; 8561 } 8562 8563 static int phy_record(struct niu_parent *parent, struct phy_probe_info *p, 8564 int dev_id_1, int dev_id_2, u8 phy_port, int type) 8565 { 8566 u32 id = (dev_id_1 << 16) | dev_id_2; 8567 u8 idx; 8568 8569 if (dev_id_1 < 0 || dev_id_2 < 0) 8570 return 0; 8571 if (type == PHY_TYPE_PMA_PMD || type == PHY_TYPE_PCS) { 8572 /* Because of the NIU_PHY_ID_MASK being applied, the 8704 8573 * test covers the 8706 as well. 8574 */ 8575 if (((id & NIU_PHY_ID_MASK) != NIU_PHY_ID_BCM8704) && 8576 ((id & NIU_PHY_ID_MASK) != NIU_PHY_ID_MRVL88X2011)) 8577 return 0; 8578 } else { 8579 if ((id & NIU_PHY_ID_MASK) != NIU_PHY_ID_BCM5464R) 8580 return 0; 8581 } 8582 8583 pr_info("niu%d: Found PHY %08x type %s at phy_port %u\n", 8584 parent->index, id, 8585 type == PHY_TYPE_PMA_PMD ? "PMA/PMD" : 8586 type == PHY_TYPE_PCS ? "PCS" : "MII", 8587 phy_port); 8588 8589 if (p->cur[type] >= NIU_MAX_PORTS) { 8590 pr_err("Too many PHY ports\n"); 8591 return -EINVAL; 8592 } 8593 idx = p->cur[type]; 8594 p->phy_id[type][idx] = id; 8595 p->phy_port[type][idx] = phy_port; 8596 p->cur[type] = idx + 1; 8597 return 0; 8598 } 8599 8600 static int port_has_10g(struct phy_probe_info *p, int port) 8601 { 8602 int i; 8603 8604 for (i = 0; i < p->cur[PHY_TYPE_PMA_PMD]; i++) { 8605 if (p->phy_port[PHY_TYPE_PMA_PMD][i] == port) 8606 return 1; 8607 } 8608 for (i = 0; i < p->cur[PHY_TYPE_PCS]; i++) { 8609 if (p->phy_port[PHY_TYPE_PCS][i] == port) 8610 return 1; 8611 } 8612 8613 return 0; 8614 } 8615 8616 static int count_10g_ports(struct phy_probe_info *p, int *lowest) 8617 { 8618 int port, cnt; 8619 8620 cnt = 0; 8621 *lowest = 32; 8622 for (port = 8; port < 32; port++) { 8623 if (port_has_10g(p, port)) { 8624 if (!cnt) 8625 *lowest = port; 8626 cnt++; 8627 } 8628 } 8629 8630 return cnt; 8631 } 8632 8633 static int count_1g_ports(struct phy_probe_info *p, int *lowest) 8634 { 8635 *lowest = 32; 8636 if (p->cur[PHY_TYPE_MII]) 8637 *lowest = p->phy_port[PHY_TYPE_MII][0]; 8638 8639 return p->cur[PHY_TYPE_MII]; 8640 } 8641 8642 static void niu_n2_divide_channels(struct niu_parent *parent) 8643 { 8644 int num_ports = parent->num_ports; 8645 int i; 8646 8647 for (i = 0; i < num_ports; i++) { 8648 parent->rxchan_per_port[i] = (16 / num_ports); 8649 parent->txchan_per_port[i] = (16 / num_ports); 8650 8651 pr_info("niu%d: Port %u [%u RX chans] [%u TX chans]\n", 8652 parent->index, i, 8653 parent->rxchan_per_port[i], 8654 parent->txchan_per_port[i]); 8655 } 8656 } 8657 8658 static void niu_divide_channels(struct niu_parent *parent, 8659 int num_10g, int num_1g) 8660 { 8661 int num_ports = parent->num_ports; 8662 int rx_chans_per_10g, rx_chans_per_1g; 8663 int tx_chans_per_10g, tx_chans_per_1g; 8664 int i, tot_rx, tot_tx; 8665 8666 if (!num_10g || !num_1g) { 8667 rx_chans_per_10g = rx_chans_per_1g = 8668 (NIU_NUM_RXCHAN / num_ports); 8669 tx_chans_per_10g = tx_chans_per_1g = 8670 (NIU_NUM_TXCHAN / num_ports); 8671 } else { 8672 rx_chans_per_1g = NIU_NUM_RXCHAN / 8; 8673 rx_chans_per_10g = (NIU_NUM_RXCHAN - 8674 (rx_chans_per_1g * num_1g)) / 8675 num_10g; 8676 8677 tx_chans_per_1g = NIU_NUM_TXCHAN / 6; 8678 tx_chans_per_10g = (NIU_NUM_TXCHAN - 8679 (tx_chans_per_1g * num_1g)) / 8680 num_10g; 8681 } 8682 8683 tot_rx = tot_tx = 0; 8684 for (i = 0; i < num_ports; i++) { 8685 int type = phy_decode(parent->port_phy, i); 8686 8687 if (type == PORT_TYPE_10G) { 8688 parent->rxchan_per_port[i] = rx_chans_per_10g; 8689 parent->txchan_per_port[i] = tx_chans_per_10g; 8690 } else { 8691 parent->rxchan_per_port[i] = rx_chans_per_1g; 8692 parent->txchan_per_port[i] = tx_chans_per_1g; 8693 } 8694 pr_info("niu%d: Port %u [%u RX chans] [%u TX chans]\n", 8695 parent->index, i, 8696 parent->rxchan_per_port[i], 8697 parent->txchan_per_port[i]); 8698 tot_rx += parent->rxchan_per_port[i]; 8699 tot_tx += parent->txchan_per_port[i]; 8700 } 8701 8702 if (tot_rx > NIU_NUM_RXCHAN) { 8703 pr_err("niu%d: Too many RX channels (%d), resetting to one per port\n", 8704 parent->index, tot_rx); 8705 for (i = 0; i < num_ports; i++) 8706 parent->rxchan_per_port[i] = 1; 8707 } 8708 if (tot_tx > NIU_NUM_TXCHAN) { 8709 pr_err("niu%d: Too many TX channels (%d), resetting to one per port\n", 8710 parent->index, tot_tx); 8711 for (i = 0; i < num_ports; i++) 8712 parent->txchan_per_port[i] = 1; 8713 } 8714 if (tot_rx < NIU_NUM_RXCHAN || tot_tx < NIU_NUM_TXCHAN) { 8715 pr_warn("niu%d: Driver bug, wasted channels, RX[%d] TX[%d]\n", 8716 parent->index, tot_rx, tot_tx); 8717 } 8718 } 8719 8720 static void niu_divide_rdc_groups(struct niu_parent *parent, 8721 int num_10g, int num_1g) 8722 { 8723 int i, num_ports = parent->num_ports; 8724 int rdc_group, rdc_groups_per_port; 8725 int rdc_channel_base; 8726 8727 rdc_group = 0; 8728 rdc_groups_per_port = NIU_NUM_RDC_TABLES / num_ports; 8729 8730 rdc_channel_base = 0; 8731 8732 for (i = 0; i < num_ports; i++) { 8733 struct niu_rdc_tables *tp = &parent->rdc_group_cfg[i]; 8734 int grp, num_channels = parent->rxchan_per_port[i]; 8735 int this_channel_offset; 8736 8737 tp->first_table_num = rdc_group; 8738 tp->num_tables = rdc_groups_per_port; 8739 this_channel_offset = 0; 8740 for (grp = 0; grp < tp->num_tables; grp++) { 8741 struct rdc_table *rt = &tp->tables[grp]; 8742 int slot; 8743 8744 pr_info("niu%d: Port %d RDC tbl(%d) [ ", 8745 parent->index, i, tp->first_table_num + grp); 8746 for (slot = 0; slot < NIU_RDC_TABLE_SLOTS; slot++) { 8747 rt->rxdma_channel[slot] = 8748 rdc_channel_base + this_channel_offset; 8749 8750 pr_cont("%d ", rt->rxdma_channel[slot]); 8751 8752 if (++this_channel_offset == num_channels) 8753 this_channel_offset = 0; 8754 } 8755 pr_cont("]\n"); 8756 } 8757 8758 parent->rdc_default[i] = rdc_channel_base; 8759 8760 rdc_channel_base += num_channels; 8761 rdc_group += rdc_groups_per_port; 8762 } 8763 } 8764 8765 static int fill_phy_probe_info(struct niu *np, struct niu_parent *parent, 8766 struct phy_probe_info *info) 8767 { 8768 unsigned long flags; 8769 int port, err; 8770 8771 memset(info, 0, sizeof(*info)); 8772 8773 /* Port 0 to 7 are reserved for onboard Serdes, probe the rest. */ 8774 niu_lock_parent(np, flags); 8775 err = 0; 8776 for (port = 8; port < 32; port++) { 8777 int dev_id_1, dev_id_2; 8778 8779 dev_id_1 = mdio_read(np, port, 8780 NIU_PMA_PMD_DEV_ADDR, MII_PHYSID1); 8781 dev_id_2 = mdio_read(np, port, 8782 NIU_PMA_PMD_DEV_ADDR, MII_PHYSID2); 8783 err = phy_record(parent, info, dev_id_1, dev_id_2, port, 8784 PHY_TYPE_PMA_PMD); 8785 if (err) 8786 break; 8787 dev_id_1 = mdio_read(np, port, 8788 NIU_PCS_DEV_ADDR, MII_PHYSID1); 8789 dev_id_2 = mdio_read(np, port, 8790 NIU_PCS_DEV_ADDR, MII_PHYSID2); 8791 err = phy_record(parent, info, dev_id_1, dev_id_2, port, 8792 PHY_TYPE_PCS); 8793 if (err) 8794 break; 8795 dev_id_1 = mii_read(np, port, MII_PHYSID1); 8796 dev_id_2 = mii_read(np, port, MII_PHYSID2); 8797 err = phy_record(parent, info, dev_id_1, dev_id_2, port, 8798 PHY_TYPE_MII); 8799 if (err) 8800 break; 8801 } 8802 niu_unlock_parent(np, flags); 8803 8804 return err; 8805 } 8806 8807 static int walk_phys(struct niu *np, struct niu_parent *parent) 8808 { 8809 struct phy_probe_info *info = &parent->phy_probe_info; 8810 int lowest_10g, lowest_1g; 8811 int num_10g, num_1g; 8812 u32 val; 8813 int err; 8814 8815 num_10g = num_1g = 0; 8816 8817 if (!strcmp(np->vpd.model, NIU_ALONSO_MDL_STR) || 8818 !strcmp(np->vpd.model, NIU_KIMI_MDL_STR)) { 8819 num_10g = 0; 8820 num_1g = 2; 8821 parent->plat_type = PLAT_TYPE_ATCA_CP3220; 8822 parent->num_ports = 4; 8823 val = (phy_encode(PORT_TYPE_1G, 0) | 8824 phy_encode(PORT_TYPE_1G, 1) | 8825 phy_encode(PORT_TYPE_1G, 2) | 8826 phy_encode(PORT_TYPE_1G, 3)); 8827 } else if (!strcmp(np->vpd.model, NIU_FOXXY_MDL_STR)) { 8828 num_10g = 2; 8829 num_1g = 0; 8830 parent->num_ports = 2; 8831 val = (phy_encode(PORT_TYPE_10G, 0) | 8832 phy_encode(PORT_TYPE_10G, 1)); 8833 } else if ((np->flags & NIU_FLAGS_XCVR_SERDES) && 8834 (parent->plat_type == PLAT_TYPE_NIU)) { 8835 /* this is the Monza case */ 8836 if (np->flags & NIU_FLAGS_10G) { 8837 val = (phy_encode(PORT_TYPE_10G, 0) | 8838 phy_encode(PORT_TYPE_10G, 1)); 8839 } else { 8840 val = (phy_encode(PORT_TYPE_1G, 0) | 8841 phy_encode(PORT_TYPE_1G, 1)); 8842 } 8843 } else { 8844 err = fill_phy_probe_info(np, parent, info); 8845 if (err) 8846 return err; 8847 8848 num_10g = count_10g_ports(info, &lowest_10g); 8849 num_1g = count_1g_ports(info, &lowest_1g); 8850 8851 switch ((num_10g << 4) | num_1g) { 8852 case 0x24: 8853 if (lowest_1g == 10) 8854 parent->plat_type = PLAT_TYPE_VF_P0; 8855 else if (lowest_1g == 26) 8856 parent->plat_type = PLAT_TYPE_VF_P1; 8857 else 8858 goto unknown_vg_1g_port; 8859 8860 /* fallthru */ 8861 case 0x22: 8862 val = (phy_encode(PORT_TYPE_10G, 0) | 8863 phy_encode(PORT_TYPE_10G, 1) | 8864 phy_encode(PORT_TYPE_1G, 2) | 8865 phy_encode(PORT_TYPE_1G, 3)); 8866 break; 8867 8868 case 0x20: 8869 val = (phy_encode(PORT_TYPE_10G, 0) | 8870 phy_encode(PORT_TYPE_10G, 1)); 8871 break; 8872 8873 case 0x10: 8874 val = phy_encode(PORT_TYPE_10G, np->port); 8875 break; 8876 8877 case 0x14: 8878 if (lowest_1g == 10) 8879 parent->plat_type = PLAT_TYPE_VF_P0; 8880 else if (lowest_1g == 26) 8881 parent->plat_type = PLAT_TYPE_VF_P1; 8882 else 8883 goto unknown_vg_1g_port; 8884 8885 /* fallthru */ 8886 case 0x13: 8887 if ((lowest_10g & 0x7) == 0) 8888 val = (phy_encode(PORT_TYPE_10G, 0) | 8889 phy_encode(PORT_TYPE_1G, 1) | 8890 phy_encode(PORT_TYPE_1G, 2) | 8891 phy_encode(PORT_TYPE_1G, 3)); 8892 else 8893 val = (phy_encode(PORT_TYPE_1G, 0) | 8894 phy_encode(PORT_TYPE_10G, 1) | 8895 phy_encode(PORT_TYPE_1G, 2) | 8896 phy_encode(PORT_TYPE_1G, 3)); 8897 break; 8898 8899 case 0x04: 8900 if (lowest_1g == 10) 8901 parent->plat_type = PLAT_TYPE_VF_P0; 8902 else if (lowest_1g == 26) 8903 parent->plat_type = PLAT_TYPE_VF_P1; 8904 else 8905 goto unknown_vg_1g_port; 8906 8907 val = (phy_encode(PORT_TYPE_1G, 0) | 8908 phy_encode(PORT_TYPE_1G, 1) | 8909 phy_encode(PORT_TYPE_1G, 2) | 8910 phy_encode(PORT_TYPE_1G, 3)); 8911 break; 8912 8913 default: 8914 pr_err("Unsupported port config 10G[%d] 1G[%d]\n", 8915 num_10g, num_1g); 8916 return -EINVAL; 8917 } 8918 } 8919 8920 parent->port_phy = val; 8921 8922 if (parent->plat_type == PLAT_TYPE_NIU) 8923 niu_n2_divide_channels(parent); 8924 else 8925 niu_divide_channels(parent, num_10g, num_1g); 8926 8927 niu_divide_rdc_groups(parent, num_10g, num_1g); 8928 8929 return 0; 8930 8931 unknown_vg_1g_port: 8932 pr_err("Cannot identify platform type, 1gport=%d\n", lowest_1g); 8933 return -EINVAL; 8934 } 8935 8936 static int niu_probe_ports(struct niu *np) 8937 { 8938 struct niu_parent *parent = np->parent; 8939 int err, i; 8940 8941 if (parent->port_phy == PORT_PHY_UNKNOWN) { 8942 err = walk_phys(np, parent); 8943 if (err) 8944 return err; 8945 8946 niu_set_ldg_timer_res(np, 2); 8947 for (i = 0; i <= LDN_MAX; i++) 8948 niu_ldn_irq_enable(np, i, 0); 8949 } 8950 8951 if (parent->port_phy == PORT_PHY_INVALID) 8952 return -EINVAL; 8953 8954 return 0; 8955 } 8956 8957 static int niu_classifier_swstate_init(struct niu *np) 8958 { 8959 struct niu_classifier *cp = &np->clas; 8960 8961 cp->tcam_top = (u16) np->port; 8962 cp->tcam_sz = np->parent->tcam_num_entries / np->parent->num_ports; 8963 cp->h1_init = 0xffffffff; 8964 cp->h2_init = 0xffff; 8965 8966 return fflp_early_init(np); 8967 } 8968 8969 static void niu_link_config_init(struct niu *np) 8970 { 8971 struct niu_link_config *lp = &np->link_config; 8972 8973 lp->advertising = (ADVERTISED_10baseT_Half | 8974 ADVERTISED_10baseT_Full | 8975 ADVERTISED_100baseT_Half | 8976 ADVERTISED_100baseT_Full | 8977 ADVERTISED_1000baseT_Half | 8978 ADVERTISED_1000baseT_Full | 8979 ADVERTISED_10000baseT_Full | 8980 ADVERTISED_Autoneg); 8981 lp->speed = lp->active_speed = SPEED_INVALID; 8982 lp->duplex = DUPLEX_FULL; 8983 lp->active_duplex = DUPLEX_INVALID; 8984 lp->autoneg = 1; 8985 #if 0 8986 lp->loopback_mode = LOOPBACK_MAC; 8987 lp->active_speed = SPEED_10000; 8988 lp->active_duplex = DUPLEX_FULL; 8989 #else 8990 lp->loopback_mode = LOOPBACK_DISABLED; 8991 #endif 8992 } 8993 8994 static int niu_init_mac_ipp_pcs_base(struct niu *np) 8995 { 8996 switch (np->port) { 8997 case 0: 8998 np->mac_regs = np->regs + XMAC_PORT0_OFF; 8999 np->ipp_off = 0x00000; 9000 np->pcs_off = 0x04000; 9001 np->xpcs_off = 0x02000; 9002 break; 9003 9004 case 1: 9005 np->mac_regs = np->regs + XMAC_PORT1_OFF; 9006 np->ipp_off = 0x08000; 9007 np->pcs_off = 0x0a000; 9008 np->xpcs_off = 0x08000; 9009 break; 9010 9011 case 2: 9012 np->mac_regs = np->regs + BMAC_PORT2_OFF; 9013 np->ipp_off = 0x04000; 9014 np->pcs_off = 0x0e000; 9015 np->xpcs_off = ~0UL; 9016 break; 9017 9018 case 3: 9019 np->mac_regs = np->regs + BMAC_PORT3_OFF; 9020 np->ipp_off = 0x0c000; 9021 np->pcs_off = 0x12000; 9022 np->xpcs_off = ~0UL; 9023 break; 9024 9025 default: 9026 dev_err(np->device, "Port %u is invalid, cannot compute MAC block offset\n", np->port); 9027 return -EINVAL; 9028 } 9029 9030 return 0; 9031 } 9032 9033 static void niu_try_msix(struct niu *np, u8 *ldg_num_map) 9034 { 9035 struct msix_entry msi_vec[NIU_NUM_LDG]; 9036 struct niu_parent *parent = np->parent; 9037 struct pci_dev *pdev = np->pdev; 9038 int i, num_irqs; 9039 u8 first_ldg; 9040 9041 first_ldg = (NIU_NUM_LDG / parent->num_ports) * np->port; 9042 for (i = 0; i < (NIU_NUM_LDG / parent->num_ports); i++) 9043 ldg_num_map[i] = first_ldg + i; 9044 9045 num_irqs = (parent->rxchan_per_port[np->port] + 9046 parent->txchan_per_port[np->port] + 9047 (np->port == 0 ? 3 : 1)); 9048 BUG_ON(num_irqs > (NIU_NUM_LDG / parent->num_ports)); 9049 9050 for (i = 0; i < num_irqs; i++) { 9051 msi_vec[i].vector = 0; 9052 msi_vec[i].entry = i; 9053 } 9054 9055 num_irqs = pci_enable_msix_range(pdev, msi_vec, 1, num_irqs); 9056 if (num_irqs < 0) { 9057 np->flags &= ~NIU_FLAGS_MSIX; 9058 return; 9059 } 9060 9061 np->flags |= NIU_FLAGS_MSIX; 9062 for (i = 0; i < num_irqs; i++) 9063 np->ldg[i].irq = msi_vec[i].vector; 9064 np->num_ldg = num_irqs; 9065 } 9066 9067 static int niu_n2_irq_init(struct niu *np, u8 *ldg_num_map) 9068 { 9069 #ifdef CONFIG_SPARC64 9070 struct platform_device *op = np->op; 9071 const u32 *int_prop; 9072 int i; 9073 9074 int_prop = of_get_property(op->dev.of_node, "interrupts", NULL); 9075 if (!int_prop) 9076 return -ENODEV; 9077 9078 for (i = 0; i < op->archdata.num_irqs; i++) { 9079 ldg_num_map[i] = int_prop[i]; 9080 np->ldg[i].irq = op->archdata.irqs[i]; 9081 } 9082 9083 np->num_ldg = op->archdata.num_irqs; 9084 9085 return 0; 9086 #else 9087 return -EINVAL; 9088 #endif 9089 } 9090 9091 static int niu_ldg_init(struct niu *np) 9092 { 9093 struct niu_parent *parent = np->parent; 9094 u8 ldg_num_map[NIU_NUM_LDG]; 9095 int first_chan, num_chan; 9096 int i, err, ldg_rotor; 9097 u8 port; 9098 9099 np->num_ldg = 1; 9100 np->ldg[0].irq = np->dev->irq; 9101 if (parent->plat_type == PLAT_TYPE_NIU) { 9102 err = niu_n2_irq_init(np, ldg_num_map); 9103 if (err) 9104 return err; 9105 } else 9106 niu_try_msix(np, ldg_num_map); 9107 9108 port = np->port; 9109 for (i = 0; i < np->num_ldg; i++) { 9110 struct niu_ldg *lp = &np->ldg[i]; 9111 9112 netif_napi_add(np->dev, &lp->napi, niu_poll, 64); 9113 9114 lp->np = np; 9115 lp->ldg_num = ldg_num_map[i]; 9116 lp->timer = 2; /* XXX */ 9117 9118 /* On N2 NIU the firmware has setup the SID mappings so they go 9119 * to the correct values that will route the LDG to the proper 9120 * interrupt in the NCU interrupt table. 9121 */ 9122 if (np->parent->plat_type != PLAT_TYPE_NIU) { 9123 err = niu_set_ldg_sid(np, lp->ldg_num, port, i); 9124 if (err) 9125 return err; 9126 } 9127 } 9128 9129 /* We adopt the LDG assignment ordering used by the N2 NIU 9130 * 'interrupt' properties because that simplifies a lot of 9131 * things. This ordering is: 9132 * 9133 * MAC 9134 * MIF (if port zero) 9135 * SYSERR (if port zero) 9136 * RX channels 9137 * TX channels 9138 */ 9139 9140 ldg_rotor = 0; 9141 9142 err = niu_ldg_assign_ldn(np, parent, ldg_num_map[ldg_rotor], 9143 LDN_MAC(port)); 9144 if (err) 9145 return err; 9146 9147 ldg_rotor++; 9148 if (ldg_rotor == np->num_ldg) 9149 ldg_rotor = 0; 9150 9151 if (port == 0) { 9152 err = niu_ldg_assign_ldn(np, parent, 9153 ldg_num_map[ldg_rotor], 9154 LDN_MIF); 9155 if (err) 9156 return err; 9157 9158 ldg_rotor++; 9159 if (ldg_rotor == np->num_ldg) 9160 ldg_rotor = 0; 9161 9162 err = niu_ldg_assign_ldn(np, parent, 9163 ldg_num_map[ldg_rotor], 9164 LDN_DEVICE_ERROR); 9165 if (err) 9166 return err; 9167 9168 ldg_rotor++; 9169 if (ldg_rotor == np->num_ldg) 9170 ldg_rotor = 0; 9171 9172 } 9173 9174 first_chan = 0; 9175 for (i = 0; i < port; i++) 9176 first_chan += parent->rxchan_per_port[i]; 9177 num_chan = parent->rxchan_per_port[port]; 9178 9179 for (i = first_chan; i < (first_chan + num_chan); i++) { 9180 err = niu_ldg_assign_ldn(np, parent, 9181 ldg_num_map[ldg_rotor], 9182 LDN_RXDMA(i)); 9183 if (err) 9184 return err; 9185 ldg_rotor++; 9186 if (ldg_rotor == np->num_ldg) 9187 ldg_rotor = 0; 9188 } 9189 9190 first_chan = 0; 9191 for (i = 0; i < port; i++) 9192 first_chan += parent->txchan_per_port[i]; 9193 num_chan = parent->txchan_per_port[port]; 9194 for (i = first_chan; i < (first_chan + num_chan); i++) { 9195 err = niu_ldg_assign_ldn(np, parent, 9196 ldg_num_map[ldg_rotor], 9197 LDN_TXDMA(i)); 9198 if (err) 9199 return err; 9200 ldg_rotor++; 9201 if (ldg_rotor == np->num_ldg) 9202 ldg_rotor = 0; 9203 } 9204 9205 return 0; 9206 } 9207 9208 static void niu_ldg_free(struct niu *np) 9209 { 9210 if (np->flags & NIU_FLAGS_MSIX) 9211 pci_disable_msix(np->pdev); 9212 } 9213 9214 static int niu_get_of_props(struct niu *np) 9215 { 9216 #ifdef CONFIG_SPARC64 9217 struct net_device *dev = np->dev; 9218 struct device_node *dp; 9219 const char *phy_type; 9220 const u8 *mac_addr; 9221 const char *model; 9222 int prop_len; 9223 9224 if (np->parent->plat_type == PLAT_TYPE_NIU) 9225 dp = np->op->dev.of_node; 9226 else 9227 dp = pci_device_to_OF_node(np->pdev); 9228 9229 phy_type = of_get_property(dp, "phy-type", &prop_len); 9230 if (!phy_type) { 9231 netdev_err(dev, "%s: OF node lacks phy-type property\n", 9232 dp->full_name); 9233 return -EINVAL; 9234 } 9235 9236 if (!strcmp(phy_type, "none")) 9237 return -ENODEV; 9238 9239 strcpy(np->vpd.phy_type, phy_type); 9240 9241 if (niu_phy_type_prop_decode(np, np->vpd.phy_type)) { 9242 netdev_err(dev, "%s: Illegal phy string [%s]\n", 9243 dp->full_name, np->vpd.phy_type); 9244 return -EINVAL; 9245 } 9246 9247 mac_addr = of_get_property(dp, "local-mac-address", &prop_len); 9248 if (!mac_addr) { 9249 netdev_err(dev, "%s: OF node lacks local-mac-address property\n", 9250 dp->full_name); 9251 return -EINVAL; 9252 } 9253 if (prop_len != dev->addr_len) { 9254 netdev_err(dev, "%s: OF MAC address prop len (%d) is wrong\n", 9255 dp->full_name, prop_len); 9256 } 9257 memcpy(dev->dev_addr, mac_addr, dev->addr_len); 9258 if (!is_valid_ether_addr(&dev->dev_addr[0])) { 9259 netdev_err(dev, "%s: OF MAC address is invalid\n", 9260 dp->full_name); 9261 netdev_err(dev, "%s: [ %pM ]\n", dp->full_name, dev->dev_addr); 9262 return -EINVAL; 9263 } 9264 9265 model = of_get_property(dp, "model", &prop_len); 9266 9267 if (model) 9268 strcpy(np->vpd.model, model); 9269 9270 if (of_find_property(dp, "hot-swappable-phy", &prop_len)) { 9271 np->flags |= (NIU_FLAGS_10G | NIU_FLAGS_FIBER | 9272 NIU_FLAGS_HOTPLUG_PHY); 9273 } 9274 9275 return 0; 9276 #else 9277 return -EINVAL; 9278 #endif 9279 } 9280 9281 static int niu_get_invariants(struct niu *np) 9282 { 9283 int err, have_props; 9284 u32 offset; 9285 9286 err = niu_get_of_props(np); 9287 if (err == -ENODEV) 9288 return err; 9289 9290 have_props = !err; 9291 9292 err = niu_init_mac_ipp_pcs_base(np); 9293 if (err) 9294 return err; 9295 9296 if (have_props) { 9297 err = niu_get_and_validate_port(np); 9298 if (err) 9299 return err; 9300 9301 } else { 9302 if (np->parent->plat_type == PLAT_TYPE_NIU) 9303 return -EINVAL; 9304 9305 nw64(ESPC_PIO_EN, ESPC_PIO_EN_ENABLE); 9306 offset = niu_pci_vpd_offset(np); 9307 netif_printk(np, probe, KERN_DEBUG, np->dev, 9308 "%s() VPD offset [%08x]\n", __func__, offset); 9309 if (offset) 9310 niu_pci_vpd_fetch(np, offset); 9311 nw64(ESPC_PIO_EN, 0); 9312 9313 if (np->flags & NIU_FLAGS_VPD_VALID) { 9314 niu_pci_vpd_validate(np); 9315 err = niu_get_and_validate_port(np); 9316 if (err) 9317 return err; 9318 } 9319 9320 if (!(np->flags & NIU_FLAGS_VPD_VALID)) { 9321 err = niu_get_and_validate_port(np); 9322 if (err) 9323 return err; 9324 err = niu_pci_probe_sprom(np); 9325 if (err) 9326 return err; 9327 } 9328 } 9329 9330 err = niu_probe_ports(np); 9331 if (err) 9332 return err; 9333 9334 niu_ldg_init(np); 9335 9336 niu_classifier_swstate_init(np); 9337 niu_link_config_init(np); 9338 9339 err = niu_determine_phy_disposition(np); 9340 if (!err) 9341 err = niu_init_link(np); 9342 9343 return err; 9344 } 9345 9346 static LIST_HEAD(niu_parent_list); 9347 static DEFINE_MUTEX(niu_parent_lock); 9348 static int niu_parent_index; 9349 9350 static ssize_t show_port_phy(struct device *dev, 9351 struct device_attribute *attr, char *buf) 9352 { 9353 struct platform_device *plat_dev = to_platform_device(dev); 9354 struct niu_parent *p = dev_get_platdata(&plat_dev->dev); 9355 u32 port_phy = p->port_phy; 9356 char *orig_buf = buf; 9357 int i; 9358 9359 if (port_phy == PORT_PHY_UNKNOWN || 9360 port_phy == PORT_PHY_INVALID) 9361 return 0; 9362 9363 for (i = 0; i < p->num_ports; i++) { 9364 const char *type_str; 9365 int type; 9366 9367 type = phy_decode(port_phy, i); 9368 if (type == PORT_TYPE_10G) 9369 type_str = "10G"; 9370 else 9371 type_str = "1G"; 9372 buf += sprintf(buf, 9373 (i == 0) ? "%s" : " %s", 9374 type_str); 9375 } 9376 buf += sprintf(buf, "\n"); 9377 return buf - orig_buf; 9378 } 9379 9380 static ssize_t show_plat_type(struct device *dev, 9381 struct device_attribute *attr, char *buf) 9382 { 9383 struct platform_device *plat_dev = to_platform_device(dev); 9384 struct niu_parent *p = dev_get_platdata(&plat_dev->dev); 9385 const char *type_str; 9386 9387 switch (p->plat_type) { 9388 case PLAT_TYPE_ATLAS: 9389 type_str = "atlas"; 9390 break; 9391 case PLAT_TYPE_NIU: 9392 type_str = "niu"; 9393 break; 9394 case PLAT_TYPE_VF_P0: 9395 type_str = "vf_p0"; 9396 break; 9397 case PLAT_TYPE_VF_P1: 9398 type_str = "vf_p1"; 9399 break; 9400 default: 9401 type_str = "unknown"; 9402 break; 9403 } 9404 9405 return sprintf(buf, "%s\n", type_str); 9406 } 9407 9408 static ssize_t __show_chan_per_port(struct device *dev, 9409 struct device_attribute *attr, char *buf, 9410 int rx) 9411 { 9412 struct platform_device *plat_dev = to_platform_device(dev); 9413 struct niu_parent *p = dev_get_platdata(&plat_dev->dev); 9414 char *orig_buf = buf; 9415 u8 *arr; 9416 int i; 9417 9418 arr = (rx ? p->rxchan_per_port : p->txchan_per_port); 9419 9420 for (i = 0; i < p->num_ports; i++) { 9421 buf += sprintf(buf, 9422 (i == 0) ? "%d" : " %d", 9423 arr[i]); 9424 } 9425 buf += sprintf(buf, "\n"); 9426 9427 return buf - orig_buf; 9428 } 9429 9430 static ssize_t show_rxchan_per_port(struct device *dev, 9431 struct device_attribute *attr, char *buf) 9432 { 9433 return __show_chan_per_port(dev, attr, buf, 1); 9434 } 9435 9436 static ssize_t show_txchan_per_port(struct device *dev, 9437 struct device_attribute *attr, char *buf) 9438 { 9439 return __show_chan_per_port(dev, attr, buf, 1); 9440 } 9441 9442 static ssize_t show_num_ports(struct device *dev, 9443 struct device_attribute *attr, char *buf) 9444 { 9445 struct platform_device *plat_dev = to_platform_device(dev); 9446 struct niu_parent *p = dev_get_platdata(&plat_dev->dev); 9447 9448 return sprintf(buf, "%d\n", p->num_ports); 9449 } 9450 9451 static struct device_attribute niu_parent_attributes[] = { 9452 __ATTR(port_phy, S_IRUGO, show_port_phy, NULL), 9453 __ATTR(plat_type, S_IRUGO, show_plat_type, NULL), 9454 __ATTR(rxchan_per_port, S_IRUGO, show_rxchan_per_port, NULL), 9455 __ATTR(txchan_per_port, S_IRUGO, show_txchan_per_port, NULL), 9456 __ATTR(num_ports, S_IRUGO, show_num_ports, NULL), 9457 {} 9458 }; 9459 9460 static struct niu_parent *niu_new_parent(struct niu *np, 9461 union niu_parent_id *id, u8 ptype) 9462 { 9463 struct platform_device *plat_dev; 9464 struct niu_parent *p; 9465 int i; 9466 9467 plat_dev = platform_device_register_simple("niu-board", niu_parent_index, 9468 NULL, 0); 9469 if (IS_ERR(plat_dev)) 9470 return NULL; 9471 9472 for (i = 0; niu_parent_attributes[i].attr.name; i++) { 9473 int err = device_create_file(&plat_dev->dev, 9474 &niu_parent_attributes[i]); 9475 if (err) 9476 goto fail_unregister; 9477 } 9478 9479 p = kzalloc(sizeof(*p), GFP_KERNEL); 9480 if (!p) 9481 goto fail_unregister; 9482 9483 p->index = niu_parent_index++; 9484 9485 plat_dev->dev.platform_data = p; 9486 p->plat_dev = plat_dev; 9487 9488 memcpy(&p->id, id, sizeof(*id)); 9489 p->plat_type = ptype; 9490 INIT_LIST_HEAD(&p->list); 9491 atomic_set(&p->refcnt, 0); 9492 list_add(&p->list, &niu_parent_list); 9493 spin_lock_init(&p->lock); 9494 9495 p->rxdma_clock_divider = 7500; 9496 9497 p->tcam_num_entries = NIU_PCI_TCAM_ENTRIES; 9498 if (p->plat_type == PLAT_TYPE_NIU) 9499 p->tcam_num_entries = NIU_NONPCI_TCAM_ENTRIES; 9500 9501 for (i = CLASS_CODE_USER_PROG1; i <= CLASS_CODE_SCTP_IPV6; i++) { 9502 int index = i - CLASS_CODE_USER_PROG1; 9503 9504 p->tcam_key[index] = TCAM_KEY_TSEL; 9505 p->flow_key[index] = (FLOW_KEY_IPSA | 9506 FLOW_KEY_IPDA | 9507 FLOW_KEY_PROTO | 9508 (FLOW_KEY_L4_BYTE12 << 9509 FLOW_KEY_L4_0_SHIFT) | 9510 (FLOW_KEY_L4_BYTE12 << 9511 FLOW_KEY_L4_1_SHIFT)); 9512 } 9513 9514 for (i = 0; i < LDN_MAX + 1; i++) 9515 p->ldg_map[i] = LDG_INVALID; 9516 9517 return p; 9518 9519 fail_unregister: 9520 platform_device_unregister(plat_dev); 9521 return NULL; 9522 } 9523 9524 static struct niu_parent *niu_get_parent(struct niu *np, 9525 union niu_parent_id *id, u8 ptype) 9526 { 9527 struct niu_parent *p, *tmp; 9528 int port = np->port; 9529 9530 mutex_lock(&niu_parent_lock); 9531 p = NULL; 9532 list_for_each_entry(tmp, &niu_parent_list, list) { 9533 if (!memcmp(id, &tmp->id, sizeof(*id))) { 9534 p = tmp; 9535 break; 9536 } 9537 } 9538 if (!p) 9539 p = niu_new_parent(np, id, ptype); 9540 9541 if (p) { 9542 char port_name[6]; 9543 int err; 9544 9545 sprintf(port_name, "port%d", port); 9546 err = sysfs_create_link(&p->plat_dev->dev.kobj, 9547 &np->device->kobj, 9548 port_name); 9549 if (!err) { 9550 p->ports[port] = np; 9551 atomic_inc(&p->refcnt); 9552 } 9553 } 9554 mutex_unlock(&niu_parent_lock); 9555 9556 return p; 9557 } 9558 9559 static void niu_put_parent(struct niu *np) 9560 { 9561 struct niu_parent *p = np->parent; 9562 u8 port = np->port; 9563 char port_name[6]; 9564 9565 BUG_ON(!p || p->ports[port] != np); 9566 9567 netif_printk(np, probe, KERN_DEBUG, np->dev, 9568 "%s() port[%u]\n", __func__, port); 9569 9570 sprintf(port_name, "port%d", port); 9571 9572 mutex_lock(&niu_parent_lock); 9573 9574 sysfs_remove_link(&p->plat_dev->dev.kobj, port_name); 9575 9576 p->ports[port] = NULL; 9577 np->parent = NULL; 9578 9579 if (atomic_dec_and_test(&p->refcnt)) { 9580 list_del(&p->list); 9581 platform_device_unregister(p->plat_dev); 9582 } 9583 9584 mutex_unlock(&niu_parent_lock); 9585 } 9586 9587 static void *niu_pci_alloc_coherent(struct device *dev, size_t size, 9588 u64 *handle, gfp_t flag) 9589 { 9590 dma_addr_t dh; 9591 void *ret; 9592 9593 ret = dma_alloc_coherent(dev, size, &dh, flag); 9594 if (ret) 9595 *handle = dh; 9596 return ret; 9597 } 9598 9599 static void niu_pci_free_coherent(struct device *dev, size_t size, 9600 void *cpu_addr, u64 handle) 9601 { 9602 dma_free_coherent(dev, size, cpu_addr, handle); 9603 } 9604 9605 static u64 niu_pci_map_page(struct device *dev, struct page *page, 9606 unsigned long offset, size_t size, 9607 enum dma_data_direction direction) 9608 { 9609 return dma_map_page(dev, page, offset, size, direction); 9610 } 9611 9612 static void niu_pci_unmap_page(struct device *dev, u64 dma_address, 9613 size_t size, enum dma_data_direction direction) 9614 { 9615 dma_unmap_page(dev, dma_address, size, direction); 9616 } 9617 9618 static u64 niu_pci_map_single(struct device *dev, void *cpu_addr, 9619 size_t size, 9620 enum dma_data_direction direction) 9621 { 9622 return dma_map_single(dev, cpu_addr, size, direction); 9623 } 9624 9625 static void niu_pci_unmap_single(struct device *dev, u64 dma_address, 9626 size_t size, 9627 enum dma_data_direction direction) 9628 { 9629 dma_unmap_single(dev, dma_address, size, direction); 9630 } 9631 9632 static const struct niu_ops niu_pci_ops = { 9633 .alloc_coherent = niu_pci_alloc_coherent, 9634 .free_coherent = niu_pci_free_coherent, 9635 .map_page = niu_pci_map_page, 9636 .unmap_page = niu_pci_unmap_page, 9637 .map_single = niu_pci_map_single, 9638 .unmap_single = niu_pci_unmap_single, 9639 }; 9640 9641 static void niu_driver_version(void) 9642 { 9643 static int niu_version_printed; 9644 9645 if (niu_version_printed++ == 0) 9646 pr_info("%s", version); 9647 } 9648 9649 static struct net_device *niu_alloc_and_init(struct device *gen_dev, 9650 struct pci_dev *pdev, 9651 struct platform_device *op, 9652 const struct niu_ops *ops, u8 port) 9653 { 9654 struct net_device *dev; 9655 struct niu *np; 9656 9657 dev = alloc_etherdev_mq(sizeof(struct niu), NIU_NUM_TXCHAN); 9658 if (!dev) 9659 return NULL; 9660 9661 SET_NETDEV_DEV(dev, gen_dev); 9662 9663 np = netdev_priv(dev); 9664 np->dev = dev; 9665 np->pdev = pdev; 9666 np->op = op; 9667 np->device = gen_dev; 9668 np->ops = ops; 9669 9670 np->msg_enable = niu_debug; 9671 9672 spin_lock_init(&np->lock); 9673 INIT_WORK(&np->reset_task, niu_reset_task); 9674 9675 np->port = port; 9676 9677 return dev; 9678 } 9679 9680 static const struct net_device_ops niu_netdev_ops = { 9681 .ndo_open = niu_open, 9682 .ndo_stop = niu_close, 9683 .ndo_start_xmit = niu_start_xmit, 9684 .ndo_get_stats64 = niu_get_stats, 9685 .ndo_set_rx_mode = niu_set_rx_mode, 9686 .ndo_validate_addr = eth_validate_addr, 9687 .ndo_set_mac_address = niu_set_mac_addr, 9688 .ndo_do_ioctl = niu_ioctl, 9689 .ndo_tx_timeout = niu_tx_timeout, 9690 .ndo_change_mtu = niu_change_mtu, 9691 }; 9692 9693 static void niu_assign_netdev_ops(struct net_device *dev) 9694 { 9695 dev->netdev_ops = &niu_netdev_ops; 9696 dev->ethtool_ops = &niu_ethtool_ops; 9697 dev->watchdog_timeo = NIU_TX_TIMEOUT; 9698 } 9699 9700 static void niu_device_announce(struct niu *np) 9701 { 9702 struct net_device *dev = np->dev; 9703 9704 pr_info("%s: NIU Ethernet %pM\n", dev->name, dev->dev_addr); 9705 9706 if (np->parent->plat_type == PLAT_TYPE_ATCA_CP3220) { 9707 pr_info("%s: Port type[%s] mode[%s:%s] XCVR[%s] phy[%s]\n", 9708 dev->name, 9709 (np->flags & NIU_FLAGS_XMAC ? "XMAC" : "BMAC"), 9710 (np->flags & NIU_FLAGS_10G ? "10G" : "1G"), 9711 (np->flags & NIU_FLAGS_FIBER ? "RGMII FIBER" : "SERDES"), 9712 (np->mac_xcvr == MAC_XCVR_MII ? "MII" : 9713 (np->mac_xcvr == MAC_XCVR_PCS ? "PCS" : "XPCS")), 9714 np->vpd.phy_type); 9715 } else { 9716 pr_info("%s: Port type[%s] mode[%s:%s] XCVR[%s] phy[%s]\n", 9717 dev->name, 9718 (np->flags & NIU_FLAGS_XMAC ? "XMAC" : "BMAC"), 9719 (np->flags & NIU_FLAGS_10G ? "10G" : "1G"), 9720 (np->flags & NIU_FLAGS_FIBER ? "FIBER" : 9721 (np->flags & NIU_FLAGS_XCVR_SERDES ? "SERDES" : 9722 "COPPER")), 9723 (np->mac_xcvr == MAC_XCVR_MII ? "MII" : 9724 (np->mac_xcvr == MAC_XCVR_PCS ? "PCS" : "XPCS")), 9725 np->vpd.phy_type); 9726 } 9727 } 9728 9729 static void niu_set_basic_features(struct net_device *dev) 9730 { 9731 dev->hw_features = NETIF_F_SG | NETIF_F_HW_CSUM | NETIF_F_RXHASH; 9732 dev->features |= dev->hw_features | NETIF_F_RXCSUM; 9733 } 9734 9735 static int niu_pci_init_one(struct pci_dev *pdev, 9736 const struct pci_device_id *ent) 9737 { 9738 union niu_parent_id parent_id; 9739 struct net_device *dev; 9740 struct niu *np; 9741 int err; 9742 u64 dma_mask; 9743 9744 niu_driver_version(); 9745 9746 err = pci_enable_device(pdev); 9747 if (err) { 9748 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n"); 9749 return err; 9750 } 9751 9752 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM) || 9753 !(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) { 9754 dev_err(&pdev->dev, "Cannot find proper PCI device base addresses, aborting\n"); 9755 err = -ENODEV; 9756 goto err_out_disable_pdev; 9757 } 9758 9759 err = pci_request_regions(pdev, DRV_MODULE_NAME); 9760 if (err) { 9761 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n"); 9762 goto err_out_disable_pdev; 9763 } 9764 9765 if (!pci_is_pcie(pdev)) { 9766 dev_err(&pdev->dev, "Cannot find PCI Express capability, aborting\n"); 9767 err = -ENODEV; 9768 goto err_out_free_res; 9769 } 9770 9771 dev = niu_alloc_and_init(&pdev->dev, pdev, NULL, 9772 &niu_pci_ops, PCI_FUNC(pdev->devfn)); 9773 if (!dev) { 9774 err = -ENOMEM; 9775 goto err_out_free_res; 9776 } 9777 np = netdev_priv(dev); 9778 9779 memset(&parent_id, 0, sizeof(parent_id)); 9780 parent_id.pci.domain = pci_domain_nr(pdev->bus); 9781 parent_id.pci.bus = pdev->bus->number; 9782 parent_id.pci.device = PCI_SLOT(pdev->devfn); 9783 9784 np->parent = niu_get_parent(np, &parent_id, 9785 PLAT_TYPE_ATLAS); 9786 if (!np->parent) { 9787 err = -ENOMEM; 9788 goto err_out_free_dev; 9789 } 9790 9791 pcie_capability_clear_and_set_word(pdev, PCI_EXP_DEVCTL, 9792 PCI_EXP_DEVCTL_NOSNOOP_EN, 9793 PCI_EXP_DEVCTL_CERE | PCI_EXP_DEVCTL_NFERE | 9794 PCI_EXP_DEVCTL_FERE | PCI_EXP_DEVCTL_URRE | 9795 PCI_EXP_DEVCTL_RELAX_EN); 9796 9797 dma_mask = DMA_BIT_MASK(44); 9798 err = pci_set_dma_mask(pdev, dma_mask); 9799 if (!err) { 9800 dev->features |= NETIF_F_HIGHDMA; 9801 err = pci_set_consistent_dma_mask(pdev, dma_mask); 9802 if (err) { 9803 dev_err(&pdev->dev, "Unable to obtain 44 bit DMA for consistent allocations, aborting\n"); 9804 goto err_out_release_parent; 9805 } 9806 } 9807 if (err) { 9808 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); 9809 if (err) { 9810 dev_err(&pdev->dev, "No usable DMA configuration, aborting\n"); 9811 goto err_out_release_parent; 9812 } 9813 } 9814 9815 niu_set_basic_features(dev); 9816 9817 dev->priv_flags |= IFF_UNICAST_FLT; 9818 9819 np->regs = pci_ioremap_bar(pdev, 0); 9820 if (!np->regs) { 9821 dev_err(&pdev->dev, "Cannot map device registers, aborting\n"); 9822 err = -ENOMEM; 9823 goto err_out_release_parent; 9824 } 9825 9826 pci_set_master(pdev); 9827 pci_save_state(pdev); 9828 9829 dev->irq = pdev->irq; 9830 9831 niu_assign_netdev_ops(dev); 9832 9833 err = niu_get_invariants(np); 9834 if (err) { 9835 if (err != -ENODEV) 9836 dev_err(&pdev->dev, "Problem fetching invariants of chip, aborting\n"); 9837 goto err_out_iounmap; 9838 } 9839 9840 err = register_netdev(dev); 9841 if (err) { 9842 dev_err(&pdev->dev, "Cannot register net device, aborting\n"); 9843 goto err_out_iounmap; 9844 } 9845 9846 pci_set_drvdata(pdev, dev); 9847 9848 niu_device_announce(np); 9849 9850 return 0; 9851 9852 err_out_iounmap: 9853 if (np->regs) { 9854 iounmap(np->regs); 9855 np->regs = NULL; 9856 } 9857 9858 err_out_release_parent: 9859 niu_put_parent(np); 9860 9861 err_out_free_dev: 9862 free_netdev(dev); 9863 9864 err_out_free_res: 9865 pci_release_regions(pdev); 9866 9867 err_out_disable_pdev: 9868 pci_disable_device(pdev); 9869 9870 return err; 9871 } 9872 9873 static void niu_pci_remove_one(struct pci_dev *pdev) 9874 { 9875 struct net_device *dev = pci_get_drvdata(pdev); 9876 9877 if (dev) { 9878 struct niu *np = netdev_priv(dev); 9879 9880 unregister_netdev(dev); 9881 if (np->regs) { 9882 iounmap(np->regs); 9883 np->regs = NULL; 9884 } 9885 9886 niu_ldg_free(np); 9887 9888 niu_put_parent(np); 9889 9890 free_netdev(dev); 9891 pci_release_regions(pdev); 9892 pci_disable_device(pdev); 9893 } 9894 } 9895 9896 static int niu_suspend(struct pci_dev *pdev, pm_message_t state) 9897 { 9898 struct net_device *dev = pci_get_drvdata(pdev); 9899 struct niu *np = netdev_priv(dev); 9900 unsigned long flags; 9901 9902 if (!netif_running(dev)) 9903 return 0; 9904 9905 flush_work(&np->reset_task); 9906 niu_netif_stop(np); 9907 9908 del_timer_sync(&np->timer); 9909 9910 spin_lock_irqsave(&np->lock, flags); 9911 niu_enable_interrupts(np, 0); 9912 spin_unlock_irqrestore(&np->lock, flags); 9913 9914 netif_device_detach(dev); 9915 9916 spin_lock_irqsave(&np->lock, flags); 9917 niu_stop_hw(np); 9918 spin_unlock_irqrestore(&np->lock, flags); 9919 9920 pci_save_state(pdev); 9921 9922 return 0; 9923 } 9924 9925 static int niu_resume(struct pci_dev *pdev) 9926 { 9927 struct net_device *dev = pci_get_drvdata(pdev); 9928 struct niu *np = netdev_priv(dev); 9929 unsigned long flags; 9930 int err; 9931 9932 if (!netif_running(dev)) 9933 return 0; 9934 9935 pci_restore_state(pdev); 9936 9937 netif_device_attach(dev); 9938 9939 spin_lock_irqsave(&np->lock, flags); 9940 9941 err = niu_init_hw(np); 9942 if (!err) { 9943 np->timer.expires = jiffies + HZ; 9944 add_timer(&np->timer); 9945 niu_netif_start(np); 9946 } 9947 9948 spin_unlock_irqrestore(&np->lock, flags); 9949 9950 return err; 9951 } 9952 9953 static struct pci_driver niu_pci_driver = { 9954 .name = DRV_MODULE_NAME, 9955 .id_table = niu_pci_tbl, 9956 .probe = niu_pci_init_one, 9957 .remove = niu_pci_remove_one, 9958 .suspend = niu_suspend, 9959 .resume = niu_resume, 9960 }; 9961 9962 #ifdef CONFIG_SPARC64 9963 static void *niu_phys_alloc_coherent(struct device *dev, size_t size, 9964 u64 *dma_addr, gfp_t flag) 9965 { 9966 unsigned long order = get_order(size); 9967 unsigned long page = __get_free_pages(flag, order); 9968 9969 if (page == 0UL) 9970 return NULL; 9971 memset((char *)page, 0, PAGE_SIZE << order); 9972 *dma_addr = __pa(page); 9973 9974 return (void *) page; 9975 } 9976 9977 static void niu_phys_free_coherent(struct device *dev, size_t size, 9978 void *cpu_addr, u64 handle) 9979 { 9980 unsigned long order = get_order(size); 9981 9982 free_pages((unsigned long) cpu_addr, order); 9983 } 9984 9985 static u64 niu_phys_map_page(struct device *dev, struct page *page, 9986 unsigned long offset, size_t size, 9987 enum dma_data_direction direction) 9988 { 9989 return page_to_phys(page) + offset; 9990 } 9991 9992 static void niu_phys_unmap_page(struct device *dev, u64 dma_address, 9993 size_t size, enum dma_data_direction direction) 9994 { 9995 /* Nothing to do. */ 9996 } 9997 9998 static u64 niu_phys_map_single(struct device *dev, void *cpu_addr, 9999 size_t size, 10000 enum dma_data_direction direction) 10001 { 10002 return __pa(cpu_addr); 10003 } 10004 10005 static void niu_phys_unmap_single(struct device *dev, u64 dma_address, 10006 size_t size, 10007 enum dma_data_direction direction) 10008 { 10009 /* Nothing to do. */ 10010 } 10011 10012 static const struct niu_ops niu_phys_ops = { 10013 .alloc_coherent = niu_phys_alloc_coherent, 10014 .free_coherent = niu_phys_free_coherent, 10015 .map_page = niu_phys_map_page, 10016 .unmap_page = niu_phys_unmap_page, 10017 .map_single = niu_phys_map_single, 10018 .unmap_single = niu_phys_unmap_single, 10019 }; 10020 10021 static int niu_of_probe(struct platform_device *op) 10022 { 10023 union niu_parent_id parent_id; 10024 struct net_device *dev; 10025 struct niu *np; 10026 const u32 *reg; 10027 int err; 10028 10029 niu_driver_version(); 10030 10031 reg = of_get_property(op->dev.of_node, "reg", NULL); 10032 if (!reg) { 10033 dev_err(&op->dev, "%s: No 'reg' property, aborting\n", 10034 op->dev.of_node->full_name); 10035 return -ENODEV; 10036 } 10037 10038 dev = niu_alloc_and_init(&op->dev, NULL, op, 10039 &niu_phys_ops, reg[0] & 0x1); 10040 if (!dev) { 10041 err = -ENOMEM; 10042 goto err_out; 10043 } 10044 np = netdev_priv(dev); 10045 10046 memset(&parent_id, 0, sizeof(parent_id)); 10047 parent_id.of = of_get_parent(op->dev.of_node); 10048 10049 np->parent = niu_get_parent(np, &parent_id, 10050 PLAT_TYPE_NIU); 10051 if (!np->parent) { 10052 err = -ENOMEM; 10053 goto err_out_free_dev; 10054 } 10055 10056 niu_set_basic_features(dev); 10057 10058 np->regs = of_ioremap(&op->resource[1], 0, 10059 resource_size(&op->resource[1]), 10060 "niu regs"); 10061 if (!np->regs) { 10062 dev_err(&op->dev, "Cannot map device registers, aborting\n"); 10063 err = -ENOMEM; 10064 goto err_out_release_parent; 10065 } 10066 10067 np->vir_regs_1 = of_ioremap(&op->resource[2], 0, 10068 resource_size(&op->resource[2]), 10069 "niu vregs-1"); 10070 if (!np->vir_regs_1) { 10071 dev_err(&op->dev, "Cannot map device vir registers 1, aborting\n"); 10072 err = -ENOMEM; 10073 goto err_out_iounmap; 10074 } 10075 10076 np->vir_regs_2 = of_ioremap(&op->resource[3], 0, 10077 resource_size(&op->resource[3]), 10078 "niu vregs-2"); 10079 if (!np->vir_regs_2) { 10080 dev_err(&op->dev, "Cannot map device vir registers 2, aborting\n"); 10081 err = -ENOMEM; 10082 goto err_out_iounmap; 10083 } 10084 10085 niu_assign_netdev_ops(dev); 10086 10087 err = niu_get_invariants(np); 10088 if (err) { 10089 if (err != -ENODEV) 10090 dev_err(&op->dev, "Problem fetching invariants of chip, aborting\n"); 10091 goto err_out_iounmap; 10092 } 10093 10094 err = register_netdev(dev); 10095 if (err) { 10096 dev_err(&op->dev, "Cannot register net device, aborting\n"); 10097 goto err_out_iounmap; 10098 } 10099 10100 platform_set_drvdata(op, dev); 10101 10102 niu_device_announce(np); 10103 10104 return 0; 10105 10106 err_out_iounmap: 10107 if (np->vir_regs_1) { 10108 of_iounmap(&op->resource[2], np->vir_regs_1, 10109 resource_size(&op->resource[2])); 10110 np->vir_regs_1 = NULL; 10111 } 10112 10113 if (np->vir_regs_2) { 10114 of_iounmap(&op->resource[3], np->vir_regs_2, 10115 resource_size(&op->resource[3])); 10116 np->vir_regs_2 = NULL; 10117 } 10118 10119 if (np->regs) { 10120 of_iounmap(&op->resource[1], np->regs, 10121 resource_size(&op->resource[1])); 10122 np->regs = NULL; 10123 } 10124 10125 err_out_release_parent: 10126 niu_put_parent(np); 10127 10128 err_out_free_dev: 10129 free_netdev(dev); 10130 10131 err_out: 10132 return err; 10133 } 10134 10135 static int niu_of_remove(struct platform_device *op) 10136 { 10137 struct net_device *dev = platform_get_drvdata(op); 10138 10139 if (dev) { 10140 struct niu *np = netdev_priv(dev); 10141 10142 unregister_netdev(dev); 10143 10144 if (np->vir_regs_1) { 10145 of_iounmap(&op->resource[2], np->vir_regs_1, 10146 resource_size(&op->resource[2])); 10147 np->vir_regs_1 = NULL; 10148 } 10149 10150 if (np->vir_regs_2) { 10151 of_iounmap(&op->resource[3], np->vir_regs_2, 10152 resource_size(&op->resource[3])); 10153 np->vir_regs_2 = NULL; 10154 } 10155 10156 if (np->regs) { 10157 of_iounmap(&op->resource[1], np->regs, 10158 resource_size(&op->resource[1])); 10159 np->regs = NULL; 10160 } 10161 10162 niu_ldg_free(np); 10163 10164 niu_put_parent(np); 10165 10166 free_netdev(dev); 10167 } 10168 return 0; 10169 } 10170 10171 static const struct of_device_id niu_match[] = { 10172 { 10173 .name = "network", 10174 .compatible = "SUNW,niusl", 10175 }, 10176 {}, 10177 }; 10178 MODULE_DEVICE_TABLE(of, niu_match); 10179 10180 static struct platform_driver niu_of_driver = { 10181 .driver = { 10182 .name = "niu", 10183 .of_match_table = niu_match, 10184 }, 10185 .probe = niu_of_probe, 10186 .remove = niu_of_remove, 10187 }; 10188 10189 #endif /* CONFIG_SPARC64 */ 10190 10191 static int __init niu_init(void) 10192 { 10193 int err = 0; 10194 10195 BUILD_BUG_ON(PAGE_SIZE < 4 * 1024); 10196 10197 niu_debug = netif_msg_init(debug, NIU_MSG_DEFAULT); 10198 10199 #ifdef CONFIG_SPARC64 10200 err = platform_driver_register(&niu_of_driver); 10201 #endif 10202 10203 if (!err) { 10204 err = pci_register_driver(&niu_pci_driver); 10205 #ifdef CONFIG_SPARC64 10206 if (err) 10207 platform_driver_unregister(&niu_of_driver); 10208 #endif 10209 } 10210 10211 return err; 10212 } 10213 10214 static void __exit niu_exit(void) 10215 { 10216 pci_unregister_driver(&niu_pci_driver); 10217 #ifdef CONFIG_SPARC64 10218 platform_driver_unregister(&niu_of_driver); 10219 #endif 10220 } 10221 10222 module_init(niu_init); 10223 module_exit(niu_exit); 10224