1 /* niu.c: Neptune ethernet driver. 2 * 3 * Copyright (C) 2007, 2008 David S. Miller (davem@davemloft.net) 4 */ 5 6 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 7 8 #include <linux/module.h> 9 #include <linux/init.h> 10 #include <linux/interrupt.h> 11 #include <linux/pci.h> 12 #include <linux/dma-mapping.h> 13 #include <linux/netdevice.h> 14 #include <linux/ethtool.h> 15 #include <linux/etherdevice.h> 16 #include <linux/platform_device.h> 17 #include <linux/delay.h> 18 #include <linux/bitops.h> 19 #include <linux/mii.h> 20 #include <linux/if.h> 21 #include <linux/if_ether.h> 22 #include <linux/if_vlan.h> 23 #include <linux/ip.h> 24 #include <linux/in.h> 25 #include <linux/ipv6.h> 26 #include <linux/log2.h> 27 #include <linux/jiffies.h> 28 #include <linux/crc32.h> 29 #include <linux/list.h> 30 #include <linux/slab.h> 31 32 #include <linux/io.h> 33 #include <linux/of_device.h> 34 35 #include "niu.h" 36 37 #define DRV_MODULE_NAME "niu" 38 #define DRV_MODULE_VERSION "1.1" 39 #define DRV_MODULE_RELDATE "Apr 22, 2010" 40 41 static char version[] = 42 DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n"; 43 44 MODULE_AUTHOR("David S. Miller (davem@davemloft.net)"); 45 MODULE_DESCRIPTION("NIU ethernet driver"); 46 MODULE_LICENSE("GPL"); 47 MODULE_VERSION(DRV_MODULE_VERSION); 48 49 #ifndef readq 50 static u64 readq(void __iomem *reg) 51 { 52 return ((u64) readl(reg)) | (((u64) readl(reg + 4UL)) << 32); 53 } 54 55 static void writeq(u64 val, void __iomem *reg) 56 { 57 writel(val & 0xffffffff, reg); 58 writel(val >> 32, reg + 0x4UL); 59 } 60 #endif 61 62 static const struct pci_device_id niu_pci_tbl[] = { 63 {PCI_DEVICE(PCI_VENDOR_ID_SUN, 0xabcd)}, 64 {} 65 }; 66 67 MODULE_DEVICE_TABLE(pci, niu_pci_tbl); 68 69 #define NIU_TX_TIMEOUT (5 * HZ) 70 71 #define nr64(reg) readq(np->regs + (reg)) 72 #define nw64(reg, val) writeq((val), np->regs + (reg)) 73 74 #define nr64_mac(reg) readq(np->mac_regs + (reg)) 75 #define nw64_mac(reg, val) writeq((val), np->mac_regs + (reg)) 76 77 #define nr64_ipp(reg) readq(np->regs + np->ipp_off + (reg)) 78 #define nw64_ipp(reg, val) writeq((val), np->regs + np->ipp_off + (reg)) 79 80 #define nr64_pcs(reg) readq(np->regs + np->pcs_off + (reg)) 81 #define nw64_pcs(reg, val) writeq((val), np->regs + np->pcs_off + (reg)) 82 83 #define nr64_xpcs(reg) readq(np->regs + np->xpcs_off + (reg)) 84 #define nw64_xpcs(reg, val) writeq((val), np->regs + np->xpcs_off + (reg)) 85 86 #define NIU_MSG_DEFAULT (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK) 87 88 static int niu_debug; 89 static int debug = -1; 90 module_param(debug, int, 0); 91 MODULE_PARM_DESC(debug, "NIU debug level"); 92 93 #define niu_lock_parent(np, flags) \ 94 spin_lock_irqsave(&np->parent->lock, flags) 95 #define niu_unlock_parent(np, flags) \ 96 spin_unlock_irqrestore(&np->parent->lock, flags) 97 98 static int serdes_init_10g_serdes(struct niu *np); 99 100 static int __niu_wait_bits_clear_mac(struct niu *np, unsigned long reg, 101 u64 bits, int limit, int delay) 102 { 103 while (--limit >= 0) { 104 u64 val = nr64_mac(reg); 105 106 if (!(val & bits)) 107 break; 108 udelay(delay); 109 } 110 if (limit < 0) 111 return -ENODEV; 112 return 0; 113 } 114 115 static int __niu_set_and_wait_clear_mac(struct niu *np, unsigned long reg, 116 u64 bits, int limit, int delay, 117 const char *reg_name) 118 { 119 int err; 120 121 nw64_mac(reg, bits); 122 err = __niu_wait_bits_clear_mac(np, reg, bits, limit, delay); 123 if (err) 124 netdev_err(np->dev, "bits (%llx) of register %s would not clear, val[%llx]\n", 125 (unsigned long long)bits, reg_name, 126 (unsigned long long)nr64_mac(reg)); 127 return err; 128 } 129 130 #define niu_set_and_wait_clear_mac(NP, REG, BITS, LIMIT, DELAY, REG_NAME) \ 131 ({ BUILD_BUG_ON(LIMIT <= 0 || DELAY < 0); \ 132 __niu_set_and_wait_clear_mac(NP, REG, BITS, LIMIT, DELAY, REG_NAME); \ 133 }) 134 135 static int __niu_wait_bits_clear_ipp(struct niu *np, unsigned long reg, 136 u64 bits, int limit, int delay) 137 { 138 while (--limit >= 0) { 139 u64 val = nr64_ipp(reg); 140 141 if (!(val & bits)) 142 break; 143 udelay(delay); 144 } 145 if (limit < 0) 146 return -ENODEV; 147 return 0; 148 } 149 150 static int __niu_set_and_wait_clear_ipp(struct niu *np, unsigned long reg, 151 u64 bits, int limit, int delay, 152 const char *reg_name) 153 { 154 int err; 155 u64 val; 156 157 val = nr64_ipp(reg); 158 val |= bits; 159 nw64_ipp(reg, val); 160 161 err = __niu_wait_bits_clear_ipp(np, reg, bits, limit, delay); 162 if (err) 163 netdev_err(np->dev, "bits (%llx) of register %s would not clear, val[%llx]\n", 164 (unsigned long long)bits, reg_name, 165 (unsigned long long)nr64_ipp(reg)); 166 return err; 167 } 168 169 #define niu_set_and_wait_clear_ipp(NP, REG, BITS, LIMIT, DELAY, REG_NAME) \ 170 ({ BUILD_BUG_ON(LIMIT <= 0 || DELAY < 0); \ 171 __niu_set_and_wait_clear_ipp(NP, REG, BITS, LIMIT, DELAY, REG_NAME); \ 172 }) 173 174 static int __niu_wait_bits_clear(struct niu *np, unsigned long reg, 175 u64 bits, int limit, int delay) 176 { 177 while (--limit >= 0) { 178 u64 val = nr64(reg); 179 180 if (!(val & bits)) 181 break; 182 udelay(delay); 183 } 184 if (limit < 0) 185 return -ENODEV; 186 return 0; 187 } 188 189 #define niu_wait_bits_clear(NP, REG, BITS, LIMIT, DELAY) \ 190 ({ BUILD_BUG_ON(LIMIT <= 0 || DELAY < 0); \ 191 __niu_wait_bits_clear(NP, REG, BITS, LIMIT, DELAY); \ 192 }) 193 194 static int __niu_set_and_wait_clear(struct niu *np, unsigned long reg, 195 u64 bits, int limit, int delay, 196 const char *reg_name) 197 { 198 int err; 199 200 nw64(reg, bits); 201 err = __niu_wait_bits_clear(np, reg, bits, limit, delay); 202 if (err) 203 netdev_err(np->dev, "bits (%llx) of register %s would not clear, val[%llx]\n", 204 (unsigned long long)bits, reg_name, 205 (unsigned long long)nr64(reg)); 206 return err; 207 } 208 209 #define niu_set_and_wait_clear(NP, REG, BITS, LIMIT, DELAY, REG_NAME) \ 210 ({ BUILD_BUG_ON(LIMIT <= 0 || DELAY < 0); \ 211 __niu_set_and_wait_clear(NP, REG, BITS, LIMIT, DELAY, REG_NAME); \ 212 }) 213 214 static void niu_ldg_rearm(struct niu *np, struct niu_ldg *lp, int on) 215 { 216 u64 val = (u64) lp->timer; 217 218 if (on) 219 val |= LDG_IMGMT_ARM; 220 221 nw64(LDG_IMGMT(lp->ldg_num), val); 222 } 223 224 static int niu_ldn_irq_enable(struct niu *np, int ldn, int on) 225 { 226 unsigned long mask_reg, bits; 227 u64 val; 228 229 if (ldn < 0 || ldn > LDN_MAX) 230 return -EINVAL; 231 232 if (ldn < 64) { 233 mask_reg = LD_IM0(ldn); 234 bits = LD_IM0_MASK; 235 } else { 236 mask_reg = LD_IM1(ldn - 64); 237 bits = LD_IM1_MASK; 238 } 239 240 val = nr64(mask_reg); 241 if (on) 242 val &= ~bits; 243 else 244 val |= bits; 245 nw64(mask_reg, val); 246 247 return 0; 248 } 249 250 static int niu_enable_ldn_in_ldg(struct niu *np, struct niu_ldg *lp, int on) 251 { 252 struct niu_parent *parent = np->parent; 253 int i; 254 255 for (i = 0; i <= LDN_MAX; i++) { 256 int err; 257 258 if (parent->ldg_map[i] != lp->ldg_num) 259 continue; 260 261 err = niu_ldn_irq_enable(np, i, on); 262 if (err) 263 return err; 264 } 265 return 0; 266 } 267 268 static int niu_enable_interrupts(struct niu *np, int on) 269 { 270 int i; 271 272 for (i = 0; i < np->num_ldg; i++) { 273 struct niu_ldg *lp = &np->ldg[i]; 274 int err; 275 276 err = niu_enable_ldn_in_ldg(np, lp, on); 277 if (err) 278 return err; 279 } 280 for (i = 0; i < np->num_ldg; i++) 281 niu_ldg_rearm(np, &np->ldg[i], on); 282 283 return 0; 284 } 285 286 static u32 phy_encode(u32 type, int port) 287 { 288 return type << (port * 2); 289 } 290 291 static u32 phy_decode(u32 val, int port) 292 { 293 return (val >> (port * 2)) & PORT_TYPE_MASK; 294 } 295 296 static int mdio_wait(struct niu *np) 297 { 298 int limit = 1000; 299 u64 val; 300 301 while (--limit > 0) { 302 val = nr64(MIF_FRAME_OUTPUT); 303 if ((val >> MIF_FRAME_OUTPUT_TA_SHIFT) & 0x1) 304 return val & MIF_FRAME_OUTPUT_DATA; 305 306 udelay(10); 307 } 308 309 return -ENODEV; 310 } 311 312 static int mdio_read(struct niu *np, int port, int dev, int reg) 313 { 314 int err; 315 316 nw64(MIF_FRAME_OUTPUT, MDIO_ADDR_OP(port, dev, reg)); 317 err = mdio_wait(np); 318 if (err < 0) 319 return err; 320 321 nw64(MIF_FRAME_OUTPUT, MDIO_READ_OP(port, dev)); 322 return mdio_wait(np); 323 } 324 325 static int mdio_write(struct niu *np, int port, int dev, int reg, int data) 326 { 327 int err; 328 329 nw64(MIF_FRAME_OUTPUT, MDIO_ADDR_OP(port, dev, reg)); 330 err = mdio_wait(np); 331 if (err < 0) 332 return err; 333 334 nw64(MIF_FRAME_OUTPUT, MDIO_WRITE_OP(port, dev, data)); 335 err = mdio_wait(np); 336 if (err < 0) 337 return err; 338 339 return 0; 340 } 341 342 static int mii_read(struct niu *np, int port, int reg) 343 { 344 nw64(MIF_FRAME_OUTPUT, MII_READ_OP(port, reg)); 345 return mdio_wait(np); 346 } 347 348 static int mii_write(struct niu *np, int port, int reg, int data) 349 { 350 int err; 351 352 nw64(MIF_FRAME_OUTPUT, MII_WRITE_OP(port, reg, data)); 353 err = mdio_wait(np); 354 if (err < 0) 355 return err; 356 357 return 0; 358 } 359 360 static int esr2_set_tx_cfg(struct niu *np, unsigned long channel, u32 val) 361 { 362 int err; 363 364 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR, 365 ESR2_TI_PLL_TX_CFG_L(channel), 366 val & 0xffff); 367 if (!err) 368 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR, 369 ESR2_TI_PLL_TX_CFG_H(channel), 370 val >> 16); 371 return err; 372 } 373 374 static int esr2_set_rx_cfg(struct niu *np, unsigned long channel, u32 val) 375 { 376 int err; 377 378 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR, 379 ESR2_TI_PLL_RX_CFG_L(channel), 380 val & 0xffff); 381 if (!err) 382 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR, 383 ESR2_TI_PLL_RX_CFG_H(channel), 384 val >> 16); 385 return err; 386 } 387 388 /* Mode is always 10G fiber. */ 389 static int serdes_init_niu_10g_fiber(struct niu *np) 390 { 391 struct niu_link_config *lp = &np->link_config; 392 u32 tx_cfg, rx_cfg; 393 unsigned long i; 394 395 tx_cfg = (PLL_TX_CFG_ENTX | PLL_TX_CFG_SWING_1375MV); 396 rx_cfg = (PLL_RX_CFG_ENRX | PLL_RX_CFG_TERM_0P8VDDT | 397 PLL_RX_CFG_ALIGN_ENA | PLL_RX_CFG_LOS_LTHRESH | 398 PLL_RX_CFG_EQ_LP_ADAPTIVE); 399 400 if (lp->loopback_mode == LOOPBACK_PHY) { 401 u16 test_cfg = PLL_TEST_CFG_LOOPBACK_CML_DIS; 402 403 mdio_write(np, np->port, NIU_ESR2_DEV_ADDR, 404 ESR2_TI_PLL_TEST_CFG_L, test_cfg); 405 406 tx_cfg |= PLL_TX_CFG_ENTEST; 407 rx_cfg |= PLL_RX_CFG_ENTEST; 408 } 409 410 /* Initialize all 4 lanes of the SERDES. */ 411 for (i = 0; i < 4; i++) { 412 int err = esr2_set_tx_cfg(np, i, tx_cfg); 413 if (err) 414 return err; 415 } 416 417 for (i = 0; i < 4; i++) { 418 int err = esr2_set_rx_cfg(np, i, rx_cfg); 419 if (err) 420 return err; 421 } 422 423 return 0; 424 } 425 426 static int serdes_init_niu_1g_serdes(struct niu *np) 427 { 428 struct niu_link_config *lp = &np->link_config; 429 u16 pll_cfg, pll_sts; 430 int max_retry = 100; 431 u64 uninitialized_var(sig), mask, val; 432 u32 tx_cfg, rx_cfg; 433 unsigned long i; 434 int err; 435 436 tx_cfg = (PLL_TX_CFG_ENTX | PLL_TX_CFG_SWING_1375MV | 437 PLL_TX_CFG_RATE_HALF); 438 rx_cfg = (PLL_RX_CFG_ENRX | PLL_RX_CFG_TERM_0P8VDDT | 439 PLL_RX_CFG_ALIGN_ENA | PLL_RX_CFG_LOS_LTHRESH | 440 PLL_RX_CFG_RATE_HALF); 441 442 if (np->port == 0) 443 rx_cfg |= PLL_RX_CFG_EQ_LP_ADAPTIVE; 444 445 if (lp->loopback_mode == LOOPBACK_PHY) { 446 u16 test_cfg = PLL_TEST_CFG_LOOPBACK_CML_DIS; 447 448 mdio_write(np, np->port, NIU_ESR2_DEV_ADDR, 449 ESR2_TI_PLL_TEST_CFG_L, test_cfg); 450 451 tx_cfg |= PLL_TX_CFG_ENTEST; 452 rx_cfg |= PLL_RX_CFG_ENTEST; 453 } 454 455 /* Initialize PLL for 1G */ 456 pll_cfg = (PLL_CFG_ENPLL | PLL_CFG_MPY_8X); 457 458 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR, 459 ESR2_TI_PLL_CFG_L, pll_cfg); 460 if (err) { 461 netdev_err(np->dev, "NIU Port %d %s() mdio write to ESR2_TI_PLL_CFG_L failed\n", 462 np->port, __func__); 463 return err; 464 } 465 466 pll_sts = PLL_CFG_ENPLL; 467 468 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR, 469 ESR2_TI_PLL_STS_L, pll_sts); 470 if (err) { 471 netdev_err(np->dev, "NIU Port %d %s() mdio write to ESR2_TI_PLL_STS_L failed\n", 472 np->port, __func__); 473 return err; 474 } 475 476 udelay(200); 477 478 /* Initialize all 4 lanes of the SERDES. */ 479 for (i = 0; i < 4; i++) { 480 err = esr2_set_tx_cfg(np, i, tx_cfg); 481 if (err) 482 return err; 483 } 484 485 for (i = 0; i < 4; i++) { 486 err = esr2_set_rx_cfg(np, i, rx_cfg); 487 if (err) 488 return err; 489 } 490 491 switch (np->port) { 492 case 0: 493 val = (ESR_INT_SRDY0_P0 | ESR_INT_DET0_P0); 494 mask = val; 495 break; 496 497 case 1: 498 val = (ESR_INT_SRDY0_P1 | ESR_INT_DET0_P1); 499 mask = val; 500 break; 501 502 default: 503 return -EINVAL; 504 } 505 506 while (max_retry--) { 507 sig = nr64(ESR_INT_SIGNALS); 508 if ((sig & mask) == val) 509 break; 510 511 mdelay(500); 512 } 513 514 if ((sig & mask) != val) { 515 netdev_err(np->dev, "Port %u signal bits [%08x] are not [%08x]\n", 516 np->port, (int)(sig & mask), (int)val); 517 return -ENODEV; 518 } 519 520 return 0; 521 } 522 523 static int serdes_init_niu_10g_serdes(struct niu *np) 524 { 525 struct niu_link_config *lp = &np->link_config; 526 u32 tx_cfg, rx_cfg, pll_cfg, pll_sts; 527 int max_retry = 100; 528 u64 uninitialized_var(sig), mask, val; 529 unsigned long i; 530 int err; 531 532 tx_cfg = (PLL_TX_CFG_ENTX | PLL_TX_CFG_SWING_1375MV); 533 rx_cfg = (PLL_RX_CFG_ENRX | PLL_RX_CFG_TERM_0P8VDDT | 534 PLL_RX_CFG_ALIGN_ENA | PLL_RX_CFG_LOS_LTHRESH | 535 PLL_RX_CFG_EQ_LP_ADAPTIVE); 536 537 if (lp->loopback_mode == LOOPBACK_PHY) { 538 u16 test_cfg = PLL_TEST_CFG_LOOPBACK_CML_DIS; 539 540 mdio_write(np, np->port, NIU_ESR2_DEV_ADDR, 541 ESR2_TI_PLL_TEST_CFG_L, test_cfg); 542 543 tx_cfg |= PLL_TX_CFG_ENTEST; 544 rx_cfg |= PLL_RX_CFG_ENTEST; 545 } 546 547 /* Initialize PLL for 10G */ 548 pll_cfg = (PLL_CFG_ENPLL | PLL_CFG_MPY_10X); 549 550 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR, 551 ESR2_TI_PLL_CFG_L, pll_cfg & 0xffff); 552 if (err) { 553 netdev_err(np->dev, "NIU Port %d %s() mdio write to ESR2_TI_PLL_CFG_L failed\n", 554 np->port, __func__); 555 return err; 556 } 557 558 pll_sts = PLL_CFG_ENPLL; 559 560 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR, 561 ESR2_TI_PLL_STS_L, pll_sts & 0xffff); 562 if (err) { 563 netdev_err(np->dev, "NIU Port %d %s() mdio write to ESR2_TI_PLL_STS_L failed\n", 564 np->port, __func__); 565 return err; 566 } 567 568 udelay(200); 569 570 /* Initialize all 4 lanes of the SERDES. */ 571 for (i = 0; i < 4; i++) { 572 err = esr2_set_tx_cfg(np, i, tx_cfg); 573 if (err) 574 return err; 575 } 576 577 for (i = 0; i < 4; i++) { 578 err = esr2_set_rx_cfg(np, i, rx_cfg); 579 if (err) 580 return err; 581 } 582 583 /* check if serdes is ready */ 584 585 switch (np->port) { 586 case 0: 587 mask = ESR_INT_SIGNALS_P0_BITS; 588 val = (ESR_INT_SRDY0_P0 | 589 ESR_INT_DET0_P0 | 590 ESR_INT_XSRDY_P0 | 591 ESR_INT_XDP_P0_CH3 | 592 ESR_INT_XDP_P0_CH2 | 593 ESR_INT_XDP_P0_CH1 | 594 ESR_INT_XDP_P0_CH0); 595 break; 596 597 case 1: 598 mask = ESR_INT_SIGNALS_P1_BITS; 599 val = (ESR_INT_SRDY0_P1 | 600 ESR_INT_DET0_P1 | 601 ESR_INT_XSRDY_P1 | 602 ESR_INT_XDP_P1_CH3 | 603 ESR_INT_XDP_P1_CH2 | 604 ESR_INT_XDP_P1_CH1 | 605 ESR_INT_XDP_P1_CH0); 606 break; 607 608 default: 609 return -EINVAL; 610 } 611 612 while (max_retry--) { 613 sig = nr64(ESR_INT_SIGNALS); 614 if ((sig & mask) == val) 615 break; 616 617 mdelay(500); 618 } 619 620 if ((sig & mask) != val) { 621 pr_info("NIU Port %u signal bits [%08x] are not [%08x] for 10G...trying 1G\n", 622 np->port, (int)(sig & mask), (int)val); 623 624 /* 10G failed, try initializing at 1G */ 625 err = serdes_init_niu_1g_serdes(np); 626 if (!err) { 627 np->flags &= ~NIU_FLAGS_10G; 628 np->mac_xcvr = MAC_XCVR_PCS; 629 } else { 630 netdev_err(np->dev, "Port %u 10G/1G SERDES Link Failed\n", 631 np->port); 632 return -ENODEV; 633 } 634 } 635 return 0; 636 } 637 638 static int esr_read_rxtx_ctrl(struct niu *np, unsigned long chan, u32 *val) 639 { 640 int err; 641 642 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR, ESR_RXTX_CTRL_L(chan)); 643 if (err >= 0) { 644 *val = (err & 0xffff); 645 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR, 646 ESR_RXTX_CTRL_H(chan)); 647 if (err >= 0) 648 *val |= ((err & 0xffff) << 16); 649 err = 0; 650 } 651 return err; 652 } 653 654 static int esr_read_glue0(struct niu *np, unsigned long chan, u32 *val) 655 { 656 int err; 657 658 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR, 659 ESR_GLUE_CTRL0_L(chan)); 660 if (err >= 0) { 661 *val = (err & 0xffff); 662 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR, 663 ESR_GLUE_CTRL0_H(chan)); 664 if (err >= 0) { 665 *val |= ((err & 0xffff) << 16); 666 err = 0; 667 } 668 } 669 return err; 670 } 671 672 static int esr_read_reset(struct niu *np, u32 *val) 673 { 674 int err; 675 676 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR, 677 ESR_RXTX_RESET_CTRL_L); 678 if (err >= 0) { 679 *val = (err & 0xffff); 680 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR, 681 ESR_RXTX_RESET_CTRL_H); 682 if (err >= 0) { 683 *val |= ((err & 0xffff) << 16); 684 err = 0; 685 } 686 } 687 return err; 688 } 689 690 static int esr_write_rxtx_ctrl(struct niu *np, unsigned long chan, u32 val) 691 { 692 int err; 693 694 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR, 695 ESR_RXTX_CTRL_L(chan), val & 0xffff); 696 if (!err) 697 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR, 698 ESR_RXTX_CTRL_H(chan), (val >> 16)); 699 return err; 700 } 701 702 static int esr_write_glue0(struct niu *np, unsigned long chan, u32 val) 703 { 704 int err; 705 706 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR, 707 ESR_GLUE_CTRL0_L(chan), val & 0xffff); 708 if (!err) 709 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR, 710 ESR_GLUE_CTRL0_H(chan), (val >> 16)); 711 return err; 712 } 713 714 static int esr_reset(struct niu *np) 715 { 716 u32 uninitialized_var(reset); 717 int err; 718 719 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR, 720 ESR_RXTX_RESET_CTRL_L, 0x0000); 721 if (err) 722 return err; 723 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR, 724 ESR_RXTX_RESET_CTRL_H, 0xffff); 725 if (err) 726 return err; 727 udelay(200); 728 729 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR, 730 ESR_RXTX_RESET_CTRL_L, 0xffff); 731 if (err) 732 return err; 733 udelay(200); 734 735 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR, 736 ESR_RXTX_RESET_CTRL_H, 0x0000); 737 if (err) 738 return err; 739 udelay(200); 740 741 err = esr_read_reset(np, &reset); 742 if (err) 743 return err; 744 if (reset != 0) { 745 netdev_err(np->dev, "Port %u ESR_RESET did not clear [%08x]\n", 746 np->port, reset); 747 return -ENODEV; 748 } 749 750 return 0; 751 } 752 753 static int serdes_init_10g(struct niu *np) 754 { 755 struct niu_link_config *lp = &np->link_config; 756 unsigned long ctrl_reg, test_cfg_reg, i; 757 u64 ctrl_val, test_cfg_val, sig, mask, val; 758 int err; 759 760 switch (np->port) { 761 case 0: 762 ctrl_reg = ENET_SERDES_0_CTRL_CFG; 763 test_cfg_reg = ENET_SERDES_0_TEST_CFG; 764 break; 765 case 1: 766 ctrl_reg = ENET_SERDES_1_CTRL_CFG; 767 test_cfg_reg = ENET_SERDES_1_TEST_CFG; 768 break; 769 770 default: 771 return -EINVAL; 772 } 773 ctrl_val = (ENET_SERDES_CTRL_SDET_0 | 774 ENET_SERDES_CTRL_SDET_1 | 775 ENET_SERDES_CTRL_SDET_2 | 776 ENET_SERDES_CTRL_SDET_3 | 777 (0x5 << ENET_SERDES_CTRL_EMPH_0_SHIFT) | 778 (0x5 << ENET_SERDES_CTRL_EMPH_1_SHIFT) | 779 (0x5 << ENET_SERDES_CTRL_EMPH_2_SHIFT) | 780 (0x5 << ENET_SERDES_CTRL_EMPH_3_SHIFT) | 781 (0x1 << ENET_SERDES_CTRL_LADJ_0_SHIFT) | 782 (0x1 << ENET_SERDES_CTRL_LADJ_1_SHIFT) | 783 (0x1 << ENET_SERDES_CTRL_LADJ_2_SHIFT) | 784 (0x1 << ENET_SERDES_CTRL_LADJ_3_SHIFT)); 785 test_cfg_val = 0; 786 787 if (lp->loopback_mode == LOOPBACK_PHY) { 788 test_cfg_val |= ((ENET_TEST_MD_PAD_LOOPBACK << 789 ENET_SERDES_TEST_MD_0_SHIFT) | 790 (ENET_TEST_MD_PAD_LOOPBACK << 791 ENET_SERDES_TEST_MD_1_SHIFT) | 792 (ENET_TEST_MD_PAD_LOOPBACK << 793 ENET_SERDES_TEST_MD_2_SHIFT) | 794 (ENET_TEST_MD_PAD_LOOPBACK << 795 ENET_SERDES_TEST_MD_3_SHIFT)); 796 } 797 798 nw64(ctrl_reg, ctrl_val); 799 nw64(test_cfg_reg, test_cfg_val); 800 801 /* Initialize all 4 lanes of the SERDES. */ 802 for (i = 0; i < 4; i++) { 803 u32 rxtx_ctrl, glue0; 804 805 err = esr_read_rxtx_ctrl(np, i, &rxtx_ctrl); 806 if (err) 807 return err; 808 err = esr_read_glue0(np, i, &glue0); 809 if (err) 810 return err; 811 812 rxtx_ctrl &= ~(ESR_RXTX_CTRL_VMUXLO); 813 rxtx_ctrl |= (ESR_RXTX_CTRL_ENSTRETCH | 814 (2 << ESR_RXTX_CTRL_VMUXLO_SHIFT)); 815 816 glue0 &= ~(ESR_GLUE_CTRL0_SRATE | 817 ESR_GLUE_CTRL0_THCNT | 818 ESR_GLUE_CTRL0_BLTIME); 819 glue0 |= (ESR_GLUE_CTRL0_RXLOSENAB | 820 (0xf << ESR_GLUE_CTRL0_SRATE_SHIFT) | 821 (0xff << ESR_GLUE_CTRL0_THCNT_SHIFT) | 822 (BLTIME_300_CYCLES << 823 ESR_GLUE_CTRL0_BLTIME_SHIFT)); 824 825 err = esr_write_rxtx_ctrl(np, i, rxtx_ctrl); 826 if (err) 827 return err; 828 err = esr_write_glue0(np, i, glue0); 829 if (err) 830 return err; 831 } 832 833 err = esr_reset(np); 834 if (err) 835 return err; 836 837 sig = nr64(ESR_INT_SIGNALS); 838 switch (np->port) { 839 case 0: 840 mask = ESR_INT_SIGNALS_P0_BITS; 841 val = (ESR_INT_SRDY0_P0 | 842 ESR_INT_DET0_P0 | 843 ESR_INT_XSRDY_P0 | 844 ESR_INT_XDP_P0_CH3 | 845 ESR_INT_XDP_P0_CH2 | 846 ESR_INT_XDP_P0_CH1 | 847 ESR_INT_XDP_P0_CH0); 848 break; 849 850 case 1: 851 mask = ESR_INT_SIGNALS_P1_BITS; 852 val = (ESR_INT_SRDY0_P1 | 853 ESR_INT_DET0_P1 | 854 ESR_INT_XSRDY_P1 | 855 ESR_INT_XDP_P1_CH3 | 856 ESR_INT_XDP_P1_CH2 | 857 ESR_INT_XDP_P1_CH1 | 858 ESR_INT_XDP_P1_CH0); 859 break; 860 861 default: 862 return -EINVAL; 863 } 864 865 if ((sig & mask) != val) { 866 if (np->flags & NIU_FLAGS_HOTPLUG_PHY) { 867 np->flags &= ~NIU_FLAGS_HOTPLUG_PHY_PRESENT; 868 return 0; 869 } 870 netdev_err(np->dev, "Port %u signal bits [%08x] are not [%08x]\n", 871 np->port, (int)(sig & mask), (int)val); 872 return -ENODEV; 873 } 874 if (np->flags & NIU_FLAGS_HOTPLUG_PHY) 875 np->flags |= NIU_FLAGS_HOTPLUG_PHY_PRESENT; 876 return 0; 877 } 878 879 static int serdes_init_1g(struct niu *np) 880 { 881 u64 val; 882 883 val = nr64(ENET_SERDES_1_PLL_CFG); 884 val &= ~ENET_SERDES_PLL_FBDIV2; 885 switch (np->port) { 886 case 0: 887 val |= ENET_SERDES_PLL_HRATE0; 888 break; 889 case 1: 890 val |= ENET_SERDES_PLL_HRATE1; 891 break; 892 case 2: 893 val |= ENET_SERDES_PLL_HRATE2; 894 break; 895 case 3: 896 val |= ENET_SERDES_PLL_HRATE3; 897 break; 898 default: 899 return -EINVAL; 900 } 901 nw64(ENET_SERDES_1_PLL_CFG, val); 902 903 return 0; 904 } 905 906 static int serdes_init_1g_serdes(struct niu *np) 907 { 908 struct niu_link_config *lp = &np->link_config; 909 unsigned long ctrl_reg, test_cfg_reg, pll_cfg, i; 910 u64 ctrl_val, test_cfg_val, sig, mask, val; 911 int err; 912 u64 reset_val, val_rd; 913 914 val = ENET_SERDES_PLL_HRATE0 | ENET_SERDES_PLL_HRATE1 | 915 ENET_SERDES_PLL_HRATE2 | ENET_SERDES_PLL_HRATE3 | 916 ENET_SERDES_PLL_FBDIV0; 917 switch (np->port) { 918 case 0: 919 reset_val = ENET_SERDES_RESET_0; 920 ctrl_reg = ENET_SERDES_0_CTRL_CFG; 921 test_cfg_reg = ENET_SERDES_0_TEST_CFG; 922 pll_cfg = ENET_SERDES_0_PLL_CFG; 923 break; 924 case 1: 925 reset_val = ENET_SERDES_RESET_1; 926 ctrl_reg = ENET_SERDES_1_CTRL_CFG; 927 test_cfg_reg = ENET_SERDES_1_TEST_CFG; 928 pll_cfg = ENET_SERDES_1_PLL_CFG; 929 break; 930 931 default: 932 return -EINVAL; 933 } 934 ctrl_val = (ENET_SERDES_CTRL_SDET_0 | 935 ENET_SERDES_CTRL_SDET_1 | 936 ENET_SERDES_CTRL_SDET_2 | 937 ENET_SERDES_CTRL_SDET_3 | 938 (0x5 << ENET_SERDES_CTRL_EMPH_0_SHIFT) | 939 (0x5 << ENET_SERDES_CTRL_EMPH_1_SHIFT) | 940 (0x5 << ENET_SERDES_CTRL_EMPH_2_SHIFT) | 941 (0x5 << ENET_SERDES_CTRL_EMPH_3_SHIFT) | 942 (0x1 << ENET_SERDES_CTRL_LADJ_0_SHIFT) | 943 (0x1 << ENET_SERDES_CTRL_LADJ_1_SHIFT) | 944 (0x1 << ENET_SERDES_CTRL_LADJ_2_SHIFT) | 945 (0x1 << ENET_SERDES_CTRL_LADJ_3_SHIFT)); 946 test_cfg_val = 0; 947 948 if (lp->loopback_mode == LOOPBACK_PHY) { 949 test_cfg_val |= ((ENET_TEST_MD_PAD_LOOPBACK << 950 ENET_SERDES_TEST_MD_0_SHIFT) | 951 (ENET_TEST_MD_PAD_LOOPBACK << 952 ENET_SERDES_TEST_MD_1_SHIFT) | 953 (ENET_TEST_MD_PAD_LOOPBACK << 954 ENET_SERDES_TEST_MD_2_SHIFT) | 955 (ENET_TEST_MD_PAD_LOOPBACK << 956 ENET_SERDES_TEST_MD_3_SHIFT)); 957 } 958 959 nw64(ENET_SERDES_RESET, reset_val); 960 mdelay(20); 961 val_rd = nr64(ENET_SERDES_RESET); 962 val_rd &= ~reset_val; 963 nw64(pll_cfg, val); 964 nw64(ctrl_reg, ctrl_val); 965 nw64(test_cfg_reg, test_cfg_val); 966 nw64(ENET_SERDES_RESET, val_rd); 967 mdelay(2000); 968 969 /* Initialize all 4 lanes of the SERDES. */ 970 for (i = 0; i < 4; i++) { 971 u32 rxtx_ctrl, glue0; 972 973 err = esr_read_rxtx_ctrl(np, i, &rxtx_ctrl); 974 if (err) 975 return err; 976 err = esr_read_glue0(np, i, &glue0); 977 if (err) 978 return err; 979 980 rxtx_ctrl &= ~(ESR_RXTX_CTRL_VMUXLO); 981 rxtx_ctrl |= (ESR_RXTX_CTRL_ENSTRETCH | 982 (2 << ESR_RXTX_CTRL_VMUXLO_SHIFT)); 983 984 glue0 &= ~(ESR_GLUE_CTRL0_SRATE | 985 ESR_GLUE_CTRL0_THCNT | 986 ESR_GLUE_CTRL0_BLTIME); 987 glue0 |= (ESR_GLUE_CTRL0_RXLOSENAB | 988 (0xf << ESR_GLUE_CTRL0_SRATE_SHIFT) | 989 (0xff << ESR_GLUE_CTRL0_THCNT_SHIFT) | 990 (BLTIME_300_CYCLES << 991 ESR_GLUE_CTRL0_BLTIME_SHIFT)); 992 993 err = esr_write_rxtx_ctrl(np, i, rxtx_ctrl); 994 if (err) 995 return err; 996 err = esr_write_glue0(np, i, glue0); 997 if (err) 998 return err; 999 } 1000 1001 1002 sig = nr64(ESR_INT_SIGNALS); 1003 switch (np->port) { 1004 case 0: 1005 val = (ESR_INT_SRDY0_P0 | ESR_INT_DET0_P0); 1006 mask = val; 1007 break; 1008 1009 case 1: 1010 val = (ESR_INT_SRDY0_P1 | ESR_INT_DET0_P1); 1011 mask = val; 1012 break; 1013 1014 default: 1015 return -EINVAL; 1016 } 1017 1018 if ((sig & mask) != val) { 1019 netdev_err(np->dev, "Port %u signal bits [%08x] are not [%08x]\n", 1020 np->port, (int)(sig & mask), (int)val); 1021 return -ENODEV; 1022 } 1023 1024 return 0; 1025 } 1026 1027 static int link_status_1g_serdes(struct niu *np, int *link_up_p) 1028 { 1029 struct niu_link_config *lp = &np->link_config; 1030 int link_up; 1031 u64 val; 1032 u16 current_speed; 1033 unsigned long flags; 1034 u8 current_duplex; 1035 1036 link_up = 0; 1037 current_speed = SPEED_INVALID; 1038 current_duplex = DUPLEX_INVALID; 1039 1040 spin_lock_irqsave(&np->lock, flags); 1041 1042 val = nr64_pcs(PCS_MII_STAT); 1043 1044 if (val & PCS_MII_STAT_LINK_STATUS) { 1045 link_up = 1; 1046 current_speed = SPEED_1000; 1047 current_duplex = DUPLEX_FULL; 1048 } 1049 1050 lp->active_speed = current_speed; 1051 lp->active_duplex = current_duplex; 1052 spin_unlock_irqrestore(&np->lock, flags); 1053 1054 *link_up_p = link_up; 1055 return 0; 1056 } 1057 1058 static int link_status_10g_serdes(struct niu *np, int *link_up_p) 1059 { 1060 unsigned long flags; 1061 struct niu_link_config *lp = &np->link_config; 1062 int link_up = 0; 1063 int link_ok = 1; 1064 u64 val, val2; 1065 u16 current_speed; 1066 u8 current_duplex; 1067 1068 if (!(np->flags & NIU_FLAGS_10G)) 1069 return link_status_1g_serdes(np, link_up_p); 1070 1071 current_speed = SPEED_INVALID; 1072 current_duplex = DUPLEX_INVALID; 1073 spin_lock_irqsave(&np->lock, flags); 1074 1075 val = nr64_xpcs(XPCS_STATUS(0)); 1076 val2 = nr64_mac(XMAC_INTER2); 1077 if (val2 & 0x01000000) 1078 link_ok = 0; 1079 1080 if ((val & 0x1000ULL) && link_ok) { 1081 link_up = 1; 1082 current_speed = SPEED_10000; 1083 current_duplex = DUPLEX_FULL; 1084 } 1085 lp->active_speed = current_speed; 1086 lp->active_duplex = current_duplex; 1087 spin_unlock_irqrestore(&np->lock, flags); 1088 *link_up_p = link_up; 1089 return 0; 1090 } 1091 1092 static int link_status_mii(struct niu *np, int *link_up_p) 1093 { 1094 struct niu_link_config *lp = &np->link_config; 1095 int err; 1096 int bmsr, advert, ctrl1000, stat1000, lpa, bmcr, estatus; 1097 int supported, advertising, active_speed, active_duplex; 1098 1099 err = mii_read(np, np->phy_addr, MII_BMCR); 1100 if (unlikely(err < 0)) 1101 return err; 1102 bmcr = err; 1103 1104 err = mii_read(np, np->phy_addr, MII_BMSR); 1105 if (unlikely(err < 0)) 1106 return err; 1107 bmsr = err; 1108 1109 err = mii_read(np, np->phy_addr, MII_ADVERTISE); 1110 if (unlikely(err < 0)) 1111 return err; 1112 advert = err; 1113 1114 err = mii_read(np, np->phy_addr, MII_LPA); 1115 if (unlikely(err < 0)) 1116 return err; 1117 lpa = err; 1118 1119 if (likely(bmsr & BMSR_ESTATEN)) { 1120 err = mii_read(np, np->phy_addr, MII_ESTATUS); 1121 if (unlikely(err < 0)) 1122 return err; 1123 estatus = err; 1124 1125 err = mii_read(np, np->phy_addr, MII_CTRL1000); 1126 if (unlikely(err < 0)) 1127 return err; 1128 ctrl1000 = err; 1129 1130 err = mii_read(np, np->phy_addr, MII_STAT1000); 1131 if (unlikely(err < 0)) 1132 return err; 1133 stat1000 = err; 1134 } else 1135 estatus = ctrl1000 = stat1000 = 0; 1136 1137 supported = 0; 1138 if (bmsr & BMSR_ANEGCAPABLE) 1139 supported |= SUPPORTED_Autoneg; 1140 if (bmsr & BMSR_10HALF) 1141 supported |= SUPPORTED_10baseT_Half; 1142 if (bmsr & BMSR_10FULL) 1143 supported |= SUPPORTED_10baseT_Full; 1144 if (bmsr & BMSR_100HALF) 1145 supported |= SUPPORTED_100baseT_Half; 1146 if (bmsr & BMSR_100FULL) 1147 supported |= SUPPORTED_100baseT_Full; 1148 if (estatus & ESTATUS_1000_THALF) 1149 supported |= SUPPORTED_1000baseT_Half; 1150 if (estatus & ESTATUS_1000_TFULL) 1151 supported |= SUPPORTED_1000baseT_Full; 1152 lp->supported = supported; 1153 1154 advertising = mii_adv_to_ethtool_adv_t(advert); 1155 advertising |= mii_ctrl1000_to_ethtool_adv_t(ctrl1000); 1156 1157 if (bmcr & BMCR_ANENABLE) { 1158 int neg, neg1000; 1159 1160 lp->active_autoneg = 1; 1161 advertising |= ADVERTISED_Autoneg; 1162 1163 neg = advert & lpa; 1164 neg1000 = (ctrl1000 << 2) & stat1000; 1165 1166 if (neg1000 & (LPA_1000FULL | LPA_1000HALF)) 1167 active_speed = SPEED_1000; 1168 else if (neg & LPA_100) 1169 active_speed = SPEED_100; 1170 else if (neg & (LPA_10HALF | LPA_10FULL)) 1171 active_speed = SPEED_10; 1172 else 1173 active_speed = SPEED_INVALID; 1174 1175 if ((neg1000 & LPA_1000FULL) || (neg & LPA_DUPLEX)) 1176 active_duplex = DUPLEX_FULL; 1177 else if (active_speed != SPEED_INVALID) 1178 active_duplex = DUPLEX_HALF; 1179 else 1180 active_duplex = DUPLEX_INVALID; 1181 } else { 1182 lp->active_autoneg = 0; 1183 1184 if ((bmcr & BMCR_SPEED1000) && !(bmcr & BMCR_SPEED100)) 1185 active_speed = SPEED_1000; 1186 else if (bmcr & BMCR_SPEED100) 1187 active_speed = SPEED_100; 1188 else 1189 active_speed = SPEED_10; 1190 1191 if (bmcr & BMCR_FULLDPLX) 1192 active_duplex = DUPLEX_FULL; 1193 else 1194 active_duplex = DUPLEX_HALF; 1195 } 1196 1197 lp->active_advertising = advertising; 1198 lp->active_speed = active_speed; 1199 lp->active_duplex = active_duplex; 1200 *link_up_p = !!(bmsr & BMSR_LSTATUS); 1201 1202 return 0; 1203 } 1204 1205 static int link_status_1g_rgmii(struct niu *np, int *link_up_p) 1206 { 1207 struct niu_link_config *lp = &np->link_config; 1208 u16 current_speed, bmsr; 1209 unsigned long flags; 1210 u8 current_duplex; 1211 int err, link_up; 1212 1213 link_up = 0; 1214 current_speed = SPEED_INVALID; 1215 current_duplex = DUPLEX_INVALID; 1216 1217 spin_lock_irqsave(&np->lock, flags); 1218 1219 err = -EINVAL; 1220 1221 err = mii_read(np, np->phy_addr, MII_BMSR); 1222 if (err < 0) 1223 goto out; 1224 1225 bmsr = err; 1226 if (bmsr & BMSR_LSTATUS) { 1227 u16 adv, lpa; 1228 1229 err = mii_read(np, np->phy_addr, MII_ADVERTISE); 1230 if (err < 0) 1231 goto out; 1232 adv = err; 1233 1234 err = mii_read(np, np->phy_addr, MII_LPA); 1235 if (err < 0) 1236 goto out; 1237 lpa = err; 1238 1239 err = mii_read(np, np->phy_addr, MII_ESTATUS); 1240 if (err < 0) 1241 goto out; 1242 link_up = 1; 1243 current_speed = SPEED_1000; 1244 current_duplex = DUPLEX_FULL; 1245 1246 } 1247 lp->active_speed = current_speed; 1248 lp->active_duplex = current_duplex; 1249 err = 0; 1250 1251 out: 1252 spin_unlock_irqrestore(&np->lock, flags); 1253 1254 *link_up_p = link_up; 1255 return err; 1256 } 1257 1258 static int link_status_1g(struct niu *np, int *link_up_p) 1259 { 1260 struct niu_link_config *lp = &np->link_config; 1261 unsigned long flags; 1262 int err; 1263 1264 spin_lock_irqsave(&np->lock, flags); 1265 1266 err = link_status_mii(np, link_up_p); 1267 lp->supported |= SUPPORTED_TP; 1268 lp->active_advertising |= ADVERTISED_TP; 1269 1270 spin_unlock_irqrestore(&np->lock, flags); 1271 return err; 1272 } 1273 1274 static int bcm8704_reset(struct niu *np) 1275 { 1276 int err, limit; 1277 1278 err = mdio_read(np, np->phy_addr, 1279 BCM8704_PHYXS_DEV_ADDR, MII_BMCR); 1280 if (err < 0 || err == 0xffff) 1281 return err; 1282 err |= BMCR_RESET; 1283 err = mdio_write(np, np->phy_addr, BCM8704_PHYXS_DEV_ADDR, 1284 MII_BMCR, err); 1285 if (err) 1286 return err; 1287 1288 limit = 1000; 1289 while (--limit >= 0) { 1290 err = mdio_read(np, np->phy_addr, 1291 BCM8704_PHYXS_DEV_ADDR, MII_BMCR); 1292 if (err < 0) 1293 return err; 1294 if (!(err & BMCR_RESET)) 1295 break; 1296 } 1297 if (limit < 0) { 1298 netdev_err(np->dev, "Port %u PHY will not reset (bmcr=%04x)\n", 1299 np->port, (err & 0xffff)); 1300 return -ENODEV; 1301 } 1302 return 0; 1303 } 1304 1305 /* When written, certain PHY registers need to be read back twice 1306 * in order for the bits to settle properly. 1307 */ 1308 static int bcm8704_user_dev3_readback(struct niu *np, int reg) 1309 { 1310 int err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR, reg); 1311 if (err < 0) 1312 return err; 1313 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR, reg); 1314 if (err < 0) 1315 return err; 1316 return 0; 1317 } 1318 1319 static int bcm8706_init_user_dev3(struct niu *np) 1320 { 1321 int err; 1322 1323 1324 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR, 1325 BCM8704_USER_OPT_DIGITAL_CTRL); 1326 if (err < 0) 1327 return err; 1328 err &= ~USER_ODIG_CTRL_GPIOS; 1329 err |= (0x3 << USER_ODIG_CTRL_GPIOS_SHIFT); 1330 err |= USER_ODIG_CTRL_RESV2; 1331 err = mdio_write(np, np->phy_addr, BCM8704_USER_DEV3_ADDR, 1332 BCM8704_USER_OPT_DIGITAL_CTRL, err); 1333 if (err) 1334 return err; 1335 1336 mdelay(1000); 1337 1338 return 0; 1339 } 1340 1341 static int bcm8704_init_user_dev3(struct niu *np) 1342 { 1343 int err; 1344 1345 err = mdio_write(np, np->phy_addr, 1346 BCM8704_USER_DEV3_ADDR, BCM8704_USER_CONTROL, 1347 (USER_CONTROL_OPTXRST_LVL | 1348 USER_CONTROL_OPBIASFLT_LVL | 1349 USER_CONTROL_OBTMPFLT_LVL | 1350 USER_CONTROL_OPPRFLT_LVL | 1351 USER_CONTROL_OPTXFLT_LVL | 1352 USER_CONTROL_OPRXLOS_LVL | 1353 USER_CONTROL_OPRXFLT_LVL | 1354 USER_CONTROL_OPTXON_LVL | 1355 (0x3f << USER_CONTROL_RES1_SHIFT))); 1356 if (err) 1357 return err; 1358 1359 err = mdio_write(np, np->phy_addr, 1360 BCM8704_USER_DEV3_ADDR, BCM8704_USER_PMD_TX_CONTROL, 1361 (USER_PMD_TX_CTL_XFP_CLKEN | 1362 (1 << USER_PMD_TX_CTL_TX_DAC_TXD_SH) | 1363 (2 << USER_PMD_TX_CTL_TX_DAC_TXCK_SH) | 1364 USER_PMD_TX_CTL_TSCK_LPWREN)); 1365 if (err) 1366 return err; 1367 1368 err = bcm8704_user_dev3_readback(np, BCM8704_USER_CONTROL); 1369 if (err) 1370 return err; 1371 err = bcm8704_user_dev3_readback(np, BCM8704_USER_PMD_TX_CONTROL); 1372 if (err) 1373 return err; 1374 1375 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR, 1376 BCM8704_USER_OPT_DIGITAL_CTRL); 1377 if (err < 0) 1378 return err; 1379 err &= ~USER_ODIG_CTRL_GPIOS; 1380 err |= (0x3 << USER_ODIG_CTRL_GPIOS_SHIFT); 1381 err = mdio_write(np, np->phy_addr, BCM8704_USER_DEV3_ADDR, 1382 BCM8704_USER_OPT_DIGITAL_CTRL, err); 1383 if (err) 1384 return err; 1385 1386 mdelay(1000); 1387 1388 return 0; 1389 } 1390 1391 static int mrvl88x2011_act_led(struct niu *np, int val) 1392 { 1393 int err; 1394 1395 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV2_ADDR, 1396 MRVL88X2011_LED_8_TO_11_CTL); 1397 if (err < 0) 1398 return err; 1399 1400 err &= ~MRVL88X2011_LED(MRVL88X2011_LED_ACT,MRVL88X2011_LED_CTL_MASK); 1401 err |= MRVL88X2011_LED(MRVL88X2011_LED_ACT,val); 1402 1403 return mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV2_ADDR, 1404 MRVL88X2011_LED_8_TO_11_CTL, err); 1405 } 1406 1407 static int mrvl88x2011_led_blink_rate(struct niu *np, int rate) 1408 { 1409 int err; 1410 1411 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV2_ADDR, 1412 MRVL88X2011_LED_BLINK_CTL); 1413 if (err >= 0) { 1414 err &= ~MRVL88X2011_LED_BLKRATE_MASK; 1415 err |= (rate << 4); 1416 1417 err = mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV2_ADDR, 1418 MRVL88X2011_LED_BLINK_CTL, err); 1419 } 1420 1421 return err; 1422 } 1423 1424 static int xcvr_init_10g_mrvl88x2011(struct niu *np) 1425 { 1426 int err; 1427 1428 /* Set LED functions */ 1429 err = mrvl88x2011_led_blink_rate(np, MRVL88X2011_LED_BLKRATE_134MS); 1430 if (err) 1431 return err; 1432 1433 /* led activity */ 1434 err = mrvl88x2011_act_led(np, MRVL88X2011_LED_CTL_OFF); 1435 if (err) 1436 return err; 1437 1438 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV3_ADDR, 1439 MRVL88X2011_GENERAL_CTL); 1440 if (err < 0) 1441 return err; 1442 1443 err |= MRVL88X2011_ENA_XFPREFCLK; 1444 1445 err = mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV3_ADDR, 1446 MRVL88X2011_GENERAL_CTL, err); 1447 if (err < 0) 1448 return err; 1449 1450 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR, 1451 MRVL88X2011_PMA_PMD_CTL_1); 1452 if (err < 0) 1453 return err; 1454 1455 if (np->link_config.loopback_mode == LOOPBACK_MAC) 1456 err |= MRVL88X2011_LOOPBACK; 1457 else 1458 err &= ~MRVL88X2011_LOOPBACK; 1459 1460 err = mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR, 1461 MRVL88X2011_PMA_PMD_CTL_1, err); 1462 if (err < 0) 1463 return err; 1464 1465 /* Enable PMD */ 1466 return mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR, 1467 MRVL88X2011_10G_PMD_TX_DIS, MRVL88X2011_ENA_PMDTX); 1468 } 1469 1470 1471 static int xcvr_diag_bcm870x(struct niu *np) 1472 { 1473 u16 analog_stat0, tx_alarm_status; 1474 int err = 0; 1475 1476 #if 1 1477 err = mdio_read(np, np->phy_addr, BCM8704_PMA_PMD_DEV_ADDR, 1478 MII_STAT1000); 1479 if (err < 0) 1480 return err; 1481 pr_info("Port %u PMA_PMD(MII_STAT1000) [%04x]\n", np->port, err); 1482 1483 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR, 0x20); 1484 if (err < 0) 1485 return err; 1486 pr_info("Port %u USER_DEV3(0x20) [%04x]\n", np->port, err); 1487 1488 err = mdio_read(np, np->phy_addr, BCM8704_PHYXS_DEV_ADDR, 1489 MII_NWAYTEST); 1490 if (err < 0) 1491 return err; 1492 pr_info("Port %u PHYXS(MII_NWAYTEST) [%04x]\n", np->port, err); 1493 #endif 1494 1495 /* XXX dig this out it might not be so useful XXX */ 1496 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR, 1497 BCM8704_USER_ANALOG_STATUS0); 1498 if (err < 0) 1499 return err; 1500 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR, 1501 BCM8704_USER_ANALOG_STATUS0); 1502 if (err < 0) 1503 return err; 1504 analog_stat0 = err; 1505 1506 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR, 1507 BCM8704_USER_TX_ALARM_STATUS); 1508 if (err < 0) 1509 return err; 1510 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR, 1511 BCM8704_USER_TX_ALARM_STATUS); 1512 if (err < 0) 1513 return err; 1514 tx_alarm_status = err; 1515 1516 if (analog_stat0 != 0x03fc) { 1517 if ((analog_stat0 == 0x43bc) && (tx_alarm_status != 0)) { 1518 pr_info("Port %u cable not connected or bad cable\n", 1519 np->port); 1520 } else if (analog_stat0 == 0x639c) { 1521 pr_info("Port %u optical module is bad or missing\n", 1522 np->port); 1523 } 1524 } 1525 1526 return 0; 1527 } 1528 1529 static int xcvr_10g_set_lb_bcm870x(struct niu *np) 1530 { 1531 struct niu_link_config *lp = &np->link_config; 1532 int err; 1533 1534 err = mdio_read(np, np->phy_addr, BCM8704_PCS_DEV_ADDR, 1535 MII_BMCR); 1536 if (err < 0) 1537 return err; 1538 1539 err &= ~BMCR_LOOPBACK; 1540 1541 if (lp->loopback_mode == LOOPBACK_MAC) 1542 err |= BMCR_LOOPBACK; 1543 1544 err = mdio_write(np, np->phy_addr, BCM8704_PCS_DEV_ADDR, 1545 MII_BMCR, err); 1546 if (err) 1547 return err; 1548 1549 return 0; 1550 } 1551 1552 static int xcvr_init_10g_bcm8706(struct niu *np) 1553 { 1554 int err = 0; 1555 u64 val; 1556 1557 if ((np->flags & NIU_FLAGS_HOTPLUG_PHY) && 1558 (np->flags & NIU_FLAGS_HOTPLUG_PHY_PRESENT) == 0) 1559 return err; 1560 1561 val = nr64_mac(XMAC_CONFIG); 1562 val &= ~XMAC_CONFIG_LED_POLARITY; 1563 val |= XMAC_CONFIG_FORCE_LED_ON; 1564 nw64_mac(XMAC_CONFIG, val); 1565 1566 val = nr64(MIF_CONFIG); 1567 val |= MIF_CONFIG_INDIRECT_MODE; 1568 nw64(MIF_CONFIG, val); 1569 1570 err = bcm8704_reset(np); 1571 if (err) 1572 return err; 1573 1574 err = xcvr_10g_set_lb_bcm870x(np); 1575 if (err) 1576 return err; 1577 1578 err = bcm8706_init_user_dev3(np); 1579 if (err) 1580 return err; 1581 1582 err = xcvr_diag_bcm870x(np); 1583 if (err) 1584 return err; 1585 1586 return 0; 1587 } 1588 1589 static int xcvr_init_10g_bcm8704(struct niu *np) 1590 { 1591 int err; 1592 1593 err = bcm8704_reset(np); 1594 if (err) 1595 return err; 1596 1597 err = bcm8704_init_user_dev3(np); 1598 if (err) 1599 return err; 1600 1601 err = xcvr_10g_set_lb_bcm870x(np); 1602 if (err) 1603 return err; 1604 1605 err = xcvr_diag_bcm870x(np); 1606 if (err) 1607 return err; 1608 1609 return 0; 1610 } 1611 1612 static int xcvr_init_10g(struct niu *np) 1613 { 1614 int phy_id, err; 1615 u64 val; 1616 1617 val = nr64_mac(XMAC_CONFIG); 1618 val &= ~XMAC_CONFIG_LED_POLARITY; 1619 val |= XMAC_CONFIG_FORCE_LED_ON; 1620 nw64_mac(XMAC_CONFIG, val); 1621 1622 /* XXX shared resource, lock parent XXX */ 1623 val = nr64(MIF_CONFIG); 1624 val |= MIF_CONFIG_INDIRECT_MODE; 1625 nw64(MIF_CONFIG, val); 1626 1627 phy_id = phy_decode(np->parent->port_phy, np->port); 1628 phy_id = np->parent->phy_probe_info.phy_id[phy_id][np->port]; 1629 1630 /* handle different phy types */ 1631 switch (phy_id & NIU_PHY_ID_MASK) { 1632 case NIU_PHY_ID_MRVL88X2011: 1633 err = xcvr_init_10g_mrvl88x2011(np); 1634 break; 1635 1636 default: /* bcom 8704 */ 1637 err = xcvr_init_10g_bcm8704(np); 1638 break; 1639 } 1640 1641 return err; 1642 } 1643 1644 static int mii_reset(struct niu *np) 1645 { 1646 int limit, err; 1647 1648 err = mii_write(np, np->phy_addr, MII_BMCR, BMCR_RESET); 1649 if (err) 1650 return err; 1651 1652 limit = 1000; 1653 while (--limit >= 0) { 1654 udelay(500); 1655 err = mii_read(np, np->phy_addr, MII_BMCR); 1656 if (err < 0) 1657 return err; 1658 if (!(err & BMCR_RESET)) 1659 break; 1660 } 1661 if (limit < 0) { 1662 netdev_err(np->dev, "Port %u MII would not reset, bmcr[%04x]\n", 1663 np->port, err); 1664 return -ENODEV; 1665 } 1666 1667 return 0; 1668 } 1669 1670 static int xcvr_init_1g_rgmii(struct niu *np) 1671 { 1672 int err; 1673 u64 val; 1674 u16 bmcr, bmsr, estat; 1675 1676 val = nr64(MIF_CONFIG); 1677 val &= ~MIF_CONFIG_INDIRECT_MODE; 1678 nw64(MIF_CONFIG, val); 1679 1680 err = mii_reset(np); 1681 if (err) 1682 return err; 1683 1684 err = mii_read(np, np->phy_addr, MII_BMSR); 1685 if (err < 0) 1686 return err; 1687 bmsr = err; 1688 1689 estat = 0; 1690 if (bmsr & BMSR_ESTATEN) { 1691 err = mii_read(np, np->phy_addr, MII_ESTATUS); 1692 if (err < 0) 1693 return err; 1694 estat = err; 1695 } 1696 1697 bmcr = 0; 1698 err = mii_write(np, np->phy_addr, MII_BMCR, bmcr); 1699 if (err) 1700 return err; 1701 1702 if (bmsr & BMSR_ESTATEN) { 1703 u16 ctrl1000 = 0; 1704 1705 if (estat & ESTATUS_1000_TFULL) 1706 ctrl1000 |= ADVERTISE_1000FULL; 1707 err = mii_write(np, np->phy_addr, MII_CTRL1000, ctrl1000); 1708 if (err) 1709 return err; 1710 } 1711 1712 bmcr = (BMCR_SPEED1000 | BMCR_FULLDPLX); 1713 1714 err = mii_write(np, np->phy_addr, MII_BMCR, bmcr); 1715 if (err) 1716 return err; 1717 1718 err = mii_read(np, np->phy_addr, MII_BMCR); 1719 if (err < 0) 1720 return err; 1721 bmcr = mii_read(np, np->phy_addr, MII_BMCR); 1722 1723 err = mii_read(np, np->phy_addr, MII_BMSR); 1724 if (err < 0) 1725 return err; 1726 1727 return 0; 1728 } 1729 1730 static int mii_init_common(struct niu *np) 1731 { 1732 struct niu_link_config *lp = &np->link_config; 1733 u16 bmcr, bmsr, adv, estat; 1734 int err; 1735 1736 err = mii_reset(np); 1737 if (err) 1738 return err; 1739 1740 err = mii_read(np, np->phy_addr, MII_BMSR); 1741 if (err < 0) 1742 return err; 1743 bmsr = err; 1744 1745 estat = 0; 1746 if (bmsr & BMSR_ESTATEN) { 1747 err = mii_read(np, np->phy_addr, MII_ESTATUS); 1748 if (err < 0) 1749 return err; 1750 estat = err; 1751 } 1752 1753 bmcr = 0; 1754 err = mii_write(np, np->phy_addr, MII_BMCR, bmcr); 1755 if (err) 1756 return err; 1757 1758 if (lp->loopback_mode == LOOPBACK_MAC) { 1759 bmcr |= BMCR_LOOPBACK; 1760 if (lp->active_speed == SPEED_1000) 1761 bmcr |= BMCR_SPEED1000; 1762 if (lp->active_duplex == DUPLEX_FULL) 1763 bmcr |= BMCR_FULLDPLX; 1764 } 1765 1766 if (lp->loopback_mode == LOOPBACK_PHY) { 1767 u16 aux; 1768 1769 aux = (BCM5464R_AUX_CTL_EXT_LB | 1770 BCM5464R_AUX_CTL_WRITE_1); 1771 err = mii_write(np, np->phy_addr, BCM5464R_AUX_CTL, aux); 1772 if (err) 1773 return err; 1774 } 1775 1776 if (lp->autoneg) { 1777 u16 ctrl1000; 1778 1779 adv = ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP; 1780 if ((bmsr & BMSR_10HALF) && 1781 (lp->advertising & ADVERTISED_10baseT_Half)) 1782 adv |= ADVERTISE_10HALF; 1783 if ((bmsr & BMSR_10FULL) && 1784 (lp->advertising & ADVERTISED_10baseT_Full)) 1785 adv |= ADVERTISE_10FULL; 1786 if ((bmsr & BMSR_100HALF) && 1787 (lp->advertising & ADVERTISED_100baseT_Half)) 1788 adv |= ADVERTISE_100HALF; 1789 if ((bmsr & BMSR_100FULL) && 1790 (lp->advertising & ADVERTISED_100baseT_Full)) 1791 adv |= ADVERTISE_100FULL; 1792 err = mii_write(np, np->phy_addr, MII_ADVERTISE, adv); 1793 if (err) 1794 return err; 1795 1796 if (likely(bmsr & BMSR_ESTATEN)) { 1797 ctrl1000 = 0; 1798 if ((estat & ESTATUS_1000_THALF) && 1799 (lp->advertising & ADVERTISED_1000baseT_Half)) 1800 ctrl1000 |= ADVERTISE_1000HALF; 1801 if ((estat & ESTATUS_1000_TFULL) && 1802 (lp->advertising & ADVERTISED_1000baseT_Full)) 1803 ctrl1000 |= ADVERTISE_1000FULL; 1804 err = mii_write(np, np->phy_addr, 1805 MII_CTRL1000, ctrl1000); 1806 if (err) 1807 return err; 1808 } 1809 1810 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART); 1811 } else { 1812 /* !lp->autoneg */ 1813 int fulldpx; 1814 1815 if (lp->duplex == DUPLEX_FULL) { 1816 bmcr |= BMCR_FULLDPLX; 1817 fulldpx = 1; 1818 } else if (lp->duplex == DUPLEX_HALF) 1819 fulldpx = 0; 1820 else 1821 return -EINVAL; 1822 1823 if (lp->speed == SPEED_1000) { 1824 /* if X-full requested while not supported, or 1825 X-half requested while not supported... */ 1826 if ((fulldpx && !(estat & ESTATUS_1000_TFULL)) || 1827 (!fulldpx && !(estat & ESTATUS_1000_THALF))) 1828 return -EINVAL; 1829 bmcr |= BMCR_SPEED1000; 1830 } else if (lp->speed == SPEED_100) { 1831 if ((fulldpx && !(bmsr & BMSR_100FULL)) || 1832 (!fulldpx && !(bmsr & BMSR_100HALF))) 1833 return -EINVAL; 1834 bmcr |= BMCR_SPEED100; 1835 } else if (lp->speed == SPEED_10) { 1836 if ((fulldpx && !(bmsr & BMSR_10FULL)) || 1837 (!fulldpx && !(bmsr & BMSR_10HALF))) 1838 return -EINVAL; 1839 } else 1840 return -EINVAL; 1841 } 1842 1843 err = mii_write(np, np->phy_addr, MII_BMCR, bmcr); 1844 if (err) 1845 return err; 1846 1847 #if 0 1848 err = mii_read(np, np->phy_addr, MII_BMCR); 1849 if (err < 0) 1850 return err; 1851 bmcr = err; 1852 1853 err = mii_read(np, np->phy_addr, MII_BMSR); 1854 if (err < 0) 1855 return err; 1856 bmsr = err; 1857 1858 pr_info("Port %u after MII init bmcr[%04x] bmsr[%04x]\n", 1859 np->port, bmcr, bmsr); 1860 #endif 1861 1862 return 0; 1863 } 1864 1865 static int xcvr_init_1g(struct niu *np) 1866 { 1867 u64 val; 1868 1869 /* XXX shared resource, lock parent XXX */ 1870 val = nr64(MIF_CONFIG); 1871 val &= ~MIF_CONFIG_INDIRECT_MODE; 1872 nw64(MIF_CONFIG, val); 1873 1874 return mii_init_common(np); 1875 } 1876 1877 static int niu_xcvr_init(struct niu *np) 1878 { 1879 const struct niu_phy_ops *ops = np->phy_ops; 1880 int err; 1881 1882 err = 0; 1883 if (ops->xcvr_init) 1884 err = ops->xcvr_init(np); 1885 1886 return err; 1887 } 1888 1889 static int niu_serdes_init(struct niu *np) 1890 { 1891 const struct niu_phy_ops *ops = np->phy_ops; 1892 int err; 1893 1894 err = 0; 1895 if (ops->serdes_init) 1896 err = ops->serdes_init(np); 1897 1898 return err; 1899 } 1900 1901 static void niu_init_xif(struct niu *); 1902 static void niu_handle_led(struct niu *, int status); 1903 1904 static int niu_link_status_common(struct niu *np, int link_up) 1905 { 1906 struct niu_link_config *lp = &np->link_config; 1907 struct net_device *dev = np->dev; 1908 unsigned long flags; 1909 1910 if (!netif_carrier_ok(dev) && link_up) { 1911 netif_info(np, link, dev, "Link is up at %s, %s duplex\n", 1912 lp->active_speed == SPEED_10000 ? "10Gb/sec" : 1913 lp->active_speed == SPEED_1000 ? "1Gb/sec" : 1914 lp->active_speed == SPEED_100 ? "100Mbit/sec" : 1915 "10Mbit/sec", 1916 lp->active_duplex == DUPLEX_FULL ? "full" : "half"); 1917 1918 spin_lock_irqsave(&np->lock, flags); 1919 niu_init_xif(np); 1920 niu_handle_led(np, 1); 1921 spin_unlock_irqrestore(&np->lock, flags); 1922 1923 netif_carrier_on(dev); 1924 } else if (netif_carrier_ok(dev) && !link_up) { 1925 netif_warn(np, link, dev, "Link is down\n"); 1926 spin_lock_irqsave(&np->lock, flags); 1927 niu_handle_led(np, 0); 1928 spin_unlock_irqrestore(&np->lock, flags); 1929 netif_carrier_off(dev); 1930 } 1931 1932 return 0; 1933 } 1934 1935 static int link_status_10g_mrvl(struct niu *np, int *link_up_p) 1936 { 1937 int err, link_up, pma_status, pcs_status; 1938 1939 link_up = 0; 1940 1941 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR, 1942 MRVL88X2011_10G_PMD_STATUS_2); 1943 if (err < 0) 1944 goto out; 1945 1946 /* Check PMA/PMD Register: 1.0001.2 == 1 */ 1947 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR, 1948 MRVL88X2011_PMA_PMD_STATUS_1); 1949 if (err < 0) 1950 goto out; 1951 1952 pma_status = ((err & MRVL88X2011_LNK_STATUS_OK) ? 1 : 0); 1953 1954 /* Check PMC Register : 3.0001.2 == 1: read twice */ 1955 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV3_ADDR, 1956 MRVL88X2011_PMA_PMD_STATUS_1); 1957 if (err < 0) 1958 goto out; 1959 1960 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV3_ADDR, 1961 MRVL88X2011_PMA_PMD_STATUS_1); 1962 if (err < 0) 1963 goto out; 1964 1965 pcs_status = ((err & MRVL88X2011_LNK_STATUS_OK) ? 1 : 0); 1966 1967 /* Check XGXS Register : 4.0018.[0-3,12] */ 1968 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV4_ADDR, 1969 MRVL88X2011_10G_XGXS_LANE_STAT); 1970 if (err < 0) 1971 goto out; 1972 1973 if (err == (PHYXS_XGXS_LANE_STAT_ALINGED | PHYXS_XGXS_LANE_STAT_LANE3 | 1974 PHYXS_XGXS_LANE_STAT_LANE2 | PHYXS_XGXS_LANE_STAT_LANE1 | 1975 PHYXS_XGXS_LANE_STAT_LANE0 | PHYXS_XGXS_LANE_STAT_MAGIC | 1976 0x800)) 1977 link_up = (pma_status && pcs_status) ? 1 : 0; 1978 1979 np->link_config.active_speed = SPEED_10000; 1980 np->link_config.active_duplex = DUPLEX_FULL; 1981 err = 0; 1982 out: 1983 mrvl88x2011_act_led(np, (link_up ? 1984 MRVL88X2011_LED_CTL_PCS_ACT : 1985 MRVL88X2011_LED_CTL_OFF)); 1986 1987 *link_up_p = link_up; 1988 return err; 1989 } 1990 1991 static int link_status_10g_bcm8706(struct niu *np, int *link_up_p) 1992 { 1993 int err, link_up; 1994 link_up = 0; 1995 1996 err = mdio_read(np, np->phy_addr, BCM8704_PMA_PMD_DEV_ADDR, 1997 BCM8704_PMD_RCV_SIGDET); 1998 if (err < 0 || err == 0xffff) 1999 goto out; 2000 if (!(err & PMD_RCV_SIGDET_GLOBAL)) { 2001 err = 0; 2002 goto out; 2003 } 2004 2005 err = mdio_read(np, np->phy_addr, BCM8704_PCS_DEV_ADDR, 2006 BCM8704_PCS_10G_R_STATUS); 2007 if (err < 0) 2008 goto out; 2009 2010 if (!(err & PCS_10G_R_STATUS_BLK_LOCK)) { 2011 err = 0; 2012 goto out; 2013 } 2014 2015 err = mdio_read(np, np->phy_addr, BCM8704_PHYXS_DEV_ADDR, 2016 BCM8704_PHYXS_XGXS_LANE_STAT); 2017 if (err < 0) 2018 goto out; 2019 if (err != (PHYXS_XGXS_LANE_STAT_ALINGED | 2020 PHYXS_XGXS_LANE_STAT_MAGIC | 2021 PHYXS_XGXS_LANE_STAT_PATTEST | 2022 PHYXS_XGXS_LANE_STAT_LANE3 | 2023 PHYXS_XGXS_LANE_STAT_LANE2 | 2024 PHYXS_XGXS_LANE_STAT_LANE1 | 2025 PHYXS_XGXS_LANE_STAT_LANE0)) { 2026 err = 0; 2027 np->link_config.active_speed = SPEED_INVALID; 2028 np->link_config.active_duplex = DUPLEX_INVALID; 2029 goto out; 2030 } 2031 2032 link_up = 1; 2033 np->link_config.active_speed = SPEED_10000; 2034 np->link_config.active_duplex = DUPLEX_FULL; 2035 err = 0; 2036 2037 out: 2038 *link_up_p = link_up; 2039 return err; 2040 } 2041 2042 static int link_status_10g_bcom(struct niu *np, int *link_up_p) 2043 { 2044 int err, link_up; 2045 2046 link_up = 0; 2047 2048 err = mdio_read(np, np->phy_addr, BCM8704_PMA_PMD_DEV_ADDR, 2049 BCM8704_PMD_RCV_SIGDET); 2050 if (err < 0) 2051 goto out; 2052 if (!(err & PMD_RCV_SIGDET_GLOBAL)) { 2053 err = 0; 2054 goto out; 2055 } 2056 2057 err = mdio_read(np, np->phy_addr, BCM8704_PCS_DEV_ADDR, 2058 BCM8704_PCS_10G_R_STATUS); 2059 if (err < 0) 2060 goto out; 2061 if (!(err & PCS_10G_R_STATUS_BLK_LOCK)) { 2062 err = 0; 2063 goto out; 2064 } 2065 2066 err = mdio_read(np, np->phy_addr, BCM8704_PHYXS_DEV_ADDR, 2067 BCM8704_PHYXS_XGXS_LANE_STAT); 2068 if (err < 0) 2069 goto out; 2070 2071 if (err != (PHYXS_XGXS_LANE_STAT_ALINGED | 2072 PHYXS_XGXS_LANE_STAT_MAGIC | 2073 PHYXS_XGXS_LANE_STAT_LANE3 | 2074 PHYXS_XGXS_LANE_STAT_LANE2 | 2075 PHYXS_XGXS_LANE_STAT_LANE1 | 2076 PHYXS_XGXS_LANE_STAT_LANE0)) { 2077 err = 0; 2078 goto out; 2079 } 2080 2081 link_up = 1; 2082 np->link_config.active_speed = SPEED_10000; 2083 np->link_config.active_duplex = DUPLEX_FULL; 2084 err = 0; 2085 2086 out: 2087 *link_up_p = link_up; 2088 return err; 2089 } 2090 2091 static int link_status_10g(struct niu *np, int *link_up_p) 2092 { 2093 unsigned long flags; 2094 int err = -EINVAL; 2095 2096 spin_lock_irqsave(&np->lock, flags); 2097 2098 if (np->link_config.loopback_mode == LOOPBACK_DISABLED) { 2099 int phy_id; 2100 2101 phy_id = phy_decode(np->parent->port_phy, np->port); 2102 phy_id = np->parent->phy_probe_info.phy_id[phy_id][np->port]; 2103 2104 /* handle different phy types */ 2105 switch (phy_id & NIU_PHY_ID_MASK) { 2106 case NIU_PHY_ID_MRVL88X2011: 2107 err = link_status_10g_mrvl(np, link_up_p); 2108 break; 2109 2110 default: /* bcom 8704 */ 2111 err = link_status_10g_bcom(np, link_up_p); 2112 break; 2113 } 2114 } 2115 2116 spin_unlock_irqrestore(&np->lock, flags); 2117 2118 return err; 2119 } 2120 2121 static int niu_10g_phy_present(struct niu *np) 2122 { 2123 u64 sig, mask, val; 2124 2125 sig = nr64(ESR_INT_SIGNALS); 2126 switch (np->port) { 2127 case 0: 2128 mask = ESR_INT_SIGNALS_P0_BITS; 2129 val = (ESR_INT_SRDY0_P0 | 2130 ESR_INT_DET0_P0 | 2131 ESR_INT_XSRDY_P0 | 2132 ESR_INT_XDP_P0_CH3 | 2133 ESR_INT_XDP_P0_CH2 | 2134 ESR_INT_XDP_P0_CH1 | 2135 ESR_INT_XDP_P0_CH0); 2136 break; 2137 2138 case 1: 2139 mask = ESR_INT_SIGNALS_P1_BITS; 2140 val = (ESR_INT_SRDY0_P1 | 2141 ESR_INT_DET0_P1 | 2142 ESR_INT_XSRDY_P1 | 2143 ESR_INT_XDP_P1_CH3 | 2144 ESR_INT_XDP_P1_CH2 | 2145 ESR_INT_XDP_P1_CH1 | 2146 ESR_INT_XDP_P1_CH0); 2147 break; 2148 2149 default: 2150 return 0; 2151 } 2152 2153 if ((sig & mask) != val) 2154 return 0; 2155 return 1; 2156 } 2157 2158 static int link_status_10g_hotplug(struct niu *np, int *link_up_p) 2159 { 2160 unsigned long flags; 2161 int err = 0; 2162 int phy_present; 2163 int phy_present_prev; 2164 2165 spin_lock_irqsave(&np->lock, flags); 2166 2167 if (np->link_config.loopback_mode == LOOPBACK_DISABLED) { 2168 phy_present_prev = (np->flags & NIU_FLAGS_HOTPLUG_PHY_PRESENT) ? 2169 1 : 0; 2170 phy_present = niu_10g_phy_present(np); 2171 if (phy_present != phy_present_prev) { 2172 /* state change */ 2173 if (phy_present) { 2174 /* A NEM was just plugged in */ 2175 np->flags |= NIU_FLAGS_HOTPLUG_PHY_PRESENT; 2176 if (np->phy_ops->xcvr_init) 2177 err = np->phy_ops->xcvr_init(np); 2178 if (err) { 2179 err = mdio_read(np, np->phy_addr, 2180 BCM8704_PHYXS_DEV_ADDR, MII_BMCR); 2181 if (err == 0xffff) { 2182 /* No mdio, back-to-back XAUI */ 2183 goto out; 2184 } 2185 /* debounce */ 2186 np->flags &= ~NIU_FLAGS_HOTPLUG_PHY_PRESENT; 2187 } 2188 } else { 2189 np->flags &= ~NIU_FLAGS_HOTPLUG_PHY_PRESENT; 2190 *link_up_p = 0; 2191 netif_warn(np, link, np->dev, 2192 "Hotplug PHY Removed\n"); 2193 } 2194 } 2195 out: 2196 if (np->flags & NIU_FLAGS_HOTPLUG_PHY_PRESENT) { 2197 err = link_status_10g_bcm8706(np, link_up_p); 2198 if (err == 0xffff) { 2199 /* No mdio, back-to-back XAUI: it is C10NEM */ 2200 *link_up_p = 1; 2201 np->link_config.active_speed = SPEED_10000; 2202 np->link_config.active_duplex = DUPLEX_FULL; 2203 } 2204 } 2205 } 2206 2207 spin_unlock_irqrestore(&np->lock, flags); 2208 2209 return 0; 2210 } 2211 2212 static int niu_link_status(struct niu *np, int *link_up_p) 2213 { 2214 const struct niu_phy_ops *ops = np->phy_ops; 2215 int err; 2216 2217 err = 0; 2218 if (ops->link_status) 2219 err = ops->link_status(np, link_up_p); 2220 2221 return err; 2222 } 2223 2224 static void niu_timer(unsigned long __opaque) 2225 { 2226 struct niu *np = (struct niu *) __opaque; 2227 unsigned long off; 2228 int err, link_up; 2229 2230 err = niu_link_status(np, &link_up); 2231 if (!err) 2232 niu_link_status_common(np, link_up); 2233 2234 if (netif_carrier_ok(np->dev)) 2235 off = 5 * HZ; 2236 else 2237 off = 1 * HZ; 2238 np->timer.expires = jiffies + off; 2239 2240 add_timer(&np->timer); 2241 } 2242 2243 static const struct niu_phy_ops phy_ops_10g_serdes = { 2244 .serdes_init = serdes_init_10g_serdes, 2245 .link_status = link_status_10g_serdes, 2246 }; 2247 2248 static const struct niu_phy_ops phy_ops_10g_serdes_niu = { 2249 .serdes_init = serdes_init_niu_10g_serdes, 2250 .link_status = link_status_10g_serdes, 2251 }; 2252 2253 static const struct niu_phy_ops phy_ops_1g_serdes_niu = { 2254 .serdes_init = serdes_init_niu_1g_serdes, 2255 .link_status = link_status_1g_serdes, 2256 }; 2257 2258 static const struct niu_phy_ops phy_ops_1g_rgmii = { 2259 .xcvr_init = xcvr_init_1g_rgmii, 2260 .link_status = link_status_1g_rgmii, 2261 }; 2262 2263 static const struct niu_phy_ops phy_ops_10g_fiber_niu = { 2264 .serdes_init = serdes_init_niu_10g_fiber, 2265 .xcvr_init = xcvr_init_10g, 2266 .link_status = link_status_10g, 2267 }; 2268 2269 static const struct niu_phy_ops phy_ops_10g_fiber = { 2270 .serdes_init = serdes_init_10g, 2271 .xcvr_init = xcvr_init_10g, 2272 .link_status = link_status_10g, 2273 }; 2274 2275 static const struct niu_phy_ops phy_ops_10g_fiber_hotplug = { 2276 .serdes_init = serdes_init_10g, 2277 .xcvr_init = xcvr_init_10g_bcm8706, 2278 .link_status = link_status_10g_hotplug, 2279 }; 2280 2281 static const struct niu_phy_ops phy_ops_niu_10g_hotplug = { 2282 .serdes_init = serdes_init_niu_10g_fiber, 2283 .xcvr_init = xcvr_init_10g_bcm8706, 2284 .link_status = link_status_10g_hotplug, 2285 }; 2286 2287 static const struct niu_phy_ops phy_ops_10g_copper = { 2288 .serdes_init = serdes_init_10g, 2289 .link_status = link_status_10g, /* XXX */ 2290 }; 2291 2292 static const struct niu_phy_ops phy_ops_1g_fiber = { 2293 .serdes_init = serdes_init_1g, 2294 .xcvr_init = xcvr_init_1g, 2295 .link_status = link_status_1g, 2296 }; 2297 2298 static const struct niu_phy_ops phy_ops_1g_copper = { 2299 .xcvr_init = xcvr_init_1g, 2300 .link_status = link_status_1g, 2301 }; 2302 2303 struct niu_phy_template { 2304 const struct niu_phy_ops *ops; 2305 u32 phy_addr_base; 2306 }; 2307 2308 static const struct niu_phy_template phy_template_niu_10g_fiber = { 2309 .ops = &phy_ops_10g_fiber_niu, 2310 .phy_addr_base = 16, 2311 }; 2312 2313 static const struct niu_phy_template phy_template_niu_10g_serdes = { 2314 .ops = &phy_ops_10g_serdes_niu, 2315 .phy_addr_base = 0, 2316 }; 2317 2318 static const struct niu_phy_template phy_template_niu_1g_serdes = { 2319 .ops = &phy_ops_1g_serdes_niu, 2320 .phy_addr_base = 0, 2321 }; 2322 2323 static const struct niu_phy_template phy_template_10g_fiber = { 2324 .ops = &phy_ops_10g_fiber, 2325 .phy_addr_base = 8, 2326 }; 2327 2328 static const struct niu_phy_template phy_template_10g_fiber_hotplug = { 2329 .ops = &phy_ops_10g_fiber_hotplug, 2330 .phy_addr_base = 8, 2331 }; 2332 2333 static const struct niu_phy_template phy_template_niu_10g_hotplug = { 2334 .ops = &phy_ops_niu_10g_hotplug, 2335 .phy_addr_base = 8, 2336 }; 2337 2338 static const struct niu_phy_template phy_template_10g_copper = { 2339 .ops = &phy_ops_10g_copper, 2340 .phy_addr_base = 10, 2341 }; 2342 2343 static const struct niu_phy_template phy_template_1g_fiber = { 2344 .ops = &phy_ops_1g_fiber, 2345 .phy_addr_base = 0, 2346 }; 2347 2348 static const struct niu_phy_template phy_template_1g_copper = { 2349 .ops = &phy_ops_1g_copper, 2350 .phy_addr_base = 0, 2351 }; 2352 2353 static const struct niu_phy_template phy_template_1g_rgmii = { 2354 .ops = &phy_ops_1g_rgmii, 2355 .phy_addr_base = 0, 2356 }; 2357 2358 static const struct niu_phy_template phy_template_10g_serdes = { 2359 .ops = &phy_ops_10g_serdes, 2360 .phy_addr_base = 0, 2361 }; 2362 2363 static int niu_atca_port_num[4] = { 2364 0, 0, 11, 10 2365 }; 2366 2367 static int serdes_init_10g_serdes(struct niu *np) 2368 { 2369 struct niu_link_config *lp = &np->link_config; 2370 unsigned long ctrl_reg, test_cfg_reg, pll_cfg, i; 2371 u64 ctrl_val, test_cfg_val, sig, mask, val; 2372 2373 switch (np->port) { 2374 case 0: 2375 ctrl_reg = ENET_SERDES_0_CTRL_CFG; 2376 test_cfg_reg = ENET_SERDES_0_TEST_CFG; 2377 pll_cfg = ENET_SERDES_0_PLL_CFG; 2378 break; 2379 case 1: 2380 ctrl_reg = ENET_SERDES_1_CTRL_CFG; 2381 test_cfg_reg = ENET_SERDES_1_TEST_CFG; 2382 pll_cfg = ENET_SERDES_1_PLL_CFG; 2383 break; 2384 2385 default: 2386 return -EINVAL; 2387 } 2388 ctrl_val = (ENET_SERDES_CTRL_SDET_0 | 2389 ENET_SERDES_CTRL_SDET_1 | 2390 ENET_SERDES_CTRL_SDET_2 | 2391 ENET_SERDES_CTRL_SDET_3 | 2392 (0x5 << ENET_SERDES_CTRL_EMPH_0_SHIFT) | 2393 (0x5 << ENET_SERDES_CTRL_EMPH_1_SHIFT) | 2394 (0x5 << ENET_SERDES_CTRL_EMPH_2_SHIFT) | 2395 (0x5 << ENET_SERDES_CTRL_EMPH_3_SHIFT) | 2396 (0x1 << ENET_SERDES_CTRL_LADJ_0_SHIFT) | 2397 (0x1 << ENET_SERDES_CTRL_LADJ_1_SHIFT) | 2398 (0x1 << ENET_SERDES_CTRL_LADJ_2_SHIFT) | 2399 (0x1 << ENET_SERDES_CTRL_LADJ_3_SHIFT)); 2400 test_cfg_val = 0; 2401 2402 if (lp->loopback_mode == LOOPBACK_PHY) { 2403 test_cfg_val |= ((ENET_TEST_MD_PAD_LOOPBACK << 2404 ENET_SERDES_TEST_MD_0_SHIFT) | 2405 (ENET_TEST_MD_PAD_LOOPBACK << 2406 ENET_SERDES_TEST_MD_1_SHIFT) | 2407 (ENET_TEST_MD_PAD_LOOPBACK << 2408 ENET_SERDES_TEST_MD_2_SHIFT) | 2409 (ENET_TEST_MD_PAD_LOOPBACK << 2410 ENET_SERDES_TEST_MD_3_SHIFT)); 2411 } 2412 2413 esr_reset(np); 2414 nw64(pll_cfg, ENET_SERDES_PLL_FBDIV2); 2415 nw64(ctrl_reg, ctrl_val); 2416 nw64(test_cfg_reg, test_cfg_val); 2417 2418 /* Initialize all 4 lanes of the SERDES. */ 2419 for (i = 0; i < 4; i++) { 2420 u32 rxtx_ctrl, glue0; 2421 int err; 2422 2423 err = esr_read_rxtx_ctrl(np, i, &rxtx_ctrl); 2424 if (err) 2425 return err; 2426 err = esr_read_glue0(np, i, &glue0); 2427 if (err) 2428 return err; 2429 2430 rxtx_ctrl &= ~(ESR_RXTX_CTRL_VMUXLO); 2431 rxtx_ctrl |= (ESR_RXTX_CTRL_ENSTRETCH | 2432 (2 << ESR_RXTX_CTRL_VMUXLO_SHIFT)); 2433 2434 glue0 &= ~(ESR_GLUE_CTRL0_SRATE | 2435 ESR_GLUE_CTRL0_THCNT | 2436 ESR_GLUE_CTRL0_BLTIME); 2437 glue0 |= (ESR_GLUE_CTRL0_RXLOSENAB | 2438 (0xf << ESR_GLUE_CTRL0_SRATE_SHIFT) | 2439 (0xff << ESR_GLUE_CTRL0_THCNT_SHIFT) | 2440 (BLTIME_300_CYCLES << 2441 ESR_GLUE_CTRL0_BLTIME_SHIFT)); 2442 2443 err = esr_write_rxtx_ctrl(np, i, rxtx_ctrl); 2444 if (err) 2445 return err; 2446 err = esr_write_glue0(np, i, glue0); 2447 if (err) 2448 return err; 2449 } 2450 2451 2452 sig = nr64(ESR_INT_SIGNALS); 2453 switch (np->port) { 2454 case 0: 2455 mask = ESR_INT_SIGNALS_P0_BITS; 2456 val = (ESR_INT_SRDY0_P0 | 2457 ESR_INT_DET0_P0 | 2458 ESR_INT_XSRDY_P0 | 2459 ESR_INT_XDP_P0_CH3 | 2460 ESR_INT_XDP_P0_CH2 | 2461 ESR_INT_XDP_P0_CH1 | 2462 ESR_INT_XDP_P0_CH0); 2463 break; 2464 2465 case 1: 2466 mask = ESR_INT_SIGNALS_P1_BITS; 2467 val = (ESR_INT_SRDY0_P1 | 2468 ESR_INT_DET0_P1 | 2469 ESR_INT_XSRDY_P1 | 2470 ESR_INT_XDP_P1_CH3 | 2471 ESR_INT_XDP_P1_CH2 | 2472 ESR_INT_XDP_P1_CH1 | 2473 ESR_INT_XDP_P1_CH0); 2474 break; 2475 2476 default: 2477 return -EINVAL; 2478 } 2479 2480 if ((sig & mask) != val) { 2481 int err; 2482 err = serdes_init_1g_serdes(np); 2483 if (!err) { 2484 np->flags &= ~NIU_FLAGS_10G; 2485 np->mac_xcvr = MAC_XCVR_PCS; 2486 } else { 2487 netdev_err(np->dev, "Port %u 10G/1G SERDES Link Failed\n", 2488 np->port); 2489 return -ENODEV; 2490 } 2491 } 2492 2493 return 0; 2494 } 2495 2496 static int niu_determine_phy_disposition(struct niu *np) 2497 { 2498 struct niu_parent *parent = np->parent; 2499 u8 plat_type = parent->plat_type; 2500 const struct niu_phy_template *tp; 2501 u32 phy_addr_off = 0; 2502 2503 if (plat_type == PLAT_TYPE_NIU) { 2504 switch (np->flags & 2505 (NIU_FLAGS_10G | 2506 NIU_FLAGS_FIBER | 2507 NIU_FLAGS_XCVR_SERDES)) { 2508 case NIU_FLAGS_10G | NIU_FLAGS_XCVR_SERDES: 2509 /* 10G Serdes */ 2510 tp = &phy_template_niu_10g_serdes; 2511 break; 2512 case NIU_FLAGS_XCVR_SERDES: 2513 /* 1G Serdes */ 2514 tp = &phy_template_niu_1g_serdes; 2515 break; 2516 case NIU_FLAGS_10G | NIU_FLAGS_FIBER: 2517 /* 10G Fiber */ 2518 default: 2519 if (np->flags & NIU_FLAGS_HOTPLUG_PHY) { 2520 tp = &phy_template_niu_10g_hotplug; 2521 if (np->port == 0) 2522 phy_addr_off = 8; 2523 if (np->port == 1) 2524 phy_addr_off = 12; 2525 } else { 2526 tp = &phy_template_niu_10g_fiber; 2527 phy_addr_off += np->port; 2528 } 2529 break; 2530 } 2531 } else { 2532 switch (np->flags & 2533 (NIU_FLAGS_10G | 2534 NIU_FLAGS_FIBER | 2535 NIU_FLAGS_XCVR_SERDES)) { 2536 case 0: 2537 /* 1G copper */ 2538 tp = &phy_template_1g_copper; 2539 if (plat_type == PLAT_TYPE_VF_P0) 2540 phy_addr_off = 10; 2541 else if (plat_type == PLAT_TYPE_VF_P1) 2542 phy_addr_off = 26; 2543 2544 phy_addr_off += (np->port ^ 0x3); 2545 break; 2546 2547 case NIU_FLAGS_10G: 2548 /* 10G copper */ 2549 tp = &phy_template_10g_copper; 2550 break; 2551 2552 case NIU_FLAGS_FIBER: 2553 /* 1G fiber */ 2554 tp = &phy_template_1g_fiber; 2555 break; 2556 2557 case NIU_FLAGS_10G | NIU_FLAGS_FIBER: 2558 /* 10G fiber */ 2559 tp = &phy_template_10g_fiber; 2560 if (plat_type == PLAT_TYPE_VF_P0 || 2561 plat_type == PLAT_TYPE_VF_P1) 2562 phy_addr_off = 8; 2563 phy_addr_off += np->port; 2564 if (np->flags & NIU_FLAGS_HOTPLUG_PHY) { 2565 tp = &phy_template_10g_fiber_hotplug; 2566 if (np->port == 0) 2567 phy_addr_off = 8; 2568 if (np->port == 1) 2569 phy_addr_off = 12; 2570 } 2571 break; 2572 2573 case NIU_FLAGS_10G | NIU_FLAGS_XCVR_SERDES: 2574 case NIU_FLAGS_XCVR_SERDES | NIU_FLAGS_FIBER: 2575 case NIU_FLAGS_XCVR_SERDES: 2576 switch(np->port) { 2577 case 0: 2578 case 1: 2579 tp = &phy_template_10g_serdes; 2580 break; 2581 case 2: 2582 case 3: 2583 tp = &phy_template_1g_rgmii; 2584 break; 2585 default: 2586 return -EINVAL; 2587 } 2588 phy_addr_off = niu_atca_port_num[np->port]; 2589 break; 2590 2591 default: 2592 return -EINVAL; 2593 } 2594 } 2595 2596 np->phy_ops = tp->ops; 2597 np->phy_addr = tp->phy_addr_base + phy_addr_off; 2598 2599 return 0; 2600 } 2601 2602 static int niu_init_link(struct niu *np) 2603 { 2604 struct niu_parent *parent = np->parent; 2605 int err, ignore; 2606 2607 if (parent->plat_type == PLAT_TYPE_NIU) { 2608 err = niu_xcvr_init(np); 2609 if (err) 2610 return err; 2611 msleep(200); 2612 } 2613 err = niu_serdes_init(np); 2614 if (err && !(np->flags & NIU_FLAGS_HOTPLUG_PHY)) 2615 return err; 2616 msleep(200); 2617 err = niu_xcvr_init(np); 2618 if (!err || (np->flags & NIU_FLAGS_HOTPLUG_PHY)) 2619 niu_link_status(np, &ignore); 2620 return 0; 2621 } 2622 2623 static void niu_set_primary_mac(struct niu *np, unsigned char *addr) 2624 { 2625 u16 reg0 = addr[4] << 8 | addr[5]; 2626 u16 reg1 = addr[2] << 8 | addr[3]; 2627 u16 reg2 = addr[0] << 8 | addr[1]; 2628 2629 if (np->flags & NIU_FLAGS_XMAC) { 2630 nw64_mac(XMAC_ADDR0, reg0); 2631 nw64_mac(XMAC_ADDR1, reg1); 2632 nw64_mac(XMAC_ADDR2, reg2); 2633 } else { 2634 nw64_mac(BMAC_ADDR0, reg0); 2635 nw64_mac(BMAC_ADDR1, reg1); 2636 nw64_mac(BMAC_ADDR2, reg2); 2637 } 2638 } 2639 2640 static int niu_num_alt_addr(struct niu *np) 2641 { 2642 if (np->flags & NIU_FLAGS_XMAC) 2643 return XMAC_NUM_ALT_ADDR; 2644 else 2645 return BMAC_NUM_ALT_ADDR; 2646 } 2647 2648 static int niu_set_alt_mac(struct niu *np, int index, unsigned char *addr) 2649 { 2650 u16 reg0 = addr[4] << 8 | addr[5]; 2651 u16 reg1 = addr[2] << 8 | addr[3]; 2652 u16 reg2 = addr[0] << 8 | addr[1]; 2653 2654 if (index >= niu_num_alt_addr(np)) 2655 return -EINVAL; 2656 2657 if (np->flags & NIU_FLAGS_XMAC) { 2658 nw64_mac(XMAC_ALT_ADDR0(index), reg0); 2659 nw64_mac(XMAC_ALT_ADDR1(index), reg1); 2660 nw64_mac(XMAC_ALT_ADDR2(index), reg2); 2661 } else { 2662 nw64_mac(BMAC_ALT_ADDR0(index), reg0); 2663 nw64_mac(BMAC_ALT_ADDR1(index), reg1); 2664 nw64_mac(BMAC_ALT_ADDR2(index), reg2); 2665 } 2666 2667 return 0; 2668 } 2669 2670 static int niu_enable_alt_mac(struct niu *np, int index, int on) 2671 { 2672 unsigned long reg; 2673 u64 val, mask; 2674 2675 if (index >= niu_num_alt_addr(np)) 2676 return -EINVAL; 2677 2678 if (np->flags & NIU_FLAGS_XMAC) { 2679 reg = XMAC_ADDR_CMPEN; 2680 mask = 1 << index; 2681 } else { 2682 reg = BMAC_ADDR_CMPEN; 2683 mask = 1 << (index + 1); 2684 } 2685 2686 val = nr64_mac(reg); 2687 if (on) 2688 val |= mask; 2689 else 2690 val &= ~mask; 2691 nw64_mac(reg, val); 2692 2693 return 0; 2694 } 2695 2696 static void __set_rdc_table_num_hw(struct niu *np, unsigned long reg, 2697 int num, int mac_pref) 2698 { 2699 u64 val = nr64_mac(reg); 2700 val &= ~(HOST_INFO_MACRDCTBLN | HOST_INFO_MPR); 2701 val |= num; 2702 if (mac_pref) 2703 val |= HOST_INFO_MPR; 2704 nw64_mac(reg, val); 2705 } 2706 2707 static int __set_rdc_table_num(struct niu *np, 2708 int xmac_index, int bmac_index, 2709 int rdc_table_num, int mac_pref) 2710 { 2711 unsigned long reg; 2712 2713 if (rdc_table_num & ~HOST_INFO_MACRDCTBLN) 2714 return -EINVAL; 2715 if (np->flags & NIU_FLAGS_XMAC) 2716 reg = XMAC_HOST_INFO(xmac_index); 2717 else 2718 reg = BMAC_HOST_INFO(bmac_index); 2719 __set_rdc_table_num_hw(np, reg, rdc_table_num, mac_pref); 2720 return 0; 2721 } 2722 2723 static int niu_set_primary_mac_rdc_table(struct niu *np, int table_num, 2724 int mac_pref) 2725 { 2726 return __set_rdc_table_num(np, 17, 0, table_num, mac_pref); 2727 } 2728 2729 static int niu_set_multicast_mac_rdc_table(struct niu *np, int table_num, 2730 int mac_pref) 2731 { 2732 return __set_rdc_table_num(np, 16, 8, table_num, mac_pref); 2733 } 2734 2735 static int niu_set_alt_mac_rdc_table(struct niu *np, int idx, 2736 int table_num, int mac_pref) 2737 { 2738 if (idx >= niu_num_alt_addr(np)) 2739 return -EINVAL; 2740 return __set_rdc_table_num(np, idx, idx + 1, table_num, mac_pref); 2741 } 2742 2743 static u64 vlan_entry_set_parity(u64 reg_val) 2744 { 2745 u64 port01_mask; 2746 u64 port23_mask; 2747 2748 port01_mask = 0x00ff; 2749 port23_mask = 0xff00; 2750 2751 if (hweight64(reg_val & port01_mask) & 1) 2752 reg_val |= ENET_VLAN_TBL_PARITY0; 2753 else 2754 reg_val &= ~ENET_VLAN_TBL_PARITY0; 2755 2756 if (hweight64(reg_val & port23_mask) & 1) 2757 reg_val |= ENET_VLAN_TBL_PARITY1; 2758 else 2759 reg_val &= ~ENET_VLAN_TBL_PARITY1; 2760 2761 return reg_val; 2762 } 2763 2764 static void vlan_tbl_write(struct niu *np, unsigned long index, 2765 int port, int vpr, int rdc_table) 2766 { 2767 u64 reg_val = nr64(ENET_VLAN_TBL(index)); 2768 2769 reg_val &= ~((ENET_VLAN_TBL_VPR | 2770 ENET_VLAN_TBL_VLANRDCTBLN) << 2771 ENET_VLAN_TBL_SHIFT(port)); 2772 if (vpr) 2773 reg_val |= (ENET_VLAN_TBL_VPR << 2774 ENET_VLAN_TBL_SHIFT(port)); 2775 reg_val |= (rdc_table << ENET_VLAN_TBL_SHIFT(port)); 2776 2777 reg_val = vlan_entry_set_parity(reg_val); 2778 2779 nw64(ENET_VLAN_TBL(index), reg_val); 2780 } 2781 2782 static void vlan_tbl_clear(struct niu *np) 2783 { 2784 int i; 2785 2786 for (i = 0; i < ENET_VLAN_TBL_NUM_ENTRIES; i++) 2787 nw64(ENET_VLAN_TBL(i), 0); 2788 } 2789 2790 static int tcam_wait_bit(struct niu *np, u64 bit) 2791 { 2792 int limit = 1000; 2793 2794 while (--limit > 0) { 2795 if (nr64(TCAM_CTL) & bit) 2796 break; 2797 udelay(1); 2798 } 2799 if (limit <= 0) 2800 return -ENODEV; 2801 2802 return 0; 2803 } 2804 2805 static int tcam_flush(struct niu *np, int index) 2806 { 2807 nw64(TCAM_KEY_0, 0x00); 2808 nw64(TCAM_KEY_MASK_0, 0xff); 2809 nw64(TCAM_CTL, (TCAM_CTL_RWC_TCAM_WRITE | index)); 2810 2811 return tcam_wait_bit(np, TCAM_CTL_STAT); 2812 } 2813 2814 #if 0 2815 static int tcam_read(struct niu *np, int index, 2816 u64 *key, u64 *mask) 2817 { 2818 int err; 2819 2820 nw64(TCAM_CTL, (TCAM_CTL_RWC_TCAM_READ | index)); 2821 err = tcam_wait_bit(np, TCAM_CTL_STAT); 2822 if (!err) { 2823 key[0] = nr64(TCAM_KEY_0); 2824 key[1] = nr64(TCAM_KEY_1); 2825 key[2] = nr64(TCAM_KEY_2); 2826 key[3] = nr64(TCAM_KEY_3); 2827 mask[0] = nr64(TCAM_KEY_MASK_0); 2828 mask[1] = nr64(TCAM_KEY_MASK_1); 2829 mask[2] = nr64(TCAM_KEY_MASK_2); 2830 mask[3] = nr64(TCAM_KEY_MASK_3); 2831 } 2832 return err; 2833 } 2834 #endif 2835 2836 static int tcam_write(struct niu *np, int index, 2837 u64 *key, u64 *mask) 2838 { 2839 nw64(TCAM_KEY_0, key[0]); 2840 nw64(TCAM_KEY_1, key[1]); 2841 nw64(TCAM_KEY_2, key[2]); 2842 nw64(TCAM_KEY_3, key[3]); 2843 nw64(TCAM_KEY_MASK_0, mask[0]); 2844 nw64(TCAM_KEY_MASK_1, mask[1]); 2845 nw64(TCAM_KEY_MASK_2, mask[2]); 2846 nw64(TCAM_KEY_MASK_3, mask[3]); 2847 nw64(TCAM_CTL, (TCAM_CTL_RWC_TCAM_WRITE | index)); 2848 2849 return tcam_wait_bit(np, TCAM_CTL_STAT); 2850 } 2851 2852 #if 0 2853 static int tcam_assoc_read(struct niu *np, int index, u64 *data) 2854 { 2855 int err; 2856 2857 nw64(TCAM_CTL, (TCAM_CTL_RWC_RAM_READ | index)); 2858 err = tcam_wait_bit(np, TCAM_CTL_STAT); 2859 if (!err) 2860 *data = nr64(TCAM_KEY_1); 2861 2862 return err; 2863 } 2864 #endif 2865 2866 static int tcam_assoc_write(struct niu *np, int index, u64 assoc_data) 2867 { 2868 nw64(TCAM_KEY_1, assoc_data); 2869 nw64(TCAM_CTL, (TCAM_CTL_RWC_RAM_WRITE | index)); 2870 2871 return tcam_wait_bit(np, TCAM_CTL_STAT); 2872 } 2873 2874 static void tcam_enable(struct niu *np, int on) 2875 { 2876 u64 val = nr64(FFLP_CFG_1); 2877 2878 if (on) 2879 val &= ~FFLP_CFG_1_TCAM_DIS; 2880 else 2881 val |= FFLP_CFG_1_TCAM_DIS; 2882 nw64(FFLP_CFG_1, val); 2883 } 2884 2885 static void tcam_set_lat_and_ratio(struct niu *np, u64 latency, u64 ratio) 2886 { 2887 u64 val = nr64(FFLP_CFG_1); 2888 2889 val &= ~(FFLP_CFG_1_FFLPINITDONE | 2890 FFLP_CFG_1_CAMLAT | 2891 FFLP_CFG_1_CAMRATIO); 2892 val |= (latency << FFLP_CFG_1_CAMLAT_SHIFT); 2893 val |= (ratio << FFLP_CFG_1_CAMRATIO_SHIFT); 2894 nw64(FFLP_CFG_1, val); 2895 2896 val = nr64(FFLP_CFG_1); 2897 val |= FFLP_CFG_1_FFLPINITDONE; 2898 nw64(FFLP_CFG_1, val); 2899 } 2900 2901 static int tcam_user_eth_class_enable(struct niu *np, unsigned long class, 2902 int on) 2903 { 2904 unsigned long reg; 2905 u64 val; 2906 2907 if (class < CLASS_CODE_ETHERTYPE1 || 2908 class > CLASS_CODE_ETHERTYPE2) 2909 return -EINVAL; 2910 2911 reg = L2_CLS(class - CLASS_CODE_ETHERTYPE1); 2912 val = nr64(reg); 2913 if (on) 2914 val |= L2_CLS_VLD; 2915 else 2916 val &= ~L2_CLS_VLD; 2917 nw64(reg, val); 2918 2919 return 0; 2920 } 2921 2922 #if 0 2923 static int tcam_user_eth_class_set(struct niu *np, unsigned long class, 2924 u64 ether_type) 2925 { 2926 unsigned long reg; 2927 u64 val; 2928 2929 if (class < CLASS_CODE_ETHERTYPE1 || 2930 class > CLASS_CODE_ETHERTYPE2 || 2931 (ether_type & ~(u64)0xffff) != 0) 2932 return -EINVAL; 2933 2934 reg = L2_CLS(class - CLASS_CODE_ETHERTYPE1); 2935 val = nr64(reg); 2936 val &= ~L2_CLS_ETYPE; 2937 val |= (ether_type << L2_CLS_ETYPE_SHIFT); 2938 nw64(reg, val); 2939 2940 return 0; 2941 } 2942 #endif 2943 2944 static int tcam_user_ip_class_enable(struct niu *np, unsigned long class, 2945 int on) 2946 { 2947 unsigned long reg; 2948 u64 val; 2949 2950 if (class < CLASS_CODE_USER_PROG1 || 2951 class > CLASS_CODE_USER_PROG4) 2952 return -EINVAL; 2953 2954 reg = L3_CLS(class - CLASS_CODE_USER_PROG1); 2955 val = nr64(reg); 2956 if (on) 2957 val |= L3_CLS_VALID; 2958 else 2959 val &= ~L3_CLS_VALID; 2960 nw64(reg, val); 2961 2962 return 0; 2963 } 2964 2965 static int tcam_user_ip_class_set(struct niu *np, unsigned long class, 2966 int ipv6, u64 protocol_id, 2967 u64 tos_mask, u64 tos_val) 2968 { 2969 unsigned long reg; 2970 u64 val; 2971 2972 if (class < CLASS_CODE_USER_PROG1 || 2973 class > CLASS_CODE_USER_PROG4 || 2974 (protocol_id & ~(u64)0xff) != 0 || 2975 (tos_mask & ~(u64)0xff) != 0 || 2976 (tos_val & ~(u64)0xff) != 0) 2977 return -EINVAL; 2978 2979 reg = L3_CLS(class - CLASS_CODE_USER_PROG1); 2980 val = nr64(reg); 2981 val &= ~(L3_CLS_IPVER | L3_CLS_PID | 2982 L3_CLS_TOSMASK | L3_CLS_TOS); 2983 if (ipv6) 2984 val |= L3_CLS_IPVER; 2985 val |= (protocol_id << L3_CLS_PID_SHIFT); 2986 val |= (tos_mask << L3_CLS_TOSMASK_SHIFT); 2987 val |= (tos_val << L3_CLS_TOS_SHIFT); 2988 nw64(reg, val); 2989 2990 return 0; 2991 } 2992 2993 static int tcam_early_init(struct niu *np) 2994 { 2995 unsigned long i; 2996 int err; 2997 2998 tcam_enable(np, 0); 2999 tcam_set_lat_and_ratio(np, 3000 DEFAULT_TCAM_LATENCY, 3001 DEFAULT_TCAM_ACCESS_RATIO); 3002 for (i = CLASS_CODE_ETHERTYPE1; i <= CLASS_CODE_ETHERTYPE2; i++) { 3003 err = tcam_user_eth_class_enable(np, i, 0); 3004 if (err) 3005 return err; 3006 } 3007 for (i = CLASS_CODE_USER_PROG1; i <= CLASS_CODE_USER_PROG4; i++) { 3008 err = tcam_user_ip_class_enable(np, i, 0); 3009 if (err) 3010 return err; 3011 } 3012 3013 return 0; 3014 } 3015 3016 static int tcam_flush_all(struct niu *np) 3017 { 3018 unsigned long i; 3019 3020 for (i = 0; i < np->parent->tcam_num_entries; i++) { 3021 int err = tcam_flush(np, i); 3022 if (err) 3023 return err; 3024 } 3025 return 0; 3026 } 3027 3028 static u64 hash_addr_regval(unsigned long index, unsigned long num_entries) 3029 { 3030 return (u64)index | (num_entries == 1 ? HASH_TBL_ADDR_AUTOINC : 0); 3031 } 3032 3033 #if 0 3034 static int hash_read(struct niu *np, unsigned long partition, 3035 unsigned long index, unsigned long num_entries, 3036 u64 *data) 3037 { 3038 u64 val = hash_addr_regval(index, num_entries); 3039 unsigned long i; 3040 3041 if (partition >= FCRAM_NUM_PARTITIONS || 3042 index + num_entries > FCRAM_SIZE) 3043 return -EINVAL; 3044 3045 nw64(HASH_TBL_ADDR(partition), val); 3046 for (i = 0; i < num_entries; i++) 3047 data[i] = nr64(HASH_TBL_DATA(partition)); 3048 3049 return 0; 3050 } 3051 #endif 3052 3053 static int hash_write(struct niu *np, unsigned long partition, 3054 unsigned long index, unsigned long num_entries, 3055 u64 *data) 3056 { 3057 u64 val = hash_addr_regval(index, num_entries); 3058 unsigned long i; 3059 3060 if (partition >= FCRAM_NUM_PARTITIONS || 3061 index + (num_entries * 8) > FCRAM_SIZE) 3062 return -EINVAL; 3063 3064 nw64(HASH_TBL_ADDR(partition), val); 3065 for (i = 0; i < num_entries; i++) 3066 nw64(HASH_TBL_DATA(partition), data[i]); 3067 3068 return 0; 3069 } 3070 3071 static void fflp_reset(struct niu *np) 3072 { 3073 u64 val; 3074 3075 nw64(FFLP_CFG_1, FFLP_CFG_1_PIO_FIO_RST); 3076 udelay(10); 3077 nw64(FFLP_CFG_1, 0); 3078 3079 val = FFLP_CFG_1_FCRAMOUTDR_NORMAL | FFLP_CFG_1_FFLPINITDONE; 3080 nw64(FFLP_CFG_1, val); 3081 } 3082 3083 static void fflp_set_timings(struct niu *np) 3084 { 3085 u64 val = nr64(FFLP_CFG_1); 3086 3087 val &= ~FFLP_CFG_1_FFLPINITDONE; 3088 val |= (DEFAULT_FCRAMRATIO << FFLP_CFG_1_FCRAMRATIO_SHIFT); 3089 nw64(FFLP_CFG_1, val); 3090 3091 val = nr64(FFLP_CFG_1); 3092 val |= FFLP_CFG_1_FFLPINITDONE; 3093 nw64(FFLP_CFG_1, val); 3094 3095 val = nr64(FCRAM_REF_TMR); 3096 val &= ~(FCRAM_REF_TMR_MAX | FCRAM_REF_TMR_MIN); 3097 val |= (DEFAULT_FCRAM_REFRESH_MAX << FCRAM_REF_TMR_MAX_SHIFT); 3098 val |= (DEFAULT_FCRAM_REFRESH_MIN << FCRAM_REF_TMR_MIN_SHIFT); 3099 nw64(FCRAM_REF_TMR, val); 3100 } 3101 3102 static int fflp_set_partition(struct niu *np, u64 partition, 3103 u64 mask, u64 base, int enable) 3104 { 3105 unsigned long reg; 3106 u64 val; 3107 3108 if (partition >= FCRAM_NUM_PARTITIONS || 3109 (mask & ~(u64)0x1f) != 0 || 3110 (base & ~(u64)0x1f) != 0) 3111 return -EINVAL; 3112 3113 reg = FLW_PRT_SEL(partition); 3114 3115 val = nr64(reg); 3116 val &= ~(FLW_PRT_SEL_EXT | FLW_PRT_SEL_MASK | FLW_PRT_SEL_BASE); 3117 val |= (mask << FLW_PRT_SEL_MASK_SHIFT); 3118 val |= (base << FLW_PRT_SEL_BASE_SHIFT); 3119 if (enable) 3120 val |= FLW_PRT_SEL_EXT; 3121 nw64(reg, val); 3122 3123 return 0; 3124 } 3125 3126 static int fflp_disable_all_partitions(struct niu *np) 3127 { 3128 unsigned long i; 3129 3130 for (i = 0; i < FCRAM_NUM_PARTITIONS; i++) { 3131 int err = fflp_set_partition(np, 0, 0, 0, 0); 3132 if (err) 3133 return err; 3134 } 3135 return 0; 3136 } 3137 3138 static void fflp_llcsnap_enable(struct niu *np, int on) 3139 { 3140 u64 val = nr64(FFLP_CFG_1); 3141 3142 if (on) 3143 val |= FFLP_CFG_1_LLCSNAP; 3144 else 3145 val &= ~FFLP_CFG_1_LLCSNAP; 3146 nw64(FFLP_CFG_1, val); 3147 } 3148 3149 static void fflp_errors_enable(struct niu *np, int on) 3150 { 3151 u64 val = nr64(FFLP_CFG_1); 3152 3153 if (on) 3154 val &= ~FFLP_CFG_1_ERRORDIS; 3155 else 3156 val |= FFLP_CFG_1_ERRORDIS; 3157 nw64(FFLP_CFG_1, val); 3158 } 3159 3160 static int fflp_hash_clear(struct niu *np) 3161 { 3162 struct fcram_hash_ipv4 ent; 3163 unsigned long i; 3164 3165 /* IPV4 hash entry with valid bit clear, rest is don't care. */ 3166 memset(&ent, 0, sizeof(ent)); 3167 ent.header = HASH_HEADER_EXT; 3168 3169 for (i = 0; i < FCRAM_SIZE; i += sizeof(ent)) { 3170 int err = hash_write(np, 0, i, 1, (u64 *) &ent); 3171 if (err) 3172 return err; 3173 } 3174 return 0; 3175 } 3176 3177 static int fflp_early_init(struct niu *np) 3178 { 3179 struct niu_parent *parent; 3180 unsigned long flags; 3181 int err; 3182 3183 niu_lock_parent(np, flags); 3184 3185 parent = np->parent; 3186 err = 0; 3187 if (!(parent->flags & PARENT_FLGS_CLS_HWINIT)) { 3188 if (np->parent->plat_type != PLAT_TYPE_NIU) { 3189 fflp_reset(np); 3190 fflp_set_timings(np); 3191 err = fflp_disable_all_partitions(np); 3192 if (err) { 3193 netif_printk(np, probe, KERN_DEBUG, np->dev, 3194 "fflp_disable_all_partitions failed, err=%d\n", 3195 err); 3196 goto out; 3197 } 3198 } 3199 3200 err = tcam_early_init(np); 3201 if (err) { 3202 netif_printk(np, probe, KERN_DEBUG, np->dev, 3203 "tcam_early_init failed, err=%d\n", err); 3204 goto out; 3205 } 3206 fflp_llcsnap_enable(np, 1); 3207 fflp_errors_enable(np, 0); 3208 nw64(H1POLY, 0); 3209 nw64(H2POLY, 0); 3210 3211 err = tcam_flush_all(np); 3212 if (err) { 3213 netif_printk(np, probe, KERN_DEBUG, np->dev, 3214 "tcam_flush_all failed, err=%d\n", err); 3215 goto out; 3216 } 3217 if (np->parent->plat_type != PLAT_TYPE_NIU) { 3218 err = fflp_hash_clear(np); 3219 if (err) { 3220 netif_printk(np, probe, KERN_DEBUG, np->dev, 3221 "fflp_hash_clear failed, err=%d\n", 3222 err); 3223 goto out; 3224 } 3225 } 3226 3227 vlan_tbl_clear(np); 3228 3229 parent->flags |= PARENT_FLGS_CLS_HWINIT; 3230 } 3231 out: 3232 niu_unlock_parent(np, flags); 3233 return err; 3234 } 3235 3236 static int niu_set_flow_key(struct niu *np, unsigned long class_code, u64 key) 3237 { 3238 if (class_code < CLASS_CODE_USER_PROG1 || 3239 class_code > CLASS_CODE_SCTP_IPV6) 3240 return -EINVAL; 3241 3242 nw64(FLOW_KEY(class_code - CLASS_CODE_USER_PROG1), key); 3243 return 0; 3244 } 3245 3246 static int niu_set_tcam_key(struct niu *np, unsigned long class_code, u64 key) 3247 { 3248 if (class_code < CLASS_CODE_USER_PROG1 || 3249 class_code > CLASS_CODE_SCTP_IPV6) 3250 return -EINVAL; 3251 3252 nw64(TCAM_KEY(class_code - CLASS_CODE_USER_PROG1), key); 3253 return 0; 3254 } 3255 3256 /* Entries for the ports are interleaved in the TCAM */ 3257 static u16 tcam_get_index(struct niu *np, u16 idx) 3258 { 3259 /* One entry reserved for IP fragment rule */ 3260 if (idx >= (np->clas.tcam_sz - 1)) 3261 idx = 0; 3262 return np->clas.tcam_top + ((idx+1) * np->parent->num_ports); 3263 } 3264 3265 static u16 tcam_get_size(struct niu *np) 3266 { 3267 /* One entry reserved for IP fragment rule */ 3268 return np->clas.tcam_sz - 1; 3269 } 3270 3271 static u16 tcam_get_valid_entry_cnt(struct niu *np) 3272 { 3273 /* One entry reserved for IP fragment rule */ 3274 return np->clas.tcam_valid_entries - 1; 3275 } 3276 3277 static void niu_rx_skb_append(struct sk_buff *skb, struct page *page, 3278 u32 offset, u32 size, u32 truesize) 3279 { 3280 skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags, page, offset, size); 3281 3282 skb->len += size; 3283 skb->data_len += size; 3284 skb->truesize += truesize; 3285 } 3286 3287 static unsigned int niu_hash_rxaddr(struct rx_ring_info *rp, u64 a) 3288 { 3289 a >>= PAGE_SHIFT; 3290 a ^= (a >> ilog2(MAX_RBR_RING_SIZE)); 3291 3292 return a & (MAX_RBR_RING_SIZE - 1); 3293 } 3294 3295 static struct page *niu_find_rxpage(struct rx_ring_info *rp, u64 addr, 3296 struct page ***link) 3297 { 3298 unsigned int h = niu_hash_rxaddr(rp, addr); 3299 struct page *p, **pp; 3300 3301 addr &= PAGE_MASK; 3302 pp = &rp->rxhash[h]; 3303 for (; (p = *pp) != NULL; pp = (struct page **) &p->mapping) { 3304 if (p->index == addr) { 3305 *link = pp; 3306 goto found; 3307 } 3308 } 3309 BUG(); 3310 3311 found: 3312 return p; 3313 } 3314 3315 static void niu_hash_page(struct rx_ring_info *rp, struct page *page, u64 base) 3316 { 3317 unsigned int h = niu_hash_rxaddr(rp, base); 3318 3319 page->index = base; 3320 page->mapping = (struct address_space *) rp->rxhash[h]; 3321 rp->rxhash[h] = page; 3322 } 3323 3324 static int niu_rbr_add_page(struct niu *np, struct rx_ring_info *rp, 3325 gfp_t mask, int start_index) 3326 { 3327 struct page *page; 3328 u64 addr; 3329 int i; 3330 3331 page = alloc_page(mask); 3332 if (!page) 3333 return -ENOMEM; 3334 3335 addr = np->ops->map_page(np->device, page, 0, 3336 PAGE_SIZE, DMA_FROM_DEVICE); 3337 if (!addr) { 3338 __free_page(page); 3339 return -ENOMEM; 3340 } 3341 3342 niu_hash_page(rp, page, addr); 3343 if (rp->rbr_blocks_per_page > 1) 3344 atomic_add(rp->rbr_blocks_per_page - 1, 3345 &compound_head(page)->_count); 3346 3347 for (i = 0; i < rp->rbr_blocks_per_page; i++) { 3348 __le32 *rbr = &rp->rbr[start_index + i]; 3349 3350 *rbr = cpu_to_le32(addr >> RBR_DESCR_ADDR_SHIFT); 3351 addr += rp->rbr_block_size; 3352 } 3353 3354 return 0; 3355 } 3356 3357 static void niu_rbr_refill(struct niu *np, struct rx_ring_info *rp, gfp_t mask) 3358 { 3359 int index = rp->rbr_index; 3360 3361 rp->rbr_pending++; 3362 if ((rp->rbr_pending % rp->rbr_blocks_per_page) == 0) { 3363 int err = niu_rbr_add_page(np, rp, mask, index); 3364 3365 if (unlikely(err)) { 3366 rp->rbr_pending--; 3367 return; 3368 } 3369 3370 rp->rbr_index += rp->rbr_blocks_per_page; 3371 BUG_ON(rp->rbr_index > rp->rbr_table_size); 3372 if (rp->rbr_index == rp->rbr_table_size) 3373 rp->rbr_index = 0; 3374 3375 if (rp->rbr_pending >= rp->rbr_kick_thresh) { 3376 nw64(RBR_KICK(rp->rx_channel), rp->rbr_pending); 3377 rp->rbr_pending = 0; 3378 } 3379 } 3380 } 3381 3382 static int niu_rx_pkt_ignore(struct niu *np, struct rx_ring_info *rp) 3383 { 3384 unsigned int index = rp->rcr_index; 3385 int num_rcr = 0; 3386 3387 rp->rx_dropped++; 3388 while (1) { 3389 struct page *page, **link; 3390 u64 addr, val; 3391 u32 rcr_size; 3392 3393 num_rcr++; 3394 3395 val = le64_to_cpup(&rp->rcr[index]); 3396 addr = (val & RCR_ENTRY_PKT_BUF_ADDR) << 3397 RCR_ENTRY_PKT_BUF_ADDR_SHIFT; 3398 page = niu_find_rxpage(rp, addr, &link); 3399 3400 rcr_size = rp->rbr_sizes[(val & RCR_ENTRY_PKTBUFSZ) >> 3401 RCR_ENTRY_PKTBUFSZ_SHIFT]; 3402 if ((page->index + PAGE_SIZE) - rcr_size == addr) { 3403 *link = (struct page *) page->mapping; 3404 np->ops->unmap_page(np->device, page->index, 3405 PAGE_SIZE, DMA_FROM_DEVICE); 3406 page->index = 0; 3407 page->mapping = NULL; 3408 __free_page(page); 3409 rp->rbr_refill_pending++; 3410 } 3411 3412 index = NEXT_RCR(rp, index); 3413 if (!(val & RCR_ENTRY_MULTI)) 3414 break; 3415 3416 } 3417 rp->rcr_index = index; 3418 3419 return num_rcr; 3420 } 3421 3422 static int niu_process_rx_pkt(struct napi_struct *napi, struct niu *np, 3423 struct rx_ring_info *rp) 3424 { 3425 unsigned int index = rp->rcr_index; 3426 struct rx_pkt_hdr1 *rh; 3427 struct sk_buff *skb; 3428 int len, num_rcr; 3429 3430 skb = netdev_alloc_skb(np->dev, RX_SKB_ALLOC_SIZE); 3431 if (unlikely(!skb)) 3432 return niu_rx_pkt_ignore(np, rp); 3433 3434 num_rcr = 0; 3435 while (1) { 3436 struct page *page, **link; 3437 u32 rcr_size, append_size; 3438 u64 addr, val, off; 3439 3440 num_rcr++; 3441 3442 val = le64_to_cpup(&rp->rcr[index]); 3443 3444 len = (val & RCR_ENTRY_L2_LEN) >> 3445 RCR_ENTRY_L2_LEN_SHIFT; 3446 len -= ETH_FCS_LEN; 3447 3448 addr = (val & RCR_ENTRY_PKT_BUF_ADDR) << 3449 RCR_ENTRY_PKT_BUF_ADDR_SHIFT; 3450 page = niu_find_rxpage(rp, addr, &link); 3451 3452 rcr_size = rp->rbr_sizes[(val & RCR_ENTRY_PKTBUFSZ) >> 3453 RCR_ENTRY_PKTBUFSZ_SHIFT]; 3454 3455 off = addr & ~PAGE_MASK; 3456 append_size = rcr_size; 3457 if (num_rcr == 1) { 3458 int ptype; 3459 3460 ptype = (val >> RCR_ENTRY_PKT_TYPE_SHIFT); 3461 if ((ptype == RCR_PKT_TYPE_TCP || 3462 ptype == RCR_PKT_TYPE_UDP) && 3463 !(val & (RCR_ENTRY_NOPORT | 3464 RCR_ENTRY_ERROR))) 3465 skb->ip_summed = CHECKSUM_UNNECESSARY; 3466 else 3467 skb_checksum_none_assert(skb); 3468 } else if (!(val & RCR_ENTRY_MULTI)) 3469 append_size = len - skb->len; 3470 3471 niu_rx_skb_append(skb, page, off, append_size, rcr_size); 3472 if ((page->index + rp->rbr_block_size) - rcr_size == addr) { 3473 *link = (struct page *) page->mapping; 3474 np->ops->unmap_page(np->device, page->index, 3475 PAGE_SIZE, DMA_FROM_DEVICE); 3476 page->index = 0; 3477 page->mapping = NULL; 3478 rp->rbr_refill_pending++; 3479 } else 3480 get_page(page); 3481 3482 index = NEXT_RCR(rp, index); 3483 if (!(val & RCR_ENTRY_MULTI)) 3484 break; 3485 3486 } 3487 rp->rcr_index = index; 3488 3489 len += sizeof(*rh); 3490 len = min_t(int, len, sizeof(*rh) + VLAN_ETH_HLEN); 3491 __pskb_pull_tail(skb, len); 3492 3493 rh = (struct rx_pkt_hdr1 *) skb->data; 3494 if (np->dev->features & NETIF_F_RXHASH) 3495 skb_set_hash(skb, 3496 ((u32)rh->hashval2_0 << 24 | 3497 (u32)rh->hashval2_1 << 16 | 3498 (u32)rh->hashval1_1 << 8 | 3499 (u32)rh->hashval1_2 << 0), 3500 PKT_HASH_TYPE_L3); 3501 skb_pull(skb, sizeof(*rh)); 3502 3503 rp->rx_packets++; 3504 rp->rx_bytes += skb->len; 3505 3506 skb->protocol = eth_type_trans(skb, np->dev); 3507 skb_record_rx_queue(skb, rp->rx_channel); 3508 napi_gro_receive(napi, skb); 3509 3510 return num_rcr; 3511 } 3512 3513 static int niu_rbr_fill(struct niu *np, struct rx_ring_info *rp, gfp_t mask) 3514 { 3515 int blocks_per_page = rp->rbr_blocks_per_page; 3516 int err, index = rp->rbr_index; 3517 3518 err = 0; 3519 while (index < (rp->rbr_table_size - blocks_per_page)) { 3520 err = niu_rbr_add_page(np, rp, mask, index); 3521 if (unlikely(err)) 3522 break; 3523 3524 index += blocks_per_page; 3525 } 3526 3527 rp->rbr_index = index; 3528 return err; 3529 } 3530 3531 static void niu_rbr_free(struct niu *np, struct rx_ring_info *rp) 3532 { 3533 int i; 3534 3535 for (i = 0; i < MAX_RBR_RING_SIZE; i++) { 3536 struct page *page; 3537 3538 page = rp->rxhash[i]; 3539 while (page) { 3540 struct page *next = (struct page *) page->mapping; 3541 u64 base = page->index; 3542 3543 np->ops->unmap_page(np->device, base, PAGE_SIZE, 3544 DMA_FROM_DEVICE); 3545 page->index = 0; 3546 page->mapping = NULL; 3547 3548 __free_page(page); 3549 3550 page = next; 3551 } 3552 } 3553 3554 for (i = 0; i < rp->rbr_table_size; i++) 3555 rp->rbr[i] = cpu_to_le32(0); 3556 rp->rbr_index = 0; 3557 } 3558 3559 static int release_tx_packet(struct niu *np, struct tx_ring_info *rp, int idx) 3560 { 3561 struct tx_buff_info *tb = &rp->tx_buffs[idx]; 3562 struct sk_buff *skb = tb->skb; 3563 struct tx_pkt_hdr *tp; 3564 u64 tx_flags; 3565 int i, len; 3566 3567 tp = (struct tx_pkt_hdr *) skb->data; 3568 tx_flags = le64_to_cpup(&tp->flags); 3569 3570 rp->tx_packets++; 3571 rp->tx_bytes += (((tx_flags & TXHDR_LEN) >> TXHDR_LEN_SHIFT) - 3572 ((tx_flags & TXHDR_PAD) / 2)); 3573 3574 len = skb_headlen(skb); 3575 np->ops->unmap_single(np->device, tb->mapping, 3576 len, DMA_TO_DEVICE); 3577 3578 if (le64_to_cpu(rp->descr[idx]) & TX_DESC_MARK) 3579 rp->mark_pending--; 3580 3581 tb->skb = NULL; 3582 do { 3583 idx = NEXT_TX(rp, idx); 3584 len -= MAX_TX_DESC_LEN; 3585 } while (len > 0); 3586 3587 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { 3588 tb = &rp->tx_buffs[idx]; 3589 BUG_ON(tb->skb != NULL); 3590 np->ops->unmap_page(np->device, tb->mapping, 3591 skb_frag_size(&skb_shinfo(skb)->frags[i]), 3592 DMA_TO_DEVICE); 3593 idx = NEXT_TX(rp, idx); 3594 } 3595 3596 dev_kfree_skb(skb); 3597 3598 return idx; 3599 } 3600 3601 #define NIU_TX_WAKEUP_THRESH(rp) ((rp)->pending / 4) 3602 3603 static void niu_tx_work(struct niu *np, struct tx_ring_info *rp) 3604 { 3605 struct netdev_queue *txq; 3606 u16 pkt_cnt, tmp; 3607 int cons, index; 3608 u64 cs; 3609 3610 index = (rp - np->tx_rings); 3611 txq = netdev_get_tx_queue(np->dev, index); 3612 3613 cs = rp->tx_cs; 3614 if (unlikely(!(cs & (TX_CS_MK | TX_CS_MMK)))) 3615 goto out; 3616 3617 tmp = pkt_cnt = (cs & TX_CS_PKT_CNT) >> TX_CS_PKT_CNT_SHIFT; 3618 pkt_cnt = (pkt_cnt - rp->last_pkt_cnt) & 3619 (TX_CS_PKT_CNT >> TX_CS_PKT_CNT_SHIFT); 3620 3621 rp->last_pkt_cnt = tmp; 3622 3623 cons = rp->cons; 3624 3625 netif_printk(np, tx_done, KERN_DEBUG, np->dev, 3626 "%s() pkt_cnt[%u] cons[%d]\n", __func__, pkt_cnt, cons); 3627 3628 while (pkt_cnt--) 3629 cons = release_tx_packet(np, rp, cons); 3630 3631 rp->cons = cons; 3632 smp_mb(); 3633 3634 out: 3635 if (unlikely(netif_tx_queue_stopped(txq) && 3636 (niu_tx_avail(rp) > NIU_TX_WAKEUP_THRESH(rp)))) { 3637 __netif_tx_lock(txq, smp_processor_id()); 3638 if (netif_tx_queue_stopped(txq) && 3639 (niu_tx_avail(rp) > NIU_TX_WAKEUP_THRESH(rp))) 3640 netif_tx_wake_queue(txq); 3641 __netif_tx_unlock(txq); 3642 } 3643 } 3644 3645 static inline void niu_sync_rx_discard_stats(struct niu *np, 3646 struct rx_ring_info *rp, 3647 const int limit) 3648 { 3649 /* This elaborate scheme is needed for reading the RX discard 3650 * counters, as they are only 16-bit and can overflow quickly, 3651 * and because the overflow indication bit is not usable as 3652 * the counter value does not wrap, but remains at max value 3653 * 0xFFFF. 3654 * 3655 * In theory and in practice counters can be lost in between 3656 * reading nr64() and clearing the counter nw64(). For this 3657 * reason, the number of counter clearings nw64() is 3658 * limited/reduced though the limit parameter. 3659 */ 3660 int rx_channel = rp->rx_channel; 3661 u32 misc, wred; 3662 3663 /* RXMISC (Receive Miscellaneous Discard Count), covers the 3664 * following discard events: IPP (Input Port Process), 3665 * FFLP/TCAM, Full RCR (Receive Completion Ring) RBR (Receive 3666 * Block Ring) prefetch buffer is empty. 3667 */ 3668 misc = nr64(RXMISC(rx_channel)); 3669 if (unlikely((misc & RXMISC_COUNT) > limit)) { 3670 nw64(RXMISC(rx_channel), 0); 3671 rp->rx_errors += misc & RXMISC_COUNT; 3672 3673 if (unlikely(misc & RXMISC_OFLOW)) 3674 dev_err(np->device, "rx-%d: Counter overflow RXMISC discard\n", 3675 rx_channel); 3676 3677 netif_printk(np, rx_err, KERN_DEBUG, np->dev, 3678 "rx-%d: MISC drop=%u over=%u\n", 3679 rx_channel, misc, misc-limit); 3680 } 3681 3682 /* WRED (Weighted Random Early Discard) by hardware */ 3683 wred = nr64(RED_DIS_CNT(rx_channel)); 3684 if (unlikely((wred & RED_DIS_CNT_COUNT) > limit)) { 3685 nw64(RED_DIS_CNT(rx_channel), 0); 3686 rp->rx_dropped += wred & RED_DIS_CNT_COUNT; 3687 3688 if (unlikely(wred & RED_DIS_CNT_OFLOW)) 3689 dev_err(np->device, "rx-%d: Counter overflow WRED discard\n", rx_channel); 3690 3691 netif_printk(np, rx_err, KERN_DEBUG, np->dev, 3692 "rx-%d: WRED drop=%u over=%u\n", 3693 rx_channel, wred, wred-limit); 3694 } 3695 } 3696 3697 static int niu_rx_work(struct napi_struct *napi, struct niu *np, 3698 struct rx_ring_info *rp, int budget) 3699 { 3700 int qlen, rcr_done = 0, work_done = 0; 3701 struct rxdma_mailbox *mbox = rp->mbox; 3702 u64 stat; 3703 3704 #if 1 3705 stat = nr64(RX_DMA_CTL_STAT(rp->rx_channel)); 3706 qlen = nr64(RCRSTAT_A(rp->rx_channel)) & RCRSTAT_A_QLEN; 3707 #else 3708 stat = le64_to_cpup(&mbox->rx_dma_ctl_stat); 3709 qlen = (le64_to_cpup(&mbox->rcrstat_a) & RCRSTAT_A_QLEN); 3710 #endif 3711 mbox->rx_dma_ctl_stat = 0; 3712 mbox->rcrstat_a = 0; 3713 3714 netif_printk(np, rx_status, KERN_DEBUG, np->dev, 3715 "%s(chan[%d]), stat[%llx] qlen=%d\n", 3716 __func__, rp->rx_channel, (unsigned long long)stat, qlen); 3717 3718 rcr_done = work_done = 0; 3719 qlen = min(qlen, budget); 3720 while (work_done < qlen) { 3721 rcr_done += niu_process_rx_pkt(napi, np, rp); 3722 work_done++; 3723 } 3724 3725 if (rp->rbr_refill_pending >= rp->rbr_kick_thresh) { 3726 unsigned int i; 3727 3728 for (i = 0; i < rp->rbr_refill_pending; i++) 3729 niu_rbr_refill(np, rp, GFP_ATOMIC); 3730 rp->rbr_refill_pending = 0; 3731 } 3732 3733 stat = (RX_DMA_CTL_STAT_MEX | 3734 ((u64)work_done << RX_DMA_CTL_STAT_PKTREAD_SHIFT) | 3735 ((u64)rcr_done << RX_DMA_CTL_STAT_PTRREAD_SHIFT)); 3736 3737 nw64(RX_DMA_CTL_STAT(rp->rx_channel), stat); 3738 3739 /* Only sync discards stats when qlen indicate potential for drops */ 3740 if (qlen > 10) 3741 niu_sync_rx_discard_stats(np, rp, 0x7FFF); 3742 3743 return work_done; 3744 } 3745 3746 static int niu_poll_core(struct niu *np, struct niu_ldg *lp, int budget) 3747 { 3748 u64 v0 = lp->v0; 3749 u32 tx_vec = (v0 >> 32); 3750 u32 rx_vec = (v0 & 0xffffffff); 3751 int i, work_done = 0; 3752 3753 netif_printk(np, intr, KERN_DEBUG, np->dev, 3754 "%s() v0[%016llx]\n", __func__, (unsigned long long)v0); 3755 3756 for (i = 0; i < np->num_tx_rings; i++) { 3757 struct tx_ring_info *rp = &np->tx_rings[i]; 3758 if (tx_vec & (1 << rp->tx_channel)) 3759 niu_tx_work(np, rp); 3760 nw64(LD_IM0(LDN_TXDMA(rp->tx_channel)), 0); 3761 } 3762 3763 for (i = 0; i < np->num_rx_rings; i++) { 3764 struct rx_ring_info *rp = &np->rx_rings[i]; 3765 3766 if (rx_vec & (1 << rp->rx_channel)) { 3767 int this_work_done; 3768 3769 this_work_done = niu_rx_work(&lp->napi, np, rp, 3770 budget); 3771 3772 budget -= this_work_done; 3773 work_done += this_work_done; 3774 } 3775 nw64(LD_IM0(LDN_RXDMA(rp->rx_channel)), 0); 3776 } 3777 3778 return work_done; 3779 } 3780 3781 static int niu_poll(struct napi_struct *napi, int budget) 3782 { 3783 struct niu_ldg *lp = container_of(napi, struct niu_ldg, napi); 3784 struct niu *np = lp->np; 3785 int work_done; 3786 3787 work_done = niu_poll_core(np, lp, budget); 3788 3789 if (work_done < budget) { 3790 napi_complete(napi); 3791 niu_ldg_rearm(np, lp, 1); 3792 } 3793 return work_done; 3794 } 3795 3796 static void niu_log_rxchan_errors(struct niu *np, struct rx_ring_info *rp, 3797 u64 stat) 3798 { 3799 netdev_err(np->dev, "RX channel %u errors ( ", rp->rx_channel); 3800 3801 if (stat & RX_DMA_CTL_STAT_RBR_TMOUT) 3802 pr_cont("RBR_TMOUT "); 3803 if (stat & RX_DMA_CTL_STAT_RSP_CNT_ERR) 3804 pr_cont("RSP_CNT "); 3805 if (stat & RX_DMA_CTL_STAT_BYTE_EN_BUS) 3806 pr_cont("BYTE_EN_BUS "); 3807 if (stat & RX_DMA_CTL_STAT_RSP_DAT_ERR) 3808 pr_cont("RSP_DAT "); 3809 if (stat & RX_DMA_CTL_STAT_RCR_ACK_ERR) 3810 pr_cont("RCR_ACK "); 3811 if (stat & RX_DMA_CTL_STAT_RCR_SHA_PAR) 3812 pr_cont("RCR_SHA_PAR "); 3813 if (stat & RX_DMA_CTL_STAT_RBR_PRE_PAR) 3814 pr_cont("RBR_PRE_PAR "); 3815 if (stat & RX_DMA_CTL_STAT_CONFIG_ERR) 3816 pr_cont("CONFIG "); 3817 if (stat & RX_DMA_CTL_STAT_RCRINCON) 3818 pr_cont("RCRINCON "); 3819 if (stat & RX_DMA_CTL_STAT_RCRFULL) 3820 pr_cont("RCRFULL "); 3821 if (stat & RX_DMA_CTL_STAT_RBRFULL) 3822 pr_cont("RBRFULL "); 3823 if (stat & RX_DMA_CTL_STAT_RBRLOGPAGE) 3824 pr_cont("RBRLOGPAGE "); 3825 if (stat & RX_DMA_CTL_STAT_CFIGLOGPAGE) 3826 pr_cont("CFIGLOGPAGE "); 3827 if (stat & RX_DMA_CTL_STAT_DC_FIFO_ERR) 3828 pr_cont("DC_FIDO "); 3829 3830 pr_cont(")\n"); 3831 } 3832 3833 static int niu_rx_error(struct niu *np, struct rx_ring_info *rp) 3834 { 3835 u64 stat = nr64(RX_DMA_CTL_STAT(rp->rx_channel)); 3836 int err = 0; 3837 3838 3839 if (stat & (RX_DMA_CTL_STAT_CHAN_FATAL | 3840 RX_DMA_CTL_STAT_PORT_FATAL)) 3841 err = -EINVAL; 3842 3843 if (err) { 3844 netdev_err(np->dev, "RX channel %u error, stat[%llx]\n", 3845 rp->rx_channel, 3846 (unsigned long long) stat); 3847 3848 niu_log_rxchan_errors(np, rp, stat); 3849 } 3850 3851 nw64(RX_DMA_CTL_STAT(rp->rx_channel), 3852 stat & RX_DMA_CTL_WRITE_CLEAR_ERRS); 3853 3854 return err; 3855 } 3856 3857 static void niu_log_txchan_errors(struct niu *np, struct tx_ring_info *rp, 3858 u64 cs) 3859 { 3860 netdev_err(np->dev, "TX channel %u errors ( ", rp->tx_channel); 3861 3862 if (cs & TX_CS_MBOX_ERR) 3863 pr_cont("MBOX "); 3864 if (cs & TX_CS_PKT_SIZE_ERR) 3865 pr_cont("PKT_SIZE "); 3866 if (cs & TX_CS_TX_RING_OFLOW) 3867 pr_cont("TX_RING_OFLOW "); 3868 if (cs & TX_CS_PREF_BUF_PAR_ERR) 3869 pr_cont("PREF_BUF_PAR "); 3870 if (cs & TX_CS_NACK_PREF) 3871 pr_cont("NACK_PREF "); 3872 if (cs & TX_CS_NACK_PKT_RD) 3873 pr_cont("NACK_PKT_RD "); 3874 if (cs & TX_CS_CONF_PART_ERR) 3875 pr_cont("CONF_PART "); 3876 if (cs & TX_CS_PKT_PRT_ERR) 3877 pr_cont("PKT_PTR "); 3878 3879 pr_cont(")\n"); 3880 } 3881 3882 static int niu_tx_error(struct niu *np, struct tx_ring_info *rp) 3883 { 3884 u64 cs, logh, logl; 3885 3886 cs = nr64(TX_CS(rp->tx_channel)); 3887 logh = nr64(TX_RNG_ERR_LOGH(rp->tx_channel)); 3888 logl = nr64(TX_RNG_ERR_LOGL(rp->tx_channel)); 3889 3890 netdev_err(np->dev, "TX channel %u error, cs[%llx] logh[%llx] logl[%llx]\n", 3891 rp->tx_channel, 3892 (unsigned long long)cs, 3893 (unsigned long long)logh, 3894 (unsigned long long)logl); 3895 3896 niu_log_txchan_errors(np, rp, cs); 3897 3898 return -ENODEV; 3899 } 3900 3901 static int niu_mif_interrupt(struct niu *np) 3902 { 3903 u64 mif_status = nr64(MIF_STATUS); 3904 int phy_mdint = 0; 3905 3906 if (np->flags & NIU_FLAGS_XMAC) { 3907 u64 xrxmac_stat = nr64_mac(XRXMAC_STATUS); 3908 3909 if (xrxmac_stat & XRXMAC_STATUS_PHY_MDINT) 3910 phy_mdint = 1; 3911 } 3912 3913 netdev_err(np->dev, "MIF interrupt, stat[%llx] phy_mdint(%d)\n", 3914 (unsigned long long)mif_status, phy_mdint); 3915 3916 return -ENODEV; 3917 } 3918 3919 static void niu_xmac_interrupt(struct niu *np) 3920 { 3921 struct niu_xmac_stats *mp = &np->mac_stats.xmac; 3922 u64 val; 3923 3924 val = nr64_mac(XTXMAC_STATUS); 3925 if (val & XTXMAC_STATUS_FRAME_CNT_EXP) 3926 mp->tx_frames += TXMAC_FRM_CNT_COUNT; 3927 if (val & XTXMAC_STATUS_BYTE_CNT_EXP) 3928 mp->tx_bytes += TXMAC_BYTE_CNT_COUNT; 3929 if (val & XTXMAC_STATUS_TXFIFO_XFR_ERR) 3930 mp->tx_fifo_errors++; 3931 if (val & XTXMAC_STATUS_TXMAC_OFLOW) 3932 mp->tx_overflow_errors++; 3933 if (val & XTXMAC_STATUS_MAX_PSIZE_ERR) 3934 mp->tx_max_pkt_size_errors++; 3935 if (val & XTXMAC_STATUS_TXMAC_UFLOW) 3936 mp->tx_underflow_errors++; 3937 3938 val = nr64_mac(XRXMAC_STATUS); 3939 if (val & XRXMAC_STATUS_LCL_FLT_STATUS) 3940 mp->rx_local_faults++; 3941 if (val & XRXMAC_STATUS_RFLT_DET) 3942 mp->rx_remote_faults++; 3943 if (val & XRXMAC_STATUS_LFLT_CNT_EXP) 3944 mp->rx_link_faults += LINK_FAULT_CNT_COUNT; 3945 if (val & XRXMAC_STATUS_ALIGNERR_CNT_EXP) 3946 mp->rx_align_errors += RXMAC_ALIGN_ERR_CNT_COUNT; 3947 if (val & XRXMAC_STATUS_RXFRAG_CNT_EXP) 3948 mp->rx_frags += RXMAC_FRAG_CNT_COUNT; 3949 if (val & XRXMAC_STATUS_RXMULTF_CNT_EXP) 3950 mp->rx_mcasts += RXMAC_MC_FRM_CNT_COUNT; 3951 if (val & XRXMAC_STATUS_RXBCAST_CNT_EXP) 3952 mp->rx_bcasts += RXMAC_BC_FRM_CNT_COUNT; 3953 if (val & XRXMAC_STATUS_RXBCAST_CNT_EXP) 3954 mp->rx_bcasts += RXMAC_BC_FRM_CNT_COUNT; 3955 if (val & XRXMAC_STATUS_RXHIST1_CNT_EXP) 3956 mp->rx_hist_cnt1 += RXMAC_HIST_CNT1_COUNT; 3957 if (val & XRXMAC_STATUS_RXHIST2_CNT_EXP) 3958 mp->rx_hist_cnt2 += RXMAC_HIST_CNT2_COUNT; 3959 if (val & XRXMAC_STATUS_RXHIST3_CNT_EXP) 3960 mp->rx_hist_cnt3 += RXMAC_HIST_CNT3_COUNT; 3961 if (val & XRXMAC_STATUS_RXHIST4_CNT_EXP) 3962 mp->rx_hist_cnt4 += RXMAC_HIST_CNT4_COUNT; 3963 if (val & XRXMAC_STATUS_RXHIST5_CNT_EXP) 3964 mp->rx_hist_cnt5 += RXMAC_HIST_CNT5_COUNT; 3965 if (val & XRXMAC_STATUS_RXHIST6_CNT_EXP) 3966 mp->rx_hist_cnt6 += RXMAC_HIST_CNT6_COUNT; 3967 if (val & XRXMAC_STATUS_RXHIST7_CNT_EXP) 3968 mp->rx_hist_cnt7 += RXMAC_HIST_CNT7_COUNT; 3969 if (val & XRXMAC_STATUS_RXOCTET_CNT_EXP) 3970 mp->rx_octets += RXMAC_BT_CNT_COUNT; 3971 if (val & XRXMAC_STATUS_CVIOLERR_CNT_EXP) 3972 mp->rx_code_violations += RXMAC_CD_VIO_CNT_COUNT; 3973 if (val & XRXMAC_STATUS_LENERR_CNT_EXP) 3974 mp->rx_len_errors += RXMAC_MPSZER_CNT_COUNT; 3975 if (val & XRXMAC_STATUS_CRCERR_CNT_EXP) 3976 mp->rx_crc_errors += RXMAC_CRC_ER_CNT_COUNT; 3977 if (val & XRXMAC_STATUS_RXUFLOW) 3978 mp->rx_underflows++; 3979 if (val & XRXMAC_STATUS_RXOFLOW) 3980 mp->rx_overflows++; 3981 3982 val = nr64_mac(XMAC_FC_STAT); 3983 if (val & XMAC_FC_STAT_TX_MAC_NPAUSE) 3984 mp->pause_off_state++; 3985 if (val & XMAC_FC_STAT_TX_MAC_PAUSE) 3986 mp->pause_on_state++; 3987 if (val & XMAC_FC_STAT_RX_MAC_RPAUSE) 3988 mp->pause_received++; 3989 } 3990 3991 static void niu_bmac_interrupt(struct niu *np) 3992 { 3993 struct niu_bmac_stats *mp = &np->mac_stats.bmac; 3994 u64 val; 3995 3996 val = nr64_mac(BTXMAC_STATUS); 3997 if (val & BTXMAC_STATUS_UNDERRUN) 3998 mp->tx_underflow_errors++; 3999 if (val & BTXMAC_STATUS_MAX_PKT_ERR) 4000 mp->tx_max_pkt_size_errors++; 4001 if (val & BTXMAC_STATUS_BYTE_CNT_EXP) 4002 mp->tx_bytes += BTXMAC_BYTE_CNT_COUNT; 4003 if (val & BTXMAC_STATUS_FRAME_CNT_EXP) 4004 mp->tx_frames += BTXMAC_FRM_CNT_COUNT; 4005 4006 val = nr64_mac(BRXMAC_STATUS); 4007 if (val & BRXMAC_STATUS_OVERFLOW) 4008 mp->rx_overflows++; 4009 if (val & BRXMAC_STATUS_FRAME_CNT_EXP) 4010 mp->rx_frames += BRXMAC_FRAME_CNT_COUNT; 4011 if (val & BRXMAC_STATUS_ALIGN_ERR_EXP) 4012 mp->rx_align_errors += BRXMAC_ALIGN_ERR_CNT_COUNT; 4013 if (val & BRXMAC_STATUS_CRC_ERR_EXP) 4014 mp->rx_crc_errors += BRXMAC_ALIGN_ERR_CNT_COUNT; 4015 if (val & BRXMAC_STATUS_LEN_ERR_EXP) 4016 mp->rx_len_errors += BRXMAC_CODE_VIOL_ERR_CNT_COUNT; 4017 4018 val = nr64_mac(BMAC_CTRL_STATUS); 4019 if (val & BMAC_CTRL_STATUS_NOPAUSE) 4020 mp->pause_off_state++; 4021 if (val & BMAC_CTRL_STATUS_PAUSE) 4022 mp->pause_on_state++; 4023 if (val & BMAC_CTRL_STATUS_PAUSE_RECV) 4024 mp->pause_received++; 4025 } 4026 4027 static int niu_mac_interrupt(struct niu *np) 4028 { 4029 if (np->flags & NIU_FLAGS_XMAC) 4030 niu_xmac_interrupt(np); 4031 else 4032 niu_bmac_interrupt(np); 4033 4034 return 0; 4035 } 4036 4037 static void niu_log_device_error(struct niu *np, u64 stat) 4038 { 4039 netdev_err(np->dev, "Core device errors ( "); 4040 4041 if (stat & SYS_ERR_MASK_META2) 4042 pr_cont("META2 "); 4043 if (stat & SYS_ERR_MASK_META1) 4044 pr_cont("META1 "); 4045 if (stat & SYS_ERR_MASK_PEU) 4046 pr_cont("PEU "); 4047 if (stat & SYS_ERR_MASK_TXC) 4048 pr_cont("TXC "); 4049 if (stat & SYS_ERR_MASK_RDMC) 4050 pr_cont("RDMC "); 4051 if (stat & SYS_ERR_MASK_TDMC) 4052 pr_cont("TDMC "); 4053 if (stat & SYS_ERR_MASK_ZCP) 4054 pr_cont("ZCP "); 4055 if (stat & SYS_ERR_MASK_FFLP) 4056 pr_cont("FFLP "); 4057 if (stat & SYS_ERR_MASK_IPP) 4058 pr_cont("IPP "); 4059 if (stat & SYS_ERR_MASK_MAC) 4060 pr_cont("MAC "); 4061 if (stat & SYS_ERR_MASK_SMX) 4062 pr_cont("SMX "); 4063 4064 pr_cont(")\n"); 4065 } 4066 4067 static int niu_device_error(struct niu *np) 4068 { 4069 u64 stat = nr64(SYS_ERR_STAT); 4070 4071 netdev_err(np->dev, "Core device error, stat[%llx]\n", 4072 (unsigned long long)stat); 4073 4074 niu_log_device_error(np, stat); 4075 4076 return -ENODEV; 4077 } 4078 4079 static int niu_slowpath_interrupt(struct niu *np, struct niu_ldg *lp, 4080 u64 v0, u64 v1, u64 v2) 4081 { 4082 4083 int i, err = 0; 4084 4085 lp->v0 = v0; 4086 lp->v1 = v1; 4087 lp->v2 = v2; 4088 4089 if (v1 & 0x00000000ffffffffULL) { 4090 u32 rx_vec = (v1 & 0xffffffff); 4091 4092 for (i = 0; i < np->num_rx_rings; i++) { 4093 struct rx_ring_info *rp = &np->rx_rings[i]; 4094 4095 if (rx_vec & (1 << rp->rx_channel)) { 4096 int r = niu_rx_error(np, rp); 4097 if (r) { 4098 err = r; 4099 } else { 4100 if (!v0) 4101 nw64(RX_DMA_CTL_STAT(rp->rx_channel), 4102 RX_DMA_CTL_STAT_MEX); 4103 } 4104 } 4105 } 4106 } 4107 if (v1 & 0x7fffffff00000000ULL) { 4108 u32 tx_vec = (v1 >> 32) & 0x7fffffff; 4109 4110 for (i = 0; i < np->num_tx_rings; i++) { 4111 struct tx_ring_info *rp = &np->tx_rings[i]; 4112 4113 if (tx_vec & (1 << rp->tx_channel)) { 4114 int r = niu_tx_error(np, rp); 4115 if (r) 4116 err = r; 4117 } 4118 } 4119 } 4120 if ((v0 | v1) & 0x8000000000000000ULL) { 4121 int r = niu_mif_interrupt(np); 4122 if (r) 4123 err = r; 4124 } 4125 if (v2) { 4126 if (v2 & 0x01ef) { 4127 int r = niu_mac_interrupt(np); 4128 if (r) 4129 err = r; 4130 } 4131 if (v2 & 0x0210) { 4132 int r = niu_device_error(np); 4133 if (r) 4134 err = r; 4135 } 4136 } 4137 4138 if (err) 4139 niu_enable_interrupts(np, 0); 4140 4141 return err; 4142 } 4143 4144 static void niu_rxchan_intr(struct niu *np, struct rx_ring_info *rp, 4145 int ldn) 4146 { 4147 struct rxdma_mailbox *mbox = rp->mbox; 4148 u64 stat_write, stat = le64_to_cpup(&mbox->rx_dma_ctl_stat); 4149 4150 stat_write = (RX_DMA_CTL_STAT_RCRTHRES | 4151 RX_DMA_CTL_STAT_RCRTO); 4152 nw64(RX_DMA_CTL_STAT(rp->rx_channel), stat_write); 4153 4154 netif_printk(np, intr, KERN_DEBUG, np->dev, 4155 "%s() stat[%llx]\n", __func__, (unsigned long long)stat); 4156 } 4157 4158 static void niu_txchan_intr(struct niu *np, struct tx_ring_info *rp, 4159 int ldn) 4160 { 4161 rp->tx_cs = nr64(TX_CS(rp->tx_channel)); 4162 4163 netif_printk(np, intr, KERN_DEBUG, np->dev, 4164 "%s() cs[%llx]\n", __func__, (unsigned long long)rp->tx_cs); 4165 } 4166 4167 static void __niu_fastpath_interrupt(struct niu *np, int ldg, u64 v0) 4168 { 4169 struct niu_parent *parent = np->parent; 4170 u32 rx_vec, tx_vec; 4171 int i; 4172 4173 tx_vec = (v0 >> 32); 4174 rx_vec = (v0 & 0xffffffff); 4175 4176 for (i = 0; i < np->num_rx_rings; i++) { 4177 struct rx_ring_info *rp = &np->rx_rings[i]; 4178 int ldn = LDN_RXDMA(rp->rx_channel); 4179 4180 if (parent->ldg_map[ldn] != ldg) 4181 continue; 4182 4183 nw64(LD_IM0(ldn), LD_IM0_MASK); 4184 if (rx_vec & (1 << rp->rx_channel)) 4185 niu_rxchan_intr(np, rp, ldn); 4186 } 4187 4188 for (i = 0; i < np->num_tx_rings; i++) { 4189 struct tx_ring_info *rp = &np->tx_rings[i]; 4190 int ldn = LDN_TXDMA(rp->tx_channel); 4191 4192 if (parent->ldg_map[ldn] != ldg) 4193 continue; 4194 4195 nw64(LD_IM0(ldn), LD_IM0_MASK); 4196 if (tx_vec & (1 << rp->tx_channel)) 4197 niu_txchan_intr(np, rp, ldn); 4198 } 4199 } 4200 4201 static void niu_schedule_napi(struct niu *np, struct niu_ldg *lp, 4202 u64 v0, u64 v1, u64 v2) 4203 { 4204 if (likely(napi_schedule_prep(&lp->napi))) { 4205 lp->v0 = v0; 4206 lp->v1 = v1; 4207 lp->v2 = v2; 4208 __niu_fastpath_interrupt(np, lp->ldg_num, v0); 4209 __napi_schedule(&lp->napi); 4210 } 4211 } 4212 4213 static irqreturn_t niu_interrupt(int irq, void *dev_id) 4214 { 4215 struct niu_ldg *lp = dev_id; 4216 struct niu *np = lp->np; 4217 int ldg = lp->ldg_num; 4218 unsigned long flags; 4219 u64 v0, v1, v2; 4220 4221 if (netif_msg_intr(np)) 4222 printk(KERN_DEBUG KBUILD_MODNAME ": " "%s() ldg[%p](%d)", 4223 __func__, lp, ldg); 4224 4225 spin_lock_irqsave(&np->lock, flags); 4226 4227 v0 = nr64(LDSV0(ldg)); 4228 v1 = nr64(LDSV1(ldg)); 4229 v2 = nr64(LDSV2(ldg)); 4230 4231 if (netif_msg_intr(np)) 4232 pr_cont(" v0[%llx] v1[%llx] v2[%llx]\n", 4233 (unsigned long long) v0, 4234 (unsigned long long) v1, 4235 (unsigned long long) v2); 4236 4237 if (unlikely(!v0 && !v1 && !v2)) { 4238 spin_unlock_irqrestore(&np->lock, flags); 4239 return IRQ_NONE; 4240 } 4241 4242 if (unlikely((v0 & ((u64)1 << LDN_MIF)) || v1 || v2)) { 4243 int err = niu_slowpath_interrupt(np, lp, v0, v1, v2); 4244 if (err) 4245 goto out; 4246 } 4247 if (likely(v0 & ~((u64)1 << LDN_MIF))) 4248 niu_schedule_napi(np, lp, v0, v1, v2); 4249 else 4250 niu_ldg_rearm(np, lp, 1); 4251 out: 4252 spin_unlock_irqrestore(&np->lock, flags); 4253 4254 return IRQ_HANDLED; 4255 } 4256 4257 static void niu_free_rx_ring_info(struct niu *np, struct rx_ring_info *rp) 4258 { 4259 if (rp->mbox) { 4260 np->ops->free_coherent(np->device, 4261 sizeof(struct rxdma_mailbox), 4262 rp->mbox, rp->mbox_dma); 4263 rp->mbox = NULL; 4264 } 4265 if (rp->rcr) { 4266 np->ops->free_coherent(np->device, 4267 MAX_RCR_RING_SIZE * sizeof(__le64), 4268 rp->rcr, rp->rcr_dma); 4269 rp->rcr = NULL; 4270 rp->rcr_table_size = 0; 4271 rp->rcr_index = 0; 4272 } 4273 if (rp->rbr) { 4274 niu_rbr_free(np, rp); 4275 4276 np->ops->free_coherent(np->device, 4277 MAX_RBR_RING_SIZE * sizeof(__le32), 4278 rp->rbr, rp->rbr_dma); 4279 rp->rbr = NULL; 4280 rp->rbr_table_size = 0; 4281 rp->rbr_index = 0; 4282 } 4283 kfree(rp->rxhash); 4284 rp->rxhash = NULL; 4285 } 4286 4287 static void niu_free_tx_ring_info(struct niu *np, struct tx_ring_info *rp) 4288 { 4289 if (rp->mbox) { 4290 np->ops->free_coherent(np->device, 4291 sizeof(struct txdma_mailbox), 4292 rp->mbox, rp->mbox_dma); 4293 rp->mbox = NULL; 4294 } 4295 if (rp->descr) { 4296 int i; 4297 4298 for (i = 0; i < MAX_TX_RING_SIZE; i++) { 4299 if (rp->tx_buffs[i].skb) 4300 (void) release_tx_packet(np, rp, i); 4301 } 4302 4303 np->ops->free_coherent(np->device, 4304 MAX_TX_RING_SIZE * sizeof(__le64), 4305 rp->descr, rp->descr_dma); 4306 rp->descr = NULL; 4307 rp->pending = 0; 4308 rp->prod = 0; 4309 rp->cons = 0; 4310 rp->wrap_bit = 0; 4311 } 4312 } 4313 4314 static void niu_free_channels(struct niu *np) 4315 { 4316 int i; 4317 4318 if (np->rx_rings) { 4319 for (i = 0; i < np->num_rx_rings; i++) { 4320 struct rx_ring_info *rp = &np->rx_rings[i]; 4321 4322 niu_free_rx_ring_info(np, rp); 4323 } 4324 kfree(np->rx_rings); 4325 np->rx_rings = NULL; 4326 np->num_rx_rings = 0; 4327 } 4328 4329 if (np->tx_rings) { 4330 for (i = 0; i < np->num_tx_rings; i++) { 4331 struct tx_ring_info *rp = &np->tx_rings[i]; 4332 4333 niu_free_tx_ring_info(np, rp); 4334 } 4335 kfree(np->tx_rings); 4336 np->tx_rings = NULL; 4337 np->num_tx_rings = 0; 4338 } 4339 } 4340 4341 static int niu_alloc_rx_ring_info(struct niu *np, 4342 struct rx_ring_info *rp) 4343 { 4344 BUILD_BUG_ON(sizeof(struct rxdma_mailbox) != 64); 4345 4346 rp->rxhash = kcalloc(MAX_RBR_RING_SIZE, sizeof(struct page *), 4347 GFP_KERNEL); 4348 if (!rp->rxhash) 4349 return -ENOMEM; 4350 4351 rp->mbox = np->ops->alloc_coherent(np->device, 4352 sizeof(struct rxdma_mailbox), 4353 &rp->mbox_dma, GFP_KERNEL); 4354 if (!rp->mbox) 4355 return -ENOMEM; 4356 if ((unsigned long)rp->mbox & (64UL - 1)) { 4357 netdev_err(np->dev, "Coherent alloc gives misaligned RXDMA mailbox %p\n", 4358 rp->mbox); 4359 return -EINVAL; 4360 } 4361 4362 rp->rcr = np->ops->alloc_coherent(np->device, 4363 MAX_RCR_RING_SIZE * sizeof(__le64), 4364 &rp->rcr_dma, GFP_KERNEL); 4365 if (!rp->rcr) 4366 return -ENOMEM; 4367 if ((unsigned long)rp->rcr & (64UL - 1)) { 4368 netdev_err(np->dev, "Coherent alloc gives misaligned RXDMA RCR table %p\n", 4369 rp->rcr); 4370 return -EINVAL; 4371 } 4372 rp->rcr_table_size = MAX_RCR_RING_SIZE; 4373 rp->rcr_index = 0; 4374 4375 rp->rbr = np->ops->alloc_coherent(np->device, 4376 MAX_RBR_RING_SIZE * sizeof(__le32), 4377 &rp->rbr_dma, GFP_KERNEL); 4378 if (!rp->rbr) 4379 return -ENOMEM; 4380 if ((unsigned long)rp->rbr & (64UL - 1)) { 4381 netdev_err(np->dev, "Coherent alloc gives misaligned RXDMA RBR table %p\n", 4382 rp->rbr); 4383 return -EINVAL; 4384 } 4385 rp->rbr_table_size = MAX_RBR_RING_SIZE; 4386 rp->rbr_index = 0; 4387 rp->rbr_pending = 0; 4388 4389 return 0; 4390 } 4391 4392 static void niu_set_max_burst(struct niu *np, struct tx_ring_info *rp) 4393 { 4394 int mtu = np->dev->mtu; 4395 4396 /* These values are recommended by the HW designers for fair 4397 * utilization of DRR amongst the rings. 4398 */ 4399 rp->max_burst = mtu + 32; 4400 if (rp->max_burst > 4096) 4401 rp->max_burst = 4096; 4402 } 4403 4404 static int niu_alloc_tx_ring_info(struct niu *np, 4405 struct tx_ring_info *rp) 4406 { 4407 BUILD_BUG_ON(sizeof(struct txdma_mailbox) != 64); 4408 4409 rp->mbox = np->ops->alloc_coherent(np->device, 4410 sizeof(struct txdma_mailbox), 4411 &rp->mbox_dma, GFP_KERNEL); 4412 if (!rp->mbox) 4413 return -ENOMEM; 4414 if ((unsigned long)rp->mbox & (64UL - 1)) { 4415 netdev_err(np->dev, "Coherent alloc gives misaligned TXDMA mailbox %p\n", 4416 rp->mbox); 4417 return -EINVAL; 4418 } 4419 4420 rp->descr = np->ops->alloc_coherent(np->device, 4421 MAX_TX_RING_SIZE * sizeof(__le64), 4422 &rp->descr_dma, GFP_KERNEL); 4423 if (!rp->descr) 4424 return -ENOMEM; 4425 if ((unsigned long)rp->descr & (64UL - 1)) { 4426 netdev_err(np->dev, "Coherent alloc gives misaligned TXDMA descr table %p\n", 4427 rp->descr); 4428 return -EINVAL; 4429 } 4430 4431 rp->pending = MAX_TX_RING_SIZE; 4432 rp->prod = 0; 4433 rp->cons = 0; 4434 rp->wrap_bit = 0; 4435 4436 /* XXX make these configurable... XXX */ 4437 rp->mark_freq = rp->pending / 4; 4438 4439 niu_set_max_burst(np, rp); 4440 4441 return 0; 4442 } 4443 4444 static void niu_size_rbr(struct niu *np, struct rx_ring_info *rp) 4445 { 4446 u16 bss; 4447 4448 bss = min(PAGE_SHIFT, 15); 4449 4450 rp->rbr_block_size = 1 << bss; 4451 rp->rbr_blocks_per_page = 1 << (PAGE_SHIFT-bss); 4452 4453 rp->rbr_sizes[0] = 256; 4454 rp->rbr_sizes[1] = 1024; 4455 if (np->dev->mtu > ETH_DATA_LEN) { 4456 switch (PAGE_SIZE) { 4457 case 4 * 1024: 4458 rp->rbr_sizes[2] = 4096; 4459 break; 4460 4461 default: 4462 rp->rbr_sizes[2] = 8192; 4463 break; 4464 } 4465 } else { 4466 rp->rbr_sizes[2] = 2048; 4467 } 4468 rp->rbr_sizes[3] = rp->rbr_block_size; 4469 } 4470 4471 static int niu_alloc_channels(struct niu *np) 4472 { 4473 struct niu_parent *parent = np->parent; 4474 int first_rx_channel, first_tx_channel; 4475 int num_rx_rings, num_tx_rings; 4476 struct rx_ring_info *rx_rings; 4477 struct tx_ring_info *tx_rings; 4478 int i, port, err; 4479 4480 port = np->port; 4481 first_rx_channel = first_tx_channel = 0; 4482 for (i = 0; i < port; i++) { 4483 first_rx_channel += parent->rxchan_per_port[i]; 4484 first_tx_channel += parent->txchan_per_port[i]; 4485 } 4486 4487 num_rx_rings = parent->rxchan_per_port[port]; 4488 num_tx_rings = parent->txchan_per_port[port]; 4489 4490 rx_rings = kcalloc(num_rx_rings, sizeof(struct rx_ring_info), 4491 GFP_KERNEL); 4492 err = -ENOMEM; 4493 if (!rx_rings) 4494 goto out_err; 4495 4496 np->num_rx_rings = num_rx_rings; 4497 smp_wmb(); 4498 np->rx_rings = rx_rings; 4499 4500 netif_set_real_num_rx_queues(np->dev, num_rx_rings); 4501 4502 for (i = 0; i < np->num_rx_rings; i++) { 4503 struct rx_ring_info *rp = &np->rx_rings[i]; 4504 4505 rp->np = np; 4506 rp->rx_channel = first_rx_channel + i; 4507 4508 err = niu_alloc_rx_ring_info(np, rp); 4509 if (err) 4510 goto out_err; 4511 4512 niu_size_rbr(np, rp); 4513 4514 /* XXX better defaults, configurable, etc... XXX */ 4515 rp->nonsyn_window = 64; 4516 rp->nonsyn_threshold = rp->rcr_table_size - 64; 4517 rp->syn_window = 64; 4518 rp->syn_threshold = rp->rcr_table_size - 64; 4519 rp->rcr_pkt_threshold = 16; 4520 rp->rcr_timeout = 8; 4521 rp->rbr_kick_thresh = RBR_REFILL_MIN; 4522 if (rp->rbr_kick_thresh < rp->rbr_blocks_per_page) 4523 rp->rbr_kick_thresh = rp->rbr_blocks_per_page; 4524 4525 err = niu_rbr_fill(np, rp, GFP_KERNEL); 4526 if (err) 4527 return err; 4528 } 4529 4530 tx_rings = kcalloc(num_tx_rings, sizeof(struct tx_ring_info), 4531 GFP_KERNEL); 4532 err = -ENOMEM; 4533 if (!tx_rings) 4534 goto out_err; 4535 4536 np->num_tx_rings = num_tx_rings; 4537 smp_wmb(); 4538 np->tx_rings = tx_rings; 4539 4540 netif_set_real_num_tx_queues(np->dev, num_tx_rings); 4541 4542 for (i = 0; i < np->num_tx_rings; i++) { 4543 struct tx_ring_info *rp = &np->tx_rings[i]; 4544 4545 rp->np = np; 4546 rp->tx_channel = first_tx_channel + i; 4547 4548 err = niu_alloc_tx_ring_info(np, rp); 4549 if (err) 4550 goto out_err; 4551 } 4552 4553 return 0; 4554 4555 out_err: 4556 niu_free_channels(np); 4557 return err; 4558 } 4559 4560 static int niu_tx_cs_sng_poll(struct niu *np, int channel) 4561 { 4562 int limit = 1000; 4563 4564 while (--limit > 0) { 4565 u64 val = nr64(TX_CS(channel)); 4566 if (val & TX_CS_SNG_STATE) 4567 return 0; 4568 } 4569 return -ENODEV; 4570 } 4571 4572 static int niu_tx_channel_stop(struct niu *np, int channel) 4573 { 4574 u64 val = nr64(TX_CS(channel)); 4575 4576 val |= TX_CS_STOP_N_GO; 4577 nw64(TX_CS(channel), val); 4578 4579 return niu_tx_cs_sng_poll(np, channel); 4580 } 4581 4582 static int niu_tx_cs_reset_poll(struct niu *np, int channel) 4583 { 4584 int limit = 1000; 4585 4586 while (--limit > 0) { 4587 u64 val = nr64(TX_CS(channel)); 4588 if (!(val & TX_CS_RST)) 4589 return 0; 4590 } 4591 return -ENODEV; 4592 } 4593 4594 static int niu_tx_channel_reset(struct niu *np, int channel) 4595 { 4596 u64 val = nr64(TX_CS(channel)); 4597 int err; 4598 4599 val |= TX_CS_RST; 4600 nw64(TX_CS(channel), val); 4601 4602 err = niu_tx_cs_reset_poll(np, channel); 4603 if (!err) 4604 nw64(TX_RING_KICK(channel), 0); 4605 4606 return err; 4607 } 4608 4609 static int niu_tx_channel_lpage_init(struct niu *np, int channel) 4610 { 4611 u64 val; 4612 4613 nw64(TX_LOG_MASK1(channel), 0); 4614 nw64(TX_LOG_VAL1(channel), 0); 4615 nw64(TX_LOG_MASK2(channel), 0); 4616 nw64(TX_LOG_VAL2(channel), 0); 4617 nw64(TX_LOG_PAGE_RELO1(channel), 0); 4618 nw64(TX_LOG_PAGE_RELO2(channel), 0); 4619 nw64(TX_LOG_PAGE_HDL(channel), 0); 4620 4621 val = (u64)np->port << TX_LOG_PAGE_VLD_FUNC_SHIFT; 4622 val |= (TX_LOG_PAGE_VLD_PAGE0 | TX_LOG_PAGE_VLD_PAGE1); 4623 nw64(TX_LOG_PAGE_VLD(channel), val); 4624 4625 /* XXX TXDMA 32bit mode? XXX */ 4626 4627 return 0; 4628 } 4629 4630 static void niu_txc_enable_port(struct niu *np, int on) 4631 { 4632 unsigned long flags; 4633 u64 val, mask; 4634 4635 niu_lock_parent(np, flags); 4636 val = nr64(TXC_CONTROL); 4637 mask = (u64)1 << np->port; 4638 if (on) { 4639 val |= TXC_CONTROL_ENABLE | mask; 4640 } else { 4641 val &= ~mask; 4642 if ((val & ~TXC_CONTROL_ENABLE) == 0) 4643 val &= ~TXC_CONTROL_ENABLE; 4644 } 4645 nw64(TXC_CONTROL, val); 4646 niu_unlock_parent(np, flags); 4647 } 4648 4649 static void niu_txc_set_imask(struct niu *np, u64 imask) 4650 { 4651 unsigned long flags; 4652 u64 val; 4653 4654 niu_lock_parent(np, flags); 4655 val = nr64(TXC_INT_MASK); 4656 val &= ~TXC_INT_MASK_VAL(np->port); 4657 val |= (imask << TXC_INT_MASK_VAL_SHIFT(np->port)); 4658 niu_unlock_parent(np, flags); 4659 } 4660 4661 static void niu_txc_port_dma_enable(struct niu *np, int on) 4662 { 4663 u64 val = 0; 4664 4665 if (on) { 4666 int i; 4667 4668 for (i = 0; i < np->num_tx_rings; i++) 4669 val |= (1 << np->tx_rings[i].tx_channel); 4670 } 4671 nw64(TXC_PORT_DMA(np->port), val); 4672 } 4673 4674 static int niu_init_one_tx_channel(struct niu *np, struct tx_ring_info *rp) 4675 { 4676 int err, channel = rp->tx_channel; 4677 u64 val, ring_len; 4678 4679 err = niu_tx_channel_stop(np, channel); 4680 if (err) 4681 return err; 4682 4683 err = niu_tx_channel_reset(np, channel); 4684 if (err) 4685 return err; 4686 4687 err = niu_tx_channel_lpage_init(np, channel); 4688 if (err) 4689 return err; 4690 4691 nw64(TXC_DMA_MAX(channel), rp->max_burst); 4692 nw64(TX_ENT_MSK(channel), 0); 4693 4694 if (rp->descr_dma & ~(TX_RNG_CFIG_STADDR_BASE | 4695 TX_RNG_CFIG_STADDR)) { 4696 netdev_err(np->dev, "TX ring channel %d DMA addr (%llx) is not aligned\n", 4697 channel, (unsigned long long)rp->descr_dma); 4698 return -EINVAL; 4699 } 4700 4701 /* The length field in TX_RNG_CFIG is measured in 64-byte 4702 * blocks. rp->pending is the number of TX descriptors in 4703 * our ring, 8 bytes each, thus we divide by 8 bytes more 4704 * to get the proper value the chip wants. 4705 */ 4706 ring_len = (rp->pending / 8); 4707 4708 val = ((ring_len << TX_RNG_CFIG_LEN_SHIFT) | 4709 rp->descr_dma); 4710 nw64(TX_RNG_CFIG(channel), val); 4711 4712 if (((rp->mbox_dma >> 32) & ~TXDMA_MBH_MBADDR) || 4713 ((u32)rp->mbox_dma & ~TXDMA_MBL_MBADDR)) { 4714 netdev_err(np->dev, "TX ring channel %d MBOX addr (%llx) has invalid bits\n", 4715 channel, (unsigned long long)rp->mbox_dma); 4716 return -EINVAL; 4717 } 4718 nw64(TXDMA_MBH(channel), rp->mbox_dma >> 32); 4719 nw64(TXDMA_MBL(channel), rp->mbox_dma & TXDMA_MBL_MBADDR); 4720 4721 nw64(TX_CS(channel), 0); 4722 4723 rp->last_pkt_cnt = 0; 4724 4725 return 0; 4726 } 4727 4728 static void niu_init_rdc_groups(struct niu *np) 4729 { 4730 struct niu_rdc_tables *tp = &np->parent->rdc_group_cfg[np->port]; 4731 int i, first_table_num = tp->first_table_num; 4732 4733 for (i = 0; i < tp->num_tables; i++) { 4734 struct rdc_table *tbl = &tp->tables[i]; 4735 int this_table = first_table_num + i; 4736 int slot; 4737 4738 for (slot = 0; slot < NIU_RDC_TABLE_SLOTS; slot++) 4739 nw64(RDC_TBL(this_table, slot), 4740 tbl->rxdma_channel[slot]); 4741 } 4742 4743 nw64(DEF_RDC(np->port), np->parent->rdc_default[np->port]); 4744 } 4745 4746 static void niu_init_drr_weight(struct niu *np) 4747 { 4748 int type = phy_decode(np->parent->port_phy, np->port); 4749 u64 val; 4750 4751 switch (type) { 4752 case PORT_TYPE_10G: 4753 val = PT_DRR_WEIGHT_DEFAULT_10G; 4754 break; 4755 4756 case PORT_TYPE_1G: 4757 default: 4758 val = PT_DRR_WEIGHT_DEFAULT_1G; 4759 break; 4760 } 4761 nw64(PT_DRR_WT(np->port), val); 4762 } 4763 4764 static int niu_init_hostinfo(struct niu *np) 4765 { 4766 struct niu_parent *parent = np->parent; 4767 struct niu_rdc_tables *tp = &parent->rdc_group_cfg[np->port]; 4768 int i, err, num_alt = niu_num_alt_addr(np); 4769 int first_rdc_table = tp->first_table_num; 4770 4771 err = niu_set_primary_mac_rdc_table(np, first_rdc_table, 1); 4772 if (err) 4773 return err; 4774 4775 err = niu_set_multicast_mac_rdc_table(np, first_rdc_table, 1); 4776 if (err) 4777 return err; 4778 4779 for (i = 0; i < num_alt; i++) { 4780 err = niu_set_alt_mac_rdc_table(np, i, first_rdc_table, 1); 4781 if (err) 4782 return err; 4783 } 4784 4785 return 0; 4786 } 4787 4788 static int niu_rx_channel_reset(struct niu *np, int channel) 4789 { 4790 return niu_set_and_wait_clear(np, RXDMA_CFIG1(channel), 4791 RXDMA_CFIG1_RST, 1000, 10, 4792 "RXDMA_CFIG1"); 4793 } 4794 4795 static int niu_rx_channel_lpage_init(struct niu *np, int channel) 4796 { 4797 u64 val; 4798 4799 nw64(RX_LOG_MASK1(channel), 0); 4800 nw64(RX_LOG_VAL1(channel), 0); 4801 nw64(RX_LOG_MASK2(channel), 0); 4802 nw64(RX_LOG_VAL2(channel), 0); 4803 nw64(RX_LOG_PAGE_RELO1(channel), 0); 4804 nw64(RX_LOG_PAGE_RELO2(channel), 0); 4805 nw64(RX_LOG_PAGE_HDL(channel), 0); 4806 4807 val = (u64)np->port << RX_LOG_PAGE_VLD_FUNC_SHIFT; 4808 val |= (RX_LOG_PAGE_VLD_PAGE0 | RX_LOG_PAGE_VLD_PAGE1); 4809 nw64(RX_LOG_PAGE_VLD(channel), val); 4810 4811 return 0; 4812 } 4813 4814 static void niu_rx_channel_wred_init(struct niu *np, struct rx_ring_info *rp) 4815 { 4816 u64 val; 4817 4818 val = (((u64)rp->nonsyn_window << RDC_RED_PARA_WIN_SHIFT) | 4819 ((u64)rp->nonsyn_threshold << RDC_RED_PARA_THRE_SHIFT) | 4820 ((u64)rp->syn_window << RDC_RED_PARA_WIN_SYN_SHIFT) | 4821 ((u64)rp->syn_threshold << RDC_RED_PARA_THRE_SYN_SHIFT)); 4822 nw64(RDC_RED_PARA(rp->rx_channel), val); 4823 } 4824 4825 static int niu_compute_rbr_cfig_b(struct rx_ring_info *rp, u64 *ret) 4826 { 4827 u64 val = 0; 4828 4829 *ret = 0; 4830 switch (rp->rbr_block_size) { 4831 case 4 * 1024: 4832 val |= (RBR_BLKSIZE_4K << RBR_CFIG_B_BLKSIZE_SHIFT); 4833 break; 4834 case 8 * 1024: 4835 val |= (RBR_BLKSIZE_8K << RBR_CFIG_B_BLKSIZE_SHIFT); 4836 break; 4837 case 16 * 1024: 4838 val |= (RBR_BLKSIZE_16K << RBR_CFIG_B_BLKSIZE_SHIFT); 4839 break; 4840 case 32 * 1024: 4841 val |= (RBR_BLKSIZE_32K << RBR_CFIG_B_BLKSIZE_SHIFT); 4842 break; 4843 default: 4844 return -EINVAL; 4845 } 4846 val |= RBR_CFIG_B_VLD2; 4847 switch (rp->rbr_sizes[2]) { 4848 case 2 * 1024: 4849 val |= (RBR_BUFSZ2_2K << RBR_CFIG_B_BUFSZ2_SHIFT); 4850 break; 4851 case 4 * 1024: 4852 val |= (RBR_BUFSZ2_4K << RBR_CFIG_B_BUFSZ2_SHIFT); 4853 break; 4854 case 8 * 1024: 4855 val |= (RBR_BUFSZ2_8K << RBR_CFIG_B_BUFSZ2_SHIFT); 4856 break; 4857 case 16 * 1024: 4858 val |= (RBR_BUFSZ2_16K << RBR_CFIG_B_BUFSZ2_SHIFT); 4859 break; 4860 4861 default: 4862 return -EINVAL; 4863 } 4864 val |= RBR_CFIG_B_VLD1; 4865 switch (rp->rbr_sizes[1]) { 4866 case 1 * 1024: 4867 val |= (RBR_BUFSZ1_1K << RBR_CFIG_B_BUFSZ1_SHIFT); 4868 break; 4869 case 2 * 1024: 4870 val |= (RBR_BUFSZ1_2K << RBR_CFIG_B_BUFSZ1_SHIFT); 4871 break; 4872 case 4 * 1024: 4873 val |= (RBR_BUFSZ1_4K << RBR_CFIG_B_BUFSZ1_SHIFT); 4874 break; 4875 case 8 * 1024: 4876 val |= (RBR_BUFSZ1_8K << RBR_CFIG_B_BUFSZ1_SHIFT); 4877 break; 4878 4879 default: 4880 return -EINVAL; 4881 } 4882 val |= RBR_CFIG_B_VLD0; 4883 switch (rp->rbr_sizes[0]) { 4884 case 256: 4885 val |= (RBR_BUFSZ0_256 << RBR_CFIG_B_BUFSZ0_SHIFT); 4886 break; 4887 case 512: 4888 val |= (RBR_BUFSZ0_512 << RBR_CFIG_B_BUFSZ0_SHIFT); 4889 break; 4890 case 1 * 1024: 4891 val |= (RBR_BUFSZ0_1K << RBR_CFIG_B_BUFSZ0_SHIFT); 4892 break; 4893 case 2 * 1024: 4894 val |= (RBR_BUFSZ0_2K << RBR_CFIG_B_BUFSZ0_SHIFT); 4895 break; 4896 4897 default: 4898 return -EINVAL; 4899 } 4900 4901 *ret = val; 4902 return 0; 4903 } 4904 4905 static int niu_enable_rx_channel(struct niu *np, int channel, int on) 4906 { 4907 u64 val = nr64(RXDMA_CFIG1(channel)); 4908 int limit; 4909 4910 if (on) 4911 val |= RXDMA_CFIG1_EN; 4912 else 4913 val &= ~RXDMA_CFIG1_EN; 4914 nw64(RXDMA_CFIG1(channel), val); 4915 4916 limit = 1000; 4917 while (--limit > 0) { 4918 if (nr64(RXDMA_CFIG1(channel)) & RXDMA_CFIG1_QST) 4919 break; 4920 udelay(10); 4921 } 4922 if (limit <= 0) 4923 return -ENODEV; 4924 return 0; 4925 } 4926 4927 static int niu_init_one_rx_channel(struct niu *np, struct rx_ring_info *rp) 4928 { 4929 int err, channel = rp->rx_channel; 4930 u64 val; 4931 4932 err = niu_rx_channel_reset(np, channel); 4933 if (err) 4934 return err; 4935 4936 err = niu_rx_channel_lpage_init(np, channel); 4937 if (err) 4938 return err; 4939 4940 niu_rx_channel_wred_init(np, rp); 4941 4942 nw64(RX_DMA_ENT_MSK(channel), RX_DMA_ENT_MSK_RBR_EMPTY); 4943 nw64(RX_DMA_CTL_STAT(channel), 4944 (RX_DMA_CTL_STAT_MEX | 4945 RX_DMA_CTL_STAT_RCRTHRES | 4946 RX_DMA_CTL_STAT_RCRTO | 4947 RX_DMA_CTL_STAT_RBR_EMPTY)); 4948 nw64(RXDMA_CFIG1(channel), rp->mbox_dma >> 32); 4949 nw64(RXDMA_CFIG2(channel), 4950 ((rp->mbox_dma & RXDMA_CFIG2_MBADDR_L) | 4951 RXDMA_CFIG2_FULL_HDR)); 4952 nw64(RBR_CFIG_A(channel), 4953 ((u64)rp->rbr_table_size << RBR_CFIG_A_LEN_SHIFT) | 4954 (rp->rbr_dma & (RBR_CFIG_A_STADDR_BASE | RBR_CFIG_A_STADDR))); 4955 err = niu_compute_rbr_cfig_b(rp, &val); 4956 if (err) 4957 return err; 4958 nw64(RBR_CFIG_B(channel), val); 4959 nw64(RCRCFIG_A(channel), 4960 ((u64)rp->rcr_table_size << RCRCFIG_A_LEN_SHIFT) | 4961 (rp->rcr_dma & (RCRCFIG_A_STADDR_BASE | RCRCFIG_A_STADDR))); 4962 nw64(RCRCFIG_B(channel), 4963 ((u64)rp->rcr_pkt_threshold << RCRCFIG_B_PTHRES_SHIFT) | 4964 RCRCFIG_B_ENTOUT | 4965 ((u64)rp->rcr_timeout << RCRCFIG_B_TIMEOUT_SHIFT)); 4966 4967 err = niu_enable_rx_channel(np, channel, 1); 4968 if (err) 4969 return err; 4970 4971 nw64(RBR_KICK(channel), rp->rbr_index); 4972 4973 val = nr64(RX_DMA_CTL_STAT(channel)); 4974 val |= RX_DMA_CTL_STAT_RBR_EMPTY; 4975 nw64(RX_DMA_CTL_STAT(channel), val); 4976 4977 return 0; 4978 } 4979 4980 static int niu_init_rx_channels(struct niu *np) 4981 { 4982 unsigned long flags; 4983 u64 seed = jiffies_64; 4984 int err, i; 4985 4986 niu_lock_parent(np, flags); 4987 nw64(RX_DMA_CK_DIV, np->parent->rxdma_clock_divider); 4988 nw64(RED_RAN_INIT, RED_RAN_INIT_OPMODE | (seed & RED_RAN_INIT_VAL)); 4989 niu_unlock_parent(np, flags); 4990 4991 /* XXX RXDMA 32bit mode? XXX */ 4992 4993 niu_init_rdc_groups(np); 4994 niu_init_drr_weight(np); 4995 4996 err = niu_init_hostinfo(np); 4997 if (err) 4998 return err; 4999 5000 for (i = 0; i < np->num_rx_rings; i++) { 5001 struct rx_ring_info *rp = &np->rx_rings[i]; 5002 5003 err = niu_init_one_rx_channel(np, rp); 5004 if (err) 5005 return err; 5006 } 5007 5008 return 0; 5009 } 5010 5011 static int niu_set_ip_frag_rule(struct niu *np) 5012 { 5013 struct niu_parent *parent = np->parent; 5014 struct niu_classifier *cp = &np->clas; 5015 struct niu_tcam_entry *tp; 5016 int index, err; 5017 5018 index = cp->tcam_top; 5019 tp = &parent->tcam[index]; 5020 5021 /* Note that the noport bit is the same in both ipv4 and 5022 * ipv6 format TCAM entries. 5023 */ 5024 memset(tp, 0, sizeof(*tp)); 5025 tp->key[1] = TCAM_V4KEY1_NOPORT; 5026 tp->key_mask[1] = TCAM_V4KEY1_NOPORT; 5027 tp->assoc_data = (TCAM_ASSOCDATA_TRES_USE_OFFSET | 5028 ((u64)0 << TCAM_ASSOCDATA_OFFSET_SHIFT)); 5029 err = tcam_write(np, index, tp->key, tp->key_mask); 5030 if (err) 5031 return err; 5032 err = tcam_assoc_write(np, index, tp->assoc_data); 5033 if (err) 5034 return err; 5035 tp->valid = 1; 5036 cp->tcam_valid_entries++; 5037 5038 return 0; 5039 } 5040 5041 static int niu_init_classifier_hw(struct niu *np) 5042 { 5043 struct niu_parent *parent = np->parent; 5044 struct niu_classifier *cp = &np->clas; 5045 int i, err; 5046 5047 nw64(H1POLY, cp->h1_init); 5048 nw64(H2POLY, cp->h2_init); 5049 5050 err = niu_init_hostinfo(np); 5051 if (err) 5052 return err; 5053 5054 for (i = 0; i < ENET_VLAN_TBL_NUM_ENTRIES; i++) { 5055 struct niu_vlan_rdc *vp = &cp->vlan_mappings[i]; 5056 5057 vlan_tbl_write(np, i, np->port, 5058 vp->vlan_pref, vp->rdc_num); 5059 } 5060 5061 for (i = 0; i < cp->num_alt_mac_mappings; i++) { 5062 struct niu_altmac_rdc *ap = &cp->alt_mac_mappings[i]; 5063 5064 err = niu_set_alt_mac_rdc_table(np, ap->alt_mac_num, 5065 ap->rdc_num, ap->mac_pref); 5066 if (err) 5067 return err; 5068 } 5069 5070 for (i = CLASS_CODE_USER_PROG1; i <= CLASS_CODE_SCTP_IPV6; i++) { 5071 int index = i - CLASS_CODE_USER_PROG1; 5072 5073 err = niu_set_tcam_key(np, i, parent->tcam_key[index]); 5074 if (err) 5075 return err; 5076 err = niu_set_flow_key(np, i, parent->flow_key[index]); 5077 if (err) 5078 return err; 5079 } 5080 5081 err = niu_set_ip_frag_rule(np); 5082 if (err) 5083 return err; 5084 5085 tcam_enable(np, 1); 5086 5087 return 0; 5088 } 5089 5090 static int niu_zcp_write(struct niu *np, int index, u64 *data) 5091 { 5092 nw64(ZCP_RAM_DATA0, data[0]); 5093 nw64(ZCP_RAM_DATA1, data[1]); 5094 nw64(ZCP_RAM_DATA2, data[2]); 5095 nw64(ZCP_RAM_DATA3, data[3]); 5096 nw64(ZCP_RAM_DATA4, data[4]); 5097 nw64(ZCP_RAM_BE, ZCP_RAM_BE_VAL); 5098 nw64(ZCP_RAM_ACC, 5099 (ZCP_RAM_ACC_WRITE | 5100 (0 << ZCP_RAM_ACC_ZFCID_SHIFT) | 5101 (ZCP_RAM_SEL_CFIFO(np->port) << ZCP_RAM_ACC_RAM_SEL_SHIFT))); 5102 5103 return niu_wait_bits_clear(np, ZCP_RAM_ACC, ZCP_RAM_ACC_BUSY, 5104 1000, 100); 5105 } 5106 5107 static int niu_zcp_read(struct niu *np, int index, u64 *data) 5108 { 5109 int err; 5110 5111 err = niu_wait_bits_clear(np, ZCP_RAM_ACC, ZCP_RAM_ACC_BUSY, 5112 1000, 100); 5113 if (err) { 5114 netdev_err(np->dev, "ZCP read busy won't clear, ZCP_RAM_ACC[%llx]\n", 5115 (unsigned long long)nr64(ZCP_RAM_ACC)); 5116 return err; 5117 } 5118 5119 nw64(ZCP_RAM_ACC, 5120 (ZCP_RAM_ACC_READ | 5121 (0 << ZCP_RAM_ACC_ZFCID_SHIFT) | 5122 (ZCP_RAM_SEL_CFIFO(np->port) << ZCP_RAM_ACC_RAM_SEL_SHIFT))); 5123 5124 err = niu_wait_bits_clear(np, ZCP_RAM_ACC, ZCP_RAM_ACC_BUSY, 5125 1000, 100); 5126 if (err) { 5127 netdev_err(np->dev, "ZCP read busy2 won't clear, ZCP_RAM_ACC[%llx]\n", 5128 (unsigned long long)nr64(ZCP_RAM_ACC)); 5129 return err; 5130 } 5131 5132 data[0] = nr64(ZCP_RAM_DATA0); 5133 data[1] = nr64(ZCP_RAM_DATA1); 5134 data[2] = nr64(ZCP_RAM_DATA2); 5135 data[3] = nr64(ZCP_RAM_DATA3); 5136 data[4] = nr64(ZCP_RAM_DATA4); 5137 5138 return 0; 5139 } 5140 5141 static void niu_zcp_cfifo_reset(struct niu *np) 5142 { 5143 u64 val = nr64(RESET_CFIFO); 5144 5145 val |= RESET_CFIFO_RST(np->port); 5146 nw64(RESET_CFIFO, val); 5147 udelay(10); 5148 5149 val &= ~RESET_CFIFO_RST(np->port); 5150 nw64(RESET_CFIFO, val); 5151 } 5152 5153 static int niu_init_zcp(struct niu *np) 5154 { 5155 u64 data[5], rbuf[5]; 5156 int i, max, err; 5157 5158 if (np->parent->plat_type != PLAT_TYPE_NIU) { 5159 if (np->port == 0 || np->port == 1) 5160 max = ATLAS_P0_P1_CFIFO_ENTRIES; 5161 else 5162 max = ATLAS_P2_P3_CFIFO_ENTRIES; 5163 } else 5164 max = NIU_CFIFO_ENTRIES; 5165 5166 data[0] = 0; 5167 data[1] = 0; 5168 data[2] = 0; 5169 data[3] = 0; 5170 data[4] = 0; 5171 5172 for (i = 0; i < max; i++) { 5173 err = niu_zcp_write(np, i, data); 5174 if (err) 5175 return err; 5176 err = niu_zcp_read(np, i, rbuf); 5177 if (err) 5178 return err; 5179 } 5180 5181 niu_zcp_cfifo_reset(np); 5182 nw64(CFIFO_ECC(np->port), 0); 5183 nw64(ZCP_INT_STAT, ZCP_INT_STAT_ALL); 5184 (void) nr64(ZCP_INT_STAT); 5185 nw64(ZCP_INT_MASK, ZCP_INT_MASK_ALL); 5186 5187 return 0; 5188 } 5189 5190 static void niu_ipp_write(struct niu *np, int index, u64 *data) 5191 { 5192 u64 val = nr64_ipp(IPP_CFIG); 5193 5194 nw64_ipp(IPP_CFIG, val | IPP_CFIG_DFIFO_PIO_W); 5195 nw64_ipp(IPP_DFIFO_WR_PTR, index); 5196 nw64_ipp(IPP_DFIFO_WR0, data[0]); 5197 nw64_ipp(IPP_DFIFO_WR1, data[1]); 5198 nw64_ipp(IPP_DFIFO_WR2, data[2]); 5199 nw64_ipp(IPP_DFIFO_WR3, data[3]); 5200 nw64_ipp(IPP_DFIFO_WR4, data[4]); 5201 nw64_ipp(IPP_CFIG, val & ~IPP_CFIG_DFIFO_PIO_W); 5202 } 5203 5204 static void niu_ipp_read(struct niu *np, int index, u64 *data) 5205 { 5206 nw64_ipp(IPP_DFIFO_RD_PTR, index); 5207 data[0] = nr64_ipp(IPP_DFIFO_RD0); 5208 data[1] = nr64_ipp(IPP_DFIFO_RD1); 5209 data[2] = nr64_ipp(IPP_DFIFO_RD2); 5210 data[3] = nr64_ipp(IPP_DFIFO_RD3); 5211 data[4] = nr64_ipp(IPP_DFIFO_RD4); 5212 } 5213 5214 static int niu_ipp_reset(struct niu *np) 5215 { 5216 return niu_set_and_wait_clear_ipp(np, IPP_CFIG, IPP_CFIG_SOFT_RST, 5217 1000, 100, "IPP_CFIG"); 5218 } 5219 5220 static int niu_init_ipp(struct niu *np) 5221 { 5222 u64 data[5], rbuf[5], val; 5223 int i, max, err; 5224 5225 if (np->parent->plat_type != PLAT_TYPE_NIU) { 5226 if (np->port == 0 || np->port == 1) 5227 max = ATLAS_P0_P1_DFIFO_ENTRIES; 5228 else 5229 max = ATLAS_P2_P3_DFIFO_ENTRIES; 5230 } else 5231 max = NIU_DFIFO_ENTRIES; 5232 5233 data[0] = 0; 5234 data[1] = 0; 5235 data[2] = 0; 5236 data[3] = 0; 5237 data[4] = 0; 5238 5239 for (i = 0; i < max; i++) { 5240 niu_ipp_write(np, i, data); 5241 niu_ipp_read(np, i, rbuf); 5242 } 5243 5244 (void) nr64_ipp(IPP_INT_STAT); 5245 (void) nr64_ipp(IPP_INT_STAT); 5246 5247 err = niu_ipp_reset(np); 5248 if (err) 5249 return err; 5250 5251 (void) nr64_ipp(IPP_PKT_DIS); 5252 (void) nr64_ipp(IPP_BAD_CS_CNT); 5253 (void) nr64_ipp(IPP_ECC); 5254 5255 (void) nr64_ipp(IPP_INT_STAT); 5256 5257 nw64_ipp(IPP_MSK, ~IPP_MSK_ALL); 5258 5259 val = nr64_ipp(IPP_CFIG); 5260 val &= ~IPP_CFIG_IP_MAX_PKT; 5261 val |= (IPP_CFIG_IPP_ENABLE | 5262 IPP_CFIG_DFIFO_ECC_EN | 5263 IPP_CFIG_DROP_BAD_CRC | 5264 IPP_CFIG_CKSUM_EN | 5265 (0x1ffff << IPP_CFIG_IP_MAX_PKT_SHIFT)); 5266 nw64_ipp(IPP_CFIG, val); 5267 5268 return 0; 5269 } 5270 5271 static void niu_handle_led(struct niu *np, int status) 5272 { 5273 u64 val; 5274 val = nr64_mac(XMAC_CONFIG); 5275 5276 if ((np->flags & NIU_FLAGS_10G) != 0 && 5277 (np->flags & NIU_FLAGS_FIBER) != 0) { 5278 if (status) { 5279 val |= XMAC_CONFIG_LED_POLARITY; 5280 val &= ~XMAC_CONFIG_FORCE_LED_ON; 5281 } else { 5282 val |= XMAC_CONFIG_FORCE_LED_ON; 5283 val &= ~XMAC_CONFIG_LED_POLARITY; 5284 } 5285 } 5286 5287 nw64_mac(XMAC_CONFIG, val); 5288 } 5289 5290 static void niu_init_xif_xmac(struct niu *np) 5291 { 5292 struct niu_link_config *lp = &np->link_config; 5293 u64 val; 5294 5295 if (np->flags & NIU_FLAGS_XCVR_SERDES) { 5296 val = nr64(MIF_CONFIG); 5297 val |= MIF_CONFIG_ATCA_GE; 5298 nw64(MIF_CONFIG, val); 5299 } 5300 5301 val = nr64_mac(XMAC_CONFIG); 5302 val &= ~XMAC_CONFIG_SEL_POR_CLK_SRC; 5303 5304 val |= XMAC_CONFIG_TX_OUTPUT_EN; 5305 5306 if (lp->loopback_mode == LOOPBACK_MAC) { 5307 val &= ~XMAC_CONFIG_SEL_POR_CLK_SRC; 5308 val |= XMAC_CONFIG_LOOPBACK; 5309 } else { 5310 val &= ~XMAC_CONFIG_LOOPBACK; 5311 } 5312 5313 if (np->flags & NIU_FLAGS_10G) { 5314 val &= ~XMAC_CONFIG_LFS_DISABLE; 5315 } else { 5316 val |= XMAC_CONFIG_LFS_DISABLE; 5317 if (!(np->flags & NIU_FLAGS_FIBER) && 5318 !(np->flags & NIU_FLAGS_XCVR_SERDES)) 5319 val |= XMAC_CONFIG_1G_PCS_BYPASS; 5320 else 5321 val &= ~XMAC_CONFIG_1G_PCS_BYPASS; 5322 } 5323 5324 val &= ~XMAC_CONFIG_10G_XPCS_BYPASS; 5325 5326 if (lp->active_speed == SPEED_100) 5327 val |= XMAC_CONFIG_SEL_CLK_25MHZ; 5328 else 5329 val &= ~XMAC_CONFIG_SEL_CLK_25MHZ; 5330 5331 nw64_mac(XMAC_CONFIG, val); 5332 5333 val = nr64_mac(XMAC_CONFIG); 5334 val &= ~XMAC_CONFIG_MODE_MASK; 5335 if (np->flags & NIU_FLAGS_10G) { 5336 val |= XMAC_CONFIG_MODE_XGMII; 5337 } else { 5338 if (lp->active_speed == SPEED_1000) 5339 val |= XMAC_CONFIG_MODE_GMII; 5340 else 5341 val |= XMAC_CONFIG_MODE_MII; 5342 } 5343 5344 nw64_mac(XMAC_CONFIG, val); 5345 } 5346 5347 static void niu_init_xif_bmac(struct niu *np) 5348 { 5349 struct niu_link_config *lp = &np->link_config; 5350 u64 val; 5351 5352 val = BMAC_XIF_CONFIG_TX_OUTPUT_EN; 5353 5354 if (lp->loopback_mode == LOOPBACK_MAC) 5355 val |= BMAC_XIF_CONFIG_MII_LOOPBACK; 5356 else 5357 val &= ~BMAC_XIF_CONFIG_MII_LOOPBACK; 5358 5359 if (lp->active_speed == SPEED_1000) 5360 val |= BMAC_XIF_CONFIG_GMII_MODE; 5361 else 5362 val &= ~BMAC_XIF_CONFIG_GMII_MODE; 5363 5364 val &= ~(BMAC_XIF_CONFIG_LINK_LED | 5365 BMAC_XIF_CONFIG_LED_POLARITY); 5366 5367 if (!(np->flags & NIU_FLAGS_10G) && 5368 !(np->flags & NIU_FLAGS_FIBER) && 5369 lp->active_speed == SPEED_100) 5370 val |= BMAC_XIF_CONFIG_25MHZ_CLOCK; 5371 else 5372 val &= ~BMAC_XIF_CONFIG_25MHZ_CLOCK; 5373 5374 nw64_mac(BMAC_XIF_CONFIG, val); 5375 } 5376 5377 static void niu_init_xif(struct niu *np) 5378 { 5379 if (np->flags & NIU_FLAGS_XMAC) 5380 niu_init_xif_xmac(np); 5381 else 5382 niu_init_xif_bmac(np); 5383 } 5384 5385 static void niu_pcs_mii_reset(struct niu *np) 5386 { 5387 int limit = 1000; 5388 u64 val = nr64_pcs(PCS_MII_CTL); 5389 val |= PCS_MII_CTL_RST; 5390 nw64_pcs(PCS_MII_CTL, val); 5391 while ((--limit >= 0) && (val & PCS_MII_CTL_RST)) { 5392 udelay(100); 5393 val = nr64_pcs(PCS_MII_CTL); 5394 } 5395 } 5396 5397 static void niu_xpcs_reset(struct niu *np) 5398 { 5399 int limit = 1000; 5400 u64 val = nr64_xpcs(XPCS_CONTROL1); 5401 val |= XPCS_CONTROL1_RESET; 5402 nw64_xpcs(XPCS_CONTROL1, val); 5403 while ((--limit >= 0) && (val & XPCS_CONTROL1_RESET)) { 5404 udelay(100); 5405 val = nr64_xpcs(XPCS_CONTROL1); 5406 } 5407 } 5408 5409 static int niu_init_pcs(struct niu *np) 5410 { 5411 struct niu_link_config *lp = &np->link_config; 5412 u64 val; 5413 5414 switch (np->flags & (NIU_FLAGS_10G | 5415 NIU_FLAGS_FIBER | 5416 NIU_FLAGS_XCVR_SERDES)) { 5417 case NIU_FLAGS_FIBER: 5418 /* 1G fiber */ 5419 nw64_pcs(PCS_CONF, PCS_CONF_MASK | PCS_CONF_ENABLE); 5420 nw64_pcs(PCS_DPATH_MODE, 0); 5421 niu_pcs_mii_reset(np); 5422 break; 5423 5424 case NIU_FLAGS_10G: 5425 case NIU_FLAGS_10G | NIU_FLAGS_FIBER: 5426 case NIU_FLAGS_10G | NIU_FLAGS_XCVR_SERDES: 5427 /* 10G SERDES */ 5428 if (!(np->flags & NIU_FLAGS_XMAC)) 5429 return -EINVAL; 5430 5431 /* 10G copper or fiber */ 5432 val = nr64_mac(XMAC_CONFIG); 5433 val &= ~XMAC_CONFIG_10G_XPCS_BYPASS; 5434 nw64_mac(XMAC_CONFIG, val); 5435 5436 niu_xpcs_reset(np); 5437 5438 val = nr64_xpcs(XPCS_CONTROL1); 5439 if (lp->loopback_mode == LOOPBACK_PHY) 5440 val |= XPCS_CONTROL1_LOOPBACK; 5441 else 5442 val &= ~XPCS_CONTROL1_LOOPBACK; 5443 nw64_xpcs(XPCS_CONTROL1, val); 5444 5445 nw64_xpcs(XPCS_DESKEW_ERR_CNT, 0); 5446 (void) nr64_xpcs(XPCS_SYMERR_CNT01); 5447 (void) nr64_xpcs(XPCS_SYMERR_CNT23); 5448 break; 5449 5450 5451 case NIU_FLAGS_XCVR_SERDES: 5452 /* 1G SERDES */ 5453 niu_pcs_mii_reset(np); 5454 nw64_pcs(PCS_CONF, PCS_CONF_MASK | PCS_CONF_ENABLE); 5455 nw64_pcs(PCS_DPATH_MODE, 0); 5456 break; 5457 5458 case 0: 5459 /* 1G copper */ 5460 case NIU_FLAGS_XCVR_SERDES | NIU_FLAGS_FIBER: 5461 /* 1G RGMII FIBER */ 5462 nw64_pcs(PCS_DPATH_MODE, PCS_DPATH_MODE_MII); 5463 niu_pcs_mii_reset(np); 5464 break; 5465 5466 default: 5467 return -EINVAL; 5468 } 5469 5470 return 0; 5471 } 5472 5473 static int niu_reset_tx_xmac(struct niu *np) 5474 { 5475 return niu_set_and_wait_clear_mac(np, XTXMAC_SW_RST, 5476 (XTXMAC_SW_RST_REG_RS | 5477 XTXMAC_SW_RST_SOFT_RST), 5478 1000, 100, "XTXMAC_SW_RST"); 5479 } 5480 5481 static int niu_reset_tx_bmac(struct niu *np) 5482 { 5483 int limit; 5484 5485 nw64_mac(BTXMAC_SW_RST, BTXMAC_SW_RST_RESET); 5486 limit = 1000; 5487 while (--limit >= 0) { 5488 if (!(nr64_mac(BTXMAC_SW_RST) & BTXMAC_SW_RST_RESET)) 5489 break; 5490 udelay(100); 5491 } 5492 if (limit < 0) { 5493 dev_err(np->device, "Port %u TX BMAC would not reset, BTXMAC_SW_RST[%llx]\n", 5494 np->port, 5495 (unsigned long long) nr64_mac(BTXMAC_SW_RST)); 5496 return -ENODEV; 5497 } 5498 5499 return 0; 5500 } 5501 5502 static int niu_reset_tx_mac(struct niu *np) 5503 { 5504 if (np->flags & NIU_FLAGS_XMAC) 5505 return niu_reset_tx_xmac(np); 5506 else 5507 return niu_reset_tx_bmac(np); 5508 } 5509 5510 static void niu_init_tx_xmac(struct niu *np, u64 min, u64 max) 5511 { 5512 u64 val; 5513 5514 val = nr64_mac(XMAC_MIN); 5515 val &= ~(XMAC_MIN_TX_MIN_PKT_SIZE | 5516 XMAC_MIN_RX_MIN_PKT_SIZE); 5517 val |= (min << XMAC_MIN_RX_MIN_PKT_SIZE_SHFT); 5518 val |= (min << XMAC_MIN_TX_MIN_PKT_SIZE_SHFT); 5519 nw64_mac(XMAC_MIN, val); 5520 5521 nw64_mac(XMAC_MAX, max); 5522 5523 nw64_mac(XTXMAC_STAT_MSK, ~(u64)0); 5524 5525 val = nr64_mac(XMAC_IPG); 5526 if (np->flags & NIU_FLAGS_10G) { 5527 val &= ~XMAC_IPG_IPG_XGMII; 5528 val |= (IPG_12_15_XGMII << XMAC_IPG_IPG_XGMII_SHIFT); 5529 } else { 5530 val &= ~XMAC_IPG_IPG_MII_GMII; 5531 val |= (IPG_12_MII_GMII << XMAC_IPG_IPG_MII_GMII_SHIFT); 5532 } 5533 nw64_mac(XMAC_IPG, val); 5534 5535 val = nr64_mac(XMAC_CONFIG); 5536 val &= ~(XMAC_CONFIG_ALWAYS_NO_CRC | 5537 XMAC_CONFIG_STRETCH_MODE | 5538 XMAC_CONFIG_VAR_MIN_IPG_EN | 5539 XMAC_CONFIG_TX_ENABLE); 5540 nw64_mac(XMAC_CONFIG, val); 5541 5542 nw64_mac(TXMAC_FRM_CNT, 0); 5543 nw64_mac(TXMAC_BYTE_CNT, 0); 5544 } 5545 5546 static void niu_init_tx_bmac(struct niu *np, u64 min, u64 max) 5547 { 5548 u64 val; 5549 5550 nw64_mac(BMAC_MIN_FRAME, min); 5551 nw64_mac(BMAC_MAX_FRAME, max); 5552 5553 nw64_mac(BTXMAC_STATUS_MASK, ~(u64)0); 5554 nw64_mac(BMAC_CTRL_TYPE, 0x8808); 5555 nw64_mac(BMAC_PREAMBLE_SIZE, 7); 5556 5557 val = nr64_mac(BTXMAC_CONFIG); 5558 val &= ~(BTXMAC_CONFIG_FCS_DISABLE | 5559 BTXMAC_CONFIG_ENABLE); 5560 nw64_mac(BTXMAC_CONFIG, val); 5561 } 5562 5563 static void niu_init_tx_mac(struct niu *np) 5564 { 5565 u64 min, max; 5566 5567 min = 64; 5568 if (np->dev->mtu > ETH_DATA_LEN) 5569 max = 9216; 5570 else 5571 max = 1522; 5572 5573 /* The XMAC_MIN register only accepts values for TX min which 5574 * have the low 3 bits cleared. 5575 */ 5576 BUG_ON(min & 0x7); 5577 5578 if (np->flags & NIU_FLAGS_XMAC) 5579 niu_init_tx_xmac(np, min, max); 5580 else 5581 niu_init_tx_bmac(np, min, max); 5582 } 5583 5584 static int niu_reset_rx_xmac(struct niu *np) 5585 { 5586 int limit; 5587 5588 nw64_mac(XRXMAC_SW_RST, 5589 XRXMAC_SW_RST_REG_RS | XRXMAC_SW_RST_SOFT_RST); 5590 limit = 1000; 5591 while (--limit >= 0) { 5592 if (!(nr64_mac(XRXMAC_SW_RST) & (XRXMAC_SW_RST_REG_RS | 5593 XRXMAC_SW_RST_SOFT_RST))) 5594 break; 5595 udelay(100); 5596 } 5597 if (limit < 0) { 5598 dev_err(np->device, "Port %u RX XMAC would not reset, XRXMAC_SW_RST[%llx]\n", 5599 np->port, 5600 (unsigned long long) nr64_mac(XRXMAC_SW_RST)); 5601 return -ENODEV; 5602 } 5603 5604 return 0; 5605 } 5606 5607 static int niu_reset_rx_bmac(struct niu *np) 5608 { 5609 int limit; 5610 5611 nw64_mac(BRXMAC_SW_RST, BRXMAC_SW_RST_RESET); 5612 limit = 1000; 5613 while (--limit >= 0) { 5614 if (!(nr64_mac(BRXMAC_SW_RST) & BRXMAC_SW_RST_RESET)) 5615 break; 5616 udelay(100); 5617 } 5618 if (limit < 0) { 5619 dev_err(np->device, "Port %u RX BMAC would not reset, BRXMAC_SW_RST[%llx]\n", 5620 np->port, 5621 (unsigned long long) nr64_mac(BRXMAC_SW_RST)); 5622 return -ENODEV; 5623 } 5624 5625 return 0; 5626 } 5627 5628 static int niu_reset_rx_mac(struct niu *np) 5629 { 5630 if (np->flags & NIU_FLAGS_XMAC) 5631 return niu_reset_rx_xmac(np); 5632 else 5633 return niu_reset_rx_bmac(np); 5634 } 5635 5636 static void niu_init_rx_xmac(struct niu *np) 5637 { 5638 struct niu_parent *parent = np->parent; 5639 struct niu_rdc_tables *tp = &parent->rdc_group_cfg[np->port]; 5640 int first_rdc_table = tp->first_table_num; 5641 unsigned long i; 5642 u64 val; 5643 5644 nw64_mac(XMAC_ADD_FILT0, 0); 5645 nw64_mac(XMAC_ADD_FILT1, 0); 5646 nw64_mac(XMAC_ADD_FILT2, 0); 5647 nw64_mac(XMAC_ADD_FILT12_MASK, 0); 5648 nw64_mac(XMAC_ADD_FILT00_MASK, 0); 5649 for (i = 0; i < MAC_NUM_HASH; i++) 5650 nw64_mac(XMAC_HASH_TBL(i), 0); 5651 nw64_mac(XRXMAC_STAT_MSK, ~(u64)0); 5652 niu_set_primary_mac_rdc_table(np, first_rdc_table, 1); 5653 niu_set_multicast_mac_rdc_table(np, first_rdc_table, 1); 5654 5655 val = nr64_mac(XMAC_CONFIG); 5656 val &= ~(XMAC_CONFIG_RX_MAC_ENABLE | 5657 XMAC_CONFIG_PROMISCUOUS | 5658 XMAC_CONFIG_PROMISC_GROUP | 5659 XMAC_CONFIG_ERR_CHK_DIS | 5660 XMAC_CONFIG_RX_CRC_CHK_DIS | 5661 XMAC_CONFIG_RESERVED_MULTICAST | 5662 XMAC_CONFIG_RX_CODEV_CHK_DIS | 5663 XMAC_CONFIG_ADDR_FILTER_EN | 5664 XMAC_CONFIG_RCV_PAUSE_ENABLE | 5665 XMAC_CONFIG_STRIP_CRC | 5666 XMAC_CONFIG_PASS_FLOW_CTRL | 5667 XMAC_CONFIG_MAC2IPP_PKT_CNT_EN); 5668 val |= (XMAC_CONFIG_HASH_FILTER_EN); 5669 nw64_mac(XMAC_CONFIG, val); 5670 5671 nw64_mac(RXMAC_BT_CNT, 0); 5672 nw64_mac(RXMAC_BC_FRM_CNT, 0); 5673 nw64_mac(RXMAC_MC_FRM_CNT, 0); 5674 nw64_mac(RXMAC_FRAG_CNT, 0); 5675 nw64_mac(RXMAC_HIST_CNT1, 0); 5676 nw64_mac(RXMAC_HIST_CNT2, 0); 5677 nw64_mac(RXMAC_HIST_CNT3, 0); 5678 nw64_mac(RXMAC_HIST_CNT4, 0); 5679 nw64_mac(RXMAC_HIST_CNT5, 0); 5680 nw64_mac(RXMAC_HIST_CNT6, 0); 5681 nw64_mac(RXMAC_HIST_CNT7, 0); 5682 nw64_mac(RXMAC_MPSZER_CNT, 0); 5683 nw64_mac(RXMAC_CRC_ER_CNT, 0); 5684 nw64_mac(RXMAC_CD_VIO_CNT, 0); 5685 nw64_mac(LINK_FAULT_CNT, 0); 5686 } 5687 5688 static void niu_init_rx_bmac(struct niu *np) 5689 { 5690 struct niu_parent *parent = np->parent; 5691 struct niu_rdc_tables *tp = &parent->rdc_group_cfg[np->port]; 5692 int first_rdc_table = tp->first_table_num; 5693 unsigned long i; 5694 u64 val; 5695 5696 nw64_mac(BMAC_ADD_FILT0, 0); 5697 nw64_mac(BMAC_ADD_FILT1, 0); 5698 nw64_mac(BMAC_ADD_FILT2, 0); 5699 nw64_mac(BMAC_ADD_FILT12_MASK, 0); 5700 nw64_mac(BMAC_ADD_FILT00_MASK, 0); 5701 for (i = 0; i < MAC_NUM_HASH; i++) 5702 nw64_mac(BMAC_HASH_TBL(i), 0); 5703 niu_set_primary_mac_rdc_table(np, first_rdc_table, 1); 5704 niu_set_multicast_mac_rdc_table(np, first_rdc_table, 1); 5705 nw64_mac(BRXMAC_STATUS_MASK, ~(u64)0); 5706 5707 val = nr64_mac(BRXMAC_CONFIG); 5708 val &= ~(BRXMAC_CONFIG_ENABLE | 5709 BRXMAC_CONFIG_STRIP_PAD | 5710 BRXMAC_CONFIG_STRIP_FCS | 5711 BRXMAC_CONFIG_PROMISC | 5712 BRXMAC_CONFIG_PROMISC_GRP | 5713 BRXMAC_CONFIG_ADDR_FILT_EN | 5714 BRXMAC_CONFIG_DISCARD_DIS); 5715 val |= (BRXMAC_CONFIG_HASH_FILT_EN); 5716 nw64_mac(BRXMAC_CONFIG, val); 5717 5718 val = nr64_mac(BMAC_ADDR_CMPEN); 5719 val |= BMAC_ADDR_CMPEN_EN0; 5720 nw64_mac(BMAC_ADDR_CMPEN, val); 5721 } 5722 5723 static void niu_init_rx_mac(struct niu *np) 5724 { 5725 niu_set_primary_mac(np, np->dev->dev_addr); 5726 5727 if (np->flags & NIU_FLAGS_XMAC) 5728 niu_init_rx_xmac(np); 5729 else 5730 niu_init_rx_bmac(np); 5731 } 5732 5733 static void niu_enable_tx_xmac(struct niu *np, int on) 5734 { 5735 u64 val = nr64_mac(XMAC_CONFIG); 5736 5737 if (on) 5738 val |= XMAC_CONFIG_TX_ENABLE; 5739 else 5740 val &= ~XMAC_CONFIG_TX_ENABLE; 5741 nw64_mac(XMAC_CONFIG, val); 5742 } 5743 5744 static void niu_enable_tx_bmac(struct niu *np, int on) 5745 { 5746 u64 val = nr64_mac(BTXMAC_CONFIG); 5747 5748 if (on) 5749 val |= BTXMAC_CONFIG_ENABLE; 5750 else 5751 val &= ~BTXMAC_CONFIG_ENABLE; 5752 nw64_mac(BTXMAC_CONFIG, val); 5753 } 5754 5755 static void niu_enable_tx_mac(struct niu *np, int on) 5756 { 5757 if (np->flags & NIU_FLAGS_XMAC) 5758 niu_enable_tx_xmac(np, on); 5759 else 5760 niu_enable_tx_bmac(np, on); 5761 } 5762 5763 static void niu_enable_rx_xmac(struct niu *np, int on) 5764 { 5765 u64 val = nr64_mac(XMAC_CONFIG); 5766 5767 val &= ~(XMAC_CONFIG_HASH_FILTER_EN | 5768 XMAC_CONFIG_PROMISCUOUS); 5769 5770 if (np->flags & NIU_FLAGS_MCAST) 5771 val |= XMAC_CONFIG_HASH_FILTER_EN; 5772 if (np->flags & NIU_FLAGS_PROMISC) 5773 val |= XMAC_CONFIG_PROMISCUOUS; 5774 5775 if (on) 5776 val |= XMAC_CONFIG_RX_MAC_ENABLE; 5777 else 5778 val &= ~XMAC_CONFIG_RX_MAC_ENABLE; 5779 nw64_mac(XMAC_CONFIG, val); 5780 } 5781 5782 static void niu_enable_rx_bmac(struct niu *np, int on) 5783 { 5784 u64 val = nr64_mac(BRXMAC_CONFIG); 5785 5786 val &= ~(BRXMAC_CONFIG_HASH_FILT_EN | 5787 BRXMAC_CONFIG_PROMISC); 5788 5789 if (np->flags & NIU_FLAGS_MCAST) 5790 val |= BRXMAC_CONFIG_HASH_FILT_EN; 5791 if (np->flags & NIU_FLAGS_PROMISC) 5792 val |= BRXMAC_CONFIG_PROMISC; 5793 5794 if (on) 5795 val |= BRXMAC_CONFIG_ENABLE; 5796 else 5797 val &= ~BRXMAC_CONFIG_ENABLE; 5798 nw64_mac(BRXMAC_CONFIG, val); 5799 } 5800 5801 static void niu_enable_rx_mac(struct niu *np, int on) 5802 { 5803 if (np->flags & NIU_FLAGS_XMAC) 5804 niu_enable_rx_xmac(np, on); 5805 else 5806 niu_enable_rx_bmac(np, on); 5807 } 5808 5809 static int niu_init_mac(struct niu *np) 5810 { 5811 int err; 5812 5813 niu_init_xif(np); 5814 err = niu_init_pcs(np); 5815 if (err) 5816 return err; 5817 5818 err = niu_reset_tx_mac(np); 5819 if (err) 5820 return err; 5821 niu_init_tx_mac(np); 5822 err = niu_reset_rx_mac(np); 5823 if (err) 5824 return err; 5825 niu_init_rx_mac(np); 5826 5827 /* This looks hookey but the RX MAC reset we just did will 5828 * undo some of the state we setup in niu_init_tx_mac() so we 5829 * have to call it again. In particular, the RX MAC reset will 5830 * set the XMAC_MAX register back to it's default value. 5831 */ 5832 niu_init_tx_mac(np); 5833 niu_enable_tx_mac(np, 1); 5834 5835 niu_enable_rx_mac(np, 1); 5836 5837 return 0; 5838 } 5839 5840 static void niu_stop_one_tx_channel(struct niu *np, struct tx_ring_info *rp) 5841 { 5842 (void) niu_tx_channel_stop(np, rp->tx_channel); 5843 } 5844 5845 static void niu_stop_tx_channels(struct niu *np) 5846 { 5847 int i; 5848 5849 for (i = 0; i < np->num_tx_rings; i++) { 5850 struct tx_ring_info *rp = &np->tx_rings[i]; 5851 5852 niu_stop_one_tx_channel(np, rp); 5853 } 5854 } 5855 5856 static void niu_reset_one_tx_channel(struct niu *np, struct tx_ring_info *rp) 5857 { 5858 (void) niu_tx_channel_reset(np, rp->tx_channel); 5859 } 5860 5861 static void niu_reset_tx_channels(struct niu *np) 5862 { 5863 int i; 5864 5865 for (i = 0; i < np->num_tx_rings; i++) { 5866 struct tx_ring_info *rp = &np->tx_rings[i]; 5867 5868 niu_reset_one_tx_channel(np, rp); 5869 } 5870 } 5871 5872 static void niu_stop_one_rx_channel(struct niu *np, struct rx_ring_info *rp) 5873 { 5874 (void) niu_enable_rx_channel(np, rp->rx_channel, 0); 5875 } 5876 5877 static void niu_stop_rx_channels(struct niu *np) 5878 { 5879 int i; 5880 5881 for (i = 0; i < np->num_rx_rings; i++) { 5882 struct rx_ring_info *rp = &np->rx_rings[i]; 5883 5884 niu_stop_one_rx_channel(np, rp); 5885 } 5886 } 5887 5888 static void niu_reset_one_rx_channel(struct niu *np, struct rx_ring_info *rp) 5889 { 5890 int channel = rp->rx_channel; 5891 5892 (void) niu_rx_channel_reset(np, channel); 5893 nw64(RX_DMA_ENT_MSK(channel), RX_DMA_ENT_MSK_ALL); 5894 nw64(RX_DMA_CTL_STAT(channel), 0); 5895 (void) niu_enable_rx_channel(np, channel, 0); 5896 } 5897 5898 static void niu_reset_rx_channels(struct niu *np) 5899 { 5900 int i; 5901 5902 for (i = 0; i < np->num_rx_rings; i++) { 5903 struct rx_ring_info *rp = &np->rx_rings[i]; 5904 5905 niu_reset_one_rx_channel(np, rp); 5906 } 5907 } 5908 5909 static void niu_disable_ipp(struct niu *np) 5910 { 5911 u64 rd, wr, val; 5912 int limit; 5913 5914 rd = nr64_ipp(IPP_DFIFO_RD_PTR); 5915 wr = nr64_ipp(IPP_DFIFO_WR_PTR); 5916 limit = 100; 5917 while (--limit >= 0 && (rd != wr)) { 5918 rd = nr64_ipp(IPP_DFIFO_RD_PTR); 5919 wr = nr64_ipp(IPP_DFIFO_WR_PTR); 5920 } 5921 if (limit < 0 && 5922 (rd != 0 && wr != 1)) { 5923 netdev_err(np->dev, "IPP would not quiesce, rd_ptr[%llx] wr_ptr[%llx]\n", 5924 (unsigned long long)nr64_ipp(IPP_DFIFO_RD_PTR), 5925 (unsigned long long)nr64_ipp(IPP_DFIFO_WR_PTR)); 5926 } 5927 5928 val = nr64_ipp(IPP_CFIG); 5929 val &= ~(IPP_CFIG_IPP_ENABLE | 5930 IPP_CFIG_DFIFO_ECC_EN | 5931 IPP_CFIG_DROP_BAD_CRC | 5932 IPP_CFIG_CKSUM_EN); 5933 nw64_ipp(IPP_CFIG, val); 5934 5935 (void) niu_ipp_reset(np); 5936 } 5937 5938 static int niu_init_hw(struct niu *np) 5939 { 5940 int i, err; 5941 5942 netif_printk(np, ifup, KERN_DEBUG, np->dev, "Initialize TXC\n"); 5943 niu_txc_enable_port(np, 1); 5944 niu_txc_port_dma_enable(np, 1); 5945 niu_txc_set_imask(np, 0); 5946 5947 netif_printk(np, ifup, KERN_DEBUG, np->dev, "Initialize TX channels\n"); 5948 for (i = 0; i < np->num_tx_rings; i++) { 5949 struct tx_ring_info *rp = &np->tx_rings[i]; 5950 5951 err = niu_init_one_tx_channel(np, rp); 5952 if (err) 5953 return err; 5954 } 5955 5956 netif_printk(np, ifup, KERN_DEBUG, np->dev, "Initialize RX channels\n"); 5957 err = niu_init_rx_channels(np); 5958 if (err) 5959 goto out_uninit_tx_channels; 5960 5961 netif_printk(np, ifup, KERN_DEBUG, np->dev, "Initialize classifier\n"); 5962 err = niu_init_classifier_hw(np); 5963 if (err) 5964 goto out_uninit_rx_channels; 5965 5966 netif_printk(np, ifup, KERN_DEBUG, np->dev, "Initialize ZCP\n"); 5967 err = niu_init_zcp(np); 5968 if (err) 5969 goto out_uninit_rx_channels; 5970 5971 netif_printk(np, ifup, KERN_DEBUG, np->dev, "Initialize IPP\n"); 5972 err = niu_init_ipp(np); 5973 if (err) 5974 goto out_uninit_rx_channels; 5975 5976 netif_printk(np, ifup, KERN_DEBUG, np->dev, "Initialize MAC\n"); 5977 err = niu_init_mac(np); 5978 if (err) 5979 goto out_uninit_ipp; 5980 5981 return 0; 5982 5983 out_uninit_ipp: 5984 netif_printk(np, ifup, KERN_DEBUG, np->dev, "Uninit IPP\n"); 5985 niu_disable_ipp(np); 5986 5987 out_uninit_rx_channels: 5988 netif_printk(np, ifup, KERN_DEBUG, np->dev, "Uninit RX channels\n"); 5989 niu_stop_rx_channels(np); 5990 niu_reset_rx_channels(np); 5991 5992 out_uninit_tx_channels: 5993 netif_printk(np, ifup, KERN_DEBUG, np->dev, "Uninit TX channels\n"); 5994 niu_stop_tx_channels(np); 5995 niu_reset_tx_channels(np); 5996 5997 return err; 5998 } 5999 6000 static void niu_stop_hw(struct niu *np) 6001 { 6002 netif_printk(np, ifdown, KERN_DEBUG, np->dev, "Disable interrupts\n"); 6003 niu_enable_interrupts(np, 0); 6004 6005 netif_printk(np, ifdown, KERN_DEBUG, np->dev, "Disable RX MAC\n"); 6006 niu_enable_rx_mac(np, 0); 6007 6008 netif_printk(np, ifdown, KERN_DEBUG, np->dev, "Disable IPP\n"); 6009 niu_disable_ipp(np); 6010 6011 netif_printk(np, ifdown, KERN_DEBUG, np->dev, "Stop TX channels\n"); 6012 niu_stop_tx_channels(np); 6013 6014 netif_printk(np, ifdown, KERN_DEBUG, np->dev, "Stop RX channels\n"); 6015 niu_stop_rx_channels(np); 6016 6017 netif_printk(np, ifdown, KERN_DEBUG, np->dev, "Reset TX channels\n"); 6018 niu_reset_tx_channels(np); 6019 6020 netif_printk(np, ifdown, KERN_DEBUG, np->dev, "Reset RX channels\n"); 6021 niu_reset_rx_channels(np); 6022 } 6023 6024 static void niu_set_irq_name(struct niu *np) 6025 { 6026 int port = np->port; 6027 int i, j = 1; 6028 6029 sprintf(np->irq_name[0], "%s:MAC", np->dev->name); 6030 6031 if (port == 0) { 6032 sprintf(np->irq_name[1], "%s:MIF", np->dev->name); 6033 sprintf(np->irq_name[2], "%s:SYSERR", np->dev->name); 6034 j = 3; 6035 } 6036 6037 for (i = 0; i < np->num_ldg - j; i++) { 6038 if (i < np->num_rx_rings) 6039 sprintf(np->irq_name[i+j], "%s-rx-%d", 6040 np->dev->name, i); 6041 else if (i < np->num_tx_rings + np->num_rx_rings) 6042 sprintf(np->irq_name[i+j], "%s-tx-%d", np->dev->name, 6043 i - np->num_rx_rings); 6044 } 6045 } 6046 6047 static int niu_request_irq(struct niu *np) 6048 { 6049 int i, j, err; 6050 6051 niu_set_irq_name(np); 6052 6053 err = 0; 6054 for (i = 0; i < np->num_ldg; i++) { 6055 struct niu_ldg *lp = &np->ldg[i]; 6056 6057 err = request_irq(lp->irq, niu_interrupt, IRQF_SHARED, 6058 np->irq_name[i], lp); 6059 if (err) 6060 goto out_free_irqs; 6061 6062 } 6063 6064 return 0; 6065 6066 out_free_irqs: 6067 for (j = 0; j < i; j++) { 6068 struct niu_ldg *lp = &np->ldg[j]; 6069 6070 free_irq(lp->irq, lp); 6071 } 6072 return err; 6073 } 6074 6075 static void niu_free_irq(struct niu *np) 6076 { 6077 int i; 6078 6079 for (i = 0; i < np->num_ldg; i++) { 6080 struct niu_ldg *lp = &np->ldg[i]; 6081 6082 free_irq(lp->irq, lp); 6083 } 6084 } 6085 6086 static void niu_enable_napi(struct niu *np) 6087 { 6088 int i; 6089 6090 for (i = 0; i < np->num_ldg; i++) 6091 napi_enable(&np->ldg[i].napi); 6092 } 6093 6094 static void niu_disable_napi(struct niu *np) 6095 { 6096 int i; 6097 6098 for (i = 0; i < np->num_ldg; i++) 6099 napi_disable(&np->ldg[i].napi); 6100 } 6101 6102 static int niu_open(struct net_device *dev) 6103 { 6104 struct niu *np = netdev_priv(dev); 6105 int err; 6106 6107 netif_carrier_off(dev); 6108 6109 err = niu_alloc_channels(np); 6110 if (err) 6111 goto out_err; 6112 6113 err = niu_enable_interrupts(np, 0); 6114 if (err) 6115 goto out_free_channels; 6116 6117 err = niu_request_irq(np); 6118 if (err) 6119 goto out_free_channels; 6120 6121 niu_enable_napi(np); 6122 6123 spin_lock_irq(&np->lock); 6124 6125 err = niu_init_hw(np); 6126 if (!err) { 6127 init_timer(&np->timer); 6128 np->timer.expires = jiffies + HZ; 6129 np->timer.data = (unsigned long) np; 6130 np->timer.function = niu_timer; 6131 6132 err = niu_enable_interrupts(np, 1); 6133 if (err) 6134 niu_stop_hw(np); 6135 } 6136 6137 spin_unlock_irq(&np->lock); 6138 6139 if (err) { 6140 niu_disable_napi(np); 6141 goto out_free_irq; 6142 } 6143 6144 netif_tx_start_all_queues(dev); 6145 6146 if (np->link_config.loopback_mode != LOOPBACK_DISABLED) 6147 netif_carrier_on(dev); 6148 6149 add_timer(&np->timer); 6150 6151 return 0; 6152 6153 out_free_irq: 6154 niu_free_irq(np); 6155 6156 out_free_channels: 6157 niu_free_channels(np); 6158 6159 out_err: 6160 return err; 6161 } 6162 6163 static void niu_full_shutdown(struct niu *np, struct net_device *dev) 6164 { 6165 cancel_work_sync(&np->reset_task); 6166 6167 niu_disable_napi(np); 6168 netif_tx_stop_all_queues(dev); 6169 6170 del_timer_sync(&np->timer); 6171 6172 spin_lock_irq(&np->lock); 6173 6174 niu_stop_hw(np); 6175 6176 spin_unlock_irq(&np->lock); 6177 } 6178 6179 static int niu_close(struct net_device *dev) 6180 { 6181 struct niu *np = netdev_priv(dev); 6182 6183 niu_full_shutdown(np, dev); 6184 6185 niu_free_irq(np); 6186 6187 niu_free_channels(np); 6188 6189 niu_handle_led(np, 0); 6190 6191 return 0; 6192 } 6193 6194 static void niu_sync_xmac_stats(struct niu *np) 6195 { 6196 struct niu_xmac_stats *mp = &np->mac_stats.xmac; 6197 6198 mp->tx_frames += nr64_mac(TXMAC_FRM_CNT); 6199 mp->tx_bytes += nr64_mac(TXMAC_BYTE_CNT); 6200 6201 mp->rx_link_faults += nr64_mac(LINK_FAULT_CNT); 6202 mp->rx_align_errors += nr64_mac(RXMAC_ALIGN_ERR_CNT); 6203 mp->rx_frags += nr64_mac(RXMAC_FRAG_CNT); 6204 mp->rx_mcasts += nr64_mac(RXMAC_MC_FRM_CNT); 6205 mp->rx_bcasts += nr64_mac(RXMAC_BC_FRM_CNT); 6206 mp->rx_hist_cnt1 += nr64_mac(RXMAC_HIST_CNT1); 6207 mp->rx_hist_cnt2 += nr64_mac(RXMAC_HIST_CNT2); 6208 mp->rx_hist_cnt3 += nr64_mac(RXMAC_HIST_CNT3); 6209 mp->rx_hist_cnt4 += nr64_mac(RXMAC_HIST_CNT4); 6210 mp->rx_hist_cnt5 += nr64_mac(RXMAC_HIST_CNT5); 6211 mp->rx_hist_cnt6 += nr64_mac(RXMAC_HIST_CNT6); 6212 mp->rx_hist_cnt7 += nr64_mac(RXMAC_HIST_CNT7); 6213 mp->rx_octets += nr64_mac(RXMAC_BT_CNT); 6214 mp->rx_code_violations += nr64_mac(RXMAC_CD_VIO_CNT); 6215 mp->rx_len_errors += nr64_mac(RXMAC_MPSZER_CNT); 6216 mp->rx_crc_errors += nr64_mac(RXMAC_CRC_ER_CNT); 6217 } 6218 6219 static void niu_sync_bmac_stats(struct niu *np) 6220 { 6221 struct niu_bmac_stats *mp = &np->mac_stats.bmac; 6222 6223 mp->tx_bytes += nr64_mac(BTXMAC_BYTE_CNT); 6224 mp->tx_frames += nr64_mac(BTXMAC_FRM_CNT); 6225 6226 mp->rx_frames += nr64_mac(BRXMAC_FRAME_CNT); 6227 mp->rx_align_errors += nr64_mac(BRXMAC_ALIGN_ERR_CNT); 6228 mp->rx_crc_errors += nr64_mac(BRXMAC_ALIGN_ERR_CNT); 6229 mp->rx_len_errors += nr64_mac(BRXMAC_CODE_VIOL_ERR_CNT); 6230 } 6231 6232 static void niu_sync_mac_stats(struct niu *np) 6233 { 6234 if (np->flags & NIU_FLAGS_XMAC) 6235 niu_sync_xmac_stats(np); 6236 else 6237 niu_sync_bmac_stats(np); 6238 } 6239 6240 static void niu_get_rx_stats(struct niu *np, 6241 struct rtnl_link_stats64 *stats) 6242 { 6243 u64 pkts, dropped, errors, bytes; 6244 struct rx_ring_info *rx_rings; 6245 int i; 6246 6247 pkts = dropped = errors = bytes = 0; 6248 6249 rx_rings = ACCESS_ONCE(np->rx_rings); 6250 if (!rx_rings) 6251 goto no_rings; 6252 6253 for (i = 0; i < np->num_rx_rings; i++) { 6254 struct rx_ring_info *rp = &rx_rings[i]; 6255 6256 niu_sync_rx_discard_stats(np, rp, 0); 6257 6258 pkts += rp->rx_packets; 6259 bytes += rp->rx_bytes; 6260 dropped += rp->rx_dropped; 6261 errors += rp->rx_errors; 6262 } 6263 6264 no_rings: 6265 stats->rx_packets = pkts; 6266 stats->rx_bytes = bytes; 6267 stats->rx_dropped = dropped; 6268 stats->rx_errors = errors; 6269 } 6270 6271 static void niu_get_tx_stats(struct niu *np, 6272 struct rtnl_link_stats64 *stats) 6273 { 6274 u64 pkts, errors, bytes; 6275 struct tx_ring_info *tx_rings; 6276 int i; 6277 6278 pkts = errors = bytes = 0; 6279 6280 tx_rings = ACCESS_ONCE(np->tx_rings); 6281 if (!tx_rings) 6282 goto no_rings; 6283 6284 for (i = 0; i < np->num_tx_rings; i++) { 6285 struct tx_ring_info *rp = &tx_rings[i]; 6286 6287 pkts += rp->tx_packets; 6288 bytes += rp->tx_bytes; 6289 errors += rp->tx_errors; 6290 } 6291 6292 no_rings: 6293 stats->tx_packets = pkts; 6294 stats->tx_bytes = bytes; 6295 stats->tx_errors = errors; 6296 } 6297 6298 static struct rtnl_link_stats64 *niu_get_stats(struct net_device *dev, 6299 struct rtnl_link_stats64 *stats) 6300 { 6301 struct niu *np = netdev_priv(dev); 6302 6303 if (netif_running(dev)) { 6304 niu_get_rx_stats(np, stats); 6305 niu_get_tx_stats(np, stats); 6306 } 6307 6308 return stats; 6309 } 6310 6311 static void niu_load_hash_xmac(struct niu *np, u16 *hash) 6312 { 6313 int i; 6314 6315 for (i = 0; i < 16; i++) 6316 nw64_mac(XMAC_HASH_TBL(i), hash[i]); 6317 } 6318 6319 static void niu_load_hash_bmac(struct niu *np, u16 *hash) 6320 { 6321 int i; 6322 6323 for (i = 0; i < 16; i++) 6324 nw64_mac(BMAC_HASH_TBL(i), hash[i]); 6325 } 6326 6327 static void niu_load_hash(struct niu *np, u16 *hash) 6328 { 6329 if (np->flags & NIU_FLAGS_XMAC) 6330 niu_load_hash_xmac(np, hash); 6331 else 6332 niu_load_hash_bmac(np, hash); 6333 } 6334 6335 static void niu_set_rx_mode(struct net_device *dev) 6336 { 6337 struct niu *np = netdev_priv(dev); 6338 int i, alt_cnt, err; 6339 struct netdev_hw_addr *ha; 6340 unsigned long flags; 6341 u16 hash[16] = { 0, }; 6342 6343 spin_lock_irqsave(&np->lock, flags); 6344 niu_enable_rx_mac(np, 0); 6345 6346 np->flags &= ~(NIU_FLAGS_MCAST | NIU_FLAGS_PROMISC); 6347 if (dev->flags & IFF_PROMISC) 6348 np->flags |= NIU_FLAGS_PROMISC; 6349 if ((dev->flags & IFF_ALLMULTI) || (!netdev_mc_empty(dev))) 6350 np->flags |= NIU_FLAGS_MCAST; 6351 6352 alt_cnt = netdev_uc_count(dev); 6353 if (alt_cnt > niu_num_alt_addr(np)) { 6354 alt_cnt = 0; 6355 np->flags |= NIU_FLAGS_PROMISC; 6356 } 6357 6358 if (alt_cnt) { 6359 int index = 0; 6360 6361 netdev_for_each_uc_addr(ha, dev) { 6362 err = niu_set_alt_mac(np, index, ha->addr); 6363 if (err) 6364 netdev_warn(dev, "Error %d adding alt mac %d\n", 6365 err, index); 6366 err = niu_enable_alt_mac(np, index, 1); 6367 if (err) 6368 netdev_warn(dev, "Error %d enabling alt mac %d\n", 6369 err, index); 6370 6371 index++; 6372 } 6373 } else { 6374 int alt_start; 6375 if (np->flags & NIU_FLAGS_XMAC) 6376 alt_start = 0; 6377 else 6378 alt_start = 1; 6379 for (i = alt_start; i < niu_num_alt_addr(np); i++) { 6380 err = niu_enable_alt_mac(np, i, 0); 6381 if (err) 6382 netdev_warn(dev, "Error %d disabling alt mac %d\n", 6383 err, i); 6384 } 6385 } 6386 if (dev->flags & IFF_ALLMULTI) { 6387 for (i = 0; i < 16; i++) 6388 hash[i] = 0xffff; 6389 } else if (!netdev_mc_empty(dev)) { 6390 netdev_for_each_mc_addr(ha, dev) { 6391 u32 crc = ether_crc_le(ETH_ALEN, ha->addr); 6392 6393 crc >>= 24; 6394 hash[crc >> 4] |= (1 << (15 - (crc & 0xf))); 6395 } 6396 } 6397 6398 if (np->flags & NIU_FLAGS_MCAST) 6399 niu_load_hash(np, hash); 6400 6401 niu_enable_rx_mac(np, 1); 6402 spin_unlock_irqrestore(&np->lock, flags); 6403 } 6404 6405 static int niu_set_mac_addr(struct net_device *dev, void *p) 6406 { 6407 struct niu *np = netdev_priv(dev); 6408 struct sockaddr *addr = p; 6409 unsigned long flags; 6410 6411 if (!is_valid_ether_addr(addr->sa_data)) 6412 return -EADDRNOTAVAIL; 6413 6414 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN); 6415 6416 if (!netif_running(dev)) 6417 return 0; 6418 6419 spin_lock_irqsave(&np->lock, flags); 6420 niu_enable_rx_mac(np, 0); 6421 niu_set_primary_mac(np, dev->dev_addr); 6422 niu_enable_rx_mac(np, 1); 6423 spin_unlock_irqrestore(&np->lock, flags); 6424 6425 return 0; 6426 } 6427 6428 static int niu_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) 6429 { 6430 return -EOPNOTSUPP; 6431 } 6432 6433 static void niu_netif_stop(struct niu *np) 6434 { 6435 np->dev->trans_start = jiffies; /* prevent tx timeout */ 6436 6437 niu_disable_napi(np); 6438 6439 netif_tx_disable(np->dev); 6440 } 6441 6442 static void niu_netif_start(struct niu *np) 6443 { 6444 /* NOTE: unconditional netif_wake_queue is only appropriate 6445 * so long as all callers are assured to have free tx slots 6446 * (such as after niu_init_hw). 6447 */ 6448 netif_tx_wake_all_queues(np->dev); 6449 6450 niu_enable_napi(np); 6451 6452 niu_enable_interrupts(np, 1); 6453 } 6454 6455 static void niu_reset_buffers(struct niu *np) 6456 { 6457 int i, j, k, err; 6458 6459 if (np->rx_rings) { 6460 for (i = 0; i < np->num_rx_rings; i++) { 6461 struct rx_ring_info *rp = &np->rx_rings[i]; 6462 6463 for (j = 0, k = 0; j < MAX_RBR_RING_SIZE; j++) { 6464 struct page *page; 6465 6466 page = rp->rxhash[j]; 6467 while (page) { 6468 struct page *next = 6469 (struct page *) page->mapping; 6470 u64 base = page->index; 6471 base = base >> RBR_DESCR_ADDR_SHIFT; 6472 rp->rbr[k++] = cpu_to_le32(base); 6473 page = next; 6474 } 6475 } 6476 for (; k < MAX_RBR_RING_SIZE; k++) { 6477 err = niu_rbr_add_page(np, rp, GFP_ATOMIC, k); 6478 if (unlikely(err)) 6479 break; 6480 } 6481 6482 rp->rbr_index = rp->rbr_table_size - 1; 6483 rp->rcr_index = 0; 6484 rp->rbr_pending = 0; 6485 rp->rbr_refill_pending = 0; 6486 } 6487 } 6488 if (np->tx_rings) { 6489 for (i = 0; i < np->num_tx_rings; i++) { 6490 struct tx_ring_info *rp = &np->tx_rings[i]; 6491 6492 for (j = 0; j < MAX_TX_RING_SIZE; j++) { 6493 if (rp->tx_buffs[j].skb) 6494 (void) release_tx_packet(np, rp, j); 6495 } 6496 6497 rp->pending = MAX_TX_RING_SIZE; 6498 rp->prod = 0; 6499 rp->cons = 0; 6500 rp->wrap_bit = 0; 6501 } 6502 } 6503 } 6504 6505 static void niu_reset_task(struct work_struct *work) 6506 { 6507 struct niu *np = container_of(work, struct niu, reset_task); 6508 unsigned long flags; 6509 int err; 6510 6511 spin_lock_irqsave(&np->lock, flags); 6512 if (!netif_running(np->dev)) { 6513 spin_unlock_irqrestore(&np->lock, flags); 6514 return; 6515 } 6516 6517 spin_unlock_irqrestore(&np->lock, flags); 6518 6519 del_timer_sync(&np->timer); 6520 6521 niu_netif_stop(np); 6522 6523 spin_lock_irqsave(&np->lock, flags); 6524 6525 niu_stop_hw(np); 6526 6527 spin_unlock_irqrestore(&np->lock, flags); 6528 6529 niu_reset_buffers(np); 6530 6531 spin_lock_irqsave(&np->lock, flags); 6532 6533 err = niu_init_hw(np); 6534 if (!err) { 6535 np->timer.expires = jiffies + HZ; 6536 add_timer(&np->timer); 6537 niu_netif_start(np); 6538 } 6539 6540 spin_unlock_irqrestore(&np->lock, flags); 6541 } 6542 6543 static void niu_tx_timeout(struct net_device *dev) 6544 { 6545 struct niu *np = netdev_priv(dev); 6546 6547 dev_err(np->device, "%s: Transmit timed out, resetting\n", 6548 dev->name); 6549 6550 schedule_work(&np->reset_task); 6551 } 6552 6553 static void niu_set_txd(struct tx_ring_info *rp, int index, 6554 u64 mapping, u64 len, u64 mark, 6555 u64 n_frags) 6556 { 6557 __le64 *desc = &rp->descr[index]; 6558 6559 *desc = cpu_to_le64(mark | 6560 (n_frags << TX_DESC_NUM_PTR_SHIFT) | 6561 (len << TX_DESC_TR_LEN_SHIFT) | 6562 (mapping & TX_DESC_SAD)); 6563 } 6564 6565 static u64 niu_compute_tx_flags(struct sk_buff *skb, struct ethhdr *ehdr, 6566 u64 pad_bytes, u64 len) 6567 { 6568 u16 eth_proto, eth_proto_inner; 6569 u64 csum_bits, l3off, ihl, ret; 6570 u8 ip_proto; 6571 int ipv6; 6572 6573 eth_proto = be16_to_cpu(ehdr->h_proto); 6574 eth_proto_inner = eth_proto; 6575 if (eth_proto == ETH_P_8021Q) { 6576 struct vlan_ethhdr *vp = (struct vlan_ethhdr *) ehdr; 6577 __be16 val = vp->h_vlan_encapsulated_proto; 6578 6579 eth_proto_inner = be16_to_cpu(val); 6580 } 6581 6582 ipv6 = ihl = 0; 6583 switch (skb->protocol) { 6584 case cpu_to_be16(ETH_P_IP): 6585 ip_proto = ip_hdr(skb)->protocol; 6586 ihl = ip_hdr(skb)->ihl; 6587 break; 6588 case cpu_to_be16(ETH_P_IPV6): 6589 ip_proto = ipv6_hdr(skb)->nexthdr; 6590 ihl = (40 >> 2); 6591 ipv6 = 1; 6592 break; 6593 default: 6594 ip_proto = ihl = 0; 6595 break; 6596 } 6597 6598 csum_bits = TXHDR_CSUM_NONE; 6599 if (skb->ip_summed == CHECKSUM_PARTIAL) { 6600 u64 start, stuff; 6601 6602 csum_bits = (ip_proto == IPPROTO_TCP ? 6603 TXHDR_CSUM_TCP : 6604 (ip_proto == IPPROTO_UDP ? 6605 TXHDR_CSUM_UDP : TXHDR_CSUM_SCTP)); 6606 6607 start = skb_checksum_start_offset(skb) - 6608 (pad_bytes + sizeof(struct tx_pkt_hdr)); 6609 stuff = start + skb->csum_offset; 6610 6611 csum_bits |= (start / 2) << TXHDR_L4START_SHIFT; 6612 csum_bits |= (stuff / 2) << TXHDR_L4STUFF_SHIFT; 6613 } 6614 6615 l3off = skb_network_offset(skb) - 6616 (pad_bytes + sizeof(struct tx_pkt_hdr)); 6617 6618 ret = (((pad_bytes / 2) << TXHDR_PAD_SHIFT) | 6619 (len << TXHDR_LEN_SHIFT) | 6620 ((l3off / 2) << TXHDR_L3START_SHIFT) | 6621 (ihl << TXHDR_IHL_SHIFT) | 6622 ((eth_proto_inner < ETH_P_802_3_MIN) ? TXHDR_LLC : 0) | 6623 ((eth_proto == ETH_P_8021Q) ? TXHDR_VLAN : 0) | 6624 (ipv6 ? TXHDR_IP_VER : 0) | 6625 csum_bits); 6626 6627 return ret; 6628 } 6629 6630 static netdev_tx_t niu_start_xmit(struct sk_buff *skb, 6631 struct net_device *dev) 6632 { 6633 struct niu *np = netdev_priv(dev); 6634 unsigned long align, headroom; 6635 struct netdev_queue *txq; 6636 struct tx_ring_info *rp; 6637 struct tx_pkt_hdr *tp; 6638 unsigned int len, nfg; 6639 struct ethhdr *ehdr; 6640 int prod, i, tlen; 6641 u64 mapping, mrk; 6642 6643 i = skb_get_queue_mapping(skb); 6644 rp = &np->tx_rings[i]; 6645 txq = netdev_get_tx_queue(dev, i); 6646 6647 if (niu_tx_avail(rp) <= (skb_shinfo(skb)->nr_frags + 1)) { 6648 netif_tx_stop_queue(txq); 6649 dev_err(np->device, "%s: BUG! Tx ring full when queue awake!\n", dev->name); 6650 rp->tx_errors++; 6651 return NETDEV_TX_BUSY; 6652 } 6653 6654 if (skb->len < ETH_ZLEN) { 6655 unsigned int pad_bytes = ETH_ZLEN - skb->len; 6656 6657 if (skb_pad(skb, pad_bytes)) 6658 goto out; 6659 skb_put(skb, pad_bytes); 6660 } 6661 6662 len = sizeof(struct tx_pkt_hdr) + 15; 6663 if (skb_headroom(skb) < len) { 6664 struct sk_buff *skb_new; 6665 6666 skb_new = skb_realloc_headroom(skb, len); 6667 if (!skb_new) { 6668 rp->tx_errors++; 6669 goto out_drop; 6670 } 6671 kfree_skb(skb); 6672 skb = skb_new; 6673 } else 6674 skb_orphan(skb); 6675 6676 align = ((unsigned long) skb->data & (16 - 1)); 6677 headroom = align + sizeof(struct tx_pkt_hdr); 6678 6679 ehdr = (struct ethhdr *) skb->data; 6680 tp = (struct tx_pkt_hdr *) skb_push(skb, headroom); 6681 6682 len = skb->len - sizeof(struct tx_pkt_hdr); 6683 tp->flags = cpu_to_le64(niu_compute_tx_flags(skb, ehdr, align, len)); 6684 tp->resv = 0; 6685 6686 len = skb_headlen(skb); 6687 mapping = np->ops->map_single(np->device, skb->data, 6688 len, DMA_TO_DEVICE); 6689 6690 prod = rp->prod; 6691 6692 rp->tx_buffs[prod].skb = skb; 6693 rp->tx_buffs[prod].mapping = mapping; 6694 6695 mrk = TX_DESC_SOP; 6696 if (++rp->mark_counter == rp->mark_freq) { 6697 rp->mark_counter = 0; 6698 mrk |= TX_DESC_MARK; 6699 rp->mark_pending++; 6700 } 6701 6702 tlen = len; 6703 nfg = skb_shinfo(skb)->nr_frags; 6704 while (tlen > 0) { 6705 tlen -= MAX_TX_DESC_LEN; 6706 nfg++; 6707 } 6708 6709 while (len > 0) { 6710 unsigned int this_len = len; 6711 6712 if (this_len > MAX_TX_DESC_LEN) 6713 this_len = MAX_TX_DESC_LEN; 6714 6715 niu_set_txd(rp, prod, mapping, this_len, mrk, nfg); 6716 mrk = nfg = 0; 6717 6718 prod = NEXT_TX(rp, prod); 6719 mapping += this_len; 6720 len -= this_len; 6721 } 6722 6723 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { 6724 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 6725 6726 len = skb_frag_size(frag); 6727 mapping = np->ops->map_page(np->device, skb_frag_page(frag), 6728 frag->page_offset, len, 6729 DMA_TO_DEVICE); 6730 6731 rp->tx_buffs[prod].skb = NULL; 6732 rp->tx_buffs[prod].mapping = mapping; 6733 6734 niu_set_txd(rp, prod, mapping, len, 0, 0); 6735 6736 prod = NEXT_TX(rp, prod); 6737 } 6738 6739 if (prod < rp->prod) 6740 rp->wrap_bit ^= TX_RING_KICK_WRAP; 6741 rp->prod = prod; 6742 6743 nw64(TX_RING_KICK(rp->tx_channel), rp->wrap_bit | (prod << 3)); 6744 6745 if (unlikely(niu_tx_avail(rp) <= (MAX_SKB_FRAGS + 1))) { 6746 netif_tx_stop_queue(txq); 6747 if (niu_tx_avail(rp) > NIU_TX_WAKEUP_THRESH(rp)) 6748 netif_tx_wake_queue(txq); 6749 } 6750 6751 out: 6752 return NETDEV_TX_OK; 6753 6754 out_drop: 6755 rp->tx_errors++; 6756 kfree_skb(skb); 6757 goto out; 6758 } 6759 6760 static int niu_change_mtu(struct net_device *dev, int new_mtu) 6761 { 6762 struct niu *np = netdev_priv(dev); 6763 int err, orig_jumbo, new_jumbo; 6764 6765 if (new_mtu < 68 || new_mtu > NIU_MAX_MTU) 6766 return -EINVAL; 6767 6768 orig_jumbo = (dev->mtu > ETH_DATA_LEN); 6769 new_jumbo = (new_mtu > ETH_DATA_LEN); 6770 6771 dev->mtu = new_mtu; 6772 6773 if (!netif_running(dev) || 6774 (orig_jumbo == new_jumbo)) 6775 return 0; 6776 6777 niu_full_shutdown(np, dev); 6778 6779 niu_free_channels(np); 6780 6781 niu_enable_napi(np); 6782 6783 err = niu_alloc_channels(np); 6784 if (err) 6785 return err; 6786 6787 spin_lock_irq(&np->lock); 6788 6789 err = niu_init_hw(np); 6790 if (!err) { 6791 init_timer(&np->timer); 6792 np->timer.expires = jiffies + HZ; 6793 np->timer.data = (unsigned long) np; 6794 np->timer.function = niu_timer; 6795 6796 err = niu_enable_interrupts(np, 1); 6797 if (err) 6798 niu_stop_hw(np); 6799 } 6800 6801 spin_unlock_irq(&np->lock); 6802 6803 if (!err) { 6804 netif_tx_start_all_queues(dev); 6805 if (np->link_config.loopback_mode != LOOPBACK_DISABLED) 6806 netif_carrier_on(dev); 6807 6808 add_timer(&np->timer); 6809 } 6810 6811 return err; 6812 } 6813 6814 static void niu_get_drvinfo(struct net_device *dev, 6815 struct ethtool_drvinfo *info) 6816 { 6817 struct niu *np = netdev_priv(dev); 6818 struct niu_vpd *vpd = &np->vpd; 6819 6820 strlcpy(info->driver, DRV_MODULE_NAME, sizeof(info->driver)); 6821 strlcpy(info->version, DRV_MODULE_VERSION, sizeof(info->version)); 6822 snprintf(info->fw_version, sizeof(info->fw_version), "%d.%d", 6823 vpd->fcode_major, vpd->fcode_minor); 6824 if (np->parent->plat_type != PLAT_TYPE_NIU) 6825 strlcpy(info->bus_info, pci_name(np->pdev), 6826 sizeof(info->bus_info)); 6827 } 6828 6829 static int niu_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) 6830 { 6831 struct niu *np = netdev_priv(dev); 6832 struct niu_link_config *lp; 6833 6834 lp = &np->link_config; 6835 6836 memset(cmd, 0, sizeof(*cmd)); 6837 cmd->phy_address = np->phy_addr; 6838 cmd->supported = lp->supported; 6839 cmd->advertising = lp->active_advertising; 6840 cmd->autoneg = lp->active_autoneg; 6841 ethtool_cmd_speed_set(cmd, lp->active_speed); 6842 cmd->duplex = lp->active_duplex; 6843 cmd->port = (np->flags & NIU_FLAGS_FIBER) ? PORT_FIBRE : PORT_TP; 6844 cmd->transceiver = (np->flags & NIU_FLAGS_XCVR_SERDES) ? 6845 XCVR_EXTERNAL : XCVR_INTERNAL; 6846 6847 return 0; 6848 } 6849 6850 static int niu_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) 6851 { 6852 struct niu *np = netdev_priv(dev); 6853 struct niu_link_config *lp = &np->link_config; 6854 6855 lp->advertising = cmd->advertising; 6856 lp->speed = ethtool_cmd_speed(cmd); 6857 lp->duplex = cmd->duplex; 6858 lp->autoneg = cmd->autoneg; 6859 return niu_init_link(np); 6860 } 6861 6862 static u32 niu_get_msglevel(struct net_device *dev) 6863 { 6864 struct niu *np = netdev_priv(dev); 6865 return np->msg_enable; 6866 } 6867 6868 static void niu_set_msglevel(struct net_device *dev, u32 value) 6869 { 6870 struct niu *np = netdev_priv(dev); 6871 np->msg_enable = value; 6872 } 6873 6874 static int niu_nway_reset(struct net_device *dev) 6875 { 6876 struct niu *np = netdev_priv(dev); 6877 6878 if (np->link_config.autoneg) 6879 return niu_init_link(np); 6880 6881 return 0; 6882 } 6883 6884 static int niu_get_eeprom_len(struct net_device *dev) 6885 { 6886 struct niu *np = netdev_priv(dev); 6887 6888 return np->eeprom_len; 6889 } 6890 6891 static int niu_get_eeprom(struct net_device *dev, 6892 struct ethtool_eeprom *eeprom, u8 *data) 6893 { 6894 struct niu *np = netdev_priv(dev); 6895 u32 offset, len, val; 6896 6897 offset = eeprom->offset; 6898 len = eeprom->len; 6899 6900 if (offset + len < offset) 6901 return -EINVAL; 6902 if (offset >= np->eeprom_len) 6903 return -EINVAL; 6904 if (offset + len > np->eeprom_len) 6905 len = eeprom->len = np->eeprom_len - offset; 6906 6907 if (offset & 3) { 6908 u32 b_offset, b_count; 6909 6910 b_offset = offset & 3; 6911 b_count = 4 - b_offset; 6912 if (b_count > len) 6913 b_count = len; 6914 6915 val = nr64(ESPC_NCR((offset - b_offset) / 4)); 6916 memcpy(data, ((char *)&val) + b_offset, b_count); 6917 data += b_count; 6918 len -= b_count; 6919 offset += b_count; 6920 } 6921 while (len >= 4) { 6922 val = nr64(ESPC_NCR(offset / 4)); 6923 memcpy(data, &val, 4); 6924 data += 4; 6925 len -= 4; 6926 offset += 4; 6927 } 6928 if (len) { 6929 val = nr64(ESPC_NCR(offset / 4)); 6930 memcpy(data, &val, len); 6931 } 6932 return 0; 6933 } 6934 6935 static void niu_ethflow_to_l3proto(int flow_type, u8 *pid) 6936 { 6937 switch (flow_type) { 6938 case TCP_V4_FLOW: 6939 case TCP_V6_FLOW: 6940 *pid = IPPROTO_TCP; 6941 break; 6942 case UDP_V4_FLOW: 6943 case UDP_V6_FLOW: 6944 *pid = IPPROTO_UDP; 6945 break; 6946 case SCTP_V4_FLOW: 6947 case SCTP_V6_FLOW: 6948 *pid = IPPROTO_SCTP; 6949 break; 6950 case AH_V4_FLOW: 6951 case AH_V6_FLOW: 6952 *pid = IPPROTO_AH; 6953 break; 6954 case ESP_V4_FLOW: 6955 case ESP_V6_FLOW: 6956 *pid = IPPROTO_ESP; 6957 break; 6958 default: 6959 *pid = 0; 6960 break; 6961 } 6962 } 6963 6964 static int niu_class_to_ethflow(u64 class, int *flow_type) 6965 { 6966 switch (class) { 6967 case CLASS_CODE_TCP_IPV4: 6968 *flow_type = TCP_V4_FLOW; 6969 break; 6970 case CLASS_CODE_UDP_IPV4: 6971 *flow_type = UDP_V4_FLOW; 6972 break; 6973 case CLASS_CODE_AH_ESP_IPV4: 6974 *flow_type = AH_V4_FLOW; 6975 break; 6976 case CLASS_CODE_SCTP_IPV4: 6977 *flow_type = SCTP_V4_FLOW; 6978 break; 6979 case CLASS_CODE_TCP_IPV6: 6980 *flow_type = TCP_V6_FLOW; 6981 break; 6982 case CLASS_CODE_UDP_IPV6: 6983 *flow_type = UDP_V6_FLOW; 6984 break; 6985 case CLASS_CODE_AH_ESP_IPV6: 6986 *flow_type = AH_V6_FLOW; 6987 break; 6988 case CLASS_CODE_SCTP_IPV6: 6989 *flow_type = SCTP_V6_FLOW; 6990 break; 6991 case CLASS_CODE_USER_PROG1: 6992 case CLASS_CODE_USER_PROG2: 6993 case CLASS_CODE_USER_PROG3: 6994 case CLASS_CODE_USER_PROG4: 6995 *flow_type = IP_USER_FLOW; 6996 break; 6997 default: 6998 return 0; 6999 } 7000 7001 return 1; 7002 } 7003 7004 static int niu_ethflow_to_class(int flow_type, u64 *class) 7005 { 7006 switch (flow_type) { 7007 case TCP_V4_FLOW: 7008 *class = CLASS_CODE_TCP_IPV4; 7009 break; 7010 case UDP_V4_FLOW: 7011 *class = CLASS_CODE_UDP_IPV4; 7012 break; 7013 case AH_ESP_V4_FLOW: 7014 case AH_V4_FLOW: 7015 case ESP_V4_FLOW: 7016 *class = CLASS_CODE_AH_ESP_IPV4; 7017 break; 7018 case SCTP_V4_FLOW: 7019 *class = CLASS_CODE_SCTP_IPV4; 7020 break; 7021 case TCP_V6_FLOW: 7022 *class = CLASS_CODE_TCP_IPV6; 7023 break; 7024 case UDP_V6_FLOW: 7025 *class = CLASS_CODE_UDP_IPV6; 7026 break; 7027 case AH_ESP_V6_FLOW: 7028 case AH_V6_FLOW: 7029 case ESP_V6_FLOW: 7030 *class = CLASS_CODE_AH_ESP_IPV6; 7031 break; 7032 case SCTP_V6_FLOW: 7033 *class = CLASS_CODE_SCTP_IPV6; 7034 break; 7035 default: 7036 return 0; 7037 } 7038 7039 return 1; 7040 } 7041 7042 static u64 niu_flowkey_to_ethflow(u64 flow_key) 7043 { 7044 u64 ethflow = 0; 7045 7046 if (flow_key & FLOW_KEY_L2DA) 7047 ethflow |= RXH_L2DA; 7048 if (flow_key & FLOW_KEY_VLAN) 7049 ethflow |= RXH_VLAN; 7050 if (flow_key & FLOW_KEY_IPSA) 7051 ethflow |= RXH_IP_SRC; 7052 if (flow_key & FLOW_KEY_IPDA) 7053 ethflow |= RXH_IP_DST; 7054 if (flow_key & FLOW_KEY_PROTO) 7055 ethflow |= RXH_L3_PROTO; 7056 if (flow_key & (FLOW_KEY_L4_BYTE12 << FLOW_KEY_L4_0_SHIFT)) 7057 ethflow |= RXH_L4_B_0_1; 7058 if (flow_key & (FLOW_KEY_L4_BYTE12 << FLOW_KEY_L4_1_SHIFT)) 7059 ethflow |= RXH_L4_B_2_3; 7060 7061 return ethflow; 7062 7063 } 7064 7065 static int niu_ethflow_to_flowkey(u64 ethflow, u64 *flow_key) 7066 { 7067 u64 key = 0; 7068 7069 if (ethflow & RXH_L2DA) 7070 key |= FLOW_KEY_L2DA; 7071 if (ethflow & RXH_VLAN) 7072 key |= FLOW_KEY_VLAN; 7073 if (ethflow & RXH_IP_SRC) 7074 key |= FLOW_KEY_IPSA; 7075 if (ethflow & RXH_IP_DST) 7076 key |= FLOW_KEY_IPDA; 7077 if (ethflow & RXH_L3_PROTO) 7078 key |= FLOW_KEY_PROTO; 7079 if (ethflow & RXH_L4_B_0_1) 7080 key |= (FLOW_KEY_L4_BYTE12 << FLOW_KEY_L4_0_SHIFT); 7081 if (ethflow & RXH_L4_B_2_3) 7082 key |= (FLOW_KEY_L4_BYTE12 << FLOW_KEY_L4_1_SHIFT); 7083 7084 *flow_key = key; 7085 7086 return 1; 7087 7088 } 7089 7090 static int niu_get_hash_opts(struct niu *np, struct ethtool_rxnfc *nfc) 7091 { 7092 u64 class; 7093 7094 nfc->data = 0; 7095 7096 if (!niu_ethflow_to_class(nfc->flow_type, &class)) 7097 return -EINVAL; 7098 7099 if (np->parent->tcam_key[class - CLASS_CODE_USER_PROG1] & 7100 TCAM_KEY_DISC) 7101 nfc->data = RXH_DISCARD; 7102 else 7103 nfc->data = niu_flowkey_to_ethflow(np->parent->flow_key[class - 7104 CLASS_CODE_USER_PROG1]); 7105 return 0; 7106 } 7107 7108 static void niu_get_ip4fs_from_tcam_key(struct niu_tcam_entry *tp, 7109 struct ethtool_rx_flow_spec *fsp) 7110 { 7111 u32 tmp; 7112 u16 prt; 7113 7114 tmp = (tp->key[3] & TCAM_V4KEY3_SADDR) >> TCAM_V4KEY3_SADDR_SHIFT; 7115 fsp->h_u.tcp_ip4_spec.ip4src = cpu_to_be32(tmp); 7116 7117 tmp = (tp->key[3] & TCAM_V4KEY3_DADDR) >> TCAM_V4KEY3_DADDR_SHIFT; 7118 fsp->h_u.tcp_ip4_spec.ip4dst = cpu_to_be32(tmp); 7119 7120 tmp = (tp->key_mask[3] & TCAM_V4KEY3_SADDR) >> TCAM_V4KEY3_SADDR_SHIFT; 7121 fsp->m_u.tcp_ip4_spec.ip4src = cpu_to_be32(tmp); 7122 7123 tmp = (tp->key_mask[3] & TCAM_V4KEY3_DADDR) >> TCAM_V4KEY3_DADDR_SHIFT; 7124 fsp->m_u.tcp_ip4_spec.ip4dst = cpu_to_be32(tmp); 7125 7126 fsp->h_u.tcp_ip4_spec.tos = (tp->key[2] & TCAM_V4KEY2_TOS) >> 7127 TCAM_V4KEY2_TOS_SHIFT; 7128 fsp->m_u.tcp_ip4_spec.tos = (tp->key_mask[2] & TCAM_V4KEY2_TOS) >> 7129 TCAM_V4KEY2_TOS_SHIFT; 7130 7131 switch (fsp->flow_type) { 7132 case TCP_V4_FLOW: 7133 case UDP_V4_FLOW: 7134 case SCTP_V4_FLOW: 7135 prt = ((tp->key[2] & TCAM_V4KEY2_PORT_SPI) >> 7136 TCAM_V4KEY2_PORT_SPI_SHIFT) >> 16; 7137 fsp->h_u.tcp_ip4_spec.psrc = cpu_to_be16(prt); 7138 7139 prt = ((tp->key[2] & TCAM_V4KEY2_PORT_SPI) >> 7140 TCAM_V4KEY2_PORT_SPI_SHIFT) & 0xffff; 7141 fsp->h_u.tcp_ip4_spec.pdst = cpu_to_be16(prt); 7142 7143 prt = ((tp->key_mask[2] & TCAM_V4KEY2_PORT_SPI) >> 7144 TCAM_V4KEY2_PORT_SPI_SHIFT) >> 16; 7145 fsp->m_u.tcp_ip4_spec.psrc = cpu_to_be16(prt); 7146 7147 prt = ((tp->key_mask[2] & TCAM_V4KEY2_PORT_SPI) >> 7148 TCAM_V4KEY2_PORT_SPI_SHIFT) & 0xffff; 7149 fsp->m_u.tcp_ip4_spec.pdst = cpu_to_be16(prt); 7150 break; 7151 case AH_V4_FLOW: 7152 case ESP_V4_FLOW: 7153 tmp = (tp->key[2] & TCAM_V4KEY2_PORT_SPI) >> 7154 TCAM_V4KEY2_PORT_SPI_SHIFT; 7155 fsp->h_u.ah_ip4_spec.spi = cpu_to_be32(tmp); 7156 7157 tmp = (tp->key_mask[2] & TCAM_V4KEY2_PORT_SPI) >> 7158 TCAM_V4KEY2_PORT_SPI_SHIFT; 7159 fsp->m_u.ah_ip4_spec.spi = cpu_to_be32(tmp); 7160 break; 7161 case IP_USER_FLOW: 7162 tmp = (tp->key[2] & TCAM_V4KEY2_PORT_SPI) >> 7163 TCAM_V4KEY2_PORT_SPI_SHIFT; 7164 fsp->h_u.usr_ip4_spec.l4_4_bytes = cpu_to_be32(tmp); 7165 7166 tmp = (tp->key_mask[2] & TCAM_V4KEY2_PORT_SPI) >> 7167 TCAM_V4KEY2_PORT_SPI_SHIFT; 7168 fsp->m_u.usr_ip4_spec.l4_4_bytes = cpu_to_be32(tmp); 7169 7170 fsp->h_u.usr_ip4_spec.proto = 7171 (tp->key[2] & TCAM_V4KEY2_PROTO) >> 7172 TCAM_V4KEY2_PROTO_SHIFT; 7173 fsp->m_u.usr_ip4_spec.proto = 7174 (tp->key_mask[2] & TCAM_V4KEY2_PROTO) >> 7175 TCAM_V4KEY2_PROTO_SHIFT; 7176 7177 fsp->h_u.usr_ip4_spec.ip_ver = ETH_RX_NFC_IP4; 7178 break; 7179 default: 7180 break; 7181 } 7182 } 7183 7184 static int niu_get_ethtool_tcam_entry(struct niu *np, 7185 struct ethtool_rxnfc *nfc) 7186 { 7187 struct niu_parent *parent = np->parent; 7188 struct niu_tcam_entry *tp; 7189 struct ethtool_rx_flow_spec *fsp = &nfc->fs; 7190 u16 idx; 7191 u64 class; 7192 int ret = 0; 7193 7194 idx = tcam_get_index(np, (u16)nfc->fs.location); 7195 7196 tp = &parent->tcam[idx]; 7197 if (!tp->valid) { 7198 netdev_info(np->dev, "niu%d: entry [%d] invalid for idx[%d]\n", 7199 parent->index, (u16)nfc->fs.location, idx); 7200 return -EINVAL; 7201 } 7202 7203 /* fill the flow spec entry */ 7204 class = (tp->key[0] & TCAM_V4KEY0_CLASS_CODE) >> 7205 TCAM_V4KEY0_CLASS_CODE_SHIFT; 7206 ret = niu_class_to_ethflow(class, &fsp->flow_type); 7207 7208 if (ret < 0) { 7209 netdev_info(np->dev, "niu%d: niu_class_to_ethflow failed\n", 7210 parent->index); 7211 ret = -EINVAL; 7212 goto out; 7213 } 7214 7215 if (fsp->flow_type == AH_V4_FLOW || fsp->flow_type == AH_V6_FLOW) { 7216 u32 proto = (tp->key[2] & TCAM_V4KEY2_PROTO) >> 7217 TCAM_V4KEY2_PROTO_SHIFT; 7218 if (proto == IPPROTO_ESP) { 7219 if (fsp->flow_type == AH_V4_FLOW) 7220 fsp->flow_type = ESP_V4_FLOW; 7221 else 7222 fsp->flow_type = ESP_V6_FLOW; 7223 } 7224 } 7225 7226 switch (fsp->flow_type) { 7227 case TCP_V4_FLOW: 7228 case UDP_V4_FLOW: 7229 case SCTP_V4_FLOW: 7230 case AH_V4_FLOW: 7231 case ESP_V4_FLOW: 7232 niu_get_ip4fs_from_tcam_key(tp, fsp); 7233 break; 7234 case TCP_V6_FLOW: 7235 case UDP_V6_FLOW: 7236 case SCTP_V6_FLOW: 7237 case AH_V6_FLOW: 7238 case ESP_V6_FLOW: 7239 /* Not yet implemented */ 7240 ret = -EINVAL; 7241 break; 7242 case IP_USER_FLOW: 7243 niu_get_ip4fs_from_tcam_key(tp, fsp); 7244 break; 7245 default: 7246 ret = -EINVAL; 7247 break; 7248 } 7249 7250 if (ret < 0) 7251 goto out; 7252 7253 if (tp->assoc_data & TCAM_ASSOCDATA_DISC) 7254 fsp->ring_cookie = RX_CLS_FLOW_DISC; 7255 else 7256 fsp->ring_cookie = (tp->assoc_data & TCAM_ASSOCDATA_OFFSET) >> 7257 TCAM_ASSOCDATA_OFFSET_SHIFT; 7258 7259 /* put the tcam size here */ 7260 nfc->data = tcam_get_size(np); 7261 out: 7262 return ret; 7263 } 7264 7265 static int niu_get_ethtool_tcam_all(struct niu *np, 7266 struct ethtool_rxnfc *nfc, 7267 u32 *rule_locs) 7268 { 7269 struct niu_parent *parent = np->parent; 7270 struct niu_tcam_entry *tp; 7271 int i, idx, cnt; 7272 unsigned long flags; 7273 int ret = 0; 7274 7275 /* put the tcam size here */ 7276 nfc->data = tcam_get_size(np); 7277 7278 niu_lock_parent(np, flags); 7279 for (cnt = 0, i = 0; i < nfc->data; i++) { 7280 idx = tcam_get_index(np, i); 7281 tp = &parent->tcam[idx]; 7282 if (!tp->valid) 7283 continue; 7284 if (cnt == nfc->rule_cnt) { 7285 ret = -EMSGSIZE; 7286 break; 7287 } 7288 rule_locs[cnt] = i; 7289 cnt++; 7290 } 7291 niu_unlock_parent(np, flags); 7292 7293 nfc->rule_cnt = cnt; 7294 7295 return ret; 7296 } 7297 7298 static int niu_get_nfc(struct net_device *dev, struct ethtool_rxnfc *cmd, 7299 u32 *rule_locs) 7300 { 7301 struct niu *np = netdev_priv(dev); 7302 int ret = 0; 7303 7304 switch (cmd->cmd) { 7305 case ETHTOOL_GRXFH: 7306 ret = niu_get_hash_opts(np, cmd); 7307 break; 7308 case ETHTOOL_GRXRINGS: 7309 cmd->data = np->num_rx_rings; 7310 break; 7311 case ETHTOOL_GRXCLSRLCNT: 7312 cmd->rule_cnt = tcam_get_valid_entry_cnt(np); 7313 break; 7314 case ETHTOOL_GRXCLSRULE: 7315 ret = niu_get_ethtool_tcam_entry(np, cmd); 7316 break; 7317 case ETHTOOL_GRXCLSRLALL: 7318 ret = niu_get_ethtool_tcam_all(np, cmd, rule_locs); 7319 break; 7320 default: 7321 ret = -EINVAL; 7322 break; 7323 } 7324 7325 return ret; 7326 } 7327 7328 static int niu_set_hash_opts(struct niu *np, struct ethtool_rxnfc *nfc) 7329 { 7330 u64 class; 7331 u64 flow_key = 0; 7332 unsigned long flags; 7333 7334 if (!niu_ethflow_to_class(nfc->flow_type, &class)) 7335 return -EINVAL; 7336 7337 if (class < CLASS_CODE_USER_PROG1 || 7338 class > CLASS_CODE_SCTP_IPV6) 7339 return -EINVAL; 7340 7341 if (nfc->data & RXH_DISCARD) { 7342 niu_lock_parent(np, flags); 7343 flow_key = np->parent->tcam_key[class - 7344 CLASS_CODE_USER_PROG1]; 7345 flow_key |= TCAM_KEY_DISC; 7346 nw64(TCAM_KEY(class - CLASS_CODE_USER_PROG1), flow_key); 7347 np->parent->tcam_key[class - CLASS_CODE_USER_PROG1] = flow_key; 7348 niu_unlock_parent(np, flags); 7349 return 0; 7350 } else { 7351 /* Discard was set before, but is not set now */ 7352 if (np->parent->tcam_key[class - CLASS_CODE_USER_PROG1] & 7353 TCAM_KEY_DISC) { 7354 niu_lock_parent(np, flags); 7355 flow_key = np->parent->tcam_key[class - 7356 CLASS_CODE_USER_PROG1]; 7357 flow_key &= ~TCAM_KEY_DISC; 7358 nw64(TCAM_KEY(class - CLASS_CODE_USER_PROG1), 7359 flow_key); 7360 np->parent->tcam_key[class - CLASS_CODE_USER_PROG1] = 7361 flow_key; 7362 niu_unlock_parent(np, flags); 7363 } 7364 } 7365 7366 if (!niu_ethflow_to_flowkey(nfc->data, &flow_key)) 7367 return -EINVAL; 7368 7369 niu_lock_parent(np, flags); 7370 nw64(FLOW_KEY(class - CLASS_CODE_USER_PROG1), flow_key); 7371 np->parent->flow_key[class - CLASS_CODE_USER_PROG1] = flow_key; 7372 niu_unlock_parent(np, flags); 7373 7374 return 0; 7375 } 7376 7377 static void niu_get_tcamkey_from_ip4fs(struct ethtool_rx_flow_spec *fsp, 7378 struct niu_tcam_entry *tp, 7379 int l2_rdc_tab, u64 class) 7380 { 7381 u8 pid = 0; 7382 u32 sip, dip, sipm, dipm, spi, spim; 7383 u16 sport, dport, spm, dpm; 7384 7385 sip = be32_to_cpu(fsp->h_u.tcp_ip4_spec.ip4src); 7386 sipm = be32_to_cpu(fsp->m_u.tcp_ip4_spec.ip4src); 7387 dip = be32_to_cpu(fsp->h_u.tcp_ip4_spec.ip4dst); 7388 dipm = be32_to_cpu(fsp->m_u.tcp_ip4_spec.ip4dst); 7389 7390 tp->key[0] = class << TCAM_V4KEY0_CLASS_CODE_SHIFT; 7391 tp->key_mask[0] = TCAM_V4KEY0_CLASS_CODE; 7392 tp->key[1] = (u64)l2_rdc_tab << TCAM_V4KEY1_L2RDCNUM_SHIFT; 7393 tp->key_mask[1] = TCAM_V4KEY1_L2RDCNUM; 7394 7395 tp->key[3] = (u64)sip << TCAM_V4KEY3_SADDR_SHIFT; 7396 tp->key[3] |= dip; 7397 7398 tp->key_mask[3] = (u64)sipm << TCAM_V4KEY3_SADDR_SHIFT; 7399 tp->key_mask[3] |= dipm; 7400 7401 tp->key[2] |= ((u64)fsp->h_u.tcp_ip4_spec.tos << 7402 TCAM_V4KEY2_TOS_SHIFT); 7403 tp->key_mask[2] |= ((u64)fsp->m_u.tcp_ip4_spec.tos << 7404 TCAM_V4KEY2_TOS_SHIFT); 7405 switch (fsp->flow_type) { 7406 case TCP_V4_FLOW: 7407 case UDP_V4_FLOW: 7408 case SCTP_V4_FLOW: 7409 sport = be16_to_cpu(fsp->h_u.tcp_ip4_spec.psrc); 7410 spm = be16_to_cpu(fsp->m_u.tcp_ip4_spec.psrc); 7411 dport = be16_to_cpu(fsp->h_u.tcp_ip4_spec.pdst); 7412 dpm = be16_to_cpu(fsp->m_u.tcp_ip4_spec.pdst); 7413 7414 tp->key[2] |= (((u64)sport << 16) | dport); 7415 tp->key_mask[2] |= (((u64)spm << 16) | dpm); 7416 niu_ethflow_to_l3proto(fsp->flow_type, &pid); 7417 break; 7418 case AH_V4_FLOW: 7419 case ESP_V4_FLOW: 7420 spi = be32_to_cpu(fsp->h_u.ah_ip4_spec.spi); 7421 spim = be32_to_cpu(fsp->m_u.ah_ip4_spec.spi); 7422 7423 tp->key[2] |= spi; 7424 tp->key_mask[2] |= spim; 7425 niu_ethflow_to_l3proto(fsp->flow_type, &pid); 7426 break; 7427 case IP_USER_FLOW: 7428 spi = be32_to_cpu(fsp->h_u.usr_ip4_spec.l4_4_bytes); 7429 spim = be32_to_cpu(fsp->m_u.usr_ip4_spec.l4_4_bytes); 7430 7431 tp->key[2] |= spi; 7432 tp->key_mask[2] |= spim; 7433 pid = fsp->h_u.usr_ip4_spec.proto; 7434 break; 7435 default: 7436 break; 7437 } 7438 7439 tp->key[2] |= ((u64)pid << TCAM_V4KEY2_PROTO_SHIFT); 7440 if (pid) { 7441 tp->key_mask[2] |= TCAM_V4KEY2_PROTO; 7442 } 7443 } 7444 7445 static int niu_add_ethtool_tcam_entry(struct niu *np, 7446 struct ethtool_rxnfc *nfc) 7447 { 7448 struct niu_parent *parent = np->parent; 7449 struct niu_tcam_entry *tp; 7450 struct ethtool_rx_flow_spec *fsp = &nfc->fs; 7451 struct niu_rdc_tables *rdc_table = &parent->rdc_group_cfg[np->port]; 7452 int l2_rdc_table = rdc_table->first_table_num; 7453 u16 idx; 7454 u64 class; 7455 unsigned long flags; 7456 int err, ret; 7457 7458 ret = 0; 7459 7460 idx = nfc->fs.location; 7461 if (idx >= tcam_get_size(np)) 7462 return -EINVAL; 7463 7464 if (fsp->flow_type == IP_USER_FLOW) { 7465 int i; 7466 int add_usr_cls = 0; 7467 struct ethtool_usrip4_spec *uspec = &fsp->h_u.usr_ip4_spec; 7468 struct ethtool_usrip4_spec *umask = &fsp->m_u.usr_ip4_spec; 7469 7470 if (uspec->ip_ver != ETH_RX_NFC_IP4) 7471 return -EINVAL; 7472 7473 niu_lock_parent(np, flags); 7474 7475 for (i = 0; i < NIU_L3_PROG_CLS; i++) { 7476 if (parent->l3_cls[i]) { 7477 if (uspec->proto == parent->l3_cls_pid[i]) { 7478 class = parent->l3_cls[i]; 7479 parent->l3_cls_refcnt[i]++; 7480 add_usr_cls = 1; 7481 break; 7482 } 7483 } else { 7484 /* Program new user IP class */ 7485 switch (i) { 7486 case 0: 7487 class = CLASS_CODE_USER_PROG1; 7488 break; 7489 case 1: 7490 class = CLASS_CODE_USER_PROG2; 7491 break; 7492 case 2: 7493 class = CLASS_CODE_USER_PROG3; 7494 break; 7495 case 3: 7496 class = CLASS_CODE_USER_PROG4; 7497 break; 7498 default: 7499 break; 7500 } 7501 ret = tcam_user_ip_class_set(np, class, 0, 7502 uspec->proto, 7503 uspec->tos, 7504 umask->tos); 7505 if (ret) 7506 goto out; 7507 7508 ret = tcam_user_ip_class_enable(np, class, 1); 7509 if (ret) 7510 goto out; 7511 parent->l3_cls[i] = class; 7512 parent->l3_cls_pid[i] = uspec->proto; 7513 parent->l3_cls_refcnt[i]++; 7514 add_usr_cls = 1; 7515 break; 7516 } 7517 } 7518 if (!add_usr_cls) { 7519 netdev_info(np->dev, "niu%d: %s(): Could not find/insert class for pid %d\n", 7520 parent->index, __func__, uspec->proto); 7521 ret = -EINVAL; 7522 goto out; 7523 } 7524 niu_unlock_parent(np, flags); 7525 } else { 7526 if (!niu_ethflow_to_class(fsp->flow_type, &class)) { 7527 return -EINVAL; 7528 } 7529 } 7530 7531 niu_lock_parent(np, flags); 7532 7533 idx = tcam_get_index(np, idx); 7534 tp = &parent->tcam[idx]; 7535 7536 memset(tp, 0, sizeof(*tp)); 7537 7538 /* fill in the tcam key and mask */ 7539 switch (fsp->flow_type) { 7540 case TCP_V4_FLOW: 7541 case UDP_V4_FLOW: 7542 case SCTP_V4_FLOW: 7543 case AH_V4_FLOW: 7544 case ESP_V4_FLOW: 7545 niu_get_tcamkey_from_ip4fs(fsp, tp, l2_rdc_table, class); 7546 break; 7547 case TCP_V6_FLOW: 7548 case UDP_V6_FLOW: 7549 case SCTP_V6_FLOW: 7550 case AH_V6_FLOW: 7551 case ESP_V6_FLOW: 7552 /* Not yet implemented */ 7553 netdev_info(np->dev, "niu%d: In %s(): flow %d for IPv6 not implemented\n", 7554 parent->index, __func__, fsp->flow_type); 7555 ret = -EINVAL; 7556 goto out; 7557 case IP_USER_FLOW: 7558 niu_get_tcamkey_from_ip4fs(fsp, tp, l2_rdc_table, class); 7559 break; 7560 default: 7561 netdev_info(np->dev, "niu%d: In %s(): Unknown flow type %d\n", 7562 parent->index, __func__, fsp->flow_type); 7563 ret = -EINVAL; 7564 goto out; 7565 } 7566 7567 /* fill in the assoc data */ 7568 if (fsp->ring_cookie == RX_CLS_FLOW_DISC) { 7569 tp->assoc_data = TCAM_ASSOCDATA_DISC; 7570 } else { 7571 if (fsp->ring_cookie >= np->num_rx_rings) { 7572 netdev_info(np->dev, "niu%d: In %s(): Invalid RX ring %lld\n", 7573 parent->index, __func__, 7574 (long long)fsp->ring_cookie); 7575 ret = -EINVAL; 7576 goto out; 7577 } 7578 tp->assoc_data = (TCAM_ASSOCDATA_TRES_USE_OFFSET | 7579 (fsp->ring_cookie << 7580 TCAM_ASSOCDATA_OFFSET_SHIFT)); 7581 } 7582 7583 err = tcam_write(np, idx, tp->key, tp->key_mask); 7584 if (err) { 7585 ret = -EINVAL; 7586 goto out; 7587 } 7588 err = tcam_assoc_write(np, idx, tp->assoc_data); 7589 if (err) { 7590 ret = -EINVAL; 7591 goto out; 7592 } 7593 7594 /* validate the entry */ 7595 tp->valid = 1; 7596 np->clas.tcam_valid_entries++; 7597 out: 7598 niu_unlock_parent(np, flags); 7599 7600 return ret; 7601 } 7602 7603 static int niu_del_ethtool_tcam_entry(struct niu *np, u32 loc) 7604 { 7605 struct niu_parent *parent = np->parent; 7606 struct niu_tcam_entry *tp; 7607 u16 idx; 7608 unsigned long flags; 7609 u64 class; 7610 int ret = 0; 7611 7612 if (loc >= tcam_get_size(np)) 7613 return -EINVAL; 7614 7615 niu_lock_parent(np, flags); 7616 7617 idx = tcam_get_index(np, loc); 7618 tp = &parent->tcam[idx]; 7619 7620 /* if the entry is of a user defined class, then update*/ 7621 class = (tp->key[0] & TCAM_V4KEY0_CLASS_CODE) >> 7622 TCAM_V4KEY0_CLASS_CODE_SHIFT; 7623 7624 if (class >= CLASS_CODE_USER_PROG1 && class <= CLASS_CODE_USER_PROG4) { 7625 int i; 7626 for (i = 0; i < NIU_L3_PROG_CLS; i++) { 7627 if (parent->l3_cls[i] == class) { 7628 parent->l3_cls_refcnt[i]--; 7629 if (!parent->l3_cls_refcnt[i]) { 7630 /* disable class */ 7631 ret = tcam_user_ip_class_enable(np, 7632 class, 7633 0); 7634 if (ret) 7635 goto out; 7636 parent->l3_cls[i] = 0; 7637 parent->l3_cls_pid[i] = 0; 7638 } 7639 break; 7640 } 7641 } 7642 if (i == NIU_L3_PROG_CLS) { 7643 netdev_info(np->dev, "niu%d: In %s(): Usr class 0x%llx not found\n", 7644 parent->index, __func__, 7645 (unsigned long long)class); 7646 ret = -EINVAL; 7647 goto out; 7648 } 7649 } 7650 7651 ret = tcam_flush(np, idx); 7652 if (ret) 7653 goto out; 7654 7655 /* invalidate the entry */ 7656 tp->valid = 0; 7657 np->clas.tcam_valid_entries--; 7658 out: 7659 niu_unlock_parent(np, flags); 7660 7661 return ret; 7662 } 7663 7664 static int niu_set_nfc(struct net_device *dev, struct ethtool_rxnfc *cmd) 7665 { 7666 struct niu *np = netdev_priv(dev); 7667 int ret = 0; 7668 7669 switch (cmd->cmd) { 7670 case ETHTOOL_SRXFH: 7671 ret = niu_set_hash_opts(np, cmd); 7672 break; 7673 case ETHTOOL_SRXCLSRLINS: 7674 ret = niu_add_ethtool_tcam_entry(np, cmd); 7675 break; 7676 case ETHTOOL_SRXCLSRLDEL: 7677 ret = niu_del_ethtool_tcam_entry(np, cmd->fs.location); 7678 break; 7679 default: 7680 ret = -EINVAL; 7681 break; 7682 } 7683 7684 return ret; 7685 } 7686 7687 static const struct { 7688 const char string[ETH_GSTRING_LEN]; 7689 } niu_xmac_stat_keys[] = { 7690 { "tx_frames" }, 7691 { "tx_bytes" }, 7692 { "tx_fifo_errors" }, 7693 { "tx_overflow_errors" }, 7694 { "tx_max_pkt_size_errors" }, 7695 { "tx_underflow_errors" }, 7696 { "rx_local_faults" }, 7697 { "rx_remote_faults" }, 7698 { "rx_link_faults" }, 7699 { "rx_align_errors" }, 7700 { "rx_frags" }, 7701 { "rx_mcasts" }, 7702 { "rx_bcasts" }, 7703 { "rx_hist_cnt1" }, 7704 { "rx_hist_cnt2" }, 7705 { "rx_hist_cnt3" }, 7706 { "rx_hist_cnt4" }, 7707 { "rx_hist_cnt5" }, 7708 { "rx_hist_cnt6" }, 7709 { "rx_hist_cnt7" }, 7710 { "rx_octets" }, 7711 { "rx_code_violations" }, 7712 { "rx_len_errors" }, 7713 { "rx_crc_errors" }, 7714 { "rx_underflows" }, 7715 { "rx_overflows" }, 7716 { "pause_off_state" }, 7717 { "pause_on_state" }, 7718 { "pause_received" }, 7719 }; 7720 7721 #define NUM_XMAC_STAT_KEYS ARRAY_SIZE(niu_xmac_stat_keys) 7722 7723 static const struct { 7724 const char string[ETH_GSTRING_LEN]; 7725 } niu_bmac_stat_keys[] = { 7726 { "tx_underflow_errors" }, 7727 { "tx_max_pkt_size_errors" }, 7728 { "tx_bytes" }, 7729 { "tx_frames" }, 7730 { "rx_overflows" }, 7731 { "rx_frames" }, 7732 { "rx_align_errors" }, 7733 { "rx_crc_errors" }, 7734 { "rx_len_errors" }, 7735 { "pause_off_state" }, 7736 { "pause_on_state" }, 7737 { "pause_received" }, 7738 }; 7739 7740 #define NUM_BMAC_STAT_KEYS ARRAY_SIZE(niu_bmac_stat_keys) 7741 7742 static const struct { 7743 const char string[ETH_GSTRING_LEN]; 7744 } niu_rxchan_stat_keys[] = { 7745 { "rx_channel" }, 7746 { "rx_packets" }, 7747 { "rx_bytes" }, 7748 { "rx_dropped" }, 7749 { "rx_errors" }, 7750 }; 7751 7752 #define NUM_RXCHAN_STAT_KEYS ARRAY_SIZE(niu_rxchan_stat_keys) 7753 7754 static const struct { 7755 const char string[ETH_GSTRING_LEN]; 7756 } niu_txchan_stat_keys[] = { 7757 { "tx_channel" }, 7758 { "tx_packets" }, 7759 { "tx_bytes" }, 7760 { "tx_errors" }, 7761 }; 7762 7763 #define NUM_TXCHAN_STAT_KEYS ARRAY_SIZE(niu_txchan_stat_keys) 7764 7765 static void niu_get_strings(struct net_device *dev, u32 stringset, u8 *data) 7766 { 7767 struct niu *np = netdev_priv(dev); 7768 int i; 7769 7770 if (stringset != ETH_SS_STATS) 7771 return; 7772 7773 if (np->flags & NIU_FLAGS_XMAC) { 7774 memcpy(data, niu_xmac_stat_keys, 7775 sizeof(niu_xmac_stat_keys)); 7776 data += sizeof(niu_xmac_stat_keys); 7777 } else { 7778 memcpy(data, niu_bmac_stat_keys, 7779 sizeof(niu_bmac_stat_keys)); 7780 data += sizeof(niu_bmac_stat_keys); 7781 } 7782 for (i = 0; i < np->num_rx_rings; i++) { 7783 memcpy(data, niu_rxchan_stat_keys, 7784 sizeof(niu_rxchan_stat_keys)); 7785 data += sizeof(niu_rxchan_stat_keys); 7786 } 7787 for (i = 0; i < np->num_tx_rings; i++) { 7788 memcpy(data, niu_txchan_stat_keys, 7789 sizeof(niu_txchan_stat_keys)); 7790 data += sizeof(niu_txchan_stat_keys); 7791 } 7792 } 7793 7794 static int niu_get_sset_count(struct net_device *dev, int stringset) 7795 { 7796 struct niu *np = netdev_priv(dev); 7797 7798 if (stringset != ETH_SS_STATS) 7799 return -EINVAL; 7800 7801 return (np->flags & NIU_FLAGS_XMAC ? 7802 NUM_XMAC_STAT_KEYS : 7803 NUM_BMAC_STAT_KEYS) + 7804 (np->num_rx_rings * NUM_RXCHAN_STAT_KEYS) + 7805 (np->num_tx_rings * NUM_TXCHAN_STAT_KEYS); 7806 } 7807 7808 static void niu_get_ethtool_stats(struct net_device *dev, 7809 struct ethtool_stats *stats, u64 *data) 7810 { 7811 struct niu *np = netdev_priv(dev); 7812 int i; 7813 7814 niu_sync_mac_stats(np); 7815 if (np->flags & NIU_FLAGS_XMAC) { 7816 memcpy(data, &np->mac_stats.xmac, 7817 sizeof(struct niu_xmac_stats)); 7818 data += (sizeof(struct niu_xmac_stats) / sizeof(u64)); 7819 } else { 7820 memcpy(data, &np->mac_stats.bmac, 7821 sizeof(struct niu_bmac_stats)); 7822 data += (sizeof(struct niu_bmac_stats) / sizeof(u64)); 7823 } 7824 for (i = 0; i < np->num_rx_rings; i++) { 7825 struct rx_ring_info *rp = &np->rx_rings[i]; 7826 7827 niu_sync_rx_discard_stats(np, rp, 0); 7828 7829 data[0] = rp->rx_channel; 7830 data[1] = rp->rx_packets; 7831 data[2] = rp->rx_bytes; 7832 data[3] = rp->rx_dropped; 7833 data[4] = rp->rx_errors; 7834 data += 5; 7835 } 7836 for (i = 0; i < np->num_tx_rings; i++) { 7837 struct tx_ring_info *rp = &np->tx_rings[i]; 7838 7839 data[0] = rp->tx_channel; 7840 data[1] = rp->tx_packets; 7841 data[2] = rp->tx_bytes; 7842 data[3] = rp->tx_errors; 7843 data += 4; 7844 } 7845 } 7846 7847 static u64 niu_led_state_save(struct niu *np) 7848 { 7849 if (np->flags & NIU_FLAGS_XMAC) 7850 return nr64_mac(XMAC_CONFIG); 7851 else 7852 return nr64_mac(BMAC_XIF_CONFIG); 7853 } 7854 7855 static void niu_led_state_restore(struct niu *np, u64 val) 7856 { 7857 if (np->flags & NIU_FLAGS_XMAC) 7858 nw64_mac(XMAC_CONFIG, val); 7859 else 7860 nw64_mac(BMAC_XIF_CONFIG, val); 7861 } 7862 7863 static void niu_force_led(struct niu *np, int on) 7864 { 7865 u64 val, reg, bit; 7866 7867 if (np->flags & NIU_FLAGS_XMAC) { 7868 reg = XMAC_CONFIG; 7869 bit = XMAC_CONFIG_FORCE_LED_ON; 7870 } else { 7871 reg = BMAC_XIF_CONFIG; 7872 bit = BMAC_XIF_CONFIG_LINK_LED; 7873 } 7874 7875 val = nr64_mac(reg); 7876 if (on) 7877 val |= bit; 7878 else 7879 val &= ~bit; 7880 nw64_mac(reg, val); 7881 } 7882 7883 static int niu_set_phys_id(struct net_device *dev, 7884 enum ethtool_phys_id_state state) 7885 7886 { 7887 struct niu *np = netdev_priv(dev); 7888 7889 if (!netif_running(dev)) 7890 return -EAGAIN; 7891 7892 switch (state) { 7893 case ETHTOOL_ID_ACTIVE: 7894 np->orig_led_state = niu_led_state_save(np); 7895 return 1; /* cycle on/off once per second */ 7896 7897 case ETHTOOL_ID_ON: 7898 niu_force_led(np, 1); 7899 break; 7900 7901 case ETHTOOL_ID_OFF: 7902 niu_force_led(np, 0); 7903 break; 7904 7905 case ETHTOOL_ID_INACTIVE: 7906 niu_led_state_restore(np, np->orig_led_state); 7907 } 7908 7909 return 0; 7910 } 7911 7912 static const struct ethtool_ops niu_ethtool_ops = { 7913 .get_drvinfo = niu_get_drvinfo, 7914 .get_link = ethtool_op_get_link, 7915 .get_msglevel = niu_get_msglevel, 7916 .set_msglevel = niu_set_msglevel, 7917 .nway_reset = niu_nway_reset, 7918 .get_eeprom_len = niu_get_eeprom_len, 7919 .get_eeprom = niu_get_eeprom, 7920 .get_settings = niu_get_settings, 7921 .set_settings = niu_set_settings, 7922 .get_strings = niu_get_strings, 7923 .get_sset_count = niu_get_sset_count, 7924 .get_ethtool_stats = niu_get_ethtool_stats, 7925 .set_phys_id = niu_set_phys_id, 7926 .get_rxnfc = niu_get_nfc, 7927 .set_rxnfc = niu_set_nfc, 7928 }; 7929 7930 static int niu_ldg_assign_ldn(struct niu *np, struct niu_parent *parent, 7931 int ldg, int ldn) 7932 { 7933 if (ldg < NIU_LDG_MIN || ldg > NIU_LDG_MAX) 7934 return -EINVAL; 7935 if (ldn < 0 || ldn > LDN_MAX) 7936 return -EINVAL; 7937 7938 parent->ldg_map[ldn] = ldg; 7939 7940 if (np->parent->plat_type == PLAT_TYPE_NIU) { 7941 /* On N2 NIU, the ldn-->ldg assignments are setup and fixed by 7942 * the firmware, and we're not supposed to change them. 7943 * Validate the mapping, because if it's wrong we probably 7944 * won't get any interrupts and that's painful to debug. 7945 */ 7946 if (nr64(LDG_NUM(ldn)) != ldg) { 7947 dev_err(np->device, "Port %u, mis-matched LDG assignment for ldn %d, should be %d is %llu\n", 7948 np->port, ldn, ldg, 7949 (unsigned long long) nr64(LDG_NUM(ldn))); 7950 return -EINVAL; 7951 } 7952 } else 7953 nw64(LDG_NUM(ldn), ldg); 7954 7955 return 0; 7956 } 7957 7958 static int niu_set_ldg_timer_res(struct niu *np, int res) 7959 { 7960 if (res < 0 || res > LDG_TIMER_RES_VAL) 7961 return -EINVAL; 7962 7963 7964 nw64(LDG_TIMER_RES, res); 7965 7966 return 0; 7967 } 7968 7969 static int niu_set_ldg_sid(struct niu *np, int ldg, int func, int vector) 7970 { 7971 if ((ldg < NIU_LDG_MIN || ldg > NIU_LDG_MAX) || 7972 (func < 0 || func > 3) || 7973 (vector < 0 || vector > 0x1f)) 7974 return -EINVAL; 7975 7976 nw64(SID(ldg), (func << SID_FUNC_SHIFT) | vector); 7977 7978 return 0; 7979 } 7980 7981 static int niu_pci_eeprom_read(struct niu *np, u32 addr) 7982 { 7983 u64 frame, frame_base = (ESPC_PIO_STAT_READ_START | 7984 (addr << ESPC_PIO_STAT_ADDR_SHIFT)); 7985 int limit; 7986 7987 if (addr > (ESPC_PIO_STAT_ADDR >> ESPC_PIO_STAT_ADDR_SHIFT)) 7988 return -EINVAL; 7989 7990 frame = frame_base; 7991 nw64(ESPC_PIO_STAT, frame); 7992 limit = 64; 7993 do { 7994 udelay(5); 7995 frame = nr64(ESPC_PIO_STAT); 7996 if (frame & ESPC_PIO_STAT_READ_END) 7997 break; 7998 } while (limit--); 7999 if (!(frame & ESPC_PIO_STAT_READ_END)) { 8000 dev_err(np->device, "EEPROM read timeout frame[%llx]\n", 8001 (unsigned long long) frame); 8002 return -ENODEV; 8003 } 8004 8005 frame = frame_base; 8006 nw64(ESPC_PIO_STAT, frame); 8007 limit = 64; 8008 do { 8009 udelay(5); 8010 frame = nr64(ESPC_PIO_STAT); 8011 if (frame & ESPC_PIO_STAT_READ_END) 8012 break; 8013 } while (limit--); 8014 if (!(frame & ESPC_PIO_STAT_READ_END)) { 8015 dev_err(np->device, "EEPROM read timeout frame[%llx]\n", 8016 (unsigned long long) frame); 8017 return -ENODEV; 8018 } 8019 8020 frame = nr64(ESPC_PIO_STAT); 8021 return (frame & ESPC_PIO_STAT_DATA) >> ESPC_PIO_STAT_DATA_SHIFT; 8022 } 8023 8024 static int niu_pci_eeprom_read16(struct niu *np, u32 off) 8025 { 8026 int err = niu_pci_eeprom_read(np, off); 8027 u16 val; 8028 8029 if (err < 0) 8030 return err; 8031 val = (err << 8); 8032 err = niu_pci_eeprom_read(np, off + 1); 8033 if (err < 0) 8034 return err; 8035 val |= (err & 0xff); 8036 8037 return val; 8038 } 8039 8040 static int niu_pci_eeprom_read16_swp(struct niu *np, u32 off) 8041 { 8042 int err = niu_pci_eeprom_read(np, off); 8043 u16 val; 8044 8045 if (err < 0) 8046 return err; 8047 8048 val = (err & 0xff); 8049 err = niu_pci_eeprom_read(np, off + 1); 8050 if (err < 0) 8051 return err; 8052 8053 val |= (err & 0xff) << 8; 8054 8055 return val; 8056 } 8057 8058 static int niu_pci_vpd_get_propname(struct niu *np, u32 off, char *namebuf, 8059 int namebuf_len) 8060 { 8061 int i; 8062 8063 for (i = 0; i < namebuf_len; i++) { 8064 int err = niu_pci_eeprom_read(np, off + i); 8065 if (err < 0) 8066 return err; 8067 *namebuf++ = err; 8068 if (!err) 8069 break; 8070 } 8071 if (i >= namebuf_len) 8072 return -EINVAL; 8073 8074 return i + 1; 8075 } 8076 8077 static void niu_vpd_parse_version(struct niu *np) 8078 { 8079 struct niu_vpd *vpd = &np->vpd; 8080 int len = strlen(vpd->version) + 1; 8081 const char *s = vpd->version; 8082 int i; 8083 8084 for (i = 0; i < len - 5; i++) { 8085 if (!strncmp(s + i, "FCode ", 6)) 8086 break; 8087 } 8088 if (i >= len - 5) 8089 return; 8090 8091 s += i + 5; 8092 sscanf(s, "%d.%d", &vpd->fcode_major, &vpd->fcode_minor); 8093 8094 netif_printk(np, probe, KERN_DEBUG, np->dev, 8095 "VPD_SCAN: FCODE major(%d) minor(%d)\n", 8096 vpd->fcode_major, vpd->fcode_minor); 8097 if (vpd->fcode_major > NIU_VPD_MIN_MAJOR || 8098 (vpd->fcode_major == NIU_VPD_MIN_MAJOR && 8099 vpd->fcode_minor >= NIU_VPD_MIN_MINOR)) 8100 np->flags |= NIU_FLAGS_VPD_VALID; 8101 } 8102 8103 /* ESPC_PIO_EN_ENABLE must be set */ 8104 static int niu_pci_vpd_scan_props(struct niu *np, u32 start, u32 end) 8105 { 8106 unsigned int found_mask = 0; 8107 #define FOUND_MASK_MODEL 0x00000001 8108 #define FOUND_MASK_BMODEL 0x00000002 8109 #define FOUND_MASK_VERS 0x00000004 8110 #define FOUND_MASK_MAC 0x00000008 8111 #define FOUND_MASK_NMAC 0x00000010 8112 #define FOUND_MASK_PHY 0x00000020 8113 #define FOUND_MASK_ALL 0x0000003f 8114 8115 netif_printk(np, probe, KERN_DEBUG, np->dev, 8116 "VPD_SCAN: start[%x] end[%x]\n", start, end); 8117 while (start < end) { 8118 int len, err, prop_len; 8119 char namebuf[64]; 8120 u8 *prop_buf; 8121 int max_len; 8122 8123 if (found_mask == FOUND_MASK_ALL) { 8124 niu_vpd_parse_version(np); 8125 return 1; 8126 } 8127 8128 err = niu_pci_eeprom_read(np, start + 2); 8129 if (err < 0) 8130 return err; 8131 len = err; 8132 start += 3; 8133 8134 prop_len = niu_pci_eeprom_read(np, start + 4); 8135 err = niu_pci_vpd_get_propname(np, start + 5, namebuf, 64); 8136 if (err < 0) 8137 return err; 8138 8139 prop_buf = NULL; 8140 max_len = 0; 8141 if (!strcmp(namebuf, "model")) { 8142 prop_buf = np->vpd.model; 8143 max_len = NIU_VPD_MODEL_MAX; 8144 found_mask |= FOUND_MASK_MODEL; 8145 } else if (!strcmp(namebuf, "board-model")) { 8146 prop_buf = np->vpd.board_model; 8147 max_len = NIU_VPD_BD_MODEL_MAX; 8148 found_mask |= FOUND_MASK_BMODEL; 8149 } else if (!strcmp(namebuf, "version")) { 8150 prop_buf = np->vpd.version; 8151 max_len = NIU_VPD_VERSION_MAX; 8152 found_mask |= FOUND_MASK_VERS; 8153 } else if (!strcmp(namebuf, "local-mac-address")) { 8154 prop_buf = np->vpd.local_mac; 8155 max_len = ETH_ALEN; 8156 found_mask |= FOUND_MASK_MAC; 8157 } else if (!strcmp(namebuf, "num-mac-addresses")) { 8158 prop_buf = &np->vpd.mac_num; 8159 max_len = 1; 8160 found_mask |= FOUND_MASK_NMAC; 8161 } else if (!strcmp(namebuf, "phy-type")) { 8162 prop_buf = np->vpd.phy_type; 8163 max_len = NIU_VPD_PHY_TYPE_MAX; 8164 found_mask |= FOUND_MASK_PHY; 8165 } 8166 8167 if (max_len && prop_len > max_len) { 8168 dev_err(np->device, "Property '%s' length (%d) is too long\n", namebuf, prop_len); 8169 return -EINVAL; 8170 } 8171 8172 if (prop_buf) { 8173 u32 off = start + 5 + err; 8174 int i; 8175 8176 netif_printk(np, probe, KERN_DEBUG, np->dev, 8177 "VPD_SCAN: Reading in property [%s] len[%d]\n", 8178 namebuf, prop_len); 8179 for (i = 0; i < prop_len; i++) 8180 *prop_buf++ = niu_pci_eeprom_read(np, off + i); 8181 } 8182 8183 start += len; 8184 } 8185 8186 return 0; 8187 } 8188 8189 /* ESPC_PIO_EN_ENABLE must be set */ 8190 static void niu_pci_vpd_fetch(struct niu *np, u32 start) 8191 { 8192 u32 offset; 8193 int err; 8194 8195 err = niu_pci_eeprom_read16_swp(np, start + 1); 8196 if (err < 0) 8197 return; 8198 8199 offset = err + 3; 8200 8201 while (start + offset < ESPC_EEPROM_SIZE) { 8202 u32 here = start + offset; 8203 u32 end; 8204 8205 err = niu_pci_eeprom_read(np, here); 8206 if (err != 0x90) 8207 return; 8208 8209 err = niu_pci_eeprom_read16_swp(np, here + 1); 8210 if (err < 0) 8211 return; 8212 8213 here = start + offset + 3; 8214 end = start + offset + err; 8215 8216 offset += err; 8217 8218 err = niu_pci_vpd_scan_props(np, here, end); 8219 if (err < 0 || err == 1) 8220 return; 8221 } 8222 } 8223 8224 /* ESPC_PIO_EN_ENABLE must be set */ 8225 static u32 niu_pci_vpd_offset(struct niu *np) 8226 { 8227 u32 start = 0, end = ESPC_EEPROM_SIZE, ret; 8228 int err; 8229 8230 while (start < end) { 8231 ret = start; 8232 8233 /* ROM header signature? */ 8234 err = niu_pci_eeprom_read16(np, start + 0); 8235 if (err != 0x55aa) 8236 return 0; 8237 8238 /* Apply offset to PCI data structure. */ 8239 err = niu_pci_eeprom_read16(np, start + 23); 8240 if (err < 0) 8241 return 0; 8242 start += err; 8243 8244 /* Check for "PCIR" signature. */ 8245 err = niu_pci_eeprom_read16(np, start + 0); 8246 if (err != 0x5043) 8247 return 0; 8248 err = niu_pci_eeprom_read16(np, start + 2); 8249 if (err != 0x4952) 8250 return 0; 8251 8252 /* Check for OBP image type. */ 8253 err = niu_pci_eeprom_read(np, start + 20); 8254 if (err < 0) 8255 return 0; 8256 if (err != 0x01) { 8257 err = niu_pci_eeprom_read(np, ret + 2); 8258 if (err < 0) 8259 return 0; 8260 8261 start = ret + (err * 512); 8262 continue; 8263 } 8264 8265 err = niu_pci_eeprom_read16_swp(np, start + 8); 8266 if (err < 0) 8267 return err; 8268 ret += err; 8269 8270 err = niu_pci_eeprom_read(np, ret + 0); 8271 if (err != 0x82) 8272 return 0; 8273 8274 return ret; 8275 } 8276 8277 return 0; 8278 } 8279 8280 static int niu_phy_type_prop_decode(struct niu *np, const char *phy_prop) 8281 { 8282 if (!strcmp(phy_prop, "mif")) { 8283 /* 1G copper, MII */ 8284 np->flags &= ~(NIU_FLAGS_FIBER | 8285 NIU_FLAGS_10G); 8286 np->mac_xcvr = MAC_XCVR_MII; 8287 } else if (!strcmp(phy_prop, "xgf")) { 8288 /* 10G fiber, XPCS */ 8289 np->flags |= (NIU_FLAGS_10G | 8290 NIU_FLAGS_FIBER); 8291 np->mac_xcvr = MAC_XCVR_XPCS; 8292 } else if (!strcmp(phy_prop, "pcs")) { 8293 /* 1G fiber, PCS */ 8294 np->flags &= ~NIU_FLAGS_10G; 8295 np->flags |= NIU_FLAGS_FIBER; 8296 np->mac_xcvr = MAC_XCVR_PCS; 8297 } else if (!strcmp(phy_prop, "xgc")) { 8298 /* 10G copper, XPCS */ 8299 np->flags |= NIU_FLAGS_10G; 8300 np->flags &= ~NIU_FLAGS_FIBER; 8301 np->mac_xcvr = MAC_XCVR_XPCS; 8302 } else if (!strcmp(phy_prop, "xgsd") || !strcmp(phy_prop, "gsd")) { 8303 /* 10G Serdes or 1G Serdes, default to 10G */ 8304 np->flags |= NIU_FLAGS_10G; 8305 np->flags &= ~NIU_FLAGS_FIBER; 8306 np->flags |= NIU_FLAGS_XCVR_SERDES; 8307 np->mac_xcvr = MAC_XCVR_XPCS; 8308 } else { 8309 return -EINVAL; 8310 } 8311 return 0; 8312 } 8313 8314 static int niu_pci_vpd_get_nports(struct niu *np) 8315 { 8316 int ports = 0; 8317 8318 if ((!strcmp(np->vpd.model, NIU_QGC_LP_MDL_STR)) || 8319 (!strcmp(np->vpd.model, NIU_QGC_PEM_MDL_STR)) || 8320 (!strcmp(np->vpd.model, NIU_MARAMBA_MDL_STR)) || 8321 (!strcmp(np->vpd.model, NIU_KIMI_MDL_STR)) || 8322 (!strcmp(np->vpd.model, NIU_ALONSO_MDL_STR))) { 8323 ports = 4; 8324 } else if ((!strcmp(np->vpd.model, NIU_2XGF_LP_MDL_STR)) || 8325 (!strcmp(np->vpd.model, NIU_2XGF_PEM_MDL_STR)) || 8326 (!strcmp(np->vpd.model, NIU_FOXXY_MDL_STR)) || 8327 (!strcmp(np->vpd.model, NIU_2XGF_MRVL_MDL_STR))) { 8328 ports = 2; 8329 } 8330 8331 return ports; 8332 } 8333 8334 static void niu_pci_vpd_validate(struct niu *np) 8335 { 8336 struct net_device *dev = np->dev; 8337 struct niu_vpd *vpd = &np->vpd; 8338 u8 val8; 8339 8340 if (!is_valid_ether_addr(&vpd->local_mac[0])) { 8341 dev_err(np->device, "VPD MAC invalid, falling back to SPROM\n"); 8342 8343 np->flags &= ~NIU_FLAGS_VPD_VALID; 8344 return; 8345 } 8346 8347 if (!strcmp(np->vpd.model, NIU_ALONSO_MDL_STR) || 8348 !strcmp(np->vpd.model, NIU_KIMI_MDL_STR)) { 8349 np->flags |= NIU_FLAGS_10G; 8350 np->flags &= ~NIU_FLAGS_FIBER; 8351 np->flags |= NIU_FLAGS_XCVR_SERDES; 8352 np->mac_xcvr = MAC_XCVR_PCS; 8353 if (np->port > 1) { 8354 np->flags |= NIU_FLAGS_FIBER; 8355 np->flags &= ~NIU_FLAGS_10G; 8356 } 8357 if (np->flags & NIU_FLAGS_10G) 8358 np->mac_xcvr = MAC_XCVR_XPCS; 8359 } else if (!strcmp(np->vpd.model, NIU_FOXXY_MDL_STR)) { 8360 np->flags |= (NIU_FLAGS_10G | NIU_FLAGS_FIBER | 8361 NIU_FLAGS_HOTPLUG_PHY); 8362 } else if (niu_phy_type_prop_decode(np, np->vpd.phy_type)) { 8363 dev_err(np->device, "Illegal phy string [%s]\n", 8364 np->vpd.phy_type); 8365 dev_err(np->device, "Falling back to SPROM\n"); 8366 np->flags &= ~NIU_FLAGS_VPD_VALID; 8367 return; 8368 } 8369 8370 memcpy(dev->dev_addr, vpd->local_mac, ETH_ALEN); 8371 8372 val8 = dev->dev_addr[5]; 8373 dev->dev_addr[5] += np->port; 8374 if (dev->dev_addr[5] < val8) 8375 dev->dev_addr[4]++; 8376 } 8377 8378 static int niu_pci_probe_sprom(struct niu *np) 8379 { 8380 struct net_device *dev = np->dev; 8381 int len, i; 8382 u64 val, sum; 8383 u8 val8; 8384 8385 val = (nr64(ESPC_VER_IMGSZ) & ESPC_VER_IMGSZ_IMGSZ); 8386 val >>= ESPC_VER_IMGSZ_IMGSZ_SHIFT; 8387 len = val / 4; 8388 8389 np->eeprom_len = len; 8390 8391 netif_printk(np, probe, KERN_DEBUG, np->dev, 8392 "SPROM: Image size %llu\n", (unsigned long long)val); 8393 8394 sum = 0; 8395 for (i = 0; i < len; i++) { 8396 val = nr64(ESPC_NCR(i)); 8397 sum += (val >> 0) & 0xff; 8398 sum += (val >> 8) & 0xff; 8399 sum += (val >> 16) & 0xff; 8400 sum += (val >> 24) & 0xff; 8401 } 8402 netif_printk(np, probe, KERN_DEBUG, np->dev, 8403 "SPROM: Checksum %x\n", (int)(sum & 0xff)); 8404 if ((sum & 0xff) != 0xab) { 8405 dev_err(np->device, "Bad SPROM checksum (%x, should be 0xab)\n", (int)(sum & 0xff)); 8406 return -EINVAL; 8407 } 8408 8409 val = nr64(ESPC_PHY_TYPE); 8410 switch (np->port) { 8411 case 0: 8412 val8 = (val & ESPC_PHY_TYPE_PORT0) >> 8413 ESPC_PHY_TYPE_PORT0_SHIFT; 8414 break; 8415 case 1: 8416 val8 = (val & ESPC_PHY_TYPE_PORT1) >> 8417 ESPC_PHY_TYPE_PORT1_SHIFT; 8418 break; 8419 case 2: 8420 val8 = (val & ESPC_PHY_TYPE_PORT2) >> 8421 ESPC_PHY_TYPE_PORT2_SHIFT; 8422 break; 8423 case 3: 8424 val8 = (val & ESPC_PHY_TYPE_PORT3) >> 8425 ESPC_PHY_TYPE_PORT3_SHIFT; 8426 break; 8427 default: 8428 dev_err(np->device, "Bogus port number %u\n", 8429 np->port); 8430 return -EINVAL; 8431 } 8432 netif_printk(np, probe, KERN_DEBUG, np->dev, 8433 "SPROM: PHY type %x\n", val8); 8434 8435 switch (val8) { 8436 case ESPC_PHY_TYPE_1G_COPPER: 8437 /* 1G copper, MII */ 8438 np->flags &= ~(NIU_FLAGS_FIBER | 8439 NIU_FLAGS_10G); 8440 np->mac_xcvr = MAC_XCVR_MII; 8441 break; 8442 8443 case ESPC_PHY_TYPE_1G_FIBER: 8444 /* 1G fiber, PCS */ 8445 np->flags &= ~NIU_FLAGS_10G; 8446 np->flags |= NIU_FLAGS_FIBER; 8447 np->mac_xcvr = MAC_XCVR_PCS; 8448 break; 8449 8450 case ESPC_PHY_TYPE_10G_COPPER: 8451 /* 10G copper, XPCS */ 8452 np->flags |= NIU_FLAGS_10G; 8453 np->flags &= ~NIU_FLAGS_FIBER; 8454 np->mac_xcvr = MAC_XCVR_XPCS; 8455 break; 8456 8457 case ESPC_PHY_TYPE_10G_FIBER: 8458 /* 10G fiber, XPCS */ 8459 np->flags |= (NIU_FLAGS_10G | 8460 NIU_FLAGS_FIBER); 8461 np->mac_xcvr = MAC_XCVR_XPCS; 8462 break; 8463 8464 default: 8465 dev_err(np->device, "Bogus SPROM phy type %u\n", val8); 8466 return -EINVAL; 8467 } 8468 8469 val = nr64(ESPC_MAC_ADDR0); 8470 netif_printk(np, probe, KERN_DEBUG, np->dev, 8471 "SPROM: MAC_ADDR0[%08llx]\n", (unsigned long long)val); 8472 dev->dev_addr[0] = (val >> 0) & 0xff; 8473 dev->dev_addr[1] = (val >> 8) & 0xff; 8474 dev->dev_addr[2] = (val >> 16) & 0xff; 8475 dev->dev_addr[3] = (val >> 24) & 0xff; 8476 8477 val = nr64(ESPC_MAC_ADDR1); 8478 netif_printk(np, probe, KERN_DEBUG, np->dev, 8479 "SPROM: MAC_ADDR1[%08llx]\n", (unsigned long long)val); 8480 dev->dev_addr[4] = (val >> 0) & 0xff; 8481 dev->dev_addr[5] = (val >> 8) & 0xff; 8482 8483 if (!is_valid_ether_addr(&dev->dev_addr[0])) { 8484 dev_err(np->device, "SPROM MAC address invalid [ %pM ]\n", 8485 dev->dev_addr); 8486 return -EINVAL; 8487 } 8488 8489 val8 = dev->dev_addr[5]; 8490 dev->dev_addr[5] += np->port; 8491 if (dev->dev_addr[5] < val8) 8492 dev->dev_addr[4]++; 8493 8494 val = nr64(ESPC_MOD_STR_LEN); 8495 netif_printk(np, probe, KERN_DEBUG, np->dev, 8496 "SPROM: MOD_STR_LEN[%llu]\n", (unsigned long long)val); 8497 if (val >= 8 * 4) 8498 return -EINVAL; 8499 8500 for (i = 0; i < val; i += 4) { 8501 u64 tmp = nr64(ESPC_NCR(5 + (i / 4))); 8502 8503 np->vpd.model[i + 3] = (tmp >> 0) & 0xff; 8504 np->vpd.model[i + 2] = (tmp >> 8) & 0xff; 8505 np->vpd.model[i + 1] = (tmp >> 16) & 0xff; 8506 np->vpd.model[i + 0] = (tmp >> 24) & 0xff; 8507 } 8508 np->vpd.model[val] = '\0'; 8509 8510 val = nr64(ESPC_BD_MOD_STR_LEN); 8511 netif_printk(np, probe, KERN_DEBUG, np->dev, 8512 "SPROM: BD_MOD_STR_LEN[%llu]\n", (unsigned long long)val); 8513 if (val >= 4 * 4) 8514 return -EINVAL; 8515 8516 for (i = 0; i < val; i += 4) { 8517 u64 tmp = nr64(ESPC_NCR(14 + (i / 4))); 8518 8519 np->vpd.board_model[i + 3] = (tmp >> 0) & 0xff; 8520 np->vpd.board_model[i + 2] = (tmp >> 8) & 0xff; 8521 np->vpd.board_model[i + 1] = (tmp >> 16) & 0xff; 8522 np->vpd.board_model[i + 0] = (tmp >> 24) & 0xff; 8523 } 8524 np->vpd.board_model[val] = '\0'; 8525 8526 np->vpd.mac_num = 8527 nr64(ESPC_NUM_PORTS_MACS) & ESPC_NUM_PORTS_MACS_VAL; 8528 netif_printk(np, probe, KERN_DEBUG, np->dev, 8529 "SPROM: NUM_PORTS_MACS[%d]\n", np->vpd.mac_num); 8530 8531 return 0; 8532 } 8533 8534 static int niu_get_and_validate_port(struct niu *np) 8535 { 8536 struct niu_parent *parent = np->parent; 8537 8538 if (np->port <= 1) 8539 np->flags |= NIU_FLAGS_XMAC; 8540 8541 if (!parent->num_ports) { 8542 if (parent->plat_type == PLAT_TYPE_NIU) { 8543 parent->num_ports = 2; 8544 } else { 8545 parent->num_ports = niu_pci_vpd_get_nports(np); 8546 if (!parent->num_ports) { 8547 /* Fall back to SPROM as last resort. 8548 * This will fail on most cards. 8549 */ 8550 parent->num_ports = nr64(ESPC_NUM_PORTS_MACS) & 8551 ESPC_NUM_PORTS_MACS_VAL; 8552 8553 /* All of the current probing methods fail on 8554 * Maramba on-board parts. 8555 */ 8556 if (!parent->num_ports) 8557 parent->num_ports = 4; 8558 } 8559 } 8560 } 8561 8562 if (np->port >= parent->num_ports) 8563 return -ENODEV; 8564 8565 return 0; 8566 } 8567 8568 static int phy_record(struct niu_parent *parent, struct phy_probe_info *p, 8569 int dev_id_1, int dev_id_2, u8 phy_port, int type) 8570 { 8571 u32 id = (dev_id_1 << 16) | dev_id_2; 8572 u8 idx; 8573 8574 if (dev_id_1 < 0 || dev_id_2 < 0) 8575 return 0; 8576 if (type == PHY_TYPE_PMA_PMD || type == PHY_TYPE_PCS) { 8577 /* Because of the NIU_PHY_ID_MASK being applied, the 8704 8578 * test covers the 8706 as well. 8579 */ 8580 if (((id & NIU_PHY_ID_MASK) != NIU_PHY_ID_BCM8704) && 8581 ((id & NIU_PHY_ID_MASK) != NIU_PHY_ID_MRVL88X2011)) 8582 return 0; 8583 } else { 8584 if ((id & NIU_PHY_ID_MASK) != NIU_PHY_ID_BCM5464R) 8585 return 0; 8586 } 8587 8588 pr_info("niu%d: Found PHY %08x type %s at phy_port %u\n", 8589 parent->index, id, 8590 type == PHY_TYPE_PMA_PMD ? "PMA/PMD" : 8591 type == PHY_TYPE_PCS ? "PCS" : "MII", 8592 phy_port); 8593 8594 if (p->cur[type] >= NIU_MAX_PORTS) { 8595 pr_err("Too many PHY ports\n"); 8596 return -EINVAL; 8597 } 8598 idx = p->cur[type]; 8599 p->phy_id[type][idx] = id; 8600 p->phy_port[type][idx] = phy_port; 8601 p->cur[type] = idx + 1; 8602 return 0; 8603 } 8604 8605 static int port_has_10g(struct phy_probe_info *p, int port) 8606 { 8607 int i; 8608 8609 for (i = 0; i < p->cur[PHY_TYPE_PMA_PMD]; i++) { 8610 if (p->phy_port[PHY_TYPE_PMA_PMD][i] == port) 8611 return 1; 8612 } 8613 for (i = 0; i < p->cur[PHY_TYPE_PCS]; i++) { 8614 if (p->phy_port[PHY_TYPE_PCS][i] == port) 8615 return 1; 8616 } 8617 8618 return 0; 8619 } 8620 8621 static int count_10g_ports(struct phy_probe_info *p, int *lowest) 8622 { 8623 int port, cnt; 8624 8625 cnt = 0; 8626 *lowest = 32; 8627 for (port = 8; port < 32; port++) { 8628 if (port_has_10g(p, port)) { 8629 if (!cnt) 8630 *lowest = port; 8631 cnt++; 8632 } 8633 } 8634 8635 return cnt; 8636 } 8637 8638 static int count_1g_ports(struct phy_probe_info *p, int *lowest) 8639 { 8640 *lowest = 32; 8641 if (p->cur[PHY_TYPE_MII]) 8642 *lowest = p->phy_port[PHY_TYPE_MII][0]; 8643 8644 return p->cur[PHY_TYPE_MII]; 8645 } 8646 8647 static void niu_n2_divide_channels(struct niu_parent *parent) 8648 { 8649 int num_ports = parent->num_ports; 8650 int i; 8651 8652 for (i = 0; i < num_ports; i++) { 8653 parent->rxchan_per_port[i] = (16 / num_ports); 8654 parent->txchan_per_port[i] = (16 / num_ports); 8655 8656 pr_info("niu%d: Port %u [%u RX chans] [%u TX chans]\n", 8657 parent->index, i, 8658 parent->rxchan_per_port[i], 8659 parent->txchan_per_port[i]); 8660 } 8661 } 8662 8663 static void niu_divide_channels(struct niu_parent *parent, 8664 int num_10g, int num_1g) 8665 { 8666 int num_ports = parent->num_ports; 8667 int rx_chans_per_10g, rx_chans_per_1g; 8668 int tx_chans_per_10g, tx_chans_per_1g; 8669 int i, tot_rx, tot_tx; 8670 8671 if (!num_10g || !num_1g) { 8672 rx_chans_per_10g = rx_chans_per_1g = 8673 (NIU_NUM_RXCHAN / num_ports); 8674 tx_chans_per_10g = tx_chans_per_1g = 8675 (NIU_NUM_TXCHAN / num_ports); 8676 } else { 8677 rx_chans_per_1g = NIU_NUM_RXCHAN / 8; 8678 rx_chans_per_10g = (NIU_NUM_RXCHAN - 8679 (rx_chans_per_1g * num_1g)) / 8680 num_10g; 8681 8682 tx_chans_per_1g = NIU_NUM_TXCHAN / 6; 8683 tx_chans_per_10g = (NIU_NUM_TXCHAN - 8684 (tx_chans_per_1g * num_1g)) / 8685 num_10g; 8686 } 8687 8688 tot_rx = tot_tx = 0; 8689 for (i = 0; i < num_ports; i++) { 8690 int type = phy_decode(parent->port_phy, i); 8691 8692 if (type == PORT_TYPE_10G) { 8693 parent->rxchan_per_port[i] = rx_chans_per_10g; 8694 parent->txchan_per_port[i] = tx_chans_per_10g; 8695 } else { 8696 parent->rxchan_per_port[i] = rx_chans_per_1g; 8697 parent->txchan_per_port[i] = tx_chans_per_1g; 8698 } 8699 pr_info("niu%d: Port %u [%u RX chans] [%u TX chans]\n", 8700 parent->index, i, 8701 parent->rxchan_per_port[i], 8702 parent->txchan_per_port[i]); 8703 tot_rx += parent->rxchan_per_port[i]; 8704 tot_tx += parent->txchan_per_port[i]; 8705 } 8706 8707 if (tot_rx > NIU_NUM_RXCHAN) { 8708 pr_err("niu%d: Too many RX channels (%d), resetting to one per port\n", 8709 parent->index, tot_rx); 8710 for (i = 0; i < num_ports; i++) 8711 parent->rxchan_per_port[i] = 1; 8712 } 8713 if (tot_tx > NIU_NUM_TXCHAN) { 8714 pr_err("niu%d: Too many TX channels (%d), resetting to one per port\n", 8715 parent->index, tot_tx); 8716 for (i = 0; i < num_ports; i++) 8717 parent->txchan_per_port[i] = 1; 8718 } 8719 if (tot_rx < NIU_NUM_RXCHAN || tot_tx < NIU_NUM_TXCHAN) { 8720 pr_warning("niu%d: Driver bug, wasted channels, RX[%d] TX[%d]\n", 8721 parent->index, tot_rx, tot_tx); 8722 } 8723 } 8724 8725 static void niu_divide_rdc_groups(struct niu_parent *parent, 8726 int num_10g, int num_1g) 8727 { 8728 int i, num_ports = parent->num_ports; 8729 int rdc_group, rdc_groups_per_port; 8730 int rdc_channel_base; 8731 8732 rdc_group = 0; 8733 rdc_groups_per_port = NIU_NUM_RDC_TABLES / num_ports; 8734 8735 rdc_channel_base = 0; 8736 8737 for (i = 0; i < num_ports; i++) { 8738 struct niu_rdc_tables *tp = &parent->rdc_group_cfg[i]; 8739 int grp, num_channels = parent->rxchan_per_port[i]; 8740 int this_channel_offset; 8741 8742 tp->first_table_num = rdc_group; 8743 tp->num_tables = rdc_groups_per_port; 8744 this_channel_offset = 0; 8745 for (grp = 0; grp < tp->num_tables; grp++) { 8746 struct rdc_table *rt = &tp->tables[grp]; 8747 int slot; 8748 8749 pr_info("niu%d: Port %d RDC tbl(%d) [ ", 8750 parent->index, i, tp->first_table_num + grp); 8751 for (slot = 0; slot < NIU_RDC_TABLE_SLOTS; slot++) { 8752 rt->rxdma_channel[slot] = 8753 rdc_channel_base + this_channel_offset; 8754 8755 pr_cont("%d ", rt->rxdma_channel[slot]); 8756 8757 if (++this_channel_offset == num_channels) 8758 this_channel_offset = 0; 8759 } 8760 pr_cont("]\n"); 8761 } 8762 8763 parent->rdc_default[i] = rdc_channel_base; 8764 8765 rdc_channel_base += num_channels; 8766 rdc_group += rdc_groups_per_port; 8767 } 8768 } 8769 8770 static int fill_phy_probe_info(struct niu *np, struct niu_parent *parent, 8771 struct phy_probe_info *info) 8772 { 8773 unsigned long flags; 8774 int port, err; 8775 8776 memset(info, 0, sizeof(*info)); 8777 8778 /* Port 0 to 7 are reserved for onboard Serdes, probe the rest. */ 8779 niu_lock_parent(np, flags); 8780 err = 0; 8781 for (port = 8; port < 32; port++) { 8782 int dev_id_1, dev_id_2; 8783 8784 dev_id_1 = mdio_read(np, port, 8785 NIU_PMA_PMD_DEV_ADDR, MII_PHYSID1); 8786 dev_id_2 = mdio_read(np, port, 8787 NIU_PMA_PMD_DEV_ADDR, MII_PHYSID2); 8788 err = phy_record(parent, info, dev_id_1, dev_id_2, port, 8789 PHY_TYPE_PMA_PMD); 8790 if (err) 8791 break; 8792 dev_id_1 = mdio_read(np, port, 8793 NIU_PCS_DEV_ADDR, MII_PHYSID1); 8794 dev_id_2 = mdio_read(np, port, 8795 NIU_PCS_DEV_ADDR, MII_PHYSID2); 8796 err = phy_record(parent, info, dev_id_1, dev_id_2, port, 8797 PHY_TYPE_PCS); 8798 if (err) 8799 break; 8800 dev_id_1 = mii_read(np, port, MII_PHYSID1); 8801 dev_id_2 = mii_read(np, port, MII_PHYSID2); 8802 err = phy_record(parent, info, dev_id_1, dev_id_2, port, 8803 PHY_TYPE_MII); 8804 if (err) 8805 break; 8806 } 8807 niu_unlock_parent(np, flags); 8808 8809 return err; 8810 } 8811 8812 static int walk_phys(struct niu *np, struct niu_parent *parent) 8813 { 8814 struct phy_probe_info *info = &parent->phy_probe_info; 8815 int lowest_10g, lowest_1g; 8816 int num_10g, num_1g; 8817 u32 val; 8818 int err; 8819 8820 num_10g = num_1g = 0; 8821 8822 if (!strcmp(np->vpd.model, NIU_ALONSO_MDL_STR) || 8823 !strcmp(np->vpd.model, NIU_KIMI_MDL_STR)) { 8824 num_10g = 0; 8825 num_1g = 2; 8826 parent->plat_type = PLAT_TYPE_ATCA_CP3220; 8827 parent->num_ports = 4; 8828 val = (phy_encode(PORT_TYPE_1G, 0) | 8829 phy_encode(PORT_TYPE_1G, 1) | 8830 phy_encode(PORT_TYPE_1G, 2) | 8831 phy_encode(PORT_TYPE_1G, 3)); 8832 } else if (!strcmp(np->vpd.model, NIU_FOXXY_MDL_STR)) { 8833 num_10g = 2; 8834 num_1g = 0; 8835 parent->num_ports = 2; 8836 val = (phy_encode(PORT_TYPE_10G, 0) | 8837 phy_encode(PORT_TYPE_10G, 1)); 8838 } else if ((np->flags & NIU_FLAGS_XCVR_SERDES) && 8839 (parent->plat_type == PLAT_TYPE_NIU)) { 8840 /* this is the Monza case */ 8841 if (np->flags & NIU_FLAGS_10G) { 8842 val = (phy_encode(PORT_TYPE_10G, 0) | 8843 phy_encode(PORT_TYPE_10G, 1)); 8844 } else { 8845 val = (phy_encode(PORT_TYPE_1G, 0) | 8846 phy_encode(PORT_TYPE_1G, 1)); 8847 } 8848 } else { 8849 err = fill_phy_probe_info(np, parent, info); 8850 if (err) 8851 return err; 8852 8853 num_10g = count_10g_ports(info, &lowest_10g); 8854 num_1g = count_1g_ports(info, &lowest_1g); 8855 8856 switch ((num_10g << 4) | num_1g) { 8857 case 0x24: 8858 if (lowest_1g == 10) 8859 parent->plat_type = PLAT_TYPE_VF_P0; 8860 else if (lowest_1g == 26) 8861 parent->plat_type = PLAT_TYPE_VF_P1; 8862 else 8863 goto unknown_vg_1g_port; 8864 8865 /* fallthru */ 8866 case 0x22: 8867 val = (phy_encode(PORT_TYPE_10G, 0) | 8868 phy_encode(PORT_TYPE_10G, 1) | 8869 phy_encode(PORT_TYPE_1G, 2) | 8870 phy_encode(PORT_TYPE_1G, 3)); 8871 break; 8872 8873 case 0x20: 8874 val = (phy_encode(PORT_TYPE_10G, 0) | 8875 phy_encode(PORT_TYPE_10G, 1)); 8876 break; 8877 8878 case 0x10: 8879 val = phy_encode(PORT_TYPE_10G, np->port); 8880 break; 8881 8882 case 0x14: 8883 if (lowest_1g == 10) 8884 parent->plat_type = PLAT_TYPE_VF_P0; 8885 else if (lowest_1g == 26) 8886 parent->plat_type = PLAT_TYPE_VF_P1; 8887 else 8888 goto unknown_vg_1g_port; 8889 8890 /* fallthru */ 8891 case 0x13: 8892 if ((lowest_10g & 0x7) == 0) 8893 val = (phy_encode(PORT_TYPE_10G, 0) | 8894 phy_encode(PORT_TYPE_1G, 1) | 8895 phy_encode(PORT_TYPE_1G, 2) | 8896 phy_encode(PORT_TYPE_1G, 3)); 8897 else 8898 val = (phy_encode(PORT_TYPE_1G, 0) | 8899 phy_encode(PORT_TYPE_10G, 1) | 8900 phy_encode(PORT_TYPE_1G, 2) | 8901 phy_encode(PORT_TYPE_1G, 3)); 8902 break; 8903 8904 case 0x04: 8905 if (lowest_1g == 10) 8906 parent->plat_type = PLAT_TYPE_VF_P0; 8907 else if (lowest_1g == 26) 8908 parent->plat_type = PLAT_TYPE_VF_P1; 8909 else 8910 goto unknown_vg_1g_port; 8911 8912 val = (phy_encode(PORT_TYPE_1G, 0) | 8913 phy_encode(PORT_TYPE_1G, 1) | 8914 phy_encode(PORT_TYPE_1G, 2) | 8915 phy_encode(PORT_TYPE_1G, 3)); 8916 break; 8917 8918 default: 8919 pr_err("Unsupported port config 10G[%d] 1G[%d]\n", 8920 num_10g, num_1g); 8921 return -EINVAL; 8922 } 8923 } 8924 8925 parent->port_phy = val; 8926 8927 if (parent->plat_type == PLAT_TYPE_NIU) 8928 niu_n2_divide_channels(parent); 8929 else 8930 niu_divide_channels(parent, num_10g, num_1g); 8931 8932 niu_divide_rdc_groups(parent, num_10g, num_1g); 8933 8934 return 0; 8935 8936 unknown_vg_1g_port: 8937 pr_err("Cannot identify platform type, 1gport=%d\n", lowest_1g); 8938 return -EINVAL; 8939 } 8940 8941 static int niu_probe_ports(struct niu *np) 8942 { 8943 struct niu_parent *parent = np->parent; 8944 int err, i; 8945 8946 if (parent->port_phy == PORT_PHY_UNKNOWN) { 8947 err = walk_phys(np, parent); 8948 if (err) 8949 return err; 8950 8951 niu_set_ldg_timer_res(np, 2); 8952 for (i = 0; i <= LDN_MAX; i++) 8953 niu_ldn_irq_enable(np, i, 0); 8954 } 8955 8956 if (parent->port_phy == PORT_PHY_INVALID) 8957 return -EINVAL; 8958 8959 return 0; 8960 } 8961 8962 static int niu_classifier_swstate_init(struct niu *np) 8963 { 8964 struct niu_classifier *cp = &np->clas; 8965 8966 cp->tcam_top = (u16) np->port; 8967 cp->tcam_sz = np->parent->tcam_num_entries / np->parent->num_ports; 8968 cp->h1_init = 0xffffffff; 8969 cp->h2_init = 0xffff; 8970 8971 return fflp_early_init(np); 8972 } 8973 8974 static void niu_link_config_init(struct niu *np) 8975 { 8976 struct niu_link_config *lp = &np->link_config; 8977 8978 lp->advertising = (ADVERTISED_10baseT_Half | 8979 ADVERTISED_10baseT_Full | 8980 ADVERTISED_100baseT_Half | 8981 ADVERTISED_100baseT_Full | 8982 ADVERTISED_1000baseT_Half | 8983 ADVERTISED_1000baseT_Full | 8984 ADVERTISED_10000baseT_Full | 8985 ADVERTISED_Autoneg); 8986 lp->speed = lp->active_speed = SPEED_INVALID; 8987 lp->duplex = DUPLEX_FULL; 8988 lp->active_duplex = DUPLEX_INVALID; 8989 lp->autoneg = 1; 8990 #if 0 8991 lp->loopback_mode = LOOPBACK_MAC; 8992 lp->active_speed = SPEED_10000; 8993 lp->active_duplex = DUPLEX_FULL; 8994 #else 8995 lp->loopback_mode = LOOPBACK_DISABLED; 8996 #endif 8997 } 8998 8999 static int niu_init_mac_ipp_pcs_base(struct niu *np) 9000 { 9001 switch (np->port) { 9002 case 0: 9003 np->mac_regs = np->regs + XMAC_PORT0_OFF; 9004 np->ipp_off = 0x00000; 9005 np->pcs_off = 0x04000; 9006 np->xpcs_off = 0x02000; 9007 break; 9008 9009 case 1: 9010 np->mac_regs = np->regs + XMAC_PORT1_OFF; 9011 np->ipp_off = 0x08000; 9012 np->pcs_off = 0x0a000; 9013 np->xpcs_off = 0x08000; 9014 break; 9015 9016 case 2: 9017 np->mac_regs = np->regs + BMAC_PORT2_OFF; 9018 np->ipp_off = 0x04000; 9019 np->pcs_off = 0x0e000; 9020 np->xpcs_off = ~0UL; 9021 break; 9022 9023 case 3: 9024 np->mac_regs = np->regs + BMAC_PORT3_OFF; 9025 np->ipp_off = 0x0c000; 9026 np->pcs_off = 0x12000; 9027 np->xpcs_off = ~0UL; 9028 break; 9029 9030 default: 9031 dev_err(np->device, "Port %u is invalid, cannot compute MAC block offset\n", np->port); 9032 return -EINVAL; 9033 } 9034 9035 return 0; 9036 } 9037 9038 static void niu_try_msix(struct niu *np, u8 *ldg_num_map) 9039 { 9040 struct msix_entry msi_vec[NIU_NUM_LDG]; 9041 struct niu_parent *parent = np->parent; 9042 struct pci_dev *pdev = np->pdev; 9043 int i, num_irqs; 9044 u8 first_ldg; 9045 9046 first_ldg = (NIU_NUM_LDG / parent->num_ports) * np->port; 9047 for (i = 0; i < (NIU_NUM_LDG / parent->num_ports); i++) 9048 ldg_num_map[i] = first_ldg + i; 9049 9050 num_irqs = (parent->rxchan_per_port[np->port] + 9051 parent->txchan_per_port[np->port] + 9052 (np->port == 0 ? 3 : 1)); 9053 BUG_ON(num_irqs > (NIU_NUM_LDG / parent->num_ports)); 9054 9055 for (i = 0; i < num_irqs; i++) { 9056 msi_vec[i].vector = 0; 9057 msi_vec[i].entry = i; 9058 } 9059 9060 num_irqs = pci_enable_msix_range(pdev, msi_vec, 1, num_irqs); 9061 if (num_irqs < 0) { 9062 np->flags &= ~NIU_FLAGS_MSIX; 9063 return; 9064 } 9065 9066 np->flags |= NIU_FLAGS_MSIX; 9067 for (i = 0; i < num_irqs; i++) 9068 np->ldg[i].irq = msi_vec[i].vector; 9069 np->num_ldg = num_irqs; 9070 } 9071 9072 static int niu_n2_irq_init(struct niu *np, u8 *ldg_num_map) 9073 { 9074 #ifdef CONFIG_SPARC64 9075 struct platform_device *op = np->op; 9076 const u32 *int_prop; 9077 int i; 9078 9079 int_prop = of_get_property(op->dev.of_node, "interrupts", NULL); 9080 if (!int_prop) 9081 return -ENODEV; 9082 9083 for (i = 0; i < op->archdata.num_irqs; i++) { 9084 ldg_num_map[i] = int_prop[i]; 9085 np->ldg[i].irq = op->archdata.irqs[i]; 9086 } 9087 9088 np->num_ldg = op->archdata.num_irqs; 9089 9090 return 0; 9091 #else 9092 return -EINVAL; 9093 #endif 9094 } 9095 9096 static int niu_ldg_init(struct niu *np) 9097 { 9098 struct niu_parent *parent = np->parent; 9099 u8 ldg_num_map[NIU_NUM_LDG]; 9100 int first_chan, num_chan; 9101 int i, err, ldg_rotor; 9102 u8 port; 9103 9104 np->num_ldg = 1; 9105 np->ldg[0].irq = np->dev->irq; 9106 if (parent->plat_type == PLAT_TYPE_NIU) { 9107 err = niu_n2_irq_init(np, ldg_num_map); 9108 if (err) 9109 return err; 9110 } else 9111 niu_try_msix(np, ldg_num_map); 9112 9113 port = np->port; 9114 for (i = 0; i < np->num_ldg; i++) { 9115 struct niu_ldg *lp = &np->ldg[i]; 9116 9117 netif_napi_add(np->dev, &lp->napi, niu_poll, 64); 9118 9119 lp->np = np; 9120 lp->ldg_num = ldg_num_map[i]; 9121 lp->timer = 2; /* XXX */ 9122 9123 /* On N2 NIU the firmware has setup the SID mappings so they go 9124 * to the correct values that will route the LDG to the proper 9125 * interrupt in the NCU interrupt table. 9126 */ 9127 if (np->parent->plat_type != PLAT_TYPE_NIU) { 9128 err = niu_set_ldg_sid(np, lp->ldg_num, port, i); 9129 if (err) 9130 return err; 9131 } 9132 } 9133 9134 /* We adopt the LDG assignment ordering used by the N2 NIU 9135 * 'interrupt' properties because that simplifies a lot of 9136 * things. This ordering is: 9137 * 9138 * MAC 9139 * MIF (if port zero) 9140 * SYSERR (if port zero) 9141 * RX channels 9142 * TX channels 9143 */ 9144 9145 ldg_rotor = 0; 9146 9147 err = niu_ldg_assign_ldn(np, parent, ldg_num_map[ldg_rotor], 9148 LDN_MAC(port)); 9149 if (err) 9150 return err; 9151 9152 ldg_rotor++; 9153 if (ldg_rotor == np->num_ldg) 9154 ldg_rotor = 0; 9155 9156 if (port == 0) { 9157 err = niu_ldg_assign_ldn(np, parent, 9158 ldg_num_map[ldg_rotor], 9159 LDN_MIF); 9160 if (err) 9161 return err; 9162 9163 ldg_rotor++; 9164 if (ldg_rotor == np->num_ldg) 9165 ldg_rotor = 0; 9166 9167 err = niu_ldg_assign_ldn(np, parent, 9168 ldg_num_map[ldg_rotor], 9169 LDN_DEVICE_ERROR); 9170 if (err) 9171 return err; 9172 9173 ldg_rotor++; 9174 if (ldg_rotor == np->num_ldg) 9175 ldg_rotor = 0; 9176 9177 } 9178 9179 first_chan = 0; 9180 for (i = 0; i < port; i++) 9181 first_chan += parent->rxchan_per_port[i]; 9182 num_chan = parent->rxchan_per_port[port]; 9183 9184 for (i = first_chan; i < (first_chan + num_chan); i++) { 9185 err = niu_ldg_assign_ldn(np, parent, 9186 ldg_num_map[ldg_rotor], 9187 LDN_RXDMA(i)); 9188 if (err) 9189 return err; 9190 ldg_rotor++; 9191 if (ldg_rotor == np->num_ldg) 9192 ldg_rotor = 0; 9193 } 9194 9195 first_chan = 0; 9196 for (i = 0; i < port; i++) 9197 first_chan += parent->txchan_per_port[i]; 9198 num_chan = parent->txchan_per_port[port]; 9199 for (i = first_chan; i < (first_chan + num_chan); i++) { 9200 err = niu_ldg_assign_ldn(np, parent, 9201 ldg_num_map[ldg_rotor], 9202 LDN_TXDMA(i)); 9203 if (err) 9204 return err; 9205 ldg_rotor++; 9206 if (ldg_rotor == np->num_ldg) 9207 ldg_rotor = 0; 9208 } 9209 9210 return 0; 9211 } 9212 9213 static void niu_ldg_free(struct niu *np) 9214 { 9215 if (np->flags & NIU_FLAGS_MSIX) 9216 pci_disable_msix(np->pdev); 9217 } 9218 9219 static int niu_get_of_props(struct niu *np) 9220 { 9221 #ifdef CONFIG_SPARC64 9222 struct net_device *dev = np->dev; 9223 struct device_node *dp; 9224 const char *phy_type; 9225 const u8 *mac_addr; 9226 const char *model; 9227 int prop_len; 9228 9229 if (np->parent->plat_type == PLAT_TYPE_NIU) 9230 dp = np->op->dev.of_node; 9231 else 9232 dp = pci_device_to_OF_node(np->pdev); 9233 9234 phy_type = of_get_property(dp, "phy-type", &prop_len); 9235 if (!phy_type) { 9236 netdev_err(dev, "%s: OF node lacks phy-type property\n", 9237 dp->full_name); 9238 return -EINVAL; 9239 } 9240 9241 if (!strcmp(phy_type, "none")) 9242 return -ENODEV; 9243 9244 strcpy(np->vpd.phy_type, phy_type); 9245 9246 if (niu_phy_type_prop_decode(np, np->vpd.phy_type)) { 9247 netdev_err(dev, "%s: Illegal phy string [%s]\n", 9248 dp->full_name, np->vpd.phy_type); 9249 return -EINVAL; 9250 } 9251 9252 mac_addr = of_get_property(dp, "local-mac-address", &prop_len); 9253 if (!mac_addr) { 9254 netdev_err(dev, "%s: OF node lacks local-mac-address property\n", 9255 dp->full_name); 9256 return -EINVAL; 9257 } 9258 if (prop_len != dev->addr_len) { 9259 netdev_err(dev, "%s: OF MAC address prop len (%d) is wrong\n", 9260 dp->full_name, prop_len); 9261 } 9262 memcpy(dev->dev_addr, mac_addr, dev->addr_len); 9263 if (!is_valid_ether_addr(&dev->dev_addr[0])) { 9264 netdev_err(dev, "%s: OF MAC address is invalid\n", 9265 dp->full_name); 9266 netdev_err(dev, "%s: [ %pM ]\n", dp->full_name, dev->dev_addr); 9267 return -EINVAL; 9268 } 9269 9270 model = of_get_property(dp, "model", &prop_len); 9271 9272 if (model) 9273 strcpy(np->vpd.model, model); 9274 9275 if (of_find_property(dp, "hot-swappable-phy", &prop_len)) { 9276 np->flags |= (NIU_FLAGS_10G | NIU_FLAGS_FIBER | 9277 NIU_FLAGS_HOTPLUG_PHY); 9278 } 9279 9280 return 0; 9281 #else 9282 return -EINVAL; 9283 #endif 9284 } 9285 9286 static int niu_get_invariants(struct niu *np) 9287 { 9288 int err, have_props; 9289 u32 offset; 9290 9291 err = niu_get_of_props(np); 9292 if (err == -ENODEV) 9293 return err; 9294 9295 have_props = !err; 9296 9297 err = niu_init_mac_ipp_pcs_base(np); 9298 if (err) 9299 return err; 9300 9301 if (have_props) { 9302 err = niu_get_and_validate_port(np); 9303 if (err) 9304 return err; 9305 9306 } else { 9307 if (np->parent->plat_type == PLAT_TYPE_NIU) 9308 return -EINVAL; 9309 9310 nw64(ESPC_PIO_EN, ESPC_PIO_EN_ENABLE); 9311 offset = niu_pci_vpd_offset(np); 9312 netif_printk(np, probe, KERN_DEBUG, np->dev, 9313 "%s() VPD offset [%08x]\n", __func__, offset); 9314 if (offset) 9315 niu_pci_vpd_fetch(np, offset); 9316 nw64(ESPC_PIO_EN, 0); 9317 9318 if (np->flags & NIU_FLAGS_VPD_VALID) { 9319 niu_pci_vpd_validate(np); 9320 err = niu_get_and_validate_port(np); 9321 if (err) 9322 return err; 9323 } 9324 9325 if (!(np->flags & NIU_FLAGS_VPD_VALID)) { 9326 err = niu_get_and_validate_port(np); 9327 if (err) 9328 return err; 9329 err = niu_pci_probe_sprom(np); 9330 if (err) 9331 return err; 9332 } 9333 } 9334 9335 err = niu_probe_ports(np); 9336 if (err) 9337 return err; 9338 9339 niu_ldg_init(np); 9340 9341 niu_classifier_swstate_init(np); 9342 niu_link_config_init(np); 9343 9344 err = niu_determine_phy_disposition(np); 9345 if (!err) 9346 err = niu_init_link(np); 9347 9348 return err; 9349 } 9350 9351 static LIST_HEAD(niu_parent_list); 9352 static DEFINE_MUTEX(niu_parent_lock); 9353 static int niu_parent_index; 9354 9355 static ssize_t show_port_phy(struct device *dev, 9356 struct device_attribute *attr, char *buf) 9357 { 9358 struct platform_device *plat_dev = to_platform_device(dev); 9359 struct niu_parent *p = dev_get_platdata(&plat_dev->dev); 9360 u32 port_phy = p->port_phy; 9361 char *orig_buf = buf; 9362 int i; 9363 9364 if (port_phy == PORT_PHY_UNKNOWN || 9365 port_phy == PORT_PHY_INVALID) 9366 return 0; 9367 9368 for (i = 0; i < p->num_ports; i++) { 9369 const char *type_str; 9370 int type; 9371 9372 type = phy_decode(port_phy, i); 9373 if (type == PORT_TYPE_10G) 9374 type_str = "10G"; 9375 else 9376 type_str = "1G"; 9377 buf += sprintf(buf, 9378 (i == 0) ? "%s" : " %s", 9379 type_str); 9380 } 9381 buf += sprintf(buf, "\n"); 9382 return buf - orig_buf; 9383 } 9384 9385 static ssize_t show_plat_type(struct device *dev, 9386 struct device_attribute *attr, char *buf) 9387 { 9388 struct platform_device *plat_dev = to_platform_device(dev); 9389 struct niu_parent *p = dev_get_platdata(&plat_dev->dev); 9390 const char *type_str; 9391 9392 switch (p->plat_type) { 9393 case PLAT_TYPE_ATLAS: 9394 type_str = "atlas"; 9395 break; 9396 case PLAT_TYPE_NIU: 9397 type_str = "niu"; 9398 break; 9399 case PLAT_TYPE_VF_P0: 9400 type_str = "vf_p0"; 9401 break; 9402 case PLAT_TYPE_VF_P1: 9403 type_str = "vf_p1"; 9404 break; 9405 default: 9406 type_str = "unknown"; 9407 break; 9408 } 9409 9410 return sprintf(buf, "%s\n", type_str); 9411 } 9412 9413 static ssize_t __show_chan_per_port(struct device *dev, 9414 struct device_attribute *attr, char *buf, 9415 int rx) 9416 { 9417 struct platform_device *plat_dev = to_platform_device(dev); 9418 struct niu_parent *p = dev_get_platdata(&plat_dev->dev); 9419 char *orig_buf = buf; 9420 u8 *arr; 9421 int i; 9422 9423 arr = (rx ? p->rxchan_per_port : p->txchan_per_port); 9424 9425 for (i = 0; i < p->num_ports; i++) { 9426 buf += sprintf(buf, 9427 (i == 0) ? "%d" : " %d", 9428 arr[i]); 9429 } 9430 buf += sprintf(buf, "\n"); 9431 9432 return buf - orig_buf; 9433 } 9434 9435 static ssize_t show_rxchan_per_port(struct device *dev, 9436 struct device_attribute *attr, char *buf) 9437 { 9438 return __show_chan_per_port(dev, attr, buf, 1); 9439 } 9440 9441 static ssize_t show_txchan_per_port(struct device *dev, 9442 struct device_attribute *attr, char *buf) 9443 { 9444 return __show_chan_per_port(dev, attr, buf, 1); 9445 } 9446 9447 static ssize_t show_num_ports(struct device *dev, 9448 struct device_attribute *attr, char *buf) 9449 { 9450 struct platform_device *plat_dev = to_platform_device(dev); 9451 struct niu_parent *p = dev_get_platdata(&plat_dev->dev); 9452 9453 return sprintf(buf, "%d\n", p->num_ports); 9454 } 9455 9456 static struct device_attribute niu_parent_attributes[] = { 9457 __ATTR(port_phy, S_IRUGO, show_port_phy, NULL), 9458 __ATTR(plat_type, S_IRUGO, show_plat_type, NULL), 9459 __ATTR(rxchan_per_port, S_IRUGO, show_rxchan_per_port, NULL), 9460 __ATTR(txchan_per_port, S_IRUGO, show_txchan_per_port, NULL), 9461 __ATTR(num_ports, S_IRUGO, show_num_ports, NULL), 9462 {} 9463 }; 9464 9465 static struct niu_parent *niu_new_parent(struct niu *np, 9466 union niu_parent_id *id, u8 ptype) 9467 { 9468 struct platform_device *plat_dev; 9469 struct niu_parent *p; 9470 int i; 9471 9472 plat_dev = platform_device_register_simple("niu-board", niu_parent_index, 9473 NULL, 0); 9474 if (IS_ERR(plat_dev)) 9475 return NULL; 9476 9477 for (i = 0; niu_parent_attributes[i].attr.name; i++) { 9478 int err = device_create_file(&plat_dev->dev, 9479 &niu_parent_attributes[i]); 9480 if (err) 9481 goto fail_unregister; 9482 } 9483 9484 p = kzalloc(sizeof(*p), GFP_KERNEL); 9485 if (!p) 9486 goto fail_unregister; 9487 9488 p->index = niu_parent_index++; 9489 9490 plat_dev->dev.platform_data = p; 9491 p->plat_dev = plat_dev; 9492 9493 memcpy(&p->id, id, sizeof(*id)); 9494 p->plat_type = ptype; 9495 INIT_LIST_HEAD(&p->list); 9496 atomic_set(&p->refcnt, 0); 9497 list_add(&p->list, &niu_parent_list); 9498 spin_lock_init(&p->lock); 9499 9500 p->rxdma_clock_divider = 7500; 9501 9502 p->tcam_num_entries = NIU_PCI_TCAM_ENTRIES; 9503 if (p->plat_type == PLAT_TYPE_NIU) 9504 p->tcam_num_entries = NIU_NONPCI_TCAM_ENTRIES; 9505 9506 for (i = CLASS_CODE_USER_PROG1; i <= CLASS_CODE_SCTP_IPV6; i++) { 9507 int index = i - CLASS_CODE_USER_PROG1; 9508 9509 p->tcam_key[index] = TCAM_KEY_TSEL; 9510 p->flow_key[index] = (FLOW_KEY_IPSA | 9511 FLOW_KEY_IPDA | 9512 FLOW_KEY_PROTO | 9513 (FLOW_KEY_L4_BYTE12 << 9514 FLOW_KEY_L4_0_SHIFT) | 9515 (FLOW_KEY_L4_BYTE12 << 9516 FLOW_KEY_L4_1_SHIFT)); 9517 } 9518 9519 for (i = 0; i < LDN_MAX + 1; i++) 9520 p->ldg_map[i] = LDG_INVALID; 9521 9522 return p; 9523 9524 fail_unregister: 9525 platform_device_unregister(plat_dev); 9526 return NULL; 9527 } 9528 9529 static struct niu_parent *niu_get_parent(struct niu *np, 9530 union niu_parent_id *id, u8 ptype) 9531 { 9532 struct niu_parent *p, *tmp; 9533 int port = np->port; 9534 9535 mutex_lock(&niu_parent_lock); 9536 p = NULL; 9537 list_for_each_entry(tmp, &niu_parent_list, list) { 9538 if (!memcmp(id, &tmp->id, sizeof(*id))) { 9539 p = tmp; 9540 break; 9541 } 9542 } 9543 if (!p) 9544 p = niu_new_parent(np, id, ptype); 9545 9546 if (p) { 9547 char port_name[6]; 9548 int err; 9549 9550 sprintf(port_name, "port%d", port); 9551 err = sysfs_create_link(&p->plat_dev->dev.kobj, 9552 &np->device->kobj, 9553 port_name); 9554 if (!err) { 9555 p->ports[port] = np; 9556 atomic_inc(&p->refcnt); 9557 } 9558 } 9559 mutex_unlock(&niu_parent_lock); 9560 9561 return p; 9562 } 9563 9564 static void niu_put_parent(struct niu *np) 9565 { 9566 struct niu_parent *p = np->parent; 9567 u8 port = np->port; 9568 char port_name[6]; 9569 9570 BUG_ON(!p || p->ports[port] != np); 9571 9572 netif_printk(np, probe, KERN_DEBUG, np->dev, 9573 "%s() port[%u]\n", __func__, port); 9574 9575 sprintf(port_name, "port%d", port); 9576 9577 mutex_lock(&niu_parent_lock); 9578 9579 sysfs_remove_link(&p->plat_dev->dev.kobj, port_name); 9580 9581 p->ports[port] = NULL; 9582 np->parent = NULL; 9583 9584 if (atomic_dec_and_test(&p->refcnt)) { 9585 list_del(&p->list); 9586 platform_device_unregister(p->plat_dev); 9587 } 9588 9589 mutex_unlock(&niu_parent_lock); 9590 } 9591 9592 static void *niu_pci_alloc_coherent(struct device *dev, size_t size, 9593 u64 *handle, gfp_t flag) 9594 { 9595 dma_addr_t dh; 9596 void *ret; 9597 9598 ret = dma_alloc_coherent(dev, size, &dh, flag); 9599 if (ret) 9600 *handle = dh; 9601 return ret; 9602 } 9603 9604 static void niu_pci_free_coherent(struct device *dev, size_t size, 9605 void *cpu_addr, u64 handle) 9606 { 9607 dma_free_coherent(dev, size, cpu_addr, handle); 9608 } 9609 9610 static u64 niu_pci_map_page(struct device *dev, struct page *page, 9611 unsigned long offset, size_t size, 9612 enum dma_data_direction direction) 9613 { 9614 return dma_map_page(dev, page, offset, size, direction); 9615 } 9616 9617 static void niu_pci_unmap_page(struct device *dev, u64 dma_address, 9618 size_t size, enum dma_data_direction direction) 9619 { 9620 dma_unmap_page(dev, dma_address, size, direction); 9621 } 9622 9623 static u64 niu_pci_map_single(struct device *dev, void *cpu_addr, 9624 size_t size, 9625 enum dma_data_direction direction) 9626 { 9627 return dma_map_single(dev, cpu_addr, size, direction); 9628 } 9629 9630 static void niu_pci_unmap_single(struct device *dev, u64 dma_address, 9631 size_t size, 9632 enum dma_data_direction direction) 9633 { 9634 dma_unmap_single(dev, dma_address, size, direction); 9635 } 9636 9637 static const struct niu_ops niu_pci_ops = { 9638 .alloc_coherent = niu_pci_alloc_coherent, 9639 .free_coherent = niu_pci_free_coherent, 9640 .map_page = niu_pci_map_page, 9641 .unmap_page = niu_pci_unmap_page, 9642 .map_single = niu_pci_map_single, 9643 .unmap_single = niu_pci_unmap_single, 9644 }; 9645 9646 static void niu_driver_version(void) 9647 { 9648 static int niu_version_printed; 9649 9650 if (niu_version_printed++ == 0) 9651 pr_info("%s", version); 9652 } 9653 9654 static struct net_device *niu_alloc_and_init(struct device *gen_dev, 9655 struct pci_dev *pdev, 9656 struct platform_device *op, 9657 const struct niu_ops *ops, u8 port) 9658 { 9659 struct net_device *dev; 9660 struct niu *np; 9661 9662 dev = alloc_etherdev_mq(sizeof(struct niu), NIU_NUM_TXCHAN); 9663 if (!dev) 9664 return NULL; 9665 9666 SET_NETDEV_DEV(dev, gen_dev); 9667 9668 np = netdev_priv(dev); 9669 np->dev = dev; 9670 np->pdev = pdev; 9671 np->op = op; 9672 np->device = gen_dev; 9673 np->ops = ops; 9674 9675 np->msg_enable = niu_debug; 9676 9677 spin_lock_init(&np->lock); 9678 INIT_WORK(&np->reset_task, niu_reset_task); 9679 9680 np->port = port; 9681 9682 return dev; 9683 } 9684 9685 static const struct net_device_ops niu_netdev_ops = { 9686 .ndo_open = niu_open, 9687 .ndo_stop = niu_close, 9688 .ndo_start_xmit = niu_start_xmit, 9689 .ndo_get_stats64 = niu_get_stats, 9690 .ndo_set_rx_mode = niu_set_rx_mode, 9691 .ndo_validate_addr = eth_validate_addr, 9692 .ndo_set_mac_address = niu_set_mac_addr, 9693 .ndo_do_ioctl = niu_ioctl, 9694 .ndo_tx_timeout = niu_tx_timeout, 9695 .ndo_change_mtu = niu_change_mtu, 9696 }; 9697 9698 static void niu_assign_netdev_ops(struct net_device *dev) 9699 { 9700 dev->netdev_ops = &niu_netdev_ops; 9701 dev->ethtool_ops = &niu_ethtool_ops; 9702 dev->watchdog_timeo = NIU_TX_TIMEOUT; 9703 } 9704 9705 static void niu_device_announce(struct niu *np) 9706 { 9707 struct net_device *dev = np->dev; 9708 9709 pr_info("%s: NIU Ethernet %pM\n", dev->name, dev->dev_addr); 9710 9711 if (np->parent->plat_type == PLAT_TYPE_ATCA_CP3220) { 9712 pr_info("%s: Port type[%s] mode[%s:%s] XCVR[%s] phy[%s]\n", 9713 dev->name, 9714 (np->flags & NIU_FLAGS_XMAC ? "XMAC" : "BMAC"), 9715 (np->flags & NIU_FLAGS_10G ? "10G" : "1G"), 9716 (np->flags & NIU_FLAGS_FIBER ? "RGMII FIBER" : "SERDES"), 9717 (np->mac_xcvr == MAC_XCVR_MII ? "MII" : 9718 (np->mac_xcvr == MAC_XCVR_PCS ? "PCS" : "XPCS")), 9719 np->vpd.phy_type); 9720 } else { 9721 pr_info("%s: Port type[%s] mode[%s:%s] XCVR[%s] phy[%s]\n", 9722 dev->name, 9723 (np->flags & NIU_FLAGS_XMAC ? "XMAC" : "BMAC"), 9724 (np->flags & NIU_FLAGS_10G ? "10G" : "1G"), 9725 (np->flags & NIU_FLAGS_FIBER ? "FIBER" : 9726 (np->flags & NIU_FLAGS_XCVR_SERDES ? "SERDES" : 9727 "COPPER")), 9728 (np->mac_xcvr == MAC_XCVR_MII ? "MII" : 9729 (np->mac_xcvr == MAC_XCVR_PCS ? "PCS" : "XPCS")), 9730 np->vpd.phy_type); 9731 } 9732 } 9733 9734 static void niu_set_basic_features(struct net_device *dev) 9735 { 9736 dev->hw_features = NETIF_F_SG | NETIF_F_HW_CSUM | NETIF_F_RXHASH; 9737 dev->features |= dev->hw_features | NETIF_F_RXCSUM; 9738 } 9739 9740 static int niu_pci_init_one(struct pci_dev *pdev, 9741 const struct pci_device_id *ent) 9742 { 9743 union niu_parent_id parent_id; 9744 struct net_device *dev; 9745 struct niu *np; 9746 int err; 9747 u64 dma_mask; 9748 9749 niu_driver_version(); 9750 9751 err = pci_enable_device(pdev); 9752 if (err) { 9753 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n"); 9754 return err; 9755 } 9756 9757 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM) || 9758 !(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) { 9759 dev_err(&pdev->dev, "Cannot find proper PCI device base addresses, aborting\n"); 9760 err = -ENODEV; 9761 goto err_out_disable_pdev; 9762 } 9763 9764 err = pci_request_regions(pdev, DRV_MODULE_NAME); 9765 if (err) { 9766 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n"); 9767 goto err_out_disable_pdev; 9768 } 9769 9770 if (!pci_is_pcie(pdev)) { 9771 dev_err(&pdev->dev, "Cannot find PCI Express capability, aborting\n"); 9772 err = -ENODEV; 9773 goto err_out_free_res; 9774 } 9775 9776 dev = niu_alloc_and_init(&pdev->dev, pdev, NULL, 9777 &niu_pci_ops, PCI_FUNC(pdev->devfn)); 9778 if (!dev) { 9779 err = -ENOMEM; 9780 goto err_out_free_res; 9781 } 9782 np = netdev_priv(dev); 9783 9784 memset(&parent_id, 0, sizeof(parent_id)); 9785 parent_id.pci.domain = pci_domain_nr(pdev->bus); 9786 parent_id.pci.bus = pdev->bus->number; 9787 parent_id.pci.device = PCI_SLOT(pdev->devfn); 9788 9789 np->parent = niu_get_parent(np, &parent_id, 9790 PLAT_TYPE_ATLAS); 9791 if (!np->parent) { 9792 err = -ENOMEM; 9793 goto err_out_free_dev; 9794 } 9795 9796 pcie_capability_clear_and_set_word(pdev, PCI_EXP_DEVCTL, 9797 PCI_EXP_DEVCTL_NOSNOOP_EN, 9798 PCI_EXP_DEVCTL_CERE | PCI_EXP_DEVCTL_NFERE | 9799 PCI_EXP_DEVCTL_FERE | PCI_EXP_DEVCTL_URRE | 9800 PCI_EXP_DEVCTL_RELAX_EN); 9801 9802 dma_mask = DMA_BIT_MASK(44); 9803 err = pci_set_dma_mask(pdev, dma_mask); 9804 if (!err) { 9805 dev->features |= NETIF_F_HIGHDMA; 9806 err = pci_set_consistent_dma_mask(pdev, dma_mask); 9807 if (err) { 9808 dev_err(&pdev->dev, "Unable to obtain 44 bit DMA for consistent allocations, aborting\n"); 9809 goto err_out_release_parent; 9810 } 9811 } 9812 if (err) { 9813 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); 9814 if (err) { 9815 dev_err(&pdev->dev, "No usable DMA configuration, aborting\n"); 9816 goto err_out_release_parent; 9817 } 9818 } 9819 9820 niu_set_basic_features(dev); 9821 9822 dev->priv_flags |= IFF_UNICAST_FLT; 9823 9824 np->regs = pci_ioremap_bar(pdev, 0); 9825 if (!np->regs) { 9826 dev_err(&pdev->dev, "Cannot map device registers, aborting\n"); 9827 err = -ENOMEM; 9828 goto err_out_release_parent; 9829 } 9830 9831 pci_set_master(pdev); 9832 pci_save_state(pdev); 9833 9834 dev->irq = pdev->irq; 9835 9836 niu_assign_netdev_ops(dev); 9837 9838 err = niu_get_invariants(np); 9839 if (err) { 9840 if (err != -ENODEV) 9841 dev_err(&pdev->dev, "Problem fetching invariants of chip, aborting\n"); 9842 goto err_out_iounmap; 9843 } 9844 9845 err = register_netdev(dev); 9846 if (err) { 9847 dev_err(&pdev->dev, "Cannot register net device, aborting\n"); 9848 goto err_out_iounmap; 9849 } 9850 9851 pci_set_drvdata(pdev, dev); 9852 9853 niu_device_announce(np); 9854 9855 return 0; 9856 9857 err_out_iounmap: 9858 if (np->regs) { 9859 iounmap(np->regs); 9860 np->regs = NULL; 9861 } 9862 9863 err_out_release_parent: 9864 niu_put_parent(np); 9865 9866 err_out_free_dev: 9867 free_netdev(dev); 9868 9869 err_out_free_res: 9870 pci_release_regions(pdev); 9871 9872 err_out_disable_pdev: 9873 pci_disable_device(pdev); 9874 9875 return err; 9876 } 9877 9878 static void niu_pci_remove_one(struct pci_dev *pdev) 9879 { 9880 struct net_device *dev = pci_get_drvdata(pdev); 9881 9882 if (dev) { 9883 struct niu *np = netdev_priv(dev); 9884 9885 unregister_netdev(dev); 9886 if (np->regs) { 9887 iounmap(np->regs); 9888 np->regs = NULL; 9889 } 9890 9891 niu_ldg_free(np); 9892 9893 niu_put_parent(np); 9894 9895 free_netdev(dev); 9896 pci_release_regions(pdev); 9897 pci_disable_device(pdev); 9898 } 9899 } 9900 9901 static int niu_suspend(struct pci_dev *pdev, pm_message_t state) 9902 { 9903 struct net_device *dev = pci_get_drvdata(pdev); 9904 struct niu *np = netdev_priv(dev); 9905 unsigned long flags; 9906 9907 if (!netif_running(dev)) 9908 return 0; 9909 9910 flush_work(&np->reset_task); 9911 niu_netif_stop(np); 9912 9913 del_timer_sync(&np->timer); 9914 9915 spin_lock_irqsave(&np->lock, flags); 9916 niu_enable_interrupts(np, 0); 9917 spin_unlock_irqrestore(&np->lock, flags); 9918 9919 netif_device_detach(dev); 9920 9921 spin_lock_irqsave(&np->lock, flags); 9922 niu_stop_hw(np); 9923 spin_unlock_irqrestore(&np->lock, flags); 9924 9925 pci_save_state(pdev); 9926 9927 return 0; 9928 } 9929 9930 static int niu_resume(struct pci_dev *pdev) 9931 { 9932 struct net_device *dev = pci_get_drvdata(pdev); 9933 struct niu *np = netdev_priv(dev); 9934 unsigned long flags; 9935 int err; 9936 9937 if (!netif_running(dev)) 9938 return 0; 9939 9940 pci_restore_state(pdev); 9941 9942 netif_device_attach(dev); 9943 9944 spin_lock_irqsave(&np->lock, flags); 9945 9946 err = niu_init_hw(np); 9947 if (!err) { 9948 np->timer.expires = jiffies + HZ; 9949 add_timer(&np->timer); 9950 niu_netif_start(np); 9951 } 9952 9953 spin_unlock_irqrestore(&np->lock, flags); 9954 9955 return err; 9956 } 9957 9958 static struct pci_driver niu_pci_driver = { 9959 .name = DRV_MODULE_NAME, 9960 .id_table = niu_pci_tbl, 9961 .probe = niu_pci_init_one, 9962 .remove = niu_pci_remove_one, 9963 .suspend = niu_suspend, 9964 .resume = niu_resume, 9965 }; 9966 9967 #ifdef CONFIG_SPARC64 9968 static void *niu_phys_alloc_coherent(struct device *dev, size_t size, 9969 u64 *dma_addr, gfp_t flag) 9970 { 9971 unsigned long order = get_order(size); 9972 unsigned long page = __get_free_pages(flag, order); 9973 9974 if (page == 0UL) 9975 return NULL; 9976 memset((char *)page, 0, PAGE_SIZE << order); 9977 *dma_addr = __pa(page); 9978 9979 return (void *) page; 9980 } 9981 9982 static void niu_phys_free_coherent(struct device *dev, size_t size, 9983 void *cpu_addr, u64 handle) 9984 { 9985 unsigned long order = get_order(size); 9986 9987 free_pages((unsigned long) cpu_addr, order); 9988 } 9989 9990 static u64 niu_phys_map_page(struct device *dev, struct page *page, 9991 unsigned long offset, size_t size, 9992 enum dma_data_direction direction) 9993 { 9994 return page_to_phys(page) + offset; 9995 } 9996 9997 static void niu_phys_unmap_page(struct device *dev, u64 dma_address, 9998 size_t size, enum dma_data_direction direction) 9999 { 10000 /* Nothing to do. */ 10001 } 10002 10003 static u64 niu_phys_map_single(struct device *dev, void *cpu_addr, 10004 size_t size, 10005 enum dma_data_direction direction) 10006 { 10007 return __pa(cpu_addr); 10008 } 10009 10010 static void niu_phys_unmap_single(struct device *dev, u64 dma_address, 10011 size_t size, 10012 enum dma_data_direction direction) 10013 { 10014 /* Nothing to do. */ 10015 } 10016 10017 static const struct niu_ops niu_phys_ops = { 10018 .alloc_coherent = niu_phys_alloc_coherent, 10019 .free_coherent = niu_phys_free_coherent, 10020 .map_page = niu_phys_map_page, 10021 .unmap_page = niu_phys_unmap_page, 10022 .map_single = niu_phys_map_single, 10023 .unmap_single = niu_phys_unmap_single, 10024 }; 10025 10026 static int niu_of_probe(struct platform_device *op) 10027 { 10028 union niu_parent_id parent_id; 10029 struct net_device *dev; 10030 struct niu *np; 10031 const u32 *reg; 10032 int err; 10033 10034 niu_driver_version(); 10035 10036 reg = of_get_property(op->dev.of_node, "reg", NULL); 10037 if (!reg) { 10038 dev_err(&op->dev, "%s: No 'reg' property, aborting\n", 10039 op->dev.of_node->full_name); 10040 return -ENODEV; 10041 } 10042 10043 dev = niu_alloc_and_init(&op->dev, NULL, op, 10044 &niu_phys_ops, reg[0] & 0x1); 10045 if (!dev) { 10046 err = -ENOMEM; 10047 goto err_out; 10048 } 10049 np = netdev_priv(dev); 10050 10051 memset(&parent_id, 0, sizeof(parent_id)); 10052 parent_id.of = of_get_parent(op->dev.of_node); 10053 10054 np->parent = niu_get_parent(np, &parent_id, 10055 PLAT_TYPE_NIU); 10056 if (!np->parent) { 10057 err = -ENOMEM; 10058 goto err_out_free_dev; 10059 } 10060 10061 niu_set_basic_features(dev); 10062 10063 np->regs = of_ioremap(&op->resource[1], 0, 10064 resource_size(&op->resource[1]), 10065 "niu regs"); 10066 if (!np->regs) { 10067 dev_err(&op->dev, "Cannot map device registers, aborting\n"); 10068 err = -ENOMEM; 10069 goto err_out_release_parent; 10070 } 10071 10072 np->vir_regs_1 = of_ioremap(&op->resource[2], 0, 10073 resource_size(&op->resource[2]), 10074 "niu vregs-1"); 10075 if (!np->vir_regs_1) { 10076 dev_err(&op->dev, "Cannot map device vir registers 1, aborting\n"); 10077 err = -ENOMEM; 10078 goto err_out_iounmap; 10079 } 10080 10081 np->vir_regs_2 = of_ioremap(&op->resource[3], 0, 10082 resource_size(&op->resource[3]), 10083 "niu vregs-2"); 10084 if (!np->vir_regs_2) { 10085 dev_err(&op->dev, "Cannot map device vir registers 2, aborting\n"); 10086 err = -ENOMEM; 10087 goto err_out_iounmap; 10088 } 10089 10090 niu_assign_netdev_ops(dev); 10091 10092 err = niu_get_invariants(np); 10093 if (err) { 10094 if (err != -ENODEV) 10095 dev_err(&op->dev, "Problem fetching invariants of chip, aborting\n"); 10096 goto err_out_iounmap; 10097 } 10098 10099 err = register_netdev(dev); 10100 if (err) { 10101 dev_err(&op->dev, "Cannot register net device, aborting\n"); 10102 goto err_out_iounmap; 10103 } 10104 10105 platform_set_drvdata(op, dev); 10106 10107 niu_device_announce(np); 10108 10109 return 0; 10110 10111 err_out_iounmap: 10112 if (np->vir_regs_1) { 10113 of_iounmap(&op->resource[2], np->vir_regs_1, 10114 resource_size(&op->resource[2])); 10115 np->vir_regs_1 = NULL; 10116 } 10117 10118 if (np->vir_regs_2) { 10119 of_iounmap(&op->resource[3], np->vir_regs_2, 10120 resource_size(&op->resource[3])); 10121 np->vir_regs_2 = NULL; 10122 } 10123 10124 if (np->regs) { 10125 of_iounmap(&op->resource[1], np->regs, 10126 resource_size(&op->resource[1])); 10127 np->regs = NULL; 10128 } 10129 10130 err_out_release_parent: 10131 niu_put_parent(np); 10132 10133 err_out_free_dev: 10134 free_netdev(dev); 10135 10136 err_out: 10137 return err; 10138 } 10139 10140 static int niu_of_remove(struct platform_device *op) 10141 { 10142 struct net_device *dev = platform_get_drvdata(op); 10143 10144 if (dev) { 10145 struct niu *np = netdev_priv(dev); 10146 10147 unregister_netdev(dev); 10148 10149 if (np->vir_regs_1) { 10150 of_iounmap(&op->resource[2], np->vir_regs_1, 10151 resource_size(&op->resource[2])); 10152 np->vir_regs_1 = NULL; 10153 } 10154 10155 if (np->vir_regs_2) { 10156 of_iounmap(&op->resource[3], np->vir_regs_2, 10157 resource_size(&op->resource[3])); 10158 np->vir_regs_2 = NULL; 10159 } 10160 10161 if (np->regs) { 10162 of_iounmap(&op->resource[1], np->regs, 10163 resource_size(&op->resource[1])); 10164 np->regs = NULL; 10165 } 10166 10167 niu_ldg_free(np); 10168 10169 niu_put_parent(np); 10170 10171 free_netdev(dev); 10172 } 10173 return 0; 10174 } 10175 10176 static const struct of_device_id niu_match[] = { 10177 { 10178 .name = "network", 10179 .compatible = "SUNW,niusl", 10180 }, 10181 {}, 10182 }; 10183 MODULE_DEVICE_TABLE(of, niu_match); 10184 10185 static struct platform_driver niu_of_driver = { 10186 .driver = { 10187 .name = "niu", 10188 .owner = THIS_MODULE, 10189 .of_match_table = niu_match, 10190 }, 10191 .probe = niu_of_probe, 10192 .remove = niu_of_remove, 10193 }; 10194 10195 #endif /* CONFIG_SPARC64 */ 10196 10197 static int __init niu_init(void) 10198 { 10199 int err = 0; 10200 10201 BUILD_BUG_ON(PAGE_SIZE < 4 * 1024); 10202 10203 niu_debug = netif_msg_init(debug, NIU_MSG_DEFAULT); 10204 10205 #ifdef CONFIG_SPARC64 10206 err = platform_driver_register(&niu_of_driver); 10207 #endif 10208 10209 if (!err) { 10210 err = pci_register_driver(&niu_pci_driver); 10211 #ifdef CONFIG_SPARC64 10212 if (err) 10213 platform_driver_unregister(&niu_of_driver); 10214 #endif 10215 } 10216 10217 return err; 10218 } 10219 10220 static void __exit niu_exit(void) 10221 { 10222 pci_unregister_driver(&niu_pci_driver); 10223 #ifdef CONFIG_SPARC64 10224 platform_driver_unregister(&niu_of_driver); 10225 #endif 10226 } 10227 10228 module_init(niu_init); 10229 module_exit(niu_exit); 10230